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/*
* Titor - Interface-replaced BRAM
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_BRAMMemory
`else
`define INC_BRAMMemory
`timescale 1 ns / 100 ps
// Memory module
// Holds 1K WORD of memory
module Memory(
dout,
din,
address,
size,
read_write,
enable,
clk,
reset
);
`include "definition/Definition.v"
parameter MFILE = BLANKFILE;
output [WORD-1:0] dout;
input [WORD-1:0] din;
input [WORD-1:0] address;
input [LOGWORDBYTE-1:0] size;
input read_write;
input enable;
input clk;
input reset;
wire [WORD-1:0] dout0;
wire [WORD-1:0] dout1;
wire[WORD-1:0] xaddress;
assign xaddress = address;
assign dout = xaddress[9]==0 ? dout0 : dout1;
RAMB16_S36 #(
.INIT(36'h000000000),
.SRVAL(36'h000000000),
.WRITE_MODE("READ_FIRST")
) RAMB16_S36_inst0 (
.DO(dout0), // 32-bit Data Output
.DOP(), // 4-bit parity Output
.ADDR(xaddress[8:0]), // 9-bit Address Input
.CLK(clk), // Clock
.DI(din), // 32-bit Data Input
.DIP(4'b0000), // 4-bit parity Input
.EN(enable && (xaddress[9]==0)), // RAM Enable Input
.SSR(0), // Synchronous Set/Reset Input
.WE((read_write == WRITE) && (xaddress[9]==0)) // Write Enable Input
);
RAMB16_S36 #(
.INIT(36'h000000000),
.SRVAL(36'h000000000),
.WRITE_MODE("READ_FIRST")
) RAMB16_S36_inst1 (
.DO(dout1), // 32-bit Data Output
.DOP(), // 4-bit parity Output
.ADDR(xaddress[8:0]), // 9-bit Address Input
.CLK(clk), // Clock
.DI(din), // 32-bit Data Input
.DIP(4'b0000), // 4-bit parity Input
.EN(enable && (xaddress[9]==1)), // RAM Enable Input
.SSR(0), // Synchronous Set/Reset Input
.WE((read_write == WRITE) && (xaddress[9]==1)) // Write Enable Input
);
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_1_V
`define SKY130_FD_SC_HS__SDFXBP_1_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfxbp_1 (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sdfxbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfxbp_1 (
CLK,
D ,
Q ,
Q_N,
SCD,
SCE
);
input CLK;
input D ;
output Q ;
output Q_N;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfxbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_1_V
|
// Library - static, Cell - th44w322a, View - schematic
// LAST TIME SAVED: May 23 18:02:25 2014
// NETLIST TIME: May 23 18:02:45 2014
`timescale 1ns / 1ns
module th44w322a ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w322a";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net037), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N14 ( .d(net32), .g(b), .s(net037), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net45), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net45), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(y), .s(net45), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net45), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net45), .b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(a), .s(net036), .d(net047));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net047), .d(net32));
pfet_b P10 ( .b(cds_globals.vdd_), .g(c), .s(net047), .d(net32));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net49));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module videosync(
input CLK_24MB,
input LSPC_3M,
input LSPC_1_5M,
input Q53_CO,
input RESETP,
input VMODE,
output [8:0] PIXELC,
output [8:0] RASTERC,
output SYNC,
output BNK,
output BNKB,
output CHBL,
output R15_QD,
output FLIP,
output nFLIP,
output P50_CO
);
wire [3:0] S122_REG;
wire [3:0] R15_REG;
wire [3:0] T116_REG;
assign R15_QD = R15_REG[3];
FDPCell H287(J22_OUT, H287_nQ, 1'b1, RESETP, H287_Q, H287_nQ);
assign nFLIP = ~H287_Q;
assign FLIP = ~H287_nQ;
// Pixel counter
// Used for test mode
assign P40A_OUT = P50_CO | 1'b0;
assign PIXELC = {P15_QC, P15_QB, P15_QA, P50_QD, P50_QC, P50_QB, P50_QA, LSPC_1_5M, LSPC_3M};
C43 P50(CLK_24MB, 4'b1110, RESETP, Q53_CO, 1'b1, 1'b1, {P50_QD, P50_QC, P50_QB, P50_QA}, P50_CO);
C43 P15(CLK_24MB, {3'b101, ~RESETP}, P13B_OUT, Q53_CO, P40A_OUT, 1'b1, {P15_QD, P15_QC, P15_QB, P15_QA}, P15_CO);
assign P39B_OUT = P15_CO & Q53_CO;
assign P13B_OUT = ~|{P39B_OUT, ~RESETP};
// Raster counter
// Used for test mode
assign J22_OUT = P15_QC ^ 1'b0;
assign H284A_OUT = I269_CO | 1'b0;
C43 I269(J22_OUT, {~VMODE, 3'b100}, ~J268_CO, FLIP, FLIP, RESETP, RASTERC[4:1], I269_CO);
C43 J268(J22_OUT, {3'b011, ~VMODE}, ~J268_CO, H284A_OUT, H284A_OUT, RESETP, RASTERC[8:5], J268_CO);
assign RASTERC[0] = FLIP;
// H277B H269B H275A
assign MATCH_PAL = ~&{RASTERC[4:3]} | RASTERC[5] | RASTERC[8];
FDM H272(RASTERC[2], MATCH_PAL, H272_Q, );
FDM I238(FLIP, H272_Q, BLANK_PAL, );
// J259A
assign MATCH_NTSC = ~&{RASTERC[7:5]};
// J251
FD4 J251(~RASTERC[4], MATCH_NTSC, 1'b1, RESETP, BLANK_NTSC, );
// J240A: T2E
assign VSYNC = VMODE ? BLANK_PAL : RASTERC[8];
assign BNK = ~(VMODE ? RASTERC[8] : BLANK_NTSC);
// K15B
assign BNKB = ~BNK;
assign #1 S136A_OUT = ~LSPC_1_5M;
// P13A
assign #1 nPIXEL_H256 = ~P15_QC;
assign P13A_OUT = P15_QA & nPIXEL_H256;
FS1 R15(S136A_OUT, P13A_OUT, R15_REG);
BD3 S51(R15_REG[3], S51_OUT);
FS1 T116(S136A_OUT, ~S51_OUT, T116_REG);
BD3 U127(T116_REG[3], U127_OUT);
FS1 S122(S136A_OUT, ~U127_OUT, S122_REG);
BD3 S119A(S122_REG[3], S119_OUT);
FD2 S116(S136A_OUT, S119_OUT, S116_Q, );
// S131A
assign HSYNC = ~&{S116_Q, ~T116_REG[1]};
// M149
assign SYNC = ~^{HSYNC, VSYNC};
// L40A
assign CHBL = ~&{BNKB, R15_REG[3]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_1_V
`define SKY130_FD_SC_LS__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_adc_common (
// clock reset
mmcm_rst,
// adc interface
adc_clk,
adc_rst,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode,
adc_status,
adc_sync_status,
adc_status_ovf,
adc_status_unf,
adc_clk_ratio,
adc_start_code,
adc_sync,
// channel interface
up_status_pn_err,
up_status_pn_oos,
up_status_or,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// user channel control
up_usr_chanmax,
adc_usr_chanmax,
up_adc_gpio_in,
up_adc_gpio_out,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00090062;
parameter PCORE_ID = 0;
// clock reset
output mmcm_rst;
// adc interface
input adc_clk;
output adc_rst;
output adc_r1_mode;
output adc_ddr_edgesel;
output adc_pin_mode;
input adc_status;
input adc_sync_status;
input adc_status_ovf;
input adc_status_unf;
input [31:0] adc_clk_ratio;
output [31:0] adc_start_code;
output adc_sync;
// channel interface
input up_status_pn_err;
input up_status_pn_oos;
input up_status_or;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// user channel control
output [ 7:0] up_usr_chanmax;
input [ 7:0] adc_usr_chanmax;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
reg [31:0] up_adc_gpio_out = 'd0;
reg [31:0] up_adc_start_code = 'd0;
reg up_adc_sync = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_mmcm_preset_s;
wire up_status_s;
wire up_sync_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire up_cntrl_xfer_done;
wire [31:0] up_adc_clk_count_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
assign up_mmcm_preset_s = ~up_mmcm_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
up_adc_gpio_out <= 'd0;
up_adc_start_code <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if (up_adc_sync == 1'b1) begin
if (up_cntrl_xfer_done == 1'b1) begin
up_adc_sync <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sync <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_r1_mode <= up_wdata[2];
up_adc_ddr_edgesel <= up_wdata[1];
up_adc_pin_mode <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
end else begin
up_drp_sel <= 1'b0;
up_drp_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata;
end
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[2];
end
if (up_status_unf_s == 1'b1) begin
up_status_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_unf <= up_status_unf & ~up_wdata[1];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_adc_start_code <= up_wdata[31:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_adc_gpio_out <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
8'h15: up_rdata <= up_adc_clk_count_s;
8'h16: up_rdata <= adc_clk_ratio;
8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h1a: up_rdata <= {31'd0, up_sync_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h23: up_rdata <= 32'd8;
8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
8'h29: up_rdata <= up_adc_start_code;
8'h2e: up_rdata <= up_adc_gpio_in;
8'h2f: up_rdata <= up_adc_gpio_out;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst));
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(36)) i_adc_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_sync,
up_adc_start_code,
up_adc_r1_mode,
up_adc_ddr_edgesel,
up_adc_pin_mode}),
.up_xfer_done (up_cntrl_xfer_done),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_sync,
adc_start_code,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(4)) i_adc_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_sync_status_s,
up_status_s,
up_status_ovf_s,
up_status_unf_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_sync_status,
adc_status,
adc_status_ovf,
adc_status_unf}));
// adc clock monitor
up_clock_mon i_adc_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_adc_clk_count_s),
.d_rst (adc_rst),
.d_clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
`define STATE_RESET 0
`define STATE_POWERON_INIT_0 1
`define STATE_POWERON_INIT_1 2
`define STATE_POWERON_INIT_2 3
`define STATE_POWERON_INIT_3 4
`define STATE_POWERON_INIT_4 5
`define STATE_POWERON_INIT_5 6
`define STATE_POWERON_INIT_6 7
`define STATE_POWERON_INIT_7 8
`define STATE_POWERON_INIT_8 9
`define STATE_DISPLAY_CONFIG_0 10
`define STATE_DISPLAY_CONFIG_1 11
`define STATE_DISPLAY_CONFIG_2 12
`define STATE_DISPLAY_CONFIG_3 13
`define STATE_DISPLAY_CONFIG_4 14
`define STATE_DISPLAY_CONFIG_5 15
`define STATE_DISPLAY_CONFIG_6 16
`define STATE_DISPLAY_CONFIG_7 17
`define STATE_DISPLAY_CONFIG_8 18
`define STATE_DISPLAY_CONFIG_9 19
`define STATE_DISPLAY_CONFIG_10 20
`define STATE_DISPLAY_CONFIG_11 21
`define STATE_DISPLAY_CONFIG_12 22
`define STATE_DISPLAY_CONFIG_13 23
`define STATE_DISPLAY_CONFIG_14 24
`define STATE_DISPLAY_CONFIG_15 25
//`define STATE_DISPLAY_IDLE 26
`define STATE_DISPLAY_WRITE_0 27
`define STATE_DISPLAY_WRITE_1 28
`define STATE_DISPLAY_WRITE_2 29
`define STATE_DISPLAY_WRITE_3 30
`define STATE_DISPLAY_WRITE_4 31
`define STATE_DISPLAY_WRITE_5 32
`define STATE_DISPLAY_WRITE_6 33
`define STATE_DISPLAY_WRITE_7 34
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=16)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
always @(posedge Clock )
begin
if (Reset)
Q = Initial;
else
begin
if (Enable)
Q = Q + 1;
end
end
endmodule
//----------------------------------------------------
module mux (in0,in1,in2,in3, sel, out);
input wire [7:0] in0,in1,in2,in3;
input wire [1:0] sel;
output reg [7:0] out;
always @ (*)
begin
case (sel)
0: out<=in0;
1: out<=in1;
2: out<=in2;
3: out<=in3;
default: out<=0;
endcase
end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=8 )
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @ (posedge Clock)
begin
if ( Reset )
Q <= 0;
else
begin
if (Enable)
Q <= D;
end
end//always
endmodule
//----------------------------------------------------------------------
module FULL_ADDER # (parameter SIZE=4)
(
input wire[SIZE-1:0] wA,
input wire[SIZE-1:0] wB,
input wire wCi,
output wire [SIZE-1:0] wR ,
output wire wCo
);
assign {wCo,wR} = wA + wB + wCi;
endmodule
//----------------------------------------------------------------------
module arrayMUL
(
input wire [3:0] A,
input wire [3:0] B,
output reg [7:0] out
);
reg rC1, rC2, rC3; //registros para los llevos
reg [2:0] rT1, rT2; //registros temporales
always @ (*) begin
//R0
out[0] =A[0] & B[0];
//R1
{rC1, out[1]} = (A[0] & B[1]) + (A[1] & B[0]);
//R2
{rC1, rT1[0]} = (A[2] & B[0]) + (A[1] & B[1]) + rC1;
{rC2, out[2]} = (A[0] & B[2]) + rT1[0];
//R3
{rC1, rT1[1]} = (A[3] & B[0]) + (A[2] & B[1]) + rC1;
{rC2, rT2[0]} = (A[1] & B[2]) + rT1[1] + rC2;
{rC3, out[3]} = (A[0] & B[3]) + rT2[0];
//R4
{rC1, rT1[2]} = (A[3] & B[1]) + rC1;
{rC2, rT2[1]} = (A[2] & B[2]) + rT1[2] + rC2;
{rC3, out[4]} = (A[1] & B[3]) + rT2[1] + rC3;
//R5
{rC2, rT2[2]} = (A[3] & B[2]) + rC2 + rC1;
{rC3, out[5]} = (A[2] & B[3]) + rT2[2] + rC3;
//R6 y R7.
{out[7], out[6]} = (A[3] & B[3]) + rC2 + rC3;
end
endmodule
//----------------------------------------------------------------------
module muxMUL (ia,ib,o);
input wire [3:0] ib,ia;
output [7:0] o;
wire [7:0] iaR,iaRA;
wire [7:0] o0,o1;
wire [7:0] o1R ;
assign iaR=ia<<1; // A desplazado0 una posicion a la izquierda
assign iaRA=iaR+ia; // A desplazado una posicion a la izquierda mas A
mux mux0 (.in0(8'b0),.in1({4'b0,ia}),.in2(iaR),.in3(iaRA),.sel({ib[1],ib[0]}),.out(o0));
mux mux1 (.in0(8'b0),.in1({4'b0,ia}),.in2(iaR),.in3(iaRA),.sel({ib[3],ib[2]}),.out(o1));
assign o1R=o1<<2; // Salida desplazada 2 posiciones a la izquierda
assign o = o0+o1R;
endmodule
//----------------------------------------------------------------------
module arrayMUL_GEN # (parameter SIZE = 16)(
input wire [SIZE-1:0] A,B,
output wire [(2*SIZE)-1:0] R
);
wire [(SIZE-2):0] wCarry[SIZE:0];
wire [(SIZE-2):0] wResult[(SIZE-1):0];
wire [(SIZE-2):0] wInput1[(SIZE-1):0];
wire [(SIZE-2):0] wInput2[(SIZE-1):0];
assign wInput2[SIZE-1][0]= 1'b0;
genvar CurrentRow, CurrentCol;
generate
for ( CurrentCol = 0; CurrentCol < (SIZE-1); CurrentCol = CurrentCol + 1)
begin : MUL_COL
for ( CurrentRow =0; CurrentRow < (SIZE-2); CurrentRow = CurrentRow + 1)
begin : MUL_ROW
assign wInput1[CurrentCol][CurrentRow]= A[CurrentCol] & B[CurrentRow+1];
if(CurrentCol==0)
begin
assign wCarry[0][CurrentRow]=1'b0;
end
if(CurrentRow==0 && CurrentCol!=SIZE-1)
begin
assign wInput2[CurrentCol][0]= A[CurrentCol+1] & B[CurrentRow];
end
else if(CurrentCol==(SIZE-1))
begin
assign wInput2[CurrentCol][CurrentRow]=wCarry[CurrentCol +1][CurrentRow-1];
end
else
begin
assign wInput2[CurrentCol][CurrentRow]= wResult[CurrentCol+1][CurrentRow-1];
end
FULL_ADDER # (1) add
(
.wA(wInput1 [CurrentCol][CurrentRow]),
.wB(wInput2[CurrentCol][CurrentRow]),
.wCi(wCarry[CurrentCol][CurrentRow]),
.wCo(wCarry[CurrentCol +1 ][CurrentRow]),
.wR (wResult[CurrentCol][CurrentRow])
);
end
end
endgenerate
wire wR0 = A[0] & B [0];
assign R = {wResult[0], wR0};
endmodule
/*
module arrayMUL_GEN # (parameter SIZE = 4)(
input wire [SIZE-1:0] A,B,
output wire [(2*SIZE)-1:0] R
);
wire[(SIZE-1):0] wCarry[(SIZE-1):0];
//wire[(SIZE-1):0] iResult[(SIZE-1):0];
wire iResult[(SIZE-1):0];
assign R[0] = A[0] & B[0] ;
//genvar CurrentRow, CurrentCol;
genvar i,j;
wire[SIZE-1:0] twCi; //temporal para wCi
assign twCi[0] = 1'b0;
generate
for (i = 0; i <= 0; i = i + 1 )
begin
for(j = 0; j < (SIZE-1); j = j +1 )
begin
if (j != 0)
assign twCi[j] = wCarry[j-1][i];
FULL_ADDER # (1) add
(
.wA(A[j+1]&B[i]),
.wB(A[j]&B[i+1]),
.wCo(wCarry[j+1][i]),
.wR(iResult[j+1]),
.wCi(twCi[j])
);
end //for j
end //for i
endgenerate
//assign R = {wCarry[2][3],iResult[2][3],iResult[2][2],iResult[2][1],
// iResult[2][0],iResult[1][0],iResult[0][0], A[0]&B[0]};
endmodule
*/
//----------------------------------------------------------------------
module multiplicador4bits(
input wire [3:0] iMultiplicador,
input wire [7:0] iMultiplicando,
output reg [7:0] oResult );
always @(*)
case(iMultiplicador)
0:oResult=0;
1:oResult=iMultiplicando;
2:oResult=iMultiplicando<<1;
3:oResult=(iMultiplicando<<1) +iMultiplicando;
4:oResult=(iMultiplicando<<2);
5:oResult=(iMultiplicando<<2)+iMultiplicando;
6:oResult=(iMultiplicando<<2)+(iMultiplicando<<1);
7:oResult=(iMultiplicando<<2)+(iMultiplicando<<1)+iMultiplicando;
8:oResult=iMultiplicando<<3;
9:oResult=(iMultiplicando<<3)+iMultiplicando;
10:oResult=(iMultiplicando<<3)+(iMultiplicando<<1);
11:oResult=(iMultiplicando<<3)+(iMultiplicando<<1)+iMultiplicando;
12:oResult=(iMultiplicando<<3)+(iMultiplicando<<2);
13:oResult=(iMultiplicando<<3)+(iMultiplicando<<2)+ iMultiplicando;
14:oResult=(iMultiplicando<<3)+(iMultiplicando<<2)+ (iMultiplicando<<1);
15:oResult=(iMultiplicando<<3)+(iMultiplicando<<2)+ (iMultiplicando<<1) + iMultiplicando;
endcase
endmodule
module VGA_Controller_Josue (Clock25, Reset, iRGB, H_Sync, V_Sync, oRGB, Cont_X, Cont_Y);
input wire Clock25, Reset;
input wire [2:0] iRGB;// iColorCuadro;
output wire H_Sync, V_Sync;
output wire [2:0] oRGB;
output wire [9:0] Cont_X, Cont_Y;
localparam RGB_MARCO = 3'b0;
localparam MARCO_X = 48;
localparam MARCO_Y = 32;
localparam MARCO = 3'b0;
localparam RESOL_X = 256;
localparam RESOL_Y = 256;
localparam NUM_CUADROS_X = 16;
localparam NUM_CUADROS_Y = 16;
wire iR, iG, iB;
wire oR, oG, oB;
wire [2:0] wMarco; //, wCuadro;
wire [2:0] wColorSelectionVGA;
assign wColorSelectionVGA = /*(((Cont_X >= MARCO_X) && (Cont_X <= MARCO_X)) &&
((Cont_Y >= MARCO_Y) && (Cont_Y <= + MARCO_Y))) ?
iColorCuadro : */{iR, iG, iB};
///assign wColorSelectionVGA = {iR, iG, iB};
assign iR = iRGB[2];
assign iG = iRGB[1];
assign iB = iRGB[0];
assign oRGB = {oR, oG, oB};
assign H_Sync = (Cont_X < 704) ? 1'b1 : 1'b0;
assign V_Sync = (Cont_Y < 519) ? 1'b1 : 1'b0;
//Marco negro con Imagen de 640*480
assign {oR, oG, oB} = (Cont_Y < MARCO_Y || Cont_Y >= RESOL_Y+MARCO_Y ||
Cont_X < MARCO_X || Cont_X > RESOL_X+MARCO_X) ?
MARCO : wColorSelectionVGA;
UPCOUNTER_POSEDGE # (10) HORIZONTAL_COUNTER
(
.Clock ( Clock25 ),
.Reset ( (Cont_X > 799) || Reset ),
.Initial ( 10'b0 ),
.Enable ( 1'b1 ),
.Q ( Cont_X )
);
UPCOUNTER_POSEDGE # (10) VERTICAL_COUNTER
(
.Clock ( Clock25 ),
.Reset ( (Cont_Y > 520) || Reset ),
.Initial ( 10'b0 ),
.Enable ( (Cont_X == 799) ? 1'b1:1'b0 ),
.Q ( Cont_Y )
);
endmodule
module VGA_controller
(
input wire pixel_Clock, // 50 MHz
input wire pixel_reset,
input wire pre_reset,
output reg oVGA_HSYNC,
output reg oVGA_VSYNC,
output wire[2:0] oVGA_RGB
);
wire[9:0] wHorizontal_counter;
wire[9:0] wVertical_counter;
assign oVGA_RGB = {1'b1, 1'b0, 1'b0 };
reg fila_final, columna_final;
//contadores de filas y columnas
UPCOUNTER_POSEDGE # ( 10 ) contador_columnas (
.Clock( pixel_Clock ),
.Reset( pixel_reset | columna_final ), //
.Initial( 10'b0 ),
.Enable( 1'b1 ),
.Q( wHorizontal_counter)
);
UPCOUNTER_POSEDGE # ( 10 ) contador_filas (
.Clock( pixel_Clock ),
.Reset( pixel_reset | fila_final ),
.Initial( 10'b0 ),
.Enable( columna_final ),
.Q( wVertical_counter)
);
always @ (posedge pixel_Clock)
if(pixel_reset)
begin
columna_final <= 1'b0;
fila_final <= 1'b0;
oVGA_VSYNC = 1'b1;
oVGA_HSYNC = 1'b1;
end
else
begin
//columnas
if(wHorizontal_counter == 10'd481) //ultima columna 640+160 10'd799
begin
columna_final <= 1'b1;
oVGA_HSYNC = 1'b1;
end
else if (wHorizontal_counter > 10'd16 && wHorizontal_counter < 10'd112 ) //655 & 751
begin
columna_final <= 1'b0;
oVGA_HSYNC = 1'b0;
end
else
begin
columna_final <= 1'b0;
oVGA_HSYNC = 1'b1;
end
//filas
if(wVertical_counter == 10'd282) //521
begin
fila_final <= 1'b1;
oVGA_VSYNC = 1'b1;
end
else if (wVertical_counter > 10'd10 && wVertical_counter < 10'd12 ) //490 & 492
begin
fila_final <= 1'b0;
oVGA_VSYNC = 1'b0;
end
else
begin
fila_final <= 1'b0;
oVGA_VSYNC = 1'b1;
end
end
endmodule
module shl
(
input wire Clock,
input wire [7:0] iRegistro,
input wire [3:0] iBits_a_correr,
output reg [7:0] oRegistro_corrido
);
always @(posedge Clock)
case(iBits_a_correr)
0: oRegistro_corrido <= iRegistro;
1: oRegistro_corrido <= iRegistro << 1;
2: oRegistro_corrido <= iRegistro << 2;
3: oRegistro_corrido <= iRegistro << 3;
4: oRegistro_corrido <= iRegistro << 4;
5: oRegistro_corrido <= iRegistro << 5;
6: oRegistro_corrido <= iRegistro << 6;
7: oRegistro_corrido <= iRegistro << 7;
endcase
endmodule
/////////////////////////////////////////
module VGA_controller_A7
(
input wire Clock_lento,
input wire Reset,
input wire [2:0] iVGA_RGB,
// input wire [2:0] iColorCuadro,
// input wire [7:0] iXRedCounter,
// input wire [7:0] iYRedCounter,
output wire [2:0] oVGA_RGB,
output wire oHsync,
output wire oVsync,
output wire [9:0] oVcounter,
output wire [9:0] oHcounter
);
wire iVGA_R, iVGA_G, iVGA_B;
wire oVGA_R, oVGA_G, oVGA_B;
wire wEndline;
wire [3:0] wMarco; //, wCuadro;
//wire [2:0] wVGAOutputSelection;
assign wMarco = 3'b0;
//assign wCuadro = 3'b100;
//assign wVGAOutputSelection = ( ((oHcounter >= iXRedCounter + 10'd240) && (oHcounter <= iXRedCounter + 10'd240 + 10'd32)) &&
// ((oVcounter >= iYRedCounter + 10'd141) && (oVcounter <= iYRedCounter + 10'd141 + 8'd32))) ?
// iColorCuadro : {iVGA_R, iVGA_G, iVGA_B};
assign iVGA_R = iVGA_RGB[2];
assign iVGA_G = iVGA_RGB[1];
assign iVGA_B = iVGA_RGB[0];
assign oVGA_RGB = {oVGA_R, oVGA_G, oVGA_B};
assign oHsync = (oHcounter < 704) ? 1'b1 : 1'b0;
assign wEndline = (oHcounter == 799);
assign oVsync = (oVcounter < 519) ? 1'b1 : 1'b0;
// Marco negro e imagen de 256*256
//assign {oVGA_R, oVGA_G, oVGA_B} = (oVcounter < 141 || oVcounter >= 397 ||
// oHcounter < 240 || oHcounter > 496) ?
// wMarco : wVGAOutputSelection;
assign {oVGA_R, oVGA_G, oVGA_B} = 3'b101;
UPCOUNTER_POSEDGE # (10) HORIZONTAL_COUNTER
(
.Clock ( Clock_lento ),
.Reset ( (oHcounter > 799) || Reset ),
.Initial ( 10'b0 ),
.Enable ( 1'b1 ),
.Q ( oHcounter )
);
UPCOUNTER_POSEDGE # (10) VERTICAL_COUNTER
(
.Clock ( Clock_lento ),
.Reset ( (oVcounter > 520) || Reset ),
.Initial ( 10'b0 ),
.Enable ( wEndline ),
.Q ( oVcounter )
);
endmodule
|
`include "common.vh"
`timescale 1ms/10us
module Tenyr(
input clk, reset, inout halt,
output[7:0] seg, output[3:0] an, inout[23:0] gpio,
output[2:0] vgaRed, vgaGreen, output[2:1] vgaBlue, output hsync, vsync, inframe
);
parameter RAMABITS = 13;
wire d_wen, d_stb, d_cyc, d_ack;
wire i_wen, i_stb, i_cyc, i_ack;
wire[3:0] d_sel, i_sel;
wire valid_clk, clk_vga, clk_core;
wire[31:0] i_adr;
wire[31:0] d_adr, d_to_slav, i_to_slav;
wire[31:0] d_to_mast, i_to_mast;
assign i_ack = i_stb;
tenyr_mainclock clocks(
.clk_in ( clk ), .clk_core ( clk_core ),
.reset ( reset ), .clk_vga ( clk_vga ),
.locked ( )
);
Core core(
.clk ( clk_core ),
.halt ( halt ),
.reset ( reset ),
.adr_o ( d_adr ),
.dat_o ( d_to_slav ),
.dat_i ( d_to_mast ),
.wen_o ( d_wen ),
.sel_o ( d_sel ),
.stb_o ( d_stb ),
.ack_i ( d_ack ),
.err_i ( 1'b0 ),
.rty_i ( 1'b0 ),
.cyc_o ( d_cyc )
);
// -----------------------------------------------------------------------------
// MEMORY ----------------------------------------------------------------------
wire r_wen, r_stb, r_cyc, r_ack;
wire[3:0] r_sel;
wire[31:0] r_adr, r_ddn, r_dup;
TwoPortRAM #(
.INIT(0),
.PBITS(32), .ABITS(RAMABITS), .OFFSET(`RESETVECTOR)
) ram(
.clka ( clk_core ), .clkb ( '0 ),
.ena ( r_stb ), .enb ( '0 ),
.acka ( r_ack ), .ackb ( ),
.wea ( r_wen ), .web ( '0 ),
.addra ( r_adr ), .addrb ( '0 ),
.dina ( r_ddn ), .dinb ( '0 ),
.douta ( r_dup ), .doutb ( )
);
// -----------------------------------------------------------------------------
// DEVICES ---------------------------------------------------------------------
wire s_wen, s_stb, s_cyc;
wire[3:0] s_sel;
wire[31:0] s_adr, s_ddn, s_dup;
wire s_stbcyc = s_stb & s_cyc;
`ifdef SERIAL
// TODO write a hardware-compatible serial device ; rename to eliminate `Sim`
SimWrap_simserial #(.BASE(32'h20), .SIZE(2)) serial(
.clk ( clk_core ), .reset ( reset ), .enable ( s_stbcyc ),
.rw ( s_wen ), .addr ( s_adr ), .data ( s_ddn )
);
`endif
wire g_wen, g_stb, g_cyc, g_ack;
wire[3:0] g_sel;
wire[31:0] g_adr, g_ddn, g_dup;
wire g_stbcyc = g_stb & g_cyc;
Seg7 seg7(
.clk ( clk_core ), .rw ( g_wen ), .seg ( seg ),
.reset ( reset ), .addr ( g_adr ), .an ( an ),
.strobe ( g_stbcyc ), .d_in ( g_ddn ), .d_out ( g_dup ), .ack( g_ack )
);
wire o_wen, o_stb, o_cyc;
wire[3:0] o_sel;
wire[31:0] o_adr, o_ddn, o_dup;
wire o_stbcyc = o_stb & o_cyc;
Gpio #(.COUNT(24)) gio(
.clk ( clk_core ), .rw ( o_wen ), .gpio ( gpio ),
.reset ( reset ), .addr ( o_adr ), .data_i ( o_ddn ),
.strobe ( o_stbcyc ), .data_o ( o_dup )
);
wire v_wen, v_stb, v_cyc;
wire[3:0] v_sel;
wire[31:0] v_adr, v_ddn, v_dup;
wire v_stbcyc = v_stb & v_cyc;
`ifdef VGA
VGAwrap vga(
.clk_core ( clk_core ), .rw ( v_wen ), .vgaRed ( vgaRed ),
.clk_vga ( clk_vga ), .addr ( v_adr ), .vgaGreen ( vgaGreen ),
.en ( 1'b1 ), .d_in ( v_ddn ), .vgaBlue ( vgaBlue ),
.reset ( reset ), .d_out ( v_dup ), .hsync ( hsync ),
.strobe ( v_stbcyc ), .vsync ( vsync ),
.inframe ( inframe )
);
`endif
wire x_wen, x_stb, x_cyc;
wire[3:0] x_sel;
wire[31:0] x_adr, x_ddn, x_dup;
assign x_dup = 32'hffffffff;
wb_mux #(
.num_slaves(6),
.MATCH_ADDR({
// GPIO 7-seg VGA display serial port memory default
32'h200,32'h100,`VIDEO_ADDR ,32'h00000020,`RESETVECTOR,-32'sd1 }),
.MATCH_MASK({
-32'd4 ,-32'd2 ,32'hffff0000,32'hfffffffe,32'hffffd000,-32'sd1 })
) mux (
.wb_clk_i ( clk_core ),
.wb_rst_i ( reset ),
.wbm_adr_i ( d_adr ),
.wbm_dat_i ( d_to_slav ),
.wbm_dat_o ( d_to_mast ),
.wbm_we_i ( d_wen ),
.wbm_sel_i ( d_sel ),
.wbm_stb_i ( d_stb ),
.wbm_ack_o ( d_ack ),
.wbm_err_o ( /* TODO */ ),
.wbm_rty_o ( /* TODO */ ),
.wbm_cyc_i ( d_cyc ),
// gpio 7-seg VGA serial mem def.
.wbs_adr_o ({ o_adr, g_adr, v_adr, s_adr, r_adr, x_adr }),
.wbs_dat_o ({ o_ddn, g_ddn, v_ddn, s_ddn, r_ddn, x_ddn }),
.wbs_dat_i ({ o_dup, g_dup, v_dup, s_dup, r_dup, x_dup }),
.wbs_we_o ({ o_wen, g_wen, v_wen, s_wen, r_wen, x_wen }),
.wbs_sel_o ({ o_sel, g_sel, v_sel, s_sel, r_sel, x_sel }),
.wbs_stb_o ({ o_stb, g_stb, v_stb, s_stb, r_stb, x_stb }),
.wbs_ack_i ({ o_stb, g_ack, v_stb, s_stb, r_ack, x_stb }),
.wbs_err_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_rty_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_cyc_o ({ o_cyc, g_cyc, v_cyc, s_cyc, r_cyc, x_cyc }),
// unused ports
.wbm_cti_i ( '0 ),
.wbm_bte_i ( '0 ),
.wbs_cti_o ( ),
.wbs_bte_o ( )
);
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
wire [width-1:0] dec_test_expr = test_expr - {{width-1{1'b0}},1'b1};
wire zoh_test_expr = ((test_expr & dec_test_expr) == {width{1'b0}});
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more or less than 1 asserted bits");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = !zoh_test_expr || (test_expr == {width{1'b0}});
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] one_hots_checked;
reg [width-1:0] prev_one_hots_checked;
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
prev_test_expr <= test_expr; // deliberately not reset
if (`OVL_RESET_SIGNAL == 1'b0) begin
one_hots_checked <= {width{1'b0}};
prev_one_hots_checked <= {width{1'b0}};
end
else begin
if (valid_test_expr && zoh_test_expr) begin
one_hots_checked <= one_hots_checked | test_expr;
end
prev_one_hots_checked <= one_hots_checked;
end
end
wire fire_cover_1, fire_cover_2;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("all_one_hots_checked covered"); // corner
end
if (fire_cover_1 || fire_cover_2) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (one_hots_checked == {width{1'b1}}) && (one_hots_checked != prev_one_hots_checked));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ssw_hp.v
*
* Date : 2012-11
*
* Description : SSW switch Model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_ssw_hp(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
rd_data_ocm_hp0,
wr_ack_ocm_hp0,
wr_dv_ocm_hp0,
rd_req_ocm_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
wr_ack_ocm_hp1,
wr_dv_ocm_hp1,
rd_req_ocm_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
wr_ack_ocm_hp2,
wr_dv_ocm_hp2,
rd_req_ocm_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ocm_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
wr_ack_ocm_hp3,
wr_dv_ocm_hp3,
rd_req_ocm_hp3,
rd_dv_ocm_hp3,
ddr_wr_ack0,
ddr_wr_dv0,
ddr_rd_req0,
ddr_rd_dv0,
ddr_rd_qos0,
ddr_wr_qos0,
ddr_wr_addr0,
ddr_wr_data0,
ddr_wr_bytes0,
ddr_rd_addr0,
ddr_rd_data0,
ddr_rd_bytes0,
ddr_wr_ack1,
ddr_wr_dv1,
ddr_rd_req1,
ddr_rd_dv1,
ddr_rd_qos1,
ddr_wr_qos1,
ddr_wr_addr1,
ddr_wr_data1,
ddr_wr_bytes1,
ddr_rd_addr1,
ddr_rd_data1,
ddr_rd_bytes1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ocm_wr_qos,
ocm_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes
);
input sw_clk;
input rstn;
input [3:0] w_qos_hp0;
input [3:0] r_qos_hp0;
input [3:0] w_qos_hp1;
input [3:0] r_qos_hp1;
input [3:0] w_qos_hp2;
input [3:0] r_qos_hp2;
input [3:0] w_qos_hp3;
input [3:0] r_qos_hp3;
output [3:0] ddr_rd_qos0;
output [3:0] ddr_wr_qos0;
output [3:0] ddr_rd_qos1;
output [3:0] ddr_wr_qos1;
output [3:0] ocm_wr_qos;
output [3:0] ocm_rd_qos;
output wr_ack_ddr_hp0;
input [1023:0] wr_data_hp0;
input [31:0] wr_addr_hp0;
input [7:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [31:0] rd_addr_hp0;
input [7:0] rd_bytes_hp0;
output [1023:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [1023:0] wr_data_hp1;
input [31:0] wr_addr_hp1;
input [7:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [31:0] rd_addr_hp1;
input [7:0] rd_bytes_hp1;
output [1023:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
output wr_ack_ddr_hp2;
input [1023:0] wr_data_hp2;
input [31:0] wr_addr_hp2;
input [7:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [31:0] rd_addr_hp2;
input [7:0] rd_bytes_hp2;
output [1023:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [1023:0] wr_data_hp3;
input [31:0] wr_addr_hp3;
input [7:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [31:0] rd_addr_hp3;
input [7:0] rd_bytes_hp3;
output [1023:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack0;
output ddr_wr_dv0;
output [31:0]ddr_wr_addr0;
output [1023:0]ddr_wr_data0;
output [7:0]ddr_wr_bytes0;
input ddr_rd_dv0;
input [1023:0] ddr_rd_data0;
output ddr_rd_req0;
output [31:0] ddr_rd_addr0;
output [7:0] ddr_rd_bytes0;
input ddr_wr_ack1;
output ddr_wr_dv1;
output [31:0]ddr_wr_addr1;
output [1023:0]ddr_wr_data1;
output [7:0]ddr_wr_bytes1;
input ddr_rd_dv1;
input [1023:0] ddr_rd_data1;
output ddr_rd_req1;
output [31:0] ddr_rd_addr1;
output [7:0] ddr_rd_bytes1;
output wr_ack_ocm_hp0;
input wr_dv_ocm_hp0;
input rd_req_ocm_hp0;
output rd_dv_ocm_hp0;
output [1023:0] rd_data_ocm_hp0;
output wr_ack_ocm_hp1;
input wr_dv_ocm_hp1;
input rd_req_ocm_hp1;
output rd_dv_ocm_hp1;
output [1023:0] rd_data_ocm_hp1;
output wr_ack_ocm_hp2;
input wr_dv_ocm_hp2;
input rd_req_ocm_hp2;
output rd_dv_ocm_hp2;
output [1023:0] rd_data_ocm_hp2;
output wr_ack_ocm_hp3;
input wr_dv_ocm_hp3;
input rd_req_ocm_hp3;
output rd_dv_ocm_hp3;
output [1023:0] rd_data_ocm_hp3;
input ocm_wr_ack;
output ocm_wr_dv;
output [31:0]ocm_wr_addr;
output [1023:0]ocm_wr_data;
output [7:0]ocm_wr_bytes;
input ocm_rd_dv;
input [1023:0] ocm_rd_data;
output ocm_rd_req;
output [31:0] ocm_rd_addr;
output [7:0] ocm_rd_bytes;
/* FOR DDR */
processing_system7_bfm_v2_0_arb_hp0_1 ddr_hp01 (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.ddr_wr_ack(ddr_wr_ack0),
.ddr_wr_dv(ddr_wr_dv0),
.ddr_rd_req(ddr_rd_req0),
.ddr_rd_dv(ddr_rd_dv0),
.ddr_rd_qos(ddr_rd_qos0),
.ddr_wr_qos(ddr_wr_qos0),
.ddr_wr_addr(ddr_wr_addr0),
.ddr_wr_data(ddr_wr_data0),
.ddr_wr_bytes(ddr_wr_bytes0),
.ddr_rd_addr(ddr_rd_addr0),
.ddr_rd_data(ddr_rd_data0),
.ddr_rd_bytes(ddr_rd_bytes0)
);
/* FOR DDR */
processing_system7_bfm_v2_0_arb_hp2_3 ddr_hp23 (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.ddr_wr_ack(ddr_wr_ack1),
.ddr_wr_dv(ddr_wr_dv1),
.ddr_rd_req(ddr_rd_req1),
.ddr_rd_dv(ddr_rd_dv1),
.ddr_rd_qos(ddr_rd_qos1),
.ddr_wr_qos(ddr_wr_qos1),
.ddr_wr_addr(ddr_wr_addr1),
.ddr_wr_data(ddr_wr_data1),
.ddr_wr_bytes(ddr_wr_bytes1),
.ddr_rd_addr(ddr_rd_addr1),
.ddr_rd_data(ddr_rd_data1),
.ddr_rd_bytes(ddr_rd_bytes1)
);
/* FOR OCM_WR */
processing_system7_bfm_v2_0_arb_wr_4 ocm_wr_hp(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.qos3(w_qos_hp2),
.qos4(w_qos_hp3),
.prt_dv1(wr_dv_ocm_hp0),
.prt_dv2(wr_dv_ocm_hp1),
.prt_dv3(wr_dv_ocm_hp2),
.prt_dv4(wr_dv_ocm_hp3),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_data3(wr_data_hp2),
.prt_data4(wr_data_hp3),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_addr3(wr_addr_hp2),
.prt_addr4(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_bytes3(wr_bytes_hp2),
.prt_bytes4(wr_bytes_hp3),
.prt_ack1(wr_ack_ocm_hp0),
.prt_ack2(wr_ack_ocm_hp1),
.prt_ack3(wr_ack_ocm_hp2),
.prt_ack4(wr_ack_ocm_hp3),
.prt_qos(ocm_wr_qos),
.prt_req(ocm_wr_dv),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
/* FOR OCM_RD */
processing_system7_bfm_v2_0_arb_rd_4 ocm_rd_hp(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.qos3(r_qos_hp2),
.qos4(r_qos_hp3),
.prt_req1(rd_req_ocm_hp0),
.prt_req2(rd_req_ocm_hp1),
.prt_req3(rd_req_ocm_hp2),
.prt_req4(rd_req_ocm_hp3),
.prt_data1(rd_data_ocm_hp0),
.prt_data2(rd_data_ocm_hp1),
.prt_data3(rd_data_ocm_hp2),
.prt_data4(rd_data_ocm_hp3),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_addr3(rd_addr_hp2),
.prt_addr4(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_bytes3(rd_bytes_hp2),
.prt_bytes4(rd_bytes_hp3),
.prt_dv1(rd_dv_ocm_hp0),
.prt_dv2(rd_dv_ocm_hp1),
.prt_dv3(rd_dv_ocm_hp2),
.prt_dv4(rd_dv_ocm_hp3),
.prt_qos(ocm_rd_qos),
.prt_req(ocm_rd_req),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DFSBP_PP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_PP_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_s00_regslice_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [11 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [11 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [11 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [11 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [11 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_7_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(1),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Registers of the uart 16550 core ////
//// ////
//// Known problems (limits): ////
//// Inserts 1 wait state in all WISHBONE transfers ////
//// ////
//// To Do: ////
//// Nothing or verification. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: (See log for the revision history ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.39 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.38 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.37 2001/12/27 13:24:09 mohor
// lsr[7] was not showing overrun errors.
//
// Revision 1.36 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.35 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.34 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.33 2001/12/17 10:14:43 mohor
// Things related to msr register changed. After THRE IRQ occurs, and one
// character is written to the transmit fifo, the detection of the THRE bit in the
// LSR is delayed for one character time.
//
// Revision 1.32 2001/12/14 13:19:24 mohor
// MSR register fixed.
//
// Revision 1.31 2001/12/14 10:06:58 mohor
// After reset modem status register MSR should be reset.
//
// Revision 1.30 2001/12/13 10:09:13 mohor
// thre irq should be cleared only when being source of interrupt.
//
// Revision 1.29 2001/12/12 09:05:46 mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28 2001/12/10 19:52:41 gorban
// Scratch register added
//
// Revision 1.27 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23 2001/11/12 21:57:29 gorban
// fixed more typo bugs
//
// Revision 1.22 2001/11/12 15:02:28 mohor
// lsr1r error fixed.
//
// Revision 1.21 2001/11/12 14:57:27 mohor
// ti_int_pnd error fixed.
//
// Revision 1.20 2001/11/12 14:50:27 mohor
// ti_int_d error fixed.
//
// Revision 1.19 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16 2001/11/02 09:55:16 mohor
// no message
//
// Revision 1.15 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.14 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/10/19 16:21:40 gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11 2001/10/18 20:35:45 gorban
// small fix
//
// Revision 1.10 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.8 2001/05/29 20:05:04 gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.5 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
`define UART_DL1 7:0
`define UART_DL2 15:8
module uart_regs (clk,
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
tf_push_o,
// additional signals
modem_inputs,
stx_pad_o, srx_pad_i,
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals enabled
ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
`endif
rts_pad_o, dtr_pad_o, int_o
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
//UART control signal
output tf_push_o;
/////////////////////////////////////////////////////
input clk;
input wb_rst_i;
input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_re_i;
output stx_pad_o;
input srx_pad_i;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
`ifdef DATA_BUS_WIDTH_8
`else
// if 32-bit databus and debug interface are enabled
output [3:0] ier;
output [3:0] iir;
output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
output [4:0] mcr;
output [7:0] lcr;
output [7:0] msr;
output [7:0] lsr;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
output [2:0] tstate;
output [3:0] rstate;
`endif
wire [3:0] modem_inputs;
reg enable;
`ifdef UART_HAS_BAUDRATE_OUTPUT
assign baud_o = enable; // baud_o is actually the enable signal
`endif
wire stx_pad_o; // received from transmitter module
wire srx_pad_i;
wire srx_pad;
reg [7:0] wb_dat_o;
wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg [7:0] scratch; // UART scratch register
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask_d; // delay for lsr_mask condition
reg msi_reset; // reset MSR 4 lower bits indicator
//reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals
wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
// LSR bits wires and regs
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask; // lsr_mask
//
// ASSINGS
//
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
// Transmitter Instance
wire serial_out;
assign tf_push_o = tf_push;
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
// Synchronizing and sampling serial RX input
uart_sync_flops i_uart_sync_flops
(
.rst_i (wb_rst_i),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (srx_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
always @(dl or dlab or ier or iir or scratch
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
`UART_REG_MS : wb_dat_o = msr;
`UART_REG_SR : wb_dat_o = scratch;
default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= #1 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= #1 1; // advance read pointer
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask_d <= #1 0;
else // reset bits in the Line Status Register
lsr_mask_d <= #1 lsr_mask_condition;
end
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= #1 1;
else
if (msi_reset)
msi_reset <= #1 0;
else
if (msr_read)
msi_reset <= #1 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= #1 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= #1 wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= #1 4'b0000; // no interrupts after reset
dl[`UART_DL2] <= #1 8'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= #1 wb_dat_i;
end
else
ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= #1 2'b11;
rx_reset <= #1 0;
tx_reset <= #1 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= #1 wb_dat_i[7:6];
rx_reset <= #1 wb_dat_i[1];
tx_reset <= #1 wb_dat_i[2];
end else begin
rx_reset <= #1 0;
tx_reset <= #1 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= #1 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= #1 wb_dat_i[4:0];
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
scratch <= #1 0; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_SR)
scratch <= #1 wb_dat_i;
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
dl[`UART_DL1] <= #1 8'b0;
tf_push <= #1 1'b0;
start_dlc <= #1 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= #1 wb_dat_i;
start_dlc <= #1 1'b1; // enable DL counter
tf_push <= #1 1'b0;
end
else
begin
tf_push <= #1 1'b1;
start_dlc <= #1 1'b0;
end // else: !if(dlab)
else
begin
start_dlc <= #1 1'b0;
tf_push <= #1 1'b0;
end // else: !if(dlab)
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase // case(fcr[`UART_FC_TL])
//
// STATUS REGISTERS //
//
// Modem Status Register
reg [3:0] delayed_modem_signals;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
msr <= #1 0;
delayed_modem_signals[3:0] <= #1 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
end
end
// Line Status Register
// activation conditions
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
// lsr bit0 (receiver data available)
reg lsr0_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0_d <= #1 0;
else lsr0_d <= #1 lsr0;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0r <= #1 0;
else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1_d <= #1 0;
else lsr1_d <= #1 lsr1;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1r <= #1 0;
else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2_d <= #1 0;
else lsr2_d <= #1 lsr2;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2r <= #1 0;
else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3_d <= #1 0;
else lsr3_d <= #1 lsr3;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3r <= #1 0;
else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4_d <= #1 0;
else lsr4_d <= #1 lsr4;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4r <= #1 0;
else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= #1 1;
else lsr5_d <= #1 lsr5;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= #1 1;
else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6_d <= #1 1;
else lsr6_d <= #1 lsr6;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= #1 1;
else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
// lsr bit 7 (error in fifo)
reg lsr7_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7_d <= #1 0;
else lsr7_d <= #1 lsr7;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7r <= #1 0;
else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
dlc <= #1 0;
else
if (start_dlc | ~ (|dlc))
dlc <= #1 dl - 1; // preset counter
else
dlc <= #1 dlc - 1; // decrement counter
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
enable <= #1 1'b0;
else
if (|dl & ~(|dlc)) // dl>0 & dlc==0
enable <= #1 1'b1;
else
enable <= #1 1'b0;
end
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95; // 6 bits
4'b0100 : block_value = 103; // 6.5 bits
4'b0001, 4'b1000 : block_value = 111; // 7 bits
4'b1100 : block_value = 119; // 7.5 bits
4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
4'b1111 : block_value = 175; // 11 bits
endcase // case(lcr[3:0])
// Counting time of one character minus stop bit
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
block_cnt <= #1 8'd0;
else
if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
block_cnt <= #1 block_value;
else
if (enable & block_cnt != 8'b0) // only work on enable times
block_cnt <= #1 block_cnt - 1; // decrement break counter
end // always of break condition detection
// Generating THRE status enable signal
assign thre_set_en = ~(|block_cnt);
//
// INTERRUPT LOGIC
//
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
// delay lines
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_d <= #1 0;
else rls_int_d <= #1 rls_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_d <= #1 0;
else rda_int_d <= #1 rda_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_d <= #1 0;
else thre_int_d <= #1 thre_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_d <= #1 0;
else ms_int_d <= #1 ms_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_d <= #1 0;
else ti_int_d <= #1 ti_int;
// rise detection signals
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
// interrupt pending flags
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
// interrupt pending flags assignments
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_pnd <= #1 0;
else
rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition
rls_int_rise ? 1 : // latch condition
rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_pnd <= #1 0;
else
rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
rda_int_rise ? 1 : // latch condition
rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_pnd <= #1 0;
else
thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
thre_int_rise ? 1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_pnd <= #1 0;
else
ms_int_pnd <= #1 msr_read ? 0 :
ms_int_rise ? 1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_pnd <= #1 0;
else
ti_int_pnd <= #1 fifo_read ? 0 :
ti_int_rise ? 1 :
ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= #1 1'b0;
else
int_o <= #1
rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1 :
ti_int_pnd ? ~fifo_read :
thre_int_pnd ? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
0; // if no interrupt are pending
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= #1 1;
else
if (rls_int_pnd) // interrupt is pending
begin
iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending)
end else // the sequence of conditions determines priority of interrupt identification
if (rda_int)
begin
iir[`UART_II_II] <= #1 `UART_II_RDA;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_TI;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_THRE;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_MS;
iir[`UART_II_IP] <= #1 1'b0;
end else // no interrupt is pending
begin
iir[`UART_II_II] <= #1 0;
iir[`UART_II_IP] <= #1 1'b1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_BEHAVIORAL_PP_V |
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_uart_0_tx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
do_force_break,
reset_n,
status_wr_strobe,
tx_data,
tx_wr_strobe,
// outputs:
tx_overrun,
tx_ready,
tx_shift_empty,
txd
)
;
output tx_overrun;
output tx_ready;
output tx_shift_empty;
output txd;
input [ 9: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input do_force_break;
input reset_n;
input status_wr_strobe;
input [ 7: 0] tx_data;
input tx_wr_strobe;
reg baud_clk_en;
reg [ 9: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg do_load_shifter;
wire do_shift;
reg pre_txd;
wire shift_done;
wire [ 9: 0] tx_load_val;
reg tx_overrun;
reg tx_ready;
reg tx_shift_empty;
wire tx_shift_reg_out;
wire [ 9: 0] tx_shift_register_contents;
wire tx_wr_strobe_onset;
reg txd;
wire [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_in;
reg [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out;
assign tx_wr_strobe_onset = tx_wr_strobe && begintransfer;
assign tx_load_val = {{1 {1'b1}},
tx_data,
1'b0};
assign shift_done = ~(|tx_shift_register_contents);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_load_shifter <= 0;
else if (clk_en)
do_load_shifter <= (~tx_ready) && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_ready <= 1'b1;
else if (clk_en)
if (tx_wr_strobe_onset)
tx_ready <= 0;
else if (do_load_shifter)
tx_ready <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
tx_overrun <= 0;
else if (~tx_ready && tx_wr_strobe_onset)
tx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_shift_empty <= 1'b1;
else if (clk_en)
tx_shift_empty <= tx_ready && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || do_load_shifter)
baud_rate_counter <= baud_divisor;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
baud_clk_en <= baud_rate_counter_is_zero;
end
assign do_shift = baud_clk_en &&
(~shift_done) &&
(~do_load_shifter);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pre_txd <= 1;
else if (~shift_done)
pre_txd <= tx_shift_reg_out;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
txd <= 1;
else if (clk_en)
txd <= pre_txd & ~do_force_break;
end
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out <= 0;
else if (clk_en)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out <= unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_in;
end
assign unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_in = (do_load_shifter)? tx_load_val :
(do_shift)? {1'b0,
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out[9 : 1]} :
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out;
assign tx_shift_register_contents = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out;
assign tx_shift_reg_out = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx6_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_uart_0_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
)
;
output source_rxd;
input [ 9: 0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
reg [ 7: 0] d1_stim_data;
reg delayed_unxrx_char_readyxx0;
wire do_send_stim_data;
wire pickup_pulse;
wire source_rxd;
wire [ 7: 0] stim_data;
wire unused_empty;
wire unused_overrun;
wire unused_ready;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//stimulus_transmitter, which is an e_instance
nios_dut_uart_0_tx stimulus_transmitter
(
.baud_divisor (baud_divisor),
.begintransfer (do_send_stim_data),
.clk (clk),
.clk_en (clk_en),
.do_force_break (1'b0),
.reset_n (reset_n),
.status_wr_strobe (1'b0),
.tx_data (d1_stim_data),
.tx_overrun (unused_overrun),
.tx_ready (unused_ready),
.tx_shift_empty (unused_empty),
.tx_wr_strobe (1'b1),
.txd (source_rxd)
);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_stim_data <= 0;
else if (do_send_stim_data)
d1_stim_data <= stim_data;
end
assign stim_data = 8'b0;
//delayed_unxrx_char_readyxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_char_readyxx0 <= 0;
else if (clk_en)
delayed_unxrx_char_readyxx0 <= rx_char_ready;
end
assign pickup_pulse = ~(rx_char_ready) & (delayed_unxrx_char_readyxx0);
assign do_send_stim_data = (pickup_pulse || 1'b0) && 1'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign source_rxd = rxd;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_uart_0_rx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
reset_n,
rx_rd_strobe,
rxd,
status_wr_strobe,
// outputs:
break_detect,
framing_error,
parity_error,
rx_char_ready,
rx_data,
rx_overrun
)
;
output break_detect;
output framing_error;
output parity_error;
output rx_char_ready;
output [ 7: 0] rx_data;
output rx_overrun;
input [ 9: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input reset_n;
input rx_rd_strobe;
input rxd;
input status_wr_strobe;
reg baud_clk_en;
wire [ 9: 0] baud_load_value;
reg [ 9: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg break_detect;
reg delayed_unxrx_in_processxx3;
reg delayed_unxsync_rxdxx1;
reg delayed_unxsync_rxdxx2;
reg do_start_rx;
reg framing_error;
wire got_new_char;
wire [ 8: 0] half_bit_cell_divisor;
wire is_break;
wire is_framing_error;
wire parity_error;
wire [ 7: 0] raw_data_in;
reg rx_char_ready;
reg [ 7: 0] rx_data;
wire rx_in_process;
reg rx_overrun;
wire rx_rd_strobe_onset;
wire rxd_edge;
wire rxd_falling;
wire [ 9: 0] rxd_shift_reg;
wire sample_enable;
wire shift_reg_start_bit_n;
wire source_rxd;
wire stop_bit;
wire sync_rxd;
wire unused_start_bit;
wire [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_in;
reg [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out;
nios_dut_uart_0_rx_stimulus_source the_nios_dut_uart_0_rx_stimulus_source
(
.baud_divisor (baud_divisor),
.clk (clk),
.clk_en (clk_en),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rxd (rxd),
.source_rxd (source_rxd)
);
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (source_rxd),
.dout (sync_rxd),
.reset_n (reset_n)
);
defparam the_altera_std_synchronizer.depth = 2;
//delayed_unxsync_rxdxx1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx1 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx1 <= sync_rxd;
end
assign rxd_falling = ~(sync_rxd) & (delayed_unxsync_rxdxx1);
//delayed_unxsync_rxdxx2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx2 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx2 <= sync_rxd;
end
assign rxd_edge = (sync_rxd) ^ (delayed_unxsync_rxdxx2);
assign rx_rd_strobe_onset = rx_rd_strobe && begintransfer;
assign half_bit_cell_divisor = baud_divisor[9 : 1];
assign baud_load_value = (rxd_edge)? half_bit_cell_divisor :
baud_divisor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || rxd_edge)
baud_rate_counter <= baud_load_value;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
if (rxd_edge)
baud_clk_en <= 0;
else
baud_clk_en <= baud_rate_counter_is_zero;
end
assign sample_enable = baud_clk_en && rx_in_process;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_start_rx <= 0;
else if (clk_en)
if (~rx_in_process && rxd_falling)
do_start_rx <= 1;
else
do_start_rx <= 0;
end
assign rx_in_process = shift_reg_start_bit_n;
assign {stop_bit,
raw_data_in,
unused_start_bit} = rxd_shift_reg;
assign is_break = ~(|rxd_shift_reg);
assign is_framing_error = ~stop_bit && ~is_break;
//delayed_unxrx_in_processxx3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_in_processxx3 <= 0;
else if (clk_en)
delayed_unxrx_in_processxx3 <= rx_in_process;
end
assign got_new_char = ~(rx_in_process) & (delayed_unxrx_in_processxx3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_data <= 0;
else if (got_new_char)
rx_data <= raw_data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
framing_error <= 0;
else if (clk_en)
if (status_wr_strobe)
framing_error <= 0;
else if (got_new_char && is_framing_error)
framing_error <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
break_detect <= 0;
else if (clk_en)
if (status_wr_strobe)
break_detect <= 0;
else if (got_new_char && is_break)
break_detect <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
rx_overrun <= 0;
else if (got_new_char && rx_char_ready)
rx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_char_ready <= 0;
else if (clk_en)
if (rx_rd_strobe_onset)
rx_char_ready <= 0;
else if (got_new_char)
rx_char_ready <= -1;
end
assign parity_error = 0;
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out <= 0;
else if (clk_en)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_in;
end
assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_in = (do_start_rx)? {10{1'b1}} :
(sample_enable)? {sync_rxd,
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out[9 : 1]} :
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out;
assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out;
assign shift_reg_start_bit_n = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx7_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_uart_0_regs (
// inputs:
address,
break_detect,
chipselect,
clk,
clk_en,
cts_n,
framing_error,
parity_error,
read_n,
reset_n,
rx_char_ready,
rx_data,
rx_overrun,
tx_overrun,
tx_ready,
tx_shift_empty,
write_n,
writedata,
// outputs:
baud_divisor,
dataavailable,
do_force_break,
irq,
readdata,
readyfordata,
rts_n,
rx_rd_strobe,
status_wr_strobe,
tx_data,
tx_wr_strobe
)
;
output [ 9: 0] baud_divisor;
output dataavailable;
output do_force_break;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output rts_n;
output rx_rd_strobe;
output status_wr_strobe;
output [ 7: 0] tx_data;
output tx_wr_strobe;
input [ 2: 0] address;
input break_detect;
input chipselect;
input clk;
input clk_en;
input cts_n;
input framing_error;
input parity_error;
input read_n;
input reset_n;
input rx_char_ready;
input [ 7: 0] rx_data;
input rx_overrun;
input tx_overrun;
input tx_ready;
input tx_shift_empty;
input write_n;
input [ 15: 0] writedata;
wire any_error;
wire [ 9: 0] baud_divisor;
reg [ 12: 0] control_reg;
wire control_wr_strobe;
wire cts_edge;
reg cts_status_bit;
reg d1_rx_char_ready;
reg d1_tx_ready;
wire dataavailable;
reg dcts_status_bit;
reg delayed_unxcts_status_bitxx5;
reg delayed_unxtx_readyxx4;
wire [ 9: 0] divisor_constant;
wire do_force_break;
wire do_write_char;
wire eop_status_bit;
wire ie_any_error;
wire ie_break_detect;
wire ie_dcts;
wire ie_framing_error;
wire ie_parity_error;
wire ie_rx_char_ready;
wire ie_rx_overrun;
wire ie_tx_overrun;
wire ie_tx_ready;
wire ie_tx_shift_empty;
reg irq;
wire qualified_irq;
reg [ 15: 0] readdata;
wire readyfordata;
wire rts_control_bit;
wire rts_n;
wire rx_rd_strobe;
wire [ 15: 0] selected_read_data;
wire [ 12: 0] status_reg;
wire status_wr_strobe;
reg [ 7: 0] tx_data;
wire tx_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= selected_read_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq <= 0;
else if (clk_en)
irq <= qualified_irq;
end
assign rx_rd_strobe = chipselect && ~read_n && (address == 3'd0);
assign tx_wr_strobe = chipselect && ~write_n && (address == 3'd1);
assign status_wr_strobe = chipselect && ~write_n && (address == 3'd2);
assign control_wr_strobe = chipselect && ~write_n && (address == 3'd3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_data <= 0;
else if (tx_wr_strobe)
tx_data <= writedata[7 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg <= 0;
else if (control_wr_strobe)
control_reg <= writedata[12 : 0];
end
assign baud_divisor = divisor_constant;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cts_status_bit <= 1;
else if (clk_en)
cts_status_bit <= ~cts_n;
end
//delayed_unxcts_status_bitxx5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcts_status_bitxx5 <= 0;
else if (clk_en)
delayed_unxcts_status_bitxx5 <= cts_status_bit;
end
assign cts_edge = (cts_status_bit) ^ (delayed_unxcts_status_bitxx5);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dcts_status_bit <= 0;
else if (clk_en)
if (status_wr_strobe)
dcts_status_bit <= 0;
else if (cts_edge)
dcts_status_bit <= -1;
end
assign rts_n = ~rts_control_bit;
assign {rts_control_bit,
ie_dcts,
do_force_break,
ie_any_error,
ie_rx_char_ready,
ie_tx_ready,
ie_tx_shift_empty,
ie_tx_overrun,
ie_rx_overrun,
ie_break_detect,
ie_framing_error,
ie_parity_error} = control_reg;
assign any_error = tx_overrun ||
rx_overrun ||
parity_error ||
framing_error ||
break_detect;
assign status_reg = {eop_status_bit,
cts_status_bit,
dcts_status_bit,
1'b0,
any_error,
rx_char_ready,
tx_ready,
tx_shift_empty,
tx_overrun,
rx_overrun,
break_detect,
framing_error,
parity_error};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_rx_char_ready <= 0;
else if (clk_en)
d1_rx_char_ready <= rx_char_ready;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_tx_ready <= 0;
else if (clk_en)
d1_tx_ready <= tx_ready;
end
assign dataavailable = d1_rx_char_ready;
assign readyfordata = d1_tx_ready;
assign eop_status_bit = 1'b0;
assign selected_read_data = ({16 {(address == 3'd0)}} & rx_data) |
({16 {(address == 3'd1)}} & tx_data) |
({16 {(address == 3'd2)}} & status_reg) |
({16 {(address == 3'd3)}} & control_reg);
assign qualified_irq = (ie_dcts && dcts_status_bit ) ||
(ie_any_error && any_error ) ||
(ie_tx_shift_empty && tx_shift_empty ) ||
(ie_tx_overrun && tx_overrun ) ||
(ie_rx_overrun && rx_overrun ) ||
(ie_break_detect && break_detect ) ||
(ie_framing_error && framing_error ) ||
(ie_parity_error && parity_error ) ||
(ie_rx_char_ready && rx_char_ready ) ||
(ie_tx_ready && tx_ready );
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//delayed_unxtx_readyxx4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxtx_readyxx4 <= 0;
else if (clk_en)
delayed_unxtx_readyxx4 <= tx_ready;
end
assign do_write_char = (tx_ready) & ~(delayed_unxtx_readyxx4);
always @(posedge clk)
begin
if (do_write_char)
$write("%c", tx_data);
end
assign divisor_constant = 4;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign divisor_constant = 543;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_uart_0 (
// inputs:
address,
begintransfer,
chipselect,
clk,
cts_n,
read_n,
reset_n,
rxd,
write_n,
writedata,
// outputs:
dataavailable,
irq,
readdata,
readyfordata,
rts_n,
txd
)
/* synthesis altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" */ ;
output dataavailable;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output rts_n;
output txd;
input [ 2: 0] address;
input begintransfer;
input chipselect;
input clk;
input cts_n;
input read_n;
input reset_n;
input rxd;
input write_n;
input [ 15: 0] writedata;
wire [ 9: 0] baud_divisor;
wire break_detect;
wire clk_en;
wire dataavailable;
wire do_force_break;
wire framing_error;
wire irq;
wire parity_error;
wire [ 15: 0] readdata;
wire readyfordata;
wire rts_n;
wire rx_char_ready;
wire [ 7: 0] rx_data;
wire rx_overrun;
wire rx_rd_strobe;
wire status_wr_strobe;
wire [ 7: 0] tx_data;
wire tx_overrun;
wire tx_ready;
wire tx_shift_empty;
wire tx_wr_strobe;
wire txd;
assign clk_en = 1;
nios_dut_uart_0_tx the_nios_dut_uart_0_tx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.clk (clk),
.clk_en (clk_en),
.do_force_break (do_force_break),
.reset_n (reset_n),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.txd (txd)
);
nios_dut_uart_0_rx the_nios_dut_uart_0_rx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.break_detect (break_detect),
.clk (clk),
.clk_en (clk_en),
.framing_error (framing_error),
.parity_error (parity_error),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.rxd (rxd),
.status_wr_strobe (status_wr_strobe)
);
nios_dut_uart_0_regs the_nios_dut_uart_0_regs
(
.address (address),
.baud_divisor (baud_divisor),
.break_detect (break_detect),
.chipselect (chipselect),
.clk (clk),
.clk_en (clk_en),
.cts_n (cts_n),
.dataavailable (dataavailable),
.do_force_break (do_force_break),
.framing_error (framing_error),
.irq (irq),
.parity_error (parity_error),
.read_n (read_n),
.readdata (readdata),
.readyfordata (readyfordata),
.reset_n (reset_n),
.rts_n (rts_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.write_n (write_n),
.writedata (writedata)
);
//s1, which is an e_avalon_slave
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: HW_SW.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module HW_SW (
address,
clock,
q);
input [7:0] address;
input clock;
output [127:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "HVSW"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "HV_SW.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "HV_SW.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=HVSW"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module premuat1_32(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
output signed [15:0] o_8;
output signed [15:0] o_9;
output signed [15:0] o_10;
output signed [15:0] o_11;
output signed [15:0] o_12;
output signed [15:0] o_13;
output signed [15:0] o_14;
output signed [15:0] o_15;
output signed [15:0] o_16;
output signed [15:0] o_17;
output signed [15:0] o_18;
output signed [15:0] o_19;
output signed [15:0] o_20;
output signed [15:0] o_21;
output signed [15:0] o_22;
output signed [15:0] o_23;
output signed [15:0] o_24;
output signed [15:0] o_25;
output signed [15:0] o_26;
output signed [15:0] o_27;
output signed [15:0] o_28;
output signed [15:0] o_29;
output signed [15:0] o_30;
output signed [15:0] o_31;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [15:0] o1;
reg signed [15:0] o2;
reg signed [15:0] o3;
reg signed [15:0] o4;
reg signed [15:0] o5;
reg signed [15:0] o6;
reg signed [15:0] o7;
reg signed [15:0] o8;
reg signed [15:0] o9;
reg signed [15:0] o10;
reg signed [15:0] o11;
reg signed [15:0] o12;
reg signed [15:0] o13;
reg signed [15:0] o14;
reg signed [15:0] o15;
reg signed [15:0] o16;
reg signed [15:0] o17;
reg signed [15:0] o18;
reg signed [15:0] o19;
reg signed [15:0] o20;
reg signed [15:0] o21;
reg signed [15:0] o22;
reg signed [15:0] o23;
reg signed [15:0] o24;
reg signed [15:0] o25;
reg signed [15:0] o26;
reg signed [15:0] o27;
reg signed [15:0] o28;
reg signed [15:0] o29;
reg signed [15:0] o30;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1 =i_2 ;
o2 =i_4 ;
o3 =i_6 ;
o4 =i_8 ;
o5 =i_10;
o6 =i_12;
o7 =i_14;
o8 =i_16;
o9 =i_18;
o10=i_20;
o11=i_22;
o12=i_24;
o13=i_26;
o14=i_28;
o15=i_30;
o16=i_1 ;
o17=i_3 ;
o18=i_5 ;
o19=i_7 ;
o20=i_9 ;
o21=i_11;
o22=i_13;
o23=i_15;
o24=i_17;
o25=i_19;
o26=i_21;
o27=i_23;
o28=i_25;
o29=i_27;
o30=i_29;
end
else
begin
o1 =i_16;
o2 =i_1;
o3 =i_17;
o4 =i_2;
o5 =i_18;
o6 =i_3;
o7 =i_19;
o8 =i_4;
o9 =i_20;
o10=i_5;
o11=i_21;
o12=i_6;
o13=i_22;
o14=i_7;
o15=i_23;
o16=i_8;
o17=i_24;
o18=i_9;
o19=i_25;
o20=i_10;
o21=i_26;
o22=i_11;
o23=i_27;
o24=i_12;
o25=i_28;
o26=i_13;
o27=i_29;
o28=i_14;
o29=i_30;
o30=i_15;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=enable?o7:i_7;
assign o_8=enable?o8:i_8;
assign o_9=enable?o9:i_9;
assign o_10=enable?o10:i_10;
assign o_11=enable?o11:i_11;
assign o_12=enable?o12:i_12;
assign o_13=enable?o13:i_13;
assign o_14=enable?o14:i_14;
assign o_15=enable?o15:i_15;
assign o_16=enable?o16:i_16;
assign o_17=enable?o17:i_17;
assign o_18=enable?o18:i_18;
assign o_19=enable?o19:i_19;
assign o_20=enable?o20:i_20;
assign o_21=enable?o21:i_21;
assign o_22=enable?o22:i_22;
assign o_23=enable?o23:i_23;
assign o_24=enable?o24:i_24;
assign o_25=enable?o25:i_25;
assign o_26=enable?o26:i_26;
assign o_27=enable?o27:i_27;
assign o_28=enable?o28:i_28;
assign o_29=enable?o29:i_29;
assign o_30=enable?o30:i_30;
assign o_31=i_31;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 19:26:51 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/system_util_vector_logic_0_0_sim_netlist.v
// Design : system_util_vector_logic_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_util_vector_logic_0_0,util_vector_logic,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "util_vector_logic,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_util_vector_logic_0_0
(Op1,
Op2,
Res);
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
wire [0:0]Op1;
wire [0:0]Op2;
wire [0:0]Res;
LUT2 #(
.INIT(4'h8))
\Res[0]_INST_0
(.I0(Op1),
.I1(Op2),
.O(Res));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_SYMBOL_V
`define SKY130_FD_SC_HD__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311AI_4_V
`define SKY130_FD_SC_MS__O311AI_4_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311ai_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311AI_4_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:47 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_processing_system7_0_0_sim_netlist.v
// Design : led_controller_design_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "led_controller_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "led_controller_design_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "led_controller_design_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
`include "riffa.vh"
/*
NUM_CLUSTERS: Number of processing cluster's composed of multiple Processing Elements (PE).
Incoming stream of reads is distributed across the clusters (operating at lower frequency than RIFFA) to achieve high bandwidth.
Increasing it causes higher incoming (download) PCIe bandwidth utilization.
NUM_PES: Number of Processing Elements per cluster. In a cluster, each PE evaluates the read assigned to the cluster against its
own reference read (so each cluster produces NUM_PES results for a single read).
Each PE in a cluster has different reference read. However, the PEs share the same reference reads across the clusters.
(i.e., cluster[n].pe[i].reference_read == cluster[m].pe[i].reference_read)
Increasing it causes higher outgoing (upload) PCIe bandwidth utilization.
*/
module SHD_top #(parameter C_PCI_DATA_WIDTH = 128, NUM_CLUSTERS = 8, NUM_PES = 8) (
//RIFFA Interface
input riffa_clk,
input riffa_rst, // riffa_reset includes riffa_endpoint resets
// Rx interface
output CHNL_RX_CLK,
input CHNL_RX,
output CHNL_RX_ACK,
input CHNL_RX_LAST,
input[31:0] CHNL_RX_LEN,
input[30:0] CHNL_RX_OFF,
input[C_PCI_DATA_WIDTH - 1:0] CHNL_RX_DATA,
input CHNL_RX_DATA_VALID,
output CHNL_RX_DATA_REN,
// Tx interface
output CHNL_TX_CLK,
output CHNL_TX,
input CHNL_TX_ACK,
output CHNL_TX_LAST,
output[31:0] CHNL_TX_LEN,
output[30:0] CHNL_TX_OFF,
output[C_PCI_DATA_WIDTH - 1:0] CHNL_TX_DATA,
output CHNL_TX_DATA_VALID,
input CHNL_TX_DATA_REN,
//App Interface
input clk,
input rst
);
parameter PE_BITS = $clog2(NUM_PES);
assign CHNL_RX_CLK = riffa_clk;
assign CHNL_TX_CLK = riffa_clk;
wire sched_rd_en;
wire[C_PCI_DATA_WIDTH - 1:0] sched_dna_data;
wire sched_dna_valid;
wire[`SIG_CHNL_LENGTH_W - 1:0] dna_len;
wire sender_en, sender_idle;
wire refread_set;
//wire[PE_BITS - 1:0] refread_cluster_id;
wire[C_PCI_DATA_WIDTH - 1:0] refread_data;
pcie_data_receiver #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .NUM_PES(NUM_PES)) i_riffa_recv(
.clk(riffa_clk),
.rst(rst),
//RIFFA Interface
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_LEN(CHNL_RX_LEN),
//Scheduler Interface
.dna_rd_en(sched_rd_en),
.dna_data(sched_dna_data),
.dna_valid(sched_dna_valid),
// RefRead Manager Interface
.refread_set(refread_set),
//.refread_cluster_id(refread_cluster_id),
.refread_data(refread_data),
//Sender Interface
.dna_len(dna_len),
.sender_ready(sender_idle),
.sender_en(sender_en)
);
wire[C_PCI_DATA_WIDTH*NUM_PES - 1:0] refread_reads;
refread_manager #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .NUM_REFS(NUM_PES)) i_refread_manager(
.clk(CHNL_RX_CLK),
.rst(rst),
.set(refread_set),
//.cluster_id(refread_cluster_id),
.refread_in(refread_data),
.refread_out(refread_reads)
);
wire[NUM_CLUSTERS - 1:0] shd_rd_en, shd_valid;
wire[NUM_CLUSTERS*C_PCI_DATA_WIDTH - 1:0] shd_dna;
SHDScheduler #(.DNA_DATA_WIDTH(C_PCI_DATA_WIDTH), .NUM_CLUSTERS(NUM_CLUSTERS)) i_sched (
.clk(riffa_clk),
.rst(rst),
//Receiver Interface
.dna_rd_en(sched_rd_en),
.dna_data_in(sched_dna_data),
.dna_valid_in(sched_dna_valid),
//Cluster Interface
.shd_clk(clk),
.shd_rd_en_in(shd_rd_en),
.shd_valid_out(shd_valid),
.shd_dna_data_out(shd_dna)
);
wire[NUM_CLUSTERS - 1:0] coll_rd_en, coll_data_valid;
wire[NUM_CLUSTERS*NUM_PES - 1:0] coll_data;
genvar i;
generate
for(i = 0; i < NUM_CLUSTERS; i = i + 1) begin
SHDCluster #(.DNA_DATA_WIDTH(C_PCI_DATA_WIDTH), .NUM_PES(NUM_PES)) i_cluster (
.clk(clk),
.rst(rst),
//Scheduler Interface
.dna_in(shd_dna[i*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH]),
.dna_ref_in(refread_reads),
.dna_valid_in(shd_valid[i]),
.dna_rd_en(shd_rd_en[i]),
//Collector Interface
.coll_clk(riffa_clk),
.coll_rd_en(coll_rd_en[i]),
.coll_dna_err(coll_data[i*NUM_PES +: NUM_PES]),
.coll_valid(coll_data_valid[i])
);
end
endgenerate
wire sender_ready, sender_data_valid;
wire[NUM_PES - 1:0] sender_data;
SHDCollector #(.DNA_DATA_WIDTH(C_PCI_DATA_WIDTH), .NUM_CLUSTERS(NUM_CLUSTERS), .NUM_PES(NUM_PES)) i_collector (
.clk(riffa_clk),
.rst(rst),
//Cluster Interface
.cluster_rd_en(coll_rd_en),
.cluster_data(coll_data),
.cluster_valid(coll_data_valid),
//Sender Interface
.sender_ready(sender_ready),
.sender_data_valid(sender_data_valid),
.sender_data(sender_data)
);
pcie_data_sender #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .INPUT_DATA_WIDTH(NUM_PES), .NUM_PES(NUM_PES)) i_sender(
.clk(CHNL_TX_CLK),
.rst(rst),
//Collector Interface
.coll_ready(sender_ready),
.coll_data_valid(sender_data_valid),
.coll_data(sender_data),
//RIFFA TX Interface
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN),
//Sender Interface
.dna_len(dna_len),
.en(sender_en),
.idle(sender_idle)
);
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1ns / 10ps
//
// CY7C1356
// Simulatiom of Verilog model
//
//
//
// test bench for US vector input
//
//
// define speed 166MHz
`define tx10 #6
`define tx08 #4.8
`define tx05 #3
`define tx04 #2.4
`define tx02 #1.2
/*
`define tx10 #4.0 // period
`define tx08 #3.2 //0.8 period
`define tx05 #2.0 //0.5 period 250MHZ
`define tx04 #1.6 //0.4 period
`define tx02 #0.8 //0.2 period
`define tx10 #4.4 // period
`define tx08 #3.52 //0.8 period
`define tx05 #2.2 //0.5 period 225MHZ
`define tx04 #1.76 //0.4 period
`define tx02 #0.88 //0.2 period
`define tx10 #5 // period
`define tx08 #4 //0.8 period
`define tx05 #2.5 //0.5 period 200MHZ
`define tx04 #2.0 //0.4 period
`define tx02 #1.0 //0.2 period
*/
module rw_test;
`define num_vectors 126
`define impi {a[15:0],io[15:0],tsti[15:0],cenb,ce1b,ce2,ce3b,bweb,bwb,adv_lb}
reg [57:1] lsim_vectors [1:`num_vectors];
reg clk;
reg adv_lb;
reg ce1b; //cs1b
reg ce2; //cs2
reg ce3b; //cs3b
reg [1:0] bwb;
reg bweb;
reg oeb;
reg ftb;
reg mode; //lbob
reg cenb; //zz
reg tp42; //sclk
reg tp39; //se
reg tp38; //tm
reg [19:0] a;
reg [17:0] io;
reg [17:0] tsti;
reg vddq;
reg vssqr;
reg iosel;
wire [17:0] d = iosel ? io[17:0] : 18'bz;
reg noti3;
reg strb,j;
integer vector,i;
cy1356 testram ( d, clk, a, bwb, bweb, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);
initial
begin
$dumpfile("dumpfile.dump");
$dumpvars(0,rw_test);
end
initial
begin
io = 18'bz;
ftb = 1;
oeb = 0;
a[19:16] = 4'h0;
mode = 0;
strb = 0;
tp38 = 0;
tp39 = 0;
tp42 = 0;
`tx02;
forever `tx05 strb = ~strb;
end
initial
begin
clk = 0;
forever `tx05 clk =~clk;
end
initial
begin
$readmemb("cy1356.inp", lsim_vectors); //load input vector file
`impi = lsim_vectors[1]; //apply 1st test vector
for (vector = 2; vector <= `num_vectors; vector = vector + 1)
@(posedge strb)
begin
`impi = lsim_vectors[vector];
io[16:13] = io[07:04];
io[12:09] = io[07:04];
io[07:04] = io[03:00];
io[03:00] = io[03:00];
io[17] = io[16] ^^ io[15] ^^ io[14] ^^ io[13] ^^ io[11] ^^ io[11] ^^ io[10] ^^ io[9];
io[8] = io[7] ^^ io[6] ^^ io[5] ^^ io[4] ^^ io[3] ^^ io[2] ^^ io[1] ^^ io[0];
tsti[16:13] = tsti[07:04];
tsti[12:09] = tsti[07:04];
tsti[07:04] = tsti[03:00];
tsti[03:00] = tsti[03:00];
tsti[17] = tsti[16] ^^ tsti[15] ^^ tsti[14] ^^ tsti[13] ^^ tsti[11] ^^ tsti[11] ^^ tsti[10] ^^ tsti[9];
tsti[8] = tsti[7] ^^ tsti[6] ^^ tsti[5] ^^ tsti[4] ^^ tsti[3] ^^ tsti[2] ^^ tsti[1] ^^ tsti[0];
if (io === 18'hxxxxx)
iosel = `tx05 0;
else
iosel = `tx05 1;
end
#15 $finish; // This prevents simulation beyond end of test patterns
end
always@(posedge clk)
begin
if (io !== 18'hxxxxx) //input cycle
begin
$display("NOTICE : 001 : line = %d OK",vector -1);
end
else //do the test
begin
if (d == tsti)
begin
$display("NOTICE : 002 : line = %d OK",vector -1);
end
else
begin
j =0;
for (i =0;i< 18; i=i+1)
begin
if(tsti[i] !== 1'bx)
begin
if (d[i] !== tsti[i]) j = 1;
end
else
j = 0;
end
if (j)
$display("ERROR *** : 003 : line = %d data = %b test = %b",vector -1,d,tsti);
else
$display("NOTICE : 003 : line = %d OK",vector -1);
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$NR_pp$PKG$sN: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$NR_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
|
`timescale 1ns / 1ps
module toplevel(
input wire clk100,
input wire cpu_reset,//active low
input wire tck,
input wire tms,
input wire tdi,
input wire trst,//ignored
output reg tdo,
input wire serial_rx,
output wire serial_tx,
input wire user_sw0,
input wire user_sw1,
input wire user_sw2,
input wire user_sw3,
input wire user_btn0,
input wire user_btn1,
input wire user_btn2,
input wire user_btn3,
output wire user_led0,
output wire user_led1,
output wire user_led2,
output wire user_led3
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_asyncReset = ~cpu_reset;
assign {user_led3,user_led2,user_led1,user_led0} = io_gpioA_write[3 : 0];
assign io_gpioA_read[3:0] = {user_sw3,user_sw2,user_sw1,user_sw0};
assign io_gpioA_read[7:4] = {user_btn3,user_btn2,user_btn1,user_btn0};
assign io_gpioA_read[11:8] = {tck,tms,tdi,trst};
reg tesic_tck,tesic_tms,tesic_tdi;
wire tesic_tdo;
reg soc_tck,soc_tms,soc_tdi;
wire soc_tdo;
always @(*) begin
{soc_tck, soc_tms, soc_tdi } = {tck,tms,tdi};
tdo = soc_tdo;
end
Murax core (
.io_asyncReset(io_asyncReset),
.io_mainClk (clk100 ),
.io_jtag_tck(soc_tck),
.io_jtag_tdi(soc_tdi),
.io_jtag_tdo(soc_tdo),
.io_jtag_tms(soc_tms),
.io_gpioA_read (io_gpioA_read),
.io_gpioA_write (io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(serial_tx),
.io_uart_rxd(serial_rx)
);
endmodule
|
`include "timescale.v"
module fb_slave_counters (MRxClk, Reset, MRxDEqDataSoC,
StateIdle, StatePreamble, StateData, StateSlaveData, StateSlaveCrc, StateFrmCrc,
TotalNibCnt, NibCnt, SlaveCrcEnd, FrmCrcStateEnd, TxRamAddr, RxRamAddr, SlaveByteCntEq0, IncrementTotalNibCnt
);
input MRxClk; // Tx clock
input Reset; // Reset
input StateIdle; // Idle state
input StatePreamble; // Preamble state
input StateData; // Data state
input [1:0] StateSlaveData; // StateSlaveData state
input StateSlaveCrc; // slave CRC state
input StateFrmCrc;
input MRxDEqDataSoC;
output [15:0] TotalNibCnt; // total Nibble counter
output [15:0] NibCnt; // Nibble counter
output SlaveCrcEnd;
output FrmCrcStateEnd;
output [7: 0] TxRamAddr;
output [7: 0] RxRamAddr;
output SlaveByteCntEq0;
output IncrementTotalNibCnt;
wire SlaveByteCntEq0;
wire [3:0] CrcNibbleCnt;
reg [15:0] TotalNibCnt;
reg [15:0] NibCnt;
reg [3: 0] CrcNibCnt;
reg [3: 0] PreambleNibCnt;
reg [3: 0] FrmCrcNibCnt;
reg [7: 0] TxRamAddr;
reg [7: 0] RxRamAddr;
assign CrcNibbleCnt = 4'd2;
wire ResetNibCnt;
wire IncrementNibCnt;
assign IncrementNibCnt = (|StateSlaveData) ;
assign ResetNibCnt = StateIdle | StateData ;
// Nibble Counter started from each slave data( only for data, no SoC no CRC)
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
NibCnt <= 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 16'd1;
end
end
wire ResetTotalNibCnt;
wire IncrementTotalNibCnt;
assign IncrementTotalNibCnt = StatePreamble | StateData | (|StateSlaveData) | StateSlaveCrc ;
assign ResetTotalNibCnt = StateIdle;
// Total Nibble Counter for the whole frame incl.( Preamble, SlaveDate, SlaveCRC, NO FrameCRC)
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TotalNibCnt <= 16'h0;
else
begin
if(ResetTotalNibCnt)
TotalNibCnt <= 16'h0;
else
if(IncrementTotalNibCnt)
TotalNibCnt <= TotalNibCnt + 16'd1;
end
end
wire IncrementCrcNibCnt;
wire ResetCrcNibCnt;
assign IncrementCrcNibCnt = StateSlaveCrc ;
assign ResetCrcNibCnt = |StateSlaveData ;
assign SlaveCrcEnd = CrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
CrcNibCnt <= 4'b0;
else
begin
if(ResetCrcNibCnt)
CrcNibCnt <= 4'b0;
else
if(IncrementCrcNibCnt)
CrcNibCnt <= CrcNibCnt + 4'b0001;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateIdle | StatePreamble | StateData | (|StateSlaveData) | StateSlaveCrc;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
wire IncrementTxRamAddr;
wire ResetTxRamAddr;
assign ResetTxRamAddr = StateIdle | StatePreamble | StateData;
assign IncrementTxRamAddr = StartSlaveData[0];
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TxRamAddr <= 8'b0;
else
begin
if(ResetTxRamAddr)
TxRamAddr <= 8'b0;
else
if(IncrementTxRamAddr)
TxRamAddr <= TxRamAddr + 8'b0001;
end
end
wire ResetRxRamAddr;
wire IncrementRxRamAddr;
assign ResetRxRamAddr = StateIdle | StateFFS | StatePreamble | StateData;
assign IncrementRxRamAddr = RxValid ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxRamAddr[7:0] <= 8'd0;
else
begin
if(ResetRxRamAddr)
RxRamAddr[7:0] <= 8'd0;
else
if(IncrementRxRamAddr)
RxRamAddr[7:0] <= RxRamAddr[7:0] + 8'd1;
end
end
wire ResetByteCounter;
wire IncrementByteCounter;
wire ByteCntMax;
assign ResetByteCounter = MRxDV & StatePreamble & MRxDEqDataSoC | StateData;
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &( StateSlaveData[1] & ~ByteCntMax ) ;
assign SlaveByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntMax = ByteCnt == 16'hffff;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_M_V
`define SKY130_FD_SC_LP__AND3_M_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_m (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_m (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_M_V
|
`timescale 1ns / 1ps
///////////////////////////////////////////////////////
// NAME : Ankit Sarraf
// CREATE DATE : 09:45:29 June 26, 2014
// PROJECT NAME : Guessing Game / Electronic Lock
// MODULE NAME : project2
///////////////////////////////////////////////////////
module project2(clock, switches, buttons, leds, cathods, anodes);
input clock;
input [6:0] switches;
input [3:0] buttons;
output reg [7:0] leds = 8'b00000000;
output reg [7:0] cathods;
output reg [3:0] anodes;
// Variables to Maintain the clock count
integer count = 0;
integer myCount = 0;
// Player 1 => 0
// Player 2 => 1
integer player = 1'b0;
// Find if default message has tl be shown to the players
integer defaultMessage = 1'b1;
// tempn represents the 'nth' Anode in 7-Segement display
integer temp3 = 8'b11111111;
integer temp2 = 8'b11111111;
integer temp1 = 8'b11111111;
integer temp0 = 8'b11111111;
// Initialized all the 7-Segment displays to show no value
// To keep the backup of the numbers Player 1 entered
integer backupValue0 = 0;
integer backupValue1 = 0;
integer backupValue2 = 0;
integer backupValue3 = 0;
// To keep record of the numbers existing player entered
integer finalValue0 = 0;
integer finalValue1 = 0;
integer finalValue2 = 0;
integer finalValue3 = 0;
integer pressed = 1'b0;
integer checking = 0;
integer flag = 0;
integer attempts = 0;
integer flag_attempts = 1'b1;
always @(posedge clock)
begin
if(checking != 0)
begin
flag = 1;
end
else
begin
flag = 0;
end
if(switches[6] == 1)
begin
if(flag_attempts == switches[6])
begin
attempts = attempts + switches[6];
flag_attempts = 1'b0;
end
end
if(flag == 1)
begin
if(checking == 1)
begin
// Winning Code - Led Blink
if(myCount < 10000000)
begin
leds = 8'b11111111;
end
else if(myCount < 20000000)
begin
leds = 8'b00000000;
end
else
begin
myCount = 0;
end
myCount = myCount + 1;
// Display Number of Attempts
temp3 = 8'b11111111;
temp2 = 8'b11111111;
temp1 = 8'b11111111;
// ASSUMPTION: There are no more than 15 Attempts
case(attempts)
4'h0: temp0 = 8'b11000000;
4'h1: temp0 = 8'b11111001;
4'h2: temp0 = 8'b10100100;
4'h3: temp0 = 8'b10110000;
4'h4: temp0 = 8'b10011001;
4'h5: temp0 = 8'b10010010;
4'h6: temp0 = 8'b10000010;
4'h7: temp0 = 8'b11111000;
4'h8: temp0 = 8'b10000000;
4'h9: temp0 = 8'b10010000;
4'hA: temp0 = 8'b10001000;
4'hb: temp0 = 8'b10000011;
4'hC: temp0 = 8'b11000110;
4'hd: temp0 = 8'b10100001;
4'hE: temp0 = 8'b10000110;
4'hF: temp0 = 8'b10001110;
default: temp0 = 8'b11000000;
endcase
end
else if(checking == 2)
begin
// Guessed LOW
// Set the 7 - Segments to " 2LO"
temp3 = 8'b11111111;
temp2 = 8'b10100100;
temp1 = 8'b11000111;
temp0 = 8'b11000000;
end
else
begin
// Guessed HIGH
// Set the 7 - Segments t0 " 2HI"
temp3 = 8'b11111111;
temp2 = 8'b10100100;
temp1 = 8'b10001001;
temp0 = 8'b11001111;
end
if(switches[5] == 0 && switches[4] == 1 && checking != 1)
begin
// To give Player2 another chance to
// guess correct number
defaultMessage = 0;
checking = 0;
flag_attempts = 1'b1;
end
if(switches[5] == 0 && switches[4] == 0 && checking == 1)
begin
// To start a new game
// Reset Everything
defaultMessage = 1;
checking = 0;
attempts = 0;
flag_attempts = 1'b1;
count = 0;
myCount = 0;
pressed = 0;
player = 0;
leds = 0;
temp0 = 8'b10111111;
temp1 = 8'b10111111;
temp2 = 8'b10111111;
temp3 = 8'b10111111;
backupValue0 = 0;
backupValue1 = 0;
backupValue2 = 0;
backupValue3 = 0;
finalValue0 = 0;
finalValue1 = 0;
finalValue2 = 0;
finalValue3 = 0;
end
end
else
begin
if(switches[5] == 1 && player == 1)
begin
// If Player 2 guesses the correct value
if(finalValue0 == backupValue0 && finalValue1 == backupValue1 &&
finalValue2 == backupValue2 && finalValue3 == backupValue3)
begin
checking = 1;
end
else if((backupValue0 > finalValue0) ||
(backupValue0 == finalValue0 &&
backupValue1 > finalValue1) ||
(backupValue0 == finalValue0 &&
backupValue1 == finalValue1 &&
backupValue2 > finalValue2) ||
(backupValue0 == finalValue0 &&
backupValue1 == finalValue1 &&
backupValue2 == finalValue2 &&
backupValue3 > finalValue3)
)
begin
// LOW Guess
checking = 2;
end
else
begin
// HIGH Guess
checking = 3;
end
end
if(switches[4] != player)
begin
backupValue0 = finalValue0;
backupValue1 = finalValue1;
backupValue2 = finalValue2;
backupValue3 = finalValue3;
finalValue0 = 0;
finalValue1 = 0;
finalValue2 = 0;
finalValue3 = 0;
defaultMessage = 1;
end
// Default Messages which Player selected
if(defaultMessage == 1)
begin
temp3 = 8'b10001100;
temp2 = 8'b11000111;
temp1 = 8'b11111111;
if(switches[4] == 1'b0)
begin
// If switch 4 is in low position
// Set to player 1
player = 0;
temp0 = 8'b11111001;
end
else
begin
// Else set player 2
player = 1;
temp0 = 8'b10100100;
end
end
if(switches[3:0] != 0)
begin
// When first time we make the changes to the sliders
if(defaultMessage == 1)
begin
// Don't show the default message now
defaultMessage = 0;
// Set the 7-Segements to display just 0
temp0 = 8'b11000000;
temp1 = 8'b11000000;
temp2 = 8'b11000000;
temp3 = 8'b11000000;
end
else
begin
if(pressed == 0)
begin
pressed = 1;
case(switches[3:0])
4'h1:
finalValue0 = finalValue0 + buttons[3:0];
4'h2:
finalValue1 = finalValue1 + buttons[3:0];
4'h4:
finalValue2 = finalValue2 + buttons[3:0];
4'h8:
finalValue3 = finalValue3 + buttons[3:0];
endcase
end
else
begin
if(buttons[3:0] == 0)
begin
pressed = 0;
end
end
end
if(finalValue0 > 15)
begin
finalValue0 = 0;
end
if(finalValue1 > 15)
begin
finalValue1 = 0;
end
if(finalValue2 > 15)
begin
finalValue2 = 0;
end
if(finalValue3 > 15)
begin
finalValue3 = 0;
end
case(finalValue0)
4'h0: temp0 = 8'b11000000;
4'h1: temp0 = 8'b11111001;
4'h2: temp0 = 8'b10100100;
4'h3: temp0 = 8'b10110000;
4'h4: temp0 = 8'b10011001;
4'h5: temp0 = 8'b10010010;
4'h6: temp0 = 8'b10000010;
4'h7: temp0 = 8'b11111000;
4'h8: temp0 = 8'b10000000;
4'h9: temp0 = 8'b10010000;
4'hA: temp0 = 8'b10001000;
4'hb: temp0 = 8'b10000011;
4'hC: temp0 = 8'b11000110;
4'hd: temp0 = 8'b10100001;
4'hE: temp0 = 8'b10000110;
4'hF: temp0 = 8'b10001110;
default: temp0 = 8'b11000000;
endcase
case(finalValue1)
4'h0: temp1 = 8'b11000000;
4'h1: temp1 = 8'b11111001;
4'h2: temp1 = 8'b10100100;
4'h3: temp1 = 8'b10110000;
4'h4: temp1 = 8'b10011001;
4'h5: temp1 = 8'b10010010;
4'h6: temp1 = 8'b10000010;
4'h7: temp1 = 8'b11111000;
4'h8: temp1 = 8'b10000000;
4'h9: temp1 = 8'b10010000;
4'hA: temp1 = 8'b10001000;
4'hb: temp1 = 8'b10000011;
4'hC: temp1 = 8'b11000110;
4'hd: temp1 = 8'b10100001;
4'hE: temp1 = 8'b10000110;
4'hF: temp1 = 8'b10001110;
default: temp1 = 8'b11000000;
endcase
case(finalValue2)
4'h0: temp2 = 8'b11000000;
4'h1: temp2 = 8'b11111001;
4'h2: temp2 = 8'b10100100;
4'h3: temp2 = 8'b10110000;
4'h4: temp2 = 8'b10011001;
4'h5: temp2 = 8'b10010010;
4'h6: temp2 = 8'b10000010;
4'h7: temp2 = 8'b11111000;
4'h8: temp2 = 8'b10000000;
4'h9: temp2 = 8'b10010000;
4'hA: temp2 = 8'b10001000;
4'hb: temp2 = 8'b10000011;
4'hC: temp2 = 8'b11000110;
4'hd: temp2 = 8'b10100001;
4'hE: temp2 = 8'b10000110;
4'hF: temp2 = 8'b10001110;
default: temp2 = 8'b11000000;
endcase
case(finalValue3)
4'h0: temp3 = 8'b11000000;
4'h1: temp3 = 8'b11111001;
4'h2: temp3 = 8'b10100100;
4'h3: temp3 = 8'b10110000;
4'h4: temp3 = 8'b10011001;
4'h5: temp3 = 8'b10010010;
4'h6: temp3 = 8'b10000010;
4'h7: temp3 = 8'b11111000;
4'h8: temp3 = 8'b10000000;
4'h9: temp3 = 8'b10010000;
4'hA: temp3 = 8'b10001000;
4'hb: temp3 = 8'b10000011;
4'hC: temp3 = 8'b11000110;
4'hd: temp3 = 8'b10100001;
4'hE: temp3 = 8'b10000110;
4'hF: temp3 = 8'b10001110;
default: temp3 = 8'b11000000;
endcase
end
end
// Strobing
if(count <= 1500)
begin
anodes = 4'b0111;
cathods = temp0;
count = count + 1;
end
else if(count <= 3000)
begin
anodes = 4'b1011;
cathods = temp1;
count = count + 1;
end
else if(count <= 4500)
begin
anodes = 4'b1101;
cathods = temp2;
count = count + 1;
end
else if(count <= 6000)
begin
anodes = 4'b1110;
cathods = temp3;
count = count + 1;
end
else
begin
count = 0;
end
end
endmodule
// EOF |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_4_V
`define SKY130_FD_SC_LP__A21O_4_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_4_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module combines two video streams by overlaying one onto the *
* other using alpha blending. The foreground image must include alpha *
* bits to be used in the blending formula: Cn = (1 - a)Cb + (a)Cf *
* Cn - new color *
* a - alpha *
* Cb - background colour *
* Cf - foreground colour *
* *
******************************************************************************/
module soc_system_vga_alpha (
// Inputs
clk,
reset,
background_data,
background_startofpacket,
background_endofpacket,
background_empty,
background_valid,
foreground_data,
foreground_startofpacket,
foreground_endofpacket,
foreground_empty,
foreground_valid,
output_ready,
// Bidirectionals
// Outputs
background_ready,
foreground_ready,
output_data,
output_startofpacket,
output_endofpacket,
output_empty,
output_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [29: 0] background_data;
input background_startofpacket;
input background_endofpacket;
input [ 1: 0] background_empty;
input background_valid;
input [39: 0] foreground_data;
input foreground_startofpacket;
input foreground_endofpacket;
input [ 1: 0] foreground_empty;
input foreground_valid;
input output_ready;
// Bidirectionals
// Outputs
output background_ready;
output foreground_ready;
output [29: 0] output_data;
output output_startofpacket;
output output_endofpacket;
output [ 1: 0] output_empty;
output output_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] new_red;
wire [ 9: 0] new_green;
wire [ 9: 0] new_blue;
wire sync_foreground;
wire sync_background;
wire valid;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign background_ready = (output_ready & output_valid) | sync_background;
assign foreground_ready = (output_ready & output_valid) | sync_foreground;
assign output_data = {new_red, new_green, new_blue};
assign output_startofpacket = foreground_startofpacket;
assign output_endofpacket = foreground_endofpacket;
assign output_empty = 2'h0;
assign output_valid = valid;
// Internal Assignments
assign sync_foreground = (foreground_valid & background_valid &
((background_startofpacket & ~foreground_startofpacket) |
(background_endofpacket & ~foreground_endofpacket)));
assign sync_background = (foreground_valid & background_valid &
((foreground_startofpacket & ~background_startofpacket) |
(foreground_endofpacket & ~background_endofpacket)));
assign valid = foreground_valid & background_valid &
~sync_foreground & ~sync_background;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_alpha_blender_simple alpha_blender (
// Inputs
.background_data (background_data),
.foreground_data (foreground_data),
// Bidirectionals
// Outputs
.new_red (new_red),
.new_green (new_green),
.new_blue (new_blue)
);
endmodule
|
/******************************************************************************/
/* FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** Comparator *****/
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** Sorter cell emitting multiple values at once *****/
/**************************************************************************************************/
module SCELL #(parameter SORTW = 32,
parameter M_LOG = 2)
(input wire CLK,
input wire RST,
input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [(SORTW<<M_LOG)-1:0] din1,
input wire [(SORTW<<M_LOG)-1:0] din2,
input wire full,
output wire [(SORTW<<M_LOG)-1:0] dout,
output wire enq);
function [(SORTW<<M_LOG)-1:0] mux;
input [(SORTW<<M_LOG)-1:0] a;
input [(SORTW<<M_LOG)-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire cmp = (din1[SORTW-1:0] < din2[SORTW-1:0]);
wire [(SORTW<<M_LOG)-1:0] cmp_dout = mux(din2, din1, cmp);
wire F_enq;
wire F_deq;
wire F_emp;
wire F_full;
wire [(SORTW<<M_LOG)-1:0] F_dot;
MRE2 #(1,(SORTW<<M_LOG)) F(.CLK(CLK), .RST(RST), .enq(F_enq), .deq(F_deq),
.din(cmp_dout), .dot(F_dot), .emp(F_emp), .full(F_full));
assign F_enq = &{~F_full,valid1,valid2}; // assign F_enq = (!F_full && valid1 && valid2);
assign F_deq = ~|{full,F_emp}; // assign F_deq = !full && !F_emp;
reg [(SORTW<<M_LOG)-1:0] fbdata;
reg [(SORTW<<M_LOG)-1:0] fbdata_a; // duplicated register
reg [(SORTW<<M_LOG)-1:0] fbdata_b; // duplicated register
reg fbinvoke;
assign enq = (F_deq && fbinvoke);
assign deq1 = (F_enq && cmp);
assign deq2 = (F_enq && !cmp);
localparam P_DATAWIDTH = 32;
wire [P_DATAWIDTH-1:0] a, b, c, d, e, f, g, h;
wire [P_DATAWIDTH-1:0] e_a, f_a, g_a, h_a; // for duplicated register
wire [P_DATAWIDTH-1:0] e_b, f_b, g_b, h_b; // for duplicated register
assign a = F_dot[ 31: 0];
assign b = F_dot[ 63:32];
assign c = F_dot[ 95:64];
assign d = F_dot[127:96];
assign e = fbdata[ 31: 0];
assign f = fbdata[ 63:32];
assign g = fbdata[ 95:64];
assign h = fbdata[127:96];
assign e_a = fbdata_a[ 31: 0];
assign f_a = fbdata_a[ 63:32];
assign g_a = fbdata_a[ 95:64];
assign h_a = fbdata_a[127:96];
assign e_b = fbdata_b[ 31: 0];
assign f_b = fbdata_b[ 63:32];
assign g_b = fbdata_b[ 95:64];
assign h_b = fbdata_b[127:96];
wire t0_c0 = (a < h);
wire t0_c1 = (b < g);
wire t0_c2 = (c < f);
wire t0_c3 = (d < e);
wire t0_x0 = t0_c0 ^ t0_c1;
wire t0_x1 = t0_c2 ^ t0_c3;
wire t0 = t0_x0 ^ t0_x1;
wire s2_c0 = (b < e);
wire s2_c1 = (a < f);
wire s3_c0 = (c < h);
wire s3_c1 = (d < g);
wire s4_c0 = (a < g);
wire s4_c1 = (b < f);
wire s4_c2 = (c < e);
wire s5_c0 = (d < f);
wire s5_c1 = (c < g);
wire s5_c2 = (b < h);
wire s0 = (a < e);
wire s1 = (d < h);
wire [1:0] s2 = {s0, (s2_c0 ^ s2_c1)};
wire [1:0] s3 = {s1, (s3_c0 ^ s3_c1)};
wire [2:0] s4 = {s2, (s4_c0 ^ s4_c1 ^ s4_c2)};
wire [2:0] s5 = {s3, (s5_c0 ^ s5_c1 ^ s5_c2)};
wire [3:0] s6 = {s4, t0};
wire [3:0] s7 = {s5, t0};
wire [P_DATAWIDTH-1:0] m0, m1, m2, m3, m4, m5, m6, m7;
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [32-1:0] mux4in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [1:0] sel;
begin
case (sel)
2'b00: mux4in32 = a;
2'b01: mux4in32 = b;
2'b10: mux4in32 = c;
2'b11: mux4in32 = d;
endcase
end
endfunction
function [32-1:0] mux6in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [2:0] sel;
begin
casex (sel)
3'b000: mux6in32 = a;
3'b001: mux6in32 = b;
3'b100: mux6in32 = c;
3'b101: mux6in32 = d;
3'bx10: mux6in32 = e;
3'bx11: mux6in32 = f;
endcase
end
endfunction
function [32-1:0] mux12in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [32-1:0] g;
input [32-1:0] h;
input [32-1:0] i;
input [32-1:0] j;
input [32-1:0] k;
input [32-1:0] l;
input [3:0] sel;
begin
casex (sel)
4'b0000: mux12in32 = a;
4'b0001: mux12in32 = b;
4'b0010: mux12in32 = c;
4'b0011: mux12in32 = d;
4'b1000: mux12in32 = e;
4'b1001: mux12in32 = f;
4'b1010: mux12in32 = g;
4'b1011: mux12in32 = h;
4'bx100: mux12in32 = i;
4'bx101: mux12in32 = j;
4'bx110: mux12in32 = k;
4'bx111: mux12in32 = l;
endcase
end
endfunction
assign m0 = mux32(e, a, s0);
assign m1 = mux32(d, h, s1);
assign m2 = mux4in32(f, a, b, e, s2);
assign m3 = mux4in32(c, h, g, d, s3);
assign m4 = mux6in32(g, a, e, c, b, f, s4);
assign m5 = mux6in32(b, h, d, f, g, c, s5);
// using duplicated registers
assign m6 = mux12in32(h_a, a, b, g_a, f_a, c, d, e_a, f_a, c, b, g_a, s6);
assign m7 = mux12in32(a, h_b, g_b, b, c, f_b, e_b, d, c, f_b, g_b, b, s7);
// output and feedback
//////////////////////////////////////////////////////////
assign dout = {m6,m4,m2,m0}; // output
always @(posedge CLK) begin // feedback
if (RST) begin
fbdata <= 0;
fbdata_a <= 0;
fbdata_b <= 0;
fbinvoke <= 0;
end else begin
if (F_deq) begin
fbdata <= {m1,m3,m5,m7};
fbdata_a <= {m1,m3,m5,m7};
fbdata_b <= {m1,m3,m5,m7};
fbinvoke <= 1;
end
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire rx_wait,
output wire [`MERGW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg [1:0] im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
(* mark_debug = "true" *) wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den;
wire im_deq = (req && !im_emp);
assign rx_wait = im_cnt[`IB_SIZE-1];
always @(posedge CLK) im_req <= (im_cnt==0) ? 3 : (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/ // todo
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`MERGW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [1:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`MERGW-1:0] mux;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[`MERGW-1:0], dot[`MERGW-1:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==3)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==2)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {`MERGW'b0, dot_t[`DRAMW-1:`MERGW]};
2'b11: dot_t <= {`MERGW'b0, dot[`DRAMW-1:`MERGW]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`MERGW-1:0] din, // data in
output wire [`MERGW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`MERGW-1:0] mux128;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux128 = a;
1'b1: mux128 = b;
endcase
end
endfunction
/*****************************************/
wire [`MERGW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`MERGW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux128(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 4;
if (ecnt==4 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`MERGW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`MERGW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07;
assign {d00, d01, d02, d03, d04, d05, d06, d07} = s_din;
// wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15;
// assign {d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [`MERGW-1:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [`MERGW-1:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [`MERGW-1:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [`MERGW-1:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [`MERGW-1:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [`MERGW-1:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [`MERGW-1:0] F07_din, F07_dot; wire [1:0] F07_cnt;
wire F08_enq, F08_deq, F08_emp, F08_full; wire [`MERGW-1:0] F08_din, F08_dot; wire [1:0] F08_cnt;
wire F09_enq, F09_deq, F09_emp, F09_full; wire [`MERGW-1:0] F09_din, F09_dot; wire [1:0] F09_cnt;
wire F10_enq, F10_deq, F10_emp, F10_full; wire [`MERGW-1:0] F10_din, F10_dot; wire [1:0] F10_cnt;
wire F11_enq, F11_deq, F11_emp, F11_full; wire [`MERGW-1:0] F11_din, F11_dot; wire [1:0] F11_cnt;
wire F12_enq, F12_deq, F12_emp, F12_full; wire [`MERGW-1:0] F12_din, F12_dot; wire [1:0] F12_cnt;
wire F13_enq, F13_deq, F13_emp, F13_full; wire [`MERGW-1:0] F13_din, F13_dot; wire [1:0] F13_cnt;
wire F14_enq, F14_deq, F14_emp, F14_full; wire [`MERGW-1:0] F14_din, F14_dot; wire [1:0] F14_cnt;
wire F15_enq, F15_deq, F15_emp, F15_full; wire [`MERGW-1:0] F15_din, F15_dot; wire [1:0] F15_cnt;
// wire F01_enq, F01_deq, F01_emp, F01_full; wire [`MERGW-1:0] F01_din, F01_dot; wire [1:0] F01_cnt;
// wire F02_enq, F02_deq, F02_emp, F02_full; wire [`MERGW-1:0] F02_din, F02_dot; wire [1:0] F02_cnt;
// wire F03_enq, F03_deq, F03_emp, F03_full; wire [`MERGW-1:0] F03_din, F03_dot; wire [1:0] F03_cnt;
// wire F04_enq, F04_deq, F04_emp, F04_full; wire [`MERGW-1:0] F04_din, F04_dot; wire [1:0] F04_cnt;
// wire F05_enq, F05_deq, F05_emp, F05_full; wire [`MERGW-1:0] F05_din, F05_dot; wire [1:0] F05_cnt;
// wire F06_enq, F06_deq, F06_emp, F06_full; wire [`MERGW-1:0] F06_din, F06_dot; wire [1:0] F06_cnt;
// wire F07_enq, F07_deq, F07_emp, F07_full; wire [`MERGW-1:0] F07_din, F07_dot; wire [1:0] F07_cnt;
// wire F08_enq, F08_deq, F08_emp, F08_full; wire [`MERGW-1:0] F08_din, F08_dot; wire [1:0] F08_cnt;
// wire F09_enq, F09_deq, F09_emp, F09_full; wire [`MERGW-1:0] F09_din, F09_dot; wire [1:0] F09_cnt;
// wire F10_enq, F10_deq, F10_emp, F10_full; wire [`MERGW-1:0] F10_din, F10_dot; wire [1:0] F10_cnt;
// wire F11_enq, F11_deq, F11_emp, F11_full; wire [`MERGW-1:0] F11_din, F11_dot; wire [1:0] F11_cnt;
// wire F12_enq, F12_deq, F12_emp, F12_full; wire [`MERGW-1:0] F12_din, F12_dot; wire [1:0] F12_cnt;
// wire F13_enq, F13_deq, F13_emp, F13_full; wire [`MERGW-1:0] F13_din, F13_dot; wire [1:0] F13_cnt;
// wire F14_enq, F14_deq, F14_emp, F14_full; wire [`MERGW-1:0] F14_din, F14_dot; wire [1:0] F14_cnt;
// wire F15_enq, F15_deq, F15_emp, F15_full; wire [`MERGW-1:0] F15_din, F15_dot; wire [1:0] F15_cnt;
// wire F16_enq, F16_deq, F16_emp, F16_full; wire [`MERGW-1:0] F16_din, F16_dot; wire [1:0] F16_cnt;
// wire F17_enq, F17_deq, F17_emp, F17_full; wire [`MERGW-1:0] F17_din, F17_dot; wire [1:0] F17_cnt;
// wire F18_enq, F18_deq, F18_emp, F18_full; wire [`MERGW-1:0] F18_din, F18_dot; wire [1:0] F18_cnt;
// wire F19_enq, F19_deq, F19_emp, F19_full; wire [`MERGW-1:0] F19_din, F19_dot; wire [1:0] F19_cnt;
// wire F20_enq, F20_deq, F20_emp, F20_full; wire [`MERGW-1:0] F20_din, F20_dot; wire [1:0] F20_cnt;
// wire F21_enq, F21_deq, F21_emp, F21_full; wire [`MERGW-1:0] F21_din, F21_dot; wire [1:0] F21_cnt;
// wire F22_enq, F22_deq, F22_emp, F22_full; wire [`MERGW-1:0] F22_din, F22_dot; wire [1:0] F22_cnt;
// wire F23_enq, F23_deq, F23_emp, F23_full; wire [`MERGW-1:0] F23_din, F23_dot; wire [1:0] F23_cnt;
// wire F24_enq, F24_deq, F24_emp, F24_full; wire [`MERGW-1:0] F24_din, F24_dot; wire [1:0] F24_cnt;
// wire F25_enq, F25_deq, F25_emp, F25_full; wire [`MERGW-1:0] F25_din, F25_dot; wire [1:0] F25_cnt;
// wire F26_enq, F26_deq, F26_emp, F26_full; wire [`MERGW-1:0] F26_din, F26_dot; wire [1:0] F26_cnt;
// wire F27_enq, F27_deq, F27_emp, F27_full; wire [`MERGW-1:0] F27_din, F27_dot; wire [1:0] F27_cnt;
// wire F28_enq, F28_deq, F28_emp, F28_full; wire [`MERGW-1:0] F28_din, F28_dot; wire [1:0] F28_cnt;
// wire F29_enq, F29_deq, F29_emp, F29_full; wire [`MERGW-1:0] F29_din, F29_dot; wire [1:0] F29_cnt;
// wire F30_enq, F30_deq, F30_emp, F30_full; wire [`MERGW-1:0] F30_din, F30_dot; wire [1:0] F30_cnt;
// wire F31_enq, F31_deq, F31_emp, F31_full; wire [`MERGW-1:0] F31_din, F31_dot; wire [1:0] F31_cnt;
INBUF IN08(CLK, RST, full[0], F08_full, F08_enq, d00, F08_din, enq[0], phase, irst);
INBUF IN09(CLK, RST, full[1], F09_full, F09_enq, d01, F09_din, enq[1], phase, irst);
INBUF IN10(CLK, RST, full[2], F10_full, F10_enq, d02, F10_din, enq[2], phase, irst);
INBUF IN11(CLK, RST, full[3], F11_full, F11_enq, d03, F11_din, enq[3], phase, irst);
INBUF IN12(CLK, RST, full[4], F12_full, F12_enq, d04, F12_din, enq[4], phase, irst);
INBUF IN13(CLK, RST, full[5], F13_full, F13_enq, d05, F13_din, enq[5], phase, irst);
INBUF IN14(CLK, RST, full[6], F14_full, F14_enq, d06, F14_din, enq[6], phase, irst);
INBUF IN15(CLK, RST, full[7], F15_full, F15_enq, d07, F15_din, enq[7], phase, irst);
// INBUF IN16(CLK, RST, full[0], F16_full, F16_enq, d00, F16_din, enq[0], phase, irst);
// INBUF IN17(CLK, RST, full[1], F17_full, F17_enq, d01, F17_din, enq[1], phase, irst);
// INBUF IN18(CLK, RST, full[2], F18_full, F18_enq, d02, F18_din, enq[2], phase, irst);
// INBUF IN19(CLK, RST, full[3], F19_full, F19_enq, d03, F19_din, enq[3], phase, irst);
// INBUF IN20(CLK, RST, full[4], F20_full, F20_enq, d04, F20_din, enq[4], phase, irst);
// INBUF IN21(CLK, RST, full[5], F21_full, F21_enq, d05, F21_din, enq[5], phase, irst);
// INBUF IN22(CLK, RST, full[6], F22_full, F22_enq, d06, F22_din, enq[6], phase, irst);
// INBUF IN23(CLK, RST, full[7], F23_full, F23_enq, d07, F23_din, enq[7], phase, irst);
// INBUF IN24(CLK, RST, full[8], F24_full, F24_enq, d08, F24_din, enq[8], phase, irst);
// INBUF IN25(CLK, RST, full[9], F25_full, F25_enq, d09, F25_din, enq[9], phase, irst);
// INBUF IN26(CLK, RST, full[10], F26_full, F26_enq, d10, F26_din, enq[10], phase, irst);
// INBUF IN27(CLK, RST, full[11], F27_full, F27_enq, d11, F27_din, enq[11], phase, irst);
// INBUF IN28(CLK, RST, full[12], F28_full, F28_enq, d12, F28_din, enq[12], phase, irst);
// INBUF IN29(CLK, RST, full[13], F29_full, F29_enq, d13, F29_din, enq[13], phase, irst);
// INBUF IN30(CLK, RST, full[14], F30_full, F30_enq, d14, F30_din, enq[14], phase, irst);
// INBUF IN31(CLK, RST, full[15], F31_full, F31_enq, d15, F31_din, enq[15], phase, irst);
MRE2 #(1, `MERGW) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1, `MERGW) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1, `MERGW) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1, `MERGW) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1, `MERGW) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1, `MERGW) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1, `MERGW) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
MRE2 #(1, `MERGW) F08(CLK, frst, F08_enq, F08_deq, F08_din, F08_dot, F08_emp, F08_full, F08_cnt);
MRE2 #(1, `MERGW) F09(CLK, frst, F09_enq, F09_deq, F09_din, F09_dot, F09_emp, F09_full, F09_cnt);
MRE2 #(1, `MERGW) F10(CLK, frst, F10_enq, F10_deq, F10_din, F10_dot, F10_emp, F10_full, F10_cnt);
MRE2 #(1, `MERGW) F11(CLK, frst, F11_enq, F11_deq, F11_din, F11_dot, F11_emp, F11_full, F11_cnt);
MRE2 #(1, `MERGW) F12(CLK, frst, F12_enq, F12_deq, F12_din, F12_dot, F12_emp, F12_full, F12_cnt);
MRE2 #(1, `MERGW) F13(CLK, frst, F13_enq, F13_deq, F13_din, F13_dot, F13_emp, F13_full, F13_cnt);
MRE2 #(1, `MERGW) F14(CLK, frst, F14_enq, F14_deq, F14_din, F14_dot, F14_emp, F14_full, F14_cnt);
MRE2 #(1, `MERGW) F15(CLK, frst, F15_enq, F15_deq, F15_din, F15_dot, F15_emp, F15_full, F15_cnt);
// MRE2 #(1, `MERGW) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
// MRE2 #(1, `MERGW) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
// MRE2 #(1, `MERGW) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
// MRE2 #(1, `MERGW) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
// MRE2 #(1, `MERGW) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
// MRE2 #(1, `MERGW) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
// MRE2 #(1, `MERGW) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
// MRE2 #(1, `MERGW) F08(CLK, frst, F08_enq, F08_deq, F08_din, F08_dot, F08_emp, F08_full, F08_cnt);
// MRE2 #(1, `MERGW) F09(CLK, frst, F09_enq, F09_deq, F09_din, F09_dot, F09_emp, F09_full, F09_cnt);
// MRE2 #(1, `MERGW) F10(CLK, frst, F10_enq, F10_deq, F10_din, F10_dot, F10_emp, F10_full, F10_cnt);
// MRE2 #(1, `MERGW) F11(CLK, frst, F11_enq, F11_deq, F11_din, F11_dot, F11_emp, F11_full, F11_cnt);
// MRE2 #(1, `MERGW) F12(CLK, frst, F12_enq, F12_deq, F12_din, F12_dot, F12_emp, F12_full, F12_cnt);
// MRE2 #(1, `MERGW) F13(CLK, frst, F13_enq, F13_deq, F13_din, F13_dot, F13_emp, F13_full, F13_cnt);
// MRE2 #(1, `MERGW) F14(CLK, frst, F14_enq, F14_deq, F14_din, F14_dot, F14_emp, F14_full, F14_cnt);
// MRE2 #(1, `MERGW) F15(CLK, frst, F15_enq, F15_deq, F15_din, F15_dot, F15_emp, F15_full, F15_cnt);
// MRE2 #(1, `MERGW) F16(CLK, frst, F16_enq, F16_deq, F16_din, F16_dot, F16_emp, F16_full, F16_cnt);
// MRE2 #(1, `MERGW) F17(CLK, frst, F17_enq, F17_deq, F17_din, F17_dot, F17_emp, F17_full, F17_cnt);
// MRE2 #(1, `MERGW) F18(CLK, frst, F18_enq, F18_deq, F18_din, F18_dot, F18_emp, F18_full, F18_cnt);
// MRE2 #(1, `MERGW) F19(CLK, frst, F19_enq, F19_deq, F19_din, F19_dot, F19_emp, F19_full, F19_cnt);
// MRE2 #(1, `MERGW) F20(CLK, frst, F20_enq, F20_deq, F20_din, F20_dot, F20_emp, F20_full, F20_cnt);
// MRE2 #(1, `MERGW) F21(CLK, frst, F21_enq, F21_deq, F21_din, F21_dot, F21_emp, F21_full, F21_cnt);
// MRE2 #(1, `MERGW) F22(CLK, frst, F22_enq, F22_deq, F22_din, F22_dot, F22_emp, F22_full, F22_cnt);
// MRE2 #(1, `MERGW) F23(CLK, frst, F23_enq, F23_deq, F23_din, F23_dot, F23_emp, F23_full, F23_cnt);
// MRE2 #(1, `MERGW) F24(CLK, frst, F24_enq, F24_deq, F24_din, F24_dot, F24_emp, F24_full, F24_cnt);
// MRE2 #(1, `MERGW) F25(CLK, frst, F25_enq, F25_deq, F25_din, F25_dot, F25_emp, F25_full, F25_cnt);
// MRE2 #(1, `MERGW) F26(CLK, frst, F26_enq, F26_deq, F26_din, F26_dot, F26_emp, F26_full, F26_cnt);
// MRE2 #(1, `MERGW) F27(CLK, frst, F27_enq, F27_deq, F27_din, F27_dot, F27_emp, F27_full, F27_cnt);
// MRE2 #(1, `MERGW) F28(CLK, frst, F28_enq, F28_deq, F28_din, F28_dot, F28_emp, F28_full, F28_cnt);
// MRE2 #(1, `MERGW) F29(CLK, frst, F29_enq, F29_deq, F29_din, F29_dot, F29_emp, F29_full, F29_cnt);
// MRE2 #(1, `MERGW) F30(CLK, frst, F30_enq, F30_deq, F30_din, F30_dot, F30_emp, F30_full, F30_cnt);
// MRE2 #(1, `MERGW) F31(CLK, frst, F31_enq, F31_deq, F31_din, F31_dot, F31_emp, F31_full, F31_cnt);
SCELL #(`SORTW, `M_LOG) S01(CLK, frst, !F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL #(`SORTW, `M_LOG) S02(CLK, frst, !F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL #(`SORTW, `M_LOG) S03(CLK, frst, !F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
SCELL #(`SORTW, `M_LOG) S04(CLK, frst, !F08_emp, !F09_emp, F08_deq, F09_deq, F08_dot, F09_dot, F04_full, F04_din, F04_enq);
SCELL #(`SORTW, `M_LOG) S05(CLK, frst, !F10_emp, !F11_emp, F10_deq, F11_deq, F10_dot, F11_dot, F05_full, F05_din, F05_enq);
SCELL #(`SORTW, `M_LOG) S06(CLK, frst, !F12_emp, !F13_emp, F12_deq, F13_deq, F12_dot, F13_dot, F06_full, F06_din, F06_enq);
SCELL #(`SORTW, `M_LOG) S07(CLK, frst, !F14_emp, !F15_emp, F14_deq, F15_deq, F14_dot, F15_dot, F07_full, F07_din, F07_enq);
// SCELL #(`SORTW, `M_LOG) S01(CLK, frst, !F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
// SCELL #(`SORTW, `M_LOG) S02(CLK, frst, !F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
// SCELL #(`SORTW, `M_LOG) S03(CLK, frst, !F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
// SCELL #(`SORTW, `M_LOG) S04(CLK, frst, !F08_emp, !F09_emp, F08_deq, F09_deq, F08_dot, F09_dot, F04_full, F04_din, F04_enq);
// SCELL #(`SORTW, `M_LOG) S05(CLK, frst, !F10_emp, !F11_emp, F10_deq, F11_deq, F10_dot, F11_dot, F05_full, F05_din, F05_enq);
// SCELL #(`SORTW, `M_LOG) S06(CLK, frst, !F12_emp, !F13_emp, F12_deq, F13_deq, F12_dot, F13_dot, F06_full, F06_din, F06_enq);
// SCELL #(`SORTW, `M_LOG) S07(CLK, frst, !F14_emp, !F15_emp, F14_deq, F15_deq, F14_dot, F15_dot, F07_full, F07_din, F07_enq);
// SCELL #(`SORTW, `M_LOG) S08(CLK, frst, !F16_emp, !F17_emp, F16_deq, F17_deq, F16_dot, F17_dot, F08_full, F08_din, F08_enq);
// SCELL #(`SORTW, `M_LOG) S09(CLK, frst, !F18_emp, !F19_emp, F18_deq, F19_deq, F18_dot, F19_dot, F09_full, F09_din, F09_enq);
// SCELL #(`SORTW, `M_LOG) S10(CLK, frst, !F20_emp, !F21_emp, F20_deq, F21_deq, F20_dot, F21_dot, F10_full, F10_din, F10_enq);
// SCELL #(`SORTW, `M_LOG) S11(CLK, frst, !F22_emp, !F23_emp, F22_deq, F23_deq, F22_dot, F23_dot, F11_full, F11_din, F11_enq);
// SCELL #(`SORTW, `M_LOG) S12(CLK, frst, !F24_emp, !F25_emp, F24_deq, F25_deq, F24_dot, F25_dot, F12_full, F12_din, F12_enq);
// SCELL #(`SORTW, `M_LOG) S13(CLK, frst, !F26_emp, !F27_emp, F26_deq, F27_deq, F26_dot, F27_dot, F13_full, F13_din, F13_enq);
// SCELL #(`SORTW, `M_LOG) S14(CLK, frst, !F28_emp, !F29_emp, F28_deq, F29_deq, F28_dot, F29_dot, F14_full, F14_din, F14_enq);
// SCELL #(`SORTW, `M_LOG) S15(CLK, frst, !F30_emp, !F31_emp, F30_deq, F31_deq, F30_dot, F31_dot, F15_full, F15_din, F15_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`MERGW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [1:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 3);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule
/***** Sorting Network *****/
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester B for data
reg pcB; // pipeline regester B for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester C for data
reg pcC; // pipeline regester C for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester D for data
reg pcD; // pipeline regester D for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester E for data
reg pcE; // pipeline regester E for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester F for data
reg pcF; // pipeline regester F for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester G for data
reg pcG; // pipeline regester G for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester H for data
reg pcH; // pipeline regester H for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester I for data
reg pcI; // pipeline regester I for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** An SRL-based FIFO *****/
/******************************************************************************/
module SRL_FIFO #(parameter FIFO_SIZE = 4, // size in log scale, 4 for 16 entry
parameter FIFO_WIDTH = 64) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
input wire [`DRAMW-1:0] rx_data,
input wire rx_data_valid,
output wire rx_wait,
input wire chnl_tx_data_ren,
input wire chnl_tx_data_valid,
output wire [`MERGW-1:0] rslt,
output wire rslt_ready);
function [1-1:0] mux1;
input [1-1:0] a;
input [1-1:0] b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORT_WAY-1:0] mux_sortway;
input [`SORT_WAY-1:0] a;
input [`SORT_WAY-1:0] b;
input sel;
begin
case (sel)
1'b0: mux_sortway = a;
1'b1: mux_sortway = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
/**********************************************************************************************/
wire [`DRAMW-1:0] OB_dot;
wire OB_req;
wire OB_full;
assign d_din = OB_dot;
reg [`DRAMW-1:0] dout_ta;
reg [`DRAMW-1:0] dout_tb;
reg [`DRAMW-1:0] dout_tc;
reg [`DRAMW-1:0] dout_td;
reg [`DRAMW-1:0] dout_te;
reg [`DRAMW-1:0] dout_tf;
reg doen_ta;
reg doen_tb; //
reg doen_tc; //
reg doen_td; //
reg doen_te; //
reg doen_tf; //
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
(* mark_debug = "true" *) reg [`SORT_WAY-1:0] req_t; //
reg [`SORT_WAY-1:0] req_ta; //
reg [`SORT_WAY-1:0] req_tb; //
reg [`SORT_WAY-1:0] req_pzero;
wire [`SORT_WAY-1:0] im_req;
wire [`SORT_WAY-1:0] rxw;
reg [31:0] elem; // sorted elements in a phase
(* mark_debug = "true" *) reg [`PHASE_W] phase; //
reg pchange; // phase_change to reset some registers
reg iter_done; //
reg [31:0] ecnt; // sorted elements in an iteration
reg irst; // INBUF reset
reg frst; // sort-tree FIFO reset
reg phase_zero;
reg last_phase;
reg RST;
always @(posedge CLK) RST <= RST_IN;
/**********************************************************************************************/
wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07;
wire [1:0] ib00_req, ib01_req, ib02_req, ib03_req, ib04_req, ib05_req, ib06_req, ib07_req;
// wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15;
// wire [1:0] ib00_req, ib01_req, ib02_req, ib03_req, ib04_req, ib05_req, ib06_req, ib07_req, ib08_req, ib09_req, ib10_req, ib11_req, ib12_req, ib13_req, ib14_req, ib15_req;
(* mark_debug = "true" *) wire rsltbuf_enq;
(* mark_debug = "true" *) wire rsltbuf_deq;
wire rsltbuf_emp;
wire rsltbuf_ful;
(* mark_debug = "true" *) wire [4:0] rsltbuf_cnt;
wire F01_emp;
wire F01_deq = mux1((~|{F01_emp,OB_full}), (~|{F01_emp,rsltbuf_ful}), last_phase);
(* mark_debug = "true" *) wire [`MERGW-1:0] F01_dot;
wire [`MERGW*`SORT_WAY-1:0] s_din = {d00, d01, d02, d03, d04, d05, d06, d07};
// wire [`MERGW*`SORT_WAY-1:0] s_din = {d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15};
wire [`SORT_WAY-1:0] enq;
wire [`SORT_WAY-1:0] s_ful;
wire [`DRAMW-1:0] stnet_dout;
wire stnet_douten;
SORTINGNETWORK sortingnetwork(CLK, RST, rx_data_valid, rx_data, stnet_dout, stnet_douten);
always @(posedge CLK) begin
if (RST) req_pzero <= 1;
else if (doen_tc) req_pzero <= {req_pzero[`SORT_WAY-2:0],req_pzero[`SORT_WAY-1]};
end
assign im_req = mux_sortway(req_tb, req_pzero, phase_zero);
INMOD2 im00(CLK, RST, dout_tc, doen_tc & im_req[0], s_ful[0], rxw[0], d00, enq[0], ib00_req);
INMOD2 im01(CLK, RST, dout_tc, doen_tc & im_req[1], s_ful[1], rxw[1], d01, enq[1], ib01_req);
INMOD2 im02(CLK, RST, dout_td, doen_td & im_req[2], s_ful[2], rxw[2], d02, enq[2], ib02_req);
INMOD2 im03(CLK, RST, dout_td, doen_td & im_req[3], s_ful[3], rxw[3], d03, enq[3], ib03_req);
INMOD2 im04(CLK, RST, dout_te, doen_te & im_req[4], s_ful[4], rxw[4], d04, enq[4], ib04_req);
INMOD2 im05(CLK, RST, dout_te, doen_te & im_req[5], s_ful[5], rxw[5], d05, enq[5], ib05_req);
INMOD2 im06(CLK, RST, dout_tf, doen_tf & im_req[6], s_ful[6], rxw[6], d06, enq[6], ib06_req);
INMOD2 im07(CLK, RST, dout_tf, doen_tf & im_req[7], s_ful[7], rxw[7], d07, enq[7], ib07_req);
// INMOD2 im00(CLK, RST, dout_tc, doen_tc & im_req[0], s_ful[0], rxw[0], d00, enq[0], ib00_req);
// INMOD2 im01(CLK, RST, dout_tc, doen_tc & im_req[1], s_ful[1], rxw[1], d01, enq[1], ib01_req);
// INMOD2 im02(CLK, RST, dout_tc, doen_tc & im_req[2], s_ful[2], rxw[2], d02, enq[2], ib02_req);
// INMOD2 im03(CLK, RST, dout_tc, doen_tc & im_req[3], s_ful[3], rxw[3], d03, enq[3], ib03_req);
// INMOD2 im04(CLK, RST, dout_td, doen_td & im_req[4], s_ful[4], rxw[4], d04, enq[4], ib04_req);
// INMOD2 im05(CLK, RST, dout_td, doen_td & im_req[5], s_ful[5], rxw[5], d05, enq[5], ib05_req);
// INMOD2 im06(CLK, RST, dout_td, doen_td & im_req[6], s_ful[6], rxw[6], d06, enq[6], ib06_req);
// INMOD2 im07(CLK, RST, dout_td, doen_td & im_req[7], s_ful[7], rxw[7], d07, enq[7], ib07_req);
// INMOD2 im08(CLK, RST, dout_te, doen_te & im_req[8], s_ful[8], rxw[8], d08, enq[8], ib08_req);
// INMOD2 im09(CLK, RST, dout_te, doen_te & im_req[9], s_ful[9], rxw[9], d09, enq[9], ib09_req);
// INMOD2 im10(CLK, RST, dout_te, doen_te & im_req[10], s_ful[10], rxw[10], d10, enq[10], ib10_req);
// INMOD2 im11(CLK, RST, dout_te, doen_te & im_req[11], s_ful[11], rxw[11], d11, enq[11], ib11_req);
// INMOD2 im12(CLK, RST, dout_tf, doen_tf & im_req[12], s_ful[12], rxw[12], d12, enq[12], ib12_req);
// INMOD2 im13(CLK, RST, dout_tf, doen_tf & im_req[13], s_ful[13], rxw[13], d13, enq[13], ib13_req);
// INMOD2 im14(CLK, RST, dout_tf, doen_tf & im_req[14], s_ful[14], rxw[14], d14, enq[14], ib14_req);
// INMOD2 im15(CLK, RST, dout_tf, doen_tf & im_req[15], s_ful[15], rxw[15], d15, enq[15], ib15_req);
assign rx_wait = |rxw;
STREE stree(CLK, RST, irst, frst, phase, s_din, enq, s_ful, F01_deq, F01_dot, F01_emp);
wire OB_deq = d_w;
OTMOD ob(CLK, RST, (!last_phase && F01_deq), F01_dot, OB_deq, OB_dot, OB_full, OB_req);
assign rsltbuf_enq = last_phase && F01_deq;
assign rsltbuf_deq = chnl_tx_data_ren && chnl_tx_data_valid;
SRL_FIFO #(4, `MERGW) rsltbuf(CLK, RST, rsltbuf_enq, rsltbuf_deq, F01_dot,
rslt, rsltbuf_emp, rsltbuf_ful, rsltbuf_cnt);
assign rslt_ready = !rsltbuf_emp;
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
reg [31:0] w_addr; //
reg [2:0] state; // state
reg [31:0] radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h;
reg c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h; // counter is full ?
// reg [31:0] radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h, radr_i, radr_j, radr_k, radr_l, radr_m, radr_n, radr_o, radr_p;
// (* mark_debug = "true" *) reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h, cnt_i, cnt_j, cnt_k, cnt_l, cnt_m, cnt_n, cnt_o, cnt_p;
// reg c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h, c_i, c_j, c_k, c_l, c_m, c_n, c_o, c_p; // counter is full ?
always @(posedge CLK) begin
if (RST || pchange) begin
if (RST) state <= 0;
if (RST) {d_req, d_initadr, d_blocks} <= 0;
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, phase[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
radr_e <= ((`SELM_PER_WAY>>3)*4);
radr_f <= ((`SELM_PER_WAY>>3)*5);
radr_g <= ((`SELM_PER_WAY>>3)*6);
radr_h <= ((`SELM_PER_WAY>>3)*7);
{cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h} <= 0;
{c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h} <= 0;
// w_addr <= mux32((`SORT_ELM>>1), 0, phase[0]);
// radr_a <= ((`SELM_PER_WAY>>3)*0);
// radr_b <= ((`SELM_PER_WAY>>3)*1);
// radr_c <= ((`SELM_PER_WAY>>3)*2);
// radr_d <= ((`SELM_PER_WAY>>3)*3);
// radr_e <= ((`SELM_PER_WAY>>3)*4);
// radr_f <= ((`SELM_PER_WAY>>3)*5);
// radr_g <= ((`SELM_PER_WAY>>3)*6);
// radr_h <= ((`SELM_PER_WAY>>3)*7);
// radr_i <= ((`SELM_PER_WAY>>3)*8);
// radr_j <= ((`SELM_PER_WAY>>3)*9);
// radr_k <= ((`SELM_PER_WAY>>3)*10);
// radr_l <= ((`SELM_PER_WAY>>3)*11);
// radr_m <= ((`SELM_PER_WAY>>3)*12);
// radr_n <= ((`SELM_PER_WAY>>3)*13);
// radr_o <= ((`SELM_PER_WAY>>3)*14);
// radr_p <= ((`SELM_PER_WAY>>3)*15);
// {cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h, cnt_i, cnt_j, cnt_k, cnt_l, cnt_m, cnt_n, cnt_o, cnt_p} <= 0;
// {c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h, c_i, c_j, c_k, c_l, c_m, c_n, c_o, c_p} <= 0;
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
state <= !(phase_zero);
if (d_req != 0) d_req <= 0;
else if (!d_busy) begin
if (OB_req) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr; //
w_addr <= w_addr + (`D_WS); // address for the next write
end
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req[1] && !c_a) begin req<=8'h01; state<=3; end // first priority
else if (ib01_req[1] && !c_b) begin req<=8'h02; state<=3; end //
else if (ib02_req[1] && !c_c) begin req<=8'h04; state<=3; end //
else if (ib03_req[1] && !c_d) begin req<=8'h08; state<=3; end //
else if (ib04_req[1] && !c_e) begin req<=8'h10; state<=3; end //
else if (ib05_req[1] && !c_f) begin req<=8'h20; state<=3; end //
else if (ib06_req[1] && !c_g) begin req<=8'h40; state<=3; end //
else if (ib07_req[1] && !c_h) begin req<=8'h80; state<=3; end //
else state<=2;
// if (ib00_req[1] && !c_a) begin req<=16'h0001; state<=3; end // first priority
// else if (ib01_req[1] && !c_b) begin req<=16'h0002; state<=3; end //
// else if (ib02_req[1] && !c_c) begin req<=16'h0004; state<=3; end //
// else if (ib03_req[1] && !c_d) begin req<=16'h0008; state<=3; end //
// else if (ib04_req[1] && !c_e) begin req<=16'h0010; state<=3; end //
// else if (ib05_req[1] && !c_f) begin req<=16'h0020; state<=3; end //
// else if (ib06_req[1] && !c_g) begin req<=16'h0040; state<=3; end //
// else if (ib07_req[1] && !c_h) begin req<=16'h0080; state<=3; end //
// else if (ib08_req[1] && !c_i) begin req<=16'h0100; state<=3; end //
// else if (ib09_req[1] && !c_j) begin req<=16'h0200; state<=3; end //
// else if (ib10_req[1] && !c_k) begin req<=16'h0400; state<=3; end //
// else if (ib11_req[1] && !c_l) begin req<=16'h0800; state<=3; end //
// else if (ib12_req[1] && !c_m) begin req<=16'h1000; state<=3; end //
// else if (ib13_req[1] && !c_n) begin req<=16'h2000; state<=3; end //
// else if (ib14_req[1] && !c_o) begin req<=16'h4000; state<=3; end //
// else if (ib15_req[1] && !c_p) begin req<=16'h8000; state<=3; end //
// else state<=2;
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req[0] && !c_a) begin req<=8'h01; state<=3; end // second priority
else if (ib01_req[0] && !c_b) begin req<=8'h02; state<=3; end //
else if (ib02_req[0] && !c_c) begin req<=8'h04; state<=3; end //
else if (ib03_req[0] && !c_d) begin req<=8'h08; state<=3; end //
else if (ib04_req[0] && !c_e) begin req<=8'h10; state<=3; end //
else if (ib05_req[0] && !c_f) begin req<=8'h20; state<=3; end //
else if (ib06_req[0] && !c_g) begin req<=8'h40; state<=3; end //
else if (ib07_req[0] && !c_h) begin req<=8'h80; state<=3; end //
else if (OB_req) begin state<=4; end // WRITE
// if (ib00_req[0] && !c_a) begin req<=16'h0001; state<=3; end // second priority
// else if (ib01_req[0] && !c_b) begin req<=16'h0002; state<=3; end //
// else if (ib02_req[0] && !c_c) begin req<=16'h0004; state<=3; end //
// else if (ib03_req[0] && !c_d) begin req<=16'h0008; state<=3; end //
// else if (ib04_req[0] && !c_e) begin req<=16'h0010; state<=3; end //
// else if (ib05_req[0] && !c_f) begin req<=16'h0020; state<=3; end //
// else if (ib06_req[0] && !c_g) begin req<=16'h0040; state<=3; end //
// else if (ib07_req[0] && !c_h) begin req<=16'h0080; state<=3; end //
// else if (ib08_req[0] && !c_i) begin req<=16'h0100; state<=3; end //
// else if (ib09_req[0] && !c_j) begin req<=16'h0200; state<=3; end //
// else if (ib10_req[0] && !c_k) begin req<=16'h0400; state<=3; end //
// else if (ib11_req[0] && !c_l) begin req<=16'h0800; state<=3; end //
// else if (ib12_req[0] && !c_m) begin req<=16'h1000; state<=3; end //
// else if (ib13_req[0] && !c_n) begin req<=16'h2000; state<=3; end //
// else if (ib14_req[0] && !c_o) begin req<=16'h4000; state<=3; end //
// else if (ib15_req[0] && !c_p) begin req<=16'h8000; state<=3; end //
// else if (OB_req) begin state<=4; end // WRITE
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
case (req)
8'h01: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase[0]);
radr_a <= radr_a+(`D_RS);
cnt_a <= cnt_a+1;
c_a <= (cnt_a>=`WAY_CN_);
end
8'h02: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase[0]);
radr_b <= radr_b+(`D_RS);
cnt_b <= cnt_b+1;
c_b <= (cnt_b>=`WAY_CN_);
end
8'h04: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase[0]);
radr_c <= radr_c+(`D_RS);
cnt_c <= cnt_c+1;
c_c <= (cnt_c>=`WAY_CN_);
end
8'h08: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase[0]);
radr_d <= radr_d+(`D_RS);
cnt_d <= cnt_d+1;
c_d <= (cnt_d>=`WAY_CN_);
end
8'h10: begin
d_initadr <= mux32(radr_e, (radr_e | (`SORT_ELM>>1)), phase[0]);
radr_e <= radr_e+(`D_RS);
cnt_e <= cnt_e+1;
c_e <= (cnt_e>=`WAY_CN_);
end
8'h20: begin
d_initadr <= mux32(radr_f, (radr_f | (`SORT_ELM>>1)), phase[0]);
radr_f <= radr_f+(`D_RS);
cnt_f <= cnt_f+1;
c_f <= (cnt_f>=`WAY_CN_);
end
8'h40: begin
d_initadr <= mux32(radr_g, (radr_g | (`SORT_ELM>>1)), phase[0]);
radr_g <= radr_g+(`D_RS);
cnt_g <= cnt_g+1;
c_g <= (cnt_g>=`WAY_CN_);
end
8'h80: begin
d_initadr <= mux32(radr_h, (radr_h | (`SORT_ELM>>1)), phase[0]);
radr_h <= radr_h+(`D_RS);
cnt_h <= cnt_h+1;
c_h <= (cnt_h>=`WAY_CN_);
end
endcase
// case (req)
// 16'h0001: begin
// d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase[0]);
// radr_a <= radr_a+(`D_RS);
// cnt_a <= cnt_a+1;
// c_a <= (cnt_a>=`WAY_CN_);
// end
// 16'h0002: begin
// d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase[0]);
// radr_b <= radr_b+(`D_RS);
// cnt_b <= cnt_b+1;
// c_b <= (cnt_b>=`WAY_CN_);
// end
// 16'h0004: begin
// d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase[0]);
// radr_c <= radr_c+(`D_RS);
// cnt_c <= cnt_c+1;
// c_c <= (cnt_c>=`WAY_CN_);
// end
// 16'h0008: begin
// d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase[0]);
// radr_d <= radr_d+(`D_RS);
// cnt_d <= cnt_d+1;
// c_d <= (cnt_d>=`WAY_CN_);
// end
// 16'h0010: begin
// d_initadr <= mux32(radr_e, (radr_e | (`SORT_ELM>>1)), phase[0]);
// radr_e <= radr_e+(`D_RS);
// cnt_e <= cnt_e+1;
// c_e <= (cnt_e>=`WAY_CN_);
// end
// 16'h0020: begin
// d_initadr <= mux32(radr_f, (radr_f | (`SORT_ELM>>1)), phase[0]);
// radr_f <= radr_f+(`D_RS);
// cnt_f <= cnt_f+1;
// c_f <= (cnt_f>=`WAY_CN_);
// end
// 16'h0040: begin
// d_initadr <= mux32(radr_g, (radr_g | (`SORT_ELM>>1)), phase[0]);
// radr_g <= radr_g+(`D_RS);
// cnt_g <= cnt_g+1;
// c_g <= (cnt_g>=`WAY_CN_);
// end
// 16'h0080: begin
// d_initadr <= mux32(radr_h, (radr_h | (`SORT_ELM>>1)), phase[0]);
// radr_h <= radr_h+(`D_RS);
// cnt_h <= cnt_h+1;
// c_h <= (cnt_h>=`WAY_CN_);
// end
// 16'h0100: begin
// d_initadr <= mux32(radr_i, (radr_i | (`SORT_ELM>>1)), phase[0]);
// radr_i <= radr_i+(`D_RS);
// cnt_i <= cnt_i+1;
// c_i <= (cnt_i>=`WAY_CN_);
// end
// 16'h0200: begin
// d_initadr <= mux32(radr_j, (radr_j | (`SORT_ELM>>1)), phase[0]);
// radr_j <= radr_j+(`D_RS);
// cnt_j <= cnt_j+1;
// c_j <= (cnt_j>=`WAY_CN_);
// end
// 16'h0400: begin
// d_initadr <= mux32(radr_k, (radr_k | (`SORT_ELM>>1)), phase[0]);
// radr_k <= radr_k+(`D_RS);
// cnt_k <= cnt_k+1;
// c_k <= (cnt_k>=`WAY_CN_);
// end
// 16'h0800: begin
// d_initadr <= mux32(radr_l, (radr_l | (`SORT_ELM>>1)), phase[0]);
// radr_l <= radr_l+(`D_RS);
// cnt_l <= cnt_l+1;
// c_l <= (cnt_l>=`WAY_CN_);
// end
// 16'h1000: begin
// d_initadr <= mux32(radr_m, (radr_m | (`SORT_ELM>>1)), phase[0]);
// radr_m <= radr_m+(`D_RS);
// cnt_m <= cnt_m+1;
// c_m <= (cnt_m>=`WAY_CN_);
// end
// 16'h2000: begin
// d_initadr <= mux32(radr_n, (radr_n | (`SORT_ELM>>1)), phase[0]);
// radr_n <= radr_n+(`D_RS);
// cnt_n <= cnt_n+1;
// c_n <= (cnt_n>=`WAY_CN_);
// end
// 16'h4000: begin
// d_initadr <= mux32(radr_o, (radr_o | (`SORT_ELM>>1)), phase[0]);
// radr_o <= radr_o+(`D_RS);
// cnt_o <= cnt_o+1;
// c_o <= (cnt_o>=`WAY_CN_);
// end
// 16'h8000: begin
// d_initadr <= mux32(radr_p, (radr_p | (`SORT_ELM>>1)), phase[0]);
// radr_p <= radr_p+(`D_RS);
// cnt_p <= cnt_p+1;
// c_p <= (cnt_p>=`WAY_CN_);
// end
// endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_t <= req;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr; //
w_addr <= w_addr + (`D_WS); // address for the next write
end
end
////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
/**********************************************************************************************/
always @(posedge CLK) begin
// Stage 0
////////////////////////////////////
dout_ta <= mux512(d_dout, stnet_dout, phase_zero);
dout_tb <= mux512(d_dout, stnet_dout, phase_zero);
doen_ta <= mux1(d_douten, stnet_douten, phase_zero);
doen_tb <= mux1(d_douten, stnet_douten, phase_zero);
req_ta <= req_t;
// Stage 1
////////////////////////////////////
dout_tc <= dout_ta;
dout_td <= dout_ta;
dout_te <= dout_tb;
dout_tf <= dout_tb;
doen_tc <= doen_ta;
doen_td <= doen_ta;
doen_te <= doen_tb;
doen_tf <= doen_tb;
req_tb <= req_ta;
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RST) begin
phase <= 0;
end else begin
if (elem==`SORT_ELM) phase <= phase + 1;
end
end
// for elem
// ###########################################################################
always @(posedge CLK) begin
if (RST) begin
elem <= 0;
end else begin
case ({OB_deq, (elem==`SORT_ELM)})
2'b01: elem <= 0;
2'b10: elem <= elem + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done <= (ecnt==8);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange <= (elem==`SORT_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst <= (ecnt==8) || pchange;
// for frst
// ###########################################################################
always @(posedge CLK) frst <= RST || (ecnt==8) || (elem==`SORT_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RST || iter_done || pchange) begin
ecnt <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase * `WAY_LOG));
end else begin
if (ecnt!=0 && F01_deq) ecnt <= ecnt - 4;
end
end
// for phase zero
// ###########################################################################
always @(posedge CLK) phase_zero <= (phase == 0);
// for last phase
// ###########################################################################
always @(posedge CLK) last_phase <= (phase == `LAST_PHASE);
// for debug
// ###########################################################################
// (* mark_debug = "true" *) reg [31:0] dcnt;
// always @(posedge CLK) begin
// if (RST) begin
// dcnt <= 0;
// end else begin
// case ({F01_deq, (dcnt==`SORT_ELM)})
// 2'b01: dcnt <= 0;
// 2'b10: dcnt <= dcnt + 4;
// endcase
// end
// end
endmodule // CORE
/**************************************************************************************************/
`default_nettype wire
|
//=================================================
// ULTRASONIC RECEIVER MODULE
//=================================================
module ultrasonicReceiver # (
parameter sampler_BITS = 8,
parameter subtractor_OFFSET = 12'h7FF,
parameter FIR_BANK = 3'b000)(
// Essential signals:
input SYS_CLK,
input RST, RSTbar,
input ADC_MISO,
output ADC_MOSI,
output ADC_CSbar,
output ADC_SCK,
input TIMER_RST,
input ABS_PEAK_FLAG,
input NIOS_FIFO_RST,
input NIOS_TIMER_RST,
input NIOS_ADC_ON,
input SUBTRACTOR_ON,
input NIOS_FIFO_ADC_DATA_VALID,
input [15:0] NIOS_FIFO_ADC_DATA,
input [23:0] NIOS_THRESHOLD,
input NIOS_RD_PEAK,
output NIOS_PEAK_FOUND,
output [109:0] NIOS_YN1, NIOS_YN2, NIOS_YN3,
output [13:0] NIOS_TIME,
// Debug signals:
output FIFO_ADC_EMPTY,
output FIFO_ADC_FULL,
output [15:0] FIFO_ADC_OUTPUT,
output [12:0] FIR_INPUT
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// TIMER Module:
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [13:0] TIMER;
COUNTER COUNTER_instant (
.clock ( SYS_CLK ),
.aclr ( RST | NIOS_TIMER_RST | NIOS_FIFO_RST | TIMER_RST ),
.cnt_en ( FIFO_ADC_WR ),
.q ( TIMER )
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// ADC Module:
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Command sent to ADC:
wire [15:0] ADC_CMD = {4'b0001, 1'b1, 2'b0, 2'b00, 7'b1000000};
// Auto-sample at 68.359375 (10bits) / 273.4375 (8bits) kHz:
localparam sampler_topbit = sampler_BITS - 1;
reg [sampler_topbit:0] clk_sample;
always @(posedge SYS_CLK)
clk_sample <= ~RST & NIOS_ADC_ON ? clk_sample + 1 : 0;
wire ADC_EN = ~clk_sample[sampler_topbit] & NIOS_ADC_ON & ~RST;
wire [15:0] ADC_DATA;
wire ADC_FIN;
// ADC SPI Master Module:
SPI_MASTER_ADC #(.outBits (16)) ADC_instant(
.SYS_CLK ( SYS_CLK ),
.ENA ( ADC_EN ),
.DATA_MOSI ( ADC_CMD ), // Command written to ADC
.MISO ( ADC_MISO ), // MISO = SDO = 3
.MOSI ( ADC_MOSI ), // MOSI = SDI = 4
.SCK ( ADC_SCK ), // SCK = SCLK = 5
.CSbar ( ADC_CSbar ), // CSbar = CSbar = 6
.FIN ( ADC_FIN ),
.DATA_MISO ( ADC_DATA ) // Sample from ADC
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// ADC FIFO: 16-bits width, 16-words depth
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Edge Detector for WR sinal to FIFO:
reg FIFO_ADC_WR, FIFO_ADC_WR_PREV;
wire FIFO_ADC_WR_SIGNAL;
assign FIFO_ADC_WR_SIGNAL = (ADC_FIN & NIOS_ADC_ON) | (NIOS_FIFO_ADC_DATA_VALID & ~NIOS_ADC_ON);
always @(posedge SYS_CLK) begin
FIFO_ADC_WR_PREV <= FIFO_ADC_WR_SIGNAL;
FIFO_ADC_WR <= ~FIFO_ADC_WR_PREV & FIFO_ADC_WR_SIGNAL & ~RST;
end
wire [12:0] SUB_OUTPUT_ADC;
assign SUB_OUTPUT_ADC = ADC_DATA[11:0] - subtractor_OFFSET;
wire [12:0] SUB_OUTPUT_NIOS;
assign SUB_OUTPUT_NIOS = NIOS_FIFO_ADC_DATA[11:0] - subtractor_OFFSET;
// MUX between taking data from NIOS or ADC:
reg [15:0] FIFO_ADC_DATA;
always @(posedge SYS_CLK) begin
if (RST) begin
FIFO_ADC_DATA <= 16'b0;
end
else begin
case (NIOS_ADC_ON)
1'b1: begin // Take data from ADC Module
if (ADC_DATA[15:12] == 4'b0)
FIFO_ADC_DATA <= SUBTRACTOR_ON ? SUB_OUTPUT_ADC : ADC_DATA;
end
1'b0: begin // Take data from NIOS
FIFO_ADC_DATA <= SUBTRACTOR_ON ? SUB_OUTPUT_NIOS : NIOS_FIFO_ADC_DATA;
end
endcase
end
end
// Altera IP FIFO Module:
FIFO_ADC FIFO_ADC_instant (
.clock ( SYS_CLK ),
.sclr ( RST | NIOS_FIFO_RST ), // Synchronous Clear
`ifdef VERIFY_FIFO_ADC_MANUAL
.rdreq ( MANUAL_RD ),
`else
.rdreq ( FIFO_ADC_RD ),
`endif
.wrreq ( FIFO_ADC_WR ), // Write when a sample is ready
.data ( FIFO_ADC_DATA ),
.empty ( FIFO_ADC_EMPTY ),
.full ( FIFO_ADC_FULL ),
.q ( FIFO_ADC_OUTPUT )
);
assign FIR_INPUT[12:0] = FIFO_ADC_OUTPUT[12:0];
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// FIR FILTER: Matched Filter - 65 Taps
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`ifdef VERIFY_FIR_OUTPUT
always @(posedge SYS_CLK) begin
FIR_OUTPUT <= FIR_OUTPUT_VALID ? FIR_OUTPUT_RAW : FIR_OUTPUT;
end
`endif
localparam FIRtaps = 7'd65;
// Read ADC FIFO when data is available to pass to FIR Filter:
wire FIFO_ADC_RD;
assign FIFO_ADC_RD = ~FIFO_ADC_EMPTY & ~RST ;
wire [29:0] FIR_OUTPUT_RAW;
wire FIR_OUTPUT_VALID;
FIR FIR_instant(
.clk ( SYS_CLK ), // clk.clk
.reset_n ( RSTbar ), // rst.reset_n
.ast_sink_data ( {FIR_BANK, FIR_INPUT} ), // avalon_streaming_sink.data
.ast_sink_valid ( FIFO_ADC_RD ), // .valid
.ast_sink_error ( 2'b00 ), // .error
.ast_source_data ( FIR_OUTPUT_RAW ), // avalon_streaming_source.data
.ast_source_valid ( FIR_OUTPUT_VALID ), // .valid
.ast_source_error ( ) // .error
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// FIR FIFO: 30-bits width, 16-words depth
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire FIFO_FIR_EMPTY, FIFO_FIR_FULL;
wire [29:0] FIFO_FIR_OUTPUT;
FIFO_FIR FIFO_FIR_instant (
.clock ( SYS_CLK ),
.sclr ( RST | NIOS_FIFO_RST ),
.rdreq ( FIFO_RD_DETECTION ),
.wrreq ( FIR_OUTPUT_VALID ),
.data ( FIR_OUTPUT_RAW ),
.empty ( FIFO_FIR_EMPTY ),
.full ( FIFO_FIR_FULL ),
.q ( FIFO_FIR_OUTPUT )
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// SUM FIR INPUT SQUARED:
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [25:0] FIR_INPUT_SQ;
MULT MULT_Xsq_instant (
.dataa ( FIR_INPUT ),
.result ( FIR_INPUT_SQ )
);
wire [25:0] sumXsq_RAW;
ADDSUBWIDE ADDSUBWIDE_sumXsqRAW_instant (
.add_sub ( 1'b1 ),
.dataa ( FIR_INPUT_SQ ),
.datab ( sumXsq ),
.result ( sumXsq_RAW )
);
wire [12:0] FIR_TAP_POP;
SHIFTREGRAM SHIFTREGRAM_instant (
.clken ( FIFO_ADC_RD ),
.clock ( SYS_CLK ),
.shiftin ( FIR_INPUT ),
.shiftout ( FIR_TAP_POP ),
.taps ( )
);
wire [25:0] FIR_TAP_POPsq;
MULT MULT_XprevSq_instant (
.dataa ( FIR_TAP_POP ),
.result ( FIR_TAP_POPsq )
);
wire [25:0] sumXsq_RESULT;
ADDSUBWIDE ADDSUBWIDE_sumXsq_instant (
.add_sub ( 1'b0 ),
.dataa ( sumXsq_RAW ),
.datab ( FIR_TAP_POPsq ),
.result ( sumXsq_RESULT )
);
reg [25:0] sumXsq;
always @(negedge SYS_CLK) begin
if (RST | NIOS_FIFO_RST)
sumXsq <= 0;
else
sumXsq <= FIFO_ADC_RD ? sumXsq_RESULT : sumXsq;
end
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// SUM X SQUARED FIFO: 26-bits width, 16-words depth
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [25:0] FIFO_sumXsq_OUTPUT;
wire FIFO_sumXsq_EMPTY, FIFO_sumXsq_FULL;
FIFO_SUM_IN_SQUARED FIFO_sumXsq_instant (
.clock ( SYS_CLK ),
.sclr ( RST | NIOS_FIFO_RST ),
.rdreq ( FIFO_RD_DETECTION ),
.wrreq ( FIFO_ADC_RD ),
.data ( sumXsq ),
.empty ( FIFO_sumXsq_EMPTY ),
.full ( FIFO_sumXsq_FULL ),
.q ( FIFO_sumXsq_OUTPUT )
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DETECTION Module
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire FIFO_RD_DETECTION;
assign FIFO_RD_DETECTION = ~FIFO_FIR_EMPTY & ~FIFO_sumXsq_EMPTY;
wire [59:0] Yn_NUM;
wire [49:0] Yn_DEN;
wire DETECTION;
DETECTOR DETECTOR_instant (
.SYS_CLK ( SYS_CLK ),
.RST ( RST | NIOS_FIFO_RST ),
.TIME ( TIMER ),
.THRESHOLD ( NIOS_THRESHOLD ),
.Y ( FIFO_FIR_OUTPUT ),
.sumXsq ( FIFO_sumXsq_OUTPUT ),
.Yn_NUM ( Yn_NUM ),
.Yn_DEN ( Yn_DEN ),
.DETECTION ( DETECTION )
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// PEAK FINDER
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PEAKFINDER #(
.taps(65))
PEAKFINDER_instant (
.SYS_CLK ( SYS_CLK ),
.RST ( RST | NIOS_FIFO_RST | TIMER_RST ),
.NIOS_ADC_ON ( NIOS_ADC_ON ),
.CLK_EN ( FIFO_RD_DETECTION ),
.DETECTION ( DETECTION ),
.Yn_NUM ( Yn_NUM ),
.Yn_DEN ( Yn_DEN ),
.TIMER ( TIMER ),
.ABS_PEAK_FLAG ( ABS_PEAK_FLAG ),
.NIOS_RD_PEAK ( NIOS_RD_PEAK ),
.VALID_PEAK_FOUND ( NIOS_PEAK_FOUND ),
.FIFO_DETECTION_YN1_OUTPUT ( NIOS_YN1 ),
.FIFO_DETECTION_YN2_OUTPUT ( NIOS_YN2 ),
.FIFO_DETECTION_YN3_OUTPUT ( NIOS_YN3 ),
.FIFO_DETECTION_TIME_OUTPUT ( NIOS_TIME )
);
endmodule
//=================================================
// END ULTRASONIC RECEIVER MODULE
//=================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_4_V
`define SKY130_FD_SC_HS__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_4_V
|
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Receiver for RPC network, protocol version 3
This module expects OUT_DATA_WIDTH to be less than IN_DATA_WIDTH.
Network-side interface is standard RPCv3
Router-side interface is a FIFO.
space_available Asserted by router if it has at least one *packet* worth of buffer space.
packet_start Asserted by transceiver for one clock at start of message.
Asserted concurrently with first assertion of data_valid.
data_valid Asserted by transceiver if data should be processed.
Will be asserted constantly between packet_start and packet_done.
data One word of message data.
packet_done Asserted by transceiver for one clock at end of message.
Concurrent with last assertion of data_valid.
RESOURCE USAGE (XST A7 rough estimate)
Width FF LUT Slice
32 -> 16 40 76 43
64 -> 16 72 154 73
128 -> 16 136 104 36
64 -> 32 71 89 39
128 -> 32 134 102 49
128 -> 64 132 164 68
*/
module RPCv3RouterReceiver_collapsing
#(
//Data width (must be one of 16, 32, 64, 128).
parameter OUT_DATA_WIDTH = 16,
parameter IN_DATA_WIDTH = 32
)
(
//Interface clock
input wire clk,
//Network interface, inbound side
input wire rpc_rx_en,
input wire[IN_DATA_WIDTH-1:0] rpc_rx_data,
output reg rpc_rx_ready = 0,
//Router interface, outbound side
input wire rpc_fab_rx_space_available,
output wire rpc_fab_rx_packet_start,
output reg rpc_fab_rx_data_valid = 0,
output reg[OUT_DATA_WIDTH-1:0] rpc_fab_rx_data = 0,
output reg rpc_fab_rx_packet_done = 0
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Synthesis-time sanity checking
initial begin
case(IN_DATA_WIDTH)
32: begin
end
64: begin
end
128: begin
end
default: begin
$display("ERROR: RPCv3RouterReceiver_collapsing IN_DATA_WIDTH must be 16/32/64/128");
$finish;
end
endcase
case(OUT_DATA_WIDTH)
16: begin
end
32: begin
end
64: begin
end
default: begin
$display("ERROR: RPCv3RouterReceiver_collapsing OUT_DATA_WIDTH must be 16/32/64");
$finish;
end
endcase
if(IN_DATA_WIDTH <= OUT_DATA_WIDTH) begin
$display("ERROR: RPCv3RouterReceiver_collapsing IN_DATA_WIDTH must be greater than OUT_DATA_WIDTH");
$finish;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Compute some useful values
//Number of clocks it takes to receive a message
localparam MESSAGE_CYCLES = 128 / IN_DATA_WIDTH;
localparam MESSAGE_MAX = MESSAGE_CYCLES - 1;
//Number of clocks it takes to re-send a message
localparam OUT_CYCLES = 128 / OUT_DATA_WIDTH;
//Number of bits we need in the cycle counter
`include "../../synth_helpers/clog2.vh"
localparam CYCLE_BITS = clog2(MESSAGE_CYCLES);
localparam CYCLE_MAX = CYCLE_BITS ? CYCLE_BITS-1 : 0;
localparam OUT_CYCLE_BITS = clog2(OUT_CYCLES);
localparam OUT_CYCLE_MAX = OUT_CYCLE_BITS ? OUT_CYCLE_BITS-1 : 0;
//Calculate the collapsing ratio (number of output words per input word)
//Always 2, 4, or 8
localparam COLLAPSE_RATIO = IN_DATA_WIDTH / OUT_DATA_WIDTH;
localparam COLLAPSE_MAX = COLLAPSE_RATIO - 1;
localparam COLLAPSE_BITS = clog2(COLLAPSE_RATIO);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FIFO of data being received
wire fifo_wr;
reg fifo_rd = 0;
wire fifo_empty;
wire[IN_DATA_WIDTH-1:0] fifo_dout;
wire unused_full;
wire unused_underflow;
wire unused_overflow;
wire[CYCLE_BITS:0] unused_rsize;
wire[CYCLE_BITS:0] unused_wsize;
generate
if(IN_DATA_WIDTH < 128) begin
SingleClockShiftRegisterFifo #(
.WIDTH(IN_DATA_WIDTH),
.DEPTH(MESSAGE_CYCLES),
.OUT_REG(1)
) rx_fifo (
.clk(clk),
.wr(fifo_wr),
.din(rpc_rx_data),
.rd(fifo_rd),
.dout(fifo_dout),
.overflow(unused_overflow),
.underflow(unused_underflow),
.empty(fifo_empty),
.full(unused_full),
.rsize(unused_rsize),
.wsize(unused_wsize),
.reset(1'b0) //never reset the fifo
);
end
//Special stuff for 128-bit link width - no fifo, just a buffer
else begin
reg[127:0] fifo_data = 0;
reg fifo_valid = 0;
always @(posedge clk) begin
if(fifo_wr) begin
fifo_valid <= 1;
fifo_data <= rpc_rx_data;
end
if(fifo_rd)
fifo_valid <= 0;
end
assign fifo_dout = fifo_data;
assign fifo_empty = !fifo_valid;
end
endgenerate
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Main RX logic
//True if we are in the first cycle of an incoming message
wire rx_starting = (rpc_rx_en && rpc_rx_ready);
assign rpc_fab_rx_packet_start = rx_starting;
//Position within the message (in IN_DATA_WIDTH-bit units)
reg[2:0] rx_count = 0;
//True if a receive is in progress
wire rx_active = (rx_count != 0) || rx_starting;
assign fifo_wr = rx_active;
//True if fifo_dout contains a valid data word
reg fifo_dout_valid = 0;
//Position within the output word (in OUT_DATA_WIDTH-bit units)
reg[COLLAPSE_BITS-1:0] out_pos = 0;
//True if a transmit (to our host) is active
wire tx_active = (fifo_dout_valid || !fifo_empty);
//True if we are currently at the last word in fifo_dout
wire last_word_in_buffer = (out_pos == COLLAPSE_MAX);
//If we have data in the FIFO, and our current word is missing or done, go read another one
always @(*) begin
fifo_rd <= !fifo_empty && (!fifo_dout_valid || last_word_in_buffer);
end
//Combinatorial muxing of the output to save a bit of time
integer i;
always @(*) begin
rpc_fab_rx_data_valid <= fifo_dout_valid;
rpc_fab_rx_packet_done <= fifo_empty && last_word_in_buffer;
rpc_fab_rx_data <= 0;
for(i=0; i<COLLAPSE_RATIO; i=i+1) begin
if(i == out_pos)
rpc_fab_rx_data <= fifo_dout[OUT_DATA_WIDTH*(COLLAPSE_MAX - i) +: OUT_DATA_WIDTH];
end
end
always @(posedge clk) begin
//Update status flags as we read data from the FIFO
if(fifo_rd)
fifo_dout_valid <= 1;
//Keep track of position in the output word
if(fifo_dout_valid)
out_pos <= out_pos + 1'h1;
//Clear state on the last word
if(rpc_fab_rx_packet_done) begin
rx_count <= 0;
fifo_dout_valid <= 0;
out_pos <= 0;
end
//Process incoming data words
if(rx_active) begin
//Clear some status flags at the start of a new message
if(rx_starting) begin
out_pos <= 0;
fifo_dout_valid <= 0;
end
//Update word count as we move through the message
if(rx_starting)
rx_count <= 1;
else
rx_count <= rx_count + 1'h1;
//When we hit the end of the message, stop
if(rx_count == MESSAGE_MAX)
rx_count <= 0;
end
end
//Ready to receive if the fabric side is ready.
//Once we go ready, go un-ready when a message comes in.
reg rpc_rx_ready_ff = 0;
always @(posedge clk) begin
if(rpc_rx_en)
rpc_rx_ready_ff <= 0;
if(rpc_fab_rx_space_available && !rx_active && !tx_active)
rpc_rx_ready_ff <= 1;
end
always @(*) begin
rpc_rx_ready <= rpc_rx_ready_ff;
end
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1422916617 : 0;
endmodule
|
module fpu_rptr_groups ( inq_in1, inq_in2, inq_id, inq_op, inq_rnd_mode,
inq_in1_50_0_neq_0, inq_in1_53_0_neq_0, inq_in1_53_32_neq_0,
inq_in1_exp_eq_0, inq_in1_exp_neq_ffs, inq_in2_50_0_neq_0,
inq_in2_53_0_neq_0, inq_in2_53_32_neq_0, inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs, ctu_tst_macrotest, ctu_tst_pre_grst_l,
ctu_tst_scan_disable, ctu_tst_scanmode, ctu_tst_short_chain,
global_shift_enable, grst_l, cluster_cken, se, arst_l, fpu_grst_l,
fmul_clken_l, fdiv_clken_l, scan_manual_6, si, so_unbuf,
pcx_fpio_data_px2, pcx_fpio_data_rdy_px2, fp_cpx_req_cq,
fp_cpx_data_ca, inq_sram_din_unbuf, inq_in1_add_buf1, inq_in1_mul_buf1,
inq_in1_div_buf1, inq_in2_add_buf1, inq_in2_mul_buf1, inq_in2_div_buf1,
inq_id_add_buf1, inq_id_mul_buf1, inq_id_div_buf1, inq_op_add_buf1,
inq_op_div_buf1, inq_op_mul_buf1, inq_rnd_mode_add_buf1,
inq_rnd_mode_div_buf1, inq_rnd_mode_mul_buf1,
inq_in1_50_0_neq_0_add_buf1, inq_in1_50_0_neq_0_mul_buf1,
inq_in1_50_0_neq_0_div_buf1, inq_in1_53_0_neq_0_add_buf1,
inq_in1_53_0_neq_0_mul_buf1, inq_in1_53_0_neq_0_div_buf1,
inq_in1_53_32_neq_0_add_buf1, inq_in1_53_32_neq_0_mul_buf1,
inq_in1_53_32_neq_0_div_buf1, inq_in1_exp_eq_0_add_buf1,
inq_in1_exp_eq_0_mul_buf1, inq_in1_exp_eq_0_div_buf1,
inq_in1_exp_neq_ffs_add_buf1, inq_in1_exp_neq_ffs_mul_buf1,
inq_in1_exp_neq_ffs_div_buf1, inq_in2_50_0_neq_0_add_buf1,
inq_in2_50_0_neq_0_mul_buf1, inq_in2_50_0_neq_0_div_buf1,
inq_in2_53_0_neq_0_add_buf1, inq_in2_53_0_neq_0_mul_buf1,
inq_in2_53_0_neq_0_div_buf1, inq_in2_53_32_neq_0_add_buf1,
inq_in2_53_32_neq_0_mul_buf1, inq_in2_53_32_neq_0_div_buf1,
inq_in2_exp_eq_0_add_buf1, inq_in2_exp_eq_0_mul_buf1,
inq_in2_exp_eq_0_div_buf1, inq_in2_exp_neq_ffs_add_buf1,
inq_in2_exp_neq_ffs_mul_buf1, inq_in2_exp_neq_ffs_div_buf1,
ctu_tst_macrotest_buf1, ctu_tst_pre_grst_l_buf1,
ctu_tst_scan_disable_buf1, ctu_tst_scanmode_buf1,
ctu_tst_short_chain_buf1, global_shift_enable_buf1, grst_l_buf1,
cluster_cken_buf1, se_add_exp_buf2, se_add_frac_buf2, se_out_buf2,
se_mul64_buf2, se_cluster_header_buf2, se_in_buf3, se_mul_buf4,
se_div_buf5, arst_l_div_buf2, arst_l_mul_buf2,
arst_l_cluster_header_buf2, arst_l_in_buf3, arst_l_out_buf3,
arst_l_add_buf4, fpu_grst_l_mul_buf1, fpu_grst_l_in_buf2,
fpu_grst_l_add_buf3, fmul_clken_l_buf1, fdiv_clken_l_div_exp_buf1,
fdiv_clken_l_div_frac_buf1, scan_manual_6_buf1, si_buf1, so,
pcx_fpio_data_px2_buf1, pcx_fpio_data_rdy_px2_buf1, fp_cpx_req_cq_buf1,
fp_cpx_data_ca_buf1, inq_sram_din_buf1 );
input [63:0] inq_in1;
input [63:0] inq_in2;
input [4:0] inq_id;
input [7:0] inq_op;
input [1:0] inq_rnd_mode;
input [123:0] pcx_fpio_data_px2;
input [7:0] fp_cpx_req_cq;
input [144:0] fp_cpx_data_ca;
input [155:0] inq_sram_din_unbuf;
output [63:0] inq_in1_add_buf1;
output [63:0] inq_in1_mul_buf1;
output [63:0] inq_in1_div_buf1;
output [63:0] inq_in2_add_buf1;
output [63:0] inq_in2_mul_buf1;
output [63:0] inq_in2_div_buf1;
output [4:0] inq_id_add_buf1;
output [4:0] inq_id_mul_buf1;
output [4:0] inq_id_div_buf1;
output [7:0] inq_op_add_buf1;
output [7:0] inq_op_div_buf1;
output [7:0] inq_op_mul_buf1;
output [1:0] inq_rnd_mode_add_buf1;
output [1:0] inq_rnd_mode_div_buf1;
output [1:0] inq_rnd_mode_mul_buf1;
output [123:0] pcx_fpio_data_px2_buf1;
output [7:0] fp_cpx_req_cq_buf1;
output [144:0] fp_cpx_data_ca_buf1;
output [155:0] inq_sram_din_buf1;
input inq_in1_50_0_neq_0, inq_in1_53_0_neq_0, inq_in1_53_32_neq_0,
inq_in1_exp_eq_0, inq_in1_exp_neq_ffs, inq_in2_50_0_neq_0,
inq_in2_53_0_neq_0, inq_in2_53_32_neq_0, inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs, ctu_tst_macrotest, ctu_tst_pre_grst_l,
ctu_tst_scan_disable, ctu_tst_scanmode, ctu_tst_short_chain,
global_shift_enable, grst_l, cluster_cken, se, arst_l, fpu_grst_l,
fmul_clken_l, fdiv_clken_l, scan_manual_6, si, so_unbuf,
pcx_fpio_data_rdy_px2;
output inq_in1_50_0_neq_0_add_buf1, inq_in1_50_0_neq_0_mul_buf1,
inq_in1_50_0_neq_0_div_buf1, inq_in1_53_0_neq_0_add_buf1,
inq_in1_53_0_neq_0_mul_buf1, inq_in1_53_0_neq_0_div_buf1,
inq_in1_53_32_neq_0_add_buf1, inq_in1_53_32_neq_0_mul_buf1,
inq_in1_53_32_neq_0_div_buf1, inq_in1_exp_eq_0_add_buf1,
inq_in1_exp_eq_0_mul_buf1, inq_in1_exp_eq_0_div_buf1,
inq_in1_exp_neq_ffs_add_buf1, inq_in1_exp_neq_ffs_mul_buf1,
inq_in1_exp_neq_ffs_div_buf1, inq_in2_50_0_neq_0_add_buf1,
inq_in2_50_0_neq_0_mul_buf1, inq_in2_50_0_neq_0_div_buf1,
inq_in2_53_0_neq_0_add_buf1, inq_in2_53_0_neq_0_mul_buf1,
inq_in2_53_0_neq_0_div_buf1, inq_in2_53_32_neq_0_add_buf1,
inq_in2_53_32_neq_0_mul_buf1, inq_in2_53_32_neq_0_div_buf1,
inq_in2_exp_eq_0_add_buf1, inq_in2_exp_eq_0_mul_buf1,
inq_in2_exp_eq_0_div_buf1, inq_in2_exp_neq_ffs_add_buf1,
inq_in2_exp_neq_ffs_mul_buf1, inq_in2_exp_neq_ffs_div_buf1,
ctu_tst_macrotest_buf1, ctu_tst_pre_grst_l_buf1,
ctu_tst_scan_disable_buf1, ctu_tst_scanmode_buf1,
ctu_tst_short_chain_buf1, global_shift_enable_buf1, grst_l_buf1,
cluster_cken_buf1, se_add_exp_buf2, se_add_frac_buf2, se_out_buf2,
se_mul64_buf2, se_cluster_header_buf2, se_in_buf3, se_mul_buf4,
se_div_buf5, arst_l_div_buf2, arst_l_mul_buf2,
arst_l_cluster_header_buf2, arst_l_in_buf3, arst_l_out_buf3,
arst_l_add_buf4, fpu_grst_l_mul_buf1, fpu_grst_l_in_buf2,
fpu_grst_l_add_buf3, fmul_clken_l_buf1, fdiv_clken_l_div_exp_buf1,
fdiv_clken_l_div_frac_buf1, scan_manual_6_buf1, si_buf1, so,
pcx_fpio_data_rdy_px2_buf1;
wire inq_in1_50_0_neq_0_div_buf1, inq_in1_53_0_neq_0_div_buf1,
inq_in1_53_32_neq_0_div_buf1, inq_in1_exp_eq_0_div_buf1,
inq_in1_exp_neq_ffs_div_buf1, inq_in2_50_0_neq_0_div_buf1,
inq_in2_53_0_neq_0_div_buf1, inq_in2_53_32_neq_0_div_buf1,
inq_in2_exp_eq_0_div_buf1, inq_in2_exp_neq_ffs_div_buf1,
ctu_tst_macrotest_buf1, ctu_tst_pre_grst_l_buf1,
ctu_tst_scan_disable_buf1, ctu_tst_scanmode_buf1,
ctu_tst_short_chain_buf1, global_shift_enable_buf1, grst_l_buf1,
cluster_cken_buf1, se_mul64_buf2, arst_l_in_buf3, fpu_grst_l_add_buf3,
fmul_clken_l_buf1, fdiv_clken_l_div_exp_buf1, scan_manual_6_buf1,
si_buf1, so, pcx_fpio_data_rdy_px2_buf1;
assign inq_in1_mul_buf1[63] = inq_in1_div_buf1[63];
assign inq_in1_add_buf1[63] = inq_in1_div_buf1[63];
assign inq_in1_div_buf1[63] = inq_in1[63];
assign inq_in1_mul_buf1[62] = inq_in1_div_buf1[62];
assign inq_in1_add_buf1[62] = inq_in1_div_buf1[62];
assign inq_in1_div_buf1[62] = inq_in1[62];
assign inq_in1_mul_buf1[61] = inq_in1_div_buf1[61];
assign inq_in1_add_buf1[61] = inq_in1_div_buf1[61];
assign inq_in1_div_buf1[61] = inq_in1[61];
assign inq_in1_mul_buf1[60] = inq_in1_div_buf1[60];
assign inq_in1_add_buf1[60] = inq_in1_div_buf1[60];
assign inq_in1_div_buf1[60] = inq_in1[60];
assign inq_in1_mul_buf1[59] = inq_in1_div_buf1[59];
assign inq_in1_add_buf1[59] = inq_in1_div_buf1[59];
assign inq_in1_div_buf1[59] = inq_in1[59];
assign inq_in1_mul_buf1[58] = inq_in1_div_buf1[58];
assign inq_in1_add_buf1[58] = inq_in1_div_buf1[58];
assign inq_in1_div_buf1[58] = inq_in1[58];
assign inq_in1_mul_buf1[57] = inq_in1_div_buf1[57];
assign inq_in1_add_buf1[57] = inq_in1_div_buf1[57];
assign inq_in1_div_buf1[57] = inq_in1[57];
assign inq_in1_mul_buf1[56] = inq_in1_div_buf1[56];
assign inq_in1_add_buf1[56] = inq_in1_div_buf1[56];
assign inq_in1_div_buf1[56] = inq_in1[56];
assign inq_in1_mul_buf1[55] = inq_in1_div_buf1[55];
assign inq_in1_add_buf1[55] = inq_in1_div_buf1[55];
assign inq_in1_div_buf1[55] = inq_in1[55];
assign inq_in1_mul_buf1[54] = inq_in1_div_buf1[54];
assign inq_in1_add_buf1[54] = inq_in1_div_buf1[54];
assign inq_in1_div_buf1[54] = inq_in1[54];
assign inq_in1_mul_buf1[53] = inq_in1_div_buf1[53];
assign inq_in1_add_buf1[53] = inq_in1_div_buf1[53];
assign inq_in1_div_buf1[53] = inq_in1[53];
assign inq_in1_mul_buf1[52] = inq_in1_div_buf1[52];
assign inq_in1_add_buf1[52] = inq_in1_div_buf1[52];
assign inq_in1_div_buf1[52] = inq_in1[52];
assign inq_in1_mul_buf1[51] = inq_in1_div_buf1[51];
assign inq_in1_add_buf1[51] = inq_in1_div_buf1[51];
assign inq_in1_div_buf1[51] = inq_in1[51];
assign inq_in1_mul_buf1[50] = inq_in1_div_buf1[50];
assign inq_in1_add_buf1[50] = inq_in1_div_buf1[50];
assign inq_in1_div_buf1[50] = inq_in1[50];
assign inq_in1_mul_buf1[49] = inq_in1_div_buf1[49];
assign inq_in1_add_buf1[49] = inq_in1_div_buf1[49];
assign inq_in1_div_buf1[49] = inq_in1[49];
assign inq_in1_mul_buf1[48] = inq_in1_div_buf1[48];
assign inq_in1_add_buf1[48] = inq_in1_div_buf1[48];
assign inq_in1_div_buf1[48] = inq_in1[48];
assign inq_in1_mul_buf1[47] = inq_in1_div_buf1[47];
assign inq_in1_add_buf1[47] = inq_in1_div_buf1[47];
assign inq_in1_div_buf1[47] = inq_in1[47];
assign inq_in1_mul_buf1[46] = inq_in1_div_buf1[46];
assign inq_in1_add_buf1[46] = inq_in1_div_buf1[46];
assign inq_in1_div_buf1[46] = inq_in1[46];
assign inq_in1_mul_buf1[45] = inq_in1_div_buf1[45];
assign inq_in1_add_buf1[45] = inq_in1_div_buf1[45];
assign inq_in1_div_buf1[45] = inq_in1[45];
assign inq_in1_mul_buf1[44] = inq_in1_div_buf1[44];
assign inq_in1_add_buf1[44] = inq_in1_div_buf1[44];
assign inq_in1_div_buf1[44] = inq_in1[44];
assign inq_in1_mul_buf1[43] = inq_in1_div_buf1[43];
assign inq_in1_add_buf1[43] = inq_in1_div_buf1[43];
assign inq_in1_div_buf1[43] = inq_in1[43];
assign inq_in1_mul_buf1[42] = inq_in1_div_buf1[42];
assign inq_in1_add_buf1[42] = inq_in1_div_buf1[42];
assign inq_in1_div_buf1[42] = inq_in1[42];
assign inq_in1_mul_buf1[41] = inq_in1_div_buf1[41];
assign inq_in1_add_buf1[41] = inq_in1_div_buf1[41];
assign inq_in1_div_buf1[41] = inq_in1[41];
assign inq_in1_mul_buf1[40] = inq_in1_div_buf1[40];
assign inq_in1_add_buf1[40] = inq_in1_div_buf1[40];
assign inq_in1_div_buf1[40] = inq_in1[40];
assign inq_in1_mul_buf1[39] = inq_in1_div_buf1[39];
assign inq_in1_add_buf1[39] = inq_in1_div_buf1[39];
assign inq_in1_div_buf1[39] = inq_in1[39];
assign inq_in1_mul_buf1[38] = inq_in1_div_buf1[38];
assign inq_in1_add_buf1[38] = inq_in1_div_buf1[38];
assign inq_in1_div_buf1[38] = inq_in1[38];
assign inq_in1_mul_buf1[37] = inq_in1_div_buf1[37];
assign inq_in1_add_buf1[37] = inq_in1_div_buf1[37];
assign inq_in1_div_buf1[37] = inq_in1[37];
assign inq_in1_mul_buf1[36] = inq_in1_div_buf1[36];
assign inq_in1_add_buf1[36] = inq_in1_div_buf1[36];
assign inq_in1_div_buf1[36] = inq_in1[36];
assign inq_in1_mul_buf1[35] = inq_in1_div_buf1[35];
assign inq_in1_add_buf1[35] = inq_in1_div_buf1[35];
assign inq_in1_div_buf1[35] = inq_in1[35];
assign inq_in1_mul_buf1[34] = inq_in1_div_buf1[34];
assign inq_in1_add_buf1[34] = inq_in1_div_buf1[34];
assign inq_in1_div_buf1[34] = inq_in1[34];
assign inq_in1_mul_buf1[33] = inq_in1_div_buf1[33];
assign inq_in1_add_buf1[33] = inq_in1_div_buf1[33];
assign inq_in1_div_buf1[33] = inq_in1[33];
assign inq_in1_mul_buf1[32] = inq_in1_div_buf1[32];
assign inq_in1_add_buf1[32] = inq_in1_div_buf1[32];
assign inq_in1_div_buf1[32] = inq_in1[32];
assign inq_in1_mul_buf1[31] = inq_in1_div_buf1[31];
assign inq_in1_add_buf1[31] = inq_in1_div_buf1[31];
assign inq_in1_div_buf1[31] = inq_in1[31];
assign inq_in1_mul_buf1[30] = inq_in1_div_buf1[30];
assign inq_in1_add_buf1[30] = inq_in1_div_buf1[30];
assign inq_in1_div_buf1[30] = inq_in1[30];
assign inq_in1_mul_buf1[29] = inq_in1_div_buf1[29];
assign inq_in1_add_buf1[29] = inq_in1_div_buf1[29];
assign inq_in1_div_buf1[29] = inq_in1[29];
assign inq_in1_mul_buf1[28] = inq_in1_div_buf1[28];
assign inq_in1_add_buf1[28] = inq_in1_div_buf1[28];
assign inq_in1_div_buf1[28] = inq_in1[28];
assign inq_in1_mul_buf1[27] = inq_in1_div_buf1[27];
assign inq_in1_add_buf1[27] = inq_in1_div_buf1[27];
assign inq_in1_div_buf1[27] = inq_in1[27];
assign inq_in1_mul_buf1[26] = inq_in1_div_buf1[26];
assign inq_in1_add_buf1[26] = inq_in1_div_buf1[26];
assign inq_in1_div_buf1[26] = inq_in1[26];
assign inq_in1_mul_buf1[25] = inq_in1_div_buf1[25];
assign inq_in1_add_buf1[25] = inq_in1_div_buf1[25];
assign inq_in1_div_buf1[25] = inq_in1[25];
assign inq_in1_mul_buf1[24] = inq_in1_div_buf1[24];
assign inq_in1_add_buf1[24] = inq_in1_div_buf1[24];
assign inq_in1_div_buf1[24] = inq_in1[24];
assign inq_in1_mul_buf1[23] = inq_in1_div_buf1[23];
assign inq_in1_add_buf1[23] = inq_in1_div_buf1[23];
assign inq_in1_div_buf1[23] = inq_in1[23];
assign inq_in1_mul_buf1[22] = inq_in1_div_buf1[22];
assign inq_in1_add_buf1[22] = inq_in1_div_buf1[22];
assign inq_in1_div_buf1[22] = inq_in1[22];
assign inq_in1_mul_buf1[21] = inq_in1_div_buf1[21];
assign inq_in1_add_buf1[21] = inq_in1_div_buf1[21];
assign inq_in1_div_buf1[21] = inq_in1[21];
assign inq_in1_mul_buf1[20] = inq_in1_div_buf1[20];
assign inq_in1_add_buf1[20] = inq_in1_div_buf1[20];
assign inq_in1_div_buf1[20] = inq_in1[20];
assign inq_in1_mul_buf1[19] = inq_in1_div_buf1[19];
assign inq_in1_add_buf1[19] = inq_in1_div_buf1[19];
assign inq_in1_div_buf1[19] = inq_in1[19];
assign inq_in1_mul_buf1[18] = inq_in1_div_buf1[18];
assign inq_in1_add_buf1[18] = inq_in1_div_buf1[18];
assign inq_in1_div_buf1[18] = inq_in1[18];
assign inq_in1_mul_buf1[17] = inq_in1_div_buf1[17];
assign inq_in1_add_buf1[17] = inq_in1_div_buf1[17];
assign inq_in1_div_buf1[17] = inq_in1[17];
assign inq_in1_mul_buf1[16] = inq_in1_div_buf1[16];
assign inq_in1_add_buf1[16] = inq_in1_div_buf1[16];
assign inq_in1_div_buf1[16] = inq_in1[16];
assign inq_in1_mul_buf1[15] = inq_in1_div_buf1[15];
assign inq_in1_add_buf1[15] = inq_in1_div_buf1[15];
assign inq_in1_div_buf1[15] = inq_in1[15];
assign inq_in1_mul_buf1[14] = inq_in1_div_buf1[14];
assign inq_in1_add_buf1[14] = inq_in1_div_buf1[14];
assign inq_in1_div_buf1[14] = inq_in1[14];
assign inq_in1_mul_buf1[13] = inq_in1_div_buf1[13];
assign inq_in1_add_buf1[13] = inq_in1_div_buf1[13];
assign inq_in1_div_buf1[13] = inq_in1[13];
assign inq_in1_mul_buf1[12] = inq_in1_div_buf1[12];
assign inq_in1_add_buf1[12] = inq_in1_div_buf1[12];
assign inq_in1_div_buf1[12] = inq_in1[12];
assign inq_in1_mul_buf1[11] = inq_in1_div_buf1[11];
assign inq_in1_add_buf1[11] = inq_in1_div_buf1[11];
assign inq_in1_div_buf1[11] = inq_in1[11];
assign inq_in1_mul_buf1[10] = inq_in1_div_buf1[10];
assign inq_in1_add_buf1[10] = inq_in1_div_buf1[10];
assign inq_in1_div_buf1[10] = inq_in1[10];
assign inq_in1_mul_buf1[9] = inq_in1_div_buf1[9];
assign inq_in1_add_buf1[9] = inq_in1_div_buf1[9];
assign inq_in1_div_buf1[9] = inq_in1[9];
assign inq_in1_mul_buf1[8] = inq_in1_div_buf1[8];
assign inq_in1_add_buf1[8] = inq_in1_div_buf1[8];
assign inq_in1_div_buf1[8] = inq_in1[8];
assign inq_in1_mul_buf1[7] = inq_in1_div_buf1[7];
assign inq_in1_add_buf1[7] = inq_in1_div_buf1[7];
assign inq_in1_div_buf1[7] = inq_in1[7];
assign inq_in1_mul_buf1[6] = inq_in1_div_buf1[6];
assign inq_in1_add_buf1[6] = inq_in1_div_buf1[6];
assign inq_in1_div_buf1[6] = inq_in1[6];
assign inq_in1_mul_buf1[5] = inq_in1_div_buf1[5];
assign inq_in1_add_buf1[5] = inq_in1_div_buf1[5];
assign inq_in1_div_buf1[5] = inq_in1[5];
assign inq_in1_mul_buf1[4] = inq_in1_div_buf1[4];
assign inq_in1_add_buf1[4] = inq_in1_div_buf1[4];
assign inq_in1_div_buf1[4] = inq_in1[4];
assign inq_in1_mul_buf1[3] = inq_in1_div_buf1[3];
assign inq_in1_add_buf1[3] = inq_in1_div_buf1[3];
assign inq_in1_div_buf1[3] = inq_in1[3];
assign inq_in1_mul_buf1[2] = inq_in1_div_buf1[2];
assign inq_in1_add_buf1[2] = inq_in1_div_buf1[2];
assign inq_in1_div_buf1[2] = inq_in1[2];
assign inq_in1_mul_buf1[1] = inq_in1_div_buf1[1];
assign inq_in1_add_buf1[1] = inq_in1_div_buf1[1];
assign inq_in1_div_buf1[1] = inq_in1[1];
assign inq_in1_mul_buf1[0] = inq_in1_div_buf1[0];
assign inq_in1_add_buf1[0] = inq_in1_div_buf1[0];
assign inq_in1_div_buf1[0] = inq_in1[0];
assign inq_in2_mul_buf1[63] = inq_in2_div_buf1[63];
assign inq_in2_add_buf1[63] = inq_in2_div_buf1[63];
assign inq_in2_div_buf1[63] = inq_in2[63];
assign inq_in2_mul_buf1[62] = inq_in2_div_buf1[62];
assign inq_in2_add_buf1[62] = inq_in2_div_buf1[62];
assign inq_in2_div_buf1[62] = inq_in2[62];
assign inq_in2_mul_buf1[61] = inq_in2_div_buf1[61];
assign inq_in2_add_buf1[61] = inq_in2_div_buf1[61];
assign inq_in2_div_buf1[61] = inq_in2[61];
assign inq_in2_mul_buf1[60] = inq_in2_div_buf1[60];
assign inq_in2_add_buf1[60] = inq_in2_div_buf1[60];
assign inq_in2_div_buf1[60] = inq_in2[60];
assign inq_in2_mul_buf1[59] = inq_in2_div_buf1[59];
assign inq_in2_add_buf1[59] = inq_in2_div_buf1[59];
assign inq_in2_div_buf1[59] = inq_in2[59];
assign inq_in2_mul_buf1[58] = inq_in2_div_buf1[58];
assign inq_in2_add_buf1[58] = inq_in2_div_buf1[58];
assign inq_in2_div_buf1[58] = inq_in2[58];
assign inq_in2_mul_buf1[57] = inq_in2_div_buf1[57];
assign inq_in2_add_buf1[57] = inq_in2_div_buf1[57];
assign inq_in2_div_buf1[57] = inq_in2[57];
assign inq_in2_mul_buf1[56] = inq_in2_div_buf1[56];
assign inq_in2_add_buf1[56] = inq_in2_div_buf1[56];
assign inq_in2_div_buf1[56] = inq_in2[56];
assign inq_in2_mul_buf1[55] = inq_in2_div_buf1[55];
assign inq_in2_add_buf1[55] = inq_in2_div_buf1[55];
assign inq_in2_div_buf1[55] = inq_in2[55];
assign inq_in2_mul_buf1[54] = inq_in2_div_buf1[54];
assign inq_in2_add_buf1[54] = inq_in2_div_buf1[54];
assign inq_in2_div_buf1[54] = inq_in2[54];
assign inq_in2_mul_buf1[53] = inq_in2_div_buf1[53];
assign inq_in2_add_buf1[53] = inq_in2_div_buf1[53];
assign inq_in2_div_buf1[53] = inq_in2[53];
assign inq_in2_mul_buf1[52] = inq_in2_div_buf1[52];
assign inq_in2_add_buf1[52] = inq_in2_div_buf1[52];
assign inq_in2_div_buf1[52] = inq_in2[52];
assign inq_in2_mul_buf1[51] = inq_in2_div_buf1[51];
assign inq_in2_add_buf1[51] = inq_in2_div_buf1[51];
assign inq_in2_div_buf1[51] = inq_in2[51];
assign inq_in2_mul_buf1[50] = inq_in2_div_buf1[50];
assign inq_in2_add_buf1[50] = inq_in2_div_buf1[50];
assign inq_in2_div_buf1[50] = inq_in2[50];
assign inq_in2_mul_buf1[49] = inq_in2_div_buf1[49];
assign inq_in2_add_buf1[49] = inq_in2_div_buf1[49];
assign inq_in2_div_buf1[49] = inq_in2[49];
assign inq_in2_mul_buf1[48] = inq_in2_div_buf1[48];
assign inq_in2_add_buf1[48] = inq_in2_div_buf1[48];
assign inq_in2_div_buf1[48] = inq_in2[48];
assign inq_in2_mul_buf1[47] = inq_in2_div_buf1[47];
assign inq_in2_add_buf1[47] = inq_in2_div_buf1[47];
assign inq_in2_div_buf1[47] = inq_in2[47];
assign inq_in2_mul_buf1[46] = inq_in2_div_buf1[46];
assign inq_in2_add_buf1[46] = inq_in2_div_buf1[46];
assign inq_in2_div_buf1[46] = inq_in2[46];
assign inq_in2_mul_buf1[45] = inq_in2_div_buf1[45];
assign inq_in2_add_buf1[45] = inq_in2_div_buf1[45];
assign inq_in2_div_buf1[45] = inq_in2[45];
assign inq_in2_mul_buf1[44] = inq_in2_div_buf1[44];
assign inq_in2_add_buf1[44] = inq_in2_div_buf1[44];
assign inq_in2_div_buf1[44] = inq_in2[44];
assign inq_in2_mul_buf1[43] = inq_in2_div_buf1[43];
assign inq_in2_add_buf1[43] = inq_in2_div_buf1[43];
assign inq_in2_div_buf1[43] = inq_in2[43];
assign inq_in2_mul_buf1[42] = inq_in2_div_buf1[42];
assign inq_in2_add_buf1[42] = inq_in2_div_buf1[42];
assign inq_in2_div_buf1[42] = inq_in2[42];
assign inq_in2_mul_buf1[41] = inq_in2_div_buf1[41];
assign inq_in2_add_buf1[41] = inq_in2_div_buf1[41];
assign inq_in2_div_buf1[41] = inq_in2[41];
assign inq_in2_mul_buf1[40] = inq_in2_div_buf1[40];
assign inq_in2_add_buf1[40] = inq_in2_div_buf1[40];
assign inq_in2_div_buf1[40] = inq_in2[40];
assign inq_in2_mul_buf1[39] = inq_in2_div_buf1[39];
assign inq_in2_add_buf1[39] = inq_in2_div_buf1[39];
assign inq_in2_div_buf1[39] = inq_in2[39];
assign inq_in2_mul_buf1[38] = inq_in2_div_buf1[38];
assign inq_in2_add_buf1[38] = inq_in2_div_buf1[38];
assign inq_in2_div_buf1[38] = inq_in2[38];
assign inq_in2_mul_buf1[37] = inq_in2_div_buf1[37];
assign inq_in2_add_buf1[37] = inq_in2_div_buf1[37];
assign inq_in2_div_buf1[37] = inq_in2[37];
assign inq_in2_mul_buf1[36] = inq_in2_div_buf1[36];
assign inq_in2_add_buf1[36] = inq_in2_div_buf1[36];
assign inq_in2_div_buf1[36] = inq_in2[36];
assign inq_in2_mul_buf1[35] = inq_in2_div_buf1[35];
assign inq_in2_add_buf1[35] = inq_in2_div_buf1[35];
assign inq_in2_div_buf1[35] = inq_in2[35];
assign inq_in2_mul_buf1[34] = inq_in2_div_buf1[34];
assign inq_in2_add_buf1[34] = inq_in2_div_buf1[34];
assign inq_in2_div_buf1[34] = inq_in2[34];
assign inq_in2_mul_buf1[33] = inq_in2_div_buf1[33];
assign inq_in2_add_buf1[33] = inq_in2_div_buf1[33];
assign inq_in2_div_buf1[33] = inq_in2[33];
assign inq_in2_mul_buf1[32] = inq_in2_div_buf1[32];
assign inq_in2_add_buf1[32] = inq_in2_div_buf1[32];
assign inq_in2_div_buf1[32] = inq_in2[32];
assign inq_in2_mul_buf1[31] = inq_in2_div_buf1[31];
assign inq_in2_add_buf1[31] = inq_in2_div_buf1[31];
assign inq_in2_div_buf1[31] = inq_in2[31];
assign inq_in2_mul_buf1[30] = inq_in2_div_buf1[30];
assign inq_in2_add_buf1[30] = inq_in2_div_buf1[30];
assign inq_in2_div_buf1[30] = inq_in2[30];
assign inq_in2_mul_buf1[29] = inq_in2_div_buf1[29];
assign inq_in2_add_buf1[29] = inq_in2_div_buf1[29];
assign inq_in2_div_buf1[29] = inq_in2[29];
assign inq_in2_mul_buf1[28] = inq_in2_div_buf1[28];
assign inq_in2_add_buf1[28] = inq_in2_div_buf1[28];
assign inq_in2_div_buf1[28] = inq_in2[28];
assign inq_in2_mul_buf1[27] = inq_in2_div_buf1[27];
assign inq_in2_add_buf1[27] = inq_in2_div_buf1[27];
assign inq_in2_div_buf1[27] = inq_in2[27];
assign inq_in2_mul_buf1[26] = inq_in2_div_buf1[26];
assign inq_in2_add_buf1[26] = inq_in2_div_buf1[26];
assign inq_in2_div_buf1[26] = inq_in2[26];
assign inq_in2_mul_buf1[25] = inq_in2_div_buf1[25];
assign inq_in2_add_buf1[25] = inq_in2_div_buf1[25];
assign inq_in2_div_buf1[25] = inq_in2[25];
assign inq_in2_mul_buf1[24] = inq_in2_div_buf1[24];
assign inq_in2_add_buf1[24] = inq_in2_div_buf1[24];
assign inq_in2_div_buf1[24] = inq_in2[24];
assign inq_in2_mul_buf1[23] = inq_in2_div_buf1[23];
assign inq_in2_add_buf1[23] = inq_in2_div_buf1[23];
assign inq_in2_div_buf1[23] = inq_in2[23];
assign inq_in2_mul_buf1[22] = inq_in2_div_buf1[22];
assign inq_in2_add_buf1[22] = inq_in2_div_buf1[22];
assign inq_in2_div_buf1[22] = inq_in2[22];
assign inq_in2_mul_buf1[21] = inq_in2_div_buf1[21];
assign inq_in2_add_buf1[21] = inq_in2_div_buf1[21];
assign inq_in2_div_buf1[21] = inq_in2[21];
assign inq_in2_mul_buf1[20] = inq_in2_div_buf1[20];
assign inq_in2_add_buf1[20] = inq_in2_div_buf1[20];
assign inq_in2_div_buf1[20] = inq_in2[20];
assign inq_in2_mul_buf1[19] = inq_in2_div_buf1[19];
assign inq_in2_add_buf1[19] = inq_in2_div_buf1[19];
assign inq_in2_div_buf1[19] = inq_in2[19];
assign inq_in2_mul_buf1[18] = inq_in2_div_buf1[18];
assign inq_in2_add_buf1[18] = inq_in2_div_buf1[18];
assign inq_in2_div_buf1[18] = inq_in2[18];
assign inq_in2_mul_buf1[17] = inq_in2_div_buf1[17];
assign inq_in2_add_buf1[17] = inq_in2_div_buf1[17];
assign inq_in2_div_buf1[17] = inq_in2[17];
assign inq_in2_mul_buf1[16] = inq_in2_div_buf1[16];
assign inq_in2_add_buf1[16] = inq_in2_div_buf1[16];
assign inq_in2_div_buf1[16] = inq_in2[16];
assign inq_in2_mul_buf1[15] = inq_in2_div_buf1[15];
assign inq_in2_add_buf1[15] = inq_in2_div_buf1[15];
assign inq_in2_div_buf1[15] = inq_in2[15];
assign inq_in2_mul_buf1[14] = inq_in2_div_buf1[14];
assign inq_in2_add_buf1[14] = inq_in2_div_buf1[14];
assign inq_in2_div_buf1[14] = inq_in2[14];
assign inq_in2_mul_buf1[13] = inq_in2_div_buf1[13];
assign inq_in2_add_buf1[13] = inq_in2_div_buf1[13];
assign inq_in2_div_buf1[13] = inq_in2[13];
assign inq_in2_mul_buf1[12] = inq_in2_div_buf1[12];
assign inq_in2_add_buf1[12] = inq_in2_div_buf1[12];
assign inq_in2_div_buf1[12] = inq_in2[12];
assign inq_in2_mul_buf1[11] = inq_in2_div_buf1[11];
assign inq_in2_add_buf1[11] = inq_in2_div_buf1[11];
assign inq_in2_div_buf1[11] = inq_in2[11];
assign inq_in2_mul_buf1[10] = inq_in2_div_buf1[10];
assign inq_in2_add_buf1[10] = inq_in2_div_buf1[10];
assign inq_in2_div_buf1[10] = inq_in2[10];
assign inq_in2_mul_buf1[9] = inq_in2_div_buf1[9];
assign inq_in2_add_buf1[9] = inq_in2_div_buf1[9];
assign inq_in2_div_buf1[9] = inq_in2[9];
assign inq_in2_mul_buf1[8] = inq_in2_div_buf1[8];
assign inq_in2_add_buf1[8] = inq_in2_div_buf1[8];
assign inq_in2_div_buf1[8] = inq_in2[8];
assign inq_in2_mul_buf1[7] = inq_in2_div_buf1[7];
assign inq_in2_add_buf1[7] = inq_in2_div_buf1[7];
assign inq_in2_div_buf1[7] = inq_in2[7];
assign inq_in2_mul_buf1[6] = inq_in2_div_buf1[6];
assign inq_in2_add_buf1[6] = inq_in2_div_buf1[6];
assign inq_in2_div_buf1[6] = inq_in2[6];
assign inq_in2_mul_buf1[5] = inq_in2_div_buf1[5];
assign inq_in2_add_buf1[5] = inq_in2_div_buf1[5];
assign inq_in2_div_buf1[5] = inq_in2[5];
assign inq_in2_mul_buf1[4] = inq_in2_div_buf1[4];
assign inq_in2_add_buf1[4] = inq_in2_div_buf1[4];
assign inq_in2_div_buf1[4] = inq_in2[4];
assign inq_in2_mul_buf1[3] = inq_in2_div_buf1[3];
assign inq_in2_add_buf1[3] = inq_in2_div_buf1[3];
assign inq_in2_div_buf1[3] = inq_in2[3];
assign inq_in2_mul_buf1[2] = inq_in2_div_buf1[2];
assign inq_in2_add_buf1[2] = inq_in2_div_buf1[2];
assign inq_in2_div_buf1[2] = inq_in2[2];
assign inq_in2_mul_buf1[1] = inq_in2_div_buf1[1];
assign inq_in2_add_buf1[1] = inq_in2_div_buf1[1];
assign inq_in2_div_buf1[1] = inq_in2[1];
assign inq_in2_mul_buf1[0] = inq_in2_div_buf1[0];
assign inq_in2_add_buf1[0] = inq_in2_div_buf1[0];
assign inq_in2_div_buf1[0] = inq_in2[0];
assign inq_id_mul_buf1[4] = inq_id_div_buf1[4];
assign inq_id_add_buf1[4] = inq_id_div_buf1[4];
assign inq_id_div_buf1[4] = inq_id[4];
assign inq_id_mul_buf1[3] = inq_id_div_buf1[3];
assign inq_id_add_buf1[3] = inq_id_div_buf1[3];
assign inq_id_div_buf1[3] = inq_id[3];
assign inq_id_mul_buf1[2] = inq_id_div_buf1[2];
assign inq_id_add_buf1[2] = inq_id_div_buf1[2];
assign inq_id_div_buf1[2] = inq_id[2];
assign inq_id_mul_buf1[1] = inq_id_div_buf1[1];
assign inq_id_add_buf1[1] = inq_id_div_buf1[1];
assign inq_id_div_buf1[1] = inq_id[1];
assign inq_id_mul_buf1[0] = inq_id_div_buf1[0];
assign inq_id_add_buf1[0] = inq_id_div_buf1[0];
assign inq_id_div_buf1[0] = inq_id[0];
assign inq_op_mul_buf1[7] = inq_op_div_buf1[7];
assign inq_op_add_buf1[7] = inq_op_div_buf1[7];
assign inq_op_div_buf1[7] = inq_op[7];
assign inq_op_mul_buf1[6] = inq_op_div_buf1[6];
assign inq_op_add_buf1[6] = inq_op_div_buf1[6];
assign inq_op_div_buf1[6] = inq_op[6];
assign inq_op_mul_buf1[5] = inq_op_div_buf1[5];
assign inq_op_add_buf1[5] = inq_op_div_buf1[5];
assign inq_op_div_buf1[5] = inq_op[5];
assign inq_op_mul_buf1[4] = inq_op_div_buf1[4];
assign inq_op_add_buf1[4] = inq_op_div_buf1[4];
assign inq_op_div_buf1[4] = inq_op[4];
assign inq_op_mul_buf1[3] = inq_op_div_buf1[3];
assign inq_op_add_buf1[3] = inq_op_div_buf1[3];
assign inq_op_div_buf1[3] = inq_op[3];
assign inq_op_mul_buf1[2] = inq_op_div_buf1[2];
assign inq_op_add_buf1[2] = inq_op_div_buf1[2];
assign inq_op_div_buf1[2] = inq_op[2];
assign inq_op_mul_buf1[1] = inq_op_div_buf1[1];
assign inq_op_add_buf1[1] = inq_op_div_buf1[1];
assign inq_op_div_buf1[1] = inq_op[1];
assign inq_op_mul_buf1[0] = inq_op_div_buf1[0];
assign inq_op_add_buf1[0] = inq_op_div_buf1[0];
assign inq_op_div_buf1[0] = inq_op[0];
assign inq_rnd_mode_mul_buf1[1] = inq_rnd_mode_div_buf1[1];
assign inq_rnd_mode_add_buf1[1] = inq_rnd_mode_div_buf1[1];
assign inq_rnd_mode_div_buf1[1] = inq_rnd_mode[1];
assign inq_rnd_mode_mul_buf1[0] = inq_rnd_mode_div_buf1[0];
assign inq_rnd_mode_add_buf1[0] = inq_rnd_mode_div_buf1[0];
assign inq_rnd_mode_div_buf1[0] = inq_rnd_mode[0];
assign inq_in1_50_0_neq_0_mul_buf1 = inq_in1_50_0_neq_0_div_buf1;
assign inq_in1_50_0_neq_0_add_buf1 = inq_in1_50_0_neq_0_div_buf1;
assign inq_in1_50_0_neq_0_div_buf1 = inq_in1_50_0_neq_0;
assign inq_in1_53_0_neq_0_mul_buf1 = inq_in1_53_0_neq_0_div_buf1;
assign inq_in1_53_0_neq_0_add_buf1 = inq_in1_53_0_neq_0_div_buf1;
assign inq_in1_53_0_neq_0_div_buf1 = inq_in1_53_0_neq_0;
assign inq_in1_53_32_neq_0_mul_buf1 = inq_in1_53_32_neq_0_div_buf1;
assign inq_in1_53_32_neq_0_add_buf1 = inq_in1_53_32_neq_0_div_buf1;
assign inq_in1_53_32_neq_0_div_buf1 = inq_in1_53_32_neq_0;
assign inq_in1_exp_eq_0_mul_buf1 = inq_in1_exp_eq_0_div_buf1;
assign inq_in1_exp_eq_0_add_buf1 = inq_in1_exp_eq_0_div_buf1;
assign inq_in1_exp_eq_0_div_buf1 = inq_in1_exp_eq_0;
assign inq_in1_exp_neq_ffs_mul_buf1 = inq_in1_exp_neq_ffs_div_buf1;
assign inq_in1_exp_neq_ffs_add_buf1 = inq_in1_exp_neq_ffs_div_buf1;
assign inq_in1_exp_neq_ffs_div_buf1 = inq_in1_exp_neq_ffs;
assign inq_in2_50_0_neq_0_mul_buf1 = inq_in2_50_0_neq_0_div_buf1;
assign inq_in2_50_0_neq_0_add_buf1 = inq_in2_50_0_neq_0_div_buf1;
assign inq_in2_50_0_neq_0_div_buf1 = inq_in2_50_0_neq_0;
assign inq_in2_53_0_neq_0_mul_buf1 = inq_in2_53_0_neq_0_div_buf1;
assign inq_in2_53_0_neq_0_add_buf1 = inq_in2_53_0_neq_0_div_buf1;
assign inq_in2_53_0_neq_0_div_buf1 = inq_in2_53_0_neq_0;
assign inq_in2_53_32_neq_0_mul_buf1 = inq_in2_53_32_neq_0_div_buf1;
assign inq_in2_53_32_neq_0_add_buf1 = inq_in2_53_32_neq_0_div_buf1;
assign inq_in2_53_32_neq_0_div_buf1 = inq_in2_53_32_neq_0;
assign inq_in2_exp_eq_0_mul_buf1 = inq_in2_exp_eq_0_div_buf1;
assign inq_in2_exp_eq_0_add_buf1 = inq_in2_exp_eq_0_div_buf1;
assign inq_in2_exp_eq_0_div_buf1 = inq_in2_exp_eq_0;
assign inq_in2_exp_neq_ffs_mul_buf1 = inq_in2_exp_neq_ffs_div_buf1;
assign inq_in2_exp_neq_ffs_add_buf1 = inq_in2_exp_neq_ffs_div_buf1;
assign inq_in2_exp_neq_ffs_div_buf1 = inq_in2_exp_neq_ffs;
assign ctu_tst_macrotest_buf1 = ctu_tst_macrotest;
assign ctu_tst_pre_grst_l_buf1 = ctu_tst_pre_grst_l;
assign ctu_tst_scan_disable_buf1 = ctu_tst_scan_disable;
assign ctu_tst_scanmode_buf1 = ctu_tst_scanmode;
assign ctu_tst_short_chain_buf1 = ctu_tst_short_chain;
assign global_shift_enable_buf1 = global_shift_enable;
assign grst_l_buf1 = grst_l;
assign cluster_cken_buf1 = cluster_cken;
assign se_div_buf5 = se_mul64_buf2;
assign se_mul_buf4 = se_mul64_buf2;
assign se_in_buf3 = se_mul64_buf2;
assign se_cluster_header_buf2 = se_mul64_buf2;
assign se_out_buf2 = se_mul64_buf2;
assign se_add_frac_buf2 = se_mul64_buf2;
assign se_add_exp_buf2 = se_mul64_buf2;
assign se_mul64_buf2 = se;
assign arst_l_add_buf4 = arst_l_in_buf3;
assign arst_l_out_buf3 = arst_l_in_buf3;
assign arst_l_cluster_header_buf2 = arst_l_in_buf3;
assign arst_l_mul_buf2 = arst_l_in_buf3;
assign arst_l_div_buf2 = arst_l_in_buf3;
assign arst_l_in_buf3 = arst_l;
assign fpu_grst_l_in_buf2 = fpu_grst_l_add_buf3;
assign fpu_grst_l_mul_buf1 = fpu_grst_l_add_buf3;
assign fpu_grst_l_add_buf3 = fpu_grst_l;
assign fmul_clken_l_buf1 = fmul_clken_l;
assign fdiv_clken_l_div_frac_buf1 = fdiv_clken_l_div_exp_buf1;
assign fdiv_clken_l_div_exp_buf1 = fdiv_clken_l;
assign scan_manual_6_buf1 = scan_manual_6;
assign si_buf1 = si;
assign so = so_unbuf;
assign pcx_fpio_data_px2_buf1[123] = pcx_fpio_data_px2[123];
assign pcx_fpio_data_px2_buf1[122] = pcx_fpio_data_px2[122];
assign pcx_fpio_data_px2_buf1[121] = pcx_fpio_data_px2[121];
assign pcx_fpio_data_px2_buf1[120] = pcx_fpio_data_px2[120];
assign pcx_fpio_data_px2_buf1[119] = pcx_fpio_data_px2[119];
assign pcx_fpio_data_px2_buf1[118] = pcx_fpio_data_px2[118];
assign pcx_fpio_data_px2_buf1[117] = pcx_fpio_data_px2[117];
assign pcx_fpio_data_px2_buf1[116] = pcx_fpio_data_px2[116];
assign pcx_fpio_data_px2_buf1[115] = pcx_fpio_data_px2[115];
assign pcx_fpio_data_px2_buf1[114] = pcx_fpio_data_px2[114];
assign pcx_fpio_data_px2_buf1[113] = pcx_fpio_data_px2[113];
assign pcx_fpio_data_px2_buf1[112] = pcx_fpio_data_px2[112];
assign pcx_fpio_data_px2_buf1[111] = pcx_fpio_data_px2[111];
assign pcx_fpio_data_px2_buf1[110] = pcx_fpio_data_px2[110];
assign pcx_fpio_data_px2_buf1[109] = pcx_fpio_data_px2[109];
assign pcx_fpio_data_px2_buf1[108] = pcx_fpio_data_px2[108];
assign pcx_fpio_data_px2_buf1[107] = pcx_fpio_data_px2[107];
assign pcx_fpio_data_px2_buf1[106] = pcx_fpio_data_px2[106];
assign pcx_fpio_data_px2_buf1[105] = pcx_fpio_data_px2[105];
assign pcx_fpio_data_px2_buf1[104] = pcx_fpio_data_px2[104];
assign pcx_fpio_data_px2_buf1[103] = pcx_fpio_data_px2[103];
assign pcx_fpio_data_px2_buf1[102] = pcx_fpio_data_px2[102];
assign pcx_fpio_data_px2_buf1[101] = pcx_fpio_data_px2[101];
assign pcx_fpio_data_px2_buf1[100] = pcx_fpio_data_px2[100];
assign pcx_fpio_data_px2_buf1[99] = pcx_fpio_data_px2[99];
assign pcx_fpio_data_px2_buf1[98] = pcx_fpio_data_px2[98];
assign pcx_fpio_data_px2_buf1[97] = pcx_fpio_data_px2[97];
assign pcx_fpio_data_px2_buf1[96] = pcx_fpio_data_px2[96];
assign pcx_fpio_data_px2_buf1[95] = pcx_fpio_data_px2[95];
assign pcx_fpio_data_px2_buf1[94] = pcx_fpio_data_px2[94];
assign pcx_fpio_data_px2_buf1[93] = pcx_fpio_data_px2[93];
assign pcx_fpio_data_px2_buf1[92] = pcx_fpio_data_px2[92];
assign pcx_fpio_data_px2_buf1[91] = pcx_fpio_data_px2[91];
assign pcx_fpio_data_px2_buf1[90] = pcx_fpio_data_px2[90];
assign pcx_fpio_data_px2_buf1[89] = pcx_fpio_data_px2[89];
assign pcx_fpio_data_px2_buf1[88] = pcx_fpio_data_px2[88];
assign pcx_fpio_data_px2_buf1[87] = pcx_fpio_data_px2[87];
assign pcx_fpio_data_px2_buf1[86] = pcx_fpio_data_px2[86];
assign pcx_fpio_data_px2_buf1[85] = pcx_fpio_data_px2[85];
assign pcx_fpio_data_px2_buf1[84] = pcx_fpio_data_px2[84];
assign pcx_fpio_data_px2_buf1[83] = pcx_fpio_data_px2[83];
assign pcx_fpio_data_px2_buf1[82] = pcx_fpio_data_px2[82];
assign pcx_fpio_data_px2_buf1[81] = pcx_fpio_data_px2[81];
assign pcx_fpio_data_px2_buf1[80] = pcx_fpio_data_px2[80];
assign pcx_fpio_data_px2_buf1[79] = pcx_fpio_data_px2[79];
assign pcx_fpio_data_px2_buf1[78] = pcx_fpio_data_px2[78];
assign pcx_fpio_data_px2_buf1[77] = pcx_fpio_data_px2[77];
assign pcx_fpio_data_px2_buf1[76] = pcx_fpio_data_px2[76];
assign pcx_fpio_data_px2_buf1[75] = pcx_fpio_data_px2[75];
assign pcx_fpio_data_px2_buf1[74] = pcx_fpio_data_px2[74];
assign pcx_fpio_data_px2_buf1[73] = pcx_fpio_data_px2[73];
assign pcx_fpio_data_px2_buf1[72] = pcx_fpio_data_px2[72];
assign pcx_fpio_data_px2_buf1[71] = pcx_fpio_data_px2[71];
assign pcx_fpio_data_px2_buf1[70] = pcx_fpio_data_px2[70];
assign pcx_fpio_data_px2_buf1[69] = pcx_fpio_data_px2[69];
assign pcx_fpio_data_px2_buf1[68] = pcx_fpio_data_px2[68];
assign pcx_fpio_data_px2_buf1[67] = pcx_fpio_data_px2[67];
assign pcx_fpio_data_px2_buf1[66] = pcx_fpio_data_px2[66];
assign pcx_fpio_data_px2_buf1[65] = pcx_fpio_data_px2[65];
assign pcx_fpio_data_px2_buf1[64] = pcx_fpio_data_px2[64];
assign pcx_fpio_data_px2_buf1[63] = pcx_fpio_data_px2[63];
assign pcx_fpio_data_px2_buf1[62] = pcx_fpio_data_px2[62];
assign pcx_fpio_data_px2_buf1[61] = pcx_fpio_data_px2[61];
assign pcx_fpio_data_px2_buf1[60] = pcx_fpio_data_px2[60];
assign pcx_fpio_data_px2_buf1[59] = pcx_fpio_data_px2[59];
assign pcx_fpio_data_px2_buf1[58] = pcx_fpio_data_px2[58];
assign pcx_fpio_data_px2_buf1[57] = pcx_fpio_data_px2[57];
assign pcx_fpio_data_px2_buf1[56] = pcx_fpio_data_px2[56];
assign pcx_fpio_data_px2_buf1[55] = pcx_fpio_data_px2[55];
assign pcx_fpio_data_px2_buf1[54] = pcx_fpio_data_px2[54];
assign pcx_fpio_data_px2_buf1[53] = pcx_fpio_data_px2[53];
assign pcx_fpio_data_px2_buf1[52] = pcx_fpio_data_px2[52];
assign pcx_fpio_data_px2_buf1[51] = pcx_fpio_data_px2[51];
assign pcx_fpio_data_px2_buf1[50] = pcx_fpio_data_px2[50];
assign pcx_fpio_data_px2_buf1[49] = pcx_fpio_data_px2[49];
assign pcx_fpio_data_px2_buf1[48] = pcx_fpio_data_px2[48];
assign pcx_fpio_data_px2_buf1[47] = pcx_fpio_data_px2[47];
assign pcx_fpio_data_px2_buf1[46] = pcx_fpio_data_px2[46];
assign pcx_fpio_data_px2_buf1[45] = pcx_fpio_data_px2[45];
assign pcx_fpio_data_px2_buf1[44] = pcx_fpio_data_px2[44];
assign pcx_fpio_data_px2_buf1[43] = pcx_fpio_data_px2[43];
assign pcx_fpio_data_px2_buf1[42] = pcx_fpio_data_px2[42];
assign pcx_fpio_data_px2_buf1[41] = pcx_fpio_data_px2[41];
assign pcx_fpio_data_px2_buf1[40] = pcx_fpio_data_px2[40];
assign pcx_fpio_data_px2_buf1[39] = pcx_fpio_data_px2[39];
assign pcx_fpio_data_px2_buf1[38] = pcx_fpio_data_px2[38];
assign pcx_fpio_data_px2_buf1[37] = pcx_fpio_data_px2[37];
assign pcx_fpio_data_px2_buf1[36] = pcx_fpio_data_px2[36];
assign pcx_fpio_data_px2_buf1[35] = pcx_fpio_data_px2[35];
assign pcx_fpio_data_px2_buf1[34] = pcx_fpio_data_px2[34];
assign pcx_fpio_data_px2_buf1[33] = pcx_fpio_data_px2[33];
assign pcx_fpio_data_px2_buf1[32] = pcx_fpio_data_px2[32];
assign pcx_fpio_data_px2_buf1[31] = pcx_fpio_data_px2[31];
assign pcx_fpio_data_px2_buf1[30] = pcx_fpio_data_px2[30];
assign pcx_fpio_data_px2_buf1[29] = pcx_fpio_data_px2[29];
assign pcx_fpio_data_px2_buf1[28] = pcx_fpio_data_px2[28];
assign pcx_fpio_data_px2_buf1[27] = pcx_fpio_data_px2[27];
assign pcx_fpio_data_px2_buf1[26] = pcx_fpio_data_px2[26];
assign pcx_fpio_data_px2_buf1[25] = pcx_fpio_data_px2[25];
assign pcx_fpio_data_px2_buf1[24] = pcx_fpio_data_px2[24];
assign pcx_fpio_data_px2_buf1[23] = pcx_fpio_data_px2[23];
assign pcx_fpio_data_px2_buf1[22] = pcx_fpio_data_px2[22];
assign pcx_fpio_data_px2_buf1[21] = pcx_fpio_data_px2[21];
assign pcx_fpio_data_px2_buf1[20] = pcx_fpio_data_px2[20];
assign pcx_fpio_data_px2_buf1[19] = pcx_fpio_data_px2[19];
assign pcx_fpio_data_px2_buf1[18] = pcx_fpio_data_px2[18];
assign pcx_fpio_data_px2_buf1[17] = pcx_fpio_data_px2[17];
assign pcx_fpio_data_px2_buf1[16] = pcx_fpio_data_px2[16];
assign pcx_fpio_data_px2_buf1[15] = pcx_fpio_data_px2[15];
assign pcx_fpio_data_px2_buf1[14] = pcx_fpio_data_px2[14];
assign pcx_fpio_data_px2_buf1[13] = pcx_fpio_data_px2[13];
assign pcx_fpio_data_px2_buf1[12] = pcx_fpio_data_px2[12];
assign pcx_fpio_data_px2_buf1[11] = pcx_fpio_data_px2[11];
assign pcx_fpio_data_px2_buf1[10] = pcx_fpio_data_px2[10];
assign pcx_fpio_data_px2_buf1[9] = pcx_fpio_data_px2[9];
assign pcx_fpio_data_px2_buf1[8] = pcx_fpio_data_px2[8];
assign pcx_fpio_data_px2_buf1[7] = pcx_fpio_data_px2[7];
assign pcx_fpio_data_px2_buf1[6] = pcx_fpio_data_px2[6];
assign pcx_fpio_data_px2_buf1[5] = pcx_fpio_data_px2[5];
assign pcx_fpio_data_px2_buf1[4] = pcx_fpio_data_px2[4];
assign pcx_fpio_data_px2_buf1[3] = pcx_fpio_data_px2[3];
assign pcx_fpio_data_px2_buf1[2] = pcx_fpio_data_px2[2];
assign pcx_fpio_data_px2_buf1[1] = pcx_fpio_data_px2[1];
assign pcx_fpio_data_px2_buf1[0] = pcx_fpio_data_px2[0];
assign pcx_fpio_data_rdy_px2_buf1 = pcx_fpio_data_rdy_px2;
assign fp_cpx_req_cq_buf1[7] = fp_cpx_req_cq[7];
assign fp_cpx_req_cq_buf1[6] = fp_cpx_req_cq[6];
assign fp_cpx_req_cq_buf1[5] = fp_cpx_req_cq[5];
assign fp_cpx_req_cq_buf1[4] = fp_cpx_req_cq[4];
assign fp_cpx_req_cq_buf1[3] = fp_cpx_req_cq[3];
assign fp_cpx_req_cq_buf1[2] = fp_cpx_req_cq[2];
assign fp_cpx_req_cq_buf1[1] = fp_cpx_req_cq[1];
assign fp_cpx_req_cq_buf1[0] = fp_cpx_req_cq[0];
assign fp_cpx_data_ca_buf1[144] = fp_cpx_data_ca[144];
assign fp_cpx_data_ca_buf1[143] = fp_cpx_data_ca[143];
assign fp_cpx_data_ca_buf1[142] = fp_cpx_data_ca[142];
assign fp_cpx_data_ca_buf1[141] = fp_cpx_data_ca[141];
assign fp_cpx_data_ca_buf1[140] = fp_cpx_data_ca[140];
assign fp_cpx_data_ca_buf1[139] = fp_cpx_data_ca[139];
assign fp_cpx_data_ca_buf1[138] = fp_cpx_data_ca[138];
assign fp_cpx_data_ca_buf1[137] = fp_cpx_data_ca[137];
assign fp_cpx_data_ca_buf1[136] = fp_cpx_data_ca[136];
assign fp_cpx_data_ca_buf1[135] = fp_cpx_data_ca[135];
assign fp_cpx_data_ca_buf1[134] = fp_cpx_data_ca[134];
assign fp_cpx_data_ca_buf1[133] = fp_cpx_data_ca[133];
assign fp_cpx_data_ca_buf1[132] = fp_cpx_data_ca[132];
assign fp_cpx_data_ca_buf1[131] = fp_cpx_data_ca[131];
assign fp_cpx_data_ca_buf1[130] = fp_cpx_data_ca[130];
assign fp_cpx_data_ca_buf1[129] = fp_cpx_data_ca[129];
assign fp_cpx_data_ca_buf1[128] = fp_cpx_data_ca[128];
assign fp_cpx_data_ca_buf1[127] = fp_cpx_data_ca[127];
assign fp_cpx_data_ca_buf1[126] = fp_cpx_data_ca[126];
assign fp_cpx_data_ca_buf1[125] = fp_cpx_data_ca[125];
assign fp_cpx_data_ca_buf1[124] = fp_cpx_data_ca[124];
assign fp_cpx_data_ca_buf1[123] = fp_cpx_data_ca[123];
assign fp_cpx_data_ca_buf1[122] = fp_cpx_data_ca[122];
assign fp_cpx_data_ca_buf1[121] = fp_cpx_data_ca[121];
assign fp_cpx_data_ca_buf1[120] = fp_cpx_data_ca[120];
assign fp_cpx_data_ca_buf1[119] = fp_cpx_data_ca[119];
assign fp_cpx_data_ca_buf1[118] = fp_cpx_data_ca[118];
assign fp_cpx_data_ca_buf1[117] = fp_cpx_data_ca[117];
assign fp_cpx_data_ca_buf1[116] = fp_cpx_data_ca[116];
assign fp_cpx_data_ca_buf1[115] = fp_cpx_data_ca[115];
assign fp_cpx_data_ca_buf1[114] = fp_cpx_data_ca[114];
assign fp_cpx_data_ca_buf1[113] = fp_cpx_data_ca[113];
assign fp_cpx_data_ca_buf1[112] = fp_cpx_data_ca[112];
assign fp_cpx_data_ca_buf1[111] = fp_cpx_data_ca[111];
assign fp_cpx_data_ca_buf1[110] = fp_cpx_data_ca[110];
assign fp_cpx_data_ca_buf1[109] = fp_cpx_data_ca[109];
assign fp_cpx_data_ca_buf1[108] = fp_cpx_data_ca[108];
assign fp_cpx_data_ca_buf1[107] = fp_cpx_data_ca[107];
assign fp_cpx_data_ca_buf1[106] = fp_cpx_data_ca[106];
assign fp_cpx_data_ca_buf1[105] = fp_cpx_data_ca[105];
assign fp_cpx_data_ca_buf1[104] = fp_cpx_data_ca[104];
assign fp_cpx_data_ca_buf1[103] = fp_cpx_data_ca[103];
assign fp_cpx_data_ca_buf1[102] = fp_cpx_data_ca[102];
assign fp_cpx_data_ca_buf1[101] = fp_cpx_data_ca[101];
assign fp_cpx_data_ca_buf1[100] = fp_cpx_data_ca[100];
assign fp_cpx_data_ca_buf1[99] = fp_cpx_data_ca[99];
assign fp_cpx_data_ca_buf1[98] = fp_cpx_data_ca[98];
assign fp_cpx_data_ca_buf1[97] = fp_cpx_data_ca[97];
assign fp_cpx_data_ca_buf1[96] = fp_cpx_data_ca[96];
assign fp_cpx_data_ca_buf1[95] = fp_cpx_data_ca[95];
assign fp_cpx_data_ca_buf1[94] = fp_cpx_data_ca[94];
assign fp_cpx_data_ca_buf1[93] = fp_cpx_data_ca[93];
assign fp_cpx_data_ca_buf1[92] = fp_cpx_data_ca[92];
assign fp_cpx_data_ca_buf1[91] = fp_cpx_data_ca[91];
assign fp_cpx_data_ca_buf1[90] = fp_cpx_data_ca[90];
assign fp_cpx_data_ca_buf1[89] = fp_cpx_data_ca[89];
assign fp_cpx_data_ca_buf1[88] = fp_cpx_data_ca[88];
assign fp_cpx_data_ca_buf1[87] = fp_cpx_data_ca[87];
assign fp_cpx_data_ca_buf1[86] = fp_cpx_data_ca[86];
assign fp_cpx_data_ca_buf1[85] = fp_cpx_data_ca[85];
assign fp_cpx_data_ca_buf1[84] = fp_cpx_data_ca[84];
assign fp_cpx_data_ca_buf1[83] = fp_cpx_data_ca[83];
assign fp_cpx_data_ca_buf1[82] = fp_cpx_data_ca[82];
assign fp_cpx_data_ca_buf1[81] = fp_cpx_data_ca[81];
assign fp_cpx_data_ca_buf1[80] = fp_cpx_data_ca[80];
assign fp_cpx_data_ca_buf1[79] = fp_cpx_data_ca[79];
assign fp_cpx_data_ca_buf1[78] = fp_cpx_data_ca[78];
assign fp_cpx_data_ca_buf1[77] = fp_cpx_data_ca[77];
assign fp_cpx_data_ca_buf1[76] = fp_cpx_data_ca[76];
assign fp_cpx_data_ca_buf1[75] = fp_cpx_data_ca[75];
assign fp_cpx_data_ca_buf1[74] = fp_cpx_data_ca[74];
assign fp_cpx_data_ca_buf1[73] = fp_cpx_data_ca[73];
assign fp_cpx_data_ca_buf1[72] = fp_cpx_data_ca[72];
assign fp_cpx_data_ca_buf1[71] = fp_cpx_data_ca[71];
assign fp_cpx_data_ca_buf1[70] = fp_cpx_data_ca[70];
assign fp_cpx_data_ca_buf1[69] = fp_cpx_data_ca[69];
assign fp_cpx_data_ca_buf1[68] = fp_cpx_data_ca[68];
assign fp_cpx_data_ca_buf1[67] = fp_cpx_data_ca[67];
assign fp_cpx_data_ca_buf1[66] = fp_cpx_data_ca[66];
assign fp_cpx_data_ca_buf1[65] = fp_cpx_data_ca[65];
assign fp_cpx_data_ca_buf1[64] = fp_cpx_data_ca[64];
assign fp_cpx_data_ca_buf1[63] = fp_cpx_data_ca[63];
assign fp_cpx_data_ca_buf1[62] = fp_cpx_data_ca[62];
assign fp_cpx_data_ca_buf1[61] = fp_cpx_data_ca[61];
assign fp_cpx_data_ca_buf1[60] = fp_cpx_data_ca[60];
assign fp_cpx_data_ca_buf1[59] = fp_cpx_data_ca[59];
assign fp_cpx_data_ca_buf1[58] = fp_cpx_data_ca[58];
assign fp_cpx_data_ca_buf1[57] = fp_cpx_data_ca[57];
assign fp_cpx_data_ca_buf1[56] = fp_cpx_data_ca[56];
assign fp_cpx_data_ca_buf1[55] = fp_cpx_data_ca[55];
assign fp_cpx_data_ca_buf1[54] = fp_cpx_data_ca[54];
assign fp_cpx_data_ca_buf1[53] = fp_cpx_data_ca[53];
assign fp_cpx_data_ca_buf1[52] = fp_cpx_data_ca[52];
assign fp_cpx_data_ca_buf1[51] = fp_cpx_data_ca[51];
assign fp_cpx_data_ca_buf1[50] = fp_cpx_data_ca[50];
assign fp_cpx_data_ca_buf1[49] = fp_cpx_data_ca[49];
assign fp_cpx_data_ca_buf1[48] = fp_cpx_data_ca[48];
assign fp_cpx_data_ca_buf1[47] = fp_cpx_data_ca[47];
assign fp_cpx_data_ca_buf1[46] = fp_cpx_data_ca[46];
assign fp_cpx_data_ca_buf1[45] = fp_cpx_data_ca[45];
assign fp_cpx_data_ca_buf1[44] = fp_cpx_data_ca[44];
assign fp_cpx_data_ca_buf1[43] = fp_cpx_data_ca[43];
assign fp_cpx_data_ca_buf1[42] = fp_cpx_data_ca[42];
assign fp_cpx_data_ca_buf1[41] = fp_cpx_data_ca[41];
assign fp_cpx_data_ca_buf1[40] = fp_cpx_data_ca[40];
assign fp_cpx_data_ca_buf1[39] = fp_cpx_data_ca[39];
assign fp_cpx_data_ca_buf1[38] = fp_cpx_data_ca[38];
assign fp_cpx_data_ca_buf1[37] = fp_cpx_data_ca[37];
assign fp_cpx_data_ca_buf1[36] = fp_cpx_data_ca[36];
assign fp_cpx_data_ca_buf1[35] = fp_cpx_data_ca[35];
assign fp_cpx_data_ca_buf1[34] = fp_cpx_data_ca[34];
assign fp_cpx_data_ca_buf1[33] = fp_cpx_data_ca[33];
assign fp_cpx_data_ca_buf1[32] = fp_cpx_data_ca[32];
assign fp_cpx_data_ca_buf1[31] = fp_cpx_data_ca[31];
assign fp_cpx_data_ca_buf1[30] = fp_cpx_data_ca[30];
assign fp_cpx_data_ca_buf1[29] = fp_cpx_data_ca[29];
assign fp_cpx_data_ca_buf1[28] = fp_cpx_data_ca[28];
assign fp_cpx_data_ca_buf1[27] = fp_cpx_data_ca[27];
assign fp_cpx_data_ca_buf1[26] = fp_cpx_data_ca[26];
assign fp_cpx_data_ca_buf1[25] = fp_cpx_data_ca[25];
assign fp_cpx_data_ca_buf1[24] = fp_cpx_data_ca[24];
assign fp_cpx_data_ca_buf1[23] = fp_cpx_data_ca[23];
assign fp_cpx_data_ca_buf1[22] = fp_cpx_data_ca[22];
assign fp_cpx_data_ca_buf1[21] = fp_cpx_data_ca[21];
assign fp_cpx_data_ca_buf1[20] = fp_cpx_data_ca[20];
assign fp_cpx_data_ca_buf1[19] = fp_cpx_data_ca[19];
assign fp_cpx_data_ca_buf1[18] = fp_cpx_data_ca[18];
assign fp_cpx_data_ca_buf1[17] = fp_cpx_data_ca[17];
assign fp_cpx_data_ca_buf1[16] = fp_cpx_data_ca[16];
assign fp_cpx_data_ca_buf1[15] = fp_cpx_data_ca[15];
assign fp_cpx_data_ca_buf1[14] = fp_cpx_data_ca[14];
assign fp_cpx_data_ca_buf1[13] = fp_cpx_data_ca[13];
assign fp_cpx_data_ca_buf1[12] = fp_cpx_data_ca[12];
assign fp_cpx_data_ca_buf1[11] = fp_cpx_data_ca[11];
assign fp_cpx_data_ca_buf1[10] = fp_cpx_data_ca[10];
assign fp_cpx_data_ca_buf1[9] = fp_cpx_data_ca[9];
assign fp_cpx_data_ca_buf1[8] = fp_cpx_data_ca[8];
assign fp_cpx_data_ca_buf1[7] = fp_cpx_data_ca[7];
assign fp_cpx_data_ca_buf1[6] = fp_cpx_data_ca[6];
assign fp_cpx_data_ca_buf1[5] = fp_cpx_data_ca[5];
assign fp_cpx_data_ca_buf1[4] = fp_cpx_data_ca[4];
assign fp_cpx_data_ca_buf1[3] = fp_cpx_data_ca[3];
assign fp_cpx_data_ca_buf1[2] = fp_cpx_data_ca[2];
assign fp_cpx_data_ca_buf1[1] = fp_cpx_data_ca[1];
assign fp_cpx_data_ca_buf1[0] = fp_cpx_data_ca[0];
assign inq_sram_din_buf1[155] = inq_sram_din_unbuf[155];
assign inq_sram_din_buf1[154] = inq_sram_din_unbuf[154];
assign inq_sram_din_buf1[153] = inq_sram_din_unbuf[153];
assign inq_sram_din_buf1[152] = inq_sram_din_unbuf[152];
assign inq_sram_din_buf1[151] = inq_sram_din_unbuf[151];
assign inq_sram_din_buf1[150] = inq_sram_din_unbuf[150];
assign inq_sram_din_buf1[149] = inq_sram_din_unbuf[149];
assign inq_sram_din_buf1[148] = inq_sram_din_unbuf[148];
assign inq_sram_din_buf1[147] = inq_sram_din_unbuf[147];
assign inq_sram_din_buf1[146] = inq_sram_din_unbuf[146];
assign inq_sram_din_buf1[145] = inq_sram_din_unbuf[145];
assign inq_sram_din_buf1[144] = inq_sram_din_unbuf[144];
assign inq_sram_din_buf1[143] = inq_sram_din_unbuf[143];
assign inq_sram_din_buf1[142] = inq_sram_din_unbuf[142];
assign inq_sram_din_buf1[141] = inq_sram_din_unbuf[141];
assign inq_sram_din_buf1[140] = inq_sram_din_unbuf[140];
assign inq_sram_din_buf1[139] = inq_sram_din_unbuf[139];
assign inq_sram_din_buf1[138] = inq_sram_din_unbuf[138];
assign inq_sram_din_buf1[137] = inq_sram_din_unbuf[137];
assign inq_sram_din_buf1[136] = inq_sram_din_unbuf[136];
assign inq_sram_din_buf1[135] = inq_sram_din_unbuf[135];
assign inq_sram_din_buf1[134] = inq_sram_din_unbuf[134];
assign inq_sram_din_buf1[133] = inq_sram_din_unbuf[133];
assign inq_sram_din_buf1[132] = inq_sram_din_unbuf[132];
assign inq_sram_din_buf1[131] = inq_sram_din_unbuf[131];
assign inq_sram_din_buf1[130] = inq_sram_din_unbuf[130];
assign inq_sram_din_buf1[129] = inq_sram_din_unbuf[129];
assign inq_sram_din_buf1[128] = inq_sram_din_unbuf[128];
assign inq_sram_din_buf1[127] = inq_sram_din_unbuf[127];
assign inq_sram_din_buf1[126] = inq_sram_din_unbuf[126];
assign inq_sram_din_buf1[125] = inq_sram_din_unbuf[125];
assign inq_sram_din_buf1[124] = inq_sram_din_unbuf[124];
assign inq_sram_din_buf1[123] = inq_sram_din_unbuf[123];
assign inq_sram_din_buf1[122] = inq_sram_din_unbuf[122];
assign inq_sram_din_buf1[121] = inq_sram_din_unbuf[121];
assign inq_sram_din_buf1[120] = inq_sram_din_unbuf[120];
assign inq_sram_din_buf1[119] = inq_sram_din_unbuf[119];
assign inq_sram_din_buf1[118] = inq_sram_din_unbuf[118];
assign inq_sram_din_buf1[117] = inq_sram_din_unbuf[117];
assign inq_sram_din_buf1[116] = inq_sram_din_unbuf[116];
assign inq_sram_din_buf1[115] = inq_sram_din_unbuf[115];
assign inq_sram_din_buf1[114] = inq_sram_din_unbuf[114];
assign inq_sram_din_buf1[113] = inq_sram_din_unbuf[113];
assign inq_sram_din_buf1[112] = inq_sram_din_unbuf[112];
assign inq_sram_din_buf1[111] = inq_sram_din_unbuf[111];
assign inq_sram_din_buf1[110] = inq_sram_din_unbuf[110];
assign inq_sram_din_buf1[109] = inq_sram_din_unbuf[109];
assign inq_sram_din_buf1[108] = inq_sram_din_unbuf[108];
assign inq_sram_din_buf1[107] = inq_sram_din_unbuf[107];
assign inq_sram_din_buf1[106] = inq_sram_din_unbuf[106];
assign inq_sram_din_buf1[105] = inq_sram_din_unbuf[105];
assign inq_sram_din_buf1[104] = inq_sram_din_unbuf[104];
assign inq_sram_din_buf1[103] = inq_sram_din_unbuf[103];
assign inq_sram_din_buf1[102] = inq_sram_din_unbuf[102];
assign inq_sram_din_buf1[101] = inq_sram_din_unbuf[101];
assign inq_sram_din_buf1[100] = inq_sram_din_unbuf[100];
assign inq_sram_din_buf1[99] = inq_sram_din_unbuf[99];
assign inq_sram_din_buf1[98] = inq_sram_din_unbuf[98];
assign inq_sram_din_buf1[97] = inq_sram_din_unbuf[97];
assign inq_sram_din_buf1[96] = inq_sram_din_unbuf[96];
assign inq_sram_din_buf1[95] = inq_sram_din_unbuf[95];
assign inq_sram_din_buf1[94] = inq_sram_din_unbuf[94];
assign inq_sram_din_buf1[93] = inq_sram_din_unbuf[93];
assign inq_sram_din_buf1[92] = inq_sram_din_unbuf[92];
assign inq_sram_din_buf1[91] = inq_sram_din_unbuf[91];
assign inq_sram_din_buf1[90] = inq_sram_din_unbuf[90];
assign inq_sram_din_buf1[89] = inq_sram_din_unbuf[89];
assign inq_sram_din_buf1[88] = inq_sram_din_unbuf[88];
assign inq_sram_din_buf1[87] = inq_sram_din_unbuf[87];
assign inq_sram_din_buf1[86] = inq_sram_din_unbuf[86];
assign inq_sram_din_buf1[85] = inq_sram_din_unbuf[85];
assign inq_sram_din_buf1[84] = inq_sram_din_unbuf[84];
assign inq_sram_din_buf1[83] = inq_sram_din_unbuf[83];
assign inq_sram_din_buf1[82] = inq_sram_din_unbuf[82];
assign inq_sram_din_buf1[81] = inq_sram_din_unbuf[81];
assign inq_sram_din_buf1[80] = inq_sram_din_unbuf[80];
assign inq_sram_din_buf1[79] = inq_sram_din_unbuf[79];
assign inq_sram_din_buf1[78] = inq_sram_din_unbuf[78];
assign inq_sram_din_buf1[77] = inq_sram_din_unbuf[77];
assign inq_sram_din_buf1[76] = inq_sram_din_unbuf[76];
assign inq_sram_din_buf1[75] = inq_sram_din_unbuf[75];
assign inq_sram_din_buf1[74] = inq_sram_din_unbuf[74];
assign inq_sram_din_buf1[73] = inq_sram_din_unbuf[73];
assign inq_sram_din_buf1[72] = inq_sram_din_unbuf[72];
assign inq_sram_din_buf1[71] = inq_sram_din_unbuf[71];
assign inq_sram_din_buf1[70] = inq_sram_din_unbuf[70];
assign inq_sram_din_buf1[69] = inq_sram_din_unbuf[69];
assign inq_sram_din_buf1[68] = inq_sram_din_unbuf[68];
assign inq_sram_din_buf1[67] = inq_sram_din_unbuf[67];
assign inq_sram_din_buf1[66] = inq_sram_din_unbuf[66];
assign inq_sram_din_buf1[65] = inq_sram_din_unbuf[65];
assign inq_sram_din_buf1[64] = inq_sram_din_unbuf[64];
assign inq_sram_din_buf1[63] = inq_sram_din_unbuf[63];
assign inq_sram_din_buf1[62] = inq_sram_din_unbuf[62];
assign inq_sram_din_buf1[61] = inq_sram_din_unbuf[61];
assign inq_sram_din_buf1[60] = inq_sram_din_unbuf[60];
assign inq_sram_din_buf1[59] = inq_sram_din_unbuf[59];
assign inq_sram_din_buf1[58] = inq_sram_din_unbuf[58];
assign inq_sram_din_buf1[57] = inq_sram_din_unbuf[57];
assign inq_sram_din_buf1[56] = inq_sram_din_unbuf[56];
assign inq_sram_din_buf1[55] = inq_sram_din_unbuf[55];
assign inq_sram_din_buf1[54] = inq_sram_din_unbuf[54];
assign inq_sram_din_buf1[53] = inq_sram_din_unbuf[53];
assign inq_sram_din_buf1[52] = inq_sram_din_unbuf[52];
assign inq_sram_din_buf1[51] = inq_sram_din_unbuf[51];
assign inq_sram_din_buf1[50] = inq_sram_din_unbuf[50];
assign inq_sram_din_buf1[49] = inq_sram_din_unbuf[49];
assign inq_sram_din_buf1[48] = inq_sram_din_unbuf[48];
assign inq_sram_din_buf1[47] = inq_sram_din_unbuf[47];
assign inq_sram_din_buf1[46] = inq_sram_din_unbuf[46];
assign inq_sram_din_buf1[45] = inq_sram_din_unbuf[45];
assign inq_sram_din_buf1[44] = inq_sram_din_unbuf[44];
assign inq_sram_din_buf1[43] = inq_sram_din_unbuf[43];
assign inq_sram_din_buf1[42] = inq_sram_din_unbuf[42];
assign inq_sram_din_buf1[41] = inq_sram_din_unbuf[41];
assign inq_sram_din_buf1[40] = inq_sram_din_unbuf[40];
assign inq_sram_din_buf1[39] = inq_sram_din_unbuf[39];
assign inq_sram_din_buf1[38] = inq_sram_din_unbuf[38];
assign inq_sram_din_buf1[37] = inq_sram_din_unbuf[37];
assign inq_sram_din_buf1[36] = inq_sram_din_unbuf[36];
assign inq_sram_din_buf1[35] = inq_sram_din_unbuf[35];
assign inq_sram_din_buf1[34] = inq_sram_din_unbuf[34];
assign inq_sram_din_buf1[33] = inq_sram_din_unbuf[33];
assign inq_sram_din_buf1[32] = inq_sram_din_unbuf[32];
assign inq_sram_din_buf1[31] = inq_sram_din_unbuf[31];
assign inq_sram_din_buf1[30] = inq_sram_din_unbuf[30];
assign inq_sram_din_buf1[29] = inq_sram_din_unbuf[29];
assign inq_sram_din_buf1[28] = inq_sram_din_unbuf[28];
assign inq_sram_din_buf1[27] = inq_sram_din_unbuf[27];
assign inq_sram_din_buf1[26] = inq_sram_din_unbuf[26];
assign inq_sram_din_buf1[25] = inq_sram_din_unbuf[25];
assign inq_sram_din_buf1[24] = inq_sram_din_unbuf[24];
assign inq_sram_din_buf1[23] = inq_sram_din_unbuf[23];
assign inq_sram_din_buf1[22] = inq_sram_din_unbuf[22];
assign inq_sram_din_buf1[21] = inq_sram_din_unbuf[21];
assign inq_sram_din_buf1[20] = inq_sram_din_unbuf[20];
assign inq_sram_din_buf1[19] = inq_sram_din_unbuf[19];
assign inq_sram_din_buf1[18] = inq_sram_din_unbuf[18];
assign inq_sram_din_buf1[17] = inq_sram_din_unbuf[17];
assign inq_sram_din_buf1[16] = inq_sram_din_unbuf[16];
assign inq_sram_din_buf1[15] = inq_sram_din_unbuf[15];
assign inq_sram_din_buf1[14] = inq_sram_din_unbuf[14];
assign inq_sram_din_buf1[13] = inq_sram_din_unbuf[13];
assign inq_sram_din_buf1[12] = inq_sram_din_unbuf[12];
assign inq_sram_din_buf1[11] = inq_sram_din_unbuf[11];
assign inq_sram_din_buf1[10] = inq_sram_din_unbuf[10];
assign inq_sram_din_buf1[9] = inq_sram_din_unbuf[9];
assign inq_sram_din_buf1[8] = inq_sram_din_unbuf[8];
assign inq_sram_din_buf1[7] = inq_sram_din_unbuf[7];
assign inq_sram_din_buf1[6] = inq_sram_din_unbuf[6];
assign inq_sram_din_buf1[5] = inq_sram_din_unbuf[5];
assign inq_sram_din_buf1[4] = inq_sram_din_unbuf[4];
assign inq_sram_din_buf1[3] = inq_sram_din_unbuf[3];
assign inq_sram_din_buf1[2] = inq_sram_din_unbuf[2];
assign inq_sram_din_buf1[1] = inq_sram_din_unbuf[1];
assign inq_sram_din_buf1[0] = inq_sram_din_unbuf[0];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/30/2017 01:38:40 PM
// Design Name:
// Module Name: SHA1_core_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SHA1_core_tb(
);
reg clk,rst;
reg i_hash_in_start;
reg [31:0]i_hash_in;
reg msg_in_start;
reg [31:0]msgIn;
reg [9:0]msgLenBits;
wire msgOutDone;
wire [511:0]msgOut;
wire [159:0]i_hash_out;
wire i_hash_out_done;
wire digest_done;
wire [159:0]digest;
wire f_hash_done;
wire [31:0]f_hash_out;
Initial_Hash_In I1(clk,rst,i_hash_in_start,i_hash_in,i_hash_out_done,i_hash_out);
Msg_In M1(clk,rst,msg_in_start,msgIn,msgOutDone,msgOut);
SHA1_core S1(clk,rst,i_hash_out_done,i_hash_out,msgOutDone,msgLenBits,msgOut,digest_done,digest);
SHA1_out O1(clk,rst,digest_done,digest,f_hash_done,f_hash_out);
initial begin
clk = 0;
#5 rst = 0;
#10 rst = 1;
#10 i_hash_in_start = 1;
msg_in_start = 1;
msgLenBits = 24;
msgIn = 32'h61626300;
i_hash_in = 32'h67452301;
#10 msgIn = 0;
i_hash_in = 32'hefcdab89;
#10 msgIn = 0;
i_hash_in = 32'h98badcfe;
#10 msgIn = 0;
i_hash_in = 32'h10325476;
#10 msgIn = 0;
i_hash_in = 32'hc3d2e1f0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn =0;
#6000 $finish;
end
always begin
#5 clk = ~clk;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 18:30:50 09/19/2015
// Design Name: Moore State Machine
// Module Name: hw2problem3
//////////////////////////////////////////////////////////////////////////////////
module hw2problem3(X, Y, RESET, CLOCK, CurrentState);
input X, RESET, CLOCK;
output reg Y;
output reg [1:0] CurrentState;
reg [1:0] NextState;
parameter State0 = 2'b00, State1 = 2'b01, State2 = 2'b10, State3 = 2'b11;
always @ (CurrentState)
if (CurrentState == State2) Y <= 1;
else Y <= 1;
always @ (posedge CLOCK or negedge RESET)
if (RESET == 0) CurrentState <= State0;
else CurrentState <= NextState;
always @ (CurrentState or X)
case (CurrentState)
State0: NextState <= (X == 1) ? State1 : State0;
State1: NextState <= (X == 1) ? State3 : State0;
State2: NextState <= (X == 1) ? State2 : State0;
State3: NextState <= (X == 1) ? State2 : State0;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_1_V
`define SKY130_FD_SC_HS__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_1 (
GCLK,
GATE,
CLK ,
SCE ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_1 (
GCLK,
GATE,
CLK ,
SCE
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_1_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1417708681 : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A311OI_PP_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18.04.2018 12:29:16
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input wire [2:0]mon_in,
input wire [2:0]panel_przyciskow_in,
input wire c_k, p_w, i_k, i_m, p_b,
input wire clk,
output wire [2:0] mon_out, // zwrot monet
output wire [2:0] urzadzenia,
output wire [3:0] segment_out, // wskanik wywietlanej liczby (0-wywietlany, 1-zgaszony)
output wire seg_um, // góra, rodek
output wire seg_ul, // góra, lewo
output wire seg_ur, // góra, prawo
output wire seg_mm, // rodek, rodek
output wire seg_dl, // dó³, lewo
output wire seg_dr, // dó³, prawo
output wire seg_dm, // dól, rodek
output wire seg_dot // kropka
);
// pod³¹czamy modu³ sprawnosci
wire sprawnosc_out;
sprawnosc spr_test(.c_k(c_k), .p_w(p_w), .i_k(i_k), .i_m(i_m), .p_b(p_b), .signal_s(sprawnosc_out));
//dzielnik czestotliwoci
wire clk_div;
divider #(1) div(.clk(clk), .clk_div(clk_div));
//modu³ monet
parameter CENA_OP1 = `m300; // cena opcji 1 (3.00z³ - expresso )
parameter CENA_OP2 = `m500; // cena opcji 2 (5.00z³ - expresso grande :P )
parameter CENA_OP3 = `m750; // cena opcji 3 (7.50z³ - cappuccino :P )
wire [2:0]cmd_out;
wire [1:0]cmd_in;
wire [4:0]stan_mm;
modul_monet #(.CENA_OP1(CENA_OP1), .CENA_OP2(CENA_OP2), .CENA_OP3(CENA_OP3)) wrzut_zwrot(.clk(clk_div), .cmd_in(cmd_out),
.cmd_out(cmd_in), .stan_mm(stan_mm), .mon_in(mon_in), .mon_out(mon_out));
// licznik
parameter tick_every = 20; // pozwoli dostosowaæ czasy do zegaru (oraz przyspieszyæ symulacjê ;] )
wire licz_in;
wire [3:0]licz_out;
wire [6:0]count_secs;
counter #(.tick_every(tick_every)) licznik(.clk(clk_div), .count_out(licz_in), .count_in(licz_out), .count_secs(count_secs));
// wyswietlacz
wire [4:0]L_1, L_2, L_3, L_4;
wyswietlacz_4x7seg wys_pan(.clk(clk), .L_1(L_1), .L_2(L_2), .L_3(L_3), .L_4(L_4),
.seg_um(seg_um), .seg_ul(seg_ul), .seg_ur(seg_ur), .seg_mm(seg_mm),
.seg_dm(seg_dm), .seg_dl(seg_dl), .seg_dr(seg_dr), .seg_dot(seg_dot), .segment_out(segment_out));
// pod³¹czenie starego top
wire [2:0]u;
mdk_top old_top(.sprawnosc_in(sprawnosc_out), .panel_przyciskow_in(panel_przyciskow_in), .clk_div(clk_div),
.cmd_out(cmd_out), .cmd_in(cmd_in), .stan_mm(stan_mm), .licz_in(licz_in), .licz_out(licz_out), .count_secs(count_secs),
.L_1(L_1), .L_2(L_2), .L_3(L_3), .L_4(L_4),
.urzadzenia(urzadzenia) );
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// TDM slave controller, high speed version ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// This block connectes the FPGA and CPLD on XESS XSV board ////
//// using high speed time division multiplexing over serial ////
//// connection. This block implements the slave part. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// - Simon Srot, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 OpenCores ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "rtl/verilog/bench_timescale.v"
// synopsys translate_on
module tdm_slave_if(
clk, rst, tdmfrm, tdmrx, tdmtx,
din, dout
);
//
// I/O ports
//
//
// Global signals
//
input clk;
input rst;
//
// External CPLD signals
//
input tdmfrm;
input tdmrx;
output tdmtx;
//
// Internal demuxed 8-bit buses
//
input [7:0] din;
output [7:0] dout;
//
// Internal regs and wires
//
reg [2:0] clk_cnt;
reg [7:0] dout;
reg tdmtx;
//
// Counter for low speed clock and incoming JTAG data slots
//
always @(posedge clk or posedge rst)
if (rst)
clk_cnt <= #1 3'b000;
else if (tdmfrm)
clk_cnt <= #1 3'b001;
else
clk_cnt <= #1 clk_cnt + 1;
//
// RX Data slot extraction
//
always @(posedge clk or posedge rst)
if (rst) begin
dout <= #1 8'b0000_0000;
end else
case (clk_cnt[2:0])
3'd0: dout[0] <= #1 tdmrx;
3'd1: dout[1] <= #1 tdmrx;
3'd2: dout[2] <= #1 tdmrx;
3'd3: dout[3] <= #1 tdmrx;
3'd4: dout[4] <= #1 tdmrx;
3'd5: dout[5] <= #1 tdmrx;
3'd6: dout[6] <= #1 tdmrx;
3'd7: dout[7] <= #1 tdmrx;
endcase
//
// TX Data slot insertion
//
always @(clk_cnt or din)
case (clk_cnt[2:0])
3'd0: tdmtx = din[0];
3'd1: tdmtx = din[1];
3'd2: tdmtx = din[2];
3'd3: tdmtx = din[3];
3'd4: tdmtx = din[4];
3'd5: tdmtx = din[5];
3'd6: tdmtx = din[6];
3'd7: tdmtx = din[7];
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_2_V
`define SKY130_FD_SC_LP__CLKBUFLP_2_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog wrapper for clkbuflp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuflp_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuflp_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_2_V
|
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Strings.Ascii Coq.Strings.String.
Require Import Coq.Strings.Ascii.
Require Import Coq.Lists.List.
Require Import Coq.ZArith.ZArith.
Require Import ExtLib.Structures.Monad.
Require Import ExtLib.Data.Monads.StateMonad.
Require Import ExtLib.Data.Monads.IdentityMonad.
Require Import ExtLib.Structures.MonadState.
Require Import Coq.Numbers.DecimalString.
Import ListNotations.
Import MonadNotation.
Local Open Scope monad_scope.
Local Open Scope type_scope.
(*
This is an experimental version of Cava which illustrates the
type of API I would ideally like to have for Cava for describing
circuits with feedback.
*)
(*
There are two types of wires: single wires that carry one bit of
information which are represented by Bit and a 32-bit unsigned
wire which is represented by Nat.
*)
Inductive SignalType :=
| Bit : SignalType
| Nat : SignalType.
(*
A typeclass let's us write over-loaded circuit descriptions which
can have many instantiations e.g. one for circuit semantics (by way
of similation) and another for generating a circuit netlist. A circuit
will always be a Gallina function which returns its output result
in some instance of a Monad type. We can then compose overloaded
circuit descriptions using the Kleisli arrow >=> and all the other monad
combinators. A very partial API, just enough to make some illustrative examples.
*)
Class Acorn acorn `{Monad acorn} (signal : SignalType -> Type) := {
(* An invertor gate. *)
inv : signal Bit -> acorn (signal Bit);
(* A NAND gate *)
and2 : signal Bit * signal Bit -> acorn (signal Bit);
(* Add two nat values and then mod by a nat *)
addMod : nat -> signal Nat * signal Nat -> acorn (signal Nat);
(* Delay a wire of nat values by one clock cycle. *)
natDelay : signal Nat -> acorn (signal Nat);
(* Lava type loop combinator for feedback *)
loop : (signal Nat * signal Nat -> acorn (signal Nat * signal Nat)) ->
signal Nat -> acorn (signal Nat);
(* Ideally an infinite source of some nat value *)
constNat : nat -> acorn (signal Nat);
(* True if the first value is > to the second value. *)
comparator : signal Nat * signal Nat -> acorn (signal Bit);
(* If bool select signal is true then mux2 the first value in the pair, otherwise second element is returned *)
mux2 : signal Bit * (signal Nat * signal Nat) -> acorn (signal Nat);
}.
(* Some useful circuit combinators and an example circuit. *)
Section WithAcorn.
Context {acorn} {signal} `{Acorn acorn signal}.
(* Take a wire and fork it into two branches. *)
Definition fork2 {t : SignalType}
(a : signal t) : acorn (signal t * signal t) :=
ret (a, a).
(* Take a pair input and apply the circuit r to just the first element. *)
Definition fsT {t1 t2 t3 : SignalType}
(f : signal t1 -> acorn (signal t3))
(ab : signal t1 * signal t2) : acorn (signal t3 * signal t2) :=
let (a, b) := ab in
o <- f a ;;
ret (o, b).
(* Take a pair input and apply the circuit r to just the second element. *)
Definition snD {t1 t2 t3 : SignalType}
(f : signal t2 -> acorn (signal t3))
(ab : signal t1 * signal t2) : acorn (signal t1 * signal t3) :=
let (a, b) := ab in
o <- f b ;;
ret (a, o).
(* A circuit which delays the second element of a pair and then performs
a 256-bit addition of the two values in the pair. *)
Definition circuit1 : signal Nat * signal Nat -> acorn (signal Nat) :=
snD natDelay >=> addMod 256.
End WithAcorn.
(*
So far we have overloaded circuit descriptions and combinators, but we can't
yet do anything with them until we define some instances of the Acorn class.
Let's create an instance for the simulation of these overloaded circuit descriptions,
which acts as the semantics for these circuits.
*)
(*
We need to explain how to map a SignalType to the types we use to represent the
types of the values that flow over wires. For simulation, Bit will be represented
by a list of bool values, Nat will be represented by a list of nat values.
*)
Definition simulationSignal (t: SignalType) : Type :=
match t with
| Bit => list bool
| Nat => list nat
end.
(*
Semantics of addition followed by mod. The modBy value is a compile
time constant.
*)
Definition addModSim (modBy : nat) (ab : list nat * list nat) : ident (list nat) :=
let (a, b) := ab in
ret (map (fun '(x, y) => (x + y) mod modBy) (combine a b)).
(* Semantics of the two-input comparator. *)
Definition comparatorSim (ab : list nat * list nat) : ident (list bool) :=
let (a, b) := ab in
ret (map (fun '(x, y) => y <=? x) (combine a b)).
(* Core semantics of a 2-input multiplexor. *)
Definition mux2' (sxy : bool * (nat * nat)) : nat :=
let (s, xy) := sxy in
let (x, y) := xy in
if s then x else y.
(*
An instance of the Acorn class for circuit simulation, with a dummy value
for loop (since I don't know how to define it) and a hacky definition for
constNat because I don't know how to make an infinite list.
*)
Instance AcornSimulation : Acorn ident simulationSignal := {
inv i := ret (map negb i);
and2 '(a, b) := ret (map (fun '(x, y) => andb x y) (combine a b));
addMod := addModSim;
natDelay i := ret (0 :: i);
loop f i := ret i; (* Dummy Definition. QUESTION: How to do this in Coq? cd. how it is done in Lava in Haskell *)
constNat n := ret (repeat n 100); (* Hack, just repeat n 100 times. How to get an infinite list in Coq? *)
comparator := comparatorSim;
mux2 '(sel, (a, b)) := ret (map mux2' (combine sel (combine a b)));
}.
(* We can easily simulate circuits without loops, even if they contain delay elements. *)
Compute (unIdent (circuit1 ([17; 78; 12], [42; 62; 5]))).
(*
= [17; 120; 74]
*)
(* What's we can't do is simulate circuits with loop. *)
(*
We can create circuit netlists for circuits with loops. To make a circuit
netlist we first define some types for representing a circuit netlist.
*)
(* The nodes of the circuit graph. *)
Inductive Instance :=
| Inv : N -> N -> N -> Instance
| And2 : N -> N -> N -> N -> Instance
| AddMod : nat -> N -> N -> N -> Instance
| NatDelay : N -> N -> Instance
| AssignNat : N -> N -> Instance
| ConstNat : N -> N -> Instance
| Comparator : N -> N -> N -> Instance
| Mux2 : N -> N -> N -> N -> Instance.
(* The I/O interface of the circuit. *)
Inductive Port :=
| InputBit : string -> N -> Port
| OutputBit : N -> string -> Port
| InputNat : string -> N -> Port
| OutputNat : N -> string -> Port.
(* The complete netlist type. *)
Record Netlist := mkNetlist {
netlistName : string; (* Name of the module to be generated. *)
instCount : N; (* A count of the number of nodes. *)
bitCount : N; (* A count of the number of local bit-type wires. *)
natCount : N; (* A count of the number of nat-type wires. *)
instances : list Instance; (* A list of the circuit graph nodes. *)
ports : list Port; (* The I/O interface of the circuit. *)
}.
(* An empty netlist. *)
Definition emptyNetist : Netlist :=
mkNetlist "" 0 0 0 [] [].
(*
The types of the values that flow over wires for the netlist
representation is the Signal type which is a symbolic representation
for the value on that wire (the name of a net).
*)
Inductive Signal : SignalType -> Type :=
| BitNet : N -> Signal Bit
| NatNet : N -> Signal Nat.
(* The denotion of a SignalType for netlist generation is just the Signal type. *)
Definition denoteSignal (t: SignalType) : Type := Signal t.
(* Some useful functions for working over netlists. *)
Definition newWire : state Netlist (Signal Bit) :=
ns <- get ;;
match ns with
| mkNetlist name ic bc nc is ps =>
put (mkNetlist name ic (bc + 1) nc is ps) ;;
ret (BitNet bc)
end.
Definition newNat : state Netlist (Signal Nat) :=
ns <- get ;;
match ns with
| mkNetlist name ic bc nc is ps =>
put (mkNetlist name ic bc (nc + 1) is ps) ;;
ret (NatNet nc)
end.
Definition newInstNr : state Netlist N :=
ns <- get ;;
match ns with
| mkNetlist name ic bc nc is ps =>
put (mkNetlist name (ic + 1) bc nc is ps) ;;
ret ic
end.
Definition addInstance (inst : Instance) : state Netlist unit :=
ns <- get ;;
match ns with
| mkNetlist name ic bc nc is ps =>
put (mkNetlist name ic bc nc (inst::is) ps)
end.
Definition addPort (p : Port) : state Netlist unit :=
ns <- get ;;
match ns with
| mkNetlist name ic bc nc is ps =>
put (mkNetlist name ic bc nc is (p::ps))
end.
Definition wireNr (w : Signal Bit) : N :=
match w with
| BitNet n => n
end.
Definition invGate (i : Signal Bit) : state Netlist (Signal Bit) :=
o <- newWire ;;
instNr <- newInstNr ;;
addInstance (Inv instNr (wireNr i) (wireNr o)) ;;
ret o.
Definition and2Gate (i0i1 : Signal Bit * Signal Bit) : state Netlist (Signal Bit) :=
o <- newWire ;;
instNr <- newInstNr ;;
let (i0, i1) := i0i1 in
addInstance (And2 instNr (wireNr i0) (wireNr i1) (wireNr o)) ;;
ret o.
Definition natWireNr (w : Signal Nat) : N :=
match w with
| NatNet n => n
end.
Definition natDelayDef (i : Signal Nat) : state Netlist (Signal Nat) :=
o <- newNat ;;
addInstance (NatDelay (natWireNr i) (natWireNr o)) ;;
ret o.
Definition addModCircuit (modBy : nat) (i0i1 : Signal Nat * Signal Nat) : state Netlist (Signal Nat) :=
o <- newNat ;;
let (i0, i1) := i0i1 in
addInstance (AddMod modBy (natWireNr i0) (natWireNr i1) (natWireNr o)) ;;
ret o.
(*
Note that loop is no problem for the netlist instance. We can "bend the wire" to create
a loop by creating a new wire b, using this to drive the input of the body circuit, and then
connect the second output of the body pair result, and fuse it with b to create a feedback loop
i.e. assign b := d.
*)
Definition loopNet (body : Signal Nat * Signal Nat -> state Netlist (Signal Nat * Signal Nat))
(a : Signal Nat) : state Netlist (Signal Nat) :=
b <- newNat ;;
cd <- body (a, b) ;;
let '(c, d) := cd in
addInstance (AssignNat (natWireNr b) (natWireNr d)) ;;
ret c.
Definition constNatNet (n : nat) : state Netlist (Signal Nat) :=
x <- newNat ;;
addInstance (ConstNat (natWireNr x) (N.of_nat n)) ;;
ret x.
Definition comparatorNet (ab : Signal Nat * Signal Nat) : state Netlist (Signal Bit) :=
cf <- newWire ;;
let (a, b) := ab in
addInstance (Comparator (natWireNr a) (natWireNr b) (wireNr cf)) ;;
ret cf.
Definition mux2Net (selab : Signal Bit * (Signal Nat * Signal Nat)) : state Netlist (Signal Nat) :=
let (sel, ab) := selab in
let (a, b) := ab in
o <- newNat ;;
addInstance (Mux2 (wireNr sel) (natWireNr a) (natWireNr b) (natWireNr o)) ;;
ret o.
(*
The netlist instance for Acorn plugs in the definitions above for creating
a circuit netlist using the stat monad as we go along.
*)
Instance AcornNetlist : Acorn (state Netlist) denoteSignal := {
inv := invGate;
and2 := and2Gate;
addMod := addModCircuit;
natDelay := natDelayDef;
loop := loopNet;
constNat := constNatNet;
comparator := comparatorNet;
mux2 := mux2Net;
}.
(*
Netlist functions for I/O ports which are only available for the
netlist interpretation.
*)
Definition inputBit (name : string) : state Netlist (Signal Bit) :=
o <- newWire ;;
addPort (InputBit name (wireNr o)) ;;
ret o.
Definition outputBit (driver : Signal Bit) (name : string) : state Netlist unit :=
addPort (OutputBit (wireNr driver) name).
Definition inputNat (name : string) : state Netlist (Signal Nat) :=
o <- newNat ;;
addPort (InputNat name (natWireNr o)) ;;
ret o.
Definition outputNat (driver : Signal Nat) (name : string) : state Netlist unit :=
addPort (OutputNat (natWireNr driver) name).
(* Declare the name of a circuit. *)
Definition setCircuitName (name : string) : state Netlist unit :=
ns <- get ;;
match ns with
| mkNetlist _ ic bc nc is ps =>
put (mkNetlist name ic bc nc is ps)
end.
(* Generate a netlist from a circuit name and a circuit graph. *)
Definition netlist (name : string) (circuit : state Netlist unit) : Netlist :=
execState (setCircuitName name ;; circuit) emptyNetist.
(* Generate the SystemVerilog string from the netlist data-type. *)
Local Open Scope string_scope.
Fixpoint insertCommas (lines : list string) : string :=
match lines with
| [] => ""
| [x] => x
| x::xs => x ++ ", " ++ insertCommas xs
end.
Definition portDeclaration (p : Port) : string :=
match p with
| InputBit name _ => "input logic " ++ name
| OutputBit _ name => "output logic " ++ name
| InputNat name _ => "input int unsigned " ++ name
| OutputNat _ name => "output int unsigned " ++ name
end.
Definition portDeclarations := map portDeclaration.
Definition showN (n : N) : string := NilEmpty.string_of_uint (N.to_uint n).
Definition declareBitNets (bc : N) : list string :=
match bc with
| N0 => []
| Npos bc' => [" logic net[0:" ++ showN (bc - 1) ++ "];"]
end.
Definition declareNatNets (nc : N) : list string :=
map (fun i => " int unsigned nat" ++ showN (N.of_nat i) ++ ";") (seq 0 (N.to_nat nc)).
Definition declareLocalNets (nl : Netlist) : list string :=
declareBitNets (bitCount nl) ++ declareNatNets (natCount nl).
Definition netS (n : N) : string := "net[" ++ showN n ++ "]".
Definition natS (n : N) : string := "nat" ++ showN n.
Definition instantiateComponent (component : Instance) : string :=
match component with
| Inv instNr i o => " not not_" ++ showN instNr ++ " (" ++
netS o ++ ", " ++ netS i ++ ");"
| And2 instNr i0 i1 o => " and and_" ++ showN instNr ++ " (" ++ netS o ++ ", " ++ netS i0 ++
", " ++ netS i1 ++ ");"
| AddMod modVal i0 i1 o => " assign " ++ natS o ++ " = (" ++ natS i0 ++ " + " ++
natS i1 ++ ") % " ++ showN (N.of_nat modVal) ++ ";"
| NatDelay i o => " always_ff @(posedge clk) "
++ natS o ++ " <= rst ? 0 : " ++ natS i ++ ";"
| AssignNat n v => " assign " ++ natS n ++ " = " ++ natS v ++ ";"
| ConstNat n v => " assign " ++ natS n ++ " = " ++ showN v ++ ";"
| Comparator a b cf => " assign " ++ netS cf ++ " = " ++ natS a ++ " == " ++ natS b ++ ";"
| Mux2 sel a b o => " assign " ++ natS o ++ " = " ++ netS sel ++ " ? " ++ natS a ++ " : " ++ natS b ++ ";"
end.
Definition instantiateComponents := map instantiateComponent.
Definition declarePorts (pl : list Port) : string :=
" (input logic clk, input logic rst, " ++ insertCommas (portDeclarations pl) ++ ")".
Definition wireUpPort (p : Port) : string :=
match p with
| InputBit name i => " assign " ++ netS i ++ " = " ++ name ++ ";"
| OutputBit i name => " assign " ++ name ++ " = " ++ netS i ++ ";"
| InputNat name i => " assign " ++ natS i ++ " = " ++ name ++ ";"
| OutputNat i name => " assign " ++ name ++ " = " ++ natS i ++ ";"
end.
Definition wireUpPorts := map wireUpPort.
Definition systemVerilogLines (nl : Netlist) : list string :=
["module " ++ netlistName nl ++ declarePorts (ports nl) ++ ";";
"timeunit 1ns; timeprecision 1ns;"] ++
declareLocalNets nl ++
wireUpPorts (ports nl) ++
instantiateComponents (instances nl) ++
["endmodule"].
Fixpoint unlines (lines : list string) : string :=
match lines with
| [] => ""
| x::xs => x ++ "\n" ++ unlines xs
end.
Definition systemVerilog (name : string) (nl : state Netlist unit ) : string :=
unlines (systemVerilogLines (netlist name nl)).
(* A nandGate netlist generation example. *)
Definition nandGate : state Netlist unit :=
i0 <- inputBit "i0" ;;
i1 <- inputBit "i1" ;;
o1 <- and2 (i0, i1) ;;
o <- inv o1 ;;
outputBit o "o".
Redirect "nandgate.sv" Compute (systemVerilog "nandGate" nandGate).
Definition addmod : state Netlist unit :=
a <- inputNat "a" ;;
b <- inputNat "b" ;;
c <- addMod 6 (a, b) ;;
outputNat c "c".
Redirect "addmod.sv" Compute (systemVerilog "addmod" addmod).
Definition delay1 : state Netlist unit :=
a <- inputNat "a" ;;
a1 <- natDelay a ;;
outputNat a1 "a1".
Redirect "delay1.sv" Compute (systemVerilog "delay1" delay1).
Definition pipe2 : state Netlist unit :=
a <- inputNat "a" ;;
a1 <- natDelay a ;;
a2 <- natDelay a1 ;;
outputNat a2 "a2".
Redirect "pipe2.sv" Compute (systemVerilog "pipe2" pipe2).
Definition counter6 {acorn} {signal} `{Acorn acorn signal} : signal Nat -> acorn (signal Nat) :=
loop (addMod 6 >=> natDelay >=> fork2).
Definition counter6Top : state Netlist unit :=
one <- constNat 1 ;;
count6 <- counter6 one ;;
outputNat count6 "count6".
Redirect "counter6.sv" Compute (systemVerilog "counter6" counter6Top).
Definition counter6by4 : state Netlist unit :=
zero <- constNat 0 ;;
one <- constNat 1 ;;
three <- constNat 3 ;;
count4 <- loop (addMod 4 >=> natDelay >=> fork2) one ;;
is3 <- comparator (count4, three) ;;
incVal <- mux2 (is3, (one, zero)) ;;
count6by4 <- loop (addMod 6 >=> natDelay >=> fork2) incVal ;;
outputNat count6by4 "count6by4".
Redirect "counter6by4.sv" Compute (systemVerilog "counter6by4" counter6by4).
(* An example of a nested loop. *)
Definition nestedloop : state Netlist unit :=
one <- constNat 1 ;;
o <- loop (snD natDelay >=> addMod 512 >=> loop (addMod 512 >=> natDelay >=> fork2) >=> fork2) one ;;
outputNat o "o".
Redirect "nestedloop.sv" Compute (systemVerilog "nestedloop" nestedloop).
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:32:05 03/25/2015
// Design Name:
// Module Name: RF
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RF(Data_in,Select,Acc_in,Data_out,Acc_out,RF_we,Acc_we,RF_clk,FG_pair,b_out,a_out,dat_out
);
input[7:0] Data_in;
input[2:0] Select;
input[7:0] Acc_in;
output[7:0] Data_out;
output[7:0] Acc_out;
output[15:0] FG_pair;
input RF_we;
input Acc_we;
input RF_clk;
output[7:0] b_out,a_out,dat_out;
reg[7:0] Data_out;
reg[7:0] Acc,B,C,D,E,F,G;
initial
begin
Acc <= 8'h49;
B <= 8'h06;
C <= 8'h06;
end
always @(posedge RF_clk)
begin
case(Select)
3'b000: Acc <= (RF_we ? Data_in: Acc);
3'b001: B <= (RF_we ? Data_in: B);
3'b010: C <= (RF_we ? Data_in: C);
3'b011: D <= (RF_we ? Data_in: D);
3'b100: E <= (RF_we ? Data_in: E);
3'b101: F <= (RF_we ? Data_in: F);
3'b110: G <= (RF_we ? Data_in: G);
endcase
if (Select != 3'b000)
Acc <= Acc_we ? Acc_in : Acc;
end
always @(Select or Acc or B or C or D or E or F or G)
begin
case (Select)
3'b000: Data_out <= Acc;
3'b001: Data_out <= B;
3'b010: Data_out <= C;
3'b011: Data_out <= D;
3'b100: Data_out <= E;
3'b101: Data_out <= F;
3'b110: Data_out <= G;
endcase
end
assign Acc_out = Acc;
assign FG_pair = {F,G};
assign b_out = B;
assign a_out = Acc;
assign dat_out = Data_out;
endmodule
|
`default_nettype none
module main (input wire clk,
input wire sw_in,
output wire sw_out);
//-- Configure the pull-up resistors for clk and rst inputs
wire sw_in2, sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(sw_in),
.D_IN_0(sw_in2)
);
//-- Sw is the signal from the switch-button, with standard logic and pull-ups
//-- activated
assign sw = ~sw_in2;
//-- Instanciate the debounce circuit
debounce d1 (
.clk(clk),
.sw_in(sw),
.sw_out(sw_out)
);
endmodule // main
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//-- Debug!!!
//assign sw_out = sw_in;
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A2BB2O_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2O_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
// Date : Sat Apr 1 16:02:47 2017
// Host : g-tune2016 running 64-bit Ubuntu 16.04.2 LTS
// Command : write_verilog -force -mode funcsim
// /home/minoru/FPGA/Zybo/Chapter9/vgagraph/vgagraph/src/vgagraph_fifo/vgagraph_fifo_sim_netlist.v
// Design : vgagraph_fifo
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "vgagraph_fifo,fifo_generator_v13_1_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
(* NotValidForBitStream *)
module vgagraph_fifo
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [31:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [15:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire [31:0]din;
wire [15:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [10:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "16" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "11" *)
(* C_RD_DEPTH = "2048" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "11" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
vgagraph_fifo_fifo_generator_v13_1_3 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[10:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module vgagraph_fifo_blk_mem_gen_generic_cstr
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[10] ,
din);
output [15:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [10:0]\gc0.count_d1_reg[10] ;
input [31:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire [31:0]din;
wire [15:0]dout;
wire [10:0]\gc0.count_d1_reg[10] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
vgagraph_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.WEA(WEA),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module vgagraph_fifo_blk_mem_gen_prim_width
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[10] ,
din);
output [15:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [10:0]\gc0.count_d1_reg[10] ;
input [31:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire [31:0]din;
wire [15:0]dout;
wire [10:0]\gc0.count_d1_reg[10] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
vgagraph_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.WEA(WEA),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module vgagraph_fifo_blk_mem_gen_prim_wrapper
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[10] ,
din);
output [15:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [10:0]\gc0.count_d1_reg[10] ;
input [31:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [9:0]Q;
wire [0:0]WEA;
wire [31:0]din;
wire [15:0]dout;
wire [10:0]\gc0.count_d1_reg[10] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({din[15:0],din[31:16]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(WEA),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({WEA,WEA,WEA,WEA}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module vgagraph_fifo_blk_mem_gen_top
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[10] ,
din);
output [15:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [10:0]\gc0.count_d1_reg[10] ;
input [31:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire [31:0]din;
wire [15:0]dout;
wire [10:0]\gc0.count_d1_reg[10] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
vgagraph_fifo_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.WEA(WEA),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *)
module vgagraph_fifo_blk_mem_gen_v8_3_5
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[10] ,
din);
output [15:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [10:0]\gc0.count_d1_reg[10] ;
input [31:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire [31:0]din;
wire [15:0]dout;
wire [10:0]\gc0.count_d1_reg[10] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
vgagraph_fifo_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.Q(Q),
.WEA(WEA),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module vgagraph_fifo_blk_mem_gen_v8_3_5_synth
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[10] ,
din);
output [15:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [10:0]\gc0.count_d1_reg[10] ;
input [31:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire [31:0]din;
wire [15:0]dout;
wire [10:0]\gc0.count_d1_reg[10] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
vgagraph_fifo_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.WEA(WEA),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module vgagraph_fifo_clk_x_pntrs
(v1_reg,
WR_PNTR_RD,
v1_reg_0,
RD_PNTR_WR,
Q,
\gc0.count_reg[9] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]v1_reg;
output [1:0]WR_PNTR_RD;
output [3:0]v1_reg_0;
output [9:0]RD_PNTR_WR;
input [10:0]Q;
input [7:0]\gc0.count_reg[9] ;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]AR;
wire [10:0]Q;
wire [9:0]RD_PNTR_WR;
wire [1:0]WR_PNTR_RD;
wire [8:0]bin2gray;
wire [7:0]\gc0.count_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ;
wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ;
wire [7:0]gray2bin;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire p_0_out;
wire [8:1]p_22_out;
wire [9:0]p_3_out;
wire [10:0]p_4_out;
wire [9:9]p_5_out;
wire [10:10]p_6_out;
wire rd_clk;
wire [10:0]rd_pntr_gc;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire wr_clk;
wire [9:0]wr_pntr_gc;
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(p_22_out[1]),
.I1(Q[2]),
.I2(p_22_out[2]),
.I3(Q[3]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(p_22_out[1]),
.I1(\gc0.count_reg[9] [0]),
.I2(p_22_out[2]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(p_22_out[3]),
.I1(Q[4]),
.I2(p_22_out[4]),
.I3(Q[5]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(p_22_out[3]),
.I1(\gc0.count_reg[9] [2]),
.I2(p_22_out[4]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(p_22_out[5]),
.I1(Q[6]),
.I2(p_22_out[6]),
.I3(Q[7]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(p_22_out[5]),
.I1(\gc0.count_reg[9] [4]),
.I2(p_22_out[6]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(p_22_out[7]),
.I1(Q[8]),
.I2(p_22_out[8]),
.I3(Q[9]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(p_22_out[7]),
.I1(\gc0.count_reg[9] [6]),
.I2(p_22_out[8]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg_0[3]));
vgagraph_fifo_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
vgagraph_fifo_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.wr_clk(wr_clk));
vgagraph_fifo_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\gnxpm_cdc.wr_pntr_bin_reg[8] ({p_0_out,gray2bin}),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_5_out),
.rd_clk(rd_clk));
vgagraph_fifo_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.\gnxpm_cdc.rd_pntr_bin_reg[9] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 }),
.out(p_6_out),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(p_6_out),
.Q(RD_PNTR_WR[9]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[9]_i_1
(.I0(Q[9]),
.I1(Q[10]),
.O(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[10]),
.Q(rd_pntr_gc[10]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[1]),
.Q(p_22_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[2]),
.Q(p_22_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[3]),
.Q(p_22_out[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[4]),
.Q(p_22_out[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[5]),
.Q(p_22_out[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[6]),
.Q(p_22_out[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[7]),
.Q(p_22_out[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out),
.Q(p_22_out[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_5_out),
.Q(WR_PNTR_RD[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [0]),
.I1(\gic0.gc0.count_d2_reg[9] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [1]),
.I1(\gic0.gc0.count_d2_reg[9] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [2]),
.I1(\gic0.gc0.count_d2_reg[9] [3]),
.O(bin2gray[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [3]),
.I1(\gic0.gc0.count_d2_reg[9] [4]),
.O(bin2gray[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [4]),
.I1(\gic0.gc0.count_d2_reg[9] [5]),
.O(bin2gray[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [5]),
.I1(\gic0.gc0.count_d2_reg[9] [6]),
.O(bin2gray[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [6]),
.I1(\gic0.gc0.count_d2_reg[9] [7]),
.O(bin2gray[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [7]),
.I1(\gic0.gc0.count_d2_reg[9] [8]),
.O(bin2gray[7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[8]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [8]),
.I1(\gic0.gc0.count_d2_reg[9] [9]),
.O(bin2gray[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[9] [9]),
.Q(wr_pntr_gc[9]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module vgagraph_fifo_compare
(ram_empty_fb_i_reg,
v1_reg,
\gnxpm_cdc.wr_pntr_bin_reg[7] ,
\gc0.count_d1_reg[10] ,
rd_en,
out,
comp1);
output ram_empty_fb_i_reg;
input [0:0]v1_reg;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
input \gc0.count_d1_reg[10] ;
input rd_en;
input out;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
wire out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire [0:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gnxpm_cdc.wr_pntr_bin_reg[7] [2:0],v1_reg}));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,\gnxpm_cdc.wr_pntr_bin_reg[7] [3]}));
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module vgagraph_fifo_compare_3
(comp1,
v1_reg_0,
\gnxpm_cdc.wr_pntr_bin_reg[7] ,
\gc0.count_reg[10] );
output comp1;
input [0:0]v1_reg_0;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
input \gc0.count_reg[10] ;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire \gc0.count_reg[10] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
wire [0:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gnxpm_cdc.wr_pntr_bin_reg[7] [2:0],v1_reg_0}));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_reg[10] ,\gnxpm_cdc.wr_pntr_bin_reg[7] [3]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module vgagraph_fifo_compare__parameterized0
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module vgagraph_fifo_compare__parameterized1
(ram_full_fb_i_reg,
v1_reg_0,
wr_rst_busy,
out,
wr_en,
comp1);
output ram_full_fb_i_reg;
input [4:0]v1_reg_0;
input wr_rst_busy;
input out;
input wr_en;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire comp2;
wire out;
wire ram_full_fb_i_reg;
wire [4:0]v1_reg_0;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
LUT5 #(
.INIT(32'h55550400))
ram_full_i_i_1
(.I0(wr_rst_busy),
.I1(comp2),
.I2(out),
.I3(wr_en),
.I4(comp1),
.O(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module vgagraph_fifo_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output wr_rst_busy;
output [15:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
wire [31:0]din;
wire [15:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.wr_n_1 ;
wire [4:1]\gras.rsts/c0/v1_reg ;
wire [4:1]\gras.rsts/c1/v1_reg ;
wire [10:0]p_0_out;
wire [9:0]p_12_out;
wire [9:0]p_22_out;
wire [10:1]p_23_out;
wire p_2_out;
wire rd_clk;
wire rd_en;
wire [9:2]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
wire [1:0]wr_rst_i;
vgagraph_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.Q(p_0_out),
.RD_PNTR_WR(p_23_out),
.WR_PNTR_RD({p_22_out[9],p_22_out[0]}),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.rd_clk(rd_clk),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ),
.wr_clk(wr_clk));
vgagraph_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.Q(p_0_out),
.WR_PNTR_RD({p_22_out[9],p_22_out[0]}),
.empty(empty),
.\gc0.count_d1_reg[9] (rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[7] (\gras.rsts/c0/v1_reg ),
.\gnxpm_cdc.wr_pntr_bin_reg[7]_0 (\gras.rsts/c1/v1_reg ),
.out(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en));
vgagraph_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.Q(p_12_out),
.RD_PNTR_WR(p_23_out),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.full(full),
.out(rst_full_ff_i),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
vgagraph_fifo_memory \gntv_or_sync_fifo.mem
(.Q(p_12_out),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[10] (p_0_out),
.out(rd_rst_i[0]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
vgagraph_fifo_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module vgagraph_fifo_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output wr_rst_busy;
output [15:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
wire [31:0]din;
wire [15:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
vgagraph_fifo_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "16" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "zynq" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "11" *)
(* C_RD_DEPTH = "2048" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "11" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *)
module vgagraph_fifo_fifo_generator_v13_1_3
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [31:0]din;
input wr_en;
input rd_en;
input [10:0]prog_empty_thresh;
input [10:0]prog_empty_thresh_assert;
input [10:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [15:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [10:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire [31:0]din;
wire [15:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[10] = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
vgagraph_fifo_fifo_generator_v13_1_3_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *)
module vgagraph_fifo_fifo_generator_v13_1_3_synth
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output wr_rst_busy;
output [15:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
wire [31:0]din;
wire [15:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
vgagraph_fifo_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "memory" *)
module vgagraph_fifo_memory
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[10] ,
din);
output [15:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [10:0]\gc0.count_d1_reg[10] ;
input [31:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire [31:0]din;
wire [15:0]dout;
wire [10:0]\gc0.count_d1_reg[10] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
vgagraph_fifo_blk_mem_gen_v8_3_5 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.WEA(WEA),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module vgagraph_fifo_rd_bin_cntr
(ram_empty_fb_i_reg,
Q,
ram_empty_fb_i_reg_0,
\gc0.count_d1_reg[9]_0 ,
v1_reg,
v1_reg_0,
WR_PNTR_RD,
E,
rd_clk,
AR);
output ram_empty_fb_i_reg;
output [10:0]Q;
output ram_empty_fb_i_reg_0;
output [7:0]\gc0.count_d1_reg[9]_0 ;
output [0:0]v1_reg;
output [0:0]v1_reg_0;
input [1:0]WR_PNTR_RD;
input [0:0]E;
input rd_clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [10:0]Q;
wire [1:0]WR_PNTR_RD;
wire \gc0.count[10]_i_2_n_0 ;
wire [7:0]\gc0.count_d1_reg[9]_0 ;
wire [10:0]plusOp;
wire ram_empty_fb_i_reg;
wire ram_empty_fb_i_reg_0;
wire rd_clk;
wire [10:0]rd_pntr_plus1;
wire [0:0]v1_reg;
wire [0:0]v1_reg_0;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(rd_pntr_plus1[0]),
.O(plusOp[0]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[10]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [6]),
.I1(\gc0.count_d1_reg[9]_0 [4]),
.I2(\gc0.count[10]_i_2_n_0 ),
.I3(\gc0.count_d1_reg[9]_0 [5]),
.I4(\gc0.count_d1_reg[9]_0 [7]),
.I5(rd_pntr_plus1[10]),
.O(plusOp[10]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[10]_i_2
(.I0(\gc0.count_d1_reg[9]_0 [3]),
.I1(\gc0.count_d1_reg[9]_0 [1]),
.I2(rd_pntr_plus1[1]),
.I3(rd_pntr_plus1[0]),
.I4(\gc0.count_d1_reg[9]_0 [0]),
.I5(\gc0.count_d1_reg[9]_0 [2]),
.O(\gc0.count[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(rd_pntr_plus1[0]),
.I1(rd_pntr_plus1[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(rd_pntr_plus1[0]),
.I1(rd_pntr_plus1[1]),
.I2(\gc0.count_d1_reg[9]_0 [0]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(rd_pntr_plus1[1]),
.I1(rd_pntr_plus1[0]),
.I2(\gc0.count_d1_reg[9]_0 [0]),
.I3(\gc0.count_d1_reg[9]_0 [1]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [0]),
.I1(rd_pntr_plus1[0]),
.I2(rd_pntr_plus1[1]),
.I3(\gc0.count_d1_reg[9]_0 [1]),
.I4(\gc0.count_d1_reg[9]_0 [2]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [1]),
.I1(rd_pntr_plus1[1]),
.I2(rd_pntr_plus1[0]),
.I3(\gc0.count_d1_reg[9]_0 [0]),
.I4(\gc0.count_d1_reg[9]_0 [2]),
.I5(\gc0.count_d1_reg[9]_0 [3]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[10]_i_2_n_0 ),
.I1(\gc0.count_d1_reg[9]_0 [4]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[10]_i_2_n_0 ),
.I1(\gc0.count_d1_reg[9]_0 [4]),
.I2(\gc0.count_d1_reg[9]_0 [5]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [4]),
.I1(\gc0.count[10]_i_2_n_0 ),
.I2(\gc0.count_d1_reg[9]_0 [5]),
.I3(\gc0.count_d1_reg[9]_0 [6]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [5]),
.I1(\gc0.count[10]_i_2_n_0 ),
.I2(\gc0.count_d1_reg[9]_0 [4]),
.I3(\gc0.count_d1_reg[9]_0 [6]),
.I4(\gc0.count_d1_reg[9]_0 [7]),
.O(plusOp[9]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(rd_pntr_plus1[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(rd_pntr_plus1[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(rd_pntr_plus1[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [0]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [1]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [2]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [3]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [4]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [5]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [6]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [7]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(AR),
.Q(rd_pntr_plus1[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[10]),
.Q(rd_pntr_plus1[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[1]),
.Q(rd_pntr_plus1[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[2]),
.Q(\gc0.count_d1_reg[9]_0 [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[3]),
.Q(\gc0.count_d1_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[4]),
.Q(\gc0.count_d1_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[5]),
.Q(\gc0.count_d1_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[6]),
.Q(\gc0.count_d1_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[7]),
.Q(\gc0.count_d1_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[8]),
.Q(\gc0.count_d1_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp[9]),
.Q(\gc0.count_d1_reg[9]_0 [7]));
LUT3 #(
.INIT(8'h41))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(WR_PNTR_RD[0]),
.I2(Q[1]),
.O(v1_reg));
LUT3 #(
.INIT(8'h41))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(rd_pntr_plus1[0]),
.I1(WR_PNTR_RD[0]),
.I2(rd_pntr_plus1[1]),
.O(v1_reg_0));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(WR_PNTR_RD[1]),
.O(ram_empty_fb_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1__0
(.I0(rd_pntr_plus1[10]),
.I1(WR_PNTR_RD[1]),
.O(ram_empty_fb_i_reg_0));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module vgagraph_fifo_rd_logic
(empty,
out,
Q,
\gc0.count_d1_reg[9] ,
\gnxpm_cdc.wr_pntr_bin_reg[7] ,
\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ,
rd_clk,
AR,
rd_en,
WR_PNTR_RD);
output empty;
output out;
output [10:0]Q;
output [7:0]\gc0.count_d1_reg[9] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ;
input rd_clk;
input [0:0]AR;
input rd_en;
input [1:0]WR_PNTR_RD;
wire [0:0]AR;
wire [10:0]Q;
wire [1:0]WR_PNTR_RD;
wire [0:0]\c0/v1_reg ;
wire [0:0]\c1/v1_reg ;
wire empty;
wire [7:0]\gc0.count_d1_reg[9] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ;
wire \gras.rsts_n_2 ;
wire out;
wire rd_clk;
wire rd_en;
wire rpntr_n_0;
wire rpntr_n_12;
vgagraph_fifo_rd_status_flags_as \gras.rsts
(.AR(AR),
.E(\gras.rsts_n_2 ),
.empty(empty),
.\gc0.count_d1_reg[10] (rpntr_n_0),
.\gc0.count_reg[10] (rpntr_n_12),
.\gnxpm_cdc.wr_pntr_bin_reg[7] (\gnxpm_cdc.wr_pntr_bin_reg[7] ),
.\gnxpm_cdc.wr_pntr_bin_reg[7]_0 (\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ),
.out(out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ));
vgagraph_fifo_rd_bin_cntr rpntr
(.AR(AR),
.E(\gras.rsts_n_2 ),
.Q(Q),
.WR_PNTR_RD(WR_PNTR_RD),
.\gc0.count_d1_reg[9]_0 (\gc0.count_d1_reg[9] ),
.ram_empty_fb_i_reg(rpntr_n_0),
.ram_empty_fb_i_reg_0(rpntr_n_12),
.rd_clk(rd_clk),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module vgagraph_fifo_rd_status_flags_as
(empty,
out,
E,
v1_reg,
\gnxpm_cdc.wr_pntr_bin_reg[7] ,
\gc0.count_d1_reg[10] ,
v1_reg_0,
\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ,
\gc0.count_reg[10] ,
rd_clk,
AR,
rd_en);
output empty;
output out;
output [0:0]E;
input [0:0]v1_reg;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
input \gc0.count_d1_reg[10] ;
input [0:0]v1_reg_0;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ;
input \gc0.count_reg[10] ;
input rd_clk;
input [0:0]AR;
input rd_en;
wire [0:0]AR;
wire [0:0]E;
wire c0_n_0;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire \gc0.count_reg[10] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire [0:0]v1_reg;
wire [0:0]v1_reg_0;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
vgagraph_fifo_compare c0
(.comp1(comp1),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.\gnxpm_cdc.wr_pntr_bin_reg[7] (\gnxpm_cdc.wr_pntr_bin_reg[7] ),
.out(ram_empty_fb_i),
.ram_empty_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg(v1_reg));
vgagraph_fifo_compare_3 c1
(.comp1(comp1),
.\gc0.count_reg[10] (\gc0.count_reg[10] ),
.\gnxpm_cdc.wr_pntr_bin_reg[7] (\gnxpm_cdc.wr_pntr_bin_reg[7]_0 ),
.v1_reg_0(v1_reg_0));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[10]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module vgagraph_fifo_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
rd_clk,
wr_clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input rd_clk;
input wr_clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
vgagraph_fifo_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out),
.rd_clk(rd_clk));
vgagraph_fifo_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out),
.wr_clk(wr_clk));
vgagraph_fifo_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.in0(rd_rst_asreg),
.out(p_7_out),
.rd_clk(rd_clk));
vgagraph_fifo_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.in0(wr_rst_asreg),
.out(p_8_out),
.wr_clk(wr_clk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
rd_clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input rd_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
wire rd_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
wr_clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input wr_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
wire wr_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff_1
(AS,
out,
rd_clk,
in0);
output [0:0]AS;
input out;
input rd_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire rd_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff_2
(AS,
out,
wr_clk,
in0);
output [0:0]AS;
input out;
input wr_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire wr_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff__parameterized0
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [9:0]D;
input [9:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff__parameterized1
(D,
Q,
wr_clk,
AR);
output [10:0]D;
input [10:0]Q;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [10:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [10:0]Q_reg;
wire wr_clk;
assign D[10:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[10]),
.Q(Q_reg[10]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff__parameterized2
(out,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input [9:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module vgagraph_fifo_synchronizer_ff__parameterized3
(out,
\gnxpm_cdc.rd_pntr_bin_reg[9] ,
D,
wr_clk,
AR);
output [0:0]out;
output [8:0]\gnxpm_cdc.rd_pntr_bin_reg[9] ;
input [10:0]D;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [10:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [10:0]Q_reg;
wire \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.rd_pntr_bin_reg[9] ;
wire wr_clk;
assign out[0] = Q_reg[10];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[10]),
.Q(Q_reg[10]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[3]),
.I3(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ),
.I4(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[1]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[4]),
.I2(Q_reg[10]),
.O(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[10]),
.I2(Q_reg[4]),
.I3(Q_reg[5]),
.I4(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),
.I5(Q_reg[2]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[3]_i_1
(.I0(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),
.I1(Q_reg[5]),
.I2(Q_reg[4]),
.I3(Q_reg[10]),
.I4(Q_reg[3]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[3]_i_2
(.I0(Q_reg[9]),
.I1(Q_reg[8]),
.I2(Q_reg[7]),
.I3(Q_reg[6]),
.O(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[4]_i_1
(.I0(Q_reg[10]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(\gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ),
.I4(Q_reg[8]),
.I5(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[4]_i_2
(.I0(Q_reg[6]),
.I1(Q_reg[7]),
.O(\gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[10]),
.I4(Q_reg[8]),
.I5(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[6]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[6]),
.I2(Q_reg[7]),
.I3(Q_reg[10]),
.I4(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[10]),
.I3(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[8]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[8]),
.I2(Q_reg[10]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[9]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[10]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[9] [8]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module vgagraph_fifo_wr_bin_cntr
(v1_reg,
v1_reg_0,
Q,
RD_PNTR_WR,
E,
wr_clk,
AR);
output [4:0]v1_reg;
output [4:0]v1_reg_0;
output [9:0]Q;
input [9:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire \gic0.gc0.count[9]_i_2_n_0 ;
wire [9:0]p_13_out;
wire [9:0]plusOp__0;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire [9:0]wr_pntr_plus2;
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(wr_pntr_plus2[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(wr_pntr_plus2[1]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[2]),
.I3(wr_pntr_plus2[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(wr_pntr_plus2[2]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[3]),
.I4(wr_pntr_plus2[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(wr_pntr_plus2[3]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[0]),
.I3(wr_pntr_plus2[2]),
.I4(wr_pntr_plus2[4]),
.I5(wr_pntr_plus2[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(wr_pntr_plus2[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(wr_pntr_plus2[6]),
.I2(wr_pntr_plus2[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[8]_i_1
(.I0(wr_pntr_plus2[6]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(wr_pntr_plus2[7]),
.I3(wr_pntr_plus2[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[9]_i_1
(.I0(wr_pntr_plus2[7]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(wr_pntr_plus2[6]),
.I3(wr_pntr_plus2[8]),
.I4(wr_pntr_plus2[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gic0.gc0.count[9]_i_2
(.I0(wr_pntr_plus2[5]),
.I1(wr_pntr_plus2[3]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[0]),
.I4(wr_pntr_plus2[2]),
.I5(wr_pntr_plus2[4]),
.O(\gic0.gc0.count[9]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(AR),
.Q(p_13_out[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[1]),
.Q(p_13_out[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[2]),
.Q(p_13_out[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[3]),
.Q(p_13_out[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[4]),
.Q(p_13_out[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[5]),
.Q(p_13_out[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[6]),
.Q(p_13_out[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[7]),
.Q(p_13_out[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[8]),
.Q(p_13_out[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[9]),
.Q(p_13_out[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(AR),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(wr_pntr_plus2[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(wr_pntr_plus2[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(wr_pntr_plus2[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(wr_pntr_plus2[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(wr_pntr_plus2[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(wr_pntr_plus2[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(wr_pntr_plus2[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(wr_pntr_plus2[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_13_out[0]),
.I1(RD_PNTR_WR[0]),
.I2(p_13_out[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(wr_pntr_plus2[0]),
.I1(RD_PNTR_WR[0]),
.I2(wr_pntr_plus2[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_13_out[2]),
.I1(RD_PNTR_WR[2]),
.I2(p_13_out[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(wr_pntr_plus2[2]),
.I1(RD_PNTR_WR[2]),
.I2(wr_pntr_plus2[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_13_out[4]),
.I1(RD_PNTR_WR[4]),
.I2(p_13_out[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(wr_pntr_plus2[4]),
.I1(RD_PNTR_WR[4]),
.I2(wr_pntr_plus2[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_13_out[6]),
.I1(RD_PNTR_WR[6]),
.I2(p_13_out[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(wr_pntr_plus2[6]),
.I1(RD_PNTR_WR[6]),
.I2(wr_pntr_plus2[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_13_out[8]),
.I1(RD_PNTR_WR[8]),
.I2(p_13_out[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(wr_pntr_plus2[8]),
.I1(RD_PNTR_WR[8]),
.I2(wr_pntr_plus2[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg_0[4]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module vgagraph_fifo_wr_logic
(full,
WEA,
Q,
wr_clk,
out,
wr_en,
AR,
RD_PNTR_WR,
wr_rst_busy);
output full;
output [0:0]WEA;
output [9:0]Q;
input wr_clk;
input out;
input wr_en;
input [0:0]AR;
input [9:0]RD_PNTR_WR;
input wr_rst_busy;
wire [0:0]AR;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [0:0]WEA;
wire [4:0]\c1/v1_reg ;
wire [4:0]\c2/v1_reg ;
wire full;
wire out;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
vgagraph_fifo_wr_status_flags_as \gwas.wsts
(.E(WEA),
.full(full),
.out(out),
.v1_reg(\c1/v1_reg ),
.v1_reg_0(\c2/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
vgagraph_fifo_wr_bin_cntr wpntr
(.AR(AR),
.E(WEA),
.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.v1_reg(\c1/v1_reg ),
.v1_reg_0(\c2/v1_reg ),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module vgagraph_fifo_wr_status_flags_as
(full,
E,
v1_reg,
v1_reg_0,
wr_clk,
out,
wr_en,
wr_rst_busy);
output full;
output [0:0]E;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input wr_clk;
input out;
input wr_en;
input wr_rst_busy;
wire [0:0]E;
wire c2_n_0;
wire comp1;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
vgagraph_fifo_compare__parameterized0 c1
(.comp1(comp1),
.v1_reg(v1_reg));
vgagraph_fifo_compare__parameterized1 c2
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_full_fb_i_reg(c2_n_0),
.v1_reg_0(v1_reg_0),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(out),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(out),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O21A_FUNCTIONAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_FUNCTIONAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 14:00:27 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_transform_0_1/system_affine_transform_0_1_stub.v
// Design : system_affine_transform_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "affine_block_wrapper,Vivado 2016.4" *)
module system_affine_transform_0_1(a00, a01, a10, a11, x_in, x_out, y_in, y_out)
/* synthesis syn_black_box black_box_pad_pin="a00[31:0],a01[31:0],a10[31:0],a11[31:0],x_in[9:0],x_out[9:0],y_in[9:0],y_out[9:0]" */;
input [31:0]a00;
input [31:0]a01;
input [31:0]a10;
input [31:0]a11;
input [9:0]x_in;
output [9:0]x_out;
input [9:0]y_in;
output [9:0]y_out;
endmodule
|
/*************************************************************************
* *
* Copyright (C) 2016,2017 Alves, Fredy. *
* All rights reserved. Email: [email protected] *
* *
* This design is free software; you can redistribute it and/or *
* modify it under the terms of EITHER: *
* (1) The GNU Lesser General Public License as published by the Free *
* Software Foundation; either version 2.1 of the License, or (at *
* your option) any later version. The text of the GNU Lesser *
* General Public License is included with this design in the *
* file LICENSE. *
* *
* This design is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the files *
* LICENSE.TXT and LICENSE-BSD.TXT for more details. *
* *
*************************************************************************/
//`define DEBUG 2
//`define DEBUGOUT 3
//`define DEBUGIN 4
module inputs_mem2 #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512)
(
input clk,
input reset_n,
// Read Request
output [ADDR_LMT-1:0] rd_req_addr,
output [MDATA-1:0] rd_req_mdata,
output reg rd_req_en,
input rd_req_almostfull,
// Read Response
input rd_rsp_valid,
input [MDATA-1:0] rd_rsp_mdata,
input [CACHE_WIDTH-1:0] rd_rsp_data,
output [CACHE_WIDTH-1:0] mem_out,
input [31:0] addr_mem_out,
// Done output signal
output reg done
);
reg execcounter_clr;
reg data_buf_we;
reg [CACHE_WIDTH-1:0] floatsReg, floatsReg2, floatsReg3, floatsReg4, floatsReg5, floatsReg6;
reg [2:0] counter_aux = 0;
// --- Address counter
reg addr_cnt_inc;
reg addr_cnt_clr;
reg addr_cnt_start;
reg [31:0] addr_cnt;
always @ (posedge clk) begin
if(!reset_n)
addr_cnt <= 0;
else
if(addr_cnt_inc)
addr_cnt <= addr_cnt + 1;
else if(addr_cnt_clr)
addr_cnt <= 'd0;
else if (addr_cnt_start)
addr_cnt <= 'd1;
end
// --- Address counter continuous
reg addr_cnt_continuous_inc;
reg addr_cnt_continuous_clr;
reg [31:0] addr_cnt_continuous;
always @ (posedge clk) begin
if(!reset_n)
addr_cnt_continuous <= 0;
else
if(addr_cnt_continuous_inc)
addr_cnt_continuous <= addr_cnt_continuous + 1;
else if(addr_cnt_continuous_clr)
addr_cnt_continuous <= 'd0;
end
// --- Address counter continuous mem
reg addr_cnt_continuous_mem_inc;
reg addr_cnt_continuous_mem_clr;
reg [31:0] addr_cnt_continuous_mem;
always @ (posedge clk) begin
if(!reset_n)
addr_cnt_continuous_mem <= 0;
else
if(addr_cnt_continuous_mem_inc)
addr_cnt_continuous_mem <= addr_cnt_continuous_mem + 1;
else if(addr_cnt_continuous_mem_clr)
addr_cnt_continuous_mem <= 'd0;
end
assign rd_req_mdata = addr_cnt;
// --- Rd and Wr Addr
assign rd_req_addr = addr_cnt_continuous;
reg t_start;
assign w_done = 1'b1;
wire[511:0] wIn_mem;
assign wIn_mem = (addr_cnt==0)?floatsReg:(addr_cnt==1)?floatsReg2:(addr_cnt==2)?floatsReg3:(addr_cnt==3)?floatsReg4:512'b01000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100010000000101011110101110000101000100000001010111101011100001010001000000010101111010111000010100;
/* localparam [4:0]
FSM_RD_IDLE = 0,
FSM_RD1 = 1,
FSM_RD2 = 2,
FSM_RD3 = 3,
FSM_RD4 = 4;
reg [4:0] fsm_rds;
always @ (posedge clk)
begin
if(!reset_n) fsm_rds <= 0;
else
begin
case(fsm_rds)
FSM_RD_IDLE:
begin
fsm_rds = FSM_RD1;
end
FSM_RD1:
begin
if(rd_rsp_valid)
begin
fsm_rds = FSM_RD2;
floatsReg = rd_rsp_data;
end
end
FSM_RD2:
begin
if(rd_rsp_valid)
begin
fsm_rds = FSM_RD3;
floatsReg2 = rd_rsp_data;
end
end
FSM_RD3:
begin
if(rd_rsp_valid)
begin
fsm_rds = FSM_RD4;
floatsReg3 = rd_rsp_data;
end
end
FSM_RD4:
begin
if(rd_rsp_valid)
begin
fsm_rds = FSM_RD1;
floatsReg4 = rd_rsp_data;
end
end
endcase
end
end */
always@(posedge clk)
begin
if(!reset_n) begin
floatsReg <= 0;
floatsReg2 <= 0;
floatsReg3 <= 0;
floatsReg4 <= 0;
floatsReg5 <= 0;
floatsReg6 <= 0;
end
else begin
if(rd_rsp_valid)
begin
case(addr_cnt)
'd0:
begin
floatsReg <= rd_rsp_data;
end
'd1:
begin
floatsReg2 <= rd_rsp_data;
end
'd2:
begin
floatsReg3 <= rd_rsp_data;
end
'd3:
begin
floatsReg4 <= rd_rsp_data;
end
endcase // case (addr_cnt)
end
end
end // always@ (posedge clk)
reg mem_we;
wire [511:0] out_Mem1;
ram_2_ports_d2000_w512 rammem1 (
.clock(clk),
.data(wIn_mem),
.rdaddress(addr_mem_out),
.wraddress(addr_cnt_continuous_mem),
.wren(mem_we),
.q(mem_out));
assign w_outGrid = out_Mem1;
localparam [4:0]
FSM_IDLE = 4'd0,
FSM_RD_REQ = 4'd1,
FSM_RD_RSP = 4'd2,
FSM_WR_REQ = 4'd3,
FSM_RUN_COLLISIONS = 4'd4,
FSM_WAIT_COLLISIONS = 4'd5,
FSM_WR_RSP = 4'd6,
FSM_RD_REQ2 = 4'd7,
FSM_RD_RSP2 = 4'd8,
ENDSTATE = 4'd9,
FSM_WR_MEM = 4'd10,
FSM_WR_MEM_EN = 4'd11,
FSM_AUX1 = 4'd12,
DONESTATE = 4'd13,
FSM_RD_DONE = 4'd14,
FSM_RD_RSP3 = 4'd15;
reg [4:0] fsm_cs, fsm_ns;
reg [31:0] r_cnt,n_cnt,l_cnt,l_cnt2;
/*initial begin
$monitor ("#################### DATA ################### \n
fsm_cs=%d #
l_cnt=%d #
addr_cnt_continuous=%d #
done=%b #
############################################
\n\n\n\n\n\n\n\n\n\n",
fsm_cs,
l_cnt,
addr_cnt_continuous,
done
);
end
initial begin
$monitor ("#################### DATA ################### \n
done=%b #
############################################
\n\n\n\n\n\n\n\n\n\n",
done
);
end */
always @ (posedge clk)
begin
if(!reset_n) fsm_cs <= FSM_IDLE;
else fsm_cs <= fsm_ns;
end
always@(posedge clk) r_cnt <= (!reset_n) ? 'd0 : n_cnt;
always @ *
begin
fsm_ns = fsm_cs;
addr_cnt_inc = 1'b0;
addr_cnt_clr = 1'b0;
addr_cnt_start = 1'b0;
addr_cnt_continuous_inc = 1'b0;
addr_cnt_continuous_clr = 1'b0;
addr_cnt_continuous_mem_inc = 1'b0;
addr_cnt_continuous_mem_clr = 1'b0;
data_buf_we = 1'b0;
rd_req_en = 1'b0;
done = 1'b0;
t_start = 1'b0;
n_cnt = r_cnt;
mem_we = 1'b0;
case(fsm_cs)
FSM_IDLE:
begin
fsm_ns = FSM_RD_REQ;
n_cnt = 'd0;
l_cnt = 'd0;
l_cnt2 = 'd0;
end
FSM_RD_REQ:
begin
// If there's no more data to copy
if(floatsReg[7:0] == 8'b11111111)
begin
fsm_ns = FSM_RD_REQ2;
addr_cnt_start = 1'b1;
l_cnt <= floatsReg[159:128];
$display("wwwb l_cnt_inmem: %d", l_cnt);
//addr_cnt_continuous_inc = 1'b1;
end
else
begin
if(addr_cnt >= 1'b1)
begin
addr_cnt_clr = 1'b1;
end
else
begin
if(!rd_req_almostfull)
begin
rd_req_en = 1'b1;
fsm_ns = FSM_RD_RSP;
end
end
end
end
FSM_RD_RSP:
begin
if(rd_rsp_valid)
begin
addr_cnt_inc = 1'b1;
fsm_ns = FSM_RD_REQ;
end
end
FSM_RD_REQ2:
begin
if(addr_cnt >= 5)
begin
fsm_ns = FSM_RD_DONE;
addr_cnt_clr = 1'b1;
//$display("add_cnt_continuous after reading spheres: %d", addr_cnt_continuous);
end
else
begin
if(!rd_req_almostfull)
begin
rd_req_en = 1'b1;
fsm_ns = FSM_RD_RSP2;
end
end
end
FSM_RD_RSP2:
begin
addr_cnt_inc = 1'b1;
addr_cnt_continuous_inc = 1'b1;
fsm_ns = FSM_RD_REQ2;
end
FSM_RD_DONE:
begin
if(addr_cnt >= 4)
begin
fsm_ns = FSM_WR_MEM;
addr_cnt_clr = 1'b1;
//$display("add_cnt_continuous after reading spheres: %d", addr_cnt_continuous);
end
else
begin
fsm_ns = FSM_RD_RSP3;
end
end
FSM_RD_RSP3:
begin
if(rd_rsp_valid)
begin
addr_cnt_inc = 1'b1;
fsm_ns = FSM_RD_DONE;
end
end
FSM_WR_MEM:
begin
if(addr_cnt >= 4)
begin
if(addr_cnt_continuous_mem >= l_cnt)
begin
fsm_ns = ENDSTATE;
addr_cnt_clr = 1'b1;
addr_cnt_continuous_clr = 1'b1;
addr_cnt_continuous_mem_clr = 1'b1;
end
else
begin
fsm_ns = FSM_RD_REQ2;
addr_cnt_clr = 1'b1;
end
end
else
begin
/*if(!rd_req_almostfull)
begin
rd_req_en = 1'b1;*/
fsm_ns = FSM_WR_MEM_EN;
//end
end
end
FSM_WR_MEM_EN:
begin
mem_we = 1'b1;
addr_cnt_inc = 1'b1;
addr_cnt_continuous_mem_inc = 1'b1;
fsm_ns = FSM_WR_MEM;
end
ENDSTATE:
begin
done = 1'b1;
end
endcase
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire GCLK_b ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b, m0, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Transparent Data Latch with Asynchronous Preset and Gate Enable
// /___/ /\ Filename : LDPE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 11/01/11 - Disable timing check when set reset active (CR633224)
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LDPE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_G_INVERTED = 1'b0,
parameter [0:0] IS_PRE_INVERTED = 1'b0
)(
output Q,
input D,
input G,
input GE,
input PRE
);
wire [0:0] IS_G_INVERTED_BIN;
wire [0:0] IS_PRE_INVERTED_BIN;
reg Q_out = INIT;
wire D_in;
wire GE_in;
wire G_in;
wire PRE_in;
assign IS_G_INVERTED_BIN = IS_G_INVERTED;
assign IS_PRE_INVERTED_BIN = IS_PRE_INVERTED;
`ifdef XIL_TIMING
wire D_dly;
wire GE_dly;
wire G_dly;
wire PRE_dly;
assign D_in = D_dly;
assign G_in = G_dly ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE_dly; // rv 1
assign PRE_in = (PRE !== 1'bz) && (PRE_dly ^ IS_PRE_INVERTED_BIN); // rv 0
`else
assign D_in = D;
assign G_in = G ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE; // rv 1
assign PRE_in = (PRE !== 1'bz) && (PRE ^ IS_PRE_INVERTED_BIN); // rv 0
`endif
assign Q = Q_out;
reg notifier;
wire notifier1;
reg rst_int, set_int;
wire o_out;
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nset;
wire in_clk_enable, in_clk_enable_n, in_clk_enable_p;
wire ce_clk_enable, ce_clk_enable_n, ce_clk_enable_p;
wire rst_clk_enable, rst_clk_enable1;
wire tl_enable, tl_enable_n, tl_enable_p;
wire clk_en_n, clk_en_p;
`endif
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
not (nset, PRE_in);
not (ngsr, GSR);
xor (in_out, D_dly, Q);
and (in_clk_enable, ngsr, nset, GE_in);
and (ce_clk_enable, ngsr, nset, in_out);
and (rst_clk_enable, ngsr, GE_in);
and (tl_enable, ngsr, nset);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && IS_G_INVERTED_BIN;
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && ~IS_G_INVERTED_BIN;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && IS_G_INVERTED_BIN;
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && ~IS_G_INVERTED_BIN;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
assign tl_enable_n = (MSGON =="TRUE") && tl_enable && IS_G_INVERTED_BIN;
assign tl_enable_p = (MSGON =="TRUE") && tl_enable && ~IS_G_INVERTED_BIN;
assign clk_en_n = (MSGON =="TRUE") && IS_G_INVERTED_BIN;
assign clk_en_p = (MSGON =="TRUE") && ~IS_G_INVERTED_BIN;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR or PRE_in) begin
if (GSR) begin
if (INIT) begin
rst_int = 1'b0;
set_int = 1'b1;
end
else begin
rst_int = 1'b1;
set_int = 1'b0;
end
end
else begin
rst_int = 1'b0;
set_int = PRE_in;
end
end
latchsre_ldpe (o_out, G_in, D_in, set_int, rst_int, GE_in, notifier1);
always @(o_out)
Q_out = o_out;
specify
(D => Q) = (100:100:100, 100:100:100);
(G => Q) = (100:100:100, 100:100:100);
(GE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(PRE => Q) = (0:0:0, 0:0:0);
(negedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
(posedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
$period (negedge G, 0:0:0, notifier);
$period (posedge G, 0:0:0, notifier);
$recrem (negedge GE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,GE_dly, G_dly);
$recrem (negedge GE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,GE_dly, G_dly);
$recrem (negedge PRE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,PRE_dly, G_dly);
$recrem (negedge PRE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,PRE_dly, G_dly);
$recrem (posedge PRE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,PRE_dly, G_dly);
$recrem (posedge PRE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,PRE_dly, G_dly);
$setuphold (negedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (negedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (posedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$setuphold (posedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$width (negedge G, 0:0:0, 0, notifier);
$width (negedge PRE, 0:0:0, 0, notifier);
$width (posedge G, 0:0:0, 0, notifier);
$width (posedge GE, 0:0:0, 0, notifier);
$width (posedge PRE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive latchsre_ldpe (q, clk, d, set, rst, ge, notifier);
output q; reg q;
input clk, d, set, rst, ge, notifier;
table
// clk d set rst ge notifier q q+;
1 0 0 0 1 ? : ? : 0;
1 1 0 0 1 ? : ? : 1;
0 ? 0 0 ? ? : ? : -;
? ? 0 0 0 ? : ? : -;
? 0 0 ? ? ? : 0 : -;
? 1 ? 0 ? ? : 1 : -;
? ? 1 0 ? ? : ? : 1;
? ? ? 1 ? ? : ? : 0;
0 ? 0 x ? ? : 0 : 0;
? ? 0 x 0 ? : 0 : 0;
1 0 0 x 1 ? : ? : 0;
0 ? x 0 ? ? : 1 : 1;
? ? x 0 0 ? : 1 : 1;
1 1 x 0 1 ? : ? : 1;
? ? ? ? ? * : ? : x;
endtable
endprimitive
|
(*|
Tutorial on Coq commands
************************
:author: Enrico Tassi
.. include:: ../etc/tutorial_style.rst
..
Elpi is an extension language that comes as a library
to be embedded into host applications such as Coq.
Elpi is a variant of λProlog enriched with constraints.
λProlog is a programming language designed to make it easy
to manipulate abstract syntax trees containing binders.
Elpi extends λProlog with programming constructs that are
designed to make it easy to manipulate abstract syntax trees
containing metavariables (also called unification variables, or
evars in the Coq jargon).
This software, "coq-elpi", is a Coq plugin embedding Elpi and
exposing to the extension language Coq spefic data types (e.g. terms)
and API (e.g. to declare a new inductive type).
In order to get proper syntax highlighting using VSCode please install the
"gares.coq-elpi-lang" extension. In CoqIDE please chose "coq-elpi" in
Edit -> Preferences -> Colors.
This tutorial assumes the reader is familiar with Elpi and the HOAS
representation of Coq terms; if it is not the case, please take a look at
these other tutorials first:
`Elpi tutorial <https://lpcic.github.io/coq-elpi/tutorial_elpi_lang.html>`_
and
`Coq HOAS tutorial <https://lpcic.github.io/coq-elpi/tutorial_coq_elpi_HOAS.html>`_.
.. contents::
=================
Defining commands
=================
Let's create a simple command, called "hello", which prints :e:`"Hello"`
followed by the arguments we pass to it:
|*)
From elpi Require Import elpi.
Elpi Command hello.
Elpi Accumulate lp:{{
% main is, well, the entry point
main Arguments :- coq.say "Hello" Arguments.
}}.
Elpi Typecheck.
(*|
The program declaration is made of 3 parts.
The first one `Elpi Command hello.` sets the current program to hello.
Since it is declared as a `Command` some code is loaded automatically:
* APIs (eg :builtin:`coq.say`) and data types (eg Coq :type:`term` s) are loaded from
`coq-builtin.elpi <https://github.com/LPCIC/coq-elpi/blob/master/coq-builtin.elpi>`_
* some utilities, like :lib:`copy` or :libred:`whd1` are loaded from
`elpi-command-template.elpi <https://github.com/LPCIC/coq-elpi/blob/master/elpi/elpi-command-template.elpi>`_
The second one `Elpi Accumulate ...` loads some extra code.
The `Elpi Accumulate ...` family of commands lets one accumulate code
taken from:
* verbatim text `Elpi Accumulate lp:{{ code }}`
* source files `Elpi Accumulate File path`
* data bases (Db) `Elpi Accumulate Db name`
Accumulating code via inline text or file is equivalent, the AST of `code`
is stored in the .vo file (the external file does not need to be installed).
We postpone the description of data bases to a dedicated section.
Once all the code is accumulated `Elpi Typecheck` verifies that the
code does not contain the most frequent kind of mistakes. This command
considers some mistakes minor and only warns about them. You can
pass `-w +elpi.typecheck` to `coqc` to turn these warnings into errors.
We can now run our program!
|*)
Elpi hello "world!".
(*|
You should see the following output (hover the bubble next to the
code if you are reading this online):
.. mquote:: .s(Elpi hello).msg(str world)
:language: text
The string `"world!"` we passed to the command is received by the code
as :e:`(str "world!")`.
.. note:: :builtin:`coq.say` won't print quotes around strings
=================
Command arguments
=================
Let's pass different kind of arguments to `hello`:
|*)
Elpi hello 46.
Elpi hello there.
(*|
This time we passed to the command a number and an identifier.
Identifiers are received as strings, and can contain dots, but no spaces.
|*)
Elpi hello my friend.
Elpi hello this.is.a.qualified.name.
(*|
Indeed the first invocation passes two arguments, of type string, while
the second a single one, again a string containing dots.
There are a few more types of arguments a command can receive:
* terms, delimited by `(` and `)`
* toplevel declarations, like `Inductive ..`, `Definition ..`, etc..
which are introduced by their characterizing keyword.
Let's try with a term.
|*)
Elpi hello (0 = 1).
(*|
Terms are received *raw*, in the sense that no elaboration has been
performed. In the example above the type argument to `eq` has not
been synthesized to be `nat`. As we will see later the
:builtin:`coq.typecheck` API
can be used to satisfy typing constraints.
|*)
Elpi hello Definition test := 0 = 1.
Elpi hello Record test := { f1 : nat; f2 : f1 = 1 }.
(*|
Global declarations are received raw as well. In the case of `Definition test`
the optional body (would be :e:`none` for an `Axiom` declaration) is present
while the type is omitted (that is, a variable :e:`X1` is used in place of the
type).
In the case of the `Record` declaration remark that each field has a few
attributes, like being a coercions (the `:>` in Coq's syntax). Also note that
the type of the record (which was omitted) defaults to `Type`
(for some level :e:`X0`). Finally note that the type of the second field
sees :e:`c0` (the value of the first field).
See the :type:`argument` data type
for a detailed decription of all the arguments a command can receive.
------------------------
Processing raw arguments
------------------------
There are two ways to process term arguments: typechecking and elaboration.
|*)
Elpi Command check_arg.
Elpi Accumulate lp:{{
main [trm T] :-
std.assert-ok! (coq.typecheck T Ty) "argument illtyped",
coq.say "The type of" T "is" Ty.
}}.
Elpi Typecheck.
Elpi check_arg (1 = 0).
Fail Elpi check_arg (1 = true). (* .fails *)
(*|
The command `check_arg` receives a term :e:`T` and type checks it, then it
prints the term and its type.
The :builtin:`coq.typecheck` API has 3 arguments: a term, its type and a
:stdtype:`diagnostic` which can either be :e:`ok` or :e:`(error Message)`.
The :stdlib:`assert-ok!` combinator checks if the diagnostic is :e:`ok`,
and if not it prints the error message and bails out.
The first invocation succeeds while the second one fails and prints
the type checking error (given by Coq) following the string passed to
:e:`std.assert-ok!`.
|*)
Coercion bool2nat (b : bool) := if b then 1 else 0.
Fail Elpi check_arg (1 = true). (* .fails *)
Check (1 = true).
(*|
The command still fails even if we told Coq how to inject booleans values
into the natural numbers. Indeed the `Check` commands works.
The call to :builtin:`coq.typecheck` modifies the term in place, it can assign
implicit arguments (like the type parameter of `eq`) but it cannot modify the
structure of the term. To do so, one has to use the
:builtin:`coq.elaborate-skeleton`
API.
|*)
Elpi Command elaborate_arg.
Elpi Accumulate lp:{{
main [trm T] :-
std.assert-ok! (coq.elaborate-skeleton T Ty T1) "illtyped arg",
coq.say "T=" T,
coq.say "T1=" T1,
coq.say "Ty=" Ty.
}}.
Elpi Typecheck.
Elpi elaborate_arg (1 = true).
(*|
Remark how :e:`T` is not touched by the call to this API, and how :e:`T1`
is a copy of :e:`T` where the hole after `eq` is synthesized and the value
`true` injected to `nat` by using `bool2nat`.
It is also possible to manipulate term arguments before typechecking
them, but note that all the considerations on holes in the tutorial about
the HOAS representation of Coq terms apply here.
========
Examples
========
-------------------
Synthesizing a term
-------------------
Synthesizing a term typically involves reading an existing declaration
and writing a new one. The relevant APIs are in the `coq.env.*` namespace
and are named after the global refence they manipulate, eg :builtin:`coq.env.const`
for reading and :builtin:`coq.env.add-const` for writing.
Here we implement a little command that given an inductive type name
generates a term of type `nat` whose value is the number of constructors
of the given inductive type.
|*)
Elpi Command constructors_num.
Elpi Accumulate lp:{{
pred int->nat i:int, o:term.
int->nat 0 {{ 0 }}.
int->nat N {{ S lp:X }} :- M is N - 1, int->nat M X.
main [str IndName, str Name] :-
std.assert! (coq.locate IndName (indt GR)) "not an inductive type",
coq.env.indt GR _ _ _ _ Kn _, % the names of the constructors
std.length Kn N, % count them
int->nat N Nnat, % turn the integer into a nat
coq.env.add-const Name Nnat _ _ _. % save it
}}.
Elpi Typecheck.
Elpi constructors_num bool nK_bool.
Print nK_bool.
Elpi constructors_num False nK_False.
Print nK_False.
Fail Elpi constructors_num plus nK_plus. (* .fails *)
Fail Elpi constructors_num not_there bla. (* .fails *)
(*|
The command starts by locating the first argument and asserting it points to
an inductive type. This line is idiomatic: :builtin:`coq.locate` aborts if
the string cannot be located, and if it relates it to a :e:`gref` which is not
:e:`indt` (for example :e:`const plus`) :stdlib:`assert!` aborts with the given
error message.
:builtin:`coq.env.indt` lets one access all the details of an inductive type,
here we just use the list of constructors.
The twin API :builtin:`coq.env.indt-decl` lets
one access the declaration of the inductive in HOAS form, which might be
easier to manipulate in other situations, like the next example.
Then the program crafts a natural number and declares a constant for it.
------------------------
Abstracting an inductive
------------------------
For the sake of introducing :lib:`copy`, the swiss army knife of λProlog, we
write a command which takes an inductive type declaration and builds a new
one abstracting the former one on a given term. The new inductive has a
parameter in place of the occurrences of that term.
|*)
Elpi Command abstract.
Elpi Accumulate lp:{{
% a renaming function which adds a ' to an ident (a string)
pred prime i:id, o:id.
prime S S1 :- S1 is S ^ "'".
main [str Ind, trm Param] :-
% the term to be abstracted out, P of type PTy
std.assert-ok!
(coq.elaborate-skeleton Param PTy P)
"illtyped parameter",
% fetch the old declaration
std.assert! (coq.locate Ind (indt I)) "not an inductive type",
coq.env.indt-decl I Decl,
% let's start to craft the new declaration by putting a
% parameter A which has the type of P
NewDecl = parameter "A" explicit PTy Decl',
% let's make a copy, capturing all occurrences of P with a
% (which stands for the parameter)
(pi a\ copy P a => copy-indt-decl Decl (Decl' a)),
% to avoid name clashes, we rename the type and its constructors
% (we don't need to rename the parameters)
coq.rename-indt-decl (=) prime prime NewDecl DeclRenamed,
% we type check the inductive declaration, since abstracting
% random terms may lead to illtyped declarations (type theory
% is hard)
std.assert-ok!
(coq.typecheck-indt-decl DeclRenamed)
"can't be abstracted",
coq.env.add-indt DeclRenamed _.
}}.
Elpi Typecheck.
Inductive tree := leaf | node : tree -> option nat -> tree -> tree.
Elpi abstract tree (option nat).
Print tree'.
(*|
As expected `tree'` has a parameter `A`.
Now let's focus on :lib:`copy`. The standard
coq library (loaded by the command template) contains a definition of copy
for terms and declarations.
An excerpt:
.. code:: elpi
copy X X :- name X. % checks X is a bound variable
copy (global _ as C) C.
copy (fun N T F) (fun N T1 F1) :-
copy T T1, pi x\ copy (F x) (F1 x).
copy (app L) (app L1) :- std.map L copy L1.
:e:`copy` implements the identity: it builds, recursively, a copy of the first
term into the second argument. Unless one loads in the context a new rule,
which takes precedence over the identity ones. Here we load:
.. code:: elpi
copy P a
which, at run time, looks like
.. code:: elpi
copy (app [global (indt «option»), global (indt «nat»)]) c0
and that rule masks the one for `app` when the sub-term being copied is
exactly `option nat`. The API :lib:`copy-indt-decl` copies an inductive
declaration and calls `copy` on all the terms it contains (e.g. the
type of the constructors).
The :lib:`copy` predicate is very flexible, but sometimes one needs to collect
some data along the way. The sibling API :lib:`fold-map` lets one do that.
An excerpt:
.. code:: elpi
fold-map (fun N T F) A (fun N T1 F1) A2 :-
fold-map T A T1 A1, pi x\ fold-map (F x) A1 (F1 x) A2.
For example one can use :lib:`fold-map` to collect into a list all the occurrences
of inductive type constructors in a given term, then use the list to postulate
the right number of binders for them, and finally use :lib:`copy` to capture them.
====================================
Using DBs to store data across calls
====================================
A Db can be created with the command:
|*)
Elpi Db name.db lp:{{ some code. }}.
(*|
and a Db can be later extended via `Elpi Accumulate`.
As a convention, we like Db names to end in a .db suffix.
A Db is pretty much like a regular program but can be *shared* among
other programs and is accumulated *by name*.
Since is a Db is accumulated *when a program runs* the *current
contents of the Db are used*.
Moreover the Db can be extended by Elpi programs themselves
thanks to the API :builtin:`coq.elpi.accumulate`, enabling code to save a state
which is then visible at subsequent runs.
The initial contents of a Db, `some code` in the example
above, is usually just the type declaration for the predicates part of the Db,
and maybe a few default rules.
Let's define a Db.
|*)
Elpi Db age.db lp:{{
% A typical Db is made of one main predicate
pred age o:string, o:int.
% the Db is empty for now, we put a rule giving a
% descriptive error and we name that rule "age.fail".
:name "age.fail"
age Name _ :- coq.error "I don't know who" Name "is!".
}}.
(*|
Elpi rules can be given a name via the :e:`:name` attribute. Named rules
serve as anchor-points for new rules when added to the Db.
Let's define a `Command` that makes use of a Db.
|*)
Elpi Command age.
Elpi Accumulate Db age.db. (* we accumulate the Db *)
Elpi Accumulate lp:{{
main [str Name] :-
age Name A,
coq.say Name "is" A "years old".
}}.
Elpi Typecheck.
Fail Elpi age bob. (* .fails *)
(*|
Let's put some data in the Db. Given that the Db contains a catch-all rule,
we need the new ones to be put before it.
|*)
Elpi Accumulate age.db lp:{{
:before "age.fail" % we place this rule before the catch all
age "bob" 24.
}}.
Elpi age bob.
(*|
Extending data bases this way is fine, but requires the user of our command
to be familiar with Elpi's syntax, which is not very nice. Instead,
we can write a new program that uses the :builtin:`coq.elpi.accumulate` API
to extend the Db.
|*)
Elpi Command set_age.
Elpi Accumulate Db age.db.
Elpi Accumulate lp:{{
main [str Name, int Age] :-
TheNewRule = age Name Age,
coq.elpi.accumulate _ "age.db"
(clause _ (before "age.fail") TheNewRule).
}}.
Elpi Typecheck.
Elpi set_age "alice" 21.
Elpi age "alice".
(*|
Additions to a Db are a Coq object, a bit like a Notation or a Type Class
instance: these object live inside a Coq module (or a Coq file) and become
active when that module is Imported.
Deciding to which Coq module these
extra rules belong is important and :builtin:`coq.elpi.accumulate` provides
a few options to tune that. Here we passed :e:`_`, that uses the default
setting. See the :type:`scope` and :type:`clause` data types for more info.
.. _inspecting:
---------------
Inspecting a Db
---------------
So far we did query a Db but sometimes one needs to inspect the whole
contents.
|*)
Elpi Command print_all_ages.
Elpi Accumulate Db age.db.
Elpi Accumulate lp:{{
:before "age.fail"
age _ _ :- !, fail. % softly
main [] :-
std.findall (age _ _) Rules,
std.forall Rules print-rule.
pred print-rule i:prop.
print-rule (age P N) :- coq.say P "is" N "years old".
}}.
Elpi Typecheck.
Elpi print_all_ages.
(*|
The :stdlib:`std.findall` predicate gathers in a list all solutions to
a query, while :stdlib:`std.forall` iterates a predicate over a list.
It is important to notice that :builtin:`coq.error` is a fatal error which
aborts an Elpi program. Here we shadow the catch all clause with a regular
failure so that :stdlib:`std.findall` can complete to list all the results.
===================
Polishing a command
===================
The details do make the difference, some times.
----------
Attributes
----------
Elpi programs can be prefixed with attributes, like `#[local]`.
Attributes are not passed as arguments but rather as a rule in the context,
a bit like the option :e:`@holes!` we have seen before.
|*)
Elpi Command attr.
Elpi Accumulate lp:{{
main _ :-
attributes A, % we fetch the list of attributes from the context
coq.say A.
}}.
#[this, more(stuff="33")] Elpi attr.
(*|
The first attribute, :e:`elpi.loc` is always present and corresponds to the
location in the source file of the command. Then we find an attribute for
:e:`"this"` holding the emptry string and an attribute for :e:`"more.stuff"` holding
the string :e:`"33"`.
Attributes are usually validated (parsed) and turned into regular options
using :lib:`coq.parse-attributes` and a description of their types using
the :libtype:`attribute-type` data type:
|*)
Elpi Command parse_attr.
Elpi Accumulate lp:{{
pred some-code.
some-code :-
get-option "more.stuff" N, get-option "this" B, coq.say N B.
main _ :-
attributes A,
coq.parse-attributes A [
att "this" bool,
att "more.stuff" int,
] Opts,
coq.say "options=" Opts,
Opts => some-code.
}}.
#[this, more(stuff="33")] Elpi parse_attr.
Fail #[unknown] Elpi parse_attr. (* .fails *)
(*|
Note that :e:`get-option` links a string with a datum of type :e:`any`, which means
no type checking is performed on it. It is recommended to wrap calls to
get-option into other predicates typed in a more precise way. Eg:
.. code:: elpi
pred get-my-option o:int.
get-my-option I :- get-option "my-option-name" I.
-----------------------------
Extending the command grammar
-----------------------------
Elpi programs can be exported as regular Coq commands, so that the
final user does not need to type `Elpi` to invoke them.
|*)
Elpi Command Say.
Elpi Accumulate lp:{{ main [str S] :- coq.say S. }}.
Elpi Typecheck.
Elpi Export Say. (* extend the Coq command grammar *)
Say "That is all folks!".
(*|
Not yet...
Coq offers no equivalent of `Tactic Notation` for commands.
Still Elpi commands accept any symbol or keyword as strings.
It is up to the programmer to catch and report parse errors.
|*)
Elpi Command Go.
Elpi Accumulate lp:{{
main [str Src, str "=>", str Tgt, str "/", str F] :- !,
coq.say "going from" Src "to" Tgt "via" F.
main _ :-
coq.error "Parse error! Use: go <from> => <to> / <via>".
}}.
Elpi Typecheck.
Elpi Export Go.
Go source => target / plane.
Fail Go nowhere. (* .fails *)
(*|
----------------
Reporting errors
----------------
Last, (good) Elpi programs should fail reporting intellegible error messages,
as the previous one.
|*)
Elpi Command bad.
Elpi Accumulate lp:{{ main []. }}.
Elpi Typecheck.
Elpi Export bad.
Fail bad 1. (* .fails *)
(*|
If they just fail, they produce the following generic
error:
.. mquote:: .s(bad 1).msg(inconvenience)
:language: text
You should use the :builtin:`coq.error` API or the :stdlib:`assert!` one
to abort a program. There is a dedicated :builtin:`coq.ltac.fail` API to abort
tactics.
Warnings can be reported using the :builtin:`coq.warning` which lets you
pick a name and category. In turn these can be used to disable or make fatal
your warnings (as any other Coq warning).
This is really the end, unless you want to learn more about writing
`tactics <https://lpcic.github.io/coq-elpi/tutorial_coq_elpi_tactic.html>`_
in Elpi, in that case look at that tutorial ;-)
|*)
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 5
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
wire clk_100mhz;
wire calibration_done;
wire usr_clk;
wire usr_rst;
wire cmd_clk;
wire cmd_en;
wire [2:0] cmd_instr;
wire [5:0] cmd_bl;
wire [29:0] cmd_byte_addr;
wire cmd_empty;
wire cmd_full;
wire wr_clk;
wire wr_en;
wire [3:0] wr_mask;
wire [31:0] wr_data;
wire wr_full;
wire wr_empty;
wire [6:0] wr_count;
wire wr_underrun;
wire wr_error;
wire rd_clk;
wire rd_en;
wire [31:0] rd_data;
wire rd_full;
wire rd_empty;
wire [6:0] rd_count;
wire rd_overflow;
wire rd_error;
wire [7:0] mcb3_dram_dq;
wire [13:0] mcb3_dram_a;
wire [2:0] mcb3_dram_ba;
wire mcb3_dram_ras_n;
wire mcb3_dram_cas_n;
wire mcb3_dram_we_n;
wire mcb3_dram_odt;
wire mcb3_dram_reset_n;
wire mcb3_dram_cke;
wire mcb3_dram_dm;
wire mcb3_rzq;
wire mcb3_zio;
wire mcb3_dram_dqs;
wire mcb3_dram_dqs_n;
wire mcb3_dram_ck;
wire mcb3_dram_ck_n;
wire p0_cmd_clk;
wire p0_cmd_en;
wire [2:0] p0_cmd_instr;
wire [5:0] p0_cmd_bl;
wire [29:0] p0_cmd_byte_addr;
wire p0_cmd_empty;
wire p0_cmd_full;
wire p0_wr_clk;
wire p0_wr_en;
wire [3:0] p0_wr_mask;
wire [31:0] p0_wr_data;
wire p0_wr_full;
wire p0_wr_empty;
wire [6:0] p0_wr_count;
wire p0_wr_underrun;
wire p0_wr_error;
wire p0_rd_clk;
wire p0_rd_en;
wire [31:0] p0_rd_data;
wire p0_rd_full;
wire p0_rd_empty;
wire [6:0] p0_rd_count;
wire p0_rd_overflow;
wire p0_rd_error;
wire p1_cmd_clk;
wire p1_cmd_en;
wire [2:0] p1_cmd_instr;
wire [5:0] p1_cmd_bl;
wire [29:0] p1_cmd_byte_addr;
wire p1_cmd_empty;
wire p1_cmd_full;
wire p1_wr_clk;
wire p1_wr_en;
wire [3:0] p1_wr_mask;
wire [31:0] p1_wr_data;
wire p1_wr_full;
wire p1_wr_empty;
wire [6:0] p1_wr_count;
wire p1_wr_underrun;
wire p1_wr_error;
wire p1_rd_clk;
wire p1_rd_en;
wire [31:0] p1_rd_data;
wire p1_rd_full;
wire p1_rd_empty;
wire [6:0] p1_rd_count;
wire p1_rd_overflow;
wire p1_rd_error;
wire p2_cmd_clk;
wire p2_cmd_en;
wire [2:0] p2_cmd_instr;
wire [5:0] p2_cmd_bl;
wire [29:0] p2_cmd_byte_addr;
wire p2_cmd_empty;
wire p2_cmd_full;
wire p2_wr_clk;
wire p2_wr_en;
wire [3:0] p2_wr_mask;
wire [31:0] p2_wr_data;
wire p2_wr_full;
wire p2_wr_empty;
wire [6:0] p2_wr_count;
wire p2_wr_underrun;
wire p2_wr_error;
wire p2_rd_clk;
wire p2_rd_en;
wire [31:0] p2_rd_data;
wire p2_rd_full;
wire p2_rd_empty;
wire [6:0] p2_rd_count;
wire p2_rd_overflow;
wire p2_rd_error;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_artemis_ddr3 s1(
.clk (clk ),
.rst (rst ),
.ddr3_cmd_clk (cmd_clk ),
.ddr3_cmd_en (cmd_en ),
.ddr3_cmd_instr (cmd_instr ),
.ddr3_cmd_bl (cmd_bl ),
.ddr3_cmd_byte_addr(cmd_byte_addr ),
.ddr3_cmd_empty (cmd_empty ),
.ddr3_cmd_full (cmd_full ),
.ddr3_wr_clk (wr_clk ),
.ddr3_wr_en (wr_en ),
.ddr3_wr_mask (wr_mask ),
.ddr3_wr_data (wr_data ),
.ddr3_wr_full (wr_full ),
.ddr3_wr_empty (wr_empty ),
.ddr3_wr_count (wr_count ),
.ddr3_wr_underrun (wr_underrun ),
.ddr3_wr_error (wr_error ),
.ddr3_rd_clk (rd_clk ),
.ddr3_rd_en (rd_en ),
.ddr3_rd_data (rd_data ),
.ddr3_rd_full (rd_full ),
.ddr3_rd_empty (rd_empty ),
.ddr3_rd_count (rd_count ),
.ddr3_rd_overflow (rd_overflow ),
.ddr3_rd_error (rd_error ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_sel (w_wbs1_sel ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
//sim_artemis_ddr3_user adu(
sim_artemis_ddr3#(
.RFIFO_WRITE_DELAY (1 )
)adu(
.ddr3_in_clk (clk_100mhz ),
.rst (rst ),
.calibration_done (calibration_done ),
.usr_clk (usr_clk ),
.usr_rst (usr_rst ),
.mcb3_dram_dq (mcb3_dram_dq ),
.mcb3_dram_a (mcb3_dram_a ),
.mcb3_dram_ba (mcb3_dram_ba ),
.mcb3_dram_ras_n (mcb3_dram_ras_n ),
.mcb3_dram_cas_n (mcb3_dram_cas_n ),
.mcb3_dram_we_n (mcb3_dram_we_n ),
.mcb3_dram_odt (mcb3_dram_odt ),
.mcb3_dram_reset_n (mcb3_dram_reset_n ),
.mcb3_dram_cke (mcb3_dram_cke ),
.mcb3_dram_dm (mcb3_dram_dm ),
.mcb3_rzq (mcb3_rzq ),
.mcb3_zio (mcb3_zio ),
.mcb3_dram_dqs (mcb3_dram_dqs ),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n ),
.mcb3_dram_ck (mcb3_dram_ck ),
.mcb3_dram_ck_n (mcb3_dram_ck_n ),
.p0_cmd_clk (p0_cmd_clk ),
.p0_cmd_en (p0_cmd_en ),
.p0_cmd_instr (p0_cmd_instr ),
.p0_cmd_bl (p0_cmd_bl ),
.p0_cmd_byte_addr (p0_cmd_byte_addr ),
.p0_cmd_empty (p0_cmd_empty ),
.p0_cmd_full (p0_cmd_full ),
.p0_wr_clk (p0_wr_clk ),
.p0_wr_en (p0_wr_en ),
.p0_wr_mask (p0_wr_mask ),
.p0_wr_data (p0_wr_data ),
.p0_wr_full (p0_wr_full ),
.p0_wr_empty (p0_wr_empty ),
.p0_wr_count (p0_wr_count ),
.p0_wr_underrun (p0_wr_underrun ),
.p0_wr_error (p0_wr_error ),
.p0_rd_clk (p0_rd_clk ),
.p0_rd_en (p0_rd_en ),
.p0_rd_data (p0_rd_data ),
.p0_rd_full (p0_rd_full ),
.p0_rd_empty (p0_rd_empty ),
.p0_rd_count (p0_rd_count ),
.p0_rd_overflow (p0_rd_overflow ),
.p0_rd_error (p0_rd_error ),
.p1_cmd_clk (p1_cmd_clk ),
.p1_cmd_en (p1_cmd_en ),
.p1_cmd_instr (p1_cmd_instr ),
.p1_cmd_bl (p1_cmd_bl ),
.p1_cmd_byte_addr (p1_cmd_byte_addr ),
.p1_cmd_empty (p1_cmd_empty ),
.p1_cmd_full (p1_cmd_full ),
.p1_wr_clk (p1_wr_clk ),
.p1_wr_en (p1_wr_en ),
.p1_wr_mask (p1_wr_mask ),
.p1_wr_data (p1_wr_data ),
.p1_wr_full (p1_wr_full ),
.p1_wr_empty (p1_wr_empty ),
.p1_wr_count (p1_wr_count ),
.p1_wr_underrun (p1_wr_underrun ),
.p1_wr_error (p1_wr_error ),
.p1_rd_clk (p1_rd_clk ),
.p1_rd_en (p1_rd_en ),
.p1_rd_data (p1_rd_data ),
.p1_rd_full (p1_rd_full ),
.p1_rd_empty (p1_rd_empty ),
.p1_rd_count (p1_rd_count ),
.p1_rd_overflow (p1_rd_overflow ),
.p1_rd_error (p1_rd_error ),
.p2_cmd_clk (p2_cmd_clk ),
.p2_cmd_en (p2_cmd_en ),
.p2_cmd_instr (p2_cmd_instr ),
.p2_cmd_bl (p2_cmd_bl ),
.p2_cmd_byte_addr (p2_cmd_byte_addr ),
.p2_cmd_empty (p2_cmd_empty ),
.p2_cmd_full (p2_cmd_full ),
.p2_wr_clk (p2_wr_clk ),
.p2_wr_en (p2_wr_en ),
.p2_wr_mask (p2_wr_mask ),
.p2_wr_data (p2_wr_data ),
.p2_wr_full (p2_wr_full ),
.p2_wr_empty (p2_wr_empty ),
.p2_wr_count (p2_wr_count ),
.p2_wr_underrun (p2_wr_underrun ),
.p2_wr_error (p2_wr_error ),
.p2_rd_clk (p2_rd_clk ),
.p2_rd_en (p2_rd_en ),
.p2_rd_data (p2_rd_data ),
.p2_rd_full (p2_rd_full ),
.p2_rd_empty (p2_rd_empty ),
.p2_rd_count (p2_rd_count ),
.p2_rd_overflow (p2_rd_overflow ),
.p2_rd_error (p2_rd_error ),
//P.ort 3
.p3_cmd_clk (clk ),
.p3_cmd_en (cmd_en ),
.p3_cmd_instr (cmd_instr ),
.p3_cmd_bl (cmd_bl ),
.p3_cmd_byte_addr (cmd_byte_addr ),
.p3_cmd_empty (cmd_empty ),
.p3_cmd_full (cmd_full ),
.p3_wr_clk (wr_clk ),
.p3_wr_en (wr_en ),
.p3_wr_mask (wr_mask ),
.p3_wr_data (wr_data ),
.p3_wr_full (wr_full ),
.p3_wr_empty (wr_empty ),
.p3_wr_count (wr_count ),
.p3_wr_underrun (wr_underrun ),
.p3_wr_error (wr_error ),
.p3_rd_clk (rd_clk ),
.p3_rd_en (rd_en ),
.p3_rd_data (rd_data ),
.p3_rd_full (rd_full ),
.p3_rd_empty (rd_empty ),
.p3_rd_count (rd_count ),
.p3_rd_overflow (rd_overflow ),
.p3_rd_error (rd_error )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
assign clk_100mhz = clk;
assign p0_cmd_clk = clk;
assign p0_cmd_en = 0;
assign p0_cmd_instr = 0;
assign p0_cmd_bl = 0;
assign p0_cmd_byte_addr = 0;
assign p0_wr_clk = clk;
assign p0_wr_en = 0;
assign p0_wr_mask = 0;
assign p0_wr_data = 0;
assign p0_rd_clk = clk;
assign p0_rd_en = 0;
assign p0_rd_data = 0;
assign p1_cmd_clk = clk;
assign p1_cmd_en = 0;
assign p1_cmd_instr = 0;
assign p1_cmd_bl = 0;
assign p1_cmd_byte_addr = 0;
assign p1_wr_clk = clk;
assign p1_wr_en = 0;
assign p1_wr_mask = 0;
assign p1_wr_data = 0;
assign p1_rd_clk = clk;
assign p1_rd_en = 0;
assign p1_rd_data = 0;
assign p2_cmd_clk = clk;
assign p2_cmd_en = 0;
assign p2_cmd_instr = 0;
assign p2_cmd_bl = 0;
assign p2_cmd_byte_addr = 0;
assign p2_wr_clk = clk;
assign p2_wr_en = 0;
assign p2_wr_mask = 0;
assign p2_wr_data = 0;
assign p2_rd_clk = clk;
assign p2_rd_en = 0;
assign p2_rd_data = 0;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
//`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
//`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
//`ifdef VERBOSE $display ("Command Finished"); `endif
$display ("Command Finished");
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_dtl_sclk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_dtl_sclk(l2clk ,int_sclk ,sclk ,ssclk_n ,se ,si_l ,
global_reset_n );
output int_sclk ;
output sclk ;
output ssclk_n ;
input l2clk ;
input se ;
input si_l ;
input global_reset_n ;
wire [2:0] scarry ;
wire [3:0] scount ;
wire [3:0] next_scount ;
wire net113 ;
wire net050 ;
wire scan_data_1 ;
wire scan_data_2 ;
wire scan_data_3 ;
wire scan_data_4 ;
wire scan_in ;
wire scan_out ;
wire net65 ;
bw_u1_soffr_4x I128 (
.q (scount[2] ),
.so (scan_data_3 ),
.ck (l2clk ),
.d (next_scount[2] ),
.se (se ),
.sd (scan_data_2 ),
.r_l (global_reset_n ) );
bw_u1_inv_4x I156 (
.z (scan_in ),
.a (si_l ) );
bw_u1_xor2_4x I159 (
.z (next_scount[1] ),
.a (scount[1] ),
.b (scarry[0] ) );
bw_u1_xor2_4x I160 (
.z (next_scount[2] ),
.a (scount[2] ),
.b (scarry[1] ) );
bw_u1_inv_2x I161 (
.z (next_scount[0] ),
.a (scount[0] ) );
bw_u1_xor2_4x I162 (
.z (next_scount[3] ),
.a (scount[3] ),
.b (scarry[2] ) );
bw_u1_inv_4x I163 (
.z (scarry[0] ),
.a (next_scount[0] ) );
bw_u1_nand2_4x I164 (
.z (net113 ),
.a (scount[0] ),
.b (scount[1] ) );
bw_u1_inv_8x I165 (
.z (int_sclk ),
.a (net113 ) );
bw_u1_inv_4x I166 (
.z (net65 ),
.a (scount[2] ) );
bw_u1_nor2_2x I167 (
.z (scarry[2] ),
.a (net65 ),
.b (net113 ) );
bw_u1_soffr_4x I171 (
.q (sclk ),
.so (scan_out ),
.ck (l2clk ),
.d (scarry[1] ),
.se (se ),
.sd (scan_data_4 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I21 (
.q (scount[0] ),
.so (scan_data_1 ),
.ck (l2clk ),
.d (next_scount[0] ),
.se (se ),
.sd (scan_in ),
.r_l (global_reset_n ) );
bw_u1_inv_5x I173 (
.z (ssclk_n ),
.a (scan_out ) );
bw_u1_inv_2x I179 (
.z (net050 ),
.a (int_sclk ) );
bw_u1_inv_5x I180 (
.z (scarry[1] ),
.a (net050 ) );
bw_u1_soffr_4x I125 (
.q (scount[1] ),
.so (scan_data_2 ),
.ck (l2clk ),
.d (next_scount[1] ),
.se (se ),
.sd (scan_data_1 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I127 (
.q (scount[3] ),
.so (scan_data_4 ),
.ck (l2clk ),
.d (next_scount[3] ),
.se (se ),
.sd (scan_data_3 ),
.r_l (global_reset_n ) );
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Thu Mar 20 14:12:08 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_2/part_4/ip/clk_video/clk_video_stub.v
// Design : clk_video
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_video(clk_100MHz, clk_193MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_100MHz,clk_193MHz,locked" */;
input clk_100MHz;
output clk_193MHz;
output locked;
endmodule
|
/*
-- ============================================================================
-- FILE NAME : spm.v
-- DESCRIPTION : spm RAMÄ£¿é
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ???????
-- ============================================================================
*/
/********** ͨÓÃÍ·Îļþ **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** Ä£¿éÍ·Îļþ**********/
`include "spm.h"
/********** Ä£¿é **********/
module spm (
/********** ÊäÈëÊä³ö²ÎÊý **********/
input wire clk, // ʱÖÓ
/********** ¶Ë¿ÚA : IF½×¶Î **********/
input wire [`SpmAddrBus] if_spm_addr, // ?????
input wire if_spm_as_, // ??????????`??
input wire if_spm_rw, // ?i???????
input wire [`WordDataBus] if_spm_wr_data, // ?????z???`??
output wire [`WordDataBus] if_spm_rd_data, // ?i???????`??
/********** ¶Ë¿ÚB : MEM½×¶Î **********/
input wire [`SpmAddrBus] mem_spm_addr, // ?????
input wire mem_spm_as_, // ??????????`??
input wire mem_spm_rw, // ?i???????
input wire [`WordDataBus] mem_spm_wr_data, // ?????z???`??
output wire [`WordDataBus] mem_spm_rd_data // ?i???????`??
);
/********** ?????z???????? **********/
reg wea; // ??`?? A
reg web; // ??`?? B
/********** ?????z????????????? **********/
always @(*) begin
/* ¶Ë¿ÚA */
if ((if_spm_as_ == `ENABLE_) && (if_spm_rw == `WRITE)) begin
wea = `MEM_ENABLE; // ?????z?????
end else begin
wea = `MEM_DISABLE; // ?????z??o??
end
/* ¶Ë¿ÚB */
if ((mem_spm_as_ == `ENABLE_) && (mem_spm_rw == `WRITE)) begin
web = `MEM_ENABLE; // ?????z?????
end else begin
web = `MEM_DISABLE; // ?????z??o??
end
end
/********** Xilinx FPGA Block RAM :->altera_dpram **********/
altera_dpram x_s3e_dpram (
/********** ¶Ë¿ÚA : IF????`?? **********/
.clock_a (clk), // ????a?
.address_a (if_spm_addr), // ?????
.data_a (if_spm_wr_data), // ?????z???`????????A??
.wren_a (wea), // ?????z???????????`???
.q_a (if_spm_rd_data), // ?i???????`??
/********** ¶Ë¿ÚB : MEM????`?? **********/
.clock_b (clk), // ????a?
.address_b (mem_spm_addr), // ?????
.data_b (mem_spm_wr_data), // ?????z???`??
.wren_b (web), // ?????z?????
.q_b (mem_spm_rd_data) // ?i???????`??
);
endmodule
|
module peripheral_ultrsnd (clk , reset , d_in , cs , addr , rd , wr, d_out, echo, done, trigger, [15:0]distance);
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
input echo;
output trigger
//------------------------------------ regs and wires-------------------------------
//selector mux_4 and write registers
reg [5:0] s;
//---mult_32 input registers--//
reg echo = 0;
reg trigger = 0;
//---mult_32 output Regs-----//
wire [15:0]distance;
wire done;
//------------------------------------ regs and wires-------------------------------
ultrasonido (.clk(clk),.reset(reset),.echo(echo),.trigger(trigger),.done(done),.distance(distance));
//----------------address_decoder-------------------//
always @(*) begin
case (addr)
4'h0:begin s = (cs && wr) ? 6'b000001 : 6'b000000; end //echo
4'h2:begin s = (cs && wr) ? 6'b000010 : 6'b000000; end //trigger
4'h4:begin s = (cs && wr) ? 6'b000100 : 6'b000000; end //distance
4'h6:begin s = (cs && rd) ? 6'b001000 : 6'b000000; end //done
default:begin s = 6'b000000 ; end
endcase
end
//------------------address_decoder-----------------//
//-----------------escritura de registros
always @(negedge clk) begin
echo = (s[0]) ? d_in : echo; //Write Registers
trigger = (s[1]) ? d_in[0] : trigger; //Write Registers
end
//-----------------escritura de registros
//----------------mux_4 : multiplexa salidas del periferico
always @(negedge clk) begin
case (s[5:3])
4'b1000: d_out[0] = done;
4'b0100: d_out = [15:0]distance;
default: d_out = 0 ;
endcase
end
//----------------mux_4
endmodule |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_strecud_DSP48_1(
input [8 - 1:0] in0,
input [20 - 1:0] in1,
input [29 - 1:0] in2,
output [29 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in1);
assign b = $unsigned(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_strecud(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_strecud_DSP48_1 hls_contrast_strecud_DSP48_1_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
//wb_tx1_ddr3.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_tx1_ddr3
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/06/21
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module wb_tx1_ddr3 (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_0);
o_wbs_dat <= ADDR_0;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:17:34 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k160tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_iotx_tvalid,
s_axis_iotx_tready, s_axis_iotx_tlast, s_axis_iotx_tdata, s_axis_iotx_tkeep,
s_axis_iotx_tuser, m_axis_iorx_tvalid, m_axis_iorx_tready, m_axis_iorx_tlast,
m_axis_iorx_tdata, m_axis_iorx_tkeep, m_axis_iorx_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 19:58:45
// Design Name:
// Module Name: D_ff_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module D_ff_behavior_tb(
);
reg D, Clk;
wire Q;
D_ff_behavior DUT (.D(D), .Clk(Clk), .Q(Q));
initial begin
#180 $finish;
end
initial begin
Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1; D = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; D = 1;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
end
endmodule |
//
// Beeb816 Buffer board
//
module bufboard();
// Wires declared as supply* will default to wide routing
// when parsed through netlister.py
supply0 GND;
supply1 VDD_5V;
supply1 VDD_3V3;
// Netlister.py doesn't yet support Verilog bus notation so all
// busses have to be bit blasted.
wire bbc_d0, bbc_d1, bbc_d2, bbc_d3, bbc_d4, bbc_d5, bbc_d6, bbc_d7;
wire bbc_a0, bbc_a1, bbc_a2, bbc_a3, bbc_a4, bbc_a5, bbc_a6, bbc_a7;
wire bbc_a8, bbc_a9, bbc_a10, bbc_a11, bbc_a12, bbc_a13, bbc_a14, bbc_a15;
wire bbc_rnw, ram_web, ram_oeb, bbc_rstb, bbc_irqb, bbc_nmib, bbc_rdy ;
wire bbc_sync, bbc_phi0, bbc_phi1, bbc_phi2, hsclk, cpu_phi2;
wire tdo, tdi, tck, tms ;
// Link to connect 5V to regulator input - intercept to measure current or add alternative +5V supply
hdr1x02 vdd_5v_lnk ( .p1(VDD_5V_IN),.p2(VDD_5V) );
// 40W Plug which connects via IDC cable and header into the
// host computer's 6502 CPU socket
skt6502_40w_RA CON (
.vss(GND),
.rdy(bbc_rdy),
.phi1out(bbc_phi1),
.irqb(bbc_irqb),
.nc1(),
.nmib(bbc_nmib),
.sync(bbc_sync),
.vcc(VDD_5V_IN),
.a0(bbc_a0),
.a1(bbc_a1),
.a2(bbc_a2),
.a3(bbc_a3),
.a4(bbc_a4),
.a5(bbc_a5),
.a6(bbc_a6),
.a7(bbc_a7),
.a8(bbc_a8),
.a9(bbc_a9),
.a10(bbc_a10),
.a11(bbc_a11),
.vss2(GND),
.a12(bbc_a12),
.a13(bbc_a13),
.a14(bbc_a14),
.a15(bbc_a15),
.d7(bbc_d7),
.d6(bbc_d6),
.d5(bbc_d5),
.d4(bbc_d4),
.d3(bbc_d3),
.d2(bbc_d2),
.d1(bbc_d1),
.d0(bbc_d0),
.rdnw(bbc_rnw),
.nc2(),
.nc3(),
.phi0in(bbc_phi0),
.so(),
.phi2out(bbc_phi2),
.rstb(bbc_rstb)
);
hdr2x04 tstpt(
.p1(GND), .p2(GND),
.p3(tp0), .p4(tp1),
.p5(VDD_3V3), .p6(VDD_3V3),
.p7(VDD_3V3), .p8(VDD_3V3),
);
hdr1x04 gndpt(
.p1(GND),
.p2(GND),
.p3(GND),
.p4(GND)
);
// jtag header for in system programming (same pinout as MacMall Breakout board
// so that we can use existing cable).
hdr8way jtag (
.p1(GND), .p2(GND),
.p3(tms), .p4(tdi),
.p5(tdo), .p6(tck),
.p7(VDD_3V3), .p8(),
);
endmodule
|
// megafunction wizard: %DDR3 SDRAM Controller with UniPHY v14.0%
// GENERATION: XML
// ddr3_x32.v
// Generated using ACDS version 14.0 209 at 2014.11.01.16:18:41
`timescale 1 ps / 1 ps
module ddr3_x32 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire afi_reset_export_n, // afi_reset_export.reset_n
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
output wire avl_ready_0, // avl_0.waitrequest_n
input wire avl_burstbegin_0, // .beginbursttransfer
input wire [25:0] avl_addr_0, // .address
output wire avl_rdata_valid_0, // .readdatavalid
output wire [31:0] avl_rdata_0, // .readdata
input wire [31:0] avl_wdata_0, // .writedata
input wire avl_read_req_0, // .read
input wire avl_write_req_0, // .write
input wire [6:0] avl_size_0, // .burstcount
input wire [3:0] avl_be_0, // .byteenable
input wire mp_cmd_clk_0_clk, // mp_cmd_clk_0.clk
input wire mp_cmd_reset_n_0_reset_n, // mp_cmd_reset_n_0.reset_n
input wire mp_rfifo_clk_0_clk, // mp_rfifo_clk_0.clk
input wire mp_rfifo_reset_n_0_reset_n, // mp_rfifo_reset_n_0.reset_n
input wire mp_wfifo_clk_0_clk, // mp_wfifo_clk_0.clk
input wire mp_wfifo_reset_n_0_reset_n, // mp_wfifo_reset_n_0.reset_n
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rzqin, // oct.rzqin
output wire pll_mem_clk, // pll_sharing.pll_mem_clk
output wire pll_write_clk, // .pll_write_clk
output wire pll_locked, // .pll_locked
output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
output wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
output wire pll_avl_clk, // .pll_avl_clk
output wire pll_config_clk, // .pll_config_clk
output wire pll_mem_phy_clk, // .pll_mem_phy_clk
output wire afi_phy_clk, // .afi_phy_clk
output wire pll_avl_phy_clk // .pll_avl_phy_clk
);
ddr3_x32_0002 ddr3_x32_inst (
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_reset_export_n (afi_reset_export_n), // afi_reset_export.reset_n
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.avl_ready_0 (avl_ready_0), // avl_0.waitrequest_n
.avl_burstbegin_0 (avl_burstbegin_0), // .beginbursttransfer
.avl_addr_0 (avl_addr_0), // .address
.avl_rdata_valid_0 (avl_rdata_valid_0), // .readdatavalid
.avl_rdata_0 (avl_rdata_0), // .readdata
.avl_wdata_0 (avl_wdata_0), // .writedata
.avl_read_req_0 (avl_read_req_0), // .read
.avl_write_req_0 (avl_write_req_0), // .write
.avl_size_0 (avl_size_0), // .burstcount
.avl_be_0 (avl_be_0), // .byteenable
.mp_cmd_clk_0_clk (mp_cmd_clk_0_clk), // mp_cmd_clk_0.clk
.mp_cmd_reset_n_0_reset_n (mp_cmd_reset_n_0_reset_n), // mp_cmd_reset_n_0.reset_n
.mp_rfifo_clk_0_clk (mp_rfifo_clk_0_clk), // mp_rfifo_clk_0.clk
.mp_rfifo_reset_n_0_reset_n (mp_rfifo_reset_n_0_reset_n), // mp_rfifo_reset_n_0.reset_n
.mp_wfifo_clk_0_clk (mp_wfifo_clk_0_clk), // mp_wfifo_clk_0.clk
.mp_wfifo_reset_n_0_reset_n (mp_wfifo_reset_n_0_reset_n), // mp_wfifo_reset_n_0.reset_n
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.oct_rzqin (oct_rzqin), // oct.rzqin
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_write_clk), // .pll_write_clk
.pll_locked (pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_avl_phy_clk) // .pll_avl_phy_clk
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2014 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_mem_if_ddr3_emif" version="14.0" >
// Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
// Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" />
// Retrieval info: <generic name="RDIMM_CONFIG" value="0000000000000000" />
// Retrieval info: <generic name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
// Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
// Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
// Retrieval info: <generic name="DEVICE_WIDTH" value="1" />
// Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
// Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="666.667" />
// Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="13" />
// Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
// Retrieval info: <generic name="MEM_DQ_WIDTH" value="32" />
// Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
// Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
// Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
// Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
// Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
// Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
// Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
// Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
// Retrieval info: <generic name="MEM_CK_WIDTH" value="1" />
// Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
// Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
// Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
// Retrieval info: <generic name="NEXTGEN" value="true" />
// Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
// Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
// Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
// Retrieval info: <generic name="MEM_VERBOSE" value="true" />
// Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
// Retrieval info: <generic name="DUPLICATE_AC" value="false" />
// Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
// Retrieval info: <generic name="MEM_BL" value="OTF" />
// Retrieval info: <generic name="MEM_BT" value="Sequential" />
// Retrieval info: <generic name="MEM_ASR" value="Manual" />
// Retrieval info: <generic name="MEM_SRT" value="Normal" />
// Retrieval info: <generic name="MEM_PD" value="DLL off" />
// Retrieval info: <generic name="MEM_DRV_STR" value="RZQ/6" />
// Retrieval info: <generic name="MEM_DLL_EN" value="true" />
// Retrieval info: <generic name="MEM_RTT_NOM" value="RZQ/4" />
// Retrieval info: <generic name="MEM_RTT_WR" value="RZQ/4" />
// Retrieval info: <generic name="MEM_WTCL" value="6" />
// Retrieval info: <generic name="MEM_ATCL" value="Disabled" />
// Retrieval info: <generic name="MEM_TCL" value="8" />
// Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
// Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
// Retrieval info: <generic name="MEM_INIT_EN" value="false" />
// Retrieval info: <generic name="MEM_INIT_FILE" value="" />
// Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
// Retrieval info: <generic name="TIMING_TIS" value="190" />
// Retrieval info: <generic name="TIMING_TIH" value="140" />
// Retrieval info: <generic name="TIMING_TDS" value="30" />
// Retrieval info: <generic name="TIMING_TDH" value="65" />
// Retrieval info: <generic name="TIMING_TDQSQ" value="125" />
// Retrieval info: <generic name="TIMING_TQH" value="0.38" />
// Retrieval info: <generic name="TIMING_TDQSCK" value="255" />
// Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
// Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
// Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
// Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
// Retrieval info: <generic name="TIMING_TQSH" value="0.4" />
// Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
// Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
// Retrieval info: <generic name="MEM_TINIT_US" value="500" />
// Retrieval info: <generic name="MEM_TMRD_CK" value="4" />
// Retrieval info: <generic name="MEM_TRAS_NS" value="36.0" />
// Retrieval info: <generic name="MEM_TRCD_NS" value="13.5" />
// Retrieval info: <generic name="MEM_TRP_NS" value="13.5" />
// Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
// Retrieval info: <generic name="MEM_TRFC_NS" value="110.0" />
// Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
// Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
// Retrieval info: <generic name="MEM_TWTR" value="4" />
// Retrieval info: <generic name="MEM_TFAW_NS" value="45.0" />
// Retrieval info: <generic name="MEM_TRRD_NS" value="7.5" />
// Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
// Retrieval info: <generic name="RATE" value="Full" />
// Retrieval info: <generic name="MEM_CLK_FREQ" value="533.333333" />
// Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
// Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
// Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
// Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
// Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
// Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
// Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
// Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
// Retrieval info: <generic name="SPEED_GRADE" value="4" />
// Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
// Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
// Retrieval info: <generic name="HARD_EMIF" value="true" />
// Retrieval info: <generic name="HHP_HPS" value="false" />
// Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
// Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
// Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
// Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
// Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
// Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
// Retrieval info: <generic name="AVL_MAX_SIZE" value="64" />
// Retrieval info: <generic name="BYTE_ENABLE" value="false" />
// Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
// Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
// Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
// Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
// Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
// Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
// Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
// Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
// Retrieval info: <generic name="ADDR_ORDER" value="0" />
// Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
// Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
// Retrieval info: <generic name="CFG_REORDER_DATA" value="true" />
// Retrieval info: <generic name="STARVE_LIMIT" value="10" />
// Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
// Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
// Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
// Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
// Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
// Retrieval info: <generic name="MULTICAST_EN" value="false" />
// Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
// Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
// Retrieval info: <generic name="DEBUG_MODE" value="false" />
// Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
// Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
// Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="false" />
// Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
// Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
// Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="16" />
// Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="32" />
// Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
// Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
// Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
// Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
// Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
// Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
// Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
// Retrieval info: <generic name="ENABLE_BONDING" value="false" />
// Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
// Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
// Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
// Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
// Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Read-only,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
// Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
// Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
// Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
// Retrieval info: <generic name="REF_CLK_FREQ" value="100.0" />
// Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
// Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
// Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
// Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
// Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
// Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
// Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
// Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
// Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
// Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
// Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
// Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
// Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
// Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
// Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
// Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
// Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
// Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
// Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
// Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
// Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
// Retrieval info: <generic name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
// Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
// Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
// Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
// Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
// Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
// Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
// Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
// Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
// Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
// Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
// Retrieval info: <generic name="PHY_ONLY" value="false" />
// Retrieval info: <generic name="SEQ_MODE" value="0" />
// Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
// Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
// Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
// Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
// Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
// Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
// Retrieval info: <generic name="MEM_VOLTAGE" value="1.5V DDR3" />
// Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
// Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
// Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
// Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
// Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
// Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
// Retrieval info: <generic name="CALIBRATION_MODE" value="Skip" />
// Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
// Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
// Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
// Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
// Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
// Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="SLEW_RATE" />
// Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="4.349" />
// Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="2.174" />
// Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="4.349" />
// Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="2.174" />
// Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
// Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
// Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
// Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
// Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
// Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.42" />
// Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.437" />
// Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.0039" />
// Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.012" />
// Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
// Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.011" />
// Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.029" />
// Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.004" />
// Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.0039" />
// Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.001" />
// Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
// Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="INTERNAL_JTAG" />
// Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
// Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
// Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
// Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
// Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
// Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
// Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
// Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
// Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
// Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
// Retrieval info: </instance>
// IPFS_FILES : NONE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A2111OI_BEHAVIORAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:02 12/01/2014
// Design Name:
// Module Name: EscrituraRegistroToMemoriaPrueba
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module EscrituraRegistroToMemoria#(parameter Width = 4)
(Read,InError,Address,ListoIn,InDato,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,
Coeff19,Offset,DatoEntradaSistema,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9,OutDato);
// InDato es la salida de la red Neuronal
// DatoEntradaSistema es el dato con el que se obtuvo una salida igual a InDato => InDato = f(DatoEntradaSistema)
input Read,InError,ListoIn;
input [8:0] Address;
input signed [Width-1:0] InDato,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,
Coeff17,Coeff18,Coeff19,Offset,DatoEntradaSistema,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9;
output reg signed [Width-1:0] OutDato;
always @*begin // Se escribe el dato en memoria
if(Read) begin
if(Address==9'h000 && ListoIn==1'b1) begin // Direcci�n de Indicador Dato Listo
OutDato <= 1;
end else if(Address==9'h004 ) begin // Direcci�n del Dato Listo
OutDato <= InDato;
end else if(Address==9'h008 && InError==1'b1) begin // Dato Indicandor de error
OutDato <= 1;
end else if(Address==9'h00C ) begin // CoeffEntrenamiento0
OutDato <= Coeff00;
end else if(Address==9'h010 ) begin // CoeffEntrenamiento1
OutDato <= Coeff01;
end else if(Address==9'h014 ) begin // CoeffEntrenamiento2
OutDato <= Coeff02;
end else if(Address==9'h018 ) begin // CoeffEntrenamiento3
OutDato <= Coeff03;
end else if(Address==9'h01C ) begin // CoeffEntrenamiento4
OutDato <= Coeff04;
end else if(Address==9'h020 ) begin // CoeffEntrenamiento5
OutDato <= Coeff05;
end else if(Address==9'h024 ) begin // CoeffEntrenamiento6
OutDato <= Coeff06;
end else if(Address==9'h028 ) begin // CoeffEntrenamiento7
OutDato <= Coeff07;
end else if(Address==9'h02C ) begin // CoeffEntrenamiento8
OutDato <= Coeff08;
end else if(Address==9'h030 ) begin // CoeffEntrenamiento9
OutDato <= Coeff09;
end else if(Address==9'h034 ) begin // CoeffEntrenamiento10
OutDato <= Coeff10;
end else if(Address==9'h038 ) begin // CoeffEntrenamient11
OutDato <= Coeff11;
end else if(Address==9'h03C ) begin // CoeffEntrenamiento12
OutDato <= Coeff12;
end else if(Address==9'h040 ) begin // CoeffEntrenamiento13
OutDato <= Coeff13;
end else if(Address==9'h044 ) begin // CoeffEntrenamiento14
OutDato <= Coeff14;
end else if(Address==9'h048 ) begin // CoeffEntrenamiento15
OutDato <= Coeff15;
end else if(Address==9'h04C ) begin // CoeffEntrenamiento16
OutDato <= Coeff16;
end else if(Address==9'h050 ) begin // CoeffEntrenamiento17
OutDato <= Coeff17;
end else if(Address==9'h054 ) begin // CoeffEntrenamiento18
OutDato <= Coeff18;
end else if(Address==9'h058 ) begin // CoeffEntrenamiento19
OutDato <= Coeff19;
end else if(Address==9'h05C ) begin // Offset
OutDato <= Offset;
end else if(Address==9'h060 ) begin // EntradadelSistema
OutDato <= DatoEntradaSistema;
end else if(Address==9'h064 ) begin // EntradadelSistema
OutDato <= Y0;
end else if(Address==9'h068 ) begin // EntradadelSistema
OutDato <= Y1;
end else if(Address==9'h06C ) begin // EntradadelSistema
OutDato <= Y2;
end else if(Address==9'h070 ) begin // EntradadelSistema
OutDato <= Y3;
end else if(Address==9'h074 ) begin // EntradadelSistema
OutDato <= Y4;
end else if(Address==9'h078 ) begin // EntradadelSistema
OutDato <= Y5;
end else if(Address==9'h07C ) begin // EntradadelSistema
OutDato <= Y6;
end else if(Address==9'h080 ) begin // EntradadelSistema
OutDato <= Y7;
end else if(Address==9'h084 ) begin // EntradadelSistema
OutDato <= Y8;
end else if(Address==9'h088 ) begin // EntradadelSistema
OutDato <= Y9;
end else begin
OutDato <= 0;
end
end
else begin
OutDato <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_TB_V
`define SKY130_FD_SC_HD__FAHCIN_TB_V
/**
* fahcin: Full adder, inverted carry in.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fahcin.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__fahcin dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_TB_V
|
module pipeline1(
clk_in, // clock_in
RST, // reset
pc_chg, // indica mudanca do PC fora do pipeline 1
pc_in, // entrada - contador de programa
instr, // instrucao
pc_out // saida - contador de programa
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// declaracao de entrada
input clk_in, RST, pc_chg;
input [PC_WIDTH-1:0] pc_in;
// declaracao de saida
output [INSTR_WIDTH-1:0] instr;
output [PC_WIDTH-1:0] pc_out;
// variaveis auxiliares
reg [PC_WIDTH-1:0] new_pc;
wire we, clk_neg;
wire [INSTR_WIDTH-1:0] data;
// instancia de Memoria ROM de programa
mem_program rom0(.clk(clk_neg), .we(we), .addr(new_pc), .data_in(data), .data_out(instr));
assign we = 0;
assign data = 0;
assign clk_neg = ~clk_in;
assign pc_out = new_pc + 1;
// defina o PC de leitura de memoria
always @(posedge clk_in) begin
if (!RST) begin
new_pc <= PC_INITIAL;
end else if (pc_chg) begin
new_pc <= pc_in;
end else begin
new_pc <= new_pc + 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_1_V
`define SKY130_FD_SC_LS__O311A_1_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_1_V
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
//include "registers.v"
module oq_regs
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH)
)
(
// --- interface to udp_reg_grp
reg_req_in,
reg_ack_in,
reg_rd_wr_L_in,
reg_addr_in,
reg_data_in,
reg_src_in,
reg_req_out,
reg_ack_out,
reg_rd_wr_L_out,
reg_addr_out,
reg_data_out,
reg_src_out,
// --- interface to remove_pkt
src_oq_rd_addr,
src_oq_high_addr,
src_oq_low_addr,
src_oq_empty,
src_oq_rd_addr_new,
pkt_removed,
removed_pkt_data_length,
removed_pkt_overhead_length,
removed_pkt_total_word_length,
src_oq,
removed_oq,
rd_src_addr,
enable_send_pkt,
// --- interface to store_pkt
dst_oq_wr_addr_new,
pkt_stored,
stored_pkt_data_length,
stored_pkt_overhead_length,
stored_pkt_total_word_length,
pkt_dropped,
dst_oq,
rd_dst_addr,
dst_oq_high_addr,
dst_oq_low_addr,
dst_oq_wr_addr,
dst_oq_full,
// --- Misc
clk,
reset
);
// --- interface to udp_reg_grp
input reg_req_in;
input reg_ack_in;
input reg_rd_wr_L_in;
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in;
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in;
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in;
output reg_req_out;
output reg_ack_out;
output reg_rd_wr_L_out;
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out;
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out;
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out;
// --- interface to remove_pkt
output [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr;
output [SRAM_ADDR_WIDTH-1:0] src_oq_high_addr;
output [SRAM_ADDR_WIDTH-1:0] src_oq_low_addr;
output [NUM_OUTPUT_QUEUES-1:0] src_oq_empty;
input [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr_new;
input pkt_removed;
input [PKT_LEN_WIDTH-1:0] removed_pkt_data_length;
input [CTRL_WIDTH-1:0] removed_pkt_overhead_length;
input [PKT_WORDS_WIDTH-1:0] removed_pkt_total_word_length;
input [NUM_OQ_WIDTH-1:0] src_oq;
input [NUM_OQ_WIDTH-1:0] removed_oq;
input rd_src_addr;
output [NUM_OUTPUT_QUEUES-1:0] enable_send_pkt;
// --- interface to store_pkt
input [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr_new;
input pkt_stored;
input [PKT_LEN_WIDTH-1:0] stored_pkt_data_length;
input [CTRL_WIDTH-1:0] stored_pkt_overhead_length;
input [PKT_WORDS_WIDTH-1:0] stored_pkt_total_word_length;
input pkt_dropped;
input [NUM_OQ_WIDTH-1:0] dst_oq;
input rd_dst_addr;
output [SRAM_ADDR_WIDTH-1:0] dst_oq_high_addr;
output [SRAM_ADDR_WIDTH-1:0] dst_oq_low_addr;
output [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr;
output [NUM_OUTPUT_QUEUES-1:0] dst_oq_full;
// --- Misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
localparam NUM_REGS_USED = 17;
localparam MAX_PKT = 2048/CTRL_WIDTH; // allow for 2K bytes
localparam MIN_PKT = 60/CTRL_WIDTH + 1; // allow for 2K bytes
localparam PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT);
localparam ADDR_WIDTH = log2(NUM_REGS_USED);
// ------------- Wires/reg ------------------
// Register interfaces
wire [NUM_OQ_WIDTH-1:0] reg_addr;
wire num_pkt_bytes_stored_reg_req;
wire num_pkt_bytes_stored_reg_ack;
wire num_pkt_bytes_stored_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_stored_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_stored_reg_rd_data;
wire num_overhead_bytes_stored_reg_req;
wire num_overhead_bytes_stored_reg_ack;
wire num_overhead_bytes_stored_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_stored_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_stored_reg_rd_data;
wire num_pkts_stored_reg_req;
wire num_pkts_stored_reg_ack;
wire num_pkts_stored_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_stored_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_stored_reg_rd_data;
wire num_pkts_dropped_reg_req;
wire num_pkts_dropped_reg_ack;
wire num_pkts_dropped_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_dropped_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_dropped_reg_rd_data;
wire num_pkt_bytes_removed_reg_req;
wire num_pkt_bytes_removed_reg_ack;
wire num_pkt_bytes_removed_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_removed_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_removed_reg_rd_data;
wire num_overhead_bytes_removed_reg_req;
wire num_overhead_bytes_removed_reg_ack;
wire num_overhead_bytes_removed_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_removed_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_removed_reg_rd_data;
wire num_pkts_removed_reg_req;
wire num_pkts_removed_reg_ack;
wire num_pkts_removed_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_removed_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_removed_reg_rd_data;
wire oq_addr_hi_reg_req;
wire oq_addr_hi_reg_ack;
wire oq_addr_hi_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_hi_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_hi_reg_rd_data;
wire oq_addr_lo_reg_req;
wire oq_addr_lo_reg_ack;
wire oq_addr_lo_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_lo_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_lo_reg_rd_data;
wire oq_wr_addr_reg_req;
wire oq_wr_addr_reg_ack;
wire oq_wr_addr_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_wr_addr_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_wr_addr_reg_rd_data;
wire oq_rd_addr_reg_req;
wire oq_rd_addr_reg_ack;
wire oq_rd_addr_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_rd_addr_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_rd_addr_reg_rd_data;
wire max_pkts_in_q_reg_req;
wire max_pkts_in_q_reg_ack;
wire max_pkts_in_q_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] max_pkts_in_q_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] max_pkts_in_q_reg_rd_data;
wire num_pkts_in_q_reg_req;
wire num_pkts_in_q_reg_ack;
wire num_pkts_in_q_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_in_q_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_in_q_reg_rd_data;
wire num_words_left_reg_req;
wire num_words_left_reg_ack;
wire num_words_left_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_left_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_left_reg_rd_data;
wire num_words_in_q_reg_req;
wire num_words_in_q_reg_ack;
wire num_words_in_q_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_in_q_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_in_q_reg_rd_data;
wire oq_full_thresh_reg_req;
wire oq_full_thresh_reg_ack;
wire oq_full_thresh_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_full_thresh_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_full_thresh_reg_rd_data;
// Values used to calculate full/emtpy state
wire [PKTS_IN_RAM_WIDTH-1:0] max_pkts_in_q_dst;
wire [PKTS_IN_RAM_WIDTH-1:0] num_pkts_in_q_dst;
wire num_pkts_in_q_dst_wr_done;
wire [PKTS_IN_RAM_WIDTH-1:0] max_pkts_in_q_src;
wire [PKTS_IN_RAM_WIDTH-1:0] num_pkts_in_q_src;
wire num_pkts_in_q_src_wr_done;
wire [SRAM_ADDR_WIDTH-1:0] oq_full_thresh_dst;
wire [SRAM_ADDR_WIDTH-1:0] num_words_left_dst;
wire num_words_left_dst_wr_done;
wire [SRAM_ADDR_WIDTH-1:0] oq_full_thresh_src;
wire [SRAM_ADDR_WIDTH-1:0] num_words_left_src;
wire num_words_left_src_wr_done;
// --- interface to oq_regs_host_iface
wire reg_req;
wire reg_rd_wr_L_held;
wire [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_held;
wire [ADDR_WIDTH-1:0] addr;
wire [NUM_OQ_WIDTH-1:0] q_addr;
wire result_ready;
wire [`CPCI_NF2_DATA_WIDTH-1:0] reg_result;
wire [NUM_OUTPUT_QUEUES-1:0] empty;
wire [NUM_OUTPUT_QUEUES-1:0] full;
wire initialize;
wire [NUM_OQ_WIDTH-1:0] initialize_oq;
// --------- logic ---------------------------
assign src_oq_empty = empty;
assign dst_oq_full = full;
// -------------------------------------------
// Control module
// -- Contains logic for resetting the queues, initalizing the queues on
// writes to the control register and logic to process register requests
// from the host
// -------------------------------------------
oq_regs_ctrl
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.NUM_REGS_USED (NUM_REGS_USED),
.MAX_PKT (MAX_PKT), // allow for 2K bytes
.PKT_LEN_WIDTH (PKT_LEN_WIDTH)
) oq_regs_ctrl (
// --- interface to store/remove pkt
.enable (enable_send_pkt),
// --- interface to oq_regs_host_iface
.reg_req (req_in_progress),
.reg_rd_wr_L_held (reg_rd_wr_L_held),
.reg_data_held (reg_data_held),
.addr (addr),
.q_addr (q_addr),
.result_ready (result_ready),
.reg_result (reg_result),
// --- Interface to full/empty generation logic
.initialize (initialize),
.initialize_oq (initialize_oq),
// Register interfaces
.reg_addr (reg_addr),
.num_pkt_bytes_stored_reg_req (num_pkt_bytes_stored_reg_req),
.num_pkt_bytes_stored_reg_ack (num_pkt_bytes_stored_reg_ack),
.num_pkt_bytes_stored_reg_wr (num_pkt_bytes_stored_reg_wr),
.num_pkt_bytes_stored_reg_wr_data (num_pkt_bytes_stored_reg_wr_data),
.num_pkt_bytes_stored_reg_rd_data (num_pkt_bytes_stored_reg_rd_data),
.num_overhead_bytes_stored_reg_req (num_overhead_bytes_stored_reg_req),
.num_overhead_bytes_stored_reg_ack (num_overhead_bytes_stored_reg_ack),
.num_overhead_bytes_stored_reg_wr (num_overhead_bytes_stored_reg_wr),
.num_overhead_bytes_stored_reg_wr_data (num_overhead_bytes_stored_reg_wr_data),
.num_overhead_bytes_stored_reg_rd_data (num_overhead_bytes_stored_reg_rd_data),
.num_pkts_stored_reg_req (num_pkts_stored_reg_req),
.num_pkts_stored_reg_ack (num_pkts_stored_reg_ack),
.num_pkts_stored_reg_wr (num_pkts_stored_reg_wr),
.num_pkts_stored_reg_wr_data (num_pkts_stored_reg_wr_data),
.num_pkts_stored_reg_rd_data (num_pkts_stored_reg_rd_data),
.num_pkts_dropped_reg_req (num_pkts_dropped_reg_req),
.num_pkts_dropped_reg_ack (num_pkts_dropped_reg_ack),
.num_pkts_dropped_reg_wr (num_pkts_dropped_reg_wr),
.num_pkts_dropped_reg_wr_data (num_pkts_dropped_reg_wr_data),
.num_pkts_dropped_reg_rd_data (num_pkts_dropped_reg_rd_data),
.num_pkt_bytes_removed_reg_req (num_pkt_bytes_removed_reg_req),
.num_pkt_bytes_removed_reg_ack (num_pkt_bytes_removed_reg_ack),
.num_pkt_bytes_removed_reg_wr (num_pkt_bytes_removed_reg_wr),
.num_pkt_bytes_removed_reg_wr_data (num_pkt_bytes_removed_reg_wr_data),
.num_pkt_bytes_removed_reg_rd_data (num_pkt_bytes_removed_reg_rd_data),
.num_overhead_bytes_removed_reg_req (num_overhead_bytes_removed_reg_req),
.num_overhead_bytes_removed_reg_ack (num_overhead_bytes_removed_reg_ack),
.num_overhead_bytes_removed_reg_wr (num_overhead_bytes_removed_reg_wr),
.num_overhead_bytes_removed_reg_wr_data(num_overhead_bytes_removed_reg_wr_data),
.num_overhead_bytes_removed_reg_rd_data(num_overhead_bytes_removed_reg_rd_data),
.num_pkts_removed_reg_req (num_pkts_removed_reg_req),
.num_pkts_removed_reg_ack (num_pkts_removed_reg_ack),
.num_pkts_removed_reg_wr (num_pkts_removed_reg_wr),
.num_pkts_removed_reg_wr_data (num_pkts_removed_reg_wr_data),
.num_pkts_removed_reg_rd_data (num_pkts_removed_reg_rd_data),
.oq_addr_hi_reg_req (oq_addr_hi_reg_req),
.oq_addr_hi_reg_ack (oq_addr_hi_reg_ack),
.oq_addr_hi_reg_wr (oq_addr_hi_reg_wr),
.oq_addr_hi_reg_wr_data (oq_addr_hi_reg_wr_data),
.oq_addr_hi_reg_rd_data (oq_addr_hi_reg_rd_data),
.oq_addr_lo_reg_req (oq_addr_lo_reg_req),
.oq_addr_lo_reg_ack (oq_addr_lo_reg_ack),
.oq_addr_lo_reg_wr (oq_addr_lo_reg_wr),
.oq_addr_lo_reg_wr_data (oq_addr_lo_reg_wr_data),
.oq_addr_lo_reg_rd_data (oq_addr_lo_reg_rd_data),
.oq_wr_addr_reg_req (oq_wr_addr_reg_req),
.oq_wr_addr_reg_ack (oq_wr_addr_reg_ack),
.oq_wr_addr_reg_wr (oq_wr_addr_reg_wr),
.oq_wr_addr_reg_wr_data (oq_wr_addr_reg_wr_data),
.oq_wr_addr_reg_rd_data (oq_wr_addr_reg_rd_data),
.oq_rd_addr_reg_req (oq_rd_addr_reg_req),
.oq_rd_addr_reg_ack (oq_rd_addr_reg_ack),
.oq_rd_addr_reg_wr (oq_rd_addr_reg_wr),
.oq_rd_addr_reg_wr_data (oq_rd_addr_reg_wr_data),
.oq_rd_addr_reg_rd_data (oq_rd_addr_reg_rd_data),
.max_pkts_in_q_reg_req (max_pkts_in_q_reg_req),
.max_pkts_in_q_reg_ack (max_pkts_in_q_reg_ack),
.max_pkts_in_q_reg_wr (max_pkts_in_q_reg_wr),
.max_pkts_in_q_reg_wr_data (max_pkts_in_q_reg_wr_data),
.max_pkts_in_q_reg_rd_data (max_pkts_in_q_reg_rd_data),
.num_pkts_in_q_reg_req (num_pkts_in_q_reg_req),
.num_pkts_in_q_reg_ack (num_pkts_in_q_reg_ack),
.num_pkts_in_q_reg_wr (num_pkts_in_q_reg_wr),
.num_pkts_in_q_reg_wr_data (num_pkts_in_q_reg_wr_data),
.num_pkts_in_q_reg_rd_data (num_pkts_in_q_reg_rd_data),
.num_words_left_reg_req (num_words_left_reg_req),
.num_words_left_reg_ack (num_words_left_reg_ack),
.num_words_left_reg_wr (num_words_left_reg_wr),
.num_words_left_reg_wr_data (num_words_left_reg_wr_data),
.num_words_left_reg_rd_data (num_words_left_reg_rd_data),
.num_words_in_q_reg_req (num_words_in_q_reg_req),
.num_words_in_q_reg_ack (num_words_in_q_reg_ack),
.num_words_in_q_reg_wr (num_words_in_q_reg_wr),
.num_words_in_q_reg_wr_data (num_words_in_q_reg_wr_data),
.num_words_in_q_reg_rd_data (num_words_in_q_reg_rd_data),
.oq_full_thresh_reg_req (oq_full_thresh_reg_req),
.oq_full_thresh_reg_ack (oq_full_thresh_reg_ack),
.oq_full_thresh_reg_wr (oq_full_thresh_reg_wr),
.oq_full_thresh_reg_wr_data (oq_full_thresh_reg_wr_data),
.oq_full_thresh_reg_rd_data (oq_full_thresh_reg_rd_data),
// --- Misc
.clk (clk),
.reset (reset)
);
// -------------------------------------------
// Empty/full signal generation logic
// -- Analyzes the number of packets/number of words in each queue on
// updates
// -------------------------------------------
oq_regs_eval_empty
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH (PKT_LEN_WIDTH),
.MAX_PKT (MAX_PKT)
) oq_regs_eval_empty (
// --- Inputs from dst update ---
.dst_update (pkt_stored),
.dst_oq (dst_oq),
.dst_num_pkts_in_q (num_pkts_in_q_dst),
.dst_num_pkts_in_q_done (num_pkts_in_q_dst_wr_done),
// --- Inputs from src update ---
.src_update (pkt_removed),
.src_oq (removed_oq),
.src_num_pkts_in_q (num_pkts_in_q_src),
.src_num_pkts_in_q_done (num_pkts_in_q_src_wr_done),
// --- Clear the flag ---
.initialize (initialize),
.initialize_oq (initialize_oq),
.empty (empty),
// --- Misc
.clk (clk),
.reset (reset)
);
oq_regs_eval_full
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH (PKT_LEN_WIDTH),
.MAX_PKT (MAX_PKT)
) oq_regs_eval_full (
// --- Inputs from dst update ---
.dst_update (pkt_stored),
.dst_oq (dst_oq),
.dst_max_pkts_in_q (max_pkts_in_q_dst),
.dst_num_pkts_in_q (num_pkts_in_q_dst),
.dst_num_pkts_in_q_done (num_pkts_in_q_dst_wr_done),
.dst_oq_full_thresh (oq_full_thresh_dst),
.dst_num_words_left (num_words_left_dst),
.dst_num_words_left_done (num_words_left_dst_wr_done),
// --- Inputs from src update ---
.src_update (pkt_removed),
.src_oq (removed_oq),
.src_max_pkts_in_q (max_pkts_in_q_src),
.src_num_pkts_in_q (num_pkts_in_q_src),
.src_num_pkts_in_q_done (num_pkts_in_q_src_wr_done),
.src_oq_full_thresh (oq_full_thresh_src),
.src_num_words_left (num_words_left_src),
.src_num_words_left_done (num_words_left_src_wr_done),
// --- Clear the flag ---
.initialize (initialize),
.initialize_oq (initialize_oq),
.full (full),
// --- Misc
.clk (clk),
.reset (reset)
);
// -------------------------------------------
// Host interface module
// -- initial processing of incoming register
// requests
// -- most of the register processing is handed
// off to oq_regs_host_ctrl
// -------------------------------------------
oq_regs_host_iface
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.NUM_REGS_USED (NUM_REGS_USED)
) oq_regs_host_iface (
// --- interface to udp_reg_grp
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- interface to oq_regs_process_sm
.req_in_progress (req_in_progress),
.reg_rd_wr_L_held (reg_rd_wr_L_held),
.reg_data_held (reg_data_held),
.addr (addr),
.q_addr (q_addr),
.result_ready (result_ready),
.reg_result (reg_result),
// --- Misc
.clk (clk),
.reset (reset)
);
// -------------------------------------------
// Register instances module
// -- Holds the memory instances for all registers except the control
// register
// -------------------------------------------
oq_reg_instances
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH (PKT_LEN_WIDTH),
.MAX_PKT (MAX_PKT)
) oq_reg_instances (
// --- interface to remove_pkt
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
// --- interface to store_pkt
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.pkt_dropped (pkt_dropped),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
// Register interfaces
.reg_addr (reg_addr),
.num_pkt_bytes_stored_reg_req (num_pkt_bytes_stored_reg_req),
.num_pkt_bytes_stored_reg_ack (num_pkt_bytes_stored_reg_ack),
.num_pkt_bytes_stored_reg_wr (num_pkt_bytes_stored_reg_wr),
.num_pkt_bytes_stored_reg_wr_data (num_pkt_bytes_stored_reg_wr_data),
.num_pkt_bytes_stored_reg_rd_data (num_pkt_bytes_stored_reg_rd_data),
.num_overhead_bytes_stored_reg_req (num_overhead_bytes_stored_reg_req),
.num_overhead_bytes_stored_reg_ack (num_overhead_bytes_stored_reg_ack),
.num_overhead_bytes_stored_reg_wr (num_overhead_bytes_stored_reg_wr),
.num_overhead_bytes_stored_reg_wr_data(num_overhead_bytes_stored_reg_wr_data),
.num_overhead_bytes_stored_reg_rd_data(num_overhead_bytes_stored_reg_rd_data),
.num_pkts_stored_reg_req (num_pkts_stored_reg_req),
.num_pkts_stored_reg_ack (num_pkts_stored_reg_ack),
.num_pkts_stored_reg_wr (num_pkts_stored_reg_wr),
.num_pkts_stored_reg_wr_data (num_pkts_stored_reg_wr_data),
.num_pkts_stored_reg_rd_data (num_pkts_stored_reg_rd_data),
.num_pkts_dropped_reg_req (num_pkts_dropped_reg_req),
.num_pkts_dropped_reg_ack (num_pkts_dropped_reg_ack),
.num_pkts_dropped_reg_wr (num_pkts_dropped_reg_wr),
.num_pkts_dropped_reg_wr_data (num_pkts_dropped_reg_wr_data),
.num_pkts_dropped_reg_rd_data (num_pkts_dropped_reg_rd_data),
.num_pkt_bytes_removed_reg_req (num_pkt_bytes_removed_reg_req),
.num_pkt_bytes_removed_reg_ack (num_pkt_bytes_removed_reg_ack),
.num_pkt_bytes_removed_reg_wr (num_pkt_bytes_removed_reg_wr),
.num_pkt_bytes_removed_reg_wr_data (num_pkt_bytes_removed_reg_wr_data),
.num_pkt_bytes_removed_reg_rd_data (num_pkt_bytes_removed_reg_rd_data),
.num_overhead_bytes_removed_reg_req (num_overhead_bytes_removed_reg_req),
.num_overhead_bytes_removed_reg_ack (num_overhead_bytes_removed_reg_ack),
.num_overhead_bytes_removed_reg_wr (num_overhead_bytes_removed_reg_wr),
.num_overhead_bytes_removed_reg_wr_data(num_overhead_bytes_removed_reg_wr_data),
.num_overhead_bytes_removed_reg_rd_data(num_overhead_bytes_removed_reg_rd_data),
.num_pkts_removed_reg_req (num_pkts_removed_reg_req),
.num_pkts_removed_reg_ack (num_pkts_removed_reg_ack),
.num_pkts_removed_reg_wr (num_pkts_removed_reg_wr),
.num_pkts_removed_reg_wr_data (num_pkts_removed_reg_wr_data),
.num_pkts_removed_reg_rd_data (num_pkts_removed_reg_rd_data),
.oq_addr_hi_reg_req (oq_addr_hi_reg_req),
.oq_addr_hi_reg_ack (oq_addr_hi_reg_ack),
.oq_addr_hi_reg_wr (oq_addr_hi_reg_wr),
.oq_addr_hi_reg_wr_data (oq_addr_hi_reg_wr_data),
.oq_addr_hi_reg_rd_data (oq_addr_hi_reg_rd_data),
.oq_addr_lo_reg_req (oq_addr_lo_reg_req),
.oq_addr_lo_reg_ack (oq_addr_lo_reg_ack),
.oq_addr_lo_reg_wr (oq_addr_lo_reg_wr),
.oq_addr_lo_reg_wr_data (oq_addr_lo_reg_wr_data),
.oq_addr_lo_reg_rd_data (oq_addr_lo_reg_rd_data),
.oq_wr_addr_reg_req (oq_wr_addr_reg_req),
.oq_wr_addr_reg_ack (oq_wr_addr_reg_ack),
.oq_wr_addr_reg_wr (oq_wr_addr_reg_wr),
.oq_wr_addr_reg_wr_data (oq_wr_addr_reg_wr_data),
.oq_wr_addr_reg_rd_data (oq_wr_addr_reg_rd_data),
.oq_rd_addr_reg_req (oq_rd_addr_reg_req),
.oq_rd_addr_reg_ack (oq_rd_addr_reg_ack),
.oq_rd_addr_reg_wr (oq_rd_addr_reg_wr),
.oq_rd_addr_reg_wr_data (oq_rd_addr_reg_wr_data),
.oq_rd_addr_reg_rd_data (oq_rd_addr_reg_rd_data),
.max_pkts_in_q_reg_req (max_pkts_in_q_reg_req),
.max_pkts_in_q_reg_ack (max_pkts_in_q_reg_ack),
.max_pkts_in_q_reg_wr (max_pkts_in_q_reg_wr),
.max_pkts_in_q_reg_wr_data (max_pkts_in_q_reg_wr_data),
.max_pkts_in_q_reg_rd_data (max_pkts_in_q_reg_rd_data),
.num_pkts_in_q_reg_req (num_pkts_in_q_reg_req),
.num_pkts_in_q_reg_ack (num_pkts_in_q_reg_ack),
.num_pkts_in_q_reg_wr (num_pkts_in_q_reg_wr),
.num_pkts_in_q_reg_wr_data (num_pkts_in_q_reg_wr_data),
.num_pkts_in_q_reg_rd_data (num_pkts_in_q_reg_rd_data),
.num_words_left_reg_req (num_words_left_reg_req),
.num_words_left_reg_ack (num_words_left_reg_ack),
.num_words_left_reg_wr (num_words_left_reg_wr),
.num_words_left_reg_wr_data (num_words_left_reg_wr_data),
.num_words_left_reg_rd_data (num_words_left_reg_rd_data),
.num_words_in_q_reg_req (num_words_in_q_reg_req),
.num_words_in_q_reg_ack (num_words_in_q_reg_ack),
.num_words_in_q_reg_wr (num_words_in_q_reg_wr),
.num_words_in_q_reg_wr_data (num_words_in_q_reg_wr_data),
.num_words_in_q_reg_rd_data (num_words_in_q_reg_rd_data),
.oq_full_thresh_reg_req (oq_full_thresh_reg_req),
.oq_full_thresh_reg_ack (oq_full_thresh_reg_ack),
.oq_full_thresh_reg_wr (oq_full_thresh_reg_wr),
.oq_full_thresh_reg_wr_data (oq_full_thresh_reg_wr_data),
.oq_full_thresh_reg_rd_data (oq_full_thresh_reg_rd_data),
// Values used to calculate full/emtpy state
.max_pkts_in_q_dst (max_pkts_in_q_dst),
.num_pkts_in_q_dst (num_pkts_in_q_dst),
.num_pkts_in_q_dst_wr_done (num_pkts_in_q_dst_wr_done),
.max_pkts_in_q_src (max_pkts_in_q_src),
.num_pkts_in_q_src (num_pkts_in_q_src),
.num_pkts_in_q_src_wr_done (num_pkts_in_q_src_wr_done),
.oq_full_thresh_dst (oq_full_thresh_dst),
.num_words_left_dst (num_words_left_dst),
.num_words_left_dst_wr_done (num_words_left_dst_wr_done),
.oq_full_thresh_src (oq_full_thresh_src),
.num_words_left_src (num_words_left_src),
.num_words_left_src_wr_done (num_words_left_src_wr_done),
// --- Misc
.clk (clk),
.reset (reset)
);
endmodule // oq_regs
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_response_handler (
input clk,
input resetn,
input bvalid,
output bready,
input [1:0] bresp,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] wait_id,
input sync_id,
input enable,
output reg enabled,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
parameter C_ID_WIDTH = 3;
`include "resp.v"
`include "inc_id.v"
assign resp_resp = bresp;
assign resp_eot = eot;
wire active = id != wait_id && enabled;
assign bready = active && resp_ready;
assign resp_valid = active && bvalid;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (wait_id == id)
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
if ((bready && bvalid) ||
(sync_id && id != wait_id))
id <= inc_id(id);
end
end
endmodule
|
module mux_32to1 (
input [4:0] s,
input i31, i30, i29, i28, i27, i26, i25, i24, i23,i22, i21, i20, i19, i18, i17, i16,
input i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0,
output z);
wire int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7;
wire int8 , int9 , int10, int11, int12, int13, int14, int15;
not (s0_bar, s[0]);
not (s1_bar, s[1]);
not (s2_bar, s[2]);
not (s3_bar, s[3]);
not (s4_bar, s[4]);
and(int0 , i0 , s4_bar, s3_bar , s2_bar , s1_bar , s0_bar );
and(int1 , i1 , s4_bar, s3_bar , s2_bar , s1_bar , s[0] );
and(int2 , i2 , s4_bar, s3_bar , s2_bar , s[1] , s0_bar );
and(int3 , i3 , s4_bar, s3_bar , s2_bar , s[1] , s[0] );
and(int4 , i4 , s4_bar, s3_bar , s[2] , s1_bar , s0_bar );
and(int5 , i5 , s4_bar, s3_bar , s[2] , s1_bar , s[0] );
and(int6 , i6 , s4_bar, s3_bar , s[2] , s[1] , s0_bar );
and(int7 , i7 , s4_bar, s3_bar , s[2] , s[1] , s[0] );
and(int8 , i8 , s4_bar, s[3] , s2_bar , s1_bar , s0_bar );
and(int9 , i9 , s4_bar, s[3] , s2_bar , s1_bar , s[0] );
and(int10, i10, s4_bar, s[3] , s2_bar , s[1] , s0_bar );
and(int11, i11, s4_bar, s[3] , s2_bar , s[1] , s[0] );
and(int12, i12, s4_bar, s[3] , s[2] , s1_bar , s0_bar );
and(int13, i13, s4_bar, s[3] , s[2] , s1_bar , s[0] );
and(int14, i14, s4_bar, s[3] , s[2] , s[1] , s0_bar );
and(int15, i15, s4_bar, s[3] , s[2] , s[1] , s[0] );
and(int16, i16, s[4] ,s3_bar , s2_bar , s1_bar , s0_bar );
and(int17, i17, s[4] ,s3_bar , s2_bar , s1_bar , s[0] );
and(int18, i18, s[4] ,s3_bar , s2_bar , s[1] , s0_bar );
and(int19, i19, s[4] ,s3_bar , s2_bar , s[1] , s[0] );
and(int20, i20, s[4] ,s3_bar , s[2] , s1_bar , s0_bar );
and(int21, i21, s[4] ,s3_bar , s[2] , s1_bar , s[0] );
and(int22, i22, s[4] ,s3_bar , s[2] , s[1] , s0_bar );
and(int23, i23, s[4] ,s3_bar , s[2] , s[1] , s[0] );
and(int24, i24, s[4] ,s[3] , s2_bar , s1_bar , s0_bar );
and(int25, i25, s[4] ,s[3] , s2_bar , s1_bar , s[0] );
and(int26, i26, s[4] ,s[3] , s2_bar , s[1] , s0_bar );
and(int27, i27, s[4] ,s[3] , s2_bar , s[1] , s[0] );
and(int28, i28, s[4] ,s[3] , s[2] , s1_bar , s0_bar );
and(int29, i29, s[4] ,s[3] , s[2] , s1_bar , s[0] );
and(int30, i30, s[4] ,s[3] , s[2] , s[1] , s0_bar );
and(int31, i31, s[4] ,s[3] , s[2] , s[1] , s[0] );
or (z, int31, int30, int29, int28, int27, int26, int25,
int24, int23,int22, int21, int20, int19, int18, int17,
int16, int0, int1, int2, int3, int4, int5, int6, int7,
int8, int9, int10, int11, int12, int13, int14, int15);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ps/1ps
module mig_7series_v2_0_bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,
rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,
dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,
phy_mc_cmd_full, phy_mc_data_full
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input phy_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v
input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v
input rnk_config_strobe; // To bank_state0 of bank_state.v
input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v
input rnk_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input maint_sre_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sending_pre;
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output rts_pre;
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
mig_7series_v2_0_bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
mig_7series_v2_0_bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.rtc (rtc),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
mig_7series_v2_0_bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
// based on https://people.ece.cornell.edu/land/courses/ece5760/DE2/indexVGA.html
// read sram or switch and output color to screen
module vgaram
(
input wire clk50,
input wire [3:0] key,
input wire [17:0] sw,
inout wire [15:0] sram_dq,
output wire [19:0] sram_addr,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_we_n,
output wire sram_ce_n,
output wire sram_oe_n,
output wire vga_clk,
output wire vga_hs,
output wire vga_vs,
output wire vga_blank,
output wire vga_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b
);
wire rst;
wire vga_ctrl_clk;
wire [7:0] r, g, b;
wire [9:0] x, y;
assign sram_addr = {x[9:0], y[9:0]};
// hi byte select enabled
assign sram_ub_n = 0;
// low byte select enabled
assign sram_lb_n = 0;
// chip enable
assign sram_ce_n = 0;
// output enable is overriden by WE
assign sram_oe_n = 0;
// if key 1 is not pressed then float, otherwise
// drive it with data from sw to be stored in SRAM
assign sram_we_n = {key[0] ? 1 : 0};
assign sram_dq = (key[0] ? 16'hzzzz :
(key[1] ? {x[8:5], y[8:5] & ~{4{x[9]}}, y[8:5] & {4{x[9]}}, 4'b0} :
sw[15:0]));
// assign color based on contents of sram
assign r = {sram_dq[15:12], 4'b0};
assign g = {sram_dq[11:8], 4'b0};
assign b = {sram_dq[7:4], 4'b0};
// delay a little before resetting the device for board to power up
reset_delay r0(
.clk(clk50),
.rst(rst)
);
// vga needs ~25 mhz for 640x480 at 60 hz
// c0 is the rate at which we update the vga signals at
// c1 is a phase delay of 90 degree which we output to the vga clock
// meaning vga clock gets clocked and updated a little later than we
// update the internal vga signals like sync rgb data
pll p0(
.areset(~rst),
.inclk0(clk50),
.c0(vga_ctrl_clk),
.c1(vga_clk)
);
// vga controller that gets color from r, g, b
vga v0(
.clk(vga_ctrl_clk),
.rst(rst),
.r(r),
.g(g),
.b(b),
.x(x),
.y(y),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC TAG RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of data cache tag rams. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_tag.v,v $
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_dc_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_DCTAG_W;
parameter aw = `OR1200_DCTAG;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_256x21 dc_tag0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_512x20 dc_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// UTMI Line Status & Speed Negotiation block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_utmi_ls.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_utmi_ls.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.6 2003/11/11 07:15:16 rudi
// Fixed Resume signaling and initial attachment
//
// Revision 1.5 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.4 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.3 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
//
// Revision 1.2 2001/08/10 08:48:33 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.2 2001/03/31 13:00:52 rudi
//
// - Added Core configuration
// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
// - Modified WISHBONE interface and sync logic
// - Moved SSRAM outside the core (added interface)
// - Many small bug fixes ...
//
// Revision 1.1 2001/03/07 09:08:13 rudi
//
// Added USB control signaling (Line Status) block. Fixed some minor
// typos, added resume bit and signal.
//
//
//
`include "usbf_defines.v"
module usbf_utmi_ls( clk, rst,
resume_req,
// UTMI Interface
rx_active, tx_ready, drive_k,
XcvSelect, TermSel, SuspendM, LineState, OpMode,
usb_vbus,
// Misc Interfaces
mode_hs, usb_reset, usb_suspend, usb_attached,
suspend_clr
);
input clk;
//input wclk;
input rst;
input resume_req;
input rx_active, tx_ready;
output drive_k;
output XcvSelect;
output TermSel;
output SuspendM;
input [1:0] LineState;
output [1:0] OpMode;
input usb_vbus;
output mode_hs; // High Speed Mode
output usb_reset; // USB Reset
output usb_suspend; // USB Suspend
output usb_attached; // Attached to USB
output suspend_clr;
///////////////////////////////////////////////////////////////////
//
// Parameters
//
parameter [14:0]
POR = 15'b000_0000_0000_0001,
NORMAL = 15'b000_0000_0000_0010,
RES_SUSP = 15'b000_0000_0000_0100,
SUSPEND = 15'b000_0000_0000_1000,
RESUME = 15'b000_0000_0001_0000,
RESUME_REQUEST = 15'b000_0000_0010_0000,
RESUME_WAIT = 15'b000_0000_0100_0000,
RESUME_SIG = 15'b000_0000_1000_0000,
ATTACH = 15'b000_0001_0000_0000,
RESET = 15'b000_0010_0000_0000,
SPEED_NEG = 15'b000_0100_0000_0000,
SPEED_NEG_K = 15'b000_1000_0000_0000,
SPEED_NEG_J = 15'b001_0000_0000_0000,
SPEED_NEG_HS = 15'b010_0000_0000_0000,
SPEED_NEG_FS = 15'b100_0000_0000_0000;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [14:0] state, next_state;
reg [1:0] line_state_r;
reg mode_hs, mode_set_hs, mode_set_fs;
reg usb_suspend, suspend_set, suspend_clr;
reg usb_attached, attached_set, attached_clr;
reg TermSel, fs_term_on, fs_term_off;
reg XcvSelect, xcv_set_hs, xcv_set_fs;
reg [1:0] OpMode;
reg bit_stuff_on, bit_stuff_off;
reg usb_reset, usb_reset_d;
wire ls_se0, ls_j, ls_k, ls_se1;
reg ls_k_r, ls_j_r, ls_se0_r;
reg ls_idle_r;
wire ls_idle;
reg idle_long;
wire idle_long_set, idle_long_clr;
wire k_long, j_long, se0_long;
reg drive_k, drive_k_d;
reg [3:0] ps_cnt;
reg ps_cnt_clr;
reg idle_cnt_clr;
reg idle_cnt1_clr;
reg [7:0] idle_cnt1, idle_cnt1_next;
reg T1_gt_2_5_uS, T1_st_3_0_mS, T1_gt_3_0_mS;
reg T1_gt_3_125_mS, T1_gt_5_0_mS;
reg [7:0] me_ps;
reg me_cnt_clr;
reg me_ps_2_5_us;
reg [7:0] me_ps2;
reg me_ps2_0_5_ms;
reg [7:0] me_cnt;
reg me_cnt_100_ms;
reg T2_gt_100_uS, T2_wakeup, T2_gt_1_0_mS, T2_gt_1_2_mS;
reg [2:0] chirp_cnt;
reg chirp_cnt_clr, chirp_cnt_inc;
reg chirp_cnt_is_6;
reg resume_req_s1;
reg resume_req_s;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
drive_k <= drive_k_d;
assign SuspendM = (usb_suspend & !resume_req_s) | (LineState == 2'b10);
always @(posedge clk)
resume_req_s1 <= resume_req;
always @(posedge clk)
resume_req_s <= resume_req_s1;
// ---------------------------------------------------------
// USB State/Operation Mode JK Flops
always @(posedge clk)
if(mode_set_fs) mode_hs <= 1'b0;
else
if(mode_set_hs) mode_hs <= 1'b1;
always @(posedge clk)
if(suspend_clr) usb_suspend <= 1'b0;
else
if(suspend_set) usb_suspend <= 1'b1;
always @(posedge clk)
if(attached_clr) usb_attached <= 1'b0;
else
if(attached_set) usb_attached <= 1'b1;
always @(posedge clk)
if(fs_term_off) TermSel <= 1'b0;
else
if(fs_term_on) TermSel <= 1'b1;
always @(posedge clk)
if(xcv_set_fs) XcvSelect <= 1'b1;
else
if(xcv_set_hs) XcvSelect <= 1'b0;
always @(posedge clk)
if(bit_stuff_off) OpMode <= 2'b10;
else
if(bit_stuff_on) OpMode <= 2'b00;
always @(posedge clk)
usb_reset <= usb_reset_d;
// ---------------------------------------------------------
// Line State Detector
always @(posedge clk)
line_state_r <= LineState;
assign ls_se0 = (line_state_r == 2'b00);
assign ls_j = (line_state_r == 2'b01);
assign ls_k = (line_state_r == 2'b10);
assign ls_se1 = (line_state_r == 2'b11);
assign ls_idle = mode_hs ? ls_se0 : ls_j;
// Idle Detection
// Idle Has to persist for at least two cycles in a roe in the
// same state to recognized
always @(posedge clk)
ls_idle_r <= ls_idle;
assign idle_long_set = ls_idle & ls_idle_r;
assign idle_long_clr = !ls_idle & !ls_idle_r;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) idle_long <= 1'b0;
//to the prefered high reset
if(rst) idle_long <= 1'b0;
else
if(idle_long_clr) idle_long <= 1'b0;
else
if(idle_long_set) idle_long <= 1'b1;
// Detect Signals for two cycles ina row before making a transaction ...
always @(posedge clk)
ls_k_r <= ls_k;
always @(posedge clk)
ls_j_r <= ls_j;
always @(posedge clk)
ls_se0_r <= ls_se0;
assign k_long = ls_k & ls_k_r;
assign j_long = ls_j & ls_j_r;
assign se0_long = ls_se0 & ls_se0_r;
///////////////////////////////////////////////////////////////////
//
// Counters
//
// ---------------------------------------------------------
// idle Counter
// Pre-Scaler
// Generates a 0.25 uS Count Enable (ps_cnt_clr)
always @(posedge clk)
if(!idle_long || idle_cnt_clr || ps_cnt_clr) ps_cnt <= 4'd0;
else ps_cnt <= ps_cnt + 4'd1;
always @(posedge clk) // Clear the pre-scaler in 250 nS intervals
ps_cnt_clr <= (ps_cnt == `USBF_T1_PS_250_NS);
// Count uS
always @(posedge clk)
if(!idle_long || idle_cnt1_clr || idle_cnt_clr) idle_cnt1 <= 8'h0;
else
if(!T1_gt_5_0_mS && ps_cnt_clr) idle_cnt1 <= idle_cnt1_next;
always @(posedge clk)
idle_cnt1_next <= idle_cnt1 + 8'h1;
always @(posedge clk) // Clear the uS counter every 62.5 uS
idle_cnt1_clr <= idle_cnt1 == `USBF_T1_C_62_5_US;
always @(posedge clk) // Greater Than 2.5uS (Actual Time will be T0+2.75uS)
T1_gt_2_5_uS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_2_5_US);
always @(posedge clk) // Smaller Than 3 mS (Actual Time will be 0-2.9375mS)
T1_st_3_0_mS <= !idle_cnt_clr & (idle_cnt1 < `USBF_T1_C_3_0_MS);
always @(posedge clk) // Greater Than 3 mS (Actual Time will be T0+3.0625mS)
T1_gt_3_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_0_MS);
always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS)
T1_gt_3_125_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_125_MS);
always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS)
T1_gt_5_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_5_MS);
// ---------------------------------------------------------
// Misc Events Counter
// Pre-scaler - 2.5uS
always @(posedge clk)
if(me_cnt_clr || me_ps_2_5_us) me_ps <= 8'h0;
else me_ps <= me_ps + 8'h1;
always @(posedge clk) // Generate a pulse every 2.5 uS
me_ps_2_5_us <= (me_ps == `USBF_T2_C_2_5_US);
// Second Pre-scaler - 0.5mS
always @(posedge clk)
if(me_cnt_clr || me_ps2_0_5_ms ) me_ps2 <= 8'h0;
else
if(me_ps_2_5_us) me_ps2 <= me_ps2 + 8'h1;
always @(posedge clk) // Generate a pulse every 0.5 mS
me_ps2_0_5_ms <= (me_ps2 == `USBF_T2_C_0_5_MS) & !me_ps2_0_5_ms;
// final misc Counter
always @(posedge clk)
if(me_cnt_clr) me_cnt <= 8'h0;
else
if(!me_cnt_100_ms && me_ps2_0_5_ms) me_cnt <= me_cnt + 8'h1;
always @(posedge clk) // Indicate when 100uS have passed
T2_gt_100_uS <= !me_cnt_clr & (me_ps2 > `USBF_T2_C_100_US); // Actual Time: 102.5 uS
always @(posedge clk) // Indicate when wakeup period has passed
T2_wakeup <= !me_cnt_clr & (me_cnt > `USBF_T2_C_WAKEUP);
always @(posedge clk) // Indicate when 1 mS has passed
T2_gt_1_0_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_0_MS); // Actual Time: 1.5 mS
always @(posedge clk) // Indicate when 1.2 mS has passed
T2_gt_1_2_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_2_MS); // Actual Time: 1.5 mS
always @(posedge clk) // Generate a pulse after 100 mS
me_cnt_100_ms <= !me_cnt_clr & (me_cnt == `USBF_T2_C_100_MS); // Actual Time: 100 mS
// ---------------------------------------------------------
// Chirp Counter
always @(posedge clk)
if(chirp_cnt_clr) chirp_cnt <= 3'h0;
else
if(chirp_cnt_inc) chirp_cnt <= chirp_cnt + 3'h1;
always @(posedge clk)
chirp_cnt_is_6 <= (chirp_cnt == 3'h6);
///////////////////////////////////////////////////////////////////
//
// Main State Machine
//
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) state <= POR;
//to the prefered high reset
if(rst) state <= POR;
else
if(usb_vbus) state <= POR;
else state <= next_state;
always @(state or mode_hs or idle_long or resume_req_s or me_cnt_100_ms or
j_long or k_long or se0_long or ls_se0 or
T1_gt_2_5_uS or T1_st_3_0_mS or T1_gt_3_0_mS or
T1_gt_5_0_mS or T2_gt_100_uS or T2_wakeup or T2_gt_1_0_mS or
T2_gt_1_2_mS or chirp_cnt_is_6)
begin
next_state = state; // Default don't change state
mode_set_hs = 1'b0;
mode_set_fs = 1'b0;
suspend_set = 1'b0;
suspend_clr = 1'b0;
attached_set = 1'b0;
attached_clr = 1'b0;
usb_reset_d = 1'b0;
fs_term_on = 1'b0;
fs_term_off = 1'b0;
xcv_set_hs = 1'b0;
xcv_set_fs = 1'b0;
bit_stuff_on = 1'b0;
bit_stuff_off = 1'b0;
idle_cnt_clr = 1'b0;
me_cnt_clr = 1'b0;
drive_k_d = 1'b0;
chirp_cnt_clr = 1'b0;
chirp_cnt_inc = 1'b0;
case(state) // synopsys full_case parallel_case
POR: // Power On/Reset
begin
me_cnt_clr = 1'b1;
xcv_set_fs = 1'b1;
fs_term_on = 1'b1;
mode_set_fs = 1'b1;
attached_clr = 1'b1;
bit_stuff_on = 1'b0;
suspend_clr = 1'b1;
next_state = ATTACH;
end
NORMAL: // Normal Operation
begin
if(!mode_hs && T1_gt_2_5_uS && T1_st_3_0_mS && !idle_long)
begin
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(!mode_hs && T1_gt_3_0_mS)
begin
idle_cnt_clr = 1'b1;
suspend_set = 1'b1;
next_state = SUSPEND;
end
else
if(mode_hs && T1_gt_3_0_mS)
begin // Switch to FS mode, and decide
// if it's a RESET or SUSPEND
me_cnt_clr = 1'b1;
xcv_set_fs = 1'b1;
fs_term_on = 1'b1;
next_state = RES_SUSP;
end
end
RES_SUSP: // Decide if it's a Reset or Suspend Signaling
begin // We are now in FS mode, wait 100uS first
if(T2_gt_100_uS && se0_long)
begin
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(T2_gt_100_uS && j_long)
begin
idle_cnt_clr = 1'b1;
suspend_set = 1'b1;
next_state = SUSPEND;
end
end
SUSPEND: // In Suspend
begin
if(T1_gt_2_5_uS && se0_long)
begin
suspend_clr = 1'b1;
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(k_long) // Start Resuming
next_state = RESUME;
else
if(T1_gt_5_0_mS && resume_req_s)
next_state = RESUME_REQUEST;
end
RESUME:
begin
suspend_clr = 1'b1;
if(ls_se0)
begin
if(mode_hs)
begin // Switch Back to HS mode
xcv_set_hs = 1'b1;
fs_term_off = 1'b1;
end
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
me_cnt_clr = 1'b1;
next_state = RESUME_WAIT;
end
end
RESUME_WAIT:
begin
if(T2_gt_100_uS) next_state = NORMAL;
end
RESUME_REQUEST: // Function Resume Request
begin
suspend_clr = 1'b1;
// Wait for internal wake up
if(T2_wakeup)
begin
fs_term_on = 1'b1; // Switch Termination to Full Speed
bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding
me_cnt_clr = 1'b1;
next_state = RESUME_SIG;
end
end
RESUME_SIG: // Signal resume
begin
// Drive Resume ('K') for 1-15 mS
drive_k_d = 1'b1;
// Stop driving after 1.5 mS
if(T2_gt_1_0_mS) next_state = RESUME;
end
ATTACH: // Attach To USB Detected
begin
idle_cnt_clr = 1'b1;
if(me_cnt_100_ms)
//if(me_cnt_100_ms && j_long)
begin
attached_set = 1'b1;
next_state = NORMAL;
end
/*
if(me_cnt_100_ms && se0_long)
begin
attached_set = 1'b1;
me_cnt_clr = 1'b1;
next_state = RESET;
end
*/
end
RESET: // In Reset
begin
usb_reset_d = 1'b1; // Assert Internal USB Reset
xcv_set_hs = 1'b1; // Switch xcvr to HS mode
fs_term_on = 1'b1; // Turn FS termination On
mode_set_fs = 1'b1; // Change mode to FS
bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding
// Get out of reset after 1.5 mS
if(T2_gt_1_0_mS)
begin
me_cnt_clr = 1'b1;
next_state = SPEED_NEG;
end
end
SPEED_NEG: // Speed Negotiation
begin
drive_k_d = 1'b1;
chirp_cnt_clr = 1'b1;
// Start looking for 'K' after 1.5 mS
if(T2_gt_1_2_mS) next_state = SPEED_NEG_K;
end
SPEED_NEG_K:
begin
if(chirp_cnt_is_6) next_state = SPEED_NEG_HS;
else
begin
if(k_long)
begin
chirp_cnt_inc = 1'b1;
next_state = SPEED_NEG_J;
end
if(se0_long)
next_state = SPEED_NEG_FS;
end
end
SPEED_NEG_J:
begin
if(chirp_cnt_is_6) next_state = SPEED_NEG_HS;
else
begin
if(j_long)
begin
chirp_cnt_inc = 1'b1;
next_state = SPEED_NEG_K;
end
if(se0_long)
next_state = SPEED_NEG_FS;
end
end
SPEED_NEG_HS:
begin
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
xcv_set_hs = 1'b1; // Switch xcvr to HS mode
fs_term_off = 1'b1; // Turn FS termination Off
mode_set_hs = 1'b1; // Change mode to HS
if(se0_long) next_state = NORMAL;
end
SPEED_NEG_FS:
begin
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
xcv_set_fs = 1'b1; // Switch xcvr to FS mode
fs_term_on = 1'b1; // Turn FS termination On
mode_set_fs = 1'b1; // Change mode to FS
next_state = NORMAL;
end
endcase
end
endmodule
|
// nios_system_nios2_qsys_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2016.05.04.10:35:18
`timescale 1 ps / 1 ps
module nios_system_nios2_qsys_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [18:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [18:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_system_nios2_qsys_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_6_V
`define SKY130_FD_SC_HDLL__NOR4_6_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_6 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_6 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_6_V
|
// ======================================================================
// Erebus_Sensor.v generated from TopDesign.cysch
// 06/05/2014 at 22:00
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 1
`define CYDEV_CHIP_REV_EXPECT 3
`define CYDEV_CHIP_DIE_ACTUAL 1
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 3
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 4
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 1
`define CYDEV_CHIP_MEMBER_USED 1
`define CYDEV_CHIP_REVISION_USED 3
// RTC_v2_0(DstEnable=false, StartOfWeek=0, CY_COMPONENT_NAME=RTC_v2_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=RTC, CY_INSTANCE_SHORT_NAME=RTC, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=RTC, )
module RTC_v2_0_0 ;
wire Net_5;
cy_isr_v1_0
#(.int_type(2'b10))
isr
(.int_signal(Net_5));
cy_gsref_v1_0
#(.guid("2C8B7907-32C2-4035-8A12-D819F94023EF"))
gsRef_1
(.sig_out(Net_5));
endmodule
// Component: demux_v1_10
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v"
`endif
// Component: nor_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\nor_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\nor_v1_0\nor_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\nor_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\nor_v1_0\nor_v1_0.v"
`endif
// Component: CyControlReg_v1_70
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v"
`endif
// Component: cy_vref_v1_60
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_vref_v1_60"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_vref_v1_60\cy_vref_v1_60.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_vref_v1_60"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_vref_v1_60\cy_vref_v1_60.v"
`endif
// Component: cy_analog_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`endif
// Component: AMux_v1_80
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMux_v1_80"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMux_v1_80\AMux_v1_80.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMux_v1_80"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMux_v1_80\AMux_v1_80.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// ADC_DelSig_v3_0(ADC_Alignment=0, ADC_Alignment_Config2=0, ADC_Alignment_Config3=0, ADC_Alignment_Config4=0, ADC_Charge_Pump_Clock=true, ADC_Clock=1, ADC_CLOCK_FREQUENCY=150000, ADC_Input_Mode=1, ADC_Input_Range=2, ADC_Input_Range_Config2=4, ADC_Input_Range_Config3=4, ADC_Input_Range_Config4=4, ADC_Power=1, ADC_Reference=5, ADC_Reference_Config2=0, ADC_Reference_Config3=0, ADC_Reference_Config4=0, ADC_Resolution=12, ADC_Resolution_Config2=16, ADC_Resolution_Config3=16, ADC_Resolution_Config4=16, Clock_Frequency=64000, Comment_Config1=Default Config, Comment_Config2=Second Config, Comment_Config3=Third Config, Comment_Config4=Fourth Config, Config1_Name=CFG1, Config2_Name=CFG2, Config3_Name=CFG3, Config4_Name=CFG4, Configs=1, Conversion_Mode=0, Conversion_Mode_Config2=2, Conversion_Mode_Config3=2, Conversion_Mode_Config4=2, Enable_Vref_Vss=false, EnableModulatorInput=false, Input_Buffer_Gain=1, Input_Buffer_Gain_Config2=1, Input_Buffer_Gain_Config3=1, Input_Buffer_Gain_Config4=1, Input_Buffer_Mode=1, Input_Buffer_Mode_Config2=1, Input_Buffer_Mode_Config3=1, Input_Buffer_Mode_Config4=1, Ref_Voltage=1.25, Ref_Voltage_Config2=1.024, Ref_Voltage_Config3=1.024, Ref_Voltage_Config4=1.024, rm_int=false, Sample_Rate=1000, Sample_Rate_Config2=10000, Sample_Rate_Config3=10000, Sample_Rate_Config4=10000, Start_of_Conversion=0, Vdda_Value=5, CY_COMPONENT_NAME=ADC_DelSig_v3_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=ADC, CY_INSTANCE_SHORT_NAME=ADC, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=ADC, )
module ADC_DelSig_v3_0_1 (
vplus,
vminus,
soc,
eoc,
aclk,
nVref,
mi);
inout vplus;
electrical vplus;
inout vminus;
electrical vminus;
input soc;
output eoc;
input aclk;
inout nVref;
electrical nVref;
input mi;
wire Net_268;
wire Net_270;
wire Net_252;
wire Net_251;
wire Net_250;
electrical Net_249;
electrical Net_257;
electrical Net_248;
electrical Net_23;
wire Net_247;
wire aclock;
wire [3:0] mod_dat;
wire mod_reset;
electrical Net_352;
wire Net_246;
wire [7:0] Net_245;
wire Net_482;
electrical Net_34;
electrical Net_35;
electrical Net_244;
wire Net_93;
electrical Net_20;
electrical Net_690;
electrical Net_686;
electrical Net_520;
wire Net_481;
electrical Net_677;
electrical Net_41;
electrical Net_573;
electrical Net_109;
wire Net_488;
cy_vref_v1_0
#(.autoenable(1),
.guid("15B3DB15-B7B3-4d62-A2DF-25EA392A7161"),
.name("Vssa (GND)"))
vRef_2
(.vout(Net_244));
// cy_analog_virtualmux_6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_6_connect(Net_690, Net_35);
defparam cy_analog_virtualmux_6_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_34));
// cy_analog_virtualmux_4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_4_connect(Net_677, Net_34);
defparam cy_analog_virtualmux_4_connect.sig_width = 1;
// -- AMux AMux start -- ***
// -- Mux A --
cy_psoc3_amux_v1_0 AMux(
.muxin({
Net_690,
Net_244
}),
.vout(Net_20)
);
defparam AMux.muxin_width = 2;
defparam AMux.init_mux_sel = 2'h0;
defparam AMux.one_active = 0;
defparam AMux.connect_mode = 1;
// -- AMux AMux end --
cy_psoc3_ds_mod_v4_0 DSM (
.vplus(vplus),
.vminus(Net_520),
.modbit(Net_481),
.reset_udb(Net_482),
.aclock(Net_488),
.mod_dat(mod_dat[3:0]),
.dout_udb(Net_245[7:0]),
.reset_dec(mod_reset),
.dec_clock(aclock),
.extclk_cp_udb(Net_93),
.clk_udb(1'b0),
.ext_pin_1(Net_573),
.ext_pin_2(Net_41),
.ext_vssa(Net_109),
.qtz_ref(Net_677));
defparam DSM.resolution = 12;
cy_analog_noconnect_v1_0 cy_analog_noconnect_5 (
.noconnect(Net_352));
// cy_analog_virtualmux_5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_5_connect(Net_109, Net_352);
defparam cy_analog_virtualmux_5_connect.sig_width = 1;
cy_clock_v1_0
#(.id("3191f881-3e8e-486e-997a-395fee1f9105/b7604721-db56-4477-98c2-8fae77869066"),
.source_clock_id("61737EF6-3B74-48f9-8B91-F7473A442AE7"),
.divisor(1),
.period("0"),
.is_direct(0),
.is_digital(1))
Ext_CP_Clk
(.clock_out(Net_93));
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_257));
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_249));
// cy_analog_virtualmux_3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_3_connect(Net_41, Net_257);
defparam cy_analog_virtualmux_3_connect.sig_width = 1;
// cy_analog_virtualmux_2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_2_connect(Net_573, Net_249);
defparam cy_analog_virtualmux_2_connect.sig_width = 1;
// cy_analog_virtualmux_1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_1_connect(Net_520, Net_20);
defparam cy_analog_virtualmux_1_connect.sig_width = 1;
cy_isr_v1_0
#(.int_type(2'b10))
IRQ
(.int_signal(eoc));
// Clock_VirtualMux (cy_virtualmux_v1_0)
assign Net_488 = Net_250;
cy_clock_v1_0
#(.id("3191f881-3e8e-486e-997a-395fee1f9105/edd15f43-b66b-457b-be3a-5342345270c8"),
.source_clock_id("61737EF6-3B74-48f9-8B91-F7473A442AE7"),
.divisor(0),
.period("6666666666.66667"),
.is_direct(0),
.is_digital(0))
theACLK
(.clock_out(Net_250));
ZeroTerminal ZeroTerminal_2 (
.z(Net_482));
// Clock_VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_481 = Net_252;
cy_psoc3_decimator_v1_0 DEC (
.aclock(aclock),
.mod_dat(mod_dat[3:0]),
.ext_start(soc),
.mod_reset(mod_reset),
.interrupt(eoc));
ZeroTerminal ZeroTerminal_1 (
.z(Net_252));
assign Net_268 = Net_93 | Net_270;
ZeroTerminal ZeroTerminal_3 (
.z(Net_270));
endmodule
// USBFS_v2_60(AudioDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_60"> <Tree_x0020_Descriptors> <DescriptorNode Key="Audio"> <Nodes /> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, CDCDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_60"> <Tree_x0020_Descriptors> <DescriptorNode Key="CDC"> <Nodes> <DescriptorNode Key="Interface718"> <Value d6p1:type="InterfaceGeneralDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 1</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor717"> <Value d8p1:type="CyCommunicationsInterfaceDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>649</iwInterface> <bInterfaceClass>2</bInterfaceClass> <bNumEndpoints>1</bNumEndpoints> <bInterfaceSubClass>2</bInterfaceSubClass> <bInterfaceProtocol>1</bInterfaceProtocol> <iInterface>0</iInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor719"> <Value d10p1:type="CyCDCHeaderDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>HEADER</bDescriptorSubtype> <bcdADC>272</bcdADC> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor720"> <Value d10p1:type="CyCDCAbstractControlMgmtDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>4</bLength> <bDescriptorSubtype>ABSTRACT_CONTROL_MANAGEMENT</bDescriptorSubtype> <bmCapabilities>2</bmCapabilities> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor721"> <Value d10p1:type="CyCDCUnionDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>UNION</bDescriptorSubtype> <bSubordinateInterface>AQ==</bSubordinateInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor722"> <Value d10p1:type="CyCDCCallManagementDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>CALL_MANAGEMENT</bDescriptorSubtype> <bDataInterface>1</bDataInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor723"> <Value d10p1:type="EndpointDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bEndpointAddress>129</bEndpointAddress> <bmAttributes>3</bmAttributes> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> <DescriptorNode Key="Interface725"> <Value d6p1:type="InterfaceGeneralDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 2</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor724"> <Value d8p1:type="CyDataInterfaceDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>650</iwInterface> <bInterfaceClass>10</bInterfaceClass> <bInterfaceNumber>1</bInterfaceNumber> <bNumEndpoints>2</bNumEndpoints> <bInterfaceSubClass>0</bInterfaceSubClass> <bInterfaceProtocol>0</bInterfaceProtocol> <iInterface>0</iInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor726"> <Value d10p1:type="EndpointDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bEndpointAddress>130</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor727"> <Value d10p1:type="EndpointDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bEndpointAddress>3</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, DeviceDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_60"> <Tree_x0020_Descriptors> <DescriptorNode Key="Device"> <Nodes> <DescriptorNode Key="USBDescriptor651"> <Value d6p1:type="DeviceDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>DEVICE</bDescriptorType> <bLength>18</bLength> <iwManufacturer>647</iwManufacturer> <iwProduct>648</iwProduct> <sManufacturer>Erebus Labs</sManufacturer> <sProduct>STEM Sensor Rev 0.1</sProduct> <sSerialNumber /> <bDeviceClass>2</bDeviceClass> <bDeviceSubClass>0</bDeviceSubClass> <bDeviceProtocol>0</bDeviceProtocol> <bMaxPacketSize0>0</bMaxPacketSize0> <idVendor>1204</idVendor> <idProduct>62002</idProduct> <bcdDevice>1</bcdDevice> <iManufacturer>1</iManufacturer> <iProduct>2</iProduct> <iSerialNumber>128</iSerialNumber> <bNumConfigurations>1</bNumConfigurations> <bMemoryMgmt>0</bMemoryMgmt> <bMemoryAlloc>0</bMemoryAlloc> </Value> <Nodes> <DescriptorNode Key="USBDescriptor656"> <Value d8p1:type="ConfigDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CONFIGURATION</bDescriptorType> <bLength>9</bLength> <iwConfiguration>647</iwConfiguration> <sConfiguration>Erebus Labs</sConfiguration> <wTotalLength>67</wTotalLength> <bNumInterfaces>2</bNumInterfaces> <bConfigurationValue>0</bConfigurationValue> <iConfiguration>1</iConfiguration> <bmAttributes>192</bmAttributes> <bMaxPower>50</bMaxPower> </Value> <Nodes> <DescriptorNode Key="Interface718"> <Value d10p1:type="InterfaceGeneralDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 1</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor717"> <Value d12p1:type="CyCommunicationsInterfaceDescriptor" xmlns:d12p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>649</iwInterface> <bInterfaceClass>2</bInterfaceClass> <bNumEndpoints>1</bNumEndpoints> <bInterfaceSubClass>2</bInterfaceSubClass> <bInterfaceProtocol>1</bInterfaceProtocol> <iInterface>0</iInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor719"> <Value d14p1:type="CyCDCHeaderDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>HEADER</bDescriptorSubtype> <bcdADC>272</bcdADC> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor720"> <Value d14p1:type="CyCDCAbstractControlMgmtDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>4</bLength> <bDescriptorSubtype>ABSTRACT_CONTROL_MANAGEMENT</bDescriptorSubtype> <bmCapabilities>2</bmCapabilities> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor721"> <Value d14p1:type="CyCDCUnionDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>UNION</bDescriptorSubtype> <bSubordinateInterface>AQ==</bSubordinateInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor722"> <Value d14p1:type="CyCDCCallManagementDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>CDC</bDescriptorType> <bLength>5</bLength> <bDescriptorSubtype>CALL_MANAGEMENT</bDescriptorSubtype> <bDataInterface>1</bDataInterface> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor723"> <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bEndpointAddress>129</bEndpointAddress> <bmAttributes>3</bmAttributes> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> <DescriptorNode Key="Interface725"> <Value d10p1:type="InterfaceGeneralDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ALTERNATE</bDescriptorType> <bLength>0</bLength> <DisplayName>CDC Interface 2</DisplayName> </Value> <Nodes> <DescriptorNode Key="USBDescriptor724"> <Value d12p1:type="CyDataInterfaceDescriptor" xmlns:d12p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>INTERFACE</bDescriptorType> <bLength>9</bLength> <iwInterface>650</iwInterface> <bInterfaceClass>10</bInterfaceClass> <bInterfaceNumber>1</bInterfaceNumber> <bNumEndpoints>2</bNumEndpoints> <bInterfaceSubClass>0</bInterfaceSubClass> <bInterfaceProtocol>0</bInterfaceProtocol> <iInterface>0</iInterface> </Value> <Nodes> <DescriptorNode Key="USBDescriptor726"> <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bEndpointAddress>130</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor727"> <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>ENDPOINT</bDescriptorType> <bLength>7</bLength> <DoubleBuffer>false</DoubleBuffer> <bEndpointAddress>3</bEndpointAddress> <bmAttributes>2</bmAttributes> <wMaxPacketSize>64</wMaxPacketSize> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Nodes> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, EnableCDCApi=true, EnableMidiApi=true, endpointMA=0, endpointMM=0, extern_cls=false, extern_vbus=false, extern_vnd=false, extJackCount=0, HIDReportDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_60"> <Tree_x0020_Descriptors> <DescriptorNode Key="HIDReport"> <Nodes /> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, max_interfaces_num=2, MidiDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_60"> <Tree_x0020_Descriptors> <DescriptorNode Key="Midi"> <Nodes /> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, Mode=false, mon_vbus=false, out_sof=false, Pid=F232, rm_arb_int=false, rm_dma_1=true, rm_dma_2=true, rm_dma_3=true, rm_dma_4=true, rm_dma_5=true, rm_dma_6=true, rm_dma_7=true, rm_dma_8=true, rm_dp_int=false, rm_ep_isr_0=false, rm_ep_isr_1=false, rm_ep_isr_2=false, rm_ep_isr_3=false, rm_ep_isr_4=true, rm_ep_isr_5=true, rm_ep_isr_6=true, rm_ep_isr_7=true, rm_ep_isr_8=true, rm_ord_int=true, rm_sof_int=false, rm_usb_int=false, StringDescriptors=<?xml version="1.0" encoding="utf-16"?> <Tree xmlns:CustomizerVersion="2_60"> <Tree_x0020_Descriptors> <DescriptorNode Key="String"> <Nodes> <DescriptorNode Key="LANGID"> <Value d6p1:type="StringZeroDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>4</bLength> <wLANGID>1033</wLANGID> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor647"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>24</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>Erebus Labs</bString> <bUsed>false</bUsed> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="USBDescriptor648"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>40</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>STEM Sensor Rev 0.1</bString> <bUsed>false</bUsed> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> <DescriptorNode Key="SpecialString"> <Nodes> <DescriptorNode Key="Serial"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>2</bLength> <snType>SILICON_NUMBER</snType> <bString /> <bUsed>true</bUsed> </Value> <Nodes /> </DescriptorNode> <DescriptorNode Key="EE"> <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance"> <bDescriptorType>STRING</bDescriptorType> <bLength>16</bLength> <snType>USER_ENTERED_TEXT</snType> <bString>MSFT100</bString> <bUsed>true</bUsed> </Value> <Nodes /> </DescriptorNode> </Nodes> </DescriptorNode> </Tree_x0020_Descriptors> </Tree>, Vid=04B4, CY_COMPONENT_NAME=USBFS_v2_60, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=USBUART, CY_INSTANCE_SHORT_NAME=USBUART, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=60, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=USBUART, )
module USBFS_v2_60_2 (
sof,
vbusdet);
output sof;
input vbusdet;
wire [7:0] dma_req;
wire [8:0] ept_int;
wire Net_1106;
wire [7:0] Net_1105;
wire Net_1104;
wire Net_1103;
wire Net_1102;
wire Net_1101;
wire Net_1100;
wire Net_1099;
wire Net_1098;
wire Net_1097;
wire Net_1096;
wire Net_1013;
wire Net_1014;
wire Net_1015;
wire Net_1016;
wire Net_1017;
wire Net_1018;
wire Net_1019;
wire Net_1020;
wire Net_1010;
electrical Net_1000;
wire Net_79;
wire Net_81;
wire Net_95;
electrical Net_597;
wire Net_824;
cy_psoc3_usb_v1_0 USB (
.dp(Net_1000),
.dm(Net_597),
.sof_int(sof),
.arb_int(Net_79),
.usb_int(Net_81),
.ept_int(ept_int[8:0]),
.ord_int(Net_95),
.dma_req(dma_req[7:0]),
.dma_termin(Net_824));
cy_isr_v1_0
#(.int_type(2'b10))
sof_int
(.int_signal(sof));
cy_isr_v1_0
#(.int_type(2'b10))
arb_int
(.int_signal(Net_79));
cy_isr_v1_0
#(.int_type(2'b10))
bus_reset
(.int_signal(Net_81));
cy_isr_v1_0
#(.int_type(2'b10))
ep_0
(.int_signal(ept_int[0:0]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_1
(.int_signal(ept_int[1:1]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_2
(.int_signal(ept_int[2:2]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_3
(.int_signal(ept_int[3:3]));
wire [0:0] tmpOE__Dm_net;
wire [0:0] tmpFB_0__Dm_net;
wire [0:0] tmpIO_0__Dm_net;
wire [0:0] tmpINTERRUPT_0__Dm_net;
electrical [0:0] tmpSIOVREF__Dm_net;
cy_psoc3_pins_v1_10
#(.id("2b269b96-47a4-4e9a-937e-76d4080bb211/8b77a6c4-10a0-4390-971c-672353e2a49c"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("NONCONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(1),
.vtrip(2'b10),
.width(1))
Dm
(.oe(tmpOE__Dm_net),
.y({1'b0}),
.fb({tmpFB_0__Dm_net[0:0]}),
.analog({Net_597}),
.io({tmpIO_0__Dm_net[0:0]}),
.siovref(tmpSIOVREF__Dm_net),
.interrupt({tmpINTERRUPT_0__Dm_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dm_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Dp_net;
wire [0:0] tmpFB_0__Dp_net;
wire [0:0] tmpIO_0__Dp_net;
electrical [0:0] tmpSIOVREF__Dp_net;
cy_psoc3_pins_v1_10
#(.id("2b269b96-47a4-4e9a-937e-76d4080bb211/618a72fc-5ddd-4df5-958f-a3d55102db42"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
Dp
(.oe(tmpOE__Dp_net),
.y({1'b0}),
.fb({tmpFB_0__Dp_net[0:0]}),
.analog({Net_1000}),
.io({tmpIO_0__Dp_net[0:0]}),
.siovref(tmpSIOVREF__Dp_net),
.interrupt({Net_1010}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dp_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
dp_int
(.int_signal(Net_1010));
cy_clock_v1_0
#(.id("2b269b96-47a4-4e9a-937e-76d4080bb211/03f503a7-085a-4304-b786-de885b1c2f21"),
.source_clock_id("75C2148C-3656-4d8a-846D-0CAE99AB6FF7"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(1))
Clock_vbus
(.clock_out(Net_1099));
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// Component: B_PWM_v3_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_PWM_v3_0"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_PWM_v3_0\B_PWM_v3_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_PWM_v3_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_PWM_v3_0\B_PWM_v3_0.v"
`endif
// Component: OneTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`endif
// PWM_v3_0(CaptureMode=0, Compare1_16=false, Compare1_8=false, Compare2_16=false, Compare2_8=true, CompareStatusEdgeSense=true, CompareType1=1, CompareType1Software=0, CompareType2=3, CompareType2Software=0, CompareValue1=127, CompareValue2=127, CONTROL3=0, ControlReg=true, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, DeadBand=0, DeadBand2_4=0, DeadBand256=0, DeadBandUsed=0, DeadTime=1, DitherOffset=0, EnableMode=0, FF16=false, FF8=false, FixedFunction=false, FixedFunctionUsed=0, InterruptOnCMP1=false, InterruptOnCMP2=false, InterruptOnKill=false, InterruptOnTC=false, IntOnCMP1=0, IntOnCMP2=0, IntOnKill=0, IntOnTC=0, KillMode=0, KillModeMinTime=0, MinimumKillTime=1, OneCompare=false, Period=255, PWMMode=1, PWMModeCenterAligned=0, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, Resolution=8, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, Status=false, TriggerMode=0, UDB16=false, UDB8=true, UseControl=true, UseInterrupt=false, UseStatus=false, VerilogSectionReplacementString=sP8, CY_COMPONENT_NAME=PWM_v3_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LED_PWM, CY_INSTANCE_SHORT_NAME=LED_PWM, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LED_PWM, )
module PWM_v3_0_3 (
pwm2,
tc,
clock,
reset,
pwm1,
interrupt,
capture,
kill,
enable,
trigger,
cmp_sel,
pwm,
ph1,
ph2);
output pwm2;
output tc;
input clock;
input reset;
output pwm1;
output interrupt;
input capture;
input kill;
input enable;
input trigger;
input cmp_sel;
output pwm;
output ph1;
output ph2;
parameter Resolution = 8;
wire Net_114;
wire Net_113;
wire Net_107;
wire Net_96;
wire Net_55;
wire Net_57;
wire Net_101;
wire Net_54;
wire Net_63;
B_PWM_v3_0 PWMUDB (
.reset(reset),
.clock(clock),
.tc(Net_101),
.pwm1(pwm1),
.pwm2(pwm2),
.interrupt(Net_55),
.kill(kill),
.capture(capture),
.enable(enable),
.cmp_sel(cmp_sel),
.trigger(trigger),
.pwm(Net_96),
.ph1(ph1),
.ph2(ph2));
defparam PWMUDB.CaptureMode = 0;
defparam PWMUDB.CompareStatusEdgeSense = 1;
defparam PWMUDB.CompareType1 = 1;
defparam PWMUDB.CompareType2 = 3;
defparam PWMUDB.DeadBand = 0;
defparam PWMUDB.DitherOffset = 0;
defparam PWMUDB.EnableMode = 0;
defparam PWMUDB.KillMode = 0;
defparam PWMUDB.PWMMode = 1;
defparam PWMUDB.Resolution = 8;
defparam PWMUDB.RunMode = 0;
defparam PWMUDB.TriggerMode = 0;
defparam PWMUDB.UseStatus = 0;
// vmCompare (cy_virtualmux_v1_0)
assign pwm = Net_96;
// vmIRQ (cy_virtualmux_v1_0)
assign interrupt = Net_55;
// vmTC (cy_virtualmux_v1_0)
assign tc = Net_101;
OneTerminal OneTerminal_1 (
.o(Net_113));
// FFKillMux (cy_virtualmux_v1_0)
assign Net_107 = Net_114;
ZeroTerminal ZeroTerminal_1 (
.z(Net_114));
endmodule
// top
module top ;
wire Net_1574;
wire Net_1573;
wire Net_1572;
wire Net_1571;
wire Net_1570;
wire Net_1569;
wire Net_1567;
wire Net_1529;
wire Net_1489;
wire Net_1488;
wire Net_1487;
wire Net_1486;
wire Net_1485;
wire Net_1484;
wire Net_1483;
wire Net_1482;
wire Net_1481;
wire Net_1480;
wire Net_1509;
wire Net_1508;
wire Net_1507;
wire Net_1506;
wire Net_1505;
wire Net_1504;
wire Net_1503;
wire Net_1502;
wire Net_1501;
wire Net_1500;
wire Net_1348;
wire Net_1347;
wire Net_563;
electrical Net_562;
wire Net_561;
wire Net_566;
wire Net_559;
electrical Net_558;
wire Net_1499;
wire Net_1498;
wire Net_1497;
wire Net_1496;
wire Net_1495;
wire Net_1494;
wire Net_1493;
wire Net_1492;
wire Net_1491;
wire Net_1490;
wire Net_1405;
wire Net_1478;
wire Net_1524;
wire Net_1664;
wire Net_1634;
wire Net_1632;
electrical Net_1602;
electrical Net_1603;
electrical Net_1593;
wire Net_1566;
wire Net_1461;
wire Net_1462;
wire Net_1568;
wire Net_1464;
wire Net_1479;
wire Net_1565;
wire Net_1467;
wire Net_1468;
wire [1:0] Net_1460;
wire [1:0] Net_1410;
wire Net_1525;
wire Net_1415;
wire Net_1409;
wire Net_1309;
wire Net_1308;
RTC_v2_0_0 RTC ();
// -- De Mux start --
if (1)
begin : demux_2
reg tmp__demux_2_0_reg;
reg tmp__demux_2_1_reg;
reg tmp__demux_2_2_reg;
reg tmp__demux_2_3_reg;
always @(Net_1415 or Net_1460)
begin
case (Net_1460[1:0])
2'b00:
begin
tmp__demux_2_0_reg = Net_1415;
tmp__demux_2_1_reg = 1'b0;
tmp__demux_2_2_reg = 1'b0;
tmp__demux_2_3_reg = 1'b0;
end
2'b01:
begin
tmp__demux_2_0_reg = 1'b0;
tmp__demux_2_1_reg = Net_1415;
tmp__demux_2_2_reg = 1'b0;
tmp__demux_2_3_reg = 1'b0;
end
2'b10:
begin
tmp__demux_2_0_reg = 1'b0;
tmp__demux_2_1_reg = 1'b0;
tmp__demux_2_2_reg = Net_1415;
tmp__demux_2_3_reg = 1'b0;
end
2'b11:
begin
tmp__demux_2_0_reg = 1'b0;
tmp__demux_2_1_reg = 1'b0;
tmp__demux_2_2_reg = 1'b0;
tmp__demux_2_3_reg = Net_1415;
end
endcase
end
assign Net_1478 = tmp__demux_2_0_reg;
assign Net_1462 = tmp__demux_2_1_reg;
assign Net_1479 = tmp__demux_2_2_reg;
assign Net_1468 = tmp__demux_2_3_reg;
end
// -- De Mux end --
wire [2:0] tmpOE__RGB_LED_net;
wire [2:0] tmpFB_2__RGB_LED_net;
wire [2:0] tmpIO_2__RGB_LED_net;
wire [0:0] tmpINTERRUPT_0__RGB_LED_net;
electrical [0:0] tmpSIOVREF__RGB_LED_net;
cy_psoc3_pins_v1_10
#(.id("52f31aa9-2f0a-497d-9a1f-1424095e13e6"),
.drive_mode(9'b110_110_110),
.ibuf_enabled(3'b1_1_1),
.init_dr_st(3'b1_1_1),
.input_clk_en(0),
.input_sync(3'b1_1_1),
.input_sync_mode(3'b0_0_0),
.intr_mode(6'b00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(", , "),
.layout_mode("CONTIGUOUS"),
.oe_conn(3'b0_0_0),
.oe_reset(0),
.oe_sync(3'b0_0_0),
.output_clk_en(0),
.output_clock_mode(3'b0_0_0),
.output_conn(3'b1_1_1),
.output_mode(3'b0_0_0),
.output_reset(0),
.output_sync(3'b0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(",,"),
.pin_mode("OOO"),
.por_state(4),
.use_annotation(3'b0_0_0),
.sio_group_cnt(0),
.sio_hyst(3'b0_0_0),
.sio_ibuf(""),
.sio_info(6'b00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(3'b0_0_0),
.spanning(0),
.vtrip(6'b10_10_10),
.width(3))
RGB_LED
(.oe(tmpOE__RGB_LED_net),
.y({Net_1634, Net_1664, Net_1632}),
.fb({tmpFB_2__RGB_LED_net[2:0]}),
.io({tmpIO_2__RGB_LED_net[2:0]}),
.siovref(tmpSIOVREF__RGB_LED_net),
.interrupt({tmpINTERRUPT_0__RGB_LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RGB_LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{3'b111} : {3'b111};
assign Net_1632 = ~(Net_1568 | Net_1462 | Net_1461);
// -- De Mux start --
if (1)
begin : demux_1
reg tmp__demux_1_0_reg;
reg tmp__demux_1_1_reg;
reg tmp__demux_1_2_reg;
reg tmp__demux_1_3_reg;
always @(Net_1409 or Net_1410)
begin
case (Net_1410[1:0])
2'b00:
begin
tmp__demux_1_0_reg = Net_1409;
tmp__demux_1_1_reg = 1'b0;
tmp__demux_1_2_reg = 1'b0;
tmp__demux_1_3_reg = 1'b0;
end
2'b01:
begin
tmp__demux_1_0_reg = 1'b0;
tmp__demux_1_1_reg = Net_1409;
tmp__demux_1_2_reg = 1'b0;
tmp__demux_1_3_reg = 1'b0;
end
2'b10:
begin
tmp__demux_1_0_reg = 1'b0;
tmp__demux_1_1_reg = 1'b0;
tmp__demux_1_2_reg = Net_1409;
tmp__demux_1_3_reg = 1'b0;
end
2'b11:
begin
tmp__demux_1_0_reg = 1'b0;
tmp__demux_1_1_reg = 1'b0;
tmp__demux_1_2_reg = 1'b0;
tmp__demux_1_3_reg = Net_1409;
end
endcase
end
assign Net_1405 = tmp__demux_1_0_reg;
assign Net_1461 = tmp__demux_1_1_reg;
assign Net_1464 = tmp__demux_1_2_reg;
assign Net_1467 = tmp__demux_1_3_reg;
end
// -- De Mux end --
wire [0:0] tmpOE__Vbus_net;
wire [0:0] tmpFB_0__Vbus_net;
wire [0:0] tmpIO_0__Vbus_net;
electrical [0:0] tmpSIOVREF__Vbus_net;
cy_psoc3_pins_v1_10
#(.id("4c15b41e-e284-4978-99e7-5aaee19bd0ce"),
.drive_mode(3'b011),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b01),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
Vbus
(.oe(tmpOE__Vbus_net),
.y({1'b0}),
.fb({tmpFB_0__Vbus_net[0:0]}),
.io({tmpIO_0__Vbus_net[0:0]}),
.siovref(tmpSIOVREF__Vbus_net),
.interrupt({Net_1525}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Vbus_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
Vbus_IRQ
(.int_signal(Net_1525));
CyControlReg_v1_70 PWM0_CTRL (
.control_1(Net_1490),
.control_2(Net_1491),
.control_3(Net_1492),
.control_0(Net_1493),
.control_4(Net_1494),
.control_5(Net_1495),
.control_6(Net_1496),
.control_7(Net_1497),
.clock(1'b0),
.reset(1'b0),
.control_bus(Net_1410[1:0]));
defparam PWM0_CTRL.Bit0Mode = 0;
defparam PWM0_CTRL.Bit1Mode = 0;
defparam PWM0_CTRL.Bit2Mode = 0;
defparam PWM0_CTRL.Bit3Mode = 0;
defparam PWM0_CTRL.Bit4Mode = 0;
defparam PWM0_CTRL.Bit5Mode = 0;
defparam PWM0_CTRL.Bit6Mode = 0;
defparam PWM0_CTRL.Bit7Mode = 0;
defparam PWM0_CTRL.BitValue = 0;
defparam PWM0_CTRL.BusDisplay = 1;
defparam PWM0_CTRL.ExtrReset = 0;
defparam PWM0_CTRL.NumOutputs = 2;
wire [0:0] tmpOE__Sensor_In_net;
wire [0:0] tmpFB_0__Sensor_In_net;
wire [0:0] tmpIO_0__Sensor_In_net;
wire [0:0] tmpINTERRUPT_0__Sensor_In_net;
electrical [0:0] tmpSIOVREF__Sensor_In_net;
cy_psoc3_pins_v1_10
#(.id("05a9c8de-3ba2-4909-8250-95fdc61c0bf4"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Sensor_In
(.oe(tmpOE__Sensor_In_net),
.y({1'b0}),
.fb({tmpFB_0__Sensor_In_net[0:0]}),
.analog({Net_1602}),
.io({tmpIO_0__Sensor_In_net[0:0]}),
.siovref(tmpSIOVREF__Sensor_In_net),
.interrupt({tmpINTERRUPT_0__Sensor_In_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Sensor_In_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ADC_DelSig_v3_0_1 ADC (
.vplus(Net_1593),
.vminus(Net_558),
.soc(1'b1),
.eoc(Net_566),
.aclk(1'b0),
.nVref(Net_562),
.mi(1'b0));
wire [1:0] tmpOE__ModifyCollection_B_net;
wire [1:0] tmpFB_1__ModifyCollection_B_net;
wire [1:0] tmpIO_1__ModifyCollection_B_net;
electrical [0:0] tmpSIOVREF__ModifyCollection_B_net;
cy_psoc3_pins_v1_10
#(.id("7bd73714-fc02-4433-9733-e47f5d6532cc"),
.drive_mode(6'b011_011),
.ibuf_enabled(2'b1_1),
.init_dr_st(2'b0_0),
.input_clk_en(0),
.input_sync(2'b1_1),
.input_sync_mode(2'b0_0),
.intr_mode(4'b01_01),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(", "),
.layout_mode("CONTIGUOUS"),
.oe_conn(2'b0_0),
.oe_reset(0),
.oe_sync(2'b0_0),
.output_clk_en(0),
.output_clock_mode(2'b0_0),
.output_conn(2'b0_0),
.output_mode(2'b0_0),
.output_reset(0),
.output_sync(2'b0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(","),
.pin_mode("II"),
.por_state(4),
.use_annotation(2'b0_0),
.sio_group_cnt(0),
.sio_hyst(2'b0_0),
.sio_ibuf(""),
.sio_info(4'b00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(2'b0_0),
.spanning(0),
.vtrip(4'b00_00),
.width(2))
ModifyCollection_B
(.oe(tmpOE__ModifyCollection_B_net),
.y({2'b0}),
.fb({tmpFB_1__ModifyCollection_B_net[1:0]}),
.io({tmpIO_1__ModifyCollection_B_net[1:0]}),
.siovref(tmpSIOVREF__ModifyCollection_B_net),
.interrupt({Net_1524}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__ModifyCollection_B_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{2'b11} : {2'b11};
cy_isr_v1_0
#(.int_type(2'b10))
ModifyCollection_IRQ
(.int_signal(Net_1524));
USBFS_v2_60_2 USBUART (
.sof(Net_1347),
.vbusdet(1'b0));
assign Net_1664 = ~(Net_1565 | Net_1479 | Net_1464);
CyControlReg_v1_70 PWM1_CTRL (
.control_1(Net_1500),
.control_2(Net_1501),
.control_3(Net_1502),
.control_0(Net_1503),
.control_4(Net_1504),
.control_5(Net_1505),
.control_6(Net_1506),
.control_7(Net_1507),
.clock(1'b0),
.reset(1'b0),
.control_bus(Net_1460[1:0]));
defparam PWM1_CTRL.Bit0Mode = 0;
defparam PWM1_CTRL.Bit1Mode = 0;
defparam PWM1_CTRL.Bit2Mode = 0;
defparam PWM1_CTRL.Bit3Mode = 0;
defparam PWM1_CTRL.Bit4Mode = 0;
defparam PWM1_CTRL.Bit5Mode = 0;
defparam PWM1_CTRL.Bit6Mode = 0;
defparam PWM1_CTRL.Bit7Mode = 0;
defparam PWM1_CTRL.BitValue = 0;
defparam PWM1_CTRL.BusDisplay = 1;
defparam PWM1_CTRL.ExtrReset = 0;
defparam PWM1_CTRL.NumOutputs = 2;
assign Net_1308 = 1'h0;
PWM_v3_0_3 LED_PWM (
.reset(Net_1308),
.clock(Net_1309),
.tc(Net_1480),
.pwm1(Net_1409),
.pwm2(Net_1415),
.interrupt(Net_1481),
.capture(1'b0),
.kill(1'b1),
.enable(1'b1),
.trigger(1'b0),
.cmp_sel(1'b0),
.pwm(Net_1487),
.ph1(Net_1488),
.ph2(Net_1489));
defparam LED_PWM.Resolution = 8;
assign Net_1634 = ~(Net_1566 | Net_1468 | Net_1467);
cy_clock_v1_0
#(.id("48e889b6-c199-4b3a-bd89-d32bdd0d158d"),
.source_clock_id("315365C3-2E3E-4f04-84A2-BB564A173261"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(1))
PWM_CLK
(.clock_out(Net_1309));
wire [0:0] tmpOE__Batt_Monitor_net;
wire [0:0] tmpFB_0__Batt_Monitor_net;
wire [0:0] tmpIO_0__Batt_Monitor_net;
wire [0:0] tmpINTERRUPT_0__Batt_Monitor_net;
electrical [0:0] tmpSIOVREF__Batt_Monitor_net;
cy_psoc3_pins_v1_10
#(.id("0895e0c5-22fd-4e04-a47c-17021ab62788"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
Batt_Monitor
(.oe(tmpOE__Batt_Monitor_net),
.y({1'b0}),
.fb({tmpFB_0__Batt_Monitor_net[0:0]}),
.analog({Net_1603}),
.io({tmpIO_0__Batt_Monitor_net[0:0]}),
.siovref(tmpSIOVREF__Batt_Monitor_net),
.interrupt({tmpINTERRUPT_0__Batt_Monitor_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Batt_Monitor_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
CyControlReg_v1_70 SOLID_LED_CTRL (
.control_1(Net_1565),
.control_2(Net_1566),
.control_3(Net_1567),
.control_0(Net_1568),
.control_4(Net_1569),
.control_5(Net_1570),
.control_6(Net_1571),
.control_7(Net_1572),
.clock(1'b0),
.reset(1'b0));
defparam SOLID_LED_CTRL.Bit0Mode = 0;
defparam SOLID_LED_CTRL.Bit1Mode = 0;
defparam SOLID_LED_CTRL.Bit2Mode = 0;
defparam SOLID_LED_CTRL.Bit3Mode = 0;
defparam SOLID_LED_CTRL.Bit4Mode = 0;
defparam SOLID_LED_CTRL.Bit5Mode = 0;
defparam SOLID_LED_CTRL.Bit6Mode = 0;
defparam SOLID_LED_CTRL.Bit7Mode = 0;
defparam SOLID_LED_CTRL.BitValue = 0;
defparam SOLID_LED_CTRL.BusDisplay = 0;
defparam SOLID_LED_CTRL.ExtrReset = 0;
defparam SOLID_LED_CTRL.NumOutputs = 3;
// -- AMux ADC_MUX start -- ***
// -- Mux A --
cy_psoc3_amux_v1_0 ADC_MUX(
.muxin({
Net_1603,
Net_1602
}),
.vout(Net_1593)
);
defparam ADC_MUX.muxin_width = 2;
defparam ADC_MUX.init_mux_sel = 2'h0;
defparam ADC_MUX.one_active = 1;
defparam ADC_MUX.connect_mode = 0;
// -- AMux ADC_MUX end --
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 7SERIES PHASER IN
// /__/ /\ Filename : PHASER_IN.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 22APR2010 Initial UNI/UNP/SIM version from yaml
// 03JUN2010 yaml update
// 12JUL2010 enable secureip
// 12AUG2010 yaml, rtl update
// 24SEP2010 yaml, rtl update
// 29SEP2010 add width checks
// 13OCT2010 yaml, rtl update
// 26OCT2010 delay yaml, rtl update
// 02NOV2010 yaml update
// 05NOV2010 secureip parameter name update
// 01DEC2010 yaml update, REFCLK_PERIOD max
// 09DEC2010 586079 yaml update, tie off defaults
// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 02FEB2011 592485 yaml, rtl update
// 19MAY2011 611139 remove period, setup/hold checks on FREQ/MEM/PHASEREFCLK, SYNCIN
// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter
// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed
// 15AUG2011 621681 yaml update, remove SIM_SPEEDUP make default
// 01DEC2011 635710 yaml update SEL_CLK_OFFSET = 0 per model alert
// 01MAR2012 637179 (and others) RTL update, TEST_OPT split apart
// 22MAY2012 660507 DQS_AUTO_RECAL default value change
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_IN #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer CLKOUT_DIV = 4,
parameter DQS_BIAS_MODE = "FALSE",
parameter EN_ISERDES_RST = "FALSE",
parameter integer FINE_DELAY = 0,
parameter FREQ_REF_DIV = "NONE",
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real MEMREFCLK_PERIOD = 0.000,
parameter OUTPUT_CLK_SRC = "PHASE_REF",
parameter real PHASEREFCLK_PERIOD = 0.000,
parameter real REFCLK_PERIOD = 0.000,
parameter integer SEL_CLK_OFFSET = 5,
parameter SYNC_IN_DIV_RST = "FALSE"
) (
output [5:0] COUNTERREADVAL,
output FINEOVERFLOW,
output ICLK,
output ICLKDIV,
output ISERDESRST,
output RCLK,
input COUNTERLOADEN,
input [5:0] COUNTERLOADVAL,
input COUNTERREADEN,
input DIVIDERST,
input EDGEADV,
input FINEENABLE,
input FINEINC,
input FREQREFCLK,
input MEMREFCLK,
input PHASEREFCLK,
input [1:0] RANKSEL,
input RST,
input SYNCIN,
input SYSCLK
);
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
`else
localparam in_delay = 1;
localparam out_delay = 1;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 1;
`endif
localparam MODULE_NAME = "PHASER_IN";
reg MEMREFCLK_PERIOD_BINARY;
reg PHASEREFCLK_PERIOD_BINARY;
reg REFCLK_PERIOD_BINARY;
reg [0:0] BURST_MODE_BINARY;
reg [0:0] CALIB_EDGE_IN_INV_BINARY;
reg [0:0] CTL_MODE_BINARY;
reg [0:0] DQS_AUTO_RECAL_BINARY;
reg [0:0] DQS_BIAS_MODE_BINARY;
reg [0:0] EN_ISERDES_RST_BINARY;
reg [0:0] EN_TEST_RING_BINARY;
reg [0:0] GATE_SET_CLK_MUX_BINARY;
reg [0:0] HALF_CYCLE_ADJ_BINARY;
reg [0:0] ICLK_TO_RCLK_BYPASS_BINARY;
reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
reg [0:0] PHASER_IN_EN_BINARY;
reg [0:0] REG_OPT_1_BINARY;
reg [0:0] REG_OPT_2_BINARY;
reg [0:0] REG_OPT_4_BINARY;
reg [0:0] RST_SEL_BINARY;
reg [0:0] SEL_OUT_BINARY;
reg [0:0] SYNC_IN_DIV_RST_BINARY;
reg [0:0] TEST_BP_BINARY;
reg [0:0] UPDATE_NONACTIVE_BINARY;
reg [0:0] WR_CYCLES_BINARY;
reg [1:0] FREQ_REF_DIV_BINARY;
reg [1:0] RD_ADDR_INIT_BINARY;
reg [2:0] DQS_FIND_PATTERN_BINARY;
reg [2:0] PD_REVERSE_BINARY;
reg [2:0] SEL_CLK_OFFSET_BINARY;
reg [2:0] STG1_PD_UPDATE_BINARY;
reg [3:0] CLKOUT_DIV_BINARY;
reg [3:0] CLKOUT_DIV_POS_BINARY;
reg [3:0] CLKOUT_DIV_ST_BINARY;
reg [3:0] OUTPUT_CLK_SRC_BINARY;
reg [5:0] FINE_DELAY_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
BURST_MODE_BINARY <= 1'b0;
case (CLKOUT_DIV)
4 : CLKOUT_DIV_BINARY <= 4'b0010;
2 : CLKOUT_DIV_BINARY <= 4'b0000;
3 : CLKOUT_DIV_BINARY <= 4'b0001;
5 : CLKOUT_DIV_BINARY <= 4'b0011;
6 : CLKOUT_DIV_BINARY <= 4'b0100;
7 : CLKOUT_DIV_BINARY <= 4'b0101;
8 : CLKOUT_DIV_BINARY <= 4'b0110;
9 : CLKOUT_DIV_BINARY <= 4'b0111;
10 : CLKOUT_DIV_BINARY <= 4'b1000;
11 : CLKOUT_DIV_BINARY <= 4'b1001;
12 : CLKOUT_DIV_BINARY <= 4'b1010;
13 : CLKOUT_DIV_BINARY <= 4'b1011;
14 : CLKOUT_DIV_BINARY <= 4'b1100;
15 : CLKOUT_DIV_BINARY <= 4'b1101;
16 : CLKOUT_DIV_BINARY <= 4'b1110;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV);
#1 $finish;
end
endcase
CTL_MODE_BINARY <= 1'b0; // model alert
case (DQS_BIAS_MODE)
"FALSE" : DQS_BIAS_MODE_BINARY <= 1'b0;
"TRUE" : DQS_BIAS_MODE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DQS_BIAS_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_MODE);
#1 $finish;
end
endcase
case (EN_ISERDES_RST)
"FALSE" : EN_ISERDES_RST_BINARY <= 1'b0;
"TRUE" : EN_ISERDES_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute EN_ISERDES_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ISERDES_RST);
#1 $finish;
end
endcase
EN_TEST_RING_BINARY <= 1'b0;
case (FREQ_REF_DIV)
"NONE" : FREQ_REF_DIV_BINARY <= 2'b00;
"DIV2" : FREQ_REF_DIV_BINARY <= 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute FREQ_REF_DIV on %s instance %m is set to %s. Legal values for this attribute are NONE or DIV2.", MODULE_NAME, FREQ_REF_DIV);
#1 $finish;
end
endcase
HALF_CYCLE_ADJ_BINARY <= 1'b0;
ICLK_TO_RCLK_BYPASS_BINARY <= 1'b1;
case (OUTPUT_CLK_SRC)
"PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0000;
"DELAYED_MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0101;
"DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0011;
"DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0001;
"FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b1000;
"MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0010;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_MEM_REF, DELAYED_PHASE_REF, DELAYED_REF, FREQ_REF or MEM_REF.", MODULE_NAME, OUTPUT_CLK_SRC);
#1 $finish;
end
endcase
PD_REVERSE_BINARY <= 3'b011;
PHASER_IN_EN_BINARY <= 1'b1;
STG1_PD_UPDATE_BINARY <= 3'b000;
case (SYNC_IN_DIV_RST)
"FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0;
"TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST);
#1 $finish;
end
endcase
UPDATE_NONACTIVE_BINARY <= 1'b0;
WR_CYCLES_BINARY <= 1'b0;
CALIB_EDGE_IN_INV_BINARY <= 1'b0;
case (CLKOUT_DIV)
2 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
3 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
4 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
5 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
6 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
7 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
8 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
9 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
10 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
11 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
12 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
13 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
14 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
15 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
16 : CLKOUT_DIV_POS_BINARY <= 4'b1000;
default: CLKOUT_DIV_POS_BINARY <= 4'b0010;
endcase
CLKOUT_DIV_ST_BINARY <= 4'b0000;
DQS_AUTO_RECAL_BINARY <= 1'b1;
DQS_FIND_PATTERN_BINARY <= 3'b001;
if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63))
FINE_DELAY_BINARY <= FINE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY);
#1 $finish;
end
GATE_SET_CLK_MUX_BINARY <= 1'b0;
if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000))
MEMREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, MEMREFCLK_PERIOD);
#1 $finish;
end
if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000))
PHASEREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD);
#1 $finish;
end
RD_ADDR_INIT_BINARY <= 2'b00;
if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500))
REFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD);
#1 $finish;
end
REG_OPT_1_BINARY <= 1'b0;
REG_OPT_2_BINARY <= 1'b0;
REG_OPT_4_BINARY <= 1'b0;
RST_SEL_BINARY <= 1'b0;
if ((SEL_CLK_OFFSET >= 0) && (SEL_CLK_OFFSET <= 7))
SEL_CLK_OFFSET_BINARY <= 0; // Model Alert
else begin
$display("Attribute Syntax Error : The Attribute SEL_CLK_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SEL_CLK_OFFSET);
#1 $finish;
end
SEL_OUT_BINARY <= 1'b0;
TEST_BP_BINARY <= 1'b0;
end
wire [3:0] delay_TESTOUT;
wire [5:0] delay_COUNTERREADVAL;
wire [8:0] delay_STG1REGR;
wire delay_DQSFOUND;
wire delay_DQSOUTOFRANGE;
wire delay_FINEOVERFLOW;
wire delay_ICLK;
wire delay_ICLKDIV;
wire delay_ISERDESRST;
wire delay_PHASELOCKED;
wire delay_RCLK;
wire delay_SCANOUT;
wire delay_STG1OVERFLOW;
wire delay_WRENABLE;
wire [13:0] delay_TESTIN = 14'h3fff;
wire [1:0] delay_ENCALIB = 2'b11;
wire [1:0] delay_ENCALIBPHY = 2'b0;
wire [1:0] delay_RANKSEL;
wire [1:0] delay_RANKSELPHY = 2'b0;
wire [5:0] delay_COUNTERLOADVAL;
wire [8:0] delay_STG1REGL = 9'h1ff;
wire delay_BURSTPENDING = 1'b1;
wire delay_BURSTPENDINGPHY = 1'b0;
wire delay_COUNTERLOADEN;
wire delay_COUNTERREADEN;
wire delay_DIVIDERST;
wire delay_EDGEADV;
wire delay_ENSTG1 = 1'b1;
wire delay_ENSTG1ADJUSTB = 1'b1;
wire delay_FINEENABLE;
wire delay_FINEINC;
wire delay_FREQREFCLK;
wire delay_MEMREFCLK;
wire delay_PHASEREFCLK;
wire delay_RST;
wire delay_RSTDQSFIND = 1'b1;
wire delay_SCANCLK = 1'b1;
wire delay_SCANENB = 1'b1;
wire delay_SCANIN = 1'b1;
wire delay_SCANMODEB = 1'b1;
wire delay_SELCALORSTG1 = 1'b1;
wire delay_STG1INCDEC = 1'b1;
wire delay_STG1LOAD = 1'b1;
wire delay_STG1READ = 1'b1;
wire delay_SYNCIN;
wire delay_SYSCLK;
wire delay_GSR;
assign #(OUTCLK_DELAY) ICLK = delay_ICLK;
assign #(OUTCLK_DELAY) ICLKDIV = delay_ICLKDIV;
assign #(OUTCLK_DELAY) RCLK = delay_RCLK;
assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL;
assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW;
assign #(out_delay) ISERDESRST = delay_ISERDESRST;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK;
assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN;
assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL;
assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN;
assign #(in_delay) delay_DIVIDERST = DIVIDERST;
assign #(in_delay) delay_EDGEADV = EDGEADV;
assign #(in_delay) delay_FINEENABLE = FINEENABLE;
assign #(in_delay) delay_FINEINC = FINEINC;
`endif
assign #(in_delay) delay_FREQREFCLK = FREQREFCLK;
assign #(in_delay) delay_MEMREFCLK = MEMREFCLK;
assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK;
`ifndef XIL_TIMING
assign #(in_delay) delay_RANKSEL = RANKSEL;
`endif
assign #(in_delay) delay_RST = RST;
assign #(in_delay) delay_SYNCIN = SYNCIN;
assign delay_GSR = GSR;
SIP_PHASER_IN # (
.REFCLK_PERIOD (REFCLK_PERIOD)
) PHASER_IN_INST (
.BURST_MODE (BURST_MODE_BINARY),
.CALIB_EDGE_IN_INV (CALIB_EDGE_IN_INV_BINARY),
.CLKOUT_DIV (CLKOUT_DIV_BINARY),
.CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY),
.CTL_MODE (CTL_MODE_BINARY),
.DQS_AUTO_RECAL (DQS_AUTO_RECAL_BINARY),
.DQS_BIAS_MODE (DQS_BIAS_MODE_BINARY),
.DQS_FIND_PATTERN (DQS_FIND_PATTERN_BINARY),
.EN_ISERDES_RST (EN_ISERDES_RST_BINARY),
.EN_TEST_RING (EN_TEST_RING_BINARY),
.FINE_DELAY (FINE_DELAY_BINARY),
.FREQ_REF_DIV (FREQ_REF_DIV_BINARY),
.GATE_SET_CLK_MUX (GATE_SET_CLK_MUX_BINARY),
.HALF_CYCLE_ADJ (HALF_CYCLE_ADJ_BINARY),
.ICLK_TO_RCLK_BYPASS (ICLK_TO_RCLK_BYPASS_BINARY),
.OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY),
.PD_REVERSE (PD_REVERSE_BINARY),
.PHASER_IN_EN (PHASER_IN_EN_BINARY),
.RD_ADDR_INIT (RD_ADDR_INIT_BINARY),
.REG_OPT_1 (REG_OPT_1_BINARY),
.REG_OPT_2 (REG_OPT_2_BINARY),
.REG_OPT_4 (REG_OPT_4_BINARY),
.RST_SEL (RST_SEL_BINARY),
.SEL_CLK_OFFSET (SEL_CLK_OFFSET_BINARY),
.SEL_OUT (SEL_OUT_BINARY),
.STG1_PD_UPDATE (STG1_PD_UPDATE_BINARY),
.SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY),
.TEST_BP (TEST_BP_BINARY),
.UPDATE_NONACTIVE (UPDATE_NONACTIVE_BINARY),
.WR_CYCLES (WR_CYCLES_BINARY),
.CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY),
.COUNTERREADVAL (delay_COUNTERREADVAL),
.DQSFOUND (delay_DQSFOUND),
.DQSOUTOFRANGE (delay_DQSOUTOFRANGE),
.FINEOVERFLOW (delay_FINEOVERFLOW),
.ICLK (delay_ICLK),
.ICLKDIV (delay_ICLKDIV),
.ISERDESRST (delay_ISERDESRST),
.PHASELOCKED (delay_PHASELOCKED),
.RCLK (delay_RCLK),
.SCANOUT (delay_SCANOUT),
.STG1OVERFLOW (delay_STG1OVERFLOW),
.STG1REGR (delay_STG1REGR),
.TESTOUT (delay_TESTOUT),
.WRENABLE (delay_WRENABLE),
.BURSTPENDING (delay_BURSTPENDING),
.BURSTPENDINGPHY (delay_BURSTPENDINGPHY),
.COUNTERLOADEN (delay_COUNTERLOADEN),
.COUNTERLOADVAL (delay_COUNTERLOADVAL),
.COUNTERREADEN (delay_COUNTERREADEN),
.DIVIDERST (delay_DIVIDERST),
.EDGEADV (delay_EDGEADV),
.ENCALIB (delay_ENCALIB),
.ENCALIBPHY (delay_ENCALIBPHY),
.ENSTG1 (delay_ENSTG1),
.ENSTG1ADJUSTB (delay_ENSTG1ADJUSTB),
.FINEENABLE (delay_FINEENABLE),
.FINEINC (delay_FINEINC),
.FREQREFCLK (delay_FREQREFCLK),
.MEMREFCLK (delay_MEMREFCLK),
.PHASEREFCLK (delay_PHASEREFCLK),
.RANKSEL (delay_RANKSEL),
.RANKSELPHY (delay_RANKSELPHY),
.RST (delay_RST ^ IS_RST_INVERTED_REG),
.RSTDQSFIND (delay_RSTDQSFIND),
.SCANCLK (delay_SCANCLK),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.SCANMODEB (delay_SCANMODEB),
.SELCALORSTG1 (delay_SELCALORSTG1),
.STG1INCDEC (delay_STG1INCDEC),
.STG1LOAD (delay_STG1LOAD),
.STG1READ (delay_STG1READ),
.STG1REGL (delay_STG1REGL),
.SYNCIN (delay_SYNCIN),
.SYSCLK (delay_SYSCLK),
.TESTIN (delay_TESTIN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (posedge SYSCLK, 0:0:0, notifier);
$setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, negedge DIVIDERST, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_DIVIDERST);
$setuphold (posedge SYSCLK, negedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV);
$setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, negedge RANKSEL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RANKSEL);
$setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, posedge DIVIDERST, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_DIVIDERST);
$setuphold (posedge SYSCLK, posedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV);
$setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, posedge RANKSEL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RANKSEL);
$width (negedge FREQREFCLK, 0:0:0, 0, notifier);
$width (negedge MEMREFCLK, 0:0:0, 0, notifier);
$width (negedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (negedge SYNCIN, 0:0:0, 0, notifier);
$width (negedge SYSCLK, 0:0:0, 0, notifier);
$width (posedge FREQREFCLK, 0:0:0, 0, notifier);
$width (posedge MEMREFCLK, 0:0:0, 0, notifier);
$width (posedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge SYNCIN, 0:0:0, 0, notifier);
$width (posedge SYSCLK, 0:0:0, 0, notifier);
( FREQREFCLK *> ICLK) = (10:10:10, 10:10:10);
( FREQREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( FREQREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( FREQREFCLK *> RCLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( MEMREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( MEMREFCLK *> RCLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( PHASEREFCLK *> RCLK) = (10:10:10, 10:10:10);
( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10);
( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_IN
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_hdll__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_hdll__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_axi_stream (
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input m_axis_ready,
output m_axis_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output fifo_ready,
input fifo_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [3:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_S_AXIS_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
assign sync_id_ret = sync_id;
wire data_enabled;
wire [C_ID_WIDTH-1:0] data_id;
wire _fifo_ready;
// We are not allowed to just de-assert valid, but if the streaming target does
// not accept any samples anymore we'd lock up the DMA core. So retain the last
// beat when disabled until it is accepted. But if in the meantime the DMA core
// is re-enabled and new data becomes available overwrite the old.
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.m_axi_ready(m_axis_ready),
.m_axi_valid(m_axis_valid),
.m_axi_data(m_axis_data),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data)
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
assign fifo_ready = _fifo_ready | ~enabled;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IP ethernet frame transmitter (IP frame in, Ethernet frame out)
*/
module ip_eth_tx
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [7:0] m_eth_payload_axis_tdata,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_payload_early_termination
);
/*
IP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
payload length octets
This module receives an IP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the Ethernet headers, and transmits the complete Ethernet payload on an AXI
interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_PAYLOAD = 3'd2,
STATE_WRITE_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_last_word;
reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [15:0] hdr_sum_reg = 16'd0, hdr_sum_next;
reg [7:0] last_word_data_reg = 8'd0;
reg [5:0] ip_dscp_reg = 6'd0;
reg [1:0] ip_ecn_reg = 2'd0;
reg [15:0] ip_length_reg = 16'd0;
reg [15:0] ip_identification_reg = 16'd0;
reg [2:0] ip_flags_reg = 3'd0;
reg [12:0] ip_fragment_offset_reg = 13'd0;
reg [7:0] ip_ttl_reg = 8'd0;
reg [7:0] ip_protocol_reg = 8'd0;
reg [31:0] ip_source_ip_reg = 32'd0;
reg [31:0] ip_dest_ip_reg = 32'd0;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg busy_reg = 1'b0;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [7:0] m_eth_payload_axis_tdata_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
function [15:0] add1c16b;
input [15:0] a, b;
reg [16:0] t;
begin
t = a+b;
add1c16b = t[15:0] + t[16];
end
endfunction
always @* begin
state_next = STATE_IDLE;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
store_ip_hdr = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
hdr_sum_next = hdr_sum_reg;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
error_payload_early_termination_next = 1'b0;
m_eth_payload_axis_tdata_int = 8'd0;
m_eth_payload_axis_tvalid_int = 1'b0;
m_eth_payload_axis_tlast_int = 1'b0;
m_eth_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
hdr_ptr_next = 6'd0;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
store_ip_hdr = 1'b1;
s_ip_hdr_ready_next = 1'b0;
m_eth_hdr_valid_next = 1'b1;
if (m_eth_payload_axis_tready_int_reg) begin
m_eth_payload_axis_tvalid_int = 1'b1;
m_eth_payload_axis_tdata_int = {4'd4, 4'd5}; // ip_version, ip_ihl
hdr_ptr_next = 6'd1;
end
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// write header
word_count_next = ip_length_reg - 5*4;
if (m_eth_payload_axis_tready_int_reg) begin
hdr_ptr_next = hdr_ptr_reg + 6'd1;
m_eth_payload_axis_tvalid_int = 1;
state_next = STATE_WRITE_HEADER;
case (hdr_ptr_reg)
6'h00: begin
m_eth_payload_axis_tdata_int = {4'd4, 4'd5}; // ip_version, ip_ihl
end
6'h01: begin
m_eth_payload_axis_tdata_int = {ip_dscp_reg, ip_ecn_reg};
hdr_sum_next = {4'd4, 4'd5, ip_dscp_reg, ip_ecn_reg};
end
6'h02: begin
m_eth_payload_axis_tdata_int = ip_length_reg[15: 8];
hdr_sum_next = add1c16b(hdr_sum_reg, ip_length_reg);
end
6'h03: begin
m_eth_payload_axis_tdata_int = ip_length_reg[ 7: 0];
hdr_sum_next = add1c16b(hdr_sum_reg, ip_identification_reg);
end
6'h04: begin
m_eth_payload_axis_tdata_int = ip_identification_reg[15: 8];
hdr_sum_next = add1c16b(hdr_sum_reg, {ip_flags_reg, ip_fragment_offset_reg});
end
6'h05: begin
m_eth_payload_axis_tdata_int = ip_identification_reg[ 7: 0];
hdr_sum_next = add1c16b(hdr_sum_reg, {ip_ttl_reg, ip_protocol_reg});
end
6'h06: begin
m_eth_payload_axis_tdata_int = {ip_flags_reg, ip_fragment_offset_reg[12:8]};
hdr_sum_next = add1c16b(hdr_sum_reg, ip_source_ip_reg[31:16]);
end
6'h07: begin
m_eth_payload_axis_tdata_int = ip_fragment_offset_reg[ 7: 0];
hdr_sum_next = add1c16b(hdr_sum_reg, ip_source_ip_reg[15:0]);
end
6'h08: begin
m_eth_payload_axis_tdata_int = ip_ttl_reg;
hdr_sum_next = add1c16b(hdr_sum_reg, ip_dest_ip_reg[31:16]);
end
6'h09: begin
m_eth_payload_axis_tdata_int = ip_protocol_reg;
hdr_sum_next = add1c16b(hdr_sum_reg, ip_dest_ip_reg[15:0]);
end
6'h0A: m_eth_payload_axis_tdata_int = ~hdr_sum_reg[15: 8];
6'h0B: m_eth_payload_axis_tdata_int = ~hdr_sum_reg[ 7: 0];
6'h0C: m_eth_payload_axis_tdata_int = ip_source_ip_reg[31:24];
6'h0D: m_eth_payload_axis_tdata_int = ip_source_ip_reg[23:16];
6'h0E: m_eth_payload_axis_tdata_int = ip_source_ip_reg[15: 8];
6'h0F: m_eth_payload_axis_tdata_int = ip_source_ip_reg[ 7: 0];
6'h10: m_eth_payload_axis_tdata_int = ip_dest_ip_reg[31:24];
6'h11: m_eth_payload_axis_tdata_int = ip_dest_ip_reg[23:16];
6'h12: m_eth_payload_axis_tdata_int = ip_dest_ip_reg[15: 8];
6'h13: begin
m_eth_payload_axis_tdata_int = ip_dest_ip_reg[ 7: 0];
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_PAYLOAD: begin
// write payload
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early;
m_eth_payload_axis_tdata_int = s_ip_payload_axis_tdata;
m_eth_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 6'd1;
m_eth_payload_axis_tvalid_int = 1'b1;
if (s_ip_payload_axis_tlast) begin
if (word_count_reg != 16'd1) begin
// end of frame, but length does not match
m_eth_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
if (word_count_reg == 16'd1) begin
store_last_word = 1'b1;
m_eth_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early;
m_eth_payload_axis_tdata_int = last_word_data_reg;
m_eth_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
m_eth_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = 1'b1;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
error_payload_early_termination_reg <= error_payload_early_termination_next;
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
hdr_sum_reg <= hdr_sum_next;
// datapath
if (store_ip_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
ip_dscp_reg <= s_ip_dscp;
ip_ecn_reg <= s_ip_ecn;
ip_length_reg <= s_ip_length;
ip_identification_reg <= s_ip_identification;
ip_flags_reg <= s_ip_flags;
ip_fragment_offset_reg <= s_ip_fragment_offset;
ip_ttl_reg <= s_ip_ttl;
ip_protocol_reg <= s_ip_protocol;
ip_source_ip_reg <= s_ip_source_ip;
ip_dest_ip_reg <= s_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= m_eth_payload_axis_tdata_int;
end
end
// output datapath logic
reg [7:0] m_eth_payload_axis_tdata_reg = 8'd0;
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_eth_payload_axis_tdata_reg = 8'd0;
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
`resetall
|
module tacho_fpga(quadA, quadB, mosi, miso, sck, cs, dir, step);
parameter COUNT_BITS = 32;
input quadA, quadB;
output miso;
input mosi, sck, cs;
output dir, step;
wire clk;
OSCH #(
.NOM_FREQ("53.2")
) internal_oscillator_inst (
.STDBY(1'b0),
.OSC(clk)
);
reg [COUNT_BITS - 1: 0] step_period;
reg dir;
wire [COUNT_BITS * 2 - 1: 0] rx_data;
wire [COUNT_BITS - 1:0] encoder_position;
wire [COUNT_BITS - 1: 0] stepper_position;
wire [COUNT_BITS * 2 - 1: 0] tx_data;
assign tx_data[COUNT_BITS * 2 - 1:COUNT_BITS] = encoder_position;
assign tx_data[COUNT_BITS - 1:0] = stepper_position;
quad_counter #(COUNT_BITS) counter(clk, quadA, quadB, encoder_position);
step_pulse_generator #(COUNT_BITS) step_gen(clk, step_period, stepper_position, dir, step);
spi_slave #(COUNT_BITS * 2) spi(clk, mosi, miso, sck, cs, tx_data, rx_data, rx_ready);
// when received from master
always @(posedge rx_ready)
begin
// pick out stepper period part of the received data
step_period = rx_data[COUNT_BITS - 1:0];
dir = rx_data[COUNT_BITS];
end
endmodule
|
/*
* Asynchronous read 1r1w content addressable memory module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
* - Read searches the array for any data with r_tag_i
* - Write allocates a new entry, replacing an existing entry with replacement
* scheme repl_scheme_p
* - Write with w_nuke_i flag invalidates the cam
* - Allocation happens in parallel with read, so it is possible in an LRU
* scheme for the currently-being-read item to be overwritten
* - There are no concerns about simultaneous reading and writing
* - It is generally discouraged to have multiple identical tags in the array,
* i.e. you should read the array to see if anything is there before
* writing; but if there are, then the data returned on read is the OR
* of the data. If you find that functionality useful, let us know =)
*/
`include "bsg_defines.v"
module bsg_cam_1r1w
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
// The replacement scheme for the CAM
, parameter repl_scheme_p = "lru"
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
, input w_v_i
// When w_v_i & w_nuke_i, the whole cam array is invalidated
, input w_nuke_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
localparam safe_els_lp = `BSG_MAX(els_p,1);
// The tag storage for the CAM
logic [safe_els_lp-1:0] tag_r_match_lo;
logic [safe_els_lp-1:0] tag_empty_lo;
logic [safe_els_lp-1:0] repl_way_lo;
wire [safe_els_lp-1:0] tag_w_v_li = repl_way_lo | {safe_els_lp{w_nuke_i}};
bsg_cam_1r1w_tag_array
#(.width_p(tag_width_p)
,.els_p(safe_els_lp)
)
cam_tag_array
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(tag_w_v_li)
,.w_set_not_clear_i(w_v_i & ~w_nuke_i)
,.w_tag_i(w_tag_i)
,.w_empty_o(tag_empty_lo)
,.r_v_i(r_v_i)
,.r_tag_i(r_tag_i)
,.r_match_o(tag_r_match_lo)
);
// The replacement scheme for the CAM
bsg_cam_1r1w_replacement
#(.els_p(safe_els_lp)
,.scheme_p(repl_scheme_p)
)
replacement
(.clk_i(clk_i)
,.reset_i(reset_i)
,.read_v_i(tag_r_match_lo)
,.alloc_v_i(w_v_i)
,.alloc_empty_i(tag_empty_lo)
,.alloc_v_o(repl_way_lo)
);
// The data storage for the CAM
wire [safe_els_lp-1:0] mem_w_v_li = repl_way_lo;
bsg_mem_1r1w_one_hot
#(.width_p(data_width_p)
,.els_p(safe_els_lp)
)
one_hot_mem
(.w_clk_i(clk_i)
,.w_reset_i(reset_i)
,.w_v_i(mem_w_v_li)
,.w_data_i(w_data_i)
,.r_v_i(tag_r_match_lo)
,.r_data_o(r_data_o)
);
assign r_v_o = |tag_r_match_lo;
endmodule
`BSG_ABSTRACT_MODULE(bsg_cam_1r1w)
|
// #####################################################################################
// # Copyright (C) 1991-2008 Altera Corporation
// # Any megafunction design, and related netlist (encrypted or decrypted),
// # support information, device programming or simulation file, and any other
// # associated documentation or information provided by Altera or a partner
// # under Altera's Megafunction Partnership Program may be used only
// # to program PLD devices (but not masked PLD devices) from Altera. Any
// # other use of such megafunction design, netlist, support information,
// # device programming or simulation file, or any other related documentation
// # or information is prohibited for any other purpose, including, but not
// # limited to modification, reverse engineering, de-compiling, or use with
// # any other silicon devices, unless such use is explicitly licensed under
// # a separate agreement with Altera or a megafunction partner. Title to the
// # intellectual property, including patents, copyrights, trademarks, trade
// # secrets, or maskworks, embodied in any such megafunction design, netlist,
// # support information, device programming or simulation file, or any other
// # related documentation or information provided by Altera or a megafunction
// # partner, remains with Altera, the megafunction partner, or their respective
// # licensors. No other licenses, including any licenses needed under any third
// # party's intellectual property, are provided herein.
// #####################################################################################
// #####################################################################################
// # Loopback module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Tue Mar 5 15:23:02 2013 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module tse_mac2_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__FA_FUNCTIONAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_FUNCTIONAL_PP_V |
// Copyright (C) 2017-2020 The Project X-Ray Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC
`default_nettype none
`timescale 1ns / 1ps
`include "../src/message_formatter.v"
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 150)
$finish;
// ============================================================================
wire i_stb = (cycle_cnt == 10);
wire [32*2-1:0] i_dat = 64'h01234567_ABCD4321;
wire o_stb;
wire [7:0] o_dat;
message_formatter #
(
.WIDTH (32),
.COUNT (2),
.TX_INTERVAL (4)
)
dut
(
.CLK (CLK),
.RST (RST),
.I_STB (i_stb),
.I_DAT (i_dat),
.O_STB (o_stb),
.O_DAT (o_dat)
);
always @(posedge CLK)
if (o_stb)
$display("%c", o_dat);
endmodule
|
//dispatch: read p_rs, p_rt, write new p_rd and reset this valid bit, read p_old, use p_rs, p_rt, p_rd_old to index valid array getting valid bit
//complete: set valid bit of the completed physical register number
//recovery: inedxed by recover_rd, if RegDest_ROB = 1, write the p_rd_flush to that entry, and restore the valid bit
module map_table(
output [5:0] p_rs, p_rt,
output p_rs_v, p_rt_v,
output [5:0] PR_old_rd,
input clk, rst,
input hazard_stall, //from hazard detection logic
//from dispatch stage
input isDispatch,
input [4:0] l_rs, l_rt, l_rd,
input RegDest,
input [5:0] p_rd_new,
//from recovery
input [4:0] recover_rd,
input [5:0] p_rd_flush,
input recover,
input RegDest_ROB,
//from complete stage
input [5:0] p_rd_compl,
input complete,
input RegDest_compl
);
reg [5:0] mt [0:31];
reg [63:0] PR_valid; //logically separate with map table
/////////////////////////////////writing/reading map table////////////////////////////
wire write_new_rd;
integer i;
assign write_new_rd = isDispatch && RegDest && !hazard_stall && !recover;
always @(posedge clk or negedge rst) begin
if (!rst) begin //initial begin
for (i = 0; i < 32; i = i + 1) begin
mt[i] <= i;
end
end
else if (write_new_rd)
mt[l_rd] <= p_rd_new;
else if (RegDest_ROB && recover)
mt[recover_rd] <= p_rd_flush;
end
assign p_rs = mt[l_rs];
assign p_rt = mt[l_rt];
assign PR_old_rd = mt[l_rd];
/////////////////////////////valid array/////////////////////////////////
always @(posedge clk or negedge rst) begin
if (!rst) begin
PR_valid <= 64'hFFFFFFFFFFFFFFFF;
end
else begin
if (write_new_rd)
PR_valid[p_rd_new] <= 1'b0;
if (complete && RegDest_compl) //it should be ok during recovery because if complete is 1, the valid will be set to 1 several times, finally it will
PR_valid[p_rd_compl] <= 1'b1; //be 1
end
end
assign p_rs_v = PR_valid[p_rs];
assign p_rt_v = PR_valid[p_rt];
endmodule
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_bidir_ramif_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "FALSE" // First word fall-through, not sure it can be disabled for this
) (
input wire a_clk,
input wire a_rst_n,
input wire a_winc,
input wire [DSIZE-1:0] a_wdata,
input wire a_rinc,
output wire [DSIZE-1:0] a_rdata,
output wire a_full,
output wire a_afull,
output wire a_empty,
output wire a_aempty,
input wire a_dir, // dir = 1: this side is writing, dir = 0: this side is reading
input wire b_clk,
input wire b_rst_n,
input wire b_winc,
input wire [DSIZE-1:0] b_wdata,
input wire b_rinc,
output wire [DSIZE-1:0] b_rdata,
output wire b_full,
output wire b_afull,
output wire b_empty,
output wire b_aempty,
input wire b_dir, // dir = 1: this side is writing, dir = 0: this side is reading
// Dual-port RAM interface
output wire o_ram_a_clk,
output wire [DSIZE-1:0] o_ram_a_wdata,
input wire [DSIZE-1:0] i_ram_a_rdata,
output wire [ASIZE-1:0] o_ram_a_addr,
output wire o_ram_a_rinc,
output wire o_ram_a_winc,
output wire o_ram_b_clk,
output wire [DSIZE-1:0] o_ram_b_wdata,
input wire [DSIZE-1:0] i_ram_b_rdata,
output wire [ASIZE-1:0] o_ram_b_addr,
output wire o_ram_b_rinc,
output wire o_ram_b_winc
);
wire [ASIZE-1:0] a_addr, b_addr;
wire [ASIZE-1:0] a_waddr, a_raddr, b_waddr, b_raddr;
wire [ ASIZE:0] a_wptr, b_rptr, a2b_wptr, b2a_rptr;
wire [ ASIZE:0] a_rptr, b_wptr, a2b_rptr, b2a_wptr;
assign a_addr = a_dir ? a_waddr : a_raddr;
assign b_addr = b_dir ? b_waddr : b_raddr;
//////////////////////////////////////////////////////////////////////////////
// A-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync b write pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_wptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_wptr),
.dest_ptr (b2a_wptr)
);
// Sync b read pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_rptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_rptr),
.dest_ptr (b2a_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (a is writing)
wptr_full #(ASIZE)
a_wptr_inst
(
.wclk (a_clk),
.wrst_n (a_rst_n),
.winc (a_winc),
.wq2_rptr (b2a_rptr),
.awfull (a_afull),
.wfull (a_full),
.waddr (a_waddr),
.wptr (a_wptr)
);
// dir == 1 read pointer on a side calculation
rptr_empty #(ASIZE)
a_rptr_inst
(
.rclk (a_clk),
.rrst_n (a_rst_n),
.rinc (a_rinc),
.rq2_wptr (b2a_wptr),
.arempty (a_aempty),
.rempty (a_empty),
.raddr (a_raddr),
.rptr (a_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// B-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync a write pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_wptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_wptr),
.dest_ptr (a2b_wptr)
);
// Sync a read pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_rptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_rptr),
.dest_ptr (a2b_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (b is writing)
wptr_full #(ASIZE)
b_wptr_inst
(
.wclk (b_clk),
.wrst_n (b_rst_n),
.winc (b_winc),
.wq2_rptr (a2b_rptr),
.awfull (b_afull),
.wfull (b_full),
.waddr (b_waddr),
.wptr (b_wptr)
);
// dir == 1 read pointer on b side calculation
rptr_empty #(ASIZE)
b_rptr_inst
(
.rclk (b_clk),
.rrst_n (b_rst_n),
.rinc (b_rinc),
.rq2_wptr (a2b_wptr),
.arempty (b_aempty),
.rempty (b_empty),
.raddr (b_raddr),
.rptr (b_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// FIFO RAM interface
//////////////////////////////////////////////////////////////////////////////
assign o_ram_a_clk = a_clk;
assign o_ram_a_wdata = a_wdata;
assign a_rdata = i_ram_a_rdata;
assign o_ram_a_addr = a_addr;
assign o_ram_a_rinc = a_rinc & !a_dir;
assign o_ram_a_winc = a_winc & a_dir;
assign o_ram_b_clk = b_clk;
assign o_ram_b_wdata = b_wdata;
assign b_rdata = i_ram_b_rdata;
assign o_ram_b_addr = b_addr;
assign o_ram_b_rinc = b_rinc & !b_dir;
assign o_ram_b_winc = b_winc & b_dir;
endmodule
`resetall
|
// ###############################################################
// # FUNCTION: Synchronous clock divider that divides by integer
// ###############################################################
module clock_divider(/*AUTOARG*/
// Outputs
clkout, clkout90,
// Inputs
clkin, divcfg, reset
);
input clkin; // Input clock
input [3:0] divcfg; // Divide factor
input reset; // Counter init
output clkout; // Divided clock phase aligned with clkin
output clkout90; // Divided clock with 90deg phase shift with clkout
reg clkout_reg;
reg [7:0] counter;
reg [7:0] divcfg_dec;
reg [3:0] divcfg_reg;
reg [3:0] divcfg_change;
wire div2_sel;
wire div1_sel;
wire posedge_match;
wire negedge_match;
wire posedge90_match;
wire negedge90_match;
reg clkout90_div4;
reg clkout90_div2;
// ###################
// # Decode divcfg
// ###################
always @ (divcfg[3:0])
casez (divcfg[3:0])
4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
4'b0111 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
default : divcfg_dec[7:0] = 8'b00000000; // others
endcase
//Divide by two special case
assign div2_sel = divcfg[3:0]==4'b0001;
assign div1_sel = divcfg[3:0]==4'b0000;
//Edge change detector (no need for synchronizer)
always @ (posedge clkin or posedge reset)
if(reset)
divcfg_change <=1'b0;
else
begin
divcfg_change <= (divcfg_reg[3:0]^divcfg[3:0]);
divcfg_reg[3:0] <=divcfg[3:0];
end
always @ (posedge clkin or posedge reset)
if(reset)
counter[7:0] <= 8'b000001;
else
if(posedge_match | divcfg_change)
counter[7:0] <= 8'b000001;// Self resetting
else
counter[7:0] <= (counter[7:0] + 8'b000001);
assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
assign posedge90_match = (counter[7:0]==({2'b00,divcfg_dec[7:2]}));
assign negedge90_match = (counter[7:0]==({2'b00,divcfg_dec[7:2]} +
{1'b0,divcfg_dec[7:1]}));
always @ (posedge clkin or posedge reset)
if(reset)
clkout_reg <= 1'b0;
else if(posedge_match)
clkout_reg <= 1'b1;
else if(negedge_match)
clkout_reg <= 1'b0;
assign clkout = div1_sel ? clkin : clkout_reg;
always @ (posedge clkin)
clkout90_div4 <= posedge90_match ? 1'b1 :
negedge90_match ? 1'b0 :
clkout90_div4;
always @ (negedge clkin)
clkout90_div2 <= negedge_match ? 1'b1 :
posedge_match ? 1'b0 :
clkout90_div2;
assign clkout90 = div2_sel ? clkout90_div2 : clkout90_div4;
endmodule // clock_divider
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// 4. For ECC ON case inserts error on LSB bit
// of data from DRAM to FPGA.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "TRUE";
parameter PORT_MODE = "BI_MODE";
parameter DATA_MODE = 4'b0010;
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE";
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL";
// For small devices, choose one only.
// For large device, choose "DGEN_ALL"
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000;
parameter END_ADDRESS = 32'h00000fff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter DM_WIDTH = 2;
// # of DM (data mask)
parameter DQ_WIDTH = 16;
// # of DQ (data)
parameter DQS_WIDTH = 2;
parameter DQS_CNT_WIDTH = 1;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
// # of DQ per DQS
parameter ECC = "OFF";
parameter RANKS = 1;
// # of Ranks.
parameter ODT_WIDTH = 1;
// # of ODT outputs to memory.
parameter ROW_WIDTH = 14;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 28;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8";
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter CA_MIRROR = "OFF";
// C/A mirror opt for DDR3 dual rank
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 3000;
// Input Clock Period
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "SIM_INIT_CAL_FULL" - Complete
// memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter TCQ = 100;
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0;
// IODELAYCTRL reference clock frequency
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3000;
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 4;
// # of memory CKs per fabric CLK
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DRAM_TYPE = "DDR3";
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00;
// Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00;
// Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00;
// Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00;
// Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00;
// Delay for data signal during Read operation
localparam MEMORY_WIDTH = 16;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam ECC_TEST = "OFF" ;
localparam ERR_INSERT = (ECC_TEST == "ON") ? "OFF" : ECC ;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam RESET_PERIOD = 200000; //in pSec
localparam real SYSCLK_PERIOD = tCK;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
reg sys_clk_i;
reg clk_ref_i;
wire ddr3_reset_n;
wire [DQ_WIDTH-1:0] ddr3_dq_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;
wire [ROW_WIDTH-1:0] ddr3_addr_fpga;
wire [3-1:0] ddr3_ba_fpga;
wire ddr3_ras_n_fpga;
wire ddr3_cas_n_fpga;
wire ddr3_we_n_fpga;
wire [1-1:0] ddr3_cke_fpga;
wire [1-1:0] ddr3_ck_p_fpga;
wire [1-1:0] ddr3_ck_n_fpga;
wire init_calib_complete;
wire tg_compare_error;
wire [(CS_WIDTH*1)-1:0] ddr3_cs_n_fpga;
wire [DM_WIDTH-1:0] ddr3_dm_fpga;
wire [ODT_WIDTH-1:0] ddr3_odt_fpga;
reg [(CS_WIDTH*1)-1:0] ddr3_cs_n_sdram_tmp;
reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;
reg [ODT_WIDTH-1:0] ddr3_odt_sdram_tmp;
wire [DQ_WIDTH-1:0] ddr3_dq_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_sdram [0:1];
reg [3-1:0] ddr3_ba_sdram [0:1];
reg ddr3_ras_n_sdram;
reg ddr3_cas_n_sdram;
reg ddr3_we_n_sdram;
wire [(CS_WIDTH*1)-1:0] ddr3_cs_n_sdram;
wire [ODT_WIDTH-1:0] ddr3_odt_sdram;
reg [1-1:0] ddr3_cke_sdram;
wire [DM_WIDTH-1:0] ddr3_dm_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;
reg [1-1:0] ddr3_ck_p_sdram;
reg [1-1:0] ddr3_ck_n_sdram;
//**************************************************************************//
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
always @( * ) begin
ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;
ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;
ddr3_addr_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;
ddr3_addr_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ?
{ddr3_addr_fpga[ROW_WIDTH-1:9],
ddr3_addr_fpga[7], ddr3_addr_fpga[8],
ddr3_addr_fpga[5], ddr3_addr_fpga[6],
ddr3_addr_fpga[3], ddr3_addr_fpga[4],
ddr3_addr_fpga[2:0]} :
ddr3_addr_fpga;
ddr3_ba_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;
ddr3_ba_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ?
{ddr3_ba_fpga[3-1:2],
ddr3_ba_fpga[0],
ddr3_ba_fpga[1]} :
ddr3_ba_fpga;
ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;
ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;
ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;
ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;
end
always @( * )
ddr3_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;
assign ddr3_cs_n_sdram = ddr3_cs_n_sdram_tmp;
always @( * )
ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation
assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
always @( * )
ddr3_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;
assign ddr3_odt_sdram = ddr3_odt_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr3_dq_fpga[dqwd]),
.B (ddr3_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
// For ECC ON case error is inserted on LSB bit from DRAM to FPGA
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT (ERR_INSERT)
)
u_delay_dq_0
(
.A (ddr3_dq_fpga[0]),
.B (ddr3_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr3_dqs_p_fpga[dqswd]),
.B (ddr3_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr3_dqs_n_fpga[dqswd]),
.B (ddr3_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
endgenerate
//===========================================================================
// FPGA Memory Controller
//===========================================================================
example_top #
(
.SIMULATION (SIMULATION),
.PORT_MODE (PORT_MODE),
.DATA_MODE (DATA_MODE),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.EYE_TEST (EYE_TEST),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC_TEST (ECC_TEST),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.BURST_MODE (BURST_MODE),
.TCQ (TCQ),
.DRAM_TYPE (DRAM_TYPE),
.nCK_PER_CLK (nCK_PER_CLK),
.DEBUG_PORT (DEBUG_PORT),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_ip_top
(
.ddr3_dq (ddr3_dq_fpga),
.ddr3_dqs_n (ddr3_dqs_n_fpga),
.ddr3_dqs_p (ddr3_dqs_p_fpga),
.ddr3_addr (ddr3_addr_fpga),
.ddr3_ba (ddr3_ba_fpga),
.ddr3_ras_n (ddr3_ras_n_fpga),
.ddr3_cas_n (ddr3_cas_n_fpga),
.ddr3_we_n (ddr3_we_n_fpga),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_ck_p (ddr3_ck_p_fpga),
.ddr3_ck_n (ddr3_ck_n_fpga),
.ddr3_cke (ddr3_cke_fpga),
.ddr3_cs_n (ddr3_cs_n_fpga),
.ddr3_dm (ddr3_dm_fpga),
.ddr3_odt (ddr3_odt_fpga),
.sys_clk_i (sys_clk_i),
.clk_ref_i (clk_ref_i),
.device_temp_i (12'b0),
.init_calib_complete (init_calib_complete),
.tg_compare_error (tg_compare_error),
.sys_rst (sys_rst)
);
//**************************************************************************//
// Memory Models instantiations
//**************************************************************************//
genvar r,i;
generate
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
if(DQ_WIDTH/16) begin: mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram[r]),
.addr (ddr3_addr_sdram[r]),
.dq (ddr3_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram[r]),
.addr (ddr3_addr_sdram[r]),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
// Status reporting logic exists both in simulation test bench (sim_tb_top)
// and sim.do file for ModelSim. Any update in simulation run time or time out
// in this file need to be updated in sim.do file as well.
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (init_calib_complete);
$display("Calibration Done");
#50000000.0;
if (!tg_compare_error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")
#2500000000.0;
else
#1000000000.0;
if (!init_calib_complete) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_int_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr3_int_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire5;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [4:4] sub_wire7 = sub_wire0[4:4];
wire [0:0] sub_wire6 = sub_wire0[0:0];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire locked = sub_wire5;
wire c0 = sub_wire6;
wire c4 = sub_wire7;
wire phasedone = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.scanclk (scanclk),
.phaseupdown (phaseupdown),
.clk (sub_wire0),
.locked (sub_wire5),
.phasedone (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 6,
altpll_component.clk0_phase_shift = "556",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 12,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 12,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 12,
altpll_component.clk3_phase_shift = "-833",
altpll_component.clk4_divide_by = 1,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 12,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 1,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 12,
altpll_component.clk5_phase_shift = "0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 104,
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "300.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll_siii.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_bb.v TRUE
|
(** * Generic Tactics *)
Require Export Crypto.Util.FixCoqMistakes.
Require Export Crypto.Util.Tactics.BreakMatch.
Require Export Crypto.Util.Tactics.Head.
Require Export Crypto.Util.Tactics.DestructHyps.
Require Export Crypto.Util.Tactics.DestructHead.
Require Export Crypto.Util.Tactics.DoWithHyp.
Require Export Crypto.Util.Tactics.RewriteHyp.
Require Export Crypto.Util.Tactics.SpecializeBy.
Require Export Crypto.Util.Tactics.SplitInContext.
Require Export Crypto.Util.Tactics.UniquePose.
Require Export Crypto.Util.Tactics.VM.
(** Test if a tactic succeeds, but always roll-back the results *)
Tactic Notation "test" tactic3(tac) :=
try (first [ tac | fail 2 tac "does not succeed" ]; fail 0 tac "succeeds"; [](* test for [t] solved all goals *)).
(** [not tac] is equivalent to [fail tac "succeeds"] if [tac] succeeds, and is equivalent to [idtac] if [tac] fails *)
Tactic Notation "not" tactic3(tac) := try ((test tac); fail 1 tac "succeeds").
Ltac get_goal :=
match goal with |- ?G => G end.
(** [contains x expr] succeeds iff [x] appears in [expr] *)
Ltac contains search_for in_term :=
idtac;
lazymatch in_term with
| appcontext[search_for] => idtac
end.
Ltac debuglevel := constr:(0%nat).
Ltac solve_debugfail tac :=
solve [tac] ||
( let dbg := debuglevel in
match dbg with
| O => idtac
| _ => match goal with |- ?G => idtac "couldn't prove" G end
end;
fail).
Ltac set_evars :=
repeat match goal with
| [ |- appcontext[?E] ] => is_evar E; let e := fresh "e" in set (e := E)
end.
Ltac subst_evars :=
repeat match goal with
| [ e := ?E |- _ ] => is_evar E; subst e
end.
Ltac subst_let := repeat match goal with | x := _ |- _ => subst x end.
Ltac free_in x y :=
idtac;
match y with
| appcontext[x] => fail 1 x "appears in" y
| _ => idtac
end.
Ltac setoid_subst'' R x :=
is_var x;
match goal with
| [ H : R x ?y |- _ ]
=> free_in x y; rewrite ?H in *; clear x H
| [ H : R ?y x |- _ ]
=> free_in x y; rewrite <- ?H in *; clear x H
end.
Ltac setoid_subst' x :=
is_var x;
match goal with
| [ H : ?R x _ |- _ ] => setoid_subst'' R x
| [ H : ?R _ x |- _ ] => setoid_subst'' R x
end.
Ltac setoid_subst_rel' R :=
idtac;
match goal with
| [ H : R ?x _ |- _ ] => setoid_subst'' R x
| [ H : R _ ?x |- _ ] => setoid_subst'' R x
end.
Ltac setoid_subst_rel R := repeat setoid_subst_rel' R.
Ltac setoid_subst_all :=
repeat match goal with
| [ H : ?R ?x ?y |- _ ] => is_var x; setoid_subst'' R x
| [ H : ?R ?x ?y |- _ ] => is_var y; setoid_subst'' R y
end.
Tactic Notation "setoid_subst" ident(x) := setoid_subst' x.
Tactic Notation "setoid_subst" := setoid_subst_all.
Ltac destruct_trivial_step :=
match goal with
| [ H : unit |- _ ] => clear H || destruct H
| [ H : True |- _ ] => clear H || destruct H
end.
Ltac destruct_trivial := repeat destruct_trivial_step.
Ltac clear_duplicates_step :=
match goal with
| [ H : ?T, H' : ?T |- _ ] => clear H'
| [ H := ?T, H' := ?T |- _ ] => clear H'
end.
Ltac clear_duplicates := repeat clear_duplicates_step.
(** given a [matcher] that succeeds on some hypotheses and fails on
others, destruct any matching hypotheses, and then execute [tac]
after each [destruct].
The [tac] part exists so that you can, e.g., [simpl in *], to
speed things up. *)
Ltac do_one_match_then matcher do_tac tac :=
idtac;
match goal with
| [ H : ?T |- _ ]
=> matcher T; do_tac H;
try match type of H with
| T => clear H
end;
tac
end.
Ltac do_all_matches_then matcher do_tac tac :=
repeat do_one_match_then matcher do_tac tac.
Ltac destruct_all_matches_then matcher tac :=
do_all_matches_then matcher ltac:(fun H => destruct H) tac.
Ltac destruct_one_match_then matcher tac :=
do_one_match_then matcher ltac:(fun H => destruct H) tac.
Ltac inversion_all_matches_then matcher tac :=
do_all_matches_then matcher ltac:(fun H => inversion H; subst) tac.
Ltac inversion_one_match_then matcher tac :=
do_one_match_then matcher ltac:(fun H => inversion H; subst) tac.
Ltac destruct_all_matches matcher :=
destruct_all_matches_then matcher ltac:( simpl in * ).
Ltac destruct_one_match matcher := destruct_one_match_then matcher ltac:( simpl in * ).
Ltac destruct_all_matches' matcher := destruct_all_matches_then matcher idtac.
Ltac inversion_all_matches matcher := inversion_all_matches_then matcher ltac:( simpl in * ).
Ltac inversion_one_match matcher := inversion_one_match_then matcher ltac:( simpl in * ).
Ltac inversion_all_matches' matcher := inversion_all_matches_then matcher idtac.
(** If [tac_in H] operates in [H] and leaves side-conditions before
the original goal, then
[side_conditions_before_to_side_conditions_after tac_in H] does
the same thing to [H], but leaves side-conditions after the
original goal. *)
Ltac side_conditions_before_to_side_conditions_after tac_in H :=
let HT := type of H in
let HTT := type of HT in
let H' := fresh in
rename H into H';
let HT' := fresh in
evar (HT' : HTT);
cut HT';
[ subst HT'; intro H
| tac_in H';
[ ..
| subst HT'; eexact H' ] ];
instantiate; (* required in 8.4 for the [move] to succeed, because evar dependencies *)
[ (* We preserve the order of the hypotheses. We need to do this
here, after evars are instantiated, and not above. *)
move H after H'; clear H'
| .. ].
(** Execute [progress tac] on all subterms of the goal. Useful for things like [ring_simplify]. *)
Ltac tac_on_subterms tac :=
repeat match goal with
| [ |- context[?t] ]
=> progress tac t
end.
(** Like [Coq.Program.Tactics.revert_last], but only for non-dependent hypotheses *)
Ltac revert_last_nondep :=
match goal with
| [ H : _ |- _ ]
=> lazymatch goal with
| [ H' : appcontext[H] |- _ ] => fail
| [ |- appcontext[H] ] => fail
| _ => idtac
end;
revert H
end.
Ltac reverse_nondep := repeat revert_last_nondep.
Ltac simplify_repeated_ifs_step :=
match goal with
| [ |- context G[if ?b then ?x else ?y] ]
=> let x' := match x with
| context x'[b] => let x'' := context x'[true] in x''
end in
let G' := context G[if b then x' else y] in
cut G'; [ destruct b; exact (fun z => z) | cbv iota ]
| [ |- context G[if ?b then ?x else ?y] ]
=> let y' := match y with
| context y'[b] => let y'' := context y'[false] in y''
end in
let G' := context G[if b then x else y'] in
cut G'; [ destruct b; exact (fun z => z) | cbv iota ]
end.
Ltac simplify_repeated_ifs := repeat simplify_repeated_ifs_step.
(** Like [specialize] but allows holes that get filled with evars. *)
Tactic Notation "especialize" open_constr(H) := specialize H.
(** [forward H] specializes non-dependent binders in a hypothesis [H]
with side-conditions. Side-conditions come after the main goal,
like with [replace] and [rewrite].
[eforward H] is like [forward H], but also specializes dependent
binders with evars.
Both tactics do nothing on hypotheses they cannot handle. *)
Ltac forward_step H :=
match type of H with
| ?A -> ?B => let a := fresh in cut A; [ intro a; specialize (H a); clear a | ]
end.
Ltac eforward_step H :=
match type of H with
| _ => forward_step H
| forall x : ?A, _
=> let x_or_fresh := fresh x in
evar (x_or_fresh : A);
specialize (H x_or_fresh); subst x_or_fresh
end.
Ltac forward H := try (forward_step H; [ forward H | .. ]).
Ltac eforward H := try (eforward_step H; [ eforward H | .. ]).
(** [simplify_projections] reduces terms of the form [fst (_, _)] (for
any projection from [prod], [sig], [sigT], or [and]) *)
Ltac pre_simplify_projection proj proj' uproj' :=
pose proj as proj';
pose proj as uproj';
unfold proj in uproj';
change proj with proj'.
Ltac do_simplify_projection_2Targ_4carg_step proj proj' uproj' construct :=
change proj' with uproj' at 1;
lazymatch goal with
| [ |- appcontext[uproj' _ _ (construct _ _ _ _)] ]
=> cbv beta iota delta [uproj']
| _ => change uproj' with proj
end.
Ltac do_simplify_projection_2Targ_4carg proj proj' uproj' construct :=
repeat do_simplify_projection_2Targ_4carg_step proj proj' uproj' construct.
Ltac simplify_projection_2Targ_4carg proj construct :=
let proj' := fresh "proj" in
let uproj' := fresh "proj" in
pre_simplify_projection proj proj' uproj';
do_simplify_projection_2Targ_4carg proj proj' uproj' construct;
clear proj' uproj'.
Ltac simplify_projections :=
repeat (simplify_projection_2Targ_4carg @fst @pair
|| simplify_projection_2Targ_4carg @snd @pair
|| simplify_projection_2Targ_4carg @proj1_sig @exist
|| simplify_projection_2Targ_4carg @proj2_sig @exist
|| simplify_projection_2Targ_4carg @projT1 @existT
|| simplify_projection_2Targ_4carg @projT2 @existT
|| simplify_projection_2Targ_4carg @proj1 @conj
|| simplify_projection_2Targ_4carg @proj2 @conj).
(** constr-based [idtac] *)
Class cidtac {T} (msg : T) := Build_cidtac : True.
Hint Extern 0 (cidtac ?msg) => idtac msg; exact I : typeclass_instances.
(** constr-based [idtac] *)
Class cidtac2 {T1 T2} (msg1 : T1) (msg2 : T2) := Build_cidtac2 : True.
Hint Extern 0 (cidtac2 ?msg1 ?msg2) => idtac msg1 msg2; exact I : typeclass_instances.
Class cidtac3 {T1 T2 T3} (msg1 : T1) (msg2 : T2) (msg3 : T3) := Build_cidtac3 : True.
Hint Extern 0 (cidtac3 ?msg1 ?msg2 ?msg3) => idtac msg1 msg2 msg3; exact I : typeclass_instances.
Class cfail {T} (msg : T) := Build_cfail : True.
Hint Extern 0 (cfail ?msg) => idtac "Error:" msg; exact I : typeclass_instances.
Class cfail2 {T1 T2} (msg1 : T1) (msg2 : T2) := Build_cfail2 : True.
Hint Extern 0 (cfail2 ?msg1 ?msg2) => idtac "Error:" msg1 msg2; exact I : typeclass_instances.
Class cfail3 {T1 T2 T3} (msg1 : T1) (msg2 : T2) (msg3 : T3) := Build_cfail3 : True.
Hint Extern 0 (cfail3 ?msg1 ?msg2 ?msg3) => idtac "Error:" msg1 msg2 msg3; exact I : typeclass_instances.
Ltac cidtac msg := constr:(_ : cidtac msg).
Ltac cidtac2 msg1 msg2 := constr:(_ : cidtac2 msg1 msg2).
Ltac cidtac3 msg1 msg2 msg3 := constr:(_ : cidtac2 msg1 msg2 msg3).
Ltac cfail msg := let dummy := constr:(_ : cfail msg) in constr:(I : I).
Ltac cfail2 msg1 msg2 := let dummy := constr:(_ : cfail2 msg1 msg2) in constr:(I : I).
Ltac cfail3 msg1 msg2 msg3 := let dummy := constr:(_ : cfail2 msg1 msg2 msg3) in constr:(I : I).
Ltac idtac_goal := lazymatch goal with |- ?G => idtac "Goal:" G end.
Ltac idtac_context :=
try (repeat match goal with H : _ |- _ => revert H end;
idtac_goal;
lazymatch goal with |- ?G => idtac "Context:" G end;
fail).
(** Destruct the convoy pattern ([match e as x return x = e -> _ with _ => _ end eq_refl] *)
Ltac convoy_destruct_gen T change_in :=
let e' := fresh in
let H' := fresh in
match T with
| context G[?f eq_refl]
=> match f with
| match ?e with _ => _ end
=> pose e as e';
match f with
| context F[e]
=> let F' := context F[e'] in
first [ pose (eq_refl : e = e') as H';
let G' := context G[F' H'] in
change_in G';
clearbody H' e'
| pose (eq_refl : e' = e) as H';
let G' := context G[F' H'] in
change_in G';
clearbody H' e' ]
end
end;
destruct e'
end.
Ltac convoy_destruct_in H :=
let T := type of H in
convoy_destruct_gen T ltac:(fun T' => change T' in H).
Ltac convoy_destruct :=
let T := get_goal in
convoy_destruct_gen T ltac:(fun T' => change T').
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_BLACKBOX_V
`define SKY130_FD_SC_MS__OR4_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_BLACKBOX_V
|
//==================================================================================================
// Filename : antares_memwb_register.v
// Created On : Sat Sep 5 21:41:57 2015
// Last Modified : Sat Nov 07 12:10:59 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Pipeline register: MEM -> WB
//==================================================================================================
module antares_memwb_register (
input clk, // main clock
input rst, // main reset
input [31:0] mem_read_data, // data from Memory
input [31:0] mem_alu_data, // data from ALU
input [4:0] mem_gpr_wa, // GPR write enable
input mem_mem_to_gpr_select, // select MEM/ALU to GPR
input mem_gpr_we, // GPR write enable
input mem_flush,
input mem_stall, // stall MEM stage
input wb_stall, // stall WB stage
output reg [31:0] wb_read_data, // data from Memory
output reg [31:0] wb_alu_data, // data from ALU
output reg [4:0] wb_gpr_wa, // GPR write address
output reg wb_mem_to_gpr_select, // select MEM/ALU to GPR
output reg wb_gpr_we // GPR write enable
);
//--------------------------------------------------------------------------
// Propagate signals
//--------------------------------------------------------------------------
always @(posedge clk) begin
wb_read_data <= (rst) ? 32'b0 : ((wb_stall) ? wb_read_data : mem_read_data);
wb_alu_data <= (rst) ? 32'b0 : ((wb_stall) ? wb_alu_data : mem_alu_data);
wb_gpr_wa <= (rst) ? 5'b0 : ((wb_stall) ? wb_gpr_wa : mem_gpr_wa);
wb_mem_to_gpr_select <= (rst) ? 1'b0 : ((wb_stall) ? wb_mem_to_gpr_select : mem_mem_to_gpr_select);
wb_gpr_we <= (rst) ? 1'b0 : ((wb_stall) ? wb_gpr_we : ((mem_stall | mem_flush) ? 1'b0 : mem_gpr_we));
end
endmodule // antares_memwb_register
|
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