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// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Fri Jul 8 09:16:27 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode funcsim {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_sim_netlist.v}
// Design : shd_fifo
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "shd_fifo,fifo_generator_v13_0_1,{}" *) (* core_generation_info = "shd_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=128,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=128,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=511,C_PROG_FULL_THRESH_NEGATE_VAL=510,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v13_0_1,Vivado 2015.4" *)
(* NotValidForBitStream *)
module shd_fifo
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [127:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [127:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [8:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [8:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [8:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "128" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "128" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *)
(* C_PRELOAD_REGS = "1" *)
(* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "511" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "510" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "512" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "9" *)
(* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
shd_fifo_fifo_generator_v13_0_1 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[8:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[8:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[8:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module shd_fifo_blk_mem_gen_generic_cstr
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [127:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r
(.D(D[71:0]),
.E(E),
.Q(Q),
.din(din[71:0]),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
shd_fifo_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.D(D[127:72]),
.E(E),
.Q(Q),
.din(din[127:72]),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module shd_fifo_blk_mem_gen_prim_width
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [71:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [71:0]din;
wire [71:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [71:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module shd_fifo_blk_mem_gen_prim_width__parameterized0
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [55:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [55:0]din;
wire [55:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [55:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_fifo_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module shd_fifo_blk_mem_gen_prim_wrapper
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [71:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [71:0]din;
wire [71:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [71:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
(.ADDRARDADDR({1'b1,\gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(rd_clk),
.CLKBWRCLK(wr_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({din[70:63],din[61:54],din[52:45],din[43:36]}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({din[71],din[62],din[53],din[44]}),
.DOADO({D[34:27],D[25:18],D[16:9],D[7:0]}),
.DOBDO({D[70:63],D[61:54],D[52:45],D[43:36]}),
.DOPADOP({D[35],D[26],D[17],D[8]}),
.DOPBDOP({D[71],D[62],D[53],D[44]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(E),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(Q),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({E,E,E,E,E,E,E,E}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module shd_fifo_blk_mem_gen_prim_wrapper__parameterized0
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [55:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [55:0]din;
wire [55:0]D;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92 ;
wire [0:0]E;
wire [0:0]Q;
wire [55:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
(.ADDRARDADDR({1'b1,\gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(rd_clk),
.CLKBWRCLK(wr_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,din[55:49],1'b0,din[48:42],1'b0,din[41:35],1'b0,din[34:28]}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21 ,D[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29 ,D[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ,D[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ,D[6:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ,D[55:49],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61 ,D[48:42],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69 ,D[41:35],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77 ,D[34:28]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(E),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(Q),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({E,E,E,E,E,E,E,E}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module shd_fifo_blk_mem_gen_top
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [127:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_fifo_blk_mem_gen_generic_cstr \valid.cstr
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1" *)
module shd_fifo_blk_mem_gen_v8_3_1
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [127:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_fifo_blk_mem_gen_v8_3_1_synth inst_blk_mem_gen
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1_synth" *)
module shd_fifo_blk_mem_gen_v8_3_1_synth
(D,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [127:0]D;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_fifo_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module shd_fifo_clk_x_pntrs
(ram_empty_fb_i_reg,
WR_PNTR_RD,
v1_reg,
v1_reg_0,
RD_PNTR_WR,
v1_reg_1,
Q,
\gc0.count_reg[7] ,
\gic0.gc0.count_d1_reg[7] ,
\gic0.gc0.count_reg[7] ,
\gic0.gc0.count_d2_reg[8] ,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output ram_empty_fb_i_reg;
output [8:0]WR_PNTR_RD;
output [3:0]v1_reg;
output [3:0]v1_reg_0;
output [0:0]RD_PNTR_WR;
output [3:0]v1_reg_1;
input [8:0]Q;
input [7:0]\gc0.count_reg[7] ;
input [7:0]\gic0.gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_reg[7] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [8:0]Q;
wire [0:0]RD_PNTR_WR;
wire [8:0]WR_PNTR_RD;
wire [7:0]\gc0.count_reg[7] ;
wire [7:0]\gic0.gc0.count_d1_reg[7] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire [7:0]\gic0.gc0.count_reg[7] ;
wire \gsync_stage[2].wr_stg_inst_n_1 ;
wire \gsync_stage[2].wr_stg_inst_n_2 ;
wire \gsync_stage[2].wr_stg_inst_n_3 ;
wire \gsync_stage[2].wr_stg_inst_n_4 ;
wire \gsync_stage[2].wr_stg_inst_n_5 ;
wire \gsync_stage[2].wr_stg_inst_n_6 ;
wire \gsync_stage[2].wr_stg_inst_n_7 ;
wire \gsync_stage[2].wr_stg_inst_n_8 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]p_0_in;
wire [7:0]p_0_in7_out;
wire [8:8]p_0_out;
wire [8:8]p_1_out;
wire [7:0]p_22_out;
wire [8:0]p_2_out;
wire [8:0]p_3_out;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire [8:0]rd_pntr_gc;
wire \rd_pntr_gc[0]_i_1_n_0 ;
wire \rd_pntr_gc[1]_i_1_n_0 ;
wire \rd_pntr_gc[2]_i_1_n_0 ;
wire \rd_pntr_gc[3]_i_1_n_0 ;
wire \rd_pntr_gc[4]_i_1_n_0 ;
wire \rd_pntr_gc[5]_i_1_n_0 ;
wire \rd_pntr_gc[6]_i_1_n_0 ;
wire \rd_pntr_gc[7]_i_1_n_0 ;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire wr_clk;
wire [8:0]wr_pntr_gc;
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(WR_PNTR_RD[1]),
.I1(\gc0.count_reg[7] [1]),
.I2(WR_PNTR_RD[0]),
.I3(\gc0.count_reg[7] [0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_22_out[1]),
.I1(\gic0.gc0.count_d1_reg[7] [1]),
.I2(p_22_out[0]),
.I3(\gic0.gc0.count_d1_reg[7] [0]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(p_22_out[1]),
.I1(\gic0.gc0.count_reg[7] [1]),
.I2(p_22_out[0]),
.I3(\gic0.gc0.count_reg[7] [0]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(WR_PNTR_RD[3]),
.I1(\gc0.count_reg[7] [3]),
.I2(WR_PNTR_RD[2]),
.I3(\gc0.count_reg[7] [2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_22_out[3]),
.I1(\gic0.gc0.count_d1_reg[7] [3]),
.I2(p_22_out[2]),
.I3(\gic0.gc0.count_d1_reg[7] [2]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(p_22_out[3]),
.I1(\gic0.gc0.count_reg[7] [3]),
.I2(p_22_out[2]),
.I3(\gic0.gc0.count_reg[7] [2]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(WR_PNTR_RD[5]),
.I1(\gc0.count_reg[7] [5]),
.I2(WR_PNTR_RD[4]),
.I3(\gc0.count_reg[7] [4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_22_out[5]),
.I1(\gic0.gc0.count_d1_reg[7] [5]),
.I2(p_22_out[4]),
.I3(\gic0.gc0.count_d1_reg[7] [4]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(p_22_out[5]),
.I1(\gic0.gc0.count_reg[7] [5]),
.I2(p_22_out[4]),
.I3(\gic0.gc0.count_reg[7] [4]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(WR_PNTR_RD[7]),
.I1(\gc0.count_reg[7] [7]),
.I2(WR_PNTR_RD[6]),
.I3(\gc0.count_reg[7] [6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_22_out[7]),
.I1(\gic0.gc0.count_d1_reg[7] [7]),
.I2(p_22_out[6]),
.I3(\gic0.gc0.count_d1_reg[7] [6]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(p_22_out[7]),
.I1(\gic0.gc0.count_reg[7] [7]),
.I2(p_22_out[6]),
.I3(\gic0.gc0.count_reg[7] [6]),
.O(v1_reg_1[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__0
(.I0(WR_PNTR_RD[8]),
.I1(Q[8]),
.O(ram_empty_fb_i_reg));
shd_fifo_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
shd_fifo_synchronizer_ff_3 \gsync_stage[1].wr_stg_inst
(.D(p_2_out),
.Q(rd_pntr_gc),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.wr_clk(wr_clk));
shd_fifo_synchronizer_ff_4 \gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_1_out),
.rd_clk(rd_clk),
.\wr_pntr_bin_reg[7] (p_0_in));
shd_fifo_synchronizer_ff_5 \gsync_stage[2].wr_stg_inst
(.D(p_2_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.out(p_0_out),
.\rd_pntr_bin_reg[7] ({\gsync_stage[2].wr_stg_inst_n_1 ,\gsync_stage[2].wr_stg_inst_n_2 ,\gsync_stage[2].wr_stg_inst_n_3 ,\gsync_stage[2].wr_stg_inst_n_4 ,\gsync_stage[2].wr_stg_inst_n_5 ,\gsync_stage[2].wr_stg_inst_n_6 ,\gsync_stage[2].wr_stg_inst_n_7 ,\gsync_stage[2].wr_stg_inst_n_8 }),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_8 ),
.Q(p_22_out[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_7 ),
.Q(p_22_out[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_6 ),
.Q(p_22_out[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_5 ),
.Q(p_22_out[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_4 ),
.Q(p_22_out[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_3 ),
.Q(p_22_out[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_2 ),
.Q(p_22_out[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_1 ),
.Q(p_22_out[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_out),
.Q(RD_PNTR_WR));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\rd_pntr_gc[7]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[7]),
.Q(WR_PNTR_RD[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_1_out),
.Q(WR_PNTR_RD[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [0]),
.I1(\gic0.gc0.count_d2_reg[8] [1]),
.O(p_0_in7_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [1]),
.I1(\gic0.gc0.count_d2_reg[8] [2]),
.O(p_0_in7_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [2]),
.I1(\gic0.gc0.count_d2_reg[8] [3]),
.O(p_0_in7_out[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [3]),
.I1(\gic0.gc0.count_d2_reg[8] [4]),
.O(p_0_in7_out[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [4]),
.I1(\gic0.gc0.count_d2_reg[8] [5]),
.O(p_0_in7_out[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [5]),
.I1(\gic0.gc0.count_d2_reg[8] [6]),
.O(p_0_in7_out[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [6]),
.I1(\gic0.gc0.count_d2_reg[8] [7]),
.O(p_0_in7_out[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [7]),
.I1(\gic0.gc0.count_d2_reg[8] [8]),
.O(p_0_in7_out[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gic0.gc0.count_d2_reg[8] [8]),
.Q(wr_pntr_gc[8]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_fifo_compare
(comp1,
v1_reg,
\gic0.gc0.count_d1_reg[8] );
output comp1;
input [3:0]v1_reg;
input \gic0.gc0.count_d1_reg[8] ;
wire comp1;
wire \gic0.gc0.count_d1_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [3:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gic0.gc0.count_d1_reg[8] }));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_fifo_compare_0
(ram_full_i,
v1_reg_0,
\gic0.gc0.count_reg[8] ,
wr_en,
p_0_out,
comp1,
rst_full_gen_i);
output ram_full_i;
input [3:0]v1_reg_0;
input \gic0.gc0.count_reg[8] ;
input wr_en;
input p_0_out;
input comp1;
input rst_full_gen_i;
wire comp1;
wire comp2;
wire \gic0.gc0.count_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire p_0_out;
wire ram_full_i;
wire rst_full_gen_i;
wire [3:0]v1_reg_0;
wire wr_en;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gic0.gc0.count_reg[8] }));
LUT5 #(
.INIT(32'h0000FF08))
ram_full_i_i_1
(.I0(comp2),
.I1(wr_en),
.I2(p_0_out),
.I3(comp1),
.I4(rst_full_gen_i),
.O(ram_full_i));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_fifo_compare_1
(ram_empty_fb_i_reg,
v1_reg_0,
\wr_pntr_bin_reg[8] ,
p_2_out,
\gpregsm1.curr_fwft_state_reg[1] ,
rd_en,
comp1);
output ram_empty_fb_i_reg;
input [3:0]v1_reg_0;
input \wr_pntr_bin_reg[8] ;
input p_2_out;
input [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
input rd_en;
input comp1;
wire comp0;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire p_2_out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire [3:0]v1_reg_0;
wire \wr_pntr_bin_reg[8] ;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\wr_pntr_bin_reg[8] }));
LUT6 #(
.INIT(64'hBBBBABBBAAAAAAAA))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(p_2_out),
.I2(\gpregsm1.curr_fwft_state_reg[1] [0]),
.I3(\gpregsm1.curr_fwft_state_reg[1] [1]),
.I4(rd_en),
.I5(comp1),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_fifo_compare_2
(comp1,
v1_reg,
\gc0.count_reg[8] );
output comp1;
input [3:0]v1_reg;
input \gc0.count_reg[8] ;
wire comp1;
wire \gc0.count_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [3:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_reg[8] }));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module shd_fifo_fifo_generator_ramfifo
(empty,
full,
dout,
rd_clk,
wr_clk,
din,
rst,
rd_en,
wr_en);
output empty;
output full;
output [127:0]dout;
input rd_clk;
input wr_clk;
input [127:0]din;
input rst;
input rd_en;
input wr_en;
wire RD_RST;
wire RST;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gcx.clkx_n_0 ;
wire [3:0]\gras.rsts/c1/v1_reg ;
wire [3:0]\gwas.wsts/c1/v1_reg ;
wire [3:0]\gwas.wsts/c2/v1_reg ;
wire [8:0]p_0_out;
wire [8:0]p_11_out;
wire [7:0]p_12_out;
wire p_17_out;
wire [8:0]p_21_out;
wire [8:8]p_22_out;
wire p_5_out;
wire rd_clk;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire [1:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_en;
wire [7:0]wr_pntr_plus2;
wire [0:0]wr_rst_i;
shd_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.Q(p_0_out),
.RD_PNTR_WR(p_22_out),
.WR_PNTR_RD(p_21_out),
.\gc0.count_reg[7] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[7] (p_12_out),
.\gic0.gc0.count_d2_reg[8] (p_11_out),
.\gic0.gc0.count_reg[7] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (wr_rst_i),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ),
.rd_clk(rd_clk),
.v1_reg(\gras.rsts/c1/v1_reg ),
.v1_reg_0(\gwas.wsts/c1/v1_reg ),
.v1_reg_1(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk));
shd_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_0_out),
.E(p_5_out),
.Q({RD_RST,rd_rst_i[0]}),
.WR_PNTR_RD(p_21_out),
.empty(empty),
.\gc0.count_d1_reg[7] (rd_pntr_plus1),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(\gras.rsts/c1/v1_reg ),
.\wr_pntr_bin_reg[8] (\gntv_or_sync_fifo.gcx.clkx_n_0 ));
shd_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_11_out),
.E(p_17_out),
.Q(p_12_out),
.RD_PNTR_WR(p_22_out),
.full(full),
.\gic0.gc0.count_d1_reg[7] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (RST),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(\gwas.wsts/c1/v1_reg ),
.v1_reg_0(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_fifo_memory \gntv_or_sync_fifo.mem
(.E(p_17_out),
.Q(rd_rst_i[0]),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (p_0_out),
.\gic0.gc0.count_d2_reg[8] (p_11_out),
.\gpregsm1.curr_fwft_state_reg[1] (p_5_out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
shd_fifo_reset_blk_ramfifo__parameterized0 rstblk
(.Q({RST,wr_rst_i}),
.\gc0.count_reg[1] ({RD_RST,rd_rst_i}),
.rd_clk(rd_clk),
.rst(rst),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module shd_fifo_fifo_generator_top
(empty,
full,
dout,
rd_clk,
wr_clk,
din,
rst,
rd_en,
wr_en);
output empty;
output full;
output [127:0]dout;
input rd_clk;
input wr_clk;
input [127:0]din;
input rst;
input rd_en;
input wr_en;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
shd_fifo_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "128" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "128" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "511" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "510" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "512" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "9" *) (* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "9" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *)
(* ORIG_REF_NAME = "fifo_generator_v13_0_1" *)
module shd_fifo_fifo_generator_v13_0_1
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [127:0]din;
input wr_en;
input rd_en;
input [8:0]prog_empty_thresh;
input [8:0]prog_empty_thresh_assert;
input [8:0]prog_empty_thresh_negate;
input [8:0]prog_full_thresh;
input [8:0]prog_full_thresh_assert;
input [8:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [127:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [8:0]data_count;
output [8:0]rd_data_count;
output [8:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [8:0]prog_empty_thresh;
wire [8:0]prog_empty_thresh_assert;
wire [8:0]prog_empty_thresh_negate;
wire [8:0]prog_full_thresh;
wire [8:0]prog_full_thresh_assert;
wire [8:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
shd_fifo_fifo_generator_v13_0_1_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.m_aclk(m_aclk),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_0_1_synth" *)
module shd_fifo_fifo_generator_v13_0_1_synth
(dout,
empty,
full,
rd_en,
rd_clk,
wr_clk,
din,
s_aclk,
m_aclk,
rst,
wr_en,
s_aresetn);
output [127:0]dout;
output empty;
output full;
input rd_en;
input rd_clk;
input wr_clk;
input [127:0]din;
input s_aclk;
input m_aclk;
input rst;
input wr_en;
input s_aresetn;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire m_aclk;
wire rd_clk;
wire rd_en;
wire rst;
wire s_aclk;
wire s_aresetn;
wire wr_clk;
wire wr_en;
shd_fifo_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_fifo_reset_blk_ramfifo \reset_gen_ic.rstblk_cc
(.m_aclk(m_aclk),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule
(* ORIG_REF_NAME = "memory" *)
module shd_fifo_memory
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
E,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din,
\gpregsm1.curr_fwft_state_reg[1] );
output [127:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]E;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [127:0]din;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]E;
wire [0:0]Q;
wire [127:0]din;
wire [127:0]dout;
wire [127:0]doutb;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_fifo_blk_mem_gen_v8_3_1 \gbm.gbmg.gbmga.ngecc.bmg
(.D(doutb),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[0]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[0]),
.Q(dout[0]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[100]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[100]),
.Q(dout[100]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[101]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[101]),
.Q(dout[101]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[102]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[102]),
.Q(dout[102]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[103]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[103]),
.Q(dout[103]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[104]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[104]),
.Q(dout[104]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[105]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[105]),
.Q(dout[105]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[106]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[106]),
.Q(dout[106]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[107]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[107]),
.Q(dout[107]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[108]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[108]),
.Q(dout[108]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[109]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[109]),
.Q(dout[109]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[10]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[10]),
.Q(dout[10]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[110]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[110]),
.Q(dout[110]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[111]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[111]),
.Q(dout[111]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[112]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[112]),
.Q(dout[112]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[113]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[113]),
.Q(dout[113]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[114]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[114]),
.Q(dout[114]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[115]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[115]),
.Q(dout[115]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[116]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[116]),
.Q(dout[116]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[117]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[117]),
.Q(dout[117]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[118]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[118]),
.Q(dout[118]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[119]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[119]),
.Q(dout[119]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[11]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[11]),
.Q(dout[11]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[120]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[120]),
.Q(dout[120]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[121]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[121]),
.Q(dout[121]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[122]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[122]),
.Q(dout[122]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[123]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[123]),
.Q(dout[123]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[124]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[124]),
.Q(dout[124]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[125]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[125]),
.Q(dout[125]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[126]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[126]),
.Q(dout[126]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[127]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[127]),
.Q(dout[127]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[12]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[12]),
.Q(dout[12]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[13]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[13]),
.Q(dout[13]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[14]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[14]),
.Q(dout[14]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[15]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[15]),
.Q(dout[15]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[16]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[16]),
.Q(dout[16]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[17]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[17]),
.Q(dout[17]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[18]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[18]),
.Q(dout[18]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[19]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[19]),
.Q(dout[19]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[1]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[1]),
.Q(dout[1]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[20]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[20]),
.Q(dout[20]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[21]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[21]),
.Q(dout[21]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[22]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[22]),
.Q(dout[22]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[23]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[23]),
.Q(dout[23]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[24]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[24]),
.Q(dout[24]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[25]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[25]),
.Q(dout[25]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[26]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[26]),
.Q(dout[26]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[27]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[27]),
.Q(dout[27]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[28]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[28]),
.Q(dout[28]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[29]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[29]),
.Q(dout[29]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[2]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[2]),
.Q(dout[2]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[30]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[30]),
.Q(dout[30]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[31]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[31]),
.Q(dout[31]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[32]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[32]),
.Q(dout[32]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[33]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[33]),
.Q(dout[33]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[34]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[34]),
.Q(dout[34]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[35]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[35]),
.Q(dout[35]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[36]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[36]),
.Q(dout[36]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[37]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[37]),
.Q(dout[37]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[38]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[38]),
.Q(dout[38]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[39]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[39]),
.Q(dout[39]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[3]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[3]),
.Q(dout[3]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[40]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[40]),
.Q(dout[40]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[41]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[41]),
.Q(dout[41]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[42]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[42]),
.Q(dout[42]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[43]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[43]),
.Q(dout[43]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[44]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[44]),
.Q(dout[44]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[45]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[45]),
.Q(dout[45]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[46]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[46]),
.Q(dout[46]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[47]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[47]),
.Q(dout[47]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[48]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[48]),
.Q(dout[48]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[49]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[49]),
.Q(dout[49]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[4]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[4]),
.Q(dout[4]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[50]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[50]),
.Q(dout[50]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[51]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[51]),
.Q(dout[51]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[52]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[52]),
.Q(dout[52]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[53]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[53]),
.Q(dout[53]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[54]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[54]),
.Q(dout[54]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[55]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[55]),
.Q(dout[55]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[56]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[56]),
.Q(dout[56]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[57]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[57]),
.Q(dout[57]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[58]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[58]),
.Q(dout[58]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[59]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[59]),
.Q(dout[59]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[5]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[5]),
.Q(dout[5]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[60]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[60]),
.Q(dout[60]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[61]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[61]),
.Q(dout[61]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[62]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[62]),
.Q(dout[62]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[63]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[63]),
.Q(dout[63]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[64]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[64]),
.Q(dout[64]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[65]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[65]),
.Q(dout[65]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[66]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[66]),
.Q(dout[66]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[67]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[67]),
.Q(dout[67]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[68]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[68]),
.Q(dout[68]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[69]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[69]),
.Q(dout[69]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[6]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[6]),
.Q(dout[6]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[70]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[70]),
.Q(dout[70]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[71]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[71]),
.Q(dout[71]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[72]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[72]),
.Q(dout[72]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[73]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[73]),
.Q(dout[73]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[74]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[74]),
.Q(dout[74]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[75]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[75]),
.Q(dout[75]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[76]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[76]),
.Q(dout[76]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[77]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[77]),
.Q(dout[77]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[78]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[78]),
.Q(dout[78]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[79]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[79]),
.Q(dout[79]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[7]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[7]),
.Q(dout[7]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[80]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[80]),
.Q(dout[80]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[81]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[81]),
.Q(dout[81]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[82]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[82]),
.Q(dout[82]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[83]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[83]),
.Q(dout[83]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[84]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[84]),
.Q(dout[84]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[85]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[85]),
.Q(dout[85]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[86]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[86]),
.Q(dout[86]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[87]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[87]),
.Q(dout[87]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[88]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[88]),
.Q(dout[88]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[89]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[89]),
.Q(dout[89]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[8]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[8]),
.Q(dout[8]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[90]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[90]),
.Q(dout[90]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[91]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[91]),
.Q(dout[91]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[92]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[92]),
.Q(dout[92]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[93]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[93]),
.Q(dout[93]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[94]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[94]),
.Q(dout[94]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[95]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[95]),
.Q(dout[95]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[96]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[96]),
.Q(dout[96]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[97]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[97]),
.Q(dout[97]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[98]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[98]),
.Q(dout[98]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[99]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[99]),
.Q(dout[99]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[9]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[9]),
.Q(dout[9]),
.R(Q));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module shd_fifo_rd_bin_cntr
(ram_empty_fb_i_reg,
Q,
v1_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
WR_PNTR_RD,
E,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output ram_empty_fb_i_reg;
output [7:0]Q;
output [3:0]v1_reg;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
input [8:0]WR_PNTR_RD;
input [0:0]E;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [8:0]WR_PNTR_RD;
wire \gc0.count[8]_i_2_n_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [8:0]plusOp;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire [8:8]rd_pntr_plus1;
wire [3:0]v1_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h6A))
\gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[4]_i_1
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[0]),
.I4(Q[1]),
.I5(Q[4]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[6]_i_1
(.I0(Q[6]),
.I1(Q[4]),
.I2(\gc0.count[8]_i_2_n_0 ),
.I3(Q[5]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gc0.count[8]_i_2_n_0 ),
.I3(Q[4]),
.I4(Q[6]),
.O(plusOp[7]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[8]_i_1
(.I0(rd_pntr_plus1),
.I1(Q[6]),
.I2(Q[4]),
.I3(\gc0.count[8]_i_2_n_0 ),
.I4(Q[5]),
.I5(Q[7]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h8000))
\gc0.count[8]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(\gc0.count[8]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(rd_pntr_plus1),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[8]),
.Q(rd_pntr_plus1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I1(WR_PNTR_RD[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I3(WR_PNTR_RD[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I1(WR_PNTR_RD[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I3(WR_PNTR_RD[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I1(WR_PNTR_RD[5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I3(WR_PNTR_RD[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I1(WR_PNTR_RD[7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I3(WR_PNTR_RD[6]),
.O(v1_reg[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1
(.I0(rd_pntr_plus1),
.I1(WR_PNTR_RD[8]),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module shd_fifo_rd_fwft
(empty,
E,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
tmp_ram_rd_en,
\goreg_bm.dout_i_reg[127] ,
rd_clk,
Q,
p_2_out,
rd_en);
output empty;
output [0:0]E;
output [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output tmp_ram_rd_en;
output [0:0]\goreg_bm.dout_i_reg[127] ;
input rd_clk;
input [1:0]Q;
input p_2_out;
input rd_en;
wire [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [1:0]Q;
wire empty;
wire empty_fwft_fb;
wire empty_fwft_i0;
wire [0:0]\goreg_bm.dout_i_reg[127] ;
wire \gpregsm1.curr_fwft_state[0]_i_1_n_0 ;
wire \gpregsm1.curr_fwft_state[1]_i_1_n_0 ;
wire p_2_out;
wire rd_clk;
wire rd_en;
wire tmp_ram_rd_en;
LUT5 #(
.INIT(32'hAAAAEFFF))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1
(.I0(Q[0]),
.I1(rd_en),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I4(p_2_out),
.O(tmp_ram_rd_en));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(Q[1]),
.Q(empty_fwft_fb));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hBA22))
empty_fwft_i_i_1
(.I0(empty_fwft_fb),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I2(rd_en),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.O(empty_fwft_i0));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(Q[1]),
.Q(empty));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h5515))
\gc0.count_d1[8]_i_1
(.I0(p_2_out),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I3(rd_en),
.O(E));
LUT3 #(
.INIT(8'h8A))
\goreg_bm.dout_i[127]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I1(rd_en),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.O(\goreg_bm.dout_i_reg[127] ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hBA))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I1(rd_en),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.O(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h08FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I2(rd_en),
.I3(p_2_out),
.O(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q[1]),
.D(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q[1]),
.D(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module shd_fifo_rd_logic
(empty,
\gc0.count_d1_reg[7] ,
tmp_ram_rd_en,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
E,
\wr_pntr_bin_reg[8] ,
v1_reg,
rd_clk,
Q,
rd_en,
WR_PNTR_RD);
output empty;
output [7:0]\gc0.count_d1_reg[7] ;
output tmp_ram_rd_en;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [0:0]E;
input \wr_pntr_bin_reg[8] ;
input [3:0]v1_reg;
input rd_clk;
input [1:0]Q;
input rd_en;
input [8:0]WR_PNTR_RD;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [1:0]Q;
wire [8:0]WR_PNTR_RD;
wire [3:0]\c0/v1_reg ;
wire [0:0]curr_fwft_state;
wire empty;
wire [7:0]\gc0.count_d1_reg[7] ;
wire \gr1.rfwft_n_1 ;
wire \gr1.rfwft_n_2 ;
wire p_2_out;
wire rd_clk;
wire rd_en;
wire rpntr_n_0;
wire tmp_ram_rd_en;
wire [3:0]v1_reg;
wire \wr_pntr_bin_reg[8] ;
shd_fifo_rd_fwft \gr1.rfwft
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ({\gr1.rfwft_n_2 ,curr_fwft_state}),
.E(\gr1.rfwft_n_1 ),
.Q(Q),
.empty(empty),
.\goreg_bm.dout_i_reg[127] (E),
.p_2_out(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en));
shd_fifo_rd_status_flags_as \gras.rsts
(.Q(Q[1]),
.\gc0.count_reg[8] (rpntr_n_0),
.\gpregsm1.curr_fwft_state_reg[1] ({\gr1.rfwft_n_2 ,curr_fwft_state}),
.p_2_out(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.\wr_pntr_bin_reg[8] (\wr_pntr_bin_reg[8] ));
shd_fifo_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ),
.E(\gr1.rfwft_n_1 ),
.Q(\gc0.count_d1_reg[7] ),
.WR_PNTR_RD(WR_PNTR_RD),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (Q[1]),
.ram_empty_fb_i_reg(rpntr_n_0),
.rd_clk(rd_clk),
.v1_reg(\c0/v1_reg ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module shd_fifo_rd_status_flags_as
(p_2_out,
v1_reg_0,
\wr_pntr_bin_reg[8] ,
v1_reg,
\gc0.count_reg[8] ,
rd_clk,
Q,
\gpregsm1.curr_fwft_state_reg[1] ,
rd_en);
output p_2_out;
input [3:0]v1_reg_0;
input \wr_pntr_bin_reg[8] ;
input [3:0]v1_reg;
input \gc0.count_reg[8] ;
input rd_clk;
input [0:0]Q;
input [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
input rd_en;
wire [0:0]Q;
wire c0_n_0;
wire comp1;
wire \gc0.count_reg[8] ;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire p_2_out;
wire rd_clk;
wire rd_en;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire \wr_pntr_bin_reg[8] ;
shd_fifo_compare_1 c0
(.comp1(comp1),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.p_2_out(p_2_out),
.ram_empty_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg_0(v1_reg_0),
.\wr_pntr_bin_reg[8] (\wr_pntr_bin_reg[8] ));
shd_fifo_compare_2 c1
(.comp1(comp1),
.\gc0.count_reg[8] (\gc0.count_reg[8] ),
.v1_reg(v1_reg));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(Q),
.Q(p_2_out));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module shd_fifo_reset_blk_ramfifo
(s_aclk,
m_aclk,
s_aresetn);
input s_aclk;
input m_aclk;
input s_aresetn;
wire inverted_reset;
wire m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(inverted_reset),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(inverted_reset),
.Q(rst_d3));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(inverted_reset));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module shd_fifo_reset_blk_ramfifo__parameterized0
(rst_full_ff_i,
rst_full_gen_i,
Q,
\gc0.count_reg[1] ,
wr_clk,
rst,
rd_clk);
output rst_full_ff_i;
output rst_full_gen_i;
output [1:0]Q;
output [2:0]\gc0.count_reg[1] ;
input wr_clk;
input rst;
input rd_clk;
wire [1:0]Q;
wire [2:0]\gc0.count_reg[1] ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ;
wire rd_clk;
wire rd_rst_asreg;
wire rd_rst_asreg_d2;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d2;
assign rst_full_ff_i = rst_d2;
assign rst_full_gen_i = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ),
.Q(rd_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(rd_rst_asreg),
.I1(\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(\gc0.count_reg[1] [0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(\gc0.count_reg[1] [1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(\gc0.count_reg[1] [2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ),
.Q(wr_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(wr_rst_asreg),
.I1(\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_fifo_synchronizer_ff
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [8:0]D;
input [8:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [8:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[8:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_fifo_synchronizer_ff_3
(D,
Q,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [8:0]D;
input [8:0]Q;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [8:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire wr_clk;
assign D[8:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[8]),
.Q(Q_reg[8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_fifo_synchronizer_ff_4
(out,
\wr_pntr_bin_reg[7] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [7:0]\wr_pntr_bin_reg[7] ;
input [8:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [8:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
wire \wr_pntr_bin[2]_i_2_n_0 ;
wire [7:0]\wr_pntr_bin_reg[7] ;
assign out[0] = Q_reg[8];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(\wr_pntr_bin[2]_i_2_n_0 ),
.I3(Q_reg[3]),
.I4(Q_reg[2]),
.I5(Q_reg[8]),
.O(\wr_pntr_bin_reg[7] [0]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[1]_i_1
(.I0(\wr_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[3]),
.I2(Q_reg[2]),
.I3(Q_reg[8]),
.I4(Q_reg[1]),
.O(\wr_pntr_bin_reg[7] [1]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[2]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[2]),
.I2(Q_reg[3]),
.I3(\wr_pntr_bin[2]_i_2_n_0 ),
.O(\wr_pntr_bin_reg[7] [2]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[2]_i_2
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[5]),
.I3(Q_reg[4]),
.O(\wr_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[3]_i_1
(.I0(Q_reg[5]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(Q_reg[8]),
.I4(Q_reg[6]),
.I5(Q_reg[7]),
.O(\wr_pntr_bin_reg[7] [3]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[8]),
.I4(Q_reg[7]),
.O(\wr_pntr_bin_reg[7] [4]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[5]),
.I2(Q_reg[8]),
.I3(Q_reg[7]),
.O(\wr_pntr_bin_reg[7] [5]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[8]),
.O(\wr_pntr_bin_reg[7] [6]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[7]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[8]),
.O(\wr_pntr_bin_reg[7] [7]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_fifo_synchronizer_ff_5
(out,
\rd_pntr_bin_reg[7] ,
D,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [0:0]out;
output [7:0]\rd_pntr_bin_reg[7] ;
input [8:0]D;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [8:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire \rd_pntr_bin[2]_i_2_n_0 ;
wire [7:0]\rd_pntr_bin_reg[7] ;
wire wr_clk;
assign out[0] = Q_reg[8];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[8]),
.Q(Q_reg[8]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(\rd_pntr_bin[2]_i_2_n_0 ),
.I3(Q_reg[3]),
.I4(Q_reg[2]),
.I5(Q_reg[8]),
.O(\rd_pntr_bin_reg[7] [0]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[1]_i_1
(.I0(\rd_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[3]),
.I2(Q_reg[2]),
.I3(Q_reg[8]),
.I4(Q_reg[1]),
.O(\rd_pntr_bin_reg[7] [1]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[2]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[2]),
.I2(Q_reg[3]),
.I3(\rd_pntr_bin[2]_i_2_n_0 ),
.O(\rd_pntr_bin_reg[7] [2]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[2]_i_2
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[5]),
.I3(Q_reg[4]),
.O(\rd_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[3]_i_1
(.I0(Q_reg[5]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(Q_reg[8]),
.I4(Q_reg[6]),
.I5(Q_reg[7]),
.O(\rd_pntr_bin_reg[7] [3]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[8]),
.I4(Q_reg[7]),
.O(\rd_pntr_bin_reg[7] [4]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[5]),
.I2(Q_reg[8]),
.I3(Q_reg[7]),
.O(\rd_pntr_bin_reg[7] [5]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[8]),
.O(\rd_pntr_bin_reg[7] [6]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[7]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[8]),
.O(\rd_pntr_bin_reg[7] [7]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module shd_fifo_wr_bin_cntr
(ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
Q,
\gic0.gc0.count_d2_reg[7]_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
RD_PNTR_WR,
E,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output ram_full_fb_i_reg;
output ram_full_fb_i_reg_0;
output [7:0]Q;
output [7:0]\gic0.gc0.count_d2_reg[7]_0 ;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
input [0:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [0:0]RD_PNTR_WR;
wire \gic0.gc0.count[8]_i_2_n_0 ;
wire [7:0]\gic0.gc0.count_d2_reg[7]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [8:8]p_12_out;
wire [8:0]plusOp__0;
wire ram_full_fb_i_reg;
wire ram_full_fb_i_reg_0;
wire wr_clk;
wire [8:8]wr_pntr_plus2;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h6A))
\gic0.gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gic0.gc0.count[4]_i_1
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gic0.gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[0]),
.I4(Q[1]),
.I5(Q[4]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h6AAA))
\gic0.gc0.count[6]_i_1
(.I0(Q[6]),
.I1(Q[4]),
.I2(\gic0.gc0.count[8]_i_2_n_0 ),
.I3(Q[5]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gic0.gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gic0.gc0.count[8]_i_2_n_0 ),
.I3(Q[4]),
.I4(Q[6]),
.O(plusOp__0[7]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gic0.gc0.count[8]_i_1
(.I0(wr_pntr_plus2),
.I1(Q[6]),
.I2(Q[4]),
.I3(\gic0.gc0.count[8]_i_2_n_0 ),
.I4(Q[5]),
.I5(Q[7]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h8000))
\gic0.gc0.count[8]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(\gic0.gc0.count[8]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(Q[0]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(\gic0.gc0.count_d2_reg[7]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[4]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[5]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[6]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[7]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2),
.Q(p_12_out));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[8]),
.Q(wr_pntr_plus2));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out),
.I1(RD_PNTR_WR),
.O(ram_full_fb_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__2
(.I0(wr_pntr_plus2),
.I1(RD_PNTR_WR),
.O(ram_full_fb_i_reg_0));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module shd_fifo_wr_logic
(full,
Q,
\gic0.gc0.count_d1_reg[7] ,
E,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg,
v1_reg_0,
wr_clk,
rst_full_ff_i,
RD_PNTR_WR,
wr_en,
rst_full_gen_i,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output full;
output [7:0]Q;
output [7:0]\gic0.gc0.count_d1_reg[7] ;
output [0:0]E;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
input [3:0]v1_reg;
input [3:0]v1_reg_0;
input wr_clk;
input rst_full_ff_i;
input [0:0]RD_PNTR_WR;
input wr_en;
input rst_full_gen_i;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [0:0]RD_PNTR_WR;
wire full;
wire [7:0]\gic0.gc0.count_d1_reg[7] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire wpntr_n_0;
wire wpntr_n_1;
wire wr_clk;
wire wr_en;
shd_fifo_wr_status_flags_as \gwas.wsts
(.E(E),
.full(full),
.\gic0.gc0.count_d1_reg[8] (wpntr_n_0),
.\gic0.gc0.count_reg[8] (wpntr_n_1),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_fifo_wr_bin_cntr wpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ),
.E(E),
.Q(\gic0.gc0.count_d1_reg[7] ),
.RD_PNTR_WR(RD_PNTR_WR),
.\gic0.gc0.count_d2_reg[7]_0 (Q),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.ram_full_fb_i_reg(wpntr_n_0),
.ram_full_fb_i_reg_0(wpntr_n_1),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module shd_fifo_wr_status_flags_as
(full,
E,
v1_reg,
\gic0.gc0.count_d1_reg[8] ,
v1_reg_0,
\gic0.gc0.count_reg[8] ,
wr_clk,
rst_full_ff_i,
wr_en,
rst_full_gen_i);
output full;
output [0:0]E;
input [3:0]v1_reg;
input \gic0.gc0.count_d1_reg[8] ;
input [3:0]v1_reg_0;
input \gic0.gc0.count_reg[8] ;
input wr_clk;
input rst_full_ff_i;
input wr_en;
input rst_full_gen_i;
wire [0:0]E;
wire comp1;
wire full;
wire \gic0.gc0.count_d1_reg[8] ;
wire \gic0.gc0.count_reg[8] ;
wire p_0_out;
wire ram_full_i;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2
(.I0(wr_en),
.I1(p_0_out),
.O(E));
shd_fifo_compare c1
(.comp1(comp1),
.\gic0.gc0.count_d1_reg[8] (\gic0.gc0.count_d1_reg[8] ),
.v1_reg(v1_reg));
shd_fifo_compare_0 c2
(.comp1(comp1),
.\gic0.gc0.count_reg[8] (\gic0.gc0.count_reg[8] ),
.p_0_out(p_0_out),
.ram_full_i(ram_full_i),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg_0(v1_reg_0),
.wr_en(wr_en));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(p_0_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_BLACKBOX_V
|
/* this file automatically generated by make_wp.py script
* for file ../net_2core2dr_copy.v
* for module ictlb
* with the instance name ictlb_dut
*/
// FIXME:
//
// Any l2 cache pipe can go to any directory (and viceversa). The reason is to
// allow a per bank SMT option (dc_pipe and l2_pipe) and to handle the TLB
// misses that can go out of bank.
//
// Effectively, a 4 pipe dual core can switch to a 8 independent l2 coherent
// cores. No need to have a switch command as the DCs and L2s are coherent.
`include "scmem.vh"
module net_2core2dr_wp(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input logic clk
,input logic reset
// c0 core L2I
,input logic c0_l2itodr_req_valid
,output logic c0_l2itodr_req_retry
// ,input I_l2todr_req_type c0_l2itodr_req
,input SC_nodeid_type c0_l2itodr_req_nid
,input L2_reqid_type c0_l2itodr_req_l2id
,input SC_cmd_type c0_l2itodr_req_cmd
,input SC_paddr_type c0_l2itodr_req_paddr
,output logic c0_drtol2i_snack_valid
,input logic c0_drtol2i_snack_retry
// ,output I_drtol2_snack_type c0_drtol2i_snack
,output SC_nodeid_type c0_drtol2i_snack_nid
,output L2_reqid_type c0_drtol2i_snack_l2id
,output DR_reqid_type c0_drtol2i_snack_drid
,output SC_snack_type c0_drtol2i_snack_snack
,output SC_line_type c0_drtol2i_snack_line
,output SC_paddr_type c0_drtol2i_snack_paddr
,input logic c0_l2itodr_snoop_ack_valid
,output logic c0_l2itodr_snoop_ack_retry
// ,input I_l2snoop_ack_type c0_l2itodr_snoop_ack
,input L2_reqid_type c0_l2itodr_snoop_ack_l2id
,input DR_ndirs_type c0_l2itodr_snoop_ack_directory_id
,input logic c0_l2itodr_disp_valid
,output logic c0_l2itodr_disp_retry
// ,input I_l2todr_disp_type c0_l2itodr_disp
,input SC_nodeid_type c0_l2itodr_disp_nid
,input L2_reqid_type c0_l2itodr_disp_l2id
,input DR_reqid_type c0_l2itodr_disp_drid
,input SC_disp_mask_type c0_l2itodr_disp_mask
,input SC_dcmd_type c0_l2itodr_disp_dcmd
,input SC_line_type c0_l2itodr_disp_line
,input SC_paddr_type c0_l2itodr_disp_paddr
,output logic c0_drtol2i_dack_valid
,input logic c0_drtol2i_dack_retry
// ,output I_drtol2_dack_type c0_drtol2i_dack
,output SC_nodeid_type c0_drtol2i_dack_nid
,output L2_reqid_type c0_drtol2i_dack_l2id
,input logic c0_l2itodr_pfreq_valid
,output logic c0_l2itodr_pfreq_retry
// ,input I_l2todr_pfreq_type c0_l2itodr_pfreq
,input SC_nodeid_type c0_l2itodr_pfreq_nid
,input SC_paddr_type c0_l2itodr_pfreq_paddr
// c0 core L2I TLB
,input logic c0_l2ittodr_req_valid
,output logic c0_l2ittodr_req_retry
// ,input I_l2todr_req_type c0_l2ittodr_req
,input SC_nodeid_type c0_l2ittodr_req_nid
,input L2_reqid_type c0_l2ittodr_req_l2id
,input SC_cmd_type c0_l2ittodr_req_cmd
,input SC_paddr_type c0_l2ittodr_req_paddr
,output logic c0_drtol2it_snack_valid
,input logic c0_drtol2it_snack_retry
// ,output I_drtol2_snack_type c0_drtol2it_snack
,output SC_nodeid_type c0_drtol2it_snack_nid
,output L2_reqid_type c0_drtol2it_snack_l2id
,output DR_reqid_type c0_drtol2it_snack_drid
,output SC_snack_type c0_drtol2it_snack_snack
,output SC_line_type c0_drtol2it_snack_line
,output SC_paddr_type c0_drtol2it_snack_paddr
,input logic c0_l2ittodr_snoop_ack_valid
,output logic c0_l2ittodr_snoop_ack_retry
// ,input I_l2snoop_ack_type c0_l2ittodr_snoop_ack
,input L2_reqid_type c0_l2ittodr_snoop_ack_l2id
,input DR_ndirs_type c0_l2ittodr_snoop_ack_directory_id
,input logic c0_l2ittodr_disp_valid
,output logic c0_l2ittodr_disp_retry
// ,input I_l2todr_disp_type c0_l2ittodr_disp
,input SC_nodeid_type c0_l2ittodr_disp_nid
,input L2_reqid_type c0_l2ittodr_disp_l2id
,input DR_reqid_type c0_l2ittodr_disp_drid
,input SC_disp_mask_type c0_l2ittodr_disp_mask
,input SC_dcmd_type c0_l2ittodr_disp_dcmd
,input SC_line_type c0_l2ittodr_disp_line
,input SC_paddr_type c0_l2ittodr_disp_paddr
,output logic c0_drtol2it_dack_valid
,input logic c0_drtol2it_dack_retry
// ,output I_drtol2_dack_type c0_drtol2it_dack
,output SC_nodeid_type c0_drtol2it_dack_nid
,output L2_reqid_type c0_drtol2it_dack_l2id
// c0 core L2D
,input logic c0_l2d_0todr_req_valid
,output logic c0_l2d_0todr_req_retry
// ,input I_l2todr_req_type c0_l2d_0todr_req
,input SC_nodeid_type c0_l2d_0todr_req_nid
,input L2_reqid_type c0_l2d_0todr_req_l2id
,input SC_cmd_type c0_l2d_0todr_req_cmd
,input SC_paddr_type c0_l2d_0todr_req_paddr
,output logic c0_drtol2d_0_snack_valid
,input logic c0_drtol2d_0_snack_retry
// ,output I_drtol2_snack_type c0_drtol2d_0_snack
,output SC_nodeid_type c0_drtol2d_0_snack_nid
,output L2_reqid_type c0_drtol2d_0_snack_l2id
,output DR_reqid_type c0_drtol2d_0_snack_drid
,output SC_snack_type c0_drtol2d_0_snack_snack
,output SC_line_type c0_drtol2d_0_snack_line
,output SC_paddr_type c0_drtol2d_0_snack_paddr
,input logic c0_l2d_0todr_snoop_ack_valid
,output logic c0_l2d_0todr_snoop_ack_retry
// ,input I_l2snoop_ack_type c0_l2d_0todr_snoop_ack
,input L2_reqid_type c0_l2d_0todr_snoop_ack_l2id
,input DR_ndirs_type c0_l2d_0todr_snoop_ack_directory_id
,input logic c0_l2d_0todr_disp_valid
,output logic c0_l2d_0todr_disp_retry
// ,input I_l2todr_disp_type c0_l2d_0todr_disp
,input SC_nodeid_type c0_l2d_0todr_disp_nid
,input L2_reqid_type c0_l2d_0todr_disp_l2id
,input DR_reqid_type c0_l2d_0todr_disp_drid
,input SC_disp_mask_type c0_l2d_0todr_disp_mask
,input SC_dcmd_type c0_l2d_0todr_disp_dcmd
,input SC_line_type c0_l2d_0todr_disp_line
,input SC_paddr_type c0_l2d_0todr_disp_paddr
,output logic c0_drtol2d_0_dack_valid
,input logic c0_drtol2d_0_dack_retry
// ,output I_drtol2_dack_type c0_drtol2d_0_dack
,output SC_nodeid_type c0_drtol2d_0_dack_nid
,output L2_reqid_type c0_drtol2d_0_dack_l2id
,input logic c0_l2d_0todr_pfreq_valid
,output logic c0_l2d_0todr_pfreq_retry
// ,input I_l2todr_pfreq_type c0_l2d_0todr_pfreq
,input SC_nodeid_type c0_l2d_0todr_pfreq_nid
,input SC_paddr_type c0_l2d_0todr_pfreq_paddr
// c0 core L2D TLB
,input logic c0_l2dt_0todr_req_valid
,output logic c0_l2dt_0todr_req_retry
// ,input I_l2todr_req_type c0_l2dt_0todr_req
,input SC_nodeid_type c0_l2dt_0todr_req_nid
,input L2_reqid_type c0_l2dt_0todr_req_l2id
,input SC_cmd_type c0_l2dt_0todr_req_cmd
,input SC_paddr_type c0_l2dt_0todr_req_paddr
,output logic c0_drtol2dt_0_snack_valid
,input logic c0_drtol2dt_0_snack_retry
// ,output I_drtol2_snack_type c0_drtol2dt_0_snack
,output SC_nodeid_type c0_drtol2dt_0_snack_nid
,output L2_reqid_type c0_drtol2dt_0_snack_l2id
,output DR_reqid_type c0_drtol2dt_0_snack_drid
,output SC_snack_type c0_drtol2dt_0_snack_snack
,output SC_line_type c0_drtol2dt_0_snack_line
,output SC_paddr_type c0_drtol2dt_0_snack_paddr
,input logic c0_l2dt_0todr_snoop_ack_valid
,output logic c0_l2dt_0todr_snoop_ack_retry
// ,input I_l2snoop_ack_type c0_l2dt_0todr_snoop_ack
,input L2_reqid_type c0_l2dt_0todr_snoop_ack_l2id
,input DR_ndirs_type c0_l2dt_0todr_snoop_ack_directory_id
,input logic c0_l2dt_0todr_disp_valid
,output logic c0_l2dt_0todr_disp_retry
// ,input I_l2todr_disp_type c0_l2dt_0todr_disp
,input SC_nodeid_type c0_l2dt_0todr_disp_nid
,input L2_reqid_type c0_l2dt_0todr_disp_l2id
,input DR_reqid_type c0_l2dt_0todr_disp_drid
,input SC_disp_mask_type c0_l2dt_0todr_disp_mask
,input SC_dcmd_type c0_l2dt_0todr_disp_dcmd
,input SC_line_type c0_l2dt_0todr_disp_line
,input SC_paddr_type c0_l2dt_0todr_disp_paddr
,output logic c0_drtol2dt_0_dack_valid
,input logic c0_drtol2dt_0_dack_retry
// ,output I_drtol2_dack_type c0_drtol2dt_0_dack
,output SC_nodeid_type c0_drtol2dt_0_dack_nid
,output L2_reqid_type c0_drtol2dt_0_dack_l2id
// c1 core L2I
,input logic c1_l2itodr_req_valid
,output logic c1_l2itodr_req_retry
// ,input I_l2todr_req_type c1_l2itodr_req
,input SC_nodeid_type c1_l2itodr_req_nid
,input L2_reqid_type c1_l2itodr_req_l2id
,input SC_cmd_type c1_l2itodr_req_cmd
,input SC_paddr_type c1_l2itodr_req_paddr
,output logic c1_drtol2i_snack_valid
,input logic c1_drtol2i_snack_retry
// ,output I_drtol2_snack_type c1_drtol2i_snack
,output SC_nodeid_type c1_drtol2i_snack_nid
,output L2_reqid_type c1_drtol2i_snack_l2id
,output DR_reqid_type c1_drtol2i_snack_drid
,output SC_snack_type c1_drtol2i_snack_snack
,output SC_line_type c1_drtol2i_snack_line
,output SC_paddr_type c1_drtol2i_snack_paddr
,input logic c1_l2itodr_snoop_ack_valid
,output logic c1_l2itodr_snoop_ack_retry
// ,input I_l2snoop_ack_type c1_l2itodr_snoop_ack
,input L2_reqid_type c1_l2itodr_snoop_ack_l2id
,input DR_ndirs_type c1_l2itodr_snoop_ack_directory_id
,input logic c1_l2itodr_disp_valid
,output logic c1_l2itodr_disp_retry
// ,input I_l2todr_disp_type c1_l2itodr_disp
,input SC_nodeid_type c1_l2itodr_disp_nid
,input L2_reqid_type c1_l2itodr_disp_l2id
,input DR_reqid_type c1_l2itodr_disp_drid
,input SC_disp_mask_type c1_l2itodr_disp_mask
,input SC_dcmd_type c1_l2itodr_disp_dcmd
,input SC_line_type c1_l2itodr_disp_line
,input SC_paddr_type c1_l2itodr_disp_paddr
,output logic c1_drtol2i_dack_valid
,input logic c1_drtol2i_dack_retry
// ,output I_drtol2_dack_type c1_drtol2i_dack
,output SC_nodeid_type c1_drtol2i_dack_nid
,output L2_reqid_type c1_drtol2i_dack_l2id
,input logic c1_l2itodr_pfreq_valid
,output logic c1_l2itodr_pfreq_retry
// ,input I_l2todr_pfreq_type c1_l2itodr_pfreq
,input SC_nodeid_type c1_l2itodr_pfreq_nid
,input SC_paddr_type c1_l2itodr_pfreq_paddr
// c1 core L2I TLB
,input logic c1_l2ittodr_req_valid
,output logic c1_l2ittodr_req_retry
// ,input I_l2todr_req_type c1_l2ittodr_req
,input SC_nodeid_type c1_l2ittodr_req_nid
,input L2_reqid_type c1_l2ittodr_req_l2id
,input SC_cmd_type c1_l2ittodr_req_cmd
,input SC_paddr_type c1_l2ittodr_req_paddr
,output logic c1_drtol2it_snack_valid
,input logic c1_drtol2it_snack_retry
// ,output I_drtol2_snack_type c1_drtol2it_snack
,output SC_nodeid_type c1_drtol2it_snack_nid
,output L2_reqid_type c1_drtol2it_snack_l2id
,output DR_reqid_type c1_drtol2it_snack_drid
,output SC_snack_type c1_drtol2it_snack_snack
,output SC_line_type c1_drtol2it_snack_line
,output SC_paddr_type c1_drtol2it_snack_paddr
,input logic c1_l2ittodr_snoop_ack_valid
,output logic c1_l2ittodr_snoop_ack_retry
// ,input I_l2snoop_ack_type c1_l2ittodr_snoop_ack
,input L2_reqid_type c1_l2ittodr_snoop_ack_l2id
,input DR_ndirs_type c1_l2ittodr_snoop_ack_directory_id
,input logic c1_l2ittodr_disp_valid
,output logic c1_l2ittodr_disp_retry
// ,input I_l2todr_disp_type c1_l2ittodr_disp
,input SC_nodeid_type c1_l2ittodr_disp_nid
,input L2_reqid_type c1_l2ittodr_disp_l2id
,input DR_reqid_type c1_l2ittodr_disp_drid
,input SC_disp_mask_type c1_l2ittodr_disp_mask
,input SC_dcmd_type c1_l2ittodr_disp_dcmd
,input SC_line_type c1_l2ittodr_disp_line
,input SC_paddr_type c1_l2ittodr_disp_paddr
,output logic c1_drtol2it_dack_valid
,input logic c1_drtol2it_dack_retry
// ,output I_drtol2_dack_type c1_drtol2it_dack
,output SC_nodeid_type c1_drtol2it_dack_nid
,output L2_reqid_type c1_drtol2it_dack_l2id
// c1 core L2D
,input logic c1_l2d_0todr_req_valid
,output logic c1_l2d_0todr_req_retry
// ,input I_l2todr_req_type c1_l2d_0todr_req
,input SC_nodeid_type c1_l2d_0todr_req_nid
,input L2_reqid_type c1_l2d_0todr_req_l2id
,input SC_cmd_type c1_l2d_0todr_req_cmd
,input SC_paddr_type c1_l2d_0todr_req_paddr
,output logic c1_drtol2d_0_snack_valid
,input logic c1_drtol2d_0_snack_retry
// ,output I_drtol2_snack_type c1_drtol2d_0_snack
,output SC_nodeid_type c1_drtol2d_0_snack_nid
,output L2_reqid_type c1_drtol2d_0_snack_l2id
,output DR_reqid_type c1_drtol2d_0_snack_drid
,output SC_snack_type c1_drtol2d_0_snack_snack
,output SC_line_type c1_drtol2d_0_snack_line
,output SC_paddr_type c1_drtol2d_0_snack_paddr
,input logic c1_l2d_0todr_snoop_ack_valid
,output logic c1_l2d_0todr_snoop_ack_retry
// ,input I_l2snoop_ack_type c1_l2d_0todr_snoop_ack
,input L2_reqid_type c1_l2d_0todr_snoop_ack_l2id
,input DR_ndirs_type c1_l2d_0todr_snoop_ack_directory_id
,input logic c1_l2d_0todr_disp_valid
,output logic c1_l2d_0todr_disp_retry
// ,input I_l2todr_disp_type c1_l2d_0todr_disp
,input SC_nodeid_type c1_l2d_0todr_disp_nid
,input L2_reqid_type c1_l2d_0todr_disp_l2id
,input DR_reqid_type c1_l2d_0todr_disp_drid
,input SC_disp_mask_type c1_l2d_0todr_disp_mask
,input SC_dcmd_type c1_l2d_0todr_disp_dcmd
,input SC_line_type c1_l2d_0todr_disp_line
,input SC_paddr_type c1_l2d_0todr_disp_paddr
,output logic c1_drtol2d_0_dack_valid
,input logic c1_drtol2d_0_dack_retry
// ,output I_drtol2_dack_type c1_drtol2d_0_dack
,output SC_nodeid_type c1_drtol2d_0_dack_nid
,output L2_reqid_type c1_drtol2d_0_dack_l2id
,input logic c1_l2d_0todr_pfreq_valid
,output logic c1_l2d_0todr_pfreq_retry
// ,input I_l2todr_pfreq_type c1_l2d_0todr_pfreq
,input SC_nodeid_type c1_l2d_0todr_pfreq_nid
,input SC_paddr_type c1_l2d_0todr_pfreq_paddr
// c1 core L2D TLB
,input logic c1_l2dt_0todr_req_valid
,output logic c1_l2dt_0todr_req_retry
// ,input I_l2todr_req_type c1_l2dt_0todr_req
,input SC_nodeid_type c1_l2dt_0todr_req_nid
,input L2_reqid_type c1_l2dt_0todr_req_l2id
,input SC_cmd_type c1_l2dt_0todr_req_cmd
,input SC_paddr_type c1_l2dt_0todr_req_paddr
,output logic c1_drtol2dt_0_snack_valid
,input logic c1_drtol2dt_0_snack_retry
// ,output I_drtol2_snack_type c1_drtol2dt_0_snack
,output SC_nodeid_type c1_drtol2dt_0_snack_nid
,output L2_reqid_type c1_drtol2dt_0_snack_l2id
,output DR_reqid_type c1_drtol2dt_0_snack_drid
,output SC_snack_type c1_drtol2dt_0_snack_snack
,output SC_line_type c1_drtol2dt_0_snack_line
,output SC_paddr_type c1_drtol2dt_0_snack_paddr
,input logic c1_l2dt_0todr_snoop_ack_valid
,output logic c1_l2dt_0todr_snoop_ack_retry
// ,input I_l2snoop_ack_type c1_l2dt_0todr_snoop_ack
,input L2_reqid_type c1_l2dt_0todr_snoop_ack_l2id
,input DR_ndirs_type c1_l2dt_0todr_snoop_ack_directory_id
,input logic c1_l2dt_0todr_disp_valid
,output logic c1_l2dt_0todr_disp_retry
// ,input I_l2todr_disp_type c1_l2dt_0todr_disp
,input SC_nodeid_type c1_l2dt_0todr_disp_nid
,input L2_reqid_type c1_l2dt_0todr_disp_l2id
,input DR_reqid_type c1_l2dt_0todr_disp_drid
,input SC_disp_mask_type c1_l2dt_0todr_disp_mask
,input SC_dcmd_type c1_l2dt_0todr_disp_dcmd
,input SC_line_type c1_l2dt_0todr_disp_line
,input SC_paddr_type c1_l2dt_0todr_disp_paddr
,output logic c1_drtol2dt_0_dack_valid
,input logic c1_drtol2dt_0_dack_retry
// ,output I_drtol2_dack_type c1_drtol2dt_0_dack
,output SC_nodeid_type c1_drtol2dt_0_dack_nid
,output L2_reqid_type c1_drtol2dt_0_dack_l2id
// directory 0
,output logic l2todr0_req_valid
,input logic l2todr0_req_retry
// ,output I_l2todr_req_type l2todr0_req
,output SC_nodeid_type l2todr0_req_nid
,output L2_reqid_type l2todr0_req_l2id
,output SC_cmd_type l2todr0_req_cmd
,output SC_paddr_type l2todr0_req_paddr
,input logic dr0tol2_snack_valid
,output logic dr0tol2_snack_retry
// ,input I_drtol2_snack_type dr0tol2_snack
,input SC_nodeid_type dr0tol2_snack_nid
,input L2_reqid_type dr0tol2_snack_l2id
,input DR_reqid_type dr0tol2_snack_drid
,input SC_snack_type dr0tol2_snack_snack
,input SC_line_type dr0tol2_snack_line
,input SC_paddr_type dr0tol2_snack_paddr
,output logic l2todr0_disp_valid
,input logic l2todr0_disp_retry
// ,output I_l2todr_disp_type l2todr0_disp
,output SC_nodeid_type l2todr0_disp_nid
,output L2_reqid_type l2todr0_disp_l2id
,output DR_reqid_type l2todr0_disp_drid
,output SC_disp_mask_type l2todr0_disp_mask
,output SC_dcmd_type l2todr0_disp_dcmd
,output SC_line_type l2todr0_disp_line
,output SC_paddr_type l2todr0_disp_paddr
,input logic dr0tol2_dack_valid
,output logic dr0tol2_dack_retry
// ,input I_drtol2_dack_type dr0tol2_dack
,input SC_nodeid_type dr0tol2_dack_nid
,input L2_reqid_type dr0tol2_dack_l2id
,output logic l2todr0_snoop_ack_valid
,input logic l2todr0_snoop_ack_retry
// ,output I_drsnoop_ack_type l2todr0_snoop_ack
,output DR_reqid_type l2todr0_snoop_ack_drid
,output logic l2todr0_pfreq_valid
,input logic l2todr0_pfreq_retry
// ,output I_l2todr_pfreq_type l2todr0_pfreq
,output SC_nodeid_type l2todr0_pfreq_nid
,output SC_paddr_type l2todr0_pfreq_paddr
// directory 1
,output logic l2todr1_req_valid
,input logic l2todr1_req_retry
// ,output I_l2todr_req_type l2todr1_req
,output SC_nodeid_type l2todr1_req_nid
,output L2_reqid_type l2todr1_req_l2id
,output SC_cmd_type l2todr1_req_cmd
,output SC_paddr_type l2todr1_req_paddr
,input logic dr1tol2_snack_valid
,output logic dr1tol2_snack_retry
// ,input I_drtol2_snack_type dr1tol2_snack
,input SC_nodeid_type dr1tol2_snack_nid
,input L2_reqid_type dr1tol2_snack_l2id
,input DR_reqid_type dr1tol2_snack_drid
,input SC_snack_type dr1tol2_snack_snack
,input SC_line_type dr1tol2_snack_line
,input SC_paddr_type dr1tol2_snack_paddr
,output logic l2todr1_disp_valid
,input logic l2todr1_disp_retry
// ,output I_l2todr_disp_type l2todr1_disp
,output SC_nodeid_type l2todr1_disp_nid
,output L2_reqid_type l2todr1_disp_l2id
,output DR_reqid_type l2todr1_disp_drid
,output SC_disp_mask_type l2todr1_disp_mask
,output SC_dcmd_type l2todr1_disp_dcmd
,output SC_line_type l2todr1_disp_line
,output SC_paddr_type l2todr1_disp_paddr
,input logic dr1tol2_dack_valid
,output logic dr1tol2_dack_retry
// ,input I_drtol2_dack_type dr1tol2_dack
,input SC_nodeid_type dr1tol2_dack_nid
,input L2_reqid_type dr1tol2_dack_l2id
,output logic l2todr1_snoop_ack_valid
,input logic l2todr1_snoop_ack_retry
// ,output I_drsnoop_ack_type l2todr1_snoop_ack
,output DR_reqid_type l2todr1_snoop_ack_drid
,output logic l2todr1_pfreq_valid
,input logic l2todr1_pfreq_retry
// ,output I_l2todr_pfreq_type l2todr1_pfreq
,output SC_nodeid_type l2todr1_pfreq_nid
,output SC_paddr_type l2todr1_pfreq_paddr
/* verilator lint_on UNUSED */
/* verilator lint_on UNDRIVEN */
);
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
I_l2todr_req_type c0_l2itodr_req;
assign c0_l2itodr_req.nid = c0_l2itodr_req_nid;
assign c0_l2itodr_req.l2id = c0_l2itodr_req_l2id;
assign c0_l2itodr_req.cmd = c0_l2itodr_req_cmd;
assign c0_l2itodr_req.paddr = c0_l2itodr_req_paddr;
I_drtol2_snack_type c0_drtol2i_snack;
assign c0_drtol2i_snack_nid = c0_drtol2i_snack.nid;
assign c0_drtol2i_snack_l2id = c0_drtol2i_snack.l2id;
assign c0_drtol2i_snack_drid = c0_drtol2i_snack.drid;
assign c0_drtol2i_snack_snack = c0_drtol2i_snack.snack;
assign c0_drtol2i_snack_line = c0_drtol2i_snack.line;
assign c0_drtol2i_snack_paddr = c0_drtol2i_snack.paddr;
I_l2snoop_ack_type c0_l2itodr_snoop_ack;
assign c0_l2itodr_snoop_ack.l2id = c0_l2itodr_snoop_ack_l2id;
assign c0_l2itodr_snoop_ack.directory_id = c0_l2itodr_snoop_ack_directory_id;
I_l2todr_disp_type c0_l2itodr_disp;
assign c0_l2itodr_disp.nid = c0_l2itodr_disp_nid;
assign c0_l2itodr_disp.l2id = c0_l2itodr_disp_l2id;
assign c0_l2itodr_disp.drid = c0_l2itodr_disp_drid;
assign c0_l2itodr_disp.mask = c0_l2itodr_disp_mask;
assign c0_l2itodr_disp.dcmd = c0_l2itodr_disp_dcmd;
assign c0_l2itodr_disp.line = c0_l2itodr_disp_line;
assign c0_l2itodr_disp.paddr = c0_l2itodr_disp_paddr;
I_drtol2_dack_type c0_drtol2i_dack;
assign c0_drtol2i_dack_nid = c0_drtol2i_dack.nid;
assign c0_drtol2i_dack_l2id = c0_drtol2i_dack.l2id;
I_l2todr_pfreq_type c0_l2itodr_pfreq;
assign c0_l2itodr_pfreq.nid = c0_l2itodr_pfreq_nid;
assign c0_l2itodr_pfreq.paddr = c0_l2itodr_pfreq_paddr;
I_l2todr_req_type c0_l2ittodr_req;
assign c0_l2ittodr_req.nid = c0_l2ittodr_req_nid;
assign c0_l2ittodr_req.l2id = c0_l2ittodr_req_l2id;
assign c0_l2ittodr_req.cmd = c0_l2ittodr_req_cmd;
assign c0_l2ittodr_req.paddr = c0_l2ittodr_req_paddr;
I_drtol2_snack_type c0_drtol2it_snack;
assign c0_drtol2it_snack_nid = c0_drtol2it_snack.nid;
assign c0_drtol2it_snack_l2id = c0_drtol2it_snack.l2id;
assign c0_drtol2it_snack_drid = c0_drtol2it_snack.drid;
assign c0_drtol2it_snack_snack = c0_drtol2it_snack.snack;
assign c0_drtol2it_snack_line = c0_drtol2it_snack.line;
assign c0_drtol2it_snack_paddr = c0_drtol2it_snack.paddr;
I_l2snoop_ack_type c0_l2ittodr_snoop_ack;
assign c0_l2ittodr_snoop_ack.l2id = c0_l2ittodr_snoop_ack_l2id;
assign c0_l2ittodr_snoop_ack.directory_id = c0_l2ittodr_snoop_ack_directory_id;
I_l2todr_disp_type c0_l2ittodr_disp;
assign c0_l2ittodr_disp.nid = c0_l2ittodr_disp_nid;
assign c0_l2ittodr_disp.l2id = c0_l2ittodr_disp_l2id;
assign c0_l2ittodr_disp.drid = c0_l2ittodr_disp_drid;
assign c0_l2ittodr_disp.mask = c0_l2ittodr_disp_mask;
assign c0_l2ittodr_disp.dcmd = c0_l2ittodr_disp_dcmd;
assign c0_l2ittodr_disp.line = c0_l2ittodr_disp_line;
assign c0_l2ittodr_disp.paddr = c0_l2ittodr_disp_paddr;
I_drtol2_dack_type c0_drtol2it_dack;
assign c0_drtol2it_dack_nid = c0_drtol2it_dack.nid;
assign c0_drtol2it_dack_l2id = c0_drtol2it_dack.l2id;
I_l2todr_req_type c0_l2d_0todr_req;
assign c0_l2d_0todr_req.nid = c0_l2d_0todr_req_nid;
assign c0_l2d_0todr_req.l2id = c0_l2d_0todr_req_l2id;
assign c0_l2d_0todr_req.cmd = c0_l2d_0todr_req_cmd;
assign c0_l2d_0todr_req.paddr = c0_l2d_0todr_req_paddr;
I_drtol2_snack_type c0_drtol2d_0_snack;
assign c0_drtol2d_0_snack_nid = c0_drtol2d_0_snack.nid;
assign c0_drtol2d_0_snack_l2id = c0_drtol2d_0_snack.l2id;
assign c0_drtol2d_0_snack_drid = c0_drtol2d_0_snack.drid;
assign c0_drtol2d_0_snack_snack = c0_drtol2d_0_snack.snack;
assign c0_drtol2d_0_snack_line = c0_drtol2d_0_snack.line;
assign c0_drtol2d_0_snack_paddr = c0_drtol2d_0_snack.paddr;
I_l2snoop_ack_type c0_l2d_0todr_snoop_ack;
assign c0_l2d_0todr_snoop_ack.l2id = c0_l2d_0todr_snoop_ack_l2id;
assign c0_l2d_0todr_snoop_ack.directory_id = c0_l2d_0todr_snoop_ack_directory_id;
I_l2todr_disp_type c0_l2d_0todr_disp;
assign c0_l2d_0todr_disp.nid = c0_l2d_0todr_disp_nid;
assign c0_l2d_0todr_disp.l2id = c0_l2d_0todr_disp_l2id;
assign c0_l2d_0todr_disp.drid = c0_l2d_0todr_disp_drid;
assign c0_l2d_0todr_disp.mask = c0_l2d_0todr_disp_mask;
assign c0_l2d_0todr_disp.dcmd = c0_l2d_0todr_disp_dcmd;
assign c0_l2d_0todr_disp.line = c0_l2d_0todr_disp_line;
assign c0_l2d_0todr_disp.paddr = c0_l2d_0todr_disp_paddr;
I_drtol2_dack_type c0_drtol2d_0_dack;
assign c0_drtol2d_0_dack_nid = c0_drtol2d_0_dack.nid;
assign c0_drtol2d_0_dack_l2id = c0_drtol2d_0_dack.l2id;
I_l2todr_pfreq_type c0_l2d_0todr_pfreq;
assign c0_l2d_0todr_pfreq.nid = c0_l2d_0todr_pfreq_nid;
assign c0_l2d_0todr_pfreq.paddr = c0_l2d_0todr_pfreq_paddr;
I_l2todr_req_type c0_l2dt_0todr_req;
assign c0_l2dt_0todr_req.nid = c0_l2dt_0todr_req_nid;
assign c0_l2dt_0todr_req.l2id = c0_l2dt_0todr_req_l2id;
assign c0_l2dt_0todr_req.cmd = c0_l2dt_0todr_req_cmd;
assign c0_l2dt_0todr_req.paddr = c0_l2dt_0todr_req_paddr;
I_drtol2_snack_type c0_drtol2dt_0_snack;
assign c0_drtol2dt_0_snack_nid = c0_drtol2dt_0_snack.nid;
assign c0_drtol2dt_0_snack_l2id = c0_drtol2dt_0_snack.l2id;
assign c0_drtol2dt_0_snack_drid = c0_drtol2dt_0_snack.drid;
assign c0_drtol2dt_0_snack_snack = c0_drtol2dt_0_snack.snack;
assign c0_drtol2dt_0_snack_line = c0_drtol2dt_0_snack.line;
assign c0_drtol2dt_0_snack_paddr = c0_drtol2dt_0_snack.paddr;
I_l2snoop_ack_type c0_l2dt_0todr_snoop_ack;
assign c0_l2dt_0todr_snoop_ack.l2id = c0_l2dt_0todr_snoop_ack_l2id;
assign c0_l2dt_0todr_snoop_ack.directory_id = c0_l2dt_0todr_snoop_ack_directory_id;
I_l2todr_disp_type c0_l2dt_0todr_disp;
assign c0_l2dt_0todr_disp.nid = c0_l2dt_0todr_disp_nid;
assign c0_l2dt_0todr_disp.l2id = c0_l2dt_0todr_disp_l2id;
assign c0_l2dt_0todr_disp.drid = c0_l2dt_0todr_disp_drid;
assign c0_l2dt_0todr_disp.mask = c0_l2dt_0todr_disp_mask;
assign c0_l2dt_0todr_disp.dcmd = c0_l2dt_0todr_disp_dcmd;
assign c0_l2dt_0todr_disp.line = c0_l2dt_0todr_disp_line;
assign c0_l2dt_0todr_disp.paddr = c0_l2dt_0todr_disp_paddr;
I_drtol2_dack_type c0_drtol2dt_0_dack;
assign c0_drtol2dt_0_dack_nid = c0_drtol2dt_0_dack.nid;
assign c0_drtol2dt_0_dack_l2id = c0_drtol2dt_0_dack.l2id;
I_l2todr_req_type c1_l2itodr_req;
assign c1_l2itodr_req.nid = c1_l2itodr_req_nid;
assign c1_l2itodr_req.l2id = c1_l2itodr_req_l2id;
assign c1_l2itodr_req.cmd = c1_l2itodr_req_cmd;
assign c1_l2itodr_req.paddr = c1_l2itodr_req_paddr;
I_drtol2_snack_type c1_drtol2i_snack;
assign c1_drtol2i_snack_nid = c1_drtol2i_snack.nid;
assign c1_drtol2i_snack_l2id = c1_drtol2i_snack.l2id;
assign c1_drtol2i_snack_drid = c1_drtol2i_snack.drid;
assign c1_drtol2i_snack_snack = c1_drtol2i_snack.snack;
assign c1_drtol2i_snack_line = c1_drtol2i_snack.line;
assign c1_drtol2i_snack_paddr = c1_drtol2i_snack.paddr;
I_l2snoop_ack_type c1_l2itodr_snoop_ack;
assign c1_l2itodr_snoop_ack.l2id = c1_l2itodr_snoop_ack_l2id;
assign c1_l2itodr_snoop_ack.directory_id = c1_l2itodr_snoop_ack_directory_id;
I_l2todr_disp_type c1_l2itodr_disp;
assign c1_l2itodr_disp.nid = c1_l2itodr_disp_nid;
assign c1_l2itodr_disp.l2id = c1_l2itodr_disp_l2id;
assign c1_l2itodr_disp.drid = c1_l2itodr_disp_drid;
assign c1_l2itodr_disp.mask = c1_l2itodr_disp_mask;
assign c1_l2itodr_disp.dcmd = c1_l2itodr_disp_dcmd;
assign c1_l2itodr_disp.line = c1_l2itodr_disp_line;
assign c1_l2itodr_disp.paddr = c1_l2itodr_disp_paddr;
I_drtol2_dack_type c1_drtol2i_dack;
assign c1_drtol2i_dack_nid = c1_drtol2i_dack.nid;
assign c1_drtol2i_dack_l2id = c1_drtol2i_dack.l2id;
I_l2todr_pfreq_type c1_l2itodr_pfreq;
assign c1_l2itodr_pfreq.nid = c1_l2itodr_pfreq_nid;
assign c1_l2itodr_pfreq.paddr = c1_l2itodr_pfreq_paddr;
I_l2todr_req_type c1_l2ittodr_req;
assign c1_l2ittodr_req.nid = c1_l2ittodr_req_nid;
assign c1_l2ittodr_req.l2id = c1_l2ittodr_req_l2id;
assign c1_l2ittodr_req.cmd = c1_l2ittodr_req_cmd;
assign c1_l2ittodr_req.paddr = c1_l2ittodr_req_paddr;
I_drtol2_snack_type c1_drtol2it_snack;
assign c1_drtol2it_snack_nid = c1_drtol2it_snack.nid;
assign c1_drtol2it_snack_l2id = c1_drtol2it_snack.l2id;
assign c1_drtol2it_snack_drid = c1_drtol2it_snack.drid;
assign c1_drtol2it_snack_snack = c1_drtol2it_snack.snack;
assign c1_drtol2it_snack_line = c1_drtol2it_snack.line;
assign c1_drtol2it_snack_paddr = c1_drtol2it_snack.paddr;
I_l2snoop_ack_type c1_l2ittodr_snoop_ack;
assign c1_l2ittodr_snoop_ack.l2id = c1_l2ittodr_snoop_ack_l2id;
assign c1_l2ittodr_snoop_ack.directory_id = c1_l2ittodr_snoop_ack_directory_id;
I_l2todr_disp_type c1_l2ittodr_disp;
assign c1_l2ittodr_disp.nid = c1_l2ittodr_disp_nid;
assign c1_l2ittodr_disp.l2id = c1_l2ittodr_disp_l2id;
assign c1_l2ittodr_disp.drid = c1_l2ittodr_disp_drid;
assign c1_l2ittodr_disp.mask = c1_l2ittodr_disp_mask;
assign c1_l2ittodr_disp.dcmd = c1_l2ittodr_disp_dcmd;
assign c1_l2ittodr_disp.line = c1_l2ittodr_disp_line;
assign c1_l2ittodr_disp.paddr = c1_l2ittodr_disp_paddr;
I_drtol2_dack_type c1_drtol2it_dack;
assign c1_drtol2it_dack_nid = c1_drtol2it_dack.nid;
assign c1_drtol2it_dack_l2id = c1_drtol2it_dack.l2id;
I_l2todr_req_type c1_l2d_0todr_req;
assign c1_l2d_0todr_req.nid = c1_l2d_0todr_req_nid;
assign c1_l2d_0todr_req.l2id = c1_l2d_0todr_req_l2id;
assign c1_l2d_0todr_req.cmd = c1_l2d_0todr_req_cmd;
assign c1_l2d_0todr_req.paddr = c1_l2d_0todr_req_paddr;
I_drtol2_snack_type c1_drtol2d_0_snack;
assign c1_drtol2d_0_snack_nid = c1_drtol2d_0_snack.nid;
assign c1_drtol2d_0_snack_l2id = c1_drtol2d_0_snack.l2id;
assign c1_drtol2d_0_snack_drid = c1_drtol2d_0_snack.drid;
assign c1_drtol2d_0_snack_snack = c1_drtol2d_0_snack.snack;
assign c1_drtol2d_0_snack_line = c1_drtol2d_0_snack.line;
assign c1_drtol2d_0_snack_paddr = c1_drtol2d_0_snack.paddr;
I_l2snoop_ack_type c1_l2d_0todr_snoop_ack;
assign c1_l2d_0todr_snoop_ack.l2id = c1_l2d_0todr_snoop_ack_l2id;
assign c1_l2d_0todr_snoop_ack.directory_id = c1_l2d_0todr_snoop_ack_directory_id;
I_l2todr_disp_type c1_l2d_0todr_disp;
assign c1_l2d_0todr_disp.nid = c1_l2d_0todr_disp_nid;
assign c1_l2d_0todr_disp.l2id = c1_l2d_0todr_disp_l2id;
assign c1_l2d_0todr_disp.drid = c1_l2d_0todr_disp_drid;
assign c1_l2d_0todr_disp.mask = c1_l2d_0todr_disp_mask;
assign c1_l2d_0todr_disp.dcmd = c1_l2d_0todr_disp_dcmd;
assign c1_l2d_0todr_disp.line = c1_l2d_0todr_disp_line;
assign c1_l2d_0todr_disp.paddr = c1_l2d_0todr_disp_paddr;
I_drtol2_dack_type c1_drtol2d_0_dack;
assign c1_drtol2d_0_dack_nid = c1_drtol2d_0_dack.nid;
assign c1_drtol2d_0_dack_l2id = c1_drtol2d_0_dack.l2id;
I_l2todr_pfreq_type c1_l2d_0todr_pfreq;
assign c1_l2d_0todr_pfreq.nid = c1_l2d_0todr_pfreq_nid;
assign c1_l2d_0todr_pfreq.paddr = c1_l2d_0todr_pfreq_paddr;
I_l2todr_req_type c1_l2dt_0todr_req;
assign c1_l2dt_0todr_req.nid = c1_l2dt_0todr_req_nid;
assign c1_l2dt_0todr_req.l2id = c1_l2dt_0todr_req_l2id;
assign c1_l2dt_0todr_req.cmd = c1_l2dt_0todr_req_cmd;
assign c1_l2dt_0todr_req.paddr = c1_l2dt_0todr_req_paddr;
I_drtol2_snack_type c1_drtol2dt_0_snack;
assign c1_drtol2dt_0_snack_nid = c1_drtol2dt_0_snack.nid;
assign c1_drtol2dt_0_snack_l2id = c1_drtol2dt_0_snack.l2id;
assign c1_drtol2dt_0_snack_drid = c1_drtol2dt_0_snack.drid;
assign c1_drtol2dt_0_snack_snack = c1_drtol2dt_0_snack.snack;
assign c1_drtol2dt_0_snack_line = c1_drtol2dt_0_snack.line;
assign c1_drtol2dt_0_snack_paddr = c1_drtol2dt_0_snack.paddr;
I_l2snoop_ack_type c1_l2dt_0todr_snoop_ack;
assign c1_l2dt_0todr_snoop_ack.l2id = c1_l2dt_0todr_snoop_ack_l2id;
assign c1_l2dt_0todr_snoop_ack.directory_id = c1_l2dt_0todr_snoop_ack_directory_id;
I_l2todr_disp_type c1_l2dt_0todr_disp;
assign c1_l2dt_0todr_disp.nid = c1_l2dt_0todr_disp_nid;
assign c1_l2dt_0todr_disp.l2id = c1_l2dt_0todr_disp_l2id;
assign c1_l2dt_0todr_disp.drid = c1_l2dt_0todr_disp_drid;
assign c1_l2dt_0todr_disp.mask = c1_l2dt_0todr_disp_mask;
assign c1_l2dt_0todr_disp.dcmd = c1_l2dt_0todr_disp_dcmd;
assign c1_l2dt_0todr_disp.line = c1_l2dt_0todr_disp_line;
assign c1_l2dt_0todr_disp.paddr = c1_l2dt_0todr_disp_paddr;
I_drtol2_dack_type c1_drtol2dt_0_dack;
assign c1_drtol2dt_0_dack_nid = c1_drtol2dt_0_dack.nid;
assign c1_drtol2dt_0_dack_l2id = c1_drtol2dt_0_dack.l2id;
I_l2todr_req_type l2todr0_req;
assign l2todr0_req_nid = l2todr0_req.nid;
assign l2todr0_req_l2id = l2todr0_req.l2id;
assign l2todr0_req_cmd = l2todr0_req.cmd;
assign l2todr0_req_paddr = l2todr0_req.paddr;
I_drtol2_snack_type dr0tol2_snack;
assign dr0tol2_snack.nid = dr0tol2_snack_nid;
assign dr0tol2_snack.l2id = dr0tol2_snack_l2id;
assign dr0tol2_snack.drid = dr0tol2_snack_drid;
assign dr0tol2_snack.snack = dr0tol2_snack_snack;
assign dr0tol2_snack.line = dr0tol2_snack_line;
assign dr0tol2_snack.paddr = dr0tol2_snack_paddr;
I_l2todr_disp_type l2todr0_disp;
assign l2todr0_disp_nid = l2todr0_disp.nid;
assign l2todr0_disp_l2id = l2todr0_disp.l2id;
assign l2todr0_disp_drid = l2todr0_disp.drid;
assign l2todr0_disp_mask = l2todr0_disp.mask;
assign l2todr0_disp_dcmd = l2todr0_disp.dcmd;
assign l2todr0_disp_line = l2todr0_disp.line;
assign l2todr0_disp_paddr = l2todr0_disp.paddr;
I_drtol2_dack_type dr0tol2_dack;
assign dr0tol2_dack.nid = dr0tol2_dack_nid;
assign dr0tol2_dack.l2id = dr0tol2_dack_l2id;
I_drsnoop_ack_type l2todr0_snoop_ack;
assign l2todr0_snoop_ack_drid = l2todr0_snoop_ack.drid;
I_l2todr_pfreq_type l2todr0_pfreq;
assign l2todr0_pfreq_nid = l2todr0_pfreq.nid;
assign l2todr0_pfreq_paddr = l2todr0_pfreq.paddr;
I_l2todr_req_type l2todr1_req;
assign l2todr1_req_nid = l2todr1_req.nid;
assign l2todr1_req_l2id = l2todr1_req.l2id;
assign l2todr1_req_cmd = l2todr1_req.cmd;
assign l2todr1_req_paddr = l2todr1_req.paddr;
I_drtol2_snack_type dr1tol2_snack;
assign dr1tol2_snack.nid = dr1tol2_snack_nid;
assign dr1tol2_snack.l2id = dr1tol2_snack_l2id;
assign dr1tol2_snack.drid = dr1tol2_snack_drid;
assign dr1tol2_snack.snack = dr1tol2_snack_snack;
assign dr1tol2_snack.line = dr1tol2_snack_line;
assign dr1tol2_snack.paddr = dr1tol2_snack_paddr;
I_l2todr_disp_type l2todr1_disp;
assign l2todr1_disp_nid = l2todr1_disp.nid;
assign l2todr1_disp_l2id = l2todr1_disp.l2id;
assign l2todr1_disp_drid = l2todr1_disp.drid;
assign l2todr1_disp_mask = l2todr1_disp.mask;
assign l2todr1_disp_dcmd = l2todr1_disp.dcmd;
assign l2todr1_disp_line = l2todr1_disp.line;
assign l2todr1_disp_paddr = l2todr1_disp.paddr;
I_drtol2_dack_type dr1tol2_dack;
assign dr1tol2_dack.nid = dr1tol2_dack_nid;
assign dr1tol2_dack.l2id = dr1tol2_dack_l2id;
I_drsnoop_ack_type l2todr1_snoop_ack;
assign l2todr1_snoop_ack_drid = l2todr1_snoop_ack.drid;
I_l2todr_pfreq_type l2todr1_pfreq;
assign l2todr1_pfreq_nid = l2todr1_pfreq.nid;
assign l2todr1_pfreq_paddr = l2todr1_pfreq.paddr;
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
net_2core2dr net_2core2dr_dut(.*);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_1_V
`define SKY130_FD_SC_LP__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_PP_SYMBOL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_PP_SYMBOL_V
|
module ibex_alu (
operator_i,
operand_a_i,
operand_b_i,
multdiv_operand_a_i,
multdiv_operand_b_i,
multdiv_sel_i,
adder_result_o,
adder_result_ext_o,
result_o,
comparison_result_o,
is_equal_result_o
);
input wire [4:0] operator_i;
input wire [31:0] operand_a_i;
input wire [31:0] operand_b_i;
input wire [32:0] multdiv_operand_a_i;
input wire [32:0] multdiv_operand_b_i;
input wire multdiv_sel_i;
output wire [31:0] adder_result_o;
output wire [33:0] adder_result_ext_o;
output reg [31:0] result_o;
output wire comparison_result_o;
output wire is_equal_result_o;
parameter [31:0] PMP_MAX_REGIONS = 16;
parameter [31:0] PMP_CFG_W = 8;
parameter [31:0] PMP_I = 0;
parameter [31:0] PMP_D = 1;
parameter [11:0] CSR_OFF_PMP_CFG = 12'h3A0;
parameter [11:0] CSR_OFF_PMP_ADDR = 12'h3B0;
parameter [31:0] CSR_MSTATUS_MIE_BIT = 3;
parameter [31:0] CSR_MSTATUS_MPIE_BIT = 7;
parameter [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11;
parameter [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12;
parameter [31:0] CSR_MSTATUS_MPRV_BIT = 17;
parameter [31:0] CSR_MSTATUS_TW_BIT = 21;
parameter [31:0] CSR_MSIX_BIT = 3;
parameter [31:0] CSR_MTIX_BIT = 7;
parameter [31:0] CSR_MEIX_BIT = 11;
parameter [31:0] CSR_MFIX_BIT_LOW = 16;
parameter [31:0] CSR_MFIX_BIT_HIGH = 30;
localparam [0:0] IMM_A_Z = 0;
localparam [0:0] JT_ALU = 0;
localparam [0:0] OP_B_REG_B = 0;
localparam [1:0] CSR_OP_READ = 0;
localparam [1:0] EXC_PC_EXC = 0;
localparam [1:0] MD_OP_MULL = 0;
localparam [1:0] OP_A_REG_A = 0;
localparam [1:0] RF_WD_LSU = 0;
localparam [2:0] IMM_B_I = 0;
localparam [2:0] PC_BOOT = 0;
localparam [4:0] ALU_ADD = 0;
localparam [0:0] IMM_A_ZERO = 1;
localparam [0:0] JT_BT_ALU = 1;
localparam [0:0] OP_B_IMM = 1;
localparam [1:0] CSR_OP_WRITE = 1;
localparam [1:0] EXC_PC_IRQ = 1;
localparam [1:0] MD_OP_MULH = 1;
localparam [1:0] OP_A_FWD = 1;
localparam [1:0] RF_WD_EX = 1;
localparam [2:0] IMM_B_S = 1;
localparam [2:0] PC_JUMP = 1;
localparam [4:0] ALU_SUB = 1;
localparam [4:0] ALU_GE = 10;
localparam [4:0] ALU_GEU = 11;
localparam [4:0] ALU_EQ = 12;
localparam [11:0] CSR_MSTATUS = 12'h300;
localparam [11:0] CSR_MISA = 12'h301;
localparam [11:0] CSR_MIE = 12'h304;
localparam [11:0] CSR_MTVEC = 12'h305;
localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320;
localparam [11:0] CSR_MHPMEVENT3 = 12'h323;
localparam [11:0] CSR_MHPMEVENT4 = 12'h324;
localparam [11:0] CSR_MHPMEVENT5 = 12'h325;
localparam [11:0] CSR_MHPMEVENT6 = 12'h326;
localparam [11:0] CSR_MHPMEVENT7 = 12'h327;
localparam [11:0] CSR_MHPMEVENT8 = 12'h328;
localparam [11:0] CSR_MHPMEVENT9 = 12'h329;
localparam [11:0] CSR_MHPMEVENT10 = 12'h32A;
localparam [11:0] CSR_MHPMEVENT11 = 12'h32B;
localparam [11:0] CSR_MHPMEVENT12 = 12'h32C;
localparam [11:0] CSR_MHPMEVENT13 = 12'h32D;
localparam [11:0] CSR_MHPMEVENT14 = 12'h32E;
localparam [11:0] CSR_MHPMEVENT15 = 12'h32F;
localparam [11:0] CSR_MHPMEVENT16 = 12'h330;
localparam [11:0] CSR_MHPMEVENT17 = 12'h331;
localparam [11:0] CSR_MHPMEVENT18 = 12'h332;
localparam [11:0] CSR_MHPMEVENT19 = 12'h333;
localparam [11:0] CSR_MHPMEVENT20 = 12'h334;
localparam [11:0] CSR_MHPMEVENT21 = 12'h335;
localparam [11:0] CSR_MHPMEVENT22 = 12'h336;
localparam [11:0] CSR_MHPMEVENT23 = 12'h337;
localparam [11:0] CSR_MHPMEVENT24 = 12'h338;
localparam [11:0] CSR_MHPMEVENT25 = 12'h339;
localparam [11:0] CSR_MHPMEVENT26 = 12'h33A;
localparam [11:0] CSR_MHPMEVENT27 = 12'h33B;
localparam [11:0] CSR_MHPMEVENT28 = 12'h33C;
localparam [11:0] CSR_MHPMEVENT29 = 12'h33D;
localparam [11:0] CSR_MHPMEVENT30 = 12'h33E;
localparam [11:0] CSR_MHPMEVENT31 = 12'h33F;
localparam [11:0] CSR_MSCRATCH = 12'h340;
localparam [11:0] CSR_MEPC = 12'h341;
localparam [11:0] CSR_MCAUSE = 12'h342;
localparam [11:0] CSR_MTVAL = 12'h343;
localparam [11:0] CSR_MIP = 12'h344;
localparam [11:0] CSR_PMPCFG0 = 12'h3A0;
localparam [11:0] CSR_PMPCFG1 = 12'h3A1;
localparam [11:0] CSR_PMPCFG2 = 12'h3A2;
localparam [11:0] CSR_PMPCFG3 = 12'h3A3;
localparam [11:0] CSR_PMPADDR0 = 12'h3B0;
localparam [11:0] CSR_PMPADDR1 = 12'h3B1;
localparam [11:0] CSR_PMPADDR2 = 12'h3B2;
localparam [11:0] CSR_PMPADDR3 = 12'h3B3;
localparam [11:0] CSR_PMPADDR4 = 12'h3B4;
localparam [11:0] CSR_PMPADDR5 = 12'h3B5;
localparam [11:0] CSR_PMPADDR6 = 12'h3B6;
localparam [11:0] CSR_PMPADDR7 = 12'h3B7;
localparam [11:0] CSR_PMPADDR8 = 12'h3B8;
localparam [11:0] CSR_PMPADDR9 = 12'h3B9;
localparam [11:0] CSR_PMPADDR10 = 12'h3BA;
localparam [11:0] CSR_PMPADDR11 = 12'h3BB;
localparam [11:0] CSR_PMPADDR12 = 12'h3BC;
localparam [11:0] CSR_PMPADDR13 = 12'h3BD;
localparam [11:0] CSR_PMPADDR14 = 12'h3BE;
localparam [11:0] CSR_PMPADDR15 = 12'h3BF;
localparam [11:0] CSR_TSELECT = 12'h7A0;
localparam [11:0] CSR_TDATA1 = 12'h7A1;
localparam [11:0] CSR_TDATA2 = 12'h7A2;
localparam [11:0] CSR_TDATA3 = 12'h7A3;
localparam [11:0] CSR_MCONTEXT = 12'h7A8;
localparam [11:0] CSR_SCONTEXT = 12'h7AA;
localparam [11:0] CSR_DCSR = 12'h7b0;
localparam [11:0] CSR_DPC = 12'h7b1;
localparam [11:0] CSR_DSCRATCH0 = 12'h7b2;
localparam [11:0] CSR_DSCRATCH1 = 12'h7b3;
localparam [11:0] CSR_MCYCLE = 12'hB00;
localparam [11:0] CSR_MINSTRET = 12'hB02;
localparam [11:0] CSR_MHPMCOUNTER3 = 12'hB03;
localparam [11:0] CSR_MHPMCOUNTER4 = 12'hB04;
localparam [11:0] CSR_MHPMCOUNTER5 = 12'hB05;
localparam [11:0] CSR_MHPMCOUNTER6 = 12'hB06;
localparam [11:0] CSR_MHPMCOUNTER7 = 12'hB07;
localparam [11:0] CSR_MHPMCOUNTER8 = 12'hB08;
localparam [11:0] CSR_MHPMCOUNTER9 = 12'hB09;
localparam [11:0] CSR_MHPMCOUNTER10 = 12'hB0A;
localparam [11:0] CSR_MHPMCOUNTER11 = 12'hB0B;
localparam [11:0] CSR_MHPMCOUNTER12 = 12'hB0C;
localparam [11:0] CSR_MHPMCOUNTER13 = 12'hB0D;
localparam [11:0] CSR_MHPMCOUNTER14 = 12'hB0E;
localparam [11:0] CSR_MHPMCOUNTER15 = 12'hB0F;
localparam [11:0] CSR_MHPMCOUNTER16 = 12'hB10;
localparam [11:0] CSR_MHPMCOUNTER17 = 12'hB11;
localparam [11:0] CSR_MHPMCOUNTER18 = 12'hB12;
localparam [11:0] CSR_MHPMCOUNTER19 = 12'hB13;
localparam [11:0] CSR_MHPMCOUNTER20 = 12'hB14;
localparam [11:0] CSR_MHPMCOUNTER21 = 12'hB15;
localparam [11:0] CSR_MHPMCOUNTER22 = 12'hB16;
localparam [11:0] CSR_MHPMCOUNTER23 = 12'hB17;
localparam [11:0] CSR_MHPMCOUNTER24 = 12'hB18;
localparam [11:0] CSR_MHPMCOUNTER25 = 12'hB19;
localparam [11:0] CSR_MHPMCOUNTER26 = 12'hB1A;
localparam [11:0] CSR_MHPMCOUNTER27 = 12'hB1B;
localparam [11:0] CSR_MHPMCOUNTER28 = 12'hB1C;
localparam [11:0] CSR_MHPMCOUNTER29 = 12'hB1D;
localparam [11:0] CSR_MHPMCOUNTER30 = 12'hB1E;
localparam [11:0] CSR_MHPMCOUNTER31 = 12'hB1F;
localparam [11:0] CSR_MCYCLEH = 12'hB80;
localparam [11:0] CSR_MINSTRETH = 12'hB82;
localparam [11:0] CSR_MHPMCOUNTER3H = 12'hB83;
localparam [11:0] CSR_MHPMCOUNTER4H = 12'hB84;
localparam [11:0] CSR_MHPMCOUNTER5H = 12'hB85;
localparam [11:0] CSR_MHPMCOUNTER6H = 12'hB86;
localparam [11:0] CSR_MHPMCOUNTER7H = 12'hB87;
localparam [11:0] CSR_MHPMCOUNTER8H = 12'hB88;
localparam [11:0] CSR_MHPMCOUNTER9H = 12'hB89;
localparam [11:0] CSR_MHPMCOUNTER10H = 12'hB8A;
localparam [11:0] CSR_MHPMCOUNTER11H = 12'hB8B;
localparam [11:0] CSR_MHPMCOUNTER12H = 12'hB8C;
localparam [11:0] CSR_MHPMCOUNTER13H = 12'hB8D;
localparam [11:0] CSR_MHPMCOUNTER14H = 12'hB8E;
localparam [11:0] CSR_MHPMCOUNTER15H = 12'hB8F;
localparam [11:0] CSR_MHPMCOUNTER16H = 12'hB90;
localparam [11:0] CSR_MHPMCOUNTER17H = 12'hB91;
localparam [11:0] CSR_MHPMCOUNTER18H = 12'hB92;
localparam [11:0] CSR_MHPMCOUNTER19H = 12'hB93;
localparam [11:0] CSR_MHPMCOUNTER20H = 12'hB94;
localparam [11:0] CSR_MHPMCOUNTER21H = 12'hB95;
localparam [11:0] CSR_MHPMCOUNTER22H = 12'hB96;
localparam [11:0] CSR_MHPMCOUNTER23H = 12'hB97;
localparam [11:0] CSR_MHPMCOUNTER24H = 12'hB98;
localparam [11:0] CSR_MHPMCOUNTER25H = 12'hB99;
localparam [11:0] CSR_MHPMCOUNTER26H = 12'hB9A;
localparam [11:0] CSR_MHPMCOUNTER27H = 12'hB9B;
localparam [11:0] CSR_MHPMCOUNTER28H = 12'hB9C;
localparam [11:0] CSR_MHPMCOUNTER29H = 12'hB9D;
localparam [11:0] CSR_MHPMCOUNTER30H = 12'hB9E;
localparam [11:0] CSR_MHPMCOUNTER31H = 12'hB9F;
localparam [11:0] CSR_MHARTID = 12'hF14;
localparam [4:0] ALU_NE = 13;
localparam [4:0] ALU_SLT = 14;
localparam [4:0] ALU_SLTU = 15;
localparam [1:0] CSR_OP_SET = 2;
localparam [1:0] EXC_PC_DBD = 2;
localparam [1:0] MD_OP_DIV = 2;
localparam [1:0] OP_A_CURRPC = 2;
localparam [1:0] RF_WD_CSR = 2;
localparam [2:0] IMM_B_B = 2;
localparam [2:0] PC_EXC = 2;
localparam [4:0] ALU_XOR = 2;
localparam [1:0] PMP_ACC_EXEC = 2'b00;
localparam [1:0] PMP_MODE_OFF = 2'b00;
localparam [1:0] PRIV_LVL_U = 2'b00;
localparam [1:0] PMP_ACC_WRITE = 2'b01;
localparam [1:0] PMP_MODE_TOR = 2'b01;
localparam [1:0] PRIV_LVL_S = 2'b01;
localparam [1:0] PMP_ACC_READ = 2'b10;
localparam [1:0] PMP_MODE_NA4 = 2'b10;
localparam [1:0] PRIV_LVL_H = 2'b10;
localparam [1:0] PMP_MODE_NAPOT = 2'b11;
localparam [1:0] PRIV_LVL_M = 2'b11;
localparam [1:0] CSR_OP_CLEAR = 3;
localparam [1:0] EXC_PC_DBG_EXC = 3;
localparam [1:0] MD_OP_REM = 3;
localparam [1:0] OP_A_IMM = 3;
localparam [2:0] IMM_B_U = 3;
localparam [2:0] PC_ERET = 3;
localparam [4:0] ALU_OR = 3;
localparam [2:0] DBG_CAUSE_NONE = 3'h0;
localparam [2:0] DBG_CAUSE_EBREAK = 3'h1;
localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2;
localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3;
localparam [2:0] DBG_CAUSE_STEP = 3'h4;
localparam [2:0] IMM_B_J = 4;
localparam [2:0] PC_DRET = 4;
localparam [4:0] ALU_AND = 4;
localparam [3:0] XDEBUGVER_NO = 4'd0;
localparam [3:0] XDEBUGVER_NONSTD = 4'd15;
localparam [3:0] XDEBUGVER_STD = 4'd4;
localparam [2:0] IMM_B_INCR_PC = 5;
localparam [4:0] ALU_SRA = 5;
localparam [2:0] IMM_B_INCR_ADDR = 6;
localparam [4:0] ALU_SRL = 6;
localparam [4:0] ALU_SLL = 7;
localparam [6:0] OPCODE_LOAD = 7'h03;
localparam [6:0] OPCODE_MISC_MEM = 7'h0f;
localparam [6:0] OPCODE_OP_IMM = 7'h13;
localparam [6:0] OPCODE_AUIPC = 7'h17;
localparam [6:0] OPCODE_STORE = 7'h23;
localparam [6:0] OPCODE_OP = 7'h33;
localparam [6:0] OPCODE_LUI = 7'h37;
localparam [6:0] OPCODE_BRANCH = 7'h63;
localparam [6:0] OPCODE_JALR = 7'h67;
localparam [6:0] OPCODE_JAL = 7'h6f;
localparam [6:0] OPCODE_SYSTEM = 7'h73;
localparam [4:0] ALU_LT = 8;
localparam [4:0] ALU_LTU = 9;
localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00};
localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01};
localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02};
localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03};
localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05};
localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07};
localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08};
localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11};
localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03};
localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07};
localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11};
localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31};
wire [31:0] operand_a_rev;
wire [32:0] operand_b_neg;
generate
genvar gen_rev_operand_a_k;
for (gen_rev_operand_a_k = 0; (gen_rev_operand_a_k < 32); gen_rev_operand_a_k = (gen_rev_operand_a_k + 1)) begin : gen_rev_operand_a
assign operand_a_rev[gen_rev_operand_a_k] = operand_a_i[(31 - gen_rev_operand_a_k)];
end
endgenerate
reg adder_op_b_negate;
wire [32:0] adder_in_a;
wire [32:0] adder_in_b;
wire [31:0] adder_result;
always @(*) begin
adder_op_b_negate = 1'b0;
case (operator_i)
ALU_SUB, ALU_EQ, ALU_NE, ALU_GE, ALU_GEU, ALU_LT, ALU_LTU, ALU_SLT, ALU_SLTU: adder_op_b_negate = 1'b1;
default:
;
endcase
end
assign adder_in_a = (multdiv_sel_i ? multdiv_operand_a_i : {operand_a_i, 1'b1});
assign operand_b_neg = ({operand_b_i, 1'b0} ^ {33 {adder_op_b_negate}});
assign adder_in_b = (multdiv_sel_i ? multdiv_operand_b_i : operand_b_neg);
assign adder_result_ext_o = ($unsigned(adder_in_a) + $unsigned(adder_in_b));
assign adder_result = adder_result_ext_o[32:1];
assign adder_result_o = adder_result;
wire shift_left;
wire shift_arithmetic;
wire [4:0] shift_amt;
wire [31:0] shift_op_a;
wire [31:0] shift_result;
wire [31:0] shift_right_result;
wire [31:0] shift_left_result;
assign shift_amt = operand_b_i[4:0];
assign shift_left = (operator_i == ALU_SLL);
assign shift_arithmetic = (operator_i == ALU_SRA);
assign shift_op_a = (shift_left ? operand_a_rev : operand_a_i);
wire [32:0] shift_op_a_32;
assign shift_op_a_32 = {(shift_arithmetic & shift_op_a[31]), shift_op_a};
wire signed [32:0] shift_right_result_signed;
wire [32:0] shift_right_result_ext;
assign shift_right_result_signed = ($signed(shift_op_a_32) >>> shift_amt[4:0]);
assign shift_right_result_ext = $unsigned(shift_right_result_signed);
assign shift_right_result = shift_right_result_ext[31:0];
generate
genvar gen_rev_shift_right_result_j;
for (gen_rev_shift_right_result_j = 0; (gen_rev_shift_right_result_j < 32); gen_rev_shift_right_result_j = (gen_rev_shift_right_result_j + 1)) begin : gen_rev_shift_right_result
assign shift_left_result[gen_rev_shift_right_result_j] = shift_right_result[(31 - gen_rev_shift_right_result_j)];
end
endgenerate
assign shift_result = (shift_left ? shift_left_result : shift_right_result);
wire is_equal;
reg is_greater_equal;
reg cmp_signed;
always @(*) begin
cmp_signed = 1'b0;
case (operator_i)
ALU_GE, ALU_LT, ALU_SLT: cmp_signed = 1'b1;
default:
;
endcase
end
assign is_equal = (adder_result == 32'b0);
assign is_equal_result_o = is_equal;
always @(*)
if (((operand_a_i[31] ^ operand_b_i[31]) == 1'b0))
is_greater_equal = (adder_result[31] == 1'b0);
else
is_greater_equal = (operand_a_i[31] ^ cmp_signed);
reg cmp_result;
always @(*) begin
cmp_result = is_equal;
case (operator_i)
ALU_EQ: cmp_result = is_equal;
ALU_NE: cmp_result = ~is_equal;
ALU_GE, ALU_GEU: cmp_result = is_greater_equal;
ALU_LT, ALU_LTU, ALU_SLT, ALU_SLTU: cmp_result = ~is_greater_equal;
default:
;
endcase
end
assign comparison_result_o = cmp_result;
always @(*) begin
result_o = 1'sb0;
case (operator_i)
ALU_AND: result_o = (operand_a_i & operand_b_i);
ALU_OR: result_o = (operand_a_i | operand_b_i);
ALU_XOR: result_o = (operand_a_i ^ operand_b_i);
ALU_ADD, ALU_SUB: result_o = adder_result;
ALU_SLL, ALU_SRL, ALU_SRA: result_o = shift_result;
ALU_EQ, ALU_NE, ALU_GE, ALU_GEU, ALU_LT, ALU_LTU, ALU_SLT, ALU_SLTU: result_o = {31'h0, cmp_result};
default:
;
endcase
end
endmodule
|
// Single-Port BRAM with Byte-wide Write Enable
// Read-First mode
// Single-process description
// Compact description of the write with a generate-for
// statement
// Column width and number of columns easily configurable
//
// bytewrite_ram_32bits.v
//
module bytewrite_ram_32bits (clk, we, addr, din, dout);
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] din;
output reg [NB_COL*COL_WIDTH-1:0] dout;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
integer _i;
initial begin
`ifndef IVERILOG
$readmemh(filename,RAM);
`endif
#10;
// Just for debugging readmemh in case it does not work as expected
for(_i=0;_i<6;_i=_i+1) begin
$display("idx : %d data : %x",_i,RAM[_i]);
end
$display("======================");
end
always @(posedge clk)
begin
dout <= RAM[addr];
end
// Remove the original generate statement to ease Xilinx memory bitstream patching
always @(posedge clk) begin
if (we[0])
RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH];
end
always @(posedge clk) begin
if (we[1])
RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH];
end
always @(posedge clk) begin
if (we[2])
RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH];
end
always @(posedge clk) begin
if (we[3])
RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH];
end
endmodule
|
module OoO_cpu(
input clk, rst
);
//////////////////////////insturction fetch and IF/DP pipeline////////////////////////////////
/////////////////some temporary signals/////////////////
wire changeFlow_IF; assign changeFlow_IF = 0;
wire [31:0] jb_addr_IF; assign jb_addr_IF = {32{1'b0}};
wire stall_PC; assign stall_PC = 0;
wire stall_IF_DP; assign stall_IF_DP = 0;
wire flush_IF_DP; assign flush_IF_DP = 0;
wire [31:0] instr_IF_DP;
wire [31:0] pc_1_IF_DP;
///////////////////////////////////////////////////////
IF_stage i_IF_stage(
.clk(clk),
.rst(rst),
.changeFlow(changeFlow_IF),
.jb_addr(jb_addr_IF),
.stall_PC(stall_PC),
.stall_IF_DP(stall_IF_DP),
.flush_IF_DP(flush_IF_DP),
.instr_IF_DP(instr_IF_DP),
.pc_1_IF_DP(pc_1_IF_DP));
/////////////////////////////////decoder////////////////////////////////////
wire writeRd; //asserted for write rd, deasserted for write rt
wire RegDest; //asserted when write register
wire isDispatch; //
wire mem_wen;
wire mem_ren;
wire read_rs, read_rt;
//to alu reservation station
wire alloca_RS_en;
wire ldic, isSignedEx, isImmed;
wire alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3;
wire isJump, isJR;
wire link;
decoder i_decoder(
.opcode(instr_IF_DP[31:26]),
.writeRd(writeRd),
.RegDest(RegDest),
.isDispatch(isDispatch),
.mem_wen(mem_wen),
.mem_ren(mem_ren),
.read_rs(read_rs),
.read_rt(read_rt),
.alloc_RS_en(alloc_RS_en),
.ldic(ldic),
.isSignEx(isSignEx),
.isImmed(isImmed),
.alu_ctrl0(alu_ctrl0),
.alu_ctrl1(alu_ctrl1),
.alu_ctrl2(alu_ctrl2),
.alu_ctrl3(alu_ctrl3),
.isJump(isJump),
.isJR(isJR),
.link(link));
////////////////////////////////////////////////////////////////////////////
//////////////////////////map table//////////////////////////////////////////
////temporary signals/////////////////////////////////////////////////////
wire hazard_stall_map_table; assign hazard_stall_map_table = 0;
/////////////recovery////////////////
wire [4:0] recover_rd;
wire [5:0] p_rd_flush;
/////////////////complete///////
wire [5:0] p_rd_compl; assign p_rd_compl = 6'h00;
wire complete = 0;
wire RegDest_compl = 0;
//////////////////////////////////////////////////////////////////////////
wire [4:0] l_rs_map_table;
wire [4:0] l_rt_map_table;
wire [4:0] l_rd_map_table;
wire [5:0] PR_new; //from free list
////////////////these four to reservation station
wire [5:0] p_rs;
wire p_rs_v;
wire [5:0] p_rt;
wire p_rt_v;
wire [5:0] PR_old_DP; //to ROB
//from ROB, for recovery
wire recover;
wire RegDest_ROB;
wire [4:0] flush_rd;
wire [5:0] PR_old_flush;
assign l_rs_map_table = instr_IF_DP[25:21];
assign l_rt_map_table = instr_IF_DP[20:16];
assign l_rd_map_table = writeRd ? instr_IF_DP[15:11] : instr_IF_DP[20:16];
map_table i_map_table(
.clk(clk),
.rst(rst),
.hazard_stall(hazard_stall_map_table),
.l_rs(l_rs_map_table),
.l_rt(l_rt_map_table),
.l_rd(l_rd_map_table),
.isDispatch(isDispatch),
.RegDest(RegDest),
.p_rd_new(PR_new),
.recover_rd(flush_rd),
.p_rd_flush(PR_old_flush),
.recover(recover),
.RegDest_ROB(RegDest_ROB),
.p_rd_compl(p_rd_compl),
.complete(complete),
.RegDest_compl(RegDest_compl),
.p_rs(p_rs),
.p_rt(p_rt),
.p_rs_v(p_rs_v),
.p_rt_v(p_rt_v),
.PR_old_rd(PR_old_DP));
///////////////////////////////free list ////////////////////////////////////
///////////////temporary signals//////////////////////
wire hazard_stall_free_list = 0;
/////////////////////////////////////////////////////
wire free_list_empty;
wire [5:0] PR_old_RT; //from re-order buffer
wire RegDest_retire;
wire retire_reg;
//for recovery
wire [5:0] PR_new_flush;
free_list_new i_free_list_new(
.PR_old(PR_old_RT),
.RegDest_retire(RegDest_retire),
.retire_reg(retire_reg),
.RegDest(RegDest),
.clk(clk),
.rst(rst),
.hazard_stall(hazard_stall_free_list),
.recover(recover),
.PR_new_flush(PR_new_flush),
.RegDest_ROB(RegDest_ROB),
.PR_new(PR_new),
.empty(free_list_empty));
////////////////////////////reorder buffer/////////////////////////////////////
///////////////temporary signals/////////////////////
wire [3:0] rob_num_compl = 4'h0;
/////////////these two from complete stage
wire changeFlow_rob_in = 0;
wire [31:0] jb_addr_rob_in = {32{1'b0}};
wire hazard_stall_rob = 0;
/////////////////////////////////////////////////////
//////these two go to store queue
wire retire_ST;
wire [3:0] retire_rob;
wire rob_full, rob_empty;
wire [3:0] flush_rob_num;
wire [3:0] rob_num_dp; //rob number written into reservation station
reorder_buffer_beh i_reorder_buffer(
.rst(rst),
.clk(clk),
.isDispatch(isDispatch),
.isSW(mem_wen),
.RegDest(RegDest),
.PR_old_DP(PR_old_DP),
.PR_new_DP(PR_new),
.rd_DP(l_rd_map_table),
.complete(complete),
.rob_number(rob_num_compl),
.jb_addr(jb_addr_rob_in),
.changeFlow(changeFlow_rob_in),
.hazard_stall(hazard_stall_rob),
.rob_num_dp(rob_num_dp),
.PR_old_RT(PR_old_RT),
.RegDest_retire(RegDest_retire),
.retire_reg(retire_reg),
.retire_ST(retire_ST),
.retire_rob(retire_rob),
.full(full),
.empty(empty),
.RegDest_out(RegDest_ROB),
.PR_old_flush(PR_old_flush),
.PR_new_flush(PR_new_flush),
.rd_flush(flush_rd),
.out_rob_num(flush_rob_num),
.changeFlow_out(changeFlow_IF),
.changeFlow_addr(jb_addr_IF),
.recover(recover));
///////////////////////////////////////////ls_station//////////////////////////////////
///////////temporary wires/////////////////
wire hazard_stall_lss; assign hazard_stall_lss = 0;
wire stall_issue_lss = 0;
///////////////////////////////////////////
wire [5:0] p_rs_lss, p_rt_lss, p_rd_lss;
wire [15:0] immed_lss;
wire [3:0] rob_num_lss;
wire RegDest_lss, mem_ren_lss, mem_wen_lss;
wire issue_lss;
wire lss_full;
ls_station i_lss( .clk(clk),
.rst(rst),
.isDispatch(isDispatch),
.rob_num_dp(rob_num_dp), //from rob in dispatch stage
.p_rd_new(PR_new), //from free list
.p_rs(p_rs), //these four signals from map table
.read_rs(read_rs), //from decoder ********
.v_rs(p_rs_v),
.p_rt(p_rt),
.read_rt(read_rt), //from decoder ********
.v_rt(p_rt_v),
.mem_ren(mem_ren), //from decoder ********
.mem_wen(mem_wen), //from decoder ********
.immed(instr_IF_DP[15:0]), //from decode
.stall_hazard(hazard_stall_lss),
.stall_issue(stall_issue_lss),
.recover(recover), //from ROB
.rob_num_rec(flush_rob_num), //from ROB
.p_rd_compl(p_rd_compl),
.RegDest_compl(RegDest_compl),
.complete(complete),
.p_rs_out(p_rs_lss),
.p_rt_out(p_rt_lss),
.p_rd_out(p_rd_lss),
.immed_out(immed_lss),
.rob_num_out(rob_num_lss),
.RegDest_out(RegDest_lss),
.mem_ren_out(mem_ren_lss),
.mem_wen_out(mem_wen_lss),
.issue(issue_lss),
.lss_full(lss_full));
////////////////////////////////ALU reservation station///////////////////////////////////
wire rs_alu_full;
///////////////temporary signals////////////
wire stall_hazard_rs_alu;
assign stall_hazard_rs_alu = 0;
wire stall_issue_alu = 0;
////////////////////////////////////////////
wire issue_en_alu;
//to EX (IS/EX pipeline reg)
wire [16:0] EX_ctrl_in;
//[5:0] opcode, [6] ldic, [7] isSignEx, [8] isImmed, [9] alu_ctrl0, [10] alu_ctrl1, [11] alu_ctrl2, [12] alu_ctrl3
//[13] isJump, [14] isJR, [15] RegDest, [16] link
assign EX_ctrl_in = { link,
RegDest,
isJR,
isJump,
alu_ctrl3, alu_ctrl2, alu_ctrl1, alu_ctrl0,
isImmed, isSignEx,
ldic, //load instruction count
instr_IF_DP[31:26] };
wire [31:0] PC_out_rs_alu;
wire [15:0] imm_rs_alu;
//go through EX (IS/EX pipeline reg)stage, but used in COMPL stage
wire [3:0] EX_rob_alu;
wire [16:0] EX_ctrl_out;
wire [5:0] p_rd_rs_alu;
//to physical register
wire [5:0] p_rs_out_alu, p_rt_out_alu;
rs_alu i_rs_alu(
.clk(clk),
.rst(rst),
.num_rob_entry(rob_num_dp), //rob number of rob in dispatch stage
.PC_in(pc_1_IF_DP), //
.EX_ctrl_in(EX_ctrl_in),
.p_rs_in(p_rs), //from map table
.p_rt_in(p_rt),
.p_rs_rdy_in(p_rs_v), //valid bits from map table
.p_rt_rdy_in(p_rt_v),
.rs_read(read_rs), //from the decoder, indicates if read rs/rt
.rt_read(read_rt),
.imm_bits_in(instr_IF_DP[15:0]), //immediate value
.p_rd_new(PR_new), //from free list
.alloc_RS_en(alloc_RS_en),
.recover(recover),
.rec_rob_entry(flush_rob_num),
.stall_hazard(stall_hazard_rs_alu),
.stall_issue(stall_issue_alu),
.bus_en(complete && RegDest_compl), //set ready bit only if RegDest is 1
.tag(p_rd_compl),
.issue_en(issue_en_alu),
.PC_out(PC_out_rs_alu), //to EX stage
.rob_id_out(EX_rob_alu),
.EX_ctrl_out(EX_ctrl_out), //one part to EX, the other part used in COMPL
.p_rs_out(p_rs_out_alu), //to physical register
.p_rt_out(p_rt_out_alu),
.imm_bits_out(imm_rs_alu),
.p_rd_out(p_rd_rs_alu),
.stl_dec_rs_alu_full(rs_alu_full));
/////////temporary wires////////////////////
wire [31:0] result_compl;
assign result_compl = 32'h00000000;
////////////////////////////////////////////
wire [31:0] rs_data_IS_EX_alu, rt_data_IS_EX_alu;
/////////////////////////////////physical register for ALU////////////////////////////
physical_register i_physical_register_ALU(
.raddr0(p_rs_out_alu),
.raddr1(p_rt_out_alu),
.we(RegDest_compl),
.waddr(p_rd_compl),
.din(result_compl),
.clk(clk),
.dout0(rs_data_IS_EX_alu),
.dout1(rt_data_IS_EX_alu));
//////////////////////////////IS/EX pipeline register for ALU instructions///////////////
//control signals
reg ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu;
reg alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX;
reg isJump_IS_EX, isJR_IS_EX;
reg link_IS_EX, RegDest_IS_EX_alu;
///data and address signals
reg [31:0] pc_1_IS_EX;
reg [15:0] immed_value_IS_EX_alu;
reg [3:0] rob_IS_EX_alu;
reg [5:0] p_rd_IS_EX_alu;
reg [5:0] opcode_IS_EX;
reg issue_en_IS_EX_alu;
//[5:0] opcode, [6] ldic, [7] isSignEx, [8] isImmed, [9] alu_ctrl0, [10] alu_ctrl1, [11] alu_ctrl2, [12] alu_ctrl3
//[13] isJump, [14] isJR, [15] RegDest, [16] link
/////////////////////////////
///////control signals
always @(posedge clk or negedge rst) begin
if (!rst) begin
{ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu, alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX} <= 0;
{isJump_IS_EX, isJR_IS_EX} <= 0;
{link_IS_EX, RegDest_IS_EX_alu} <= 0;
end
else if ((recover && (rob_IS_EX_alu == flush_rob_num)) || !issue_en_alu) begin //flush this pipeline register
{ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu, alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX} <= 0;
{isJump_IS_EX, isJR_IS_EX} <= 0;
{link_IS_EX, RegDest_IS_EX_alu} <= 0;
issue_en_IS_EX_alu <= 0;
end
else begin
{ldic_IS_EX, isSignedEx_IS_EX, immed_IS_EX_alu, alu_ctrl0_IS_EX, alu_ctrl1_IS_EX, alu_ctrl2_IS_EX, alu_ctrl3_IS_EX}
<= {EX_ctrl_out[6], EX_ctrl_out[7], EX_ctrl_out[8], EX_ctrl_out[9], EX_ctrl_out[10], EX_ctrl_out[11], EX_ctrl_out[12]};
{isJump_IS_EX, isJR_IS_EX} <= {EX_ctrl_out[13], EX_ctrl_out[14]};
{link_IS_EX, RegDest_IS_EX_alu} <= {EX_ctrl_out[16], EX_ctrl_out[15]};
issue_en_IS_EX_alu <= issue_en_alu;
end
end
//data and address pipeline register
always @(posedge clk or negedge rst) begin
if (!rst) begin
pc_1_IS_EX <= 0;
immed_value_IS_EX_alu <= 0;
rob_IS_EX_alu <= 0;
p_rd_IS_EX_alu <= 0;
opcode_IS_EX <= 0;
end
else begin
pc_1_IS_EX <= PC_out_rs_alu;
immed_value_IS_EX_alu <= imm_rs_alu;
rob_IS_EX_alu <= EX_rob_alu;
p_rd_IS_EX_alu <= p_rd_rs_alu;
opcode_IS_EX <= EX_ctrl_out[5:0];
end
end
////temporary wires//////////
wire [15:0] instr_cnt, cycle_cnt;
assign instr_cnt = 16'h0000;
assign cycle_cnt = 16'h0000;
/////////////////////////////
wire [31:0] alu_result_EX;
wire [31:0] jb_addr_EX;
wire changeFlow_EX;
/////////////////////////////////functional units////////////////////////////////////////
EX_stage_OoO i_EX_stage_OoO(
.instr_cnt(instr_cnt),
.cycle_cnt(cycle_cnt),
.rs_data(rs_data_IS_EX_alu),
.rt_data(rt_data_IS_EX_alu),
.pc_1(pc_1_IS_EX),
.immed_value(immed_value_IS_EX_alu),
.opcode(opcode_IS_EX),
.ldic(ldic_IS_EX),
.isSignEx(isSignedEx_IS_EX),
.immed(immed_IS_EX_alu),
.alu_ctrl0(alu_ctrl0_IS_EX),
.alu_ctrl1(alu_ctrl1_IS_EX),
.alu_ctrl2(alu_ctrl2_IS_EX),
.alu_ctrl3(alu_ctrl3_IS_EX),
.isJump(isJump_IS_EX),
.isJR(isJR_IS_EX),
.link(link_IS_EX),
.alu_result(alu_result_EX),
.changeFlow(changeFlow_EX),
.jb_addr(jb_addr_EX));
wire [5:0] p_rd_EX_alu;
assign p_rd_EX_alu = link ? 6'h19 : p_rd_IS_EX_alu; //don't use $r31 in assembly code
/////////////////////////////////physical register for MEM////////////////////////////
//////////////////////////////////
//physical register serves as part of IS_EX pipeline register
wire [31:0] rs_data_IS_EX_ls, rt_data_IS_EX_ls;
physical_register i_physical_register_LS(
.raddr0(p_rs_lss),
.raddr1(p_rt_lss),
.we(RegDest_compl),
.waddr(p_rd_compl),
.din(result_compl),
.clk(clk),
.dout0(rs_data_IS_EX_ls),
.dout1(rt_data_IS_EX_ls));
/////////////IS_EX pipeline register, for LS/ST/////////////////////////////////////
///*****************WILL CONSIDER STALL HERE later
reg [5:0] p_rd_IS_EX_ls;
reg [15:0] immed_IS_EX_ls;
reg [3:0] rob_num_IS_EX_ls;
reg RegDest_IS_EX_ls;
reg mem_ren_IS_EX_ls;
reg mem_wen_IS_EX_ls;
reg issue_IS_EX_ls;
always @(posedge clk or negedge rst) begin
if (!rst) begin
{p_rd_IS_EX_ls, immed_IS_EX_ls, rob_num_IS_EX_ls} <= 0;
{RegDest_IS_EX_ls, mem_ren_IS_EX_ls, mem_wen_IS_EX_ls, issue_IS_EX_ls} <= 0;
end
else if ((recover && (rob_num_IS_EX_ls == flush_rob_num)) || (!issue_lss)) begin
{RegDest_IS_EX_ls, mem_ren_IS_EX_ls, mem_wen_IS_EX_ls, issue_IS_EX_ls} <= 0;
end
else begin
{p_rd_IS_EX_ls, immed_IS_EX_ls, rob_num_IS_EX_ls} <= {p_rd_lss, immed_lss, rob_num_lss};
{RegDest_IS_EX_ls, mem_ren_IS_EX_ls, mem_wen_IS_EX_ls, issue_IS_EX_ls} <= {RegDest_lss, mem_ren_lss, mem_wen_lss, issue_lss};
end
end
/////////////////////////////store queue/////////////////////////////
////////temporary wires/////////////
wire hazard_stall_store_queue; assign hazard_stall_store_queue = 0;
///////////////////////////////////
wire sq_full;
wire isLS_CMP; //************************need to check later***********************//
wire [31:0] load_result_CMP;
wire [5:0] ls_p_rd_CMP;
wire [3:0] ls_rob_CMP;
wire ls_RegDest_CMP;
////////////////////////////first connect the complete from store queue
store_queue i_store_queue(
.clk(clk),
.rst(rst),
.issue(issue_IS_EX_ls),
.mem_wen(mem_wen_IS_EX_ls),
.mem_ren(mem_ren_IS_EX_ls),
.rs_data(rs_data_IS_EX_ls),
.rt_data(rt_data_IS_EX_ls),
.immed(immed_IS_EX_ls),
.rob_in(rob_num_IS_EX_ls),
.p_rd_in(p_rd_IS_EX_ls),
.stall_hazard(hazard_stall_store_queue),
.retire_ST(retire_ST),
.retire_rob(retire_rob),
.recover(recover),
.rec_rob(flush_rob_num),
.sq_full(sq_full),
.isLS(isLS_CMP),
.load_result(load_result_CMP),
.ls_p_rd(ls_p_rd_CMP),
.ls_rob(ls_rob_CMP),
.ls_RegDest(ls_RegDest_CMP));
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_eclbyplog.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_eclbyplog
// Description: This block implements the bypass logic for a single
// operand. It takes the destination registers of all
// four forwarding sources and the rs. It also has the
// thread for the instruction in each stage and whether
// the instruction writes to the register file. It won't
// bypass if rs =0.
*/
module sparc_exu_eclbyplog (/*AUTOARG*/
// Outputs
rs_sel_mux1_m, rs_sel_mux1_w, rs_sel_mux1_w2, rs_sel_mux1_other,
rs_sel_mux2_usemux1, rs_sel_mux2_rf, rs_sel_mux2_e,
rs_sel_mux2_ld, rs_sel_longmux_g2, rs_sel_longmux_w2,
rs_sel_longmux_ldxa,
// Inputs
sehold, use_other, rs, rd_e, rd_m, ecl_irf_rd_w, ld_rd_g,
wb_byplog_rd_w2, wb_byplog_rd_g2, tid_d, thr_match_de,
thr_match_dm, ecl_irf_tid_w, ld_thr_match_dg, wb_byplog_tid_w2,
ld_thr_match_dg2, ifu_exu_kill_e, wb_e, bypass_m,
lsu_exu_dfill_vld_g, bypass_w, wb_byplog_wen_w2, wb_byplog_wen_g2,
ecl_byp_ldxa_g
) ;
input sehold;
input use_other;
input [4:0] rs; // source register
input [4:0] rd_e; // destination regs for all stages
input [4:0] rd_m;
input [4:0] ecl_irf_rd_w;
input [4:0] ld_rd_g;
input [4:0] wb_byplog_rd_w2;
input [4:0] wb_byplog_rd_g2;
input [1:0] tid_d;
input thr_match_de;
input thr_match_dm;
input [1:0] ecl_irf_tid_w;
input ld_thr_match_dg;
input [1:0] wb_byplog_tid_w2;
input ld_thr_match_dg2;
input ifu_exu_kill_e;
input wb_e; // whether each stage writes to reg
input bypass_m; // file
input lsu_exu_dfill_vld_g;
input bypass_w;
input wb_byplog_wen_w2;
input wb_byplog_wen_g2;
input ecl_byp_ldxa_g;
output rs_sel_mux1_m;
output rs_sel_mux1_w;
output rs_sel_mux1_w2;
output rs_sel_mux1_other;
output rs_sel_mux2_usemux1;
output rs_sel_mux2_rf;
output rs_sel_mux2_e;
output rs_sel_mux2_ld;
output rs_sel_longmux_g2;
output rs_sel_longmux_w2;
output rs_sel_longmux_ldxa;
wire use_e, use_m, use_w, use_w2, use_rf, use_ld, use_ldxa;
wire match_e, match_m, match_w, match_w2, match_ld; // outputs of comparison
wire match_g2;
wire bypass; // boolean that allows bypassing
wire rs_is_nonzero;
// Don't bypass if rs == 0 or we are supposed to use other
assign rs_is_nonzero = rs[0]|rs[1]|rs[2]|rs[3]|rs[4];
assign bypass = rs_is_nonzero & ~use_other & ~sehold;
// Normal pipe priority: E, M, W, RF
// Ld priority: LD, RF
// W2 priority: E, M, W2, RF
assign use_e = match_e & wb_e & ~ifu_exu_kill_e;
assign use_m = match_m & bypass_m & ~use_e;
assign use_w = match_w & bypass_w & ~use_m & ~use_e;
assign use_ld = match_ld & lsu_exu_dfill_vld_g & ~ecl_byp_ldxa_g;
assign use_ldxa = match_ld & ecl_byp_ldxa_g;
assign use_w2 = (match_w2 & wb_byplog_wen_w2 | match_g2 & wb_byplog_wen_g2) & ~use_e & ~use_m;
assign use_rf = ~use_w2 & ~use_w & ~use_m & ~use_e & ~use_ld & ~use_ldxa;
// mux1[M, W, W2, OTHER(optional)]
// mux2[mux1, RF, E, LD]
assign rs_sel_mux2_e = (use_e & bypass);
assign rs_sel_mux2_rf = ((use_rf | ~bypass) & ~(use_other & ~sehold));
assign rs_sel_mux2_ld = (use_ld & ~use_e & ~use_w & ~use_m & ~use_w2 & bypass);
assign rs_sel_mux2_usemux1 = (use_other & ~sehold) | (~rs_sel_mux1_other & ~use_e);
assign rs_sel_mux1_other = ~((use_m | use_w | use_w2 | use_ldxa) & bypass);
assign rs_sel_mux1_w2 = ((use_w2 | use_ldxa) & bypass);
assign rs_sel_mux1_w = (use_w & ~use_w2 & ~use_ldxa & bypass);
assign rs_sel_mux1_m = (use_m & ~use_w2 & ~use_ldxa & bypass);
assign rs_sel_longmux_ldxa = use_ldxa;
assign rs_sel_longmux_g2 = match_g2 & wb_byplog_wen_g2 & ~use_ldxa;
assign rs_sel_longmux_w2 = ~use_ldxa & ~(match_g2 & wb_byplog_wen_g2);
// Comparisons
assign match_e = thr_match_de & (rs[4:0] == rd_e[4:0]);
// sparc_exu_eclcomp7 e_comp7(.out(match_e), .in1({tid_d[1:0],rs[4:0]}),
// .in2({ecl_rml_tid_e[1:0],rd_e[4:0]}));
assign match_m = thr_match_dm & (rs[4:0] == rd_m[4:0]);
// sparc_exu_eclcomp7 m_comp7(.out(match_m), .in1({tid_d[1:0],rs[4:0]}),
// .in2({tid_m[1:0],rd_m[4:0]}));
sparc_exu_eclcomp7 w_comp7(.out(match_w), .in1({tid_d[1:0],rs[4:0]}),
.in2({ecl_irf_tid_w[1:0],ecl_irf_rd_w[4:0]}));
sparc_exu_eclcomp7 w2_comp7(.out(match_w2), .in1({tid_d[1:0],rs[4:0]}),
.in2({wb_byplog_tid_w2[1:0],wb_byplog_rd_w2[4:0]}));
assign match_ld = ld_thr_match_dg & (rs[4:0] == ld_rd_g[4:0]);
assign match_g2 = ld_thr_match_dg2 & (rs[4:0] == wb_byplog_rd_g2[4:0]);
/* -----\/----- EXCLUDED -----\/-----
sparc_exu_eclcomp7 ld_comp7(.out(match_ld), .in1({tid_d[1:0],rs[4:0]}),
.in2({ld_tid_g[1:0],ld_rd_g[4:0]}));
sparc_exu_eclcomp7 g2_comp7(.out(match_g2), .in1({tid_d[1:0],rs[4:0]}),
.in2({wb_byplog_tid_g2[1:0],wb_byplog_rd_g2[4:0]}));
-----/\----- EXCLUDED -----/\----- */
endmodule // sparc_exu_eclbyplog
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_2_V
`define SKY130_FD_SC_HDLL__CLKINVLP_2_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinvlp_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinvlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_2_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Mon Oct 10 15:12:21 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, left_right_SHT2, bit_shift_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674,
n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684,
n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757,
n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767,
n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777,
n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787,
n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797,
n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807,
n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817,
n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827,
n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837,
n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847,
n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857,
n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867,
n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877,
n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887,
n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897,
n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907,
n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917,
n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927,
n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937,
n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947,
n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957,
n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967,
n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977,
n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987,
n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997,
n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007,
n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017,
n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027,
n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037,
n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047,
n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057,
n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067,
n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077,
n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087,
n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097,
n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107,
n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117,
n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127,
n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137,
n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147,
n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157,
n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167,
n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177,
n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187,
n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197,
n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207,
n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217,
n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227,
n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237,
n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247,
n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257,
n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267,
n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277,
n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287,
n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297,
n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307,
n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317,
n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327,
n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337,
n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347,
n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357,
n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367,
n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377,
n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387,
n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397,
n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407,
n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417,
n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427,
n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437,
n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447,
n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457,
n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467,
n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477,
n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487,
n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497,
n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507,
n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517,
n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527,
n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537,
n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547,
n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557,
n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567,
n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577,
n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587,
n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597,
n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607,
n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617,
n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627,
n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637,
n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647,
n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657,
n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667,
n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677,
n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687,
n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697,
n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707,
n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717,
n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727,
n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737,
n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747,
n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757,
n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767,
n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777,
n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787,
n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797,
n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807,
n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817,
n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827,
n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837,
n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845, n3846, n3847,
n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855, n3856, n3857,
n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865, n3866, n3867,
n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875, n3876, n3877,
n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885, n3886, n3887,
n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895, n3896, n3897,
n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905, n3906, n3907,
n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917,
n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927,
n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937,
n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947,
n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957,
n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967,
n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977,
n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987,
n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997,
n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007,
n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017,
n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027,
n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037,
n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047,
n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057,
n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067,
n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077,
n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087,
n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097,
n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107,
n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117,
n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127,
n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137,
n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147,
n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157,
n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167,
n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177,
n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187,
n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197,
n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207,
n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217,
n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227,
n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237,
n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247,
n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257,
n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267,
n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277,
n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287,
n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297,
n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307,
n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317,
n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327,
n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337,
n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347,
n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357,
n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367,
n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377,
n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4386;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [54:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [62:0] DMP_SFG;
wire [54:1] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1891), .CK(clk), .RN(
n4305), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n4305), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n4060) );
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1890), .CK(clk), .RN(
n4305), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n4221) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1889), .CK(clk), .RN(n4305), .Q(
Shift_reg_FLAGS_7_6), .QN(n4065) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(n1888), .CK(clk), .RN(n4305), .Q(
Shift_reg_FLAGS_7_5), .QN(n4280) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n1886), .CK(clk), .RN(n4305), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n1885), .CK(clk), .RN(n4383), .Q(
Shift_reg_FLAGS_7[2]), .QN(n4013) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n1884), .CK(clk), .RN(n4382), .Q(
Shift_reg_FLAGS_7[1]), .QN(n4271) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n1883), .CK(clk), .RN(n4305), .Q(
Shift_reg_FLAGS_7[0]), .QN(n4229) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1882), .CK(clk), .RN(n4305),
.Q(intDX_EWSW[0]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1881), .CK(clk), .RN(n4305),
.Q(intDX_EWSW[1]), .QN(n4222) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1880), .CK(clk), .RN(n4305),
.Q(intDX_EWSW[2]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1879), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[3]), .QN(n4131) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1878), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[4]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1877), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[5]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1876), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[6]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1875), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[7]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1874), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[8]), .QN(n4158) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1873), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[9]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1872), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[10]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1871), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[11]), .QN(n4155) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1870), .CK(clk), .RN(n4306),
.Q(intDX_EWSW[12]), .QN(n4150) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1869), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[13]), .QN(n4144) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1868), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[14]), .QN(n4133) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1867), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[15]), .QN(n4026) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1866), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[16]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1865), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[17]), .QN(n4156) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1864), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[18]), .QN(n4049) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1863), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[19]), .QN(n4162) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1862), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[20]), .QN(n4149) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1861), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[21]), .QN(n4145) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1860), .CK(clk), .RN(n4307),
.Q(intDX_EWSW[22]), .QN(n4164) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1859), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[23]), .QN(n4027) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1858), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[24]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1857), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[25]), .QN(n4154) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1856), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[26]), .QN(n4050) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1855), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[27]), .QN(n4161) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1854), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[28]), .QN(n4148) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1853), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[29]), .QN(n4143) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1852), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[30]), .QN(n4163) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1851), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[31]), .QN(n4025) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1850), .CK(clk), .RN(n4308),
.Q(intDX_EWSW[32]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1849), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[33]), .QN(n4140) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1848), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[34]), .QN(n4152) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1847), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[35]), .QN(n4023) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1846), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[36]), .QN(n4142) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1845), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[37]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1844), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[38]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1843), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[39]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1842), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[40]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1841), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[41]), .QN(n4141) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1840), .CK(clk), .RN(n4309),
.Q(intDX_EWSW[42]), .QN(n4151) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1839), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[43]), .QN(n4022) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1838), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[44]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1837), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[45]), .QN(n4153) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1836), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[46]), .QN(n4146) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1835), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[47]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1834), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[48]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1833), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[49]), .QN(n4159) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1832), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[50]), .QN(n4047) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1831), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[51]), .QN(n4157) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1830), .CK(clk), .RN(n4310),
.Q(intDX_EWSW[52]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1829), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[53]), .QN(n4267) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1828), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[54]), .QN(n4095) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1827), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[55]), .QN(n4268) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1826), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[56]), .QN(n4094) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1825), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[57]), .QN(n4160) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1824), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[58]), .QN(n4035) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1823), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[59]), .QN(n4191) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1822), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[60]), .QN(n4147) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1821), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[61]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1820), .CK(clk), .RN(n4311),
.Q(intDX_EWSW[62]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1819), .CK(clk), .RN(n4312),
.Q(intDX_EWSW[63]) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1818), .CK(clk), .RN(n4312), .Q(
intAS) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1817), .CK(clk), .RN(n4312),
.Q(intDY_EWSW[0]), .QN(n4043) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1816), .CK(clk), .RN(n4312),
.Q(intDY_EWSW[1]), .QN(n4210) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1815), .CK(clk), .RN(n4312),
.Q(intDY_EWSW[2]), .QN(n4182) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1814), .CK(clk), .RN(n4312),
.Q(intDY_EWSW[3]), .QN(n4037) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1813), .CK(clk), .RN(n4312),
.Q(intDY_EWSW[4]), .QN(n4052) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1812), .CK(clk), .RN(n4312),
.QN(n4207) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1811), .CK(clk), .RN(n4312),
.Q(intDY_EWSW[6]), .QN(n4066) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1810), .CK(clk), .RN(n4312),
.QN(n4219) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1809), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[8]), .QN(n4178) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1808), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[9]), .QN(n4174) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1807), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[10]), .QN(n4173) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1806), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[11]), .QN(n4061) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1805), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[12]), .QN(n4175) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1804), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[13]), .QN(n4171) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1803), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[14]), .QN(n4216) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1802), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[15]), .QN(n4062) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1801), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[16]), .QN(n4193) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1800), .CK(clk), .RN(n4313),
.Q(intDY_EWSW[17]), .QN(n4039) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1799), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[18]), .QN(n4179) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1798), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[19]), .QN(n4041) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1797), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[20]), .QN(n4176) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1796), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[21]), .QN(n4172) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1795), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[22]), .QN(n4217) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1794), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[23]), .QN(n4063) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1793), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[24]), .QN(n4181) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1792), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[25]), .QN(n4040) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1791), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[26]), .QN(n4180) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1790), .CK(clk), .RN(n4314),
.Q(intDY_EWSW[27]), .QN(n4042) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1789), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[28]), .QN(n4177) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1788), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[29]), .QN(n4038) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1787), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[30]), .QN(n4218) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1786), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[31]), .QN(n4064) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1785), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[32]), .QN(n4183) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1784), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[33]), .QN(n4054) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1783), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[34]), .QN(n4199) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1782), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[35]), .QN(n4055) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1781), .CK(clk), .RN(n4315),
.Q(intDY_EWSW[36]), .QN(n4196) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1780), .CK(clk), .RN(n4315),
.QN(n4204) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1779), .CK(clk), .RN(n4316),
.QN(n4205) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1778), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[39]), .QN(n4201) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1777), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[40]), .QN(n4202) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1776), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[41]), .QN(n4058) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1775), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[42]), .QN(n4200) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1774), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[43]), .QN(n4056) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1773), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[44]), .QN(n4197) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1772), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[45]), .QN(n4195) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1771), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[46]), .QN(n4057) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1770), .CK(clk), .RN(n4316),
.Q(intDY_EWSW[47]), .QN(n4203) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1769), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[48]), .QN(n4192) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1768), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[49]), .QN(n4208) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1767), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[50]), .QN(n4059) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1766), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[51]), .QN(n4198) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1765), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[52]), .QN(n4220) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1764), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[53]), .QN(n4053) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1763), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[54]), .QN(n4036) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1762), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[55]), .QN(n4012) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1761), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[56]), .QN(n4014) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1760), .CK(clk), .RN(n4317),
.Q(intDY_EWSW[57]), .QN(n4206) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1759), .CK(clk), .RN(n4318),
.Q(intDY_EWSW[58]), .QN(n4045) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1758), .CK(clk), .RN(n4318),
.Q(intDY_EWSW[59]), .QN(n4213) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1757), .CK(clk), .RN(n4318),
.Q(intDY_EWSW[60]), .QN(n4184) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1756), .CK(clk), .RN(n4318),
.QN(n4215) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1755), .CK(clk), .RN(n4318),
.Q(intDY_EWSW[62]), .QN(n4209) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1754), .CK(clk), .RN(n4318),
.Q(intDY_EWSW[63]) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n1935), .CK(clk), .RN(n4318), .Q(ready) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n1753), .CK(clk), .RN(n4318),
.Q(bit_shift_SHT2), .QN(n4188) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1752), .CK(clk), .RN(n4318),
.Q(left_right_SHT2), .QN(n4194) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1696), .CK(clk), .RN(n4318),
.Q(shift_value_SHT2_EWR[2]), .QN(n4021) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1695), .CK(clk), .RN(n4319),
.Q(shift_value_SHT2_EWR[3]), .QN(n4136) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1694), .CK(clk), .RN(n4319),
.Q(shift_value_SHT2_EWR[4]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1725), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[26]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1724), .CK(clk), .RN(n4361), .Q(
Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1751), .CK(clk), .RN(n4366), .Q(
Data_array_SWR[0]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1750), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[1]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1749), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1748), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1747), .CK(clk), .RN(n4365), .Q(
Data_array_SWR[4]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1746), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[5]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1745), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[6]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1744), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[7]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1743), .CK(clk), .RN(n4368), .Q(
Data_array_SWR[8]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1742), .CK(clk), .RN(n4365), .Q(
Data_array_SWR[9]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1741), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[10]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1740), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[11]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1735), .CK(clk), .RN(n4368), .Q(
Data_array_SWR[16]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1734), .CK(clk), .RN(n4365), .Q(
Data_array_SWR[17]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1733), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[18]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1731), .CK(clk), .RN(n4369), .Q(
Data_array_SWR[20]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1729), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[22]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1728), .CK(clk), .RN(n4361), .Q(
Data_array_SWR[23]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1727), .CK(clk), .RN(n4369), .Q(
Data_array_SWR[24]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1723), .CK(clk), .RN(n4368), .Q(
Data_array_SWR[28]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1721), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[30]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1720), .CK(clk), .RN(n4361), .Q(
Data_array_SWR[31]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1719), .CK(clk), .RN(n4370), .Q(
Data_array_SWR[32]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1717), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[34]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1715), .CK(clk), .RN(n4372), .Q(
Data_array_SWR[36]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1713), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[38]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1698), .CK(clk), .RN(n4367), .Q(
Data_array_SWR[53]), .QN(n4242) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1697), .CK(clk), .RN(n4355), .Q(
Data_array_SWR[54]), .QN(n4243) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1692), .CK(clk), .RN(n4319),
.Q(shift_value_SHT2_EWR[5]), .QN(n4187) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n4355),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1690), .CK(clk), .RN(n4365),
.Q(Shift_amount_SHT1_EWR[1]), .QN(n4265) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1689), .CK(clk), .RN(n4319),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1688), .CK(clk), .RN(n4319),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1687), .CK(clk), .RN(n4319),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1686), .CK(clk), .RN(n4319),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1674), .CK(clk), .RN(n4319), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1673), .CK(clk), .RN(n4319), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1672), .CK(clk), .RN(n4319), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1671), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1670), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1669), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1668), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1667), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1666), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1665), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1664), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1663), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1662), .CK(clk), .RN(n4320), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1661), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1660), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1659), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1658), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1657), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1656), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1655), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1654), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1653), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1652), .CK(clk), .RN(n4321), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1651), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1650), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1649), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1648), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1647), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1646), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1645), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1644), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1643), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1642), .CK(clk), .RN(n4322), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1641), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1640), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1639), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1638), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1637), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1636), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1635), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1634), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1633), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1632), .CK(clk), .RN(n4323), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1631), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1630), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1629), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1628), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1627), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1626), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1625), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1624), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1623), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1622), .CK(clk), .RN(n4324), .Q(
DMP_EXP_EWSW[52]), .QN(n4225) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1621), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[53]), .QN(n4211) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1620), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[54]), .QN(n4224) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1619), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[55]), .QN(n4212) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1618), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[56]), .QN(n4269) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1617), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[57]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1616), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1615), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1614), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1613), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1612), .CK(clk), .RN(n4325), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1611), .CK(clk), .RN(n4326), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1610), .CK(clk), .RN(n4326), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1609), .CK(clk), .RN(n4326), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n4326), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1607), .CK(clk), .RN(n4375), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1605), .CK(clk), .RN(n4326), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1604), .CK(clk), .RN(n4375), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1603), .CK(clk), .RN(n4375), .Q(
DMP_SFG[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n4326), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1601), .CK(clk), .RN(n4375), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1600), .CK(clk), .RN(n4375), .Q(
DMP_SFG[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1599), .CK(clk), .RN(n4326), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1598), .CK(clk), .RN(n4375), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1597), .CK(clk), .RN(n4375), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1596), .CK(clk), .RN(n4326), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1595), .CK(clk), .RN(n4383), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1593), .CK(clk), .RN(n4326), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1592), .CK(clk), .RN(n4383), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1591), .CK(clk), .RN(n4383), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1590), .CK(clk), .RN(n4326), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1589), .CK(clk), .RN(n4383), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1588), .CK(clk), .RN(n4383), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1586), .CK(clk), .RN(n4383), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1584), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1583), .CK(clk), .RN(n4384), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1582), .CK(clk), .RN(n4386), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1581), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1580), .CK(clk), .RN(n4376), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1579), .CK(clk), .RN(n4376), .Q(
DMP_SFG[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1578), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n4376), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1576), .CK(clk), .RN(n4376), .Q(
DMP_SFG[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1575), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1574), .CK(clk), .RN(n4376), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1573), .CK(clk), .RN(n4376), .Q(
DMP_SFG[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1572), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1571), .CK(clk), .RN(n4376), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1570), .CK(clk), .RN(n4376), .Q(
DMP_SFG[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1569), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1568), .CK(clk), .RN(n4376), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1567), .CK(clk), .RN(n4376), .Q(
DMP_SFG[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1566), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1565), .CK(clk), .RN(n4377), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1564), .CK(clk), .RN(n4377), .Q(
DMP_SFG[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1563), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1562), .CK(clk), .RN(n4377), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1560), .CK(clk), .RN(n4327), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1559), .CK(clk), .RN(n4377), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1557), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1556), .CK(clk), .RN(n4377), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1555), .CK(clk), .RN(n4377), .Q(
DMP_SFG[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1554), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1553), .CK(clk), .RN(n4377), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1552), .CK(clk), .RN(n4377), .Q(
DMP_SFG[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1551), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1550), .CK(clk), .RN(n4378), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1548), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1547), .CK(clk), .RN(n4378), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1546), .CK(clk), .RN(n4378), .Q(
DMP_SFG[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1545), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1544), .CK(clk), .RN(n4378), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1543), .CK(clk), .RN(n4378), .Q(
DMP_SFG[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1542), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1541), .CK(clk), .RN(n4378), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1540), .CK(clk), .RN(n4378), .Q(
DMP_SFG[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1539), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1538), .CK(clk), .RN(n4378), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1537), .CK(clk), .RN(n4378), .Q(
DMP_SFG[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1536), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1535), .CK(clk), .RN(n4379), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1534), .CK(clk), .RN(n4379), .Q(
DMP_SFG[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1533), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1532), .CK(clk), .RN(n4379), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1531), .CK(clk), .RN(n4379), .Q(
DMP_SFG[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1530), .CK(clk), .RN(n4328), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1529), .CK(clk), .RN(n4379), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1528), .CK(clk), .RN(n4379), .Q(
DMP_SFG[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1527), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1526), .CK(clk), .RN(n4379), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1525), .CK(clk), .RN(n4379), .Q(
DMP_SFG[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1524), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1523), .CK(clk), .RN(n4379), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1522), .CK(clk), .RN(n4379), .Q(
DMP_SFG[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1521), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1520), .CK(clk), .RN(n4380), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1519), .CK(clk), .RN(n4380), .Q(
DMP_SFG[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1518), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1517), .CK(clk), .RN(n4380), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1516), .CK(clk), .RN(n4380), .Q(
DMP_SFG[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1515), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1514), .CK(clk), .RN(n4380), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1513), .CK(clk), .RN(n4380), .Q(
DMP_SFG[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1512), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1511), .CK(clk), .RN(n4380), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1510), .CK(clk), .RN(n4380), .Q(
DMP_SFG[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1509), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1508), .CK(clk), .RN(n4380), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1507), .CK(clk), .RN(n4380), .Q(
DMP_SFG[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1506), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1505), .CK(clk), .RN(n4381), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1504), .CK(clk), .RN(n4381), .Q(
DMP_SFG[34]), .QN(n1941) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1503), .CK(clk), .RN(n4329), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1502), .CK(clk), .RN(n4329), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1501), .CK(clk), .RN(n4381), .Q(
DMP_SFG[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1500), .CK(clk), .RN(n4330), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1499), .CK(clk), .RN(n4330), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1498), .CK(clk), .RN(n4381), .Q(
DMP_SFG[36]), .QN(n1937) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1497), .CK(clk), .RN(n4330), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1496), .CK(clk), .RN(n4330), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1495), .CK(clk), .RN(n4381), .Q(
DMP_SFG[37]), .QN(n1938) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1494), .CK(clk), .RN(n4330), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1493), .CK(clk), .RN(n4330), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1492), .CK(clk), .RN(n4381), .Q(
DMP_SFG[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1491), .CK(clk), .RN(n4330), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1490), .CK(clk), .RN(n4330), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1489), .CK(clk), .RN(n4381), .Q(
DMP_SFG[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1488), .CK(clk), .RN(n4330), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1487), .CK(clk), .RN(n4330), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1486), .CK(clk), .RN(n4381), .Q(
DMP_SFG[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1485), .CK(clk), .RN(n4331), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1484), .CK(clk), .RN(n4331), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1483), .CK(clk), .RN(n4381), .Q(
DMP_SFG[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1482), .CK(clk), .RN(n4331), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1481), .CK(clk), .RN(n4331), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1480), .CK(clk), .RN(n4381), .Q(
DMP_SFG[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1479), .CK(clk), .RN(n4331), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1478), .CK(clk), .RN(n4331), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1477), .CK(clk), .RN(n4382), .Q(
DMP_SFG[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1476), .CK(clk), .RN(n4331), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1475), .CK(clk), .RN(n4331), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1474), .CK(clk), .RN(n4382), .Q(
DMP_SFG[44]), .QN(n1939) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1473), .CK(clk), .RN(n4331), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1472), .CK(clk), .RN(n4331), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1471), .CK(clk), .RN(n4382), .Q(
DMP_SFG[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1470), .CK(clk), .RN(n4332), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1469), .CK(clk), .RN(n4332), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1468), .CK(clk), .RN(n4382), .Q(
DMP_SFG[46]), .QN(n1940) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1467), .CK(clk), .RN(n4332), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1466), .CK(clk), .RN(n4332), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1465), .CK(clk), .RN(n4382), .Q(
DMP_SFG[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1464), .CK(clk), .RN(n4332), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1463), .CK(clk), .RN(n4332), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1462), .CK(clk), .RN(n4382), .Q(
DMP_SFG[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1461), .CK(clk), .RN(n4332), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1460), .CK(clk), .RN(n4332), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1459), .CK(clk), .RN(n4382), .Q(
DMP_SFG[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1458), .CK(clk), .RN(n4332), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1457), .CK(clk), .RN(n4332), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1456), .CK(clk), .RN(n4382), .Q(
DMP_SFG[50]), .QN(n1898) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1455), .CK(clk), .RN(n4333), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1454), .CK(clk), .RN(n4333), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1453), .CK(clk), .RN(n4382), .Q(
DMP_SFG[51]), .QN(n1899) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1452), .CK(clk), .RN(n4333), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1451), .CK(clk), .RN(n4333), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1450), .CK(clk), .RN(n4333), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1449), .CK(clk), .RN(n4333), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1448), .CK(clk), .RN(n4354), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1447), .CK(clk), .RN(n4333), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1446), .CK(clk), .RN(n4333), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1445), .CK(clk), .RN(n4333), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1444), .CK(clk), .RN(n4333), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1443), .CK(clk), .RN(n4354), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1442), .CK(clk), .RN(n4334), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1441), .CK(clk), .RN(n4334), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1440), .CK(clk), .RN(n4334), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1439), .CK(clk), .RN(n4334), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1438), .CK(clk), .RN(n4354), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1437), .CK(clk), .RN(n4334), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1436), .CK(clk), .RN(n4334), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1435), .CK(clk), .RN(n4334), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1434), .CK(clk), .RN(n4334), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1433), .CK(clk), .RN(n4354), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1432), .CK(clk), .RN(n4334), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1431), .CK(clk), .RN(n4334), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1430), .CK(clk), .RN(n4335), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1429), .CK(clk), .RN(n4335), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1428), .CK(clk), .RN(n4354), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1427), .CK(clk), .RN(n4335), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1426), .CK(clk), .RN(n4335), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1425), .CK(clk), .RN(n4335), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1424), .CK(clk), .RN(n4335), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1423), .CK(clk), .RN(n4354), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1422), .CK(clk), .RN(n4335), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1421), .CK(clk), .RN(n4335), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1420), .CK(clk), .RN(n4335), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1419), .CK(clk), .RN(n4335), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1418), .CK(clk), .RN(n4354), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1417), .CK(clk), .RN(n4336), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1416), .CK(clk), .RN(n4336), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1415), .CK(clk), .RN(n4336), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1414), .CK(clk), .RN(n4336), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1413), .CK(clk), .RN(n4355), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1412), .CK(clk), .RN(n4336), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1411), .CK(clk), .RN(n4336), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1410), .CK(clk), .RN(n4336), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1409), .CK(clk), .RN(n4336), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1408), .CK(clk), .RN(n4355), .Q(
DMP_exp_NRM2_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1407), .CK(clk), .RN(n4336), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1406), .CK(clk), .RN(n4336), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1405), .CK(clk), .RN(n4337), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1404), .CK(clk), .RN(n4337), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1403), .CK(clk), .RN(n4355), .Q(
DMP_exp_NRM2_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1402), .CK(clk), .RN(n4337), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1401), .CK(clk), .RN(n4337), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1400), .CK(clk), .RN(n4337), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1399), .CK(clk), .RN(n4337), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1398), .CK(clk), .RN(n4355),
.Q(DMP_exp_NRM2_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1397), .CK(clk), .RN(n4337), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1396), .CK(clk), .RN(n4367), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1395), .CK(clk), .RN(n4337), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1394), .CK(clk), .RN(n4367), .Q(
DmP_mant_SHT1_SW[1]), .QN(n4263) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1393), .CK(clk), .RN(n4337), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1392), .CK(clk), .RN(n4366), .Q(
DmP_mant_SHT1_SW[2]), .QN(n4291) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1391), .CK(clk), .RN(n4337), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1390), .CK(clk), .RN(n4366), .Q(
DmP_mant_SHT1_SW[3]), .QN(n4290) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(n4338), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1388), .CK(clk), .RN(n4366), .Q(
DmP_mant_SHT1_SW[4]), .QN(n4264) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1387), .CK(clk), .RN(n4338), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1386), .CK(clk), .RN(n4338), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n4338), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(n4368), .Q(
DmP_mant_SHT1_SW[6]), .QN(n4288) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1383), .CK(clk), .RN(n4338), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1382), .CK(clk), .RN(n4338), .Q(
DmP_mant_SHT1_SW[7]), .QN(n4300) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1381), .CK(clk), .RN(n4338), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1380), .CK(clk), .RN(n4368), .Q(
DmP_mant_SHT1_SW[8]), .QN(n4261) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1379), .CK(clk), .RN(n4338), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1378), .CK(clk), .RN(n4338), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1377), .CK(clk), .RN(n4338), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1376), .CK(clk), .RN(n4368),
.Q(DmP_mant_SHT1_SW[10]), .QN(n4289) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1375), .CK(clk), .RN(n4339), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1374), .CK(clk), .RN(n4339),
.Q(DmP_mant_SHT1_SW[11]), .QN(n4301) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1373), .CK(clk), .RN(n4339), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1372), .CK(clk), .RN(n4368),
.Q(DmP_mant_SHT1_SW[12]), .QN(n4262) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1371), .CK(clk), .RN(n4339), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1370), .CK(clk), .RN(n4339),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(n4339), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(n4369),
.Q(DmP_mant_SHT1_SW[14]), .QN(n4287) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1367), .CK(clk), .RN(n4339), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1366), .CK(clk), .RN(n4339),
.Q(DmP_mant_SHT1_SW[15]), .QN(n4299) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1365), .CK(clk), .RN(n4339), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1364), .CK(clk), .RN(n4369),
.Q(DmP_mant_SHT1_SW[16]), .QN(n4260) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1363), .CK(clk), .RN(n4339), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1362), .CK(clk), .RN(n4340),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1361), .CK(clk), .RN(n4340), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1360), .CK(clk), .RN(n4370),
.Q(DmP_mant_SHT1_SW[18]), .QN(n4285) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1359), .CK(clk), .RN(n4340), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1358), .CK(clk), .RN(n4340),
.Q(DmP_mant_SHT1_SW[19]), .QN(n4297) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1357), .CK(clk), .RN(n4340), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1356), .CK(clk), .RN(n4370),
.Q(DmP_mant_SHT1_SW[20]), .QN(n4258) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1355), .CK(clk), .RN(n4340), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1354), .CK(clk), .RN(n4340),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1353), .CK(clk), .RN(n4340), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1352), .CK(clk), .RN(n4369),
.Q(DmP_mant_SHT1_SW[22]), .QN(n4286) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1351), .CK(clk), .RN(n4340), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1350), .CK(clk), .RN(n4340),
.Q(DmP_mant_SHT1_SW[23]), .QN(n4298) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1349), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1348), .CK(clk), .RN(n4369),
.Q(DmP_mant_SHT1_SW[24]), .QN(n4259) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1347), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1346), .CK(clk), .RN(n4341),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1345), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1344), .CK(clk), .RN(n4341),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1343), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1342), .CK(clk), .RN(n4368),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1341), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1340), .CK(clk), .RN(n4368),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1339), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1338), .CK(clk), .RN(n4368),
.Q(DmP_mant_SHT1_SW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1337), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1336), .CK(clk), .RN(n4370),
.Q(DmP_mant_SHT1_SW[30]), .QN(n4284) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1335), .CK(clk), .RN(n4341), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1334), .CK(clk), .RN(n4342),
.Q(DmP_mant_SHT1_SW[31]), .QN(n4296) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1333), .CK(clk), .RN(n4342), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1332), .CK(clk), .RN(n4370),
.Q(DmP_mant_SHT1_SW[32]), .QN(n4257) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1331), .CK(clk), .RN(n4342), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1330), .CK(clk), .RN(n4342),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1329), .CK(clk), .RN(n4342), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1328), .CK(clk), .RN(n4373),
.Q(DmP_mant_SHT1_SW[34]), .QN(n4281) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1327), .CK(clk), .RN(n4342), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1326), .CK(clk), .RN(n4342),
.Q(DmP_mant_SHT1_SW[35]), .QN(n4293) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1325), .CK(clk), .RN(n4342), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1324), .CK(clk), .RN(n4373),
.Q(DmP_mant_SHT1_SW[36]), .QN(n4254) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1323), .CK(clk), .RN(n4342), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1322), .CK(clk), .RN(n4342),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1321), .CK(clk), .RN(n4343), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1320), .CK(clk), .RN(n4372),
.Q(DmP_mant_SHT1_SW[38]), .QN(n4282) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1319), .CK(clk), .RN(n4343), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1318), .CK(clk), .RN(n4343),
.Q(DmP_mant_SHT1_SW[39]), .QN(n4294) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1317), .CK(clk), .RN(n4343), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1316), .CK(clk), .RN(n4372),
.Q(DmP_mant_SHT1_SW[40]), .QN(n4255) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1315), .CK(clk), .RN(n4343), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1314), .CK(clk), .RN(n4343),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1313), .CK(clk), .RN(n4343), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1312), .CK(clk), .RN(n4371),
.Q(DmP_mant_SHT1_SW[42]), .QN(n4283) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1311), .CK(clk), .RN(n4343), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1310), .CK(clk), .RN(n4343),
.Q(DmP_mant_SHT1_SW[43]), .QN(n4295) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1309), .CK(clk), .RN(n4343), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1308), .CK(clk), .RN(n4371),
.Q(DmP_mant_SHT1_SW[44]), .QN(n4256) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1307), .CK(clk), .RN(n4344), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1306), .CK(clk), .RN(n4344),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1305), .CK(clk), .RN(n4344), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1304), .CK(clk), .RN(n4364),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1303), .CK(clk), .RN(n4344), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1302), .CK(clk), .RN(n4344),
.Q(DmP_mant_SHT1_SW[47]), .QN(n4303) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1301), .CK(clk), .RN(n4344), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1300), .CK(clk), .RN(n4361),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1299), .CK(clk), .RN(n4344), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1298), .CK(clk), .RN(n4344),
.Q(DmP_mant_SHT1_SW[49]), .QN(n4304) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1297), .CK(clk), .RN(n4344), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1296), .CK(clk), .RN(n4362),
.Q(DmP_mant_SHT1_SW[50]), .QN(n4292) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1295), .CK(clk), .RN(n4344), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1294), .CK(clk), .RN(n4345),
.Q(DmP_mant_SHT1_SW[51]), .QN(n4302) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1293), .CK(clk), .RN(n4345), .Q(
DmP_EXP_EWSW[52]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1292), .CK(clk), .RN(n4345), .Q(
DmP_EXP_EWSW[53]), .QN(n4228) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1291), .CK(clk), .RN(n4345), .Q(
DmP_EXP_EWSW[54]), .QN(n4223) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1290), .CK(clk), .RN(n4345), .Q(
DmP_EXP_EWSW[55]), .QN(n4270) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1289), .CK(clk), .RN(n4345), .Q(
DmP_EXP_EWSW[56]), .QN(n4266) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1288), .CK(clk), .RN(n4345), .Q(
DmP_EXP_EWSW[57]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1285), .CK(clk), .RN(n4345), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1284), .CK(clk), .RN(n4346), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1283), .CK(clk), .RN(n4346), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1282), .CK(clk), .RN(n4346), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1281), .CK(clk), .RN(n4346),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1279), .CK(clk), .RN(n4346), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1278), .CK(clk), .RN(n4346), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1277), .CK(clk), .RN(n4375), .Q(
OP_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1276), .CK(clk), .RN(n4355), .Q(
ADD_OVRFLW_NRM) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1274), .CK(clk), .RN(n4346), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1273), .CK(clk), .RN(n4346), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1272), .CK(clk), .RN(n4346), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1271), .CK(clk), .RN(n4347), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1270), .CK(clk), .RN(n4347),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1268), .CK(clk), .RN(n4365), .Q(
Raw_mant_NRM_SWR[0]), .QN(n4273) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1267), .CK(clk), .RN(n4367), .Q(
Raw_mant_NRM_SWR[1]), .QN(n4189) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1266), .CK(clk), .RN(n4367), .Q(
Raw_mant_NRM_SWR[2]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1265), .CK(clk), .RN(n4367), .Q(
Raw_mant_NRM_SWR[3]), .QN(n4031) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1264), .CK(clk), .RN(n4366), .Q(
Raw_mant_NRM_SWR[4]), .QN(n4073) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1263), .CK(clk), .RN(n4366), .Q(
Raw_mant_NRM_SWR[5]), .QN(n4079) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1262), .CK(clk), .RN(n4366), .Q(
Raw_mant_NRM_SWR[6]), .QN(n4044) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1261), .CK(clk), .RN(n4371), .Q(
Raw_mant_NRM_SWR[7]), .QN(n4245) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1260), .CK(clk), .RN(n4371), .Q(
Raw_mant_NRM_SWR[8]), .QN(n4051) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1259), .CK(clk), .RN(n4371), .Q(
Raw_mant_NRM_SWR[9]), .QN(n4068) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1258), .CK(clk), .RN(n4371), .Q(
Raw_mant_NRM_SWR[10]), .QN(n4024) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n4372), .Q(
Raw_mant_NRM_SWR[11]), .QN(n4190) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1256), .CK(clk), .RN(n4372), .Q(
Raw_mant_NRM_SWR[12]), .QN(n4086) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1255), .CK(clk), .RN(n4372), .Q(
Raw_mant_NRM_SWR[13]), .QN(n4092) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1254), .CK(clk), .RN(n4372), .Q(
Raw_mant_NRM_SWR[14]), .QN(n4048) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1253), .CK(clk), .RN(n4372), .Q(
Raw_mant_NRM_SWR[15]), .QN(n4246) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1252), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[16]), .QN(n4046) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1251), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[17]), .QN(n4032) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[18]), .QN(n4076) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1249), .CK(clk), .RN(n4370), .Q(
Raw_mant_NRM_SWR[19]), .QN(n4165) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1248), .CK(clk), .RN(n4370), .Q(
Raw_mant_NRM_SWR[20]), .QN(n4074) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1247), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[21]), .QN(n4020) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1246), .CK(clk), .RN(n4370), .Q(
Raw_mant_NRM_SWR[22]), .QN(n4078) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1245), .CK(clk), .RN(n4369), .Q(
Raw_mant_NRM_SWR[23]), .QN(n4227) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1244), .CK(clk), .RN(n4369), .Q(
Raw_mant_NRM_SWR[24]), .QN(n4018) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1243), .CK(clk), .RN(n4369), .Q(
Raw_mant_NRM_SWR[25]), .QN(n4019) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1242), .CK(clk), .RN(n4369), .Q(
Raw_mant_NRM_SWR[26]), .QN(n4070) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1241), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[27]), .QN(n4167) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1240), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[28]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1239), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1238), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[30]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1237), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[31]), .QN(n4029) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1236), .CK(clk), .RN(n4373), .Q(
Raw_mant_NRM_SWR[32]), .QN(n4077) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1235), .CK(clk), .RN(n4375), .Q(
Raw_mant_NRM_SWR[33]), .QN(n4090) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1234), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[34]), .QN(n4069) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1233), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[35]), .QN(n4230) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1232), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[36]), .QN(n4017) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1231), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[37]), .QN(n4087) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1230), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[38]), .QN(n4093) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1229), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[39]), .QN(n4244) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1228), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[40]), .QN(n4030) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1227), .CK(clk), .RN(n4374), .Q(
Raw_mant_NRM_SWR[41]), .QN(n4088) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1226), .CK(clk), .RN(n4372), .Q(
Raw_mant_NRM_SWR[42]), .QN(n4015) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1225), .CK(clk), .RN(n4372), .Q(
Raw_mant_NRM_SWR[43]), .QN(n4166) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1224), .CK(clk), .RN(n4371), .Q(
Raw_mant_NRM_SWR[44]), .QN(n4016) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1221), .CK(clk), .RN(n4370), .Q(
Raw_mant_NRM_SWR[47]), .QN(n4226) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1220), .CK(clk), .RN(n4365), .Q(
Raw_mant_NRM_SWR[48]), .QN(n4120) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1218), .CK(clk), .RN(n4366), .Q(
Raw_mant_NRM_SWR[50]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1216), .CK(clk), .RN(n4367), .Q(
Raw_mant_NRM_SWR[52]), .QN(n4028) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1214), .CK(clk), .RN(n4355), .Q(
Raw_mant_NRM_SWR[54]), .QN(n4241) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1213), .CK(clk), .RN(n4353),
.Q(LZD_output_NRM2_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1212), .CK(clk), .RN(n4353),
.Q(LZD_output_NRM2_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1211), .CK(clk), .RN(n4353),
.Q(LZD_output_NRM2_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1210), .CK(clk), .RN(n4354),
.Q(LZD_output_NRM2_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1209), .CK(clk), .RN(n4353),
.Q(LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1208), .CK(clk), .RN(n4354),
.Q(LZD_output_NRM2_EW[5]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1154), .CK(clk), .RN(n4367), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1942) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1127), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[28]), .QN(n4122) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1126), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[29]), .QN(n4279) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1125), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[30]), .QN(n4121) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1124), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[31]), .QN(n4123) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1123), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[32]), .QN(n4126) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1122), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[33]), .QN(n4128) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1121), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[34]), .QN(n4125) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1120), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[35]), .QN(n4127) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1119), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[36]), .QN(n4124) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1118), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[37]), .QN(n4278) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1117), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[38]), .QN(n4130) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1116), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[39]), .QN(n4132) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1115), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[40]), .QN(n4129) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1114), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[41]), .QN(n4139) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1113), .CK(clk), .RN(n4359), .Q(
DmP_mant_SFG_SWR[42]), .QN(n4135) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1112), .CK(clk), .RN(n4360), .Q(
DmP_mant_SFG_SWR[43]), .QN(n4138) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1111), .CK(clk), .RN(n4360), .Q(
DmP_mant_SFG_SWR[44]), .QN(n4134) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1110), .CK(clk), .RN(n4360), .Q(
DmP_mant_SFG_SWR[45]), .QN(n4137) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1109), .CK(clk), .RN(n4360), .Q(
DmP_mant_SFG_SWR[46]), .QN(n4170) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1108), .CK(clk), .RN(n4360), .Q(
DmP_mant_SFG_SWR[47]), .QN(n4186) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1107), .CK(clk), .RN(n4360), .Q(
DmP_mant_SFG_SWR[48]), .QN(n4169) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1106), .CK(clk), .RN(n4360), .Q(
DmP_mant_SFG_SWR[49]), .QN(n4185) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1105), .CK(clk), .RN(n4361), .Q(
DmP_mant_SFG_SWR[50]), .QN(n4168) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1104), .CK(clk), .RN(n4361), .Q(
DmP_mant_SFG_SWR[51]), .QN(n4214) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1103), .CK(clk), .RN(n4362), .Q(
DmP_mant_SFG_SWR[52]), .QN(n4253) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1102), .CK(clk), .RN(n4364), .Q(
DmP_mant_SFG_SWR[53]), .QN(n4252) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1101), .CK(clk), .RN(n4355), .Q(
DmP_mant_SFG_SWR[54]), .QN(n4277) );
DFFRXLTS inst_ShiftRegister_Q_reg_4_ ( .D(n1887), .CK(clk), .RN(n4383), .Q(
n1943), .QN(n4276) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1269), .CK(clk), .RN(n4347), .Q(
final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1685), .CK(clk), .RN(n4353), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1684), .CK(clk), .RN(n4353), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1683), .CK(clk), .RN(n4353), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1680), .CK(clk), .RN(n4353), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1679), .CK(clk), .RN(n4352), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1206), .CK(clk), .RN(n4347), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1205), .CK(clk), .RN(n4347), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1204), .CK(clk), .RN(n4347), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1203), .CK(clk), .RN(n4347), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1202), .CK(clk), .RN(n4347), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1201), .CK(clk), .RN(n4347), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1200), .CK(clk), .RN(n4348), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1199), .CK(clk), .RN(n4348), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1192), .CK(clk), .RN(n4348), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1191), .CK(clk), .RN(n4348), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1188), .CK(clk), .RN(n4349), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1187), .CK(clk), .RN(n4349), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1176), .CK(clk), .RN(n4350), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1175), .CK(clk), .RN(n4350), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1174), .CK(clk), .RN(n4350), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1173), .CK(clk), .RN(n4350), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1172), .CK(clk), .RN(n4350), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1171), .CK(clk), .RN(n4350), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1170), .CK(clk), .RN(n4351), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1169), .CK(clk), .RN(n4351), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1168), .CK(clk), .RN(n4351), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1167), .CK(clk), .RN(n4351), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1160), .CK(clk), .RN(n4352), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1159), .CK(clk), .RN(n4352), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1158), .CK(clk), .RN(n4352), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1157), .CK(clk), .RN(n4352), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1156), .CK(clk), .RN(n4352), .Q(
final_result_ieee[51]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1287), .CK(clk), .RN(n4345), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1280), .CK(clk), .RN(n4346), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1286), .CK(clk), .RN(n4345), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1207), .CK(clk), .RN(n4347), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1198), .CK(clk), .RN(n4348), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1197), .CK(clk), .RN(n4348), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1196), .CK(clk), .RN(n4348), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1195), .CK(clk), .RN(n4348), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1194), .CK(clk), .RN(n4348), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1193), .CK(clk), .RN(n4348), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1190), .CK(clk), .RN(n4349), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1189), .CK(clk), .RN(n4349), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1186), .CK(clk), .RN(n4349), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1185), .CK(clk), .RN(n4349), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1184), .CK(clk), .RN(n4349), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1183), .CK(clk), .RN(n4349), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1182), .CK(clk), .RN(n4349), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1181), .CK(clk), .RN(n4349), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1180), .CK(clk), .RN(n4350), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1179), .CK(clk), .RN(n4350), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1178), .CK(clk), .RN(n4350), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1177), .CK(clk), .RN(n4350), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1166), .CK(clk), .RN(n4351), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1165), .CK(clk), .RN(n4351), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1163), .CK(clk), .RN(n4351), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1162), .CK(clk), .RN(n4351), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1161), .CK(clk), .RN(n4351), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1682), .CK(clk), .RN(n4353), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1681), .CK(clk), .RN(n4353), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1678), .CK(clk), .RN(n4352), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1677), .CK(clk), .RN(n4352), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1676), .CK(clk), .RN(n4352), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1675), .CK(clk), .RN(n4352), .Q(
final_result_ieee[62]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1164), .CK(clk), .RN(n4351), .Q(
final_result_ieee[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1700), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[51]), .QN(n4240) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1711), .CK(clk), .RN(n4371), .Q(
Data_array_SWR[40]), .QN(n4082) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1707), .CK(clk), .RN(n4370), .Q(
Data_array_SWR[44]), .QN(n4236) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1739), .CK(clk), .RN(n4367), .Q(
Data_array_SWR[12]), .QN(n4250) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1549), .CK(clk), .RN(n4378), .Q(
DMP_SFG[19]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1223), .CK(clk), .RN(n4371), .Q(
Raw_mant_NRM_SWR[45]), .QN(n4091) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1722), .CK(clk), .RN(n4365), .Q(
Data_array_SWR[29]), .QN(n4067) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1712), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[39]), .QN(n4231) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1133), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[22]), .QN(n4105) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1705), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[46]), .QN(n4080) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1219), .CK(clk), .RN(n4366), .Q(
Raw_mant_NRM_SWR[49]), .QN(n4011) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1561), .CK(clk), .RN(n4377), .Q(
DMP_SFG[15]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1138), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[17]), .QN(n4275) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1130), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[25]), .QN(n4274) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1737), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[14]), .QN(n4251) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1732), .CK(clk), .RN(n4361), .Q(
Data_array_SWR[19]), .QN(n4249) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1738), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[13]), .QN(n4248) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1736), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[15]), .QN(n4247) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1703), .CK(clk), .RN(n4360), .Q(
Data_array_SWR[48]), .QN(n4239) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1730), .CK(clk), .RN(n4365), .Q(
Data_array_SWR[21]), .QN(n4238) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1709), .CK(clk), .RN(n4363), .Q(
Data_array_SWR[42]), .QN(n4237) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1706), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[45]), .QN(n4235) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1726), .CK(clk), .RN(n4365), .Q(
Data_array_SWR[25]), .QN(n4234) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1716), .CK(clk), .RN(n4361), .Q(
Data_array_SWR[35]), .QN(n4233) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1714), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[37]), .QN(n4232) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1132), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[23]), .QN(n4119) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1131), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[24]), .QN(n4118) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1129), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[26]), .QN(n4117) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1151), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[4]), .QN(n4116) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1150), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[5]), .QN(n4115) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1149), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[6]), .QN(n4114) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1143), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[12]), .QN(n4113) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1142), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[13]), .QN(n4112) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1141), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[14]), .QN(n4111) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1140), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[15]), .QN(n4110) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1139), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[16]), .QN(n4109) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1137), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[18]), .QN(n4108) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1135), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[20]), .QN(n4107) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1134), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[21]), .QN(n4106) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1128), .CK(clk), .RN(n4358), .Q(
DmP_mant_SFG_SWR[27]), .QN(n4104) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1153), .CK(clk), .RN(n4355), .Q(
DmP_mant_SFG_SWR[2]), .QN(n4103) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1152), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[3]), .QN(n4102) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1148), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[7]), .QN(n4101) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1147), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[8]), .QN(n4100) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1146), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[9]), .QN(n4099) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1145), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[10]), .QN(n4098) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1144), .CK(clk), .RN(n4356), .Q(
DmP_mant_SFG_SWR[11]), .QN(n4097) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1136), .CK(clk), .RN(n4357), .Q(
DmP_mant_SFG_SWR[19]), .QN(n4096) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1215), .CK(clk), .RN(n4367), .Q(
Raw_mant_NRM_SWR[53]), .QN(n4089) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1702), .CK(clk), .RN(n4360), .Q(
Data_array_SWR[49]), .QN(n4085) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1701), .CK(clk), .RN(n4360), .Q(
Data_array_SWR[50]), .QN(n4084) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1699), .CK(clk), .RN(n4362), .Q(
Data_array_SWR[52]), .QN(n4083) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1710), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[41]), .QN(n4081) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1718), .CK(clk), .RN(n4364), .Q(
Data_array_SWR[33]), .QN(n4075) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1704), .CK(clk), .RN(n4361), .Q(
Data_array_SWR[47]), .QN(n4072) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1708), .CK(clk), .RN(n4361), .Q(
Data_array_SWR[43]), .QN(n4071) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1222), .CK(clk), .RN(n4371), .Q(
Raw_mant_NRM_SWR[46]), .QN(n4034) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1217), .CK(clk), .RN(n4366), .Q(
Raw_mant_NRM_SWR[51]), .QN(n4033) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1558), .CK(clk), .RN(n4377), .Q(
DMP_SFG[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1594), .CK(clk), .RN(n4383), .Q(
DMP_SFG[4]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1155), .CK(clk), .RN(n4365), .QN(
n4272) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1606), .CK(clk), .RN(n4375), .Q(
DMP_SFG[0]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1585), .CK(clk), .RN(n4383), .Q(
DMP_SFG[7]) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1275), .CK(clk), .RN(n4354),
.Q(ADD_OVRFLW_NRM2), .QN(n1894) );
OAI222X1TS U1896 ( .A0(n2658), .A1(n4094), .B0(n4269), .B1(
Shift_reg_FLAGS_7_6), .C0(n4014), .C1(n2734), .Y(n1618) );
OAI222X1TS U1897 ( .A0(n2734), .A1(n4095), .B0(n4223), .B1(
Shift_reg_FLAGS_7_6), .C0(n4036), .C1(n2536), .Y(n1291) );
NOR2X1TS U1898 ( .A(n2252), .B(n3938), .Y(n2425) );
BUFX3TS U1899 ( .A(n4001), .Y(n3977) );
CMPR32X2TS U1900 ( .A(n1908), .B(DMP_exp_NRM2_EW[8]), .C(n2568), .CO(n2570),
.S(n3878) );
CMPR32X2TS U1901 ( .A(n1894), .B(DMP_exp_NRM2_EW[7]), .C(n2566), .CO(n2568),
.S(n3877) );
INVX2TS U1902 ( .A(n2083), .Y(n2045) );
INVX2TS U1903 ( .A(n2212), .Y(n2218) );
INVX2TS U1904 ( .A(n2092), .Y(n2316) );
NOR2XLTS U1905 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[37]), .Y(
n2096) );
INVX2TS U1906 ( .A(n2230), .Y(n2236) );
OAI21XLTS U1907 ( .A0(intDY_EWSW[50]), .A1(n4047), .B0(n2233), .Y(n2237) );
NOR2XLTS U1908 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[27]), .Y(
n2101) );
NOR2XLTS U1909 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2274) );
NOR2XLTS U1910 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n3553) );
NOR2XLTS U1911 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n3535) );
INVX2TS U1912 ( .A(n2247), .Y(n2223) );
OAI21XLTS U1913 ( .A0(intDY_EWSW[58]), .A1(n4035), .B0(n2184), .Y(n2186) );
OAI211XLTS U1914 ( .A0(intDY_EWSW[20]), .A1(n4149), .B0(n2699), .C0(n2130),
.Y(n2168) );
AOI211XLTS U1915 ( .A0(intDX_EWSW[44]), .A1(n4197), .B0(n2196), .C0(n2205),
.Y(n2203) );
NOR2XLTS U1916 ( .A(n2567), .B(n3878), .Y(n2569) );
OR2X1TS U1917 ( .A(LZD_output_NRM2_EW[0]), .B(ADD_OVRFLW_NRM2), .Y(n2550) );
INVX2TS U1918 ( .A(n2070), .Y(n2073) );
OAI21XLTS U1919 ( .A0(n3535), .A1(n3540), .B0(n3536), .Y(n3195) );
NOR2XLTS U1920 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n3315) );
AOI211XLTS U1921 ( .A0(intDY_EWSW[46]), .A1(n2209), .B0(n2208), .C0(n2207),
.Y(n2246) );
OAI211XLTS U1922 ( .A0(intDY_EWSW[60]), .A1(n4147), .B0(n2192), .C0(n2188),
.Y(n2194) );
OAI31X1TS U1923 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2755), .A2(n4070), .B0(
n2754), .Y(n2756) );
NAND2X1TS U1924 ( .A(n2370), .B(n2612), .Y(n2373) );
NAND2X1TS U1925 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3746) );
OAI2BB2X1TS U1926 ( .B0(n3244), .B1(n2034), .A0N(n1937), .A1N(n4130), .Y(
n3233) );
OAI21XLTS U1927 ( .A0(n3194), .A1(n2029), .B0(n2028), .Y(n3290) );
INVX2TS U1928 ( .A(n2909), .Y(n2864) );
NAND2X1TS U1929 ( .A(n3869), .B(n2328), .Y(n2811) );
OAI21XLTS U1930 ( .A0(n4244), .A1(n2898), .B0(n2874), .Y(n3037) );
NOR2XLTS U1931 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2370) );
OAI21XLTS U1932 ( .A0(n3788), .A1(n1925), .B0(n3832), .Y(n2588) );
NOR2XLTS U1933 ( .A(n4188), .B(n1902), .Y(n3142) );
NAND2X1TS U1934 ( .A(n2370), .B(n3793), .Y(n2740) );
NOR2XLTS U1935 ( .A(n2762), .B(n2069), .Y(n2325) );
AOI211XLTS U1936 ( .A0(n2251), .A1(n2250), .B0(n2249), .C0(n2248), .Y(n2252)
);
INVX2TS U1937 ( .A(n2658), .Y(n2519) );
OAI31X1TS U1938 ( .A0(Raw_mant_NRM_SWR[2]), .A1(Raw_mant_NRM_SWR[6]), .A2(
Raw_mant_NRM_SWR[5]), .B0(n2775), .Y(n2778) );
OAI21XLTS U1939 ( .A0(n2898), .A1(n4165), .B0(n2850), .Y(n3067) );
OAI21XLTS U1940 ( .A0(n4230), .A1(n2898), .B0(n2868), .Y(n3109) );
OAI21XLTS U1941 ( .A0(n4166), .A1(n2898), .B0(n2897), .Y(n3102) );
NAND2X1TS U1942 ( .A(n2813), .B(n2804), .Y(n3166) );
NOR2XLTS U1943 ( .A(n2330), .B(n2999), .Y(n2813) );
OAI21XLTS U1944 ( .A0(n2307), .A1(n2306), .B0(n2305), .Y(n2761) );
INVX2TS U1945 ( .A(ADD_OVRFLW_NRM2), .Y(n1908) );
OR2X1TS U1946 ( .A(n2805), .B(n2804), .Y(n3641) );
NAND2X1TS U1947 ( .A(n3810), .B(n4010), .Y(n2802) );
OAI2BB1X1TS U1948 ( .A0N(n2582), .A1N(n2581), .B0(Shift_reg_FLAGS_7[0]), .Y(
n3975) );
OR2X1TS U1949 ( .A(n2649), .B(n3858), .Y(n1895) );
NAND2X1TS U1950 ( .A(n3866), .B(LZD_output_NRM2_EW[5]), .Y(n2783) );
INVX2TS U1951 ( .A(n3958), .Y(n3961) );
INVX2TS U1952 ( .A(n2909), .Y(n3865) );
INVX2TS U1953 ( .A(n2909), .Y(n3972) );
INVX2TS U1954 ( .A(n4280), .Y(n3947) );
INVX2TS U1955 ( .A(n3118), .Y(n3128) );
NAND2X1TS U1956 ( .A(n3014), .B(n2813), .Y(n2814) );
OR2X1TS U1957 ( .A(n3866), .B(ADD_OVRFLW_NRM), .Y(n2912) );
NAND2X1TS U1958 ( .A(beg_OP), .B(n3888), .Y(n3891) );
NOR2XLTS U1959 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4221), .Y(n3883) );
OAI211XLTS U1960 ( .A0(n3018), .A1(n3086), .B0(n3017), .C0(n3016), .Y(n1726)
);
OAI21XLTS U1961 ( .A0(n2935), .A1(n2964), .B0(n2934), .Y(n1173) );
OAI21XLTS U1962 ( .A0(n3154), .A1(n1927), .B0(n2963), .Y(n1204) );
OAI2BB1X1TS U1963 ( .A0N(n3504), .A1N(n2042), .B0(n2041), .Y(n1214) );
INVX2TS U1964 ( .A(n2364), .Y(n1622) );
OAI21XLTS U1965 ( .A0(n1931), .A1(n3167), .B0(n2786), .Y(n1697) );
INVX2TS U1966 ( .A(n2112), .Y(n1694) );
OR2X2TS U1967 ( .A(n3862), .B(DmP_mant_SFG_SWR[54]), .Y(n3864) );
CLKINVX1TS U1968 ( .A(n2298), .Y(n2109) );
OAI2BB2X2TS U1969 ( .B0(n3700), .B1(n2038), .A0N(n1940), .A1N(n4169), .Y(
n3679) );
CLKINVX1TS U1970 ( .A(n2774), .Y(n2775) );
CLKINVX1TS U1971 ( .A(n2773), .Y(n2307) );
NAND4X1TS U1972 ( .A(n2769), .B(n2068), .C(n2067), .D(n2103), .Y(n2069) );
NOR2X1TS U1973 ( .A(n2289), .B(n2052), .Y(n2076) );
CLKINVX1TS U1974 ( .A(n2289), .Y(n2290) );
NAND2X1TS U1975 ( .A(n2767), .B(n2051), .Y(n2289) );
CLKINVX1TS U1976 ( .A(n2081), .Y(n2319) );
NOR2X1TS U1977 ( .A(n2081), .B(n2317), .Y(n2767) );
CLKINVX1TS U1978 ( .A(n2299), .Y(n2304) );
CLKINVX1TS U1979 ( .A(n4001), .Y(n4003) );
AFHCINX2TS U1980 ( .CIN(n3237), .B(n4278), .A(DMP_SFG[35]), .S(n3241), .CO(
n3242) );
CLKINVX1TS U1981 ( .A(n2755), .Y(n2102) );
AOI2BB1X1TS U1982 ( .A0N(n2284), .A1N(Raw_mant_NRM_SWR[29]), .B0(n2283), .Y(
n2285) );
OAI2BB2X2TS U1983 ( .B0(n3250), .B1(n2033), .A0N(n1941), .A1N(n4124), .Y(
n3238) );
NAND2XLTS U1984 ( .A(n2100), .B(Raw_mant_NRM_SWR[28]), .Y(n2284) );
NAND2XLTS U1985 ( .A(n2100), .B(Raw_mant_NRM_SWR[29]), .Y(n2103) );
NOR2X1TS U1986 ( .A(n2098), .B(n2047), .Y(n2100) );
ADDFHX1TS U1987 ( .A(n1894), .B(DMP_exp_NRM2_EW[9]), .CI(n2570), .CO(n2572),
.S(n3879) );
NAND4BX1TS U1988 ( .AN(n3877), .B(n2565), .C(n3876), .D(n3875), .Y(n2567) );
AND3X2TS U1989 ( .A(n3874), .B(n3873), .C(n2578), .Y(n2580) );
INVX1TS U1990 ( .A(n2988), .Y(n2975) );
CLKBUFX2TS U1991 ( .A(n3799), .Y(n1916) );
NAND2X1TS U1992 ( .A(n3886), .B(Shift_reg_FLAGS_7[3]), .Y(n3963) );
OAI21X1TS U1993 ( .A0(intDY_EWSW[46]), .A1(n4146), .B0(n2195), .Y(n2205) );
XOR2X1TS U1994 ( .A(n1908), .B(n2549), .Y(n2557) );
NAND2XLTS U1995 ( .A(n4029), .B(Raw_mant_NRM_SWR[30]), .Y(n2097) );
INVX2TS U1996 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2896) );
NOR2X1TS U1997 ( .A(n4267), .B(intDY_EWSW[53]), .Y(n2115) );
INVX1TS U1998 ( .A(n1896), .Y(n1918) );
OAI2BB1X1TS U1999 ( .A0N(n4252), .A1N(DMP_SFG[51]), .B0(n2004), .Y(n2005) );
AND2X2TS U2000 ( .A(n2813), .B(n2811), .Y(n2997) );
NAND2XLTS U2001 ( .A(n2807), .B(n2813), .Y(n2808) );
OAI2BB1X1TS U2002 ( .A0N(n1898), .A1N(DmP_mant_SFG_SWR[52]), .B0(n3609), .Y(
n2003) );
NOR2X1TS U2003 ( .A(n2298), .B(n2297), .Y(n2424) );
INVX1TS U2004 ( .A(n2080), .Y(n1696) );
NAND3X1TS U2005 ( .A(n2326), .B(n2325), .C(n2324), .Y(n2327) );
XOR2XLTS U2006 ( .A(n3661), .B(n3660), .Y(n3662) );
AFHCINX2TS U2007 ( .CIN(n3679), .B(DMP_SFG[47]), .A(DmP_mant_SFG_SWR[49]),
.S(n3680), .CO(n3661) );
AFHCINX2TS U2008 ( .CIN(n3678), .B(n4185), .A(DMP_SFG[47]), .S(n3682), .CO(
n3659) );
OAI22X2TS U2009 ( .A0(n3698), .A1(n2001), .B0(n4169), .B1(DMP_SFG[46]), .Y(
n3678) );
NAND2BX1TS U2010 ( .AN(n2296), .B(n2779), .Y(n2297) );
NOR3X1TS U2011 ( .A(n2761), .B(n2323), .C(n2322), .Y(n2324) );
AFHCINX2TS U2012 ( .CIN(n3499), .B(n4186), .A(DMP_SFG[45]), .S(n3503), .CO(
n3698) );
AFHCINX2TS U2013 ( .CIN(n3500), .B(DMP_SFG[45]), .A(DmP_mant_SFG_SWR[47]),
.S(n3501), .CO(n3700) );
NAND2X1TS U2014 ( .A(n2295), .B(n2286), .Y(n2110) );
OAI21X1TS U2015 ( .A0(n2774), .A1(n2066), .B0(n2065), .Y(n2762) );
OAI2BB2X2TS U2016 ( .B0(n3483), .B1(n2037), .A0N(n1939), .A1N(n4170), .Y(
n3500) );
NOR2X1TS U2017 ( .A(n2774), .B(n2057), .Y(n2295) );
XOR2XLTS U2018 ( .A(n3481), .B(n3480), .Y(n3486) );
NAND3X1TS U2019 ( .A(n2292), .B(n2321), .C(n2291), .Y(n2293) );
AFHCINX2TS U2020 ( .CIN(n3461), .B(DMP_SFG[43]), .A(DmP_mant_SFG_SWR[45]),
.S(n3462), .CO(n3483) );
NAND2XLTS U2021 ( .A(n2773), .B(n2288), .Y(n2292) );
NAND3X1TS U2022 ( .A(n2321), .B(n2320), .C(n2768), .Y(n2322) );
OAI22X2TS U2023 ( .A0(n3442), .A1(n2036), .B0(DMP_SFG[42]), .B1(
DmP_mant_SFG_SWR[44]), .Y(n3461) );
AFHCINX2TS U2024 ( .CIN(n3422), .B(DMP_SFG[41]), .A(DmP_mant_SFG_SWR[43]),
.S(n3423), .CO(n3442) );
NAND2X1TS U2025 ( .A(n2076), .B(n2053), .Y(n2749) );
NAND3X1TS U2026 ( .A(n2290), .B(Raw_mant_NRM_SWR[15]), .C(n4046), .Y(n2321)
);
OAI21X1TS U2027 ( .A0(n2947), .A1(n2964), .B0(n2946), .Y(n1191) );
XOR2XLTS U2028 ( .A(n3405), .B(n3404), .Y(n3409) );
OAI21X1TS U2029 ( .A0(n2289), .A1(n4046), .B0(n2285), .Y(n2296) );
INVX1TS U2030 ( .A(n1928), .Y(n1927) );
OAI31XLTS U2031 ( .A0(Raw_mant_NRM_SWR[16]), .A1(Raw_mant_NRM_SWR[18]), .A2(
Raw_mant_NRM_SWR[14]), .B0(n2767), .Y(n2770) );
XOR2XLTS U2032 ( .A(n3227), .B(n3226), .Y(n3228) );
NAND2X1TS U2033 ( .A(n2107), .B(n4020), .Y(n2081) );
NOR2X2TS U2034 ( .A(n3977), .B(n3810), .Y(n2800) );
XOR2XLTS U2035 ( .A(n3244), .B(n3243), .Y(n3245) );
NAND4BX1TS U2036 ( .AN(n2088), .B(n2087), .C(n2086), .D(n2085), .Y(n2089) );
NOR2X1TS U2037 ( .A(n2299), .B(n2050), .Y(n2107) );
NAND3X1TS U2038 ( .A(n2102), .B(n2101), .C(Raw_mant_NRM_SWR[25]), .Y(n2302)
);
OR2X4TS U2039 ( .A(n3973), .B(n3975), .Y(n4001) );
AFHCINX2TS U2040 ( .CIN(n3238), .B(DMP_SFG[35]), .A(DmP_mant_SFG_SWR[37]),
.S(n3239), .CO(n3244) );
INVX1TS U2041 ( .A(n2088), .Y(n2068) );
XOR2XLTS U2042 ( .A(n3250), .B(n3249), .Y(n3251) );
NAND2X1TS U2043 ( .A(n2100), .B(n2048), .Y(n2755) );
INVX1TS U2044 ( .A(n2365), .Y(n1293) );
OAI222X1TS U2045 ( .A0(n2734), .A1(n4094), .B0(n4266), .B1(
Shift_reg_FLAGS_7_6), .C0(n4014), .C1(n2536), .Y(n1289) );
XOR2XLTS U2046 ( .A(n3261), .B(n3260), .Y(n3262) );
ADDFHX1TS U2047 ( .A(n1908), .B(DMP_exp_NRM2_EW[10]), .CI(n2572), .CO(n2573),
.S(n3880) );
NAND2X1TS U2048 ( .A(n2084), .B(n2046), .Y(n2098) );
NAND2XLTS U2049 ( .A(n2084), .B(Raw_mant_NRM_SWR[33]), .Y(n2094) );
AFHCINX2TS U2050 ( .CIN(n3180), .B(n4128), .A(DMP_SFG[31]), .S(n3184), .CO(
n3259) );
NOR2X1TS U2051 ( .A(n2092), .B(Raw_mant_NRM_SWR[35]), .Y(n2084) );
OAI22X1TS U2052 ( .A0(n3267), .A1(n2031), .B0(DMP_SFG[30]), .B1(
DmP_mant_SFG_SWR[32]), .Y(n3181) );
INVX1TS U2053 ( .A(n2579), .Y(n3875) );
OAI21X1TS U2054 ( .A0(n2282), .A1(n2281), .B0(n2280), .Y(n2283) );
NOR2X1TS U2055 ( .A(n2095), .B(n2044), .Y(n2082) );
NAND3X1TS U2056 ( .A(n2374), .B(n1901), .C(n2373), .Y(n2787) );
NAND3X1TS U2057 ( .A(n2403), .B(n1901), .C(n2402), .Y(n2792) );
AFHCINX2TS U2058 ( .CIN(n3283), .B(n4279), .A(DMP_SFG[27]), .S(n3287), .CO(
n3276) );
INVX1TS U2059 ( .A(n2270), .Y(n2282) );
OAI211X1TS U2060 ( .A0(n2623), .A1(n3802), .B0(n3799), .C0(n2622), .Y(n2945)
);
OAI21X1TS U2061 ( .A0(n2623), .A1(n1903), .B0(n3832), .Y(n2591) );
OAI22X2TS U2062 ( .A0(n3290), .A1(n2030), .B0(DMP_SFG[26]), .B1(
DmP_mant_SFG_SWR[28]), .Y(n3284) );
NOR2X1TS U2063 ( .A(n2062), .B(Raw_mant_NRM_SWR[41]), .Y(n2270) );
OAI211X1TS U2064 ( .A0(n1925), .A1(n2736), .B0(n2735), .C0(n1916), .Y(n2931)
);
OAI21X1TS U2065 ( .A0(n2898), .A1(n4227), .B0(n2821), .Y(n3074) );
INVX1TS U2066 ( .A(n2312), .Y(n2058) );
NOR2X1TS U2067 ( .A(n3972), .B(n2882), .Y(n2781) );
INVX1TS U2068 ( .A(n2300), .Y(n2301) );
OAI21X1TS U2069 ( .A0(n3185), .A1(n1997), .B0(n1996), .Y(n3288) );
OAI21X1TS U2070 ( .A0(n2898), .A1(n4190), .B0(n2844), .Y(n3026) );
OAI21X1TS U2071 ( .A0(n2898), .A1(n4245), .B0(n2857), .Y(n2987) );
NAND2XLTS U2072 ( .A(n2370), .B(n2636), .Y(n2402) );
NOR2X1TS U2073 ( .A(n1903), .B(n2598), .Y(n3768) );
INVX1TS U2074 ( .A(n2908), .Y(n2079) );
NOR2X1TS U2075 ( .A(n2277), .B(n4166), .Y(n2300) );
NOR2X1TS U2076 ( .A(n2368), .B(n2367), .Y(n3838) );
NOR2X1TS U2077 ( .A(n2398), .B(n2397), .Y(n3846) );
AOI211X1TS U2078 ( .A0(n2691), .A1(n2129), .B0(n2128), .C0(n2127), .Y(n2181)
);
NOR2X1TS U2079 ( .A(n2597), .B(n2596), .Y(n3841) );
NOR2X1TS U2080 ( .A(n2383), .B(n2382), .Y(n3835) );
AOI21X2TS U2081 ( .A0(n3306), .A1(n2019), .B0(n2018), .Y(n3194) );
NOR2X1TS U2082 ( .A(n2277), .B(Raw_mant_NRM_SWR[43]), .Y(n2312) );
OAI21X1TS U2083 ( .A0(n4226), .A1(n2898), .B0(n2887), .Y(n3094) );
NAND2X1TS U2084 ( .A(n2753), .B(n2043), .Y(n2277) );
NAND3X1TS U2085 ( .A(n2230), .B(n2239), .C(n2117), .Y(n2247) );
INVX1TS U2086 ( .A(n2910), .Y(n3129) );
INVX1TS U2087 ( .A(n3963), .Y(n3953) );
NAND4X1TS U2088 ( .A(n2203), .B(n2201), .C(n2114), .D(n2113), .Y(n2245) );
NAND2XLTS U2089 ( .A(n3866), .B(LZD_output_NRM2_EW[1]), .Y(n2423) );
NAND2XLTS U2090 ( .A(n3866), .B(LZD_output_NRM2_EW[3]), .Y(n2765) );
NOR2X1TS U2091 ( .A(n2055), .B(Raw_mant_NRM_SWR[9]), .Y(n2056) );
NOR2X1TS U2092 ( .A(n2072), .B(n2070), .Y(n2753) );
NOR2X1TS U2093 ( .A(n2045), .B(Raw_mant_NRM_SWR[32]), .Y(n2046) );
NOR2X1TS U2094 ( .A(n2903), .B(n3173), .Y(n2078) );
AND2X2TS U2095 ( .A(ADD_OVRFLW_NRM), .B(n2903), .Y(n2910) );
OAI211X1TS U2096 ( .A0(intDY_EWSW[36]), .A1(n4142), .B0(n2221), .C0(n2210),
.Y(n2212) );
INVX1TS U2097 ( .A(n3883), .Y(n3882) );
XOR2X1TS U2098 ( .A(n1908), .B(n2545), .Y(n2564) );
XOR2X1TS U2099 ( .A(n1908), .B(n2546), .Y(n2559) );
XOR2X1TS U2100 ( .A(n1908), .B(n2547), .Y(n2552) );
XOR2X1TS U2101 ( .A(n1908), .B(n2548), .Y(n2555) );
XOR2X1TS U2102 ( .A(n1894), .B(n2550), .Y(n2553) );
AOI211X1TS U2103 ( .A0(intDX_EWSW[52]), .A1(n4220), .B0(n2115), .C0(n2228),
.Y(n2230) );
OAI211X1TS U2104 ( .A0(intDY_EWSW[28]), .A1(n4148), .B0(n2691), .C0(n2121),
.Y(n2176) );
CLKINVX2TS U2105 ( .A(n2909), .Y(n2893) );
INVX1TS U2106 ( .A(n2096), .Y(n2044) );
INVX1TS U2107 ( .A(n2287), .Y(n2055) );
INVX1TS U2108 ( .A(n2286), .Y(n2294) );
INVX1TS U2109 ( .A(n2273), .Y(n2275) );
NOR2X1TS U2110 ( .A(shift_value_SHT2_EWR[4]), .B(n4187), .Y(n3782) );
NOR2X1TS U2111 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2286)
);
NOR2X1TS U2112 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2281) );
NOR2X1TS U2113 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .Y(n2287)
);
NOR2X1TS U2114 ( .A(n4159), .B(intDY_EWSW[49]), .Y(n2231) );
NOR2X1TS U2115 ( .A(n4160), .B(intDY_EWSW[57]), .Y(n2182) );
OR2X2TS U2116 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[19]), .Y(n2317) );
NOR2X1TS U2117 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n2051) );
NAND2BX1TS U2118 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2184) );
OR2X2TS U2119 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .Y(n2052) );
NAND2BX1TS U2120 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2192) );
NOR2X1TS U2121 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[13]), .Y(
n2053) );
NOR2X1TS U2122 ( .A(Raw_mant_NRM_SWR[11]), .B(Raw_mant_NRM_SWR[12]), .Y(
n2759) );
INVX1TS U2123 ( .A(n4280), .Y(n3956) );
CLKAND2X2TS U2124 ( .A(DmP_mant_SFG_SWR[28]), .B(DMP_SFG[26]), .Y(n2030) );
INVX1TS U2125 ( .A(n4280), .Y(n3950) );
CLKAND2X2TS U2126 ( .A(DmP_mant_SFG_SWR[36]), .B(DMP_SFG[34]), .Y(n2033) );
CLKAND2X2TS U2127 ( .A(DmP_mant_SFG_SWR[38]), .B(DMP_SFG[36]), .Y(n2034) );
INVX1TS U2128 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3979) );
CLKAND2X2TS U2129 ( .A(DmP_mant_SFG_SWR[40]), .B(DMP_SFG[38]), .Y(n2035) );
CLKAND2X2TS U2130 ( .A(DmP_mant_SFG_SWR[46]), .B(DMP_SFG[44]), .Y(n2037) );
NAND2BX1TS U2131 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2233) );
NOR2X1TS U2132 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[28]), .Y(
n2048) );
OR2X2TS U2133 ( .A(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[30]), .Y(n2047) );
NOR2X1TS U2134 ( .A(Raw_mant_NRM_SWR[34]), .B(Raw_mant_NRM_SWR[33]), .Y(
n2083) );
NOR2X1TS U2135 ( .A(n4153), .B(intDY_EWSW[45]), .Y(n2196) );
OR2X2TS U2136 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(n2050) );
NOR2X1TS U2137 ( .A(n2755), .B(n2049), .Y(n2750) );
NAND2X1TS U2138 ( .A(n2773), .B(n2056), .Y(n2774) );
NOR2X2TS U2139 ( .A(n2749), .B(n2054), .Y(n2773) );
NOR2X1TS U2140 ( .A(n2805), .B(n2811), .Y(n1896) );
OAI21X1TS U2141 ( .A0(n3615), .A1(n1945), .B0(n1944), .Y(n3619) );
AFHCINX4TS U2142 ( .CIN(n3254), .B(n4127), .A(DMP_SFG[33]), .S(n3258), .CO(
n3248) );
XNOR2X1TS U2143 ( .A(n3862), .B(DmP_mant_SFG_SWR[54]), .Y(n2040) );
ADDFHX2TS U2144 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .CI(n2336),
.CO(n3862), .S(n2337) );
OAI22X2TS U2145 ( .A0(n3661), .A1(n2039), .B0(DMP_SFG[48]), .B1(
DmP_mant_SFG_SWR[50]), .Y(n3631) );
NOR2XLTS U2146 ( .A(n3524), .B(n3190), .Y(n2021) );
NOR2XLTS U2147 ( .A(n3523), .B(n1978), .Y(n1980) );
NAND4BXLTS U2148 ( .AN(n3873), .B(n3870), .C(n3872), .D(n3871), .Y(n2560) );
NOR2XLTS U2149 ( .A(n3326), .B(n1971), .Y(n1973) );
OAI211XLTS U2150 ( .A0(intDY_EWSW[12]), .A1(n4150), .B0(n2707), .C0(n2131),
.Y(n2159) );
NAND2BXLTS U2151 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2131) );
OAI21XLTS U2152 ( .A0(n3190), .A1(n3525), .B0(n3191), .Y(n2020) );
NOR2XLTS U2153 ( .A(n4105), .B(DMP_SFG[20]), .Y(n1982) );
OAI21XLTS U2154 ( .A0(n1978), .A1(n3522), .B0(n1977), .Y(n1979) );
NOR2XLTS U2155 ( .A(n4111), .B(DMP_SFG[12]), .Y(n1965) );
NAND3XLTS U2156 ( .A(n2076), .B(Raw_mant_NRM_SWR[13]), .C(n4048), .Y(n2769)
);
OAI21XLTS U2157 ( .A0(n3307), .A1(n2017), .B0(n2016), .Y(n2018) );
NOR2XLTS U2158 ( .A(n3469), .B(n1953), .Y(n1955) );
INVX2TS U2159 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2909) );
AOI2BB2XLTS U2160 ( .B0(n2107), .B1(n2064), .A0N(n2063), .A1N(n2062), .Y(
n2065) );
CLKAND2X2TS U2161 ( .A(DmP_mant_SFG_SWR[44]), .B(DMP_SFG[42]), .Y(n2036) );
CLKAND2X2TS U2162 ( .A(n4134), .B(DMP_SFG[42]), .Y(n1999) );
CLKAND2X2TS U2163 ( .A(DmP_mant_SFG_SWR[48]), .B(DMP_SFG[46]), .Y(n2038) );
AFHCINX2TS U2164 ( .CIN(n3233), .B(DMP_SFG[37]), .A(DmP_mant_SFG_SWR[39]),
.S(n3234), .CO(n3227) );
AFHCINX2TS U2165 ( .CIN(n3255), .B(DMP_SFG[33]), .A(DmP_mant_SFG_SWR[35]),
.S(n3256), .CO(n3250) );
CLKAND2X2TS U2166 ( .A(DmP_mant_SFG_SWR[34]), .B(DMP_SFG[32]), .Y(n2032) );
NAND2BXLTS U2167 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2148) );
NAND3XLTS U2168 ( .A(n4158), .B(n2146), .C(intDY_EWSW[8]), .Y(n2147) );
NOR2XLTS U2169 ( .A(intDX_EWSW[10]), .B(n2144), .Y(n2145) );
OAI21XLTS U2170 ( .A0(intDY_EWSW[13]), .A1(n4144), .B0(intDY_EWSW[12]), .Y(
n2143) );
OAI21XLTS U2171 ( .A0(intDY_EWSW[15]), .A1(n4026), .B0(intDY_EWSW[14]), .Y(
n2152) );
NOR2XLTS U2172 ( .A(n4109), .B(DMP_SFG[14]), .Y(n1967) );
NOR2XLTS U2173 ( .A(n3380), .B(n3371), .Y(n2013) );
NAND2BXLTS U2174 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2121) );
OAI21XLTS U2175 ( .A0(intDY_EWSW[26]), .A1(n4050), .B0(n2123), .Y(n2177) );
NOR2XLTS U2176 ( .A(n4154), .B(intDY_EWSW[25]), .Y(n2174) );
NAND3BXLTS U2177 ( .AN(n2168), .B(n2161), .C(n2160), .Y(n2180) );
OAI211XLTS U2178 ( .A0(intDY_EWSW[8]), .A1(n4158), .B0(n2146), .C0(n2149),
.Y(n2157) );
NOR2XLTS U2179 ( .A(n4104), .B(DMP_SFG[25]), .Y(n1993) );
NOR2XLTS U2180 ( .A(n3298), .B(n3535), .Y(n3196) );
NOR2XLTS U2181 ( .A(n4108), .B(DMP_SFG[16]), .Y(n1976) );
NOR2XLTS U2182 ( .A(n3313), .B(n3315), .Y(n2015) );
NOR2XLTS U2183 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n3298) );
NOR2XLTS U2184 ( .A(n3331), .B(n1967), .Y(n1969) );
OAI21XLTS U2185 ( .A0(n1961), .A1(n3392), .B0(n1960), .Y(n1962) );
NOR2XLTS U2186 ( .A(n4098), .B(DMP_SFG[8]), .Y(n1959) );
NOR2XLTS U2187 ( .A(n4114), .B(DMP_SFG[4]), .Y(n1951) );
NAND2X1TS U2188 ( .A(n2312), .B(n4015), .Y(n2062) );
OAI211XLTS U2189 ( .A0(n3788), .A1(n3746), .B0(n3716), .C0(n3715), .Y(n3717)
);
NAND2BXLTS U2190 ( .AN(n3730), .B(n3729), .Y(n3731) );
NAND2BXLTS U2191 ( .AN(n3777), .B(n3728), .Y(n3729) );
OAI211XLTS U2192 ( .A0(n3790), .A1(n3746), .B0(n3722), .C0(n3721), .Y(n3730)
);
OAI211XLTS U2193 ( .A0(n3801), .A1(n3746), .B0(n3745), .C0(n3744), .Y(n3747)
);
NAND4XLTS U2194 ( .A(n3754), .B(n3753), .C(n3752), .D(n1916), .Y(n3842) );
NAND4XLTS U2195 ( .A(n3760), .B(n3759), .C(n3758), .D(n3799), .Y(n3839) );
NAND4XLTS U2196 ( .A(n3766), .B(n3765), .C(n3764), .D(n3799), .Y(n3836) );
NAND4XLTS U2197 ( .A(n3773), .B(n3772), .C(n3771), .D(n1916), .Y(n3833) );
NAND2BXLTS U2198 ( .AN(n2314), .B(n2313), .Y(n2315) );
NAND4BXLTS U2199 ( .AN(Raw_mant_NRM_SWR[38]), .B(n2312), .C(
Raw_mant_NRM_SWR[37]), .D(n2311), .Y(n2313) );
OAI21XLTS U2200 ( .A0(n1984), .A1(n3578), .B0(n1983), .Y(n1985) );
NOR2XLTS U2201 ( .A(n3204), .B(n1993), .Y(n1995) );
OAI21XLTS U2202 ( .A0(n3208), .A1(n3569), .B0(n3209), .Y(n2026) );
OAI21XLTS U2203 ( .A0(n3594), .A1(n3591), .B0(n3595), .Y(n2022) );
NOR2XLTS U2204 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n3208) );
NOR2XLTS U2205 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n3568) );
OAI21XLTS U2206 ( .A0(n1965), .A1(n3358), .B0(n1964), .Y(n3328) );
NOR2XLTS U2207 ( .A(n3357), .B(n1965), .Y(n3327) );
NOR2XLTS U2208 ( .A(n3470), .B(n3447), .Y(n2009) );
OAI21XLTS U2209 ( .A0(n1947), .A1(n3645), .B0(n1946), .Y(n1948) );
NAND4XLTS U2210 ( .A(n2104), .B(n2284), .C(n2103), .D(n2302), .Y(n2106) );
AOI2BB2XLTS U2211 ( .B0(Raw_mant_NRM_SWR[47]), .B1(n2753), .A0N(n2094),
.A1N(Raw_mant_NRM_SWR[34]), .Y(n2067) );
OR2X1TS U2212 ( .A(n2749), .B(n2759), .Y(n2291) );
OAI21XLTS U2213 ( .A0(n2908), .A1(n4044), .B0(n2907), .Y(n2988) );
AOI211XLTS U2214 ( .A0(n1936), .A1(n3820), .B0(n2506), .C0(n2505), .Y(n2590)
);
OAI211XLTS U2215 ( .A0(n3777), .A1(n3784), .B0(n2504), .C0(n2503), .Y(n2505)
);
AOI211XLTS U2216 ( .A0(n1906), .A1(n2621), .B0(n2495), .C0(n2494), .Y(n2593)
);
NOR2XLTS U2217 ( .A(n2620), .B(n3802), .Y(n2494) );
OAI211XLTS U2218 ( .A0(n2623), .A1(n3746), .B0(n2491), .C0(n2490), .Y(n2495)
);
OAI211XLTS U2219 ( .A0(n4250), .A1(n2638), .B0(n3799), .C0(n2613), .Y(n2614)
);
OAI211XLTS U2220 ( .A0(n4248), .A1(n2638), .B0(n3799), .C0(n2601), .Y(n2602)
);
OAI211XLTS U2221 ( .A0(n4251), .A1(n2638), .B0(n1916), .C0(n2637), .Y(n2639)
);
OAI211XLTS U2222 ( .A0(n4247), .A1(n2638), .B0(n1916), .C0(n2630), .Y(n2631)
);
CLKAND2X2TS U2223 ( .A(n4168), .B(DMP_SFG[48]), .Y(n2002) );
OAI22X2TS U2224 ( .A0(n3481), .A1(n2000), .B0(n4170), .B1(DMP_SFG[44]), .Y(
n3499) );
CLKAND2X2TS U2225 ( .A(n4170), .B(DMP_SFG[44]), .Y(n2000) );
AFHCINX2TS U2226 ( .CIN(n3421), .B(n4138), .A(DMP_SFG[41]), .S(n3425), .CO(
n3440) );
CLKAND2X2TS U2227 ( .A(n4135), .B(DMP_SFG[40]), .Y(n1998) );
AFHCONX2TS U2228 ( .A(DmP_mant_SFG_SWR[42]), .B(DMP_SFG[40]), .CI(n3406),
.CON(n3422), .S(n3407) );
CLKAND2X2TS U2229 ( .A(DmP_mant_SFG_SWR[32]), .B(DMP_SFG[30]), .Y(n2031) );
OAI21XLTS U2230 ( .A0(n3637), .A1(n4241), .B0(n3865), .Y(n2785) );
OAI21XLTS U2231 ( .A0(n2908), .A1(n4246), .B0(n2881), .Y(n3118) );
INVX2TS U2232 ( .A(n3641), .Y(n2920) );
MXI2XLTS U2233 ( .A(n2812), .B(n2820), .S0(n2811), .Y(n3014) );
MXI2XLTS U2234 ( .A(n3018), .B(n2812), .S0(n2811), .Y(n2807) );
XNOR2X1TS U2235 ( .A(n2005), .B(n4277), .Y(n2042) );
NOR2XLTS U2236 ( .A(n4155), .B(intDY_EWSW[11]), .Y(n2144) );
OAI211XLTS U2237 ( .A0(n4131), .A1(intDY_EWSW[3]), .B0(n2136), .C0(n2135),
.Y(n2139) );
NAND2BXLTS U2238 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2165) );
NAND2BXLTS U2239 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2123) );
NOR2XLTS U2240 ( .A(n4156), .B(intDY_EWSW[17]), .Y(n2163) );
NAND2BXLTS U2241 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2146) );
AOI211XLTS U2242 ( .A0(n2707), .A1(n2155), .B0(n2154), .C0(n2153), .Y(n2156)
);
NAND2BXLTS U2243 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2130) );
OAI21XLTS U2244 ( .A0(intDY_EWSW[18]), .A1(n4049), .B0(n2165), .Y(n2169) );
NOR2XLTS U2245 ( .A(n4107), .B(DMP_SFG[18]), .Y(n1978) );
NOR2XLTS U2246 ( .A(n4113), .B(DMP_SFG[10]), .Y(n1961) );
NOR2XLTS U2247 ( .A(n3391), .B(n1961), .Y(n1963) );
NAND3XLTS U2248 ( .A(n4142), .B(n2210), .C(intDY_EWSW[36]), .Y(n2211) );
NAND2BXLTS U2249 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2195) );
AOI2BB2XLTS U2250 ( .B0(intDY_EWSW[53]), .B1(n4267), .A0N(intDX_EWSW[52]),
.A1N(n2227), .Y(n2229) );
NAND2X1TS U2251 ( .A(n2082), .B(n4017), .Y(n2092) );
CLKAND2X2TS U2252 ( .A(bit_shift_SHT2), .B(n3739), .Y(n2625) );
OAI21XLTS U2253 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n2310), .B0(n2309), .Y(
n2314) );
NAND3XLTS U2254 ( .A(n2753), .B(Raw_mant_NRM_SWR[45]), .C(n4034), .Y(n2309)
);
NOR2XLTS U2255 ( .A(n3579), .B(n1984), .Y(n1986) );
OAI21XLTS U2256 ( .A0(n3553), .A1(n3557), .B0(n3554), .Y(n3584) );
NOR2XLTS U2257 ( .A(n3558), .B(n3553), .Y(n3585) );
OAI21XLTS U2258 ( .A0(n3315), .A1(n3335), .B0(n3316), .Y(n2014) );
OAI21XLTS U2259 ( .A0(n1967), .A1(n3332), .B0(n1966), .Y(n1968) );
NOR2XLTS U2260 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n3313) );
OAI21XLTS U2261 ( .A0(n3371), .A1(n3395), .B0(n3372), .Y(n2012) );
NOR2XLTS U2262 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n3380) );
OAI21XLTS U2263 ( .A0(n3447), .A1(n3471), .B0(n3448), .Y(n2008) );
OAI21XLTS U2264 ( .A0(n1953), .A1(n3468), .B0(n1952), .Y(n1954) );
NOR2XLTS U2265 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n3492) );
NOR2XLTS U2266 ( .A(n3670), .B(n3665), .Y(n2007) );
OAI21XLTS U2267 ( .A0(n3665), .A1(n3669), .B0(n3666), .Y(n2006) );
OAI21XLTS U2268 ( .A0(n3620), .A1(n3624), .B0(n3621), .Y(n3651) );
NAND2BXLTS U2269 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2114) );
NAND2BXLTS U2270 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2113) );
NAND2BXLTS U2271 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2118) );
NAND2BXLTS U2272 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2190) );
NAND3XLTS U2273 ( .A(n4147), .B(n2188), .C(intDY_EWSW[60]), .Y(n2189) );
NOR2XLTS U2274 ( .A(intDX_EWSW[56]), .B(n2182), .Y(n2183) );
AOI211XLTS U2275 ( .A0(n2699), .A1(n2173), .B0(n2172), .C0(n2171), .Y(n2179)
);
NAND3XLTS U2276 ( .A(n2084), .B(n2083), .C(Raw_mant_NRM_SWR[32]), .Y(n2085)
);
AOI2BB2XLTS U2277 ( .B0(n1906), .B1(n2612), .A0N(n3802), .A1N(n3838), .Y(
n2613) );
AOI2BB2XLTS U2278 ( .B0(n3797), .B1(n2636), .A0N(n3802), .A1N(n3846), .Y(
n2637) );
CLKAND2X2TS U2279 ( .A(n3809), .B(n3739), .Y(n3743) );
OAI211XLTS U2280 ( .A0(n3779), .A1(n1925), .B0(n3778), .C0(n1916), .Y(n3828)
);
AOI2BB1XLTS U2281 ( .A0N(n3777), .A1N(n3801), .B0(n1900), .Y(n3831) );
OAI211XLTS U2282 ( .A0(n3784), .A1(n1903), .B0(n3783), .C0(n1916), .Y(n3823)
);
OAI211XLTS U2283 ( .A0(n3802), .A1(n3788), .B0(n3787), .C0(n1916), .Y(n3819)
);
OAI211XLTS U2284 ( .A0(n3795), .A1(n4067), .B0(n3794), .C0(n3799), .Y(n3818)
);
OAI211XLTS U2285 ( .A0(n3802), .A1(n3801), .B0(n3800), .C0(n1916), .Y(n3811)
);
NOR2XLTS U2286 ( .A(n2600), .B(n2599), .Y(n2747) );
OAI21XLTS U2287 ( .A0(n2276), .A1(n2275), .B0(n2274), .Y(n2278) );
NOR2XLTS U2288 ( .A(n4274), .B(DMP_SFG[23]), .Y(n3566) );
NOR2XLTS U2289 ( .A(n4119), .B(DMP_SFG[21]), .Y(n3579) );
INVX2TS U2290 ( .A(n3511), .Y(n3514) );
INVX2TS U2291 ( .A(n3512), .Y(n3513) );
OAI21XLTS U2292 ( .A0(n1982), .A1(n3505), .B0(n1981), .Y(n3550) );
NOR2XLTS U2293 ( .A(n3506), .B(n1982), .Y(n3551) );
NOR2XLTS U2294 ( .A(n4106), .B(DMP_SFG[19]), .Y(n3506) );
NOR2XLTS U2295 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n3190) );
INVX2TS U2296 ( .A(n3187), .Y(n3188) );
INVX2TS U2297 ( .A(n3186), .Y(n3189) );
OAI21XLTS U2298 ( .A0(n1976), .A1(n3295), .B0(n1975), .Y(n3519) );
NOR2XLTS U2299 ( .A(n3294), .B(n1976), .Y(n3520) );
NOR2XLTS U2300 ( .A(n4110), .B(DMP_SFG[13]), .Y(n3331) );
NOR2XLTS U2301 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n3371) );
NOR2XLTS U2302 ( .A(n3428), .B(n3410), .Y(n3376) );
NOR2XLTS U2303 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n3410) );
OAI21XLTS U2304 ( .A0(n1959), .A1(n3426), .B0(n1958), .Y(n3388) );
NOR2XLTS U2305 ( .A(n3427), .B(n1959), .Y(n3387) );
NOR2XLTS U2306 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n3428) );
NOR2XLTS U2307 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n3447) );
OAI21XLTS U2308 ( .A0(n3487), .A1(n3688), .B0(n3488), .Y(n3453) );
NOR2XLTS U2309 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n3470) );
NOR2XLTS U2310 ( .A(n4101), .B(DMP_SFG[5]), .Y(n3469) );
NOR2XLTS U2311 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n3487) );
OAI21XLTS U2312 ( .A0(n1951), .A1(n3684), .B0(n1950), .Y(n3466) );
NOR2XLTS U2313 ( .A(n3683), .B(n1951), .Y(n3467) );
INVX2TS U2314 ( .A(n3452), .Y(n3693) );
NOR2XLTS U2315 ( .A(n4115), .B(DMP_SFG[3]), .Y(n3683) );
NOR2XLTS U2316 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n3665) );
NOR2XLTS U2317 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n3670) );
NOR2XLTS U2318 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n3620) );
NAND3XLTS U2319 ( .A(n2770), .B(n2769), .C(n2768), .Y(n2772) );
MXI2XLTS U2320 ( .A(DmP_mant_SHT1_SW[25]), .B(Raw_mant_NRM_SWR[27]), .S0(
n2903), .Y(n2812) );
CLKAND2X2TS U2321 ( .A(n2580), .B(n2579), .Y(n2582) );
AND3X1TS U2322 ( .A(n2577), .B(n2576), .C(n2575), .Y(n2578) );
NOR2BX1TS U2323 ( .AN(n2574), .B(n2581), .Y(n3973) );
CLKAND2X2TS U2324 ( .A(DmP_mant_SFG_SWR[50]), .B(DMP_SFG[48]), .Y(n2039) );
XNOR2X1TS U2325 ( .A(DmP_mant_SFG_SWR[46]), .B(DMP_SFG[44]), .Y(n3482) );
XOR2XLTS U2326 ( .A(n4170), .B(DMP_SFG[44]), .Y(n3480) );
AOI2BB2XLTS U2327 ( .B0(n3856), .B1(n3816), .A0N(n3815), .A1N(n4194), .Y(
n3817) );
OAI21XLTS U2328 ( .A0(n3838), .A1(n3845), .B0(n3837), .Y(n3993) );
OAI21XLTS U2329 ( .A0(n3841), .A1(n3845), .B0(n3840), .Y(n3995) );
OAI21XLTS U2330 ( .A0(n3846), .A1(n3845), .B0(n3844), .Y(n3997) );
OAI21XLTS U2331 ( .A0(n3849), .A1(n3858), .B0(n3848), .Y(n3999) );
OAI21XLTS U2332 ( .A0(n3858), .A1(n3853), .B0(n3852), .Y(n4002) );
OAI21XLTS U2333 ( .A0(n3859), .A1(n3858), .B0(n3857), .Y(n4007) );
OAI21XLTS U2334 ( .A0(n2912), .A1(n4073), .B0(n2911), .Y(n2972) );
OAI21XLTS U2335 ( .A0(n3859), .A1(n3720), .B0(n3719), .Y(n4009) );
OAI21XLTS U2336 ( .A0(n3853), .A1(n3843), .B0(n3732), .Y(n4006) );
OAI21XLTS U2337 ( .A0(n3142), .A1(n3762), .B0(n2635), .Y(n2950) );
OAI21XLTS U2338 ( .A0(n3142), .A1(n3756), .B0(n2635), .Y(n2938) );
OAI21XLTS U2339 ( .A0(n3142), .A1(n3750), .B0(n2635), .Y(n2935) );
OAI21XLTS U2340 ( .A0(n3142), .A1(n3805), .B0(n2635), .Y(n2956) );
OAI21XLTS U2341 ( .A0(n3846), .A1(n3776), .B0(n3755), .Y(n3998) );
OAI21XLTS U2342 ( .A0(n3776), .A1(n3841), .B0(n3761), .Y(n3996) );
OAI21XLTS U2343 ( .A0(n3776), .A1(n3838), .B0(n3767), .Y(n3994) );
OAI21XLTS U2344 ( .A0(n3776), .A1(n3835), .B0(n3775), .Y(n3991) );
OAI21XLTS U2345 ( .A0(left_right_SHT2), .A1(n3831), .B0(n3780), .Y(n3989) );
NAND2BXLTS U2346 ( .AN(n3777), .B(n2737), .Y(n2741) );
OAI21XLTS U2347 ( .A0(n3858), .A1(n3826), .B0(n3785), .Y(n3987) );
AOI2BB2XLTS U2348 ( .B0(n3809), .B1(n2621), .A0N(n1907), .A1N(n2620), .Y(
n2622) );
OAI21XLTS U2349 ( .A0(n2620), .A1(n1925), .B0(n2746), .Y(n2618) );
OAI21XLTS U2350 ( .A0(n3858), .A1(n3822), .B0(n3789), .Y(n3985) );
AOI2BB2XLTS U2351 ( .B0(n3803), .B1(n3816), .A0N(n3815), .A1N(n3858), .Y(
n3796) );
OAI21XLTS U2352 ( .A0(n3858), .A1(n3814), .B0(n3804), .Y(n3981) );
NAND3XLTS U2353 ( .A(n2388), .B(n2746), .C(n2387), .Y(n2796) );
NAND2BXLTS U2354 ( .AN(n1907), .B(n2384), .Y(n2388) );
NAND2BXLTS U2355 ( .AN(n1907), .B(n2369), .Y(n2374) );
AOI2BB1XLTS U2356 ( .A0N(n1907), .A1N(n3841), .B0(n2748), .Y(n3154) );
OAI21XLTS U2357 ( .A0(n2747), .A1(n1903), .B0(n2746), .Y(n2748) );
NAND2BXLTS U2358 ( .AN(n1907), .B(n2399), .Y(n2403) );
OAI21XLTS U2359 ( .A0(n3790), .A1(n1903), .B0(n3832), .Y(n2585) );
OAI2BB1X1TS U2360 ( .A0N(n1899), .A1N(DmP_mant_SFG_SWR[53]), .B0(n2335), .Y(
n2004) );
XOR2XLTS U2361 ( .A(DmP_mant_SFG_SWR[50]), .B(DMP_SFG[48]), .Y(n3660) );
XNOR2X1TS U2362 ( .A(DmP_mant_SFG_SWR[48]), .B(DMP_SFG[46]), .Y(n3699) );
XOR2XLTS U2363 ( .A(n4134), .B(DMP_SFG[42]), .Y(n3439) );
AFHCINX2TS U2364 ( .CIN(n3221), .B(DMP_SFG[39]), .A(DmP_mant_SFG_SWR[41]),
.S(n3222), .CO(n3406) );
OAI22X1TS U2365 ( .A0(n3227), .A1(n2035), .B0(DMP_SFG[38]), .B1(
DmP_mant_SFG_SWR[40]), .Y(n3221) );
NOR2XLTS U2366 ( .A(n3568), .B(n3208), .Y(n2027) );
INVX2TS U2367 ( .A(n3208), .Y(n3210) );
INVX2TS U2368 ( .A(n3204), .Y(n3207) );
INVX2TS U2369 ( .A(n3205), .Y(n3206) );
INVX2TS U2370 ( .A(n3568), .Y(n3570) );
XOR2XLTS U2371 ( .A(n3574), .B(n3573), .Y(n3575) );
OAI21XLTS U2372 ( .A0(n3593), .A1(n3592), .B0(n3591), .Y(n3597) );
INVX2TS U2373 ( .A(n3594), .Y(n3596) );
INVX2TS U2374 ( .A(n3592), .Y(n3581) );
XOR2XLTS U2375 ( .A(n3593), .B(n3587), .Y(n3588) );
OAI21XLTS U2376 ( .A0(n3559), .A1(n3558), .B0(n3557), .Y(n3561) );
INVX2TS U2377 ( .A(n3553), .Y(n3555) );
INVX2TS U2378 ( .A(n3558), .Y(n3508) );
OAI21XLTS U2379 ( .A0(n3530), .A1(n3524), .B0(n3525), .Y(n3198) );
INVX2TS U2380 ( .A(n3524), .Y(n3526) );
XOR2XLTS U2381 ( .A(n3530), .B(n3529), .Y(n3532) );
INVX2TS U2382 ( .A(n3535), .Y(n3537) );
XOR2XLTS U2383 ( .A(n3545), .B(n3544), .Y(n3546) );
INVX2TS U2384 ( .A(n3194), .Y(n3543) );
INVX2TS U2385 ( .A(n3315), .Y(n3317) );
OAI21XLTS U2386 ( .A0(n3367), .A1(n3312), .B0(n3311), .Y(n3340) );
INVX2TS U2387 ( .A(n3309), .Y(n3312) );
INVX2TS U2388 ( .A(n3344), .Y(n3346) );
OAI21XLTS U2389 ( .A0(n3375), .A1(n3330), .B0(n3329), .Y(n3348) );
INVX2TS U2390 ( .A(n3327), .Y(n3330) );
XOR2XLTS U2391 ( .A(n3367), .B(n3366), .Y(n3368) );
OAI21XLTS U2392 ( .A0(n3434), .A1(n3379), .B0(n3378), .Y(n3400) );
INVX2TS U2393 ( .A(n3376), .Y(n3379) );
INVX2TS U2394 ( .A(n3377), .Y(n3378) );
INVX2TS U2395 ( .A(n3306), .Y(n3434) );
INVX2TS U2396 ( .A(n3324), .Y(n3451) );
NOR2XLTS U2397 ( .A(n4223), .B(DMP_EXP_EWSW[54]), .Y(n3923) );
OAI21XLTS U2398 ( .A0(n2912), .A1(n4018), .B0(n2810), .Y(n3076) );
OAI211XLTS U2399 ( .A0(n2111), .A1(n2110), .B0(n2109), .C0(n2108), .Y(n3867)
);
NAND4XLTS U2400 ( .A(n2763), .B(n2325), .C(n2077), .D(n2291), .Y(n3868) );
INVX2TS U2401 ( .A(left_right_SHT2), .Y(n3843) );
NAND3XLTS U2402 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4060), .C(
n4221), .Y(n3881) );
OAI211XLTS U2403 ( .A0(n2985), .A1(n3127), .B0(n2984), .C0(n2983), .Y(n1705)
);
AOI2BB2XLTS U2404 ( .B0(n2999), .B1(Data_array_SWR[46]), .A0N(n3641), .A1N(
n2982), .Y(n2983) );
OAI211XLTS U2405 ( .A0(n2965), .A1(n2901), .B0(n2876), .C0(n2875), .Y(n1739)
);
OAI211XLTS U2406 ( .A0(n2986), .A1(n2901), .B0(n2859), .C0(n2858), .Y(n1707)
);
OAI211XLTS U2407 ( .A0(n2968), .A1(n2901), .B0(n2846), .C0(n2845), .Y(n1711)
);
OAI211XLTS U2408 ( .A0(n3167), .A1(n3641), .B0(n2835), .C0(n2834), .Y(n1700)
);
AOI2BB2XLTS U2409 ( .B0(n2999), .B1(Data_array_SWR[51]), .A0N(n3168), .A1N(
n2916), .Y(n2834) );
AO22XLTS U2410 ( .A0(final_result_ieee[3]), .A1(n4004), .B0(n4003), .B1(
n4002), .Y(n1164) );
AO22XLTS U2411 ( .A0(n4010), .A1(n4009), .B0(final_result_ieee[48]), .B1(
n4229), .Y(n1161) );
AO22XLTS U2412 ( .A0(n4008), .A1(n4007), .B0(final_result_ieee[2]), .B1(
n4229), .Y(n1162) );
AO22XLTS U2413 ( .A0(n4008), .A1(n4006), .B0(final_result_ieee[47]), .B1(
n4005), .Y(n1163) );
AO22XLTS U2414 ( .A0(n4008), .A1(n4000), .B0(final_result_ieee[46]), .B1(
n4229), .Y(n1165) );
AO22XLTS U2415 ( .A0(n4008), .A1(n3999), .B0(final_result_ieee[4]), .B1(
n4005), .Y(n1166) );
AO22XLTS U2416 ( .A0(n4008), .A1(n3998), .B0(final_result_ieee[40]), .B1(
n4005), .Y(n1177) );
AO22XLTS U2417 ( .A0(n4008), .A1(n3997), .B0(final_result_ieee[10]), .B1(
n4004), .Y(n1178) );
AO22XLTS U2418 ( .A0(n4008), .A1(n3996), .B0(final_result_ieee[39]), .B1(
n4004), .Y(n1179) );
AO22XLTS U2419 ( .A0(n4008), .A1(n3995), .B0(final_result_ieee[11]), .B1(
n4004), .Y(n1180) );
AO22XLTS U2420 ( .A0(n4008), .A1(n3994), .B0(final_result_ieee[38]), .B1(
n4005), .Y(n1181) );
AO22XLTS U2421 ( .A0(n4008), .A1(n3993), .B0(final_result_ieee[12]), .B1(
n4004), .Y(n1182) );
AO22XLTS U2422 ( .A0(n3992), .A1(n3991), .B0(final_result_ieee[37]), .B1(
n4005), .Y(n1183) );
AO22XLTS U2423 ( .A0(n3992), .A1(n3990), .B0(final_result_ieee[13]), .B1(
n4005), .Y(n1184) );
AO22XLTS U2424 ( .A0(n3992), .A1(n3989), .B0(final_result_ieee[36]), .B1(
n4004), .Y(n1185) );
AO22XLTS U2425 ( .A0(n3992), .A1(n3988), .B0(final_result_ieee[14]), .B1(
n4004), .Y(n1186) );
AO22XLTS U2426 ( .A0(n3992), .A1(n3987), .B0(final_result_ieee[34]), .B1(
n4004), .Y(n1189) );
AO22XLTS U2427 ( .A0(n3992), .A1(n3986), .B0(final_result_ieee[16]), .B1(
n4005), .Y(n1190) );
AO22XLTS U2428 ( .A0(n3992), .A1(n3985), .B0(final_result_ieee[32]), .B1(
n4005), .Y(n1193) );
AO22XLTS U2429 ( .A0(n3992), .A1(n3984), .B0(final_result_ieee[18]), .B1(
n4229), .Y(n1194) );
AO22XLTS U2430 ( .A0(n3992), .A1(n3983), .B0(final_result_ieee[31]), .B1(
n4005), .Y(n1195) );
AO22XLTS U2431 ( .A0(n4010), .A1(n3982), .B0(final_result_ieee[19]), .B1(
n4229), .Y(n1196) );
AO22XLTS U2432 ( .A0(n4010), .A1(n3981), .B0(final_result_ieee[30]), .B1(
n4229), .Y(n1197) );
AO22XLTS U2433 ( .A0(n4010), .A1(n3980), .B0(final_result_ieee[20]), .B1(
n4005), .Y(n1198) );
AO22XLTS U2434 ( .A0(n3992), .A1(n3978), .B0(final_result_ieee[25]), .B1(
n4229), .Y(n1207) );
AO22XLTS U2435 ( .A0(Shift_reg_FLAGS_7[0]), .A1(n3973), .B0(n4004), .B1(
underflow_flag), .Y(n1287) );
OAI21XLTS U2436 ( .A0(n2587), .A1(n1914), .B0(n2586), .Y(n1156) );
OAI21XLTS U2437 ( .A0(n2593), .A1(n2802), .B0(n2584), .Y(n1159) );
OAI21XLTS U2438 ( .A0(n2941), .A1(n1914), .B0(n2789), .Y(n1168) );
OAI21XLTS U2439 ( .A0(n2950), .A1(n1914), .B0(n2798), .Y(n1170) );
OAI21XLTS U2440 ( .A0(n2938), .A1(n2802), .B0(n2791), .Y(n1172) );
OAI21XLTS U2441 ( .A0(n2935), .A1(n2802), .B0(n2794), .Y(n1174) );
OAI21XLTS U2442 ( .A0(n3160), .A1(n1914), .B0(n2801), .Y(n1188) );
OAI21XLTS U2443 ( .A0(n2947), .A1(n1914), .B0(n2795), .Y(n1192) );
OAI21XLTS U2444 ( .A0(n2944), .A1(n2802), .B0(n2797), .Y(n1199) );
OAI21XLTS U2445 ( .A0(n2959), .A1(n1914), .B0(n2788), .Y(n1201) );
OAI21XLTS U2446 ( .A0(n3154), .A1(n2802), .B0(n2799), .Y(n1203) );
OAI21XLTS U2447 ( .A0(n2953), .A1(n1914), .B0(n2793), .Y(n1205) );
AOI2BB2XLTS U2448 ( .B0(n4010), .B1(n3876), .A0N(n1935), .A1N(
final_result_ieee[58]), .Y(n1679) );
AOI2BB2XLTS U2449 ( .B0(n4010), .B1(n3875), .A0N(n1935), .A1N(
final_result_ieee[57]), .Y(n1680) );
AOI2BB2XLTS U2450 ( .B0(n4010), .B1(n3872), .A0N(n1935), .A1N(
final_result_ieee[54]), .Y(n1683) );
AOI2BB2XLTS U2451 ( .B0(n4010), .B1(n3871), .A0N(n1935), .A1N(
final_result_ieee[53]), .Y(n1684) );
AOI2BB2XLTS U2452 ( .B0(n4010), .B1(n3870), .A0N(n1935), .A1N(
final_result_ieee[52]), .Y(n1685) );
XNOR2X1TS U2453 ( .A(n3483), .B(n3482), .Y(n3484) );
OAI211XLTS U2454 ( .A0(n3005), .A1(n3127), .B0(n3004), .C0(n3003), .Y(n1708)
);
OAI211XLTS U2455 ( .A0(n2975), .A1(n3168), .B0(n2974), .C0(n2973), .Y(n1704)
);
OAI211XLTS U2456 ( .A0(n3036), .A1(n3116), .B0(n3035), .C0(n3034), .Y(n1718)
);
OAI211XLTS U2457 ( .A0(n3167), .A1(n1917), .B0(n3001), .C0(n3000), .Y(n1699)
);
OAI211XLTS U2458 ( .A0(n2923), .A1(n3168), .B0(n2922), .C0(n2921), .Y(n1701)
);
OAI211XLTS U2459 ( .A0(n2919), .A1(n3168), .B0(n2918), .C0(n2917), .Y(n1702)
);
OAI2BB1X1TS U2460 ( .A0N(n3629), .A1N(n2339), .B0(n2338), .Y(n1215) );
OAI21XLTS U2461 ( .A0(n2593), .A1(n1915), .B0(n2509), .Y(n1152) );
OAI21XLTS U2462 ( .A0(n2590), .A1(n1895), .B0(n2508), .Y(n1153) );
MX2X1TS U2463 ( .A(n3990), .B(DmP_mant_SFG_SWR[15]), .S0(n3850), .Y(n1140)
);
MX2X1TS U2464 ( .A(n4002), .B(DmP_mant_SFG_SWR[5]), .S0(n3860), .Y(n1150) );
OAI211XLTS U2465 ( .A0(n3023), .A1(n3086), .B0(n3022), .C0(n3021), .Y(n1714)
);
OAI211XLTS U2466 ( .A0(n3033), .A1(n3168), .B0(n3025), .C0(n3024), .Y(n1716)
);
OAI211XLTS U2467 ( .A0(n2991), .A1(n3116), .B0(n2990), .C0(n2989), .Y(n1706)
);
OAI211XLTS U2468 ( .A0(n3032), .A1(n3127), .B0(n3031), .C0(n3030), .Y(n1709)
);
OAI211XLTS U2469 ( .A0(n3013), .A1(n3086), .B0(n3012), .C0(n3011), .Y(n1730)
);
OAI211XLTS U2470 ( .A0(n2982), .A1(n3116), .B0(n2914), .C0(n2913), .Y(n1703)
);
OAI211XLTS U2471 ( .A0(n2995), .A1(n3127), .B0(n2994), .C0(n2993), .Y(n1736)
);
OAI211XLTS U2472 ( .A0(n3038), .A1(n3086), .B0(n2967), .C0(n2966), .Y(n1738)
);
OAI211XLTS U2473 ( .A0(n3062), .A1(n3168), .B0(n2926), .C0(n2925), .Y(n1732)
);
OAI211XLTS U2474 ( .A0(n3042), .A1(n3116), .B0(n3041), .C0(n3040), .Y(n1737)
);
MXI2XLTS U2475 ( .A(n3951), .B(n3966), .S0(n3887), .Y(n1887) );
MX2X1TS U2476 ( .A(n4006), .B(DmP_mant_SFG_SWR[49]), .S0(n3827), .Y(n1106)
);
OAI21XLTS U2477 ( .A0(n2941), .A1(n1915), .B0(n2611), .Y(n1108) );
OAI21XLTS U2478 ( .A0(n2950), .A1(n1895), .B0(n2617), .Y(n1109) );
OAI21XLTS U2479 ( .A0(n2938), .A1(n1895), .B0(n2605), .Y(n1110) );
OAI21XLTS U2480 ( .A0(n2935), .A1(n1915), .B0(n2643), .Y(n1111) );
OAI21XLTS U2481 ( .A0(n2956), .A1(n1895), .B0(n2634), .Y(n1112) );
OAI21XLTS U2482 ( .A0(n2947), .A1(n1915), .B0(n2624), .Y(n1120) );
OAI21XLTS U2483 ( .A0(n2784), .A1(n3866), .B0(n2783), .Y(n1208) );
MX2X1TS U2484 ( .A(n3867), .B(LZD_output_NRM2_EW[4]), .S0(n3866), .Y(n1210)
);
OAI21XLTS U2485 ( .A0(n2766), .A1(n3866), .B0(n2765), .Y(n1212) );
MX2X1TS U2486 ( .A(n3868), .B(LZD_output_NRM2_EW[2]), .S0(n4271), .Y(n1213)
);
XOR2XLTS U2487 ( .A(n3609), .B(n3608), .Y(n3613) );
XOR2XLTS U2488 ( .A(n4253), .B(DMP_SFG[50]), .Y(n3608) );
XNOR2X1TS U2489 ( .A(n3698), .B(n3697), .Y(n3705) );
XNOR2X1TS U2490 ( .A(n3700), .B(n3699), .Y(n3703) );
XOR2XLTS U2491 ( .A(n3440), .B(n3439), .Y(n3446) );
XNOR2X1TS U2492 ( .A(n3442), .B(n3441), .Y(n3444) );
XOR2XLTS U2493 ( .A(n4135), .B(DMP_SFG[40]), .Y(n3404) );
XOR2XLTS U2494 ( .A(DmP_mant_SFG_SWR[40]), .B(DMP_SFG[38]), .Y(n3226) );
XOR2XLTS U2495 ( .A(n3232), .B(n3231), .Y(n3236) );
XOR2XLTS U2496 ( .A(DmP_mant_SFG_SWR[38]), .B(DMP_SFG[36]), .Y(n3243) );
XOR2XLTS U2497 ( .A(DmP_mant_SFG_SWR[36]), .B(DMP_SFG[34]), .Y(n3249) );
XOR2XLTS U2498 ( .A(DmP_mant_SFG_SWR[34]), .B(DMP_SFG[32]), .Y(n3260) );
XOR2XLTS U2499 ( .A(n3267), .B(n3266), .Y(n3268) );
XOR2XLTS U2500 ( .A(DmP_mant_SFG_SWR[32]), .B(DMP_SFG[30]), .Y(n3266) );
XOR2XLTS U2501 ( .A(n3318), .B(n3319), .Y(n3323) );
XOR2XLTS U2502 ( .A(n3353), .B(n3352), .Y(n3354) );
XOR2XLTS U2503 ( .A(n3383), .B(n3382), .Y(n3384) );
MXI2XLTS U2504 ( .A(n4273), .B(n4272), .S0(n1910), .Y(n1268) );
AO22XLTS U2505 ( .A0(n3864), .A1(n3863), .B0(ADD_OVRFLW_NRM), .B1(n3971),
.Y(n1276) );
OAI21XLTS U2506 ( .A0(n3935), .A1(n3938), .B0(n3137), .Y(n2732) );
OAI21XLTS U2507 ( .A0(n4209), .A1(n2734), .B0(n2657), .Y(n1612) );
OAI21XLTS U2508 ( .A0(n4184), .A1(n2655), .B0(n2654), .Y(n1614) );
OAI21XLTS U2509 ( .A0(n4213), .A1(n2655), .B0(n2651), .Y(n1615) );
OAI21XLTS U2510 ( .A0(n4045), .A1(n2655), .B0(n2653), .Y(n1616) );
OAI222X1TS U2511 ( .A0(n2658), .A1(n4268), .B0(n4212), .B1(
Shift_reg_FLAGS_7_6), .C0(n4012), .C1(n2734), .Y(n1619) );
OAI21XLTS U2512 ( .A0(n2784), .A1(n2912), .B0(n2782), .Y(n1692) );
OAI211XLTS U2513 ( .A0(n3128), .A1(n3127), .B0(n3126), .C0(n3125), .Y(n1713)
);
OAI211XLTS U2514 ( .A0(n3019), .A1(n3168), .B0(n2884), .C0(n2883), .Y(n1715)
);
OAI211XLTS U2515 ( .A0(n3073), .A1(n3127), .B0(n3072), .C0(n3071), .Y(n1717)
);
OAI211XLTS U2516 ( .A0(n2977), .A1(n3168), .B0(n2930), .C0(n2929), .Y(n1720)
);
OAI211XLTS U2517 ( .A0(n3080), .A1(n3116), .B0(n3079), .C0(n3078), .Y(n1721)
);
OAI211XLTS U2518 ( .A0(n2824), .A1(n2901), .B0(n2823), .C0(n2822), .Y(n1723)
);
AOI2BB2XLTS U2519 ( .B0(n3088), .B1(n3076), .A0N(n2820), .A1N(n1931), .Y(
n2823) );
OAI211XLTS U2520 ( .A0(n3010), .A1(n1931), .B0(n2333), .C0(n2332), .Y(n1727)
);
OAI211XLTS U2521 ( .A0(n3056), .A1(n1931), .B0(n2819), .C0(n2818), .Y(n1728)
);
AOI2BB2XLTS U2522 ( .B0(n2999), .B1(Data_array_SWR[23]), .A0N(n1917), .A1N(
n2817), .Y(n2818) );
OAI211XLTS U2523 ( .A0(n3056), .A1(n3116), .B0(n3055), .C0(n3054), .Y(n1729)
);
OAI211XLTS U2524 ( .A0(n2924), .A1(n2901), .B0(n2840), .C0(n2839), .Y(n1731)
);
OAI211XLTS U2525 ( .A0(n3117), .A1(n3116), .B0(n3115), .C0(n3114), .Y(n1733)
);
OAI211XLTS U2526 ( .A0(n3066), .A1(n3086), .B0(n3065), .C0(n3064), .Y(n1734)
);
OAI211XLTS U2527 ( .A0(n2992), .A1(n2901), .B0(n2870), .C0(n2869), .Y(n1735)
);
OAI211XLTS U2528 ( .A0(n3108), .A1(n3127), .B0(n3107), .C0(n3106), .Y(n1740)
);
OAI211XLTS U2529 ( .A0(n3050), .A1(n3116), .B0(n3049), .C0(n3048), .Y(n1741)
);
OAI211XLTS U2530 ( .A0(n3043), .A1(n2901), .B0(n2900), .C0(n2899), .Y(n1743)
);
OAI211XLTS U2531 ( .A0(n3093), .A1(n3127), .B0(n3092), .C0(n3091), .Y(n1744)
);
OAI211XLTS U2532 ( .A0(n3100), .A1(n3116), .B0(n3099), .C0(n3098), .Y(n1745)
);
OAI211XLTS U2533 ( .A0(n3087), .A1(n3086), .B0(n3085), .C0(n3084), .Y(n1746)
);
OAI211XLTS U2534 ( .A0(n2890), .A1(n2901), .B0(n2889), .C0(n2888), .Y(n1747)
);
OAI211XLTS U2535 ( .A0(n3060), .A1(n3127), .B0(n3059), .C0(n3058), .Y(n1748)
);
OAI211XLTS U2536 ( .A0(n3640), .A1(n3116), .B0(n2830), .C0(n2829), .Y(n1749)
);
AOI2BB2XLTS U2537 ( .B0(n3088), .B1(n2860), .A0N(n3635), .A1N(n1931), .Y(
n2830) );
OAI211XLTS U2538 ( .A0(n3635), .A1(n3086), .B0(n2862), .C0(n2861), .Y(n1750)
);
AO21XLTS U2539 ( .A0(n3644), .A1(n3643), .B0(n3642), .Y(n1751) );
OAI211XLTS U2540 ( .A0(n2820), .A1(n1918), .B0(n2809), .C0(n2808), .Y(n1725)
);
OAI21XLTS U2541 ( .A0(n2766), .A1(n2898), .B0(n2764), .Y(n1695) );
OAI21XLTS U2542 ( .A0(n3169), .A1(n3843), .B0(n2912), .Y(n1752) );
AO22XLTS U2543 ( .A0(n3895), .A1(Data_X[62]), .B0(n3916), .B1(intDX_EWSW[62]), .Y(n1820) );
MXI2XLTS U2544 ( .A(n3866), .B(n3701), .S0(n3887), .Y(n1884) );
OAI21XLTS U2545 ( .A0(n3883), .A1(n2340), .B0(n3881), .Y(n1890) );
OR2X1TS U2546 ( .A(n1903), .B(n1905), .Y(n1897) );
OAI22X2TS U2547 ( .A0(n3659), .A1(n2002), .B0(n4168), .B1(DMP_SFG[48]), .Y(
n3630) );
AFHCINX2TS U2548 ( .CIN(n3220), .B(n4139), .A(DMP_SFG[39]), .S(n3224), .CO(
n3405) );
AFHCINX2TS U2549 ( .CIN(n3272), .B(DMP_SFG[29]), .A(DmP_mant_SFG_SWR[31]),
.S(n3273), .CO(n3267) );
OAI22X2TS U2550 ( .A0(n3261), .A1(n2032), .B0(DMP_SFG[32]), .B1(
DmP_mant_SFG_SWR[34]), .Y(n3255) );
AFHCINX2TS U2551 ( .CIN(n3181), .B(DMP_SFG[31]), .A(DmP_mant_SFG_SWR[33]),
.S(n3182), .CO(n3261) );
INVX2TS U2552 ( .A(n2746), .Y(n1900) );
INVX2TS U2553 ( .A(n1900), .Y(n1901) );
INVX2TS U2554 ( .A(n1925), .Y(n1902) );
INVX2TS U2555 ( .A(n1902), .Y(n1903) );
INVX2TS U2556 ( .A(n3724), .Y(n1904) );
INVX2TS U2557 ( .A(n1904), .Y(n1905) );
INVX2TS U2558 ( .A(n3777), .Y(n1906) );
INVX2TS U2559 ( .A(n1906), .Y(n1907) );
INVX2TS U2560 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1909) );
INVX2TS U2561 ( .A(n1909), .Y(n1910) );
INVX2TS U2562 ( .A(n3743), .Y(n1911) );
INVX2TS U2563 ( .A(n1911), .Y(n1912) );
INVX2TS U2564 ( .A(n2802), .Y(n1913) );
INVX2TS U2565 ( .A(n1913), .Y(n1914) );
INVX2TS U2566 ( .A(n1929), .Y(n1915) );
INVX2TS U2567 ( .A(n1896), .Y(n1917) );
INVX2TS U2568 ( .A(n2375), .Y(n1919) );
INVX2TS U2569 ( .A(n1919), .Y(n1920) );
INVX2TS U2570 ( .A(n3795), .Y(n1921) );
INVX2TS U2571 ( .A(n3795), .Y(n1922) );
INVX2TS U2572 ( .A(n1897), .Y(n1923) );
INVX2TS U2573 ( .A(n1897), .Y(n1924) );
INVX2TS U2574 ( .A(n3809), .Y(n1925) );
INVX2TS U2575 ( .A(n3161), .Y(n1926) );
OAI222X1TS U2576 ( .A0(n2534), .A1(n4095), .B0(n4224), .B1(
Shift_reg_FLAGS_7_6), .C0(n4036), .C1(n2734), .Y(n1620) );
OAI222X1TS U2577 ( .A0(n2734), .A1(n4268), .B0(n4270), .B1(
Shift_reg_FLAGS_7_6), .C0(n4012), .C1(n2536), .Y(n1290) );
OAI222X1TS U2578 ( .A0(n2734), .A1(n4267), .B0(n4228), .B1(
Shift_reg_FLAGS_7_6), .C0(n4053), .C1(n2536), .Y(n1292) );
INVX2TS U2579 ( .A(Shift_reg_FLAGS_7_6), .Y(n3161) );
OAI21XLTS U2580 ( .A0(n2956), .A1(n1927), .B0(n2955), .Y(n1175) );
OAI21XLTS U2581 ( .A0(n2950), .A1(n1927), .B0(n2949), .Y(n1169) );
OAI21XLTS U2582 ( .A0(n2938), .A1(n2964), .B0(n2937), .Y(n1171) );
OAI21XLTS U2583 ( .A0(n3160), .A1(n2964), .B0(n2932), .Y(n1187) );
OAI21XLTS U2584 ( .A0(n2593), .A1(n2964), .B0(n2592), .Y(n1160) );
OAI21XLTS U2585 ( .A0(n2959), .A1(n2964), .B0(n2958), .Y(n1202) );
OAI21XLTS U2586 ( .A0(n2953), .A1(n2964), .B0(n2952), .Y(n1206) );
OAI21XLTS U2587 ( .A0(n2944), .A1(n2964), .B0(n2943), .Y(n1200) );
OAI21XLTS U2588 ( .A0(n2941), .A1(n2964), .B0(n2940), .Y(n1167) );
OAI21XLTS U2589 ( .A0(n2590), .A1(n2964), .B0(n2589), .Y(n1158) );
OAI21XLTS U2590 ( .A0(n2593), .A1(n3159), .B0(n2496), .Y(n1104) );
OAI21XLTS U2591 ( .A0(n2590), .A1(n3159), .B0(n2507), .Y(n1103) );
OAI21XLTS U2592 ( .A0(n2587), .A1(n3159), .B0(n2497), .Y(n1102) );
OAI21XLTS U2593 ( .A0(n2947), .A1(n1919), .B0(n2650), .Y(n1136) );
OAI21XLTS U2594 ( .A0(n2956), .A1(n1919), .B0(n2648), .Y(n1144) );
OAI21XLTS U2595 ( .A0(n2935), .A1(n3159), .B0(n2646), .Y(n1145) );
OAI21XLTS U2596 ( .A0(n2938), .A1(n3159), .B0(n2645), .Y(n1146) );
OAI21XLTS U2597 ( .A0(n2950), .A1(n3159), .B0(n2644), .Y(n1147) );
OAI21XLTS U2598 ( .A0(n2941), .A1(n3159), .B0(n2647), .Y(n1148) );
CLKBUFX2TS U2599 ( .A(n2800), .Y(n1928) );
INVX2TS U2600 ( .A(n2800), .Y(n2964) );
INVX2TS U2601 ( .A(n1895), .Y(n1929) );
INVX2TS U2602 ( .A(n1895), .Y(n1930) );
INVX2TS U2603 ( .A(n2981), .Y(n1931) );
NOR2X1TS U2604 ( .A(n4021), .B(n4136), .Y(n1932) );
NOR2X1TS U2605 ( .A(n4021), .B(n4136), .Y(n1933) );
NOR2XLTS U2606 ( .A(n4021), .B(n4136), .Y(n3739) );
OAI22X1TS U2607 ( .A0(n3440), .A1(n1999), .B0(n4134), .B1(DMP_SFG[42]), .Y(
n3460) );
INVX2TS U2608 ( .A(n2638), .Y(n1934) );
INVX2TS U2609 ( .A(n4229), .Y(n1935) );
OAI22X1TS U2610 ( .A0(n3405), .A1(n1998), .B0(n4135), .B1(DMP_SFG[40]), .Y(
n3421) );
NOR2X1TS U2611 ( .A(n3701), .B(OP_FLAG_SFG), .Y(n3863) );
INVX2TS U2612 ( .A(n3802), .Y(n1936) );
OAI21XLTS U2613 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n4011), .B0(n4033), .Y(
n2308) );
OAI21XLTS U2614 ( .A0(intDY_EWSW[35]), .A1(n4023), .B0(intDY_EWSW[34]), .Y(
n2214) );
NOR2XLTS U2615 ( .A(n4118), .B(DMP_SFG[22]), .Y(n1984) );
NOR2XLTS U2616 ( .A(n2163), .B(intDX_EWSW[16]), .Y(n2164) );
NOR2XLTS U2617 ( .A(n2560), .B(n3874), .Y(n2565) );
NAND2X1TS U2618 ( .A(n2270), .B(n2281), .Y(n2095) );
NOR2XLTS U2619 ( .A(n3592), .B(n3594), .Y(n2023) );
NOR2XLTS U2620 ( .A(n4100), .B(DMP_SFG[6]), .Y(n1953) );
OAI21XLTS U2621 ( .A0(intDY_EWSW[21]), .A1(n4145), .B0(intDY_EWSW[20]), .Y(
n2162) );
OAI21XLTS U2622 ( .A0(n3727), .A1(n4067), .B0(n3791), .Y(n3728) );
OR2X1TS U2623 ( .A(n4117), .B(DMP_SFG[24]), .Y(n1991) );
OAI21XLTS U2624 ( .A0(n3410), .A1(n3429), .B0(n3411), .Y(n3377) );
NOR2XLTS U2625 ( .A(n2229), .B(n2228), .Y(n2242) );
OAI21XLTS U2626 ( .A0(n2206), .A1(n2205), .B0(n2204), .Y(n2208) );
OAI211XLTS U2627 ( .A0(n4249), .A1(n1911), .B0(n1916), .C0(n2607), .Y(n2608)
);
NAND2X1TS U2628 ( .A(n2750), .B(n4018), .Y(n2299) );
OAI21XLTS U2629 ( .A0(n3205), .A1(n1993), .B0(n1992), .Y(n1994) );
INVX2TS U2630 ( .A(n3190), .Y(n3192) );
NOR2XLTS U2631 ( .A(n4275), .B(DMP_SFG[15]), .Y(n3294) );
NOR2XLTS U2632 ( .A(n4112), .B(DMP_SFG[11]), .Y(n3357) );
NOR2XLTS U2633 ( .A(n4097), .B(DMP_SFG[9]), .Y(n3391) );
NOR2XLTS U2634 ( .A(n3492), .B(n3487), .Y(n3454) );
OAI21XLTS U2635 ( .A0(Data_array_SWR[52]), .A1(n1905), .B0(n3141), .Y(n3788)
);
NOR2XLTS U2636 ( .A(n2493), .B(n2492), .Y(n2620) );
OAI21XLTS U2637 ( .A0(n3574), .A1(n3568), .B0(n3569), .Y(n3216) );
NOR2XLTS U2638 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n3592) );
NOR2XLTS U2639 ( .A(n4096), .B(DMP_SFG[17]), .Y(n3523) );
INVX2TS U2640 ( .A(n3185), .Y(n3521) );
OAI21XLTS U2641 ( .A0(n3451), .A1(n3326), .B0(n3325), .Y(n3361) );
NOR2XLTS U2642 ( .A(n4099), .B(DMP_SFG[7]), .Y(n3427) );
OAI21XLTS U2643 ( .A0(n3671), .A1(n3670), .B0(n3669), .Y(n3673) );
NOR2XLTS U2644 ( .A(n4266), .B(DMP_EXP_EWSW[56]), .Y(n3931) );
INVX2TS U2645 ( .A(n1914), .Y(n2962) );
OAI2BB1X1TS U2646 ( .A0N(n4253), .A1N(DMP_SFG[50]), .B0(n2003), .Y(n2335) );
OAI211XLTS U2647 ( .A0(n1907), .A1(n3779), .B0(n3151), .C0(n3150), .Y(n3152)
);
OAI211XLTS U2648 ( .A0(n1907), .A1(n2736), .B0(n2481), .C0(n2480), .Y(n2482)
);
XOR2XLTS U2649 ( .A(n3290), .B(n3289), .Y(n3291) );
OAI21XLTS U2650 ( .A0(n3580), .A1(n3579), .B0(n3578), .Y(n3583) );
OAI21XLTS U2651 ( .A0(n3451), .A1(n3427), .B0(n3426), .Y(n3432) );
INVX2TS U2652 ( .A(n3465), .Y(n3687) );
OAI21XLTS U2653 ( .A0(DmP_EXP_EWSW[55]), .A1(n4212), .B0(n3927), .Y(n3924)
);
CLKBUFX2TS U2654 ( .A(n2920), .Y(n3063) );
AFHCINX2TS U2655 ( .CIN(n3460), .B(n4137), .A(DMP_SFG[43]), .S(n3464), .CO(
n3481) );
INVX2TS U2656 ( .A(n3977), .Y(n4010) );
OAI21XLTS U2657 ( .A0(n3835), .A1(n3845), .B0(n3834), .Y(n3990) );
AOI211XLTS U2658 ( .A0(n1936), .A1(n3812), .B0(n3153), .C0(n3152), .Y(n3157)
);
OAI21XLTS U2659 ( .A0(n3142), .A1(n3769), .B0(n2635), .Y(n2941) );
AND3X1TS U2660 ( .A(n2741), .B(n1901), .C(n2740), .Y(n3160) );
AOI211XLTS U2661 ( .A0(n1936), .A1(n3816), .B0(n2483), .C0(n2482), .Y(n2587)
);
XNOR2X1TS U2662 ( .A(n3659), .B(n3658), .Y(n3664) );
AFHCINX2TS U2663 ( .CIN(n3271), .B(n4123), .A(DMP_SFG[29]), .S(n3275), .CO(
n3265) );
INVX2TS U2664 ( .A(Shift_reg_FLAGS_7_5), .Y(n3964) );
OAI211XLTS U2665 ( .A0(n3641), .A1(n3640), .B0(n3639), .C0(n3638), .Y(n3642)
);
NOR4BXLTS U2666 ( .AN(n2763), .B(n2762), .C(n2761), .D(n2760), .Y(n2766) );
AOI32X1TS U2667 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n3170), .B1(n4221), .Y(n3887)
);
OAI211XLTS U2668 ( .A0(n2980), .A1(n3086), .B0(n2979), .C0(n2978), .Y(n1722)
);
OAI21XLTS U2669 ( .A0(n2590), .A1(n1914), .B0(n2583), .Y(n1157) );
OAI21XLTS U2670 ( .A0(n2956), .A1(n1914), .B0(n2790), .Y(n1176) );
OAI211XLTS U2671 ( .A0(n3006), .A1(n3086), .B0(n2970), .C0(n2969), .Y(n1710)
);
OAI211XLTS U2672 ( .A0(n3020), .A1(n3127), .B0(n3008), .C0(n3007), .Y(n1712)
);
OAI21XLTS U2673 ( .A0(n2587), .A1(n1915), .B0(n2487), .Y(n1154) );
OAI222X1TS U2674 ( .A0(n2534), .A1(n4267), .B0(n4211), .B1(
Shift_reg_FLAGS_7_6), .C0(n4053), .C1(n2734), .Y(n1621) );
OAI211XLTS U2675 ( .A0(n2927), .A1(n2901), .B0(n2852), .C0(n2851), .Y(n1719)
);
OAI211XLTS U2676 ( .A0(n3046), .A1(n3086), .B0(n3045), .C0(n3044), .Y(n1742)
);
OAI211XLTS U2677 ( .A0(n2824), .A1(n1918), .B0(n2815), .C0(n2814), .Y(n1724)
);
CLKBUFX2TS U2678 ( .A(n4013), .Y(n3971) );
NOR2BX1TS U2679 ( .AN(OP_FLAG_SFG), .B(n3971), .Y(n3606) );
CLKBUFX2TS U2680 ( .A(n3606), .Y(n3504) );
NAND2X1TS U2681 ( .A(n1942), .B(n4272), .Y(n3615) );
NOR2XLTS U2682 ( .A(n4103), .B(DMP_SFG[0]), .Y(n1945) );
NAND2X1TS U2683 ( .A(n4103), .B(DMP_SFG[0]), .Y(n1944) );
NOR2XLTS U2684 ( .A(n4102), .B(DMP_SFG[1]), .Y(n3646) );
NOR2XLTS U2685 ( .A(n4116), .B(DMP_SFG[2]), .Y(n1947) );
NOR2XLTS U2686 ( .A(n3646), .B(n1947), .Y(n1949) );
NAND2X1TS U2687 ( .A(n4102), .B(DMP_SFG[1]), .Y(n3645) );
NAND2X1TS U2688 ( .A(n4116), .B(DMP_SFG[2]), .Y(n1946) );
AOI21X1TS U2689 ( .A0(n3619), .A1(n1949), .B0(n1948), .Y(n3465) );
NAND2X1TS U2690 ( .A(n3467), .B(n1955), .Y(n1957) );
NAND2X1TS U2691 ( .A(n4115), .B(DMP_SFG[3]), .Y(n3684) );
NAND2X1TS U2692 ( .A(n4114), .B(DMP_SFG[4]), .Y(n1950) );
NAND2X1TS U2693 ( .A(n4101), .B(DMP_SFG[5]), .Y(n3468) );
NAND2X1TS U2694 ( .A(n4100), .B(DMP_SFG[6]), .Y(n1952) );
AOI21X1TS U2695 ( .A0(n1955), .A1(n3466), .B0(n1954), .Y(n1956) );
OAI21X1TS U2696 ( .A0(n3465), .A1(n1957), .B0(n1956), .Y(n3324) );
NAND2X1TS U2697 ( .A(n3387), .B(n1963), .Y(n3326) );
NAND2X1TS U2698 ( .A(n3327), .B(n1969), .Y(n1971) );
NAND2X1TS U2699 ( .A(n4099), .B(DMP_SFG[7]), .Y(n3426) );
NAND2X1TS U2700 ( .A(n4098), .B(DMP_SFG[8]), .Y(n1958) );
NAND2X1TS U2701 ( .A(n4097), .B(DMP_SFG[9]), .Y(n3392) );
NAND2X1TS U2702 ( .A(n4113), .B(DMP_SFG[10]), .Y(n1960) );
AOI21X1TS U2703 ( .A0(n1963), .A1(n3388), .B0(n1962), .Y(n3325) );
NAND2X1TS U2704 ( .A(n4112), .B(DMP_SFG[11]), .Y(n3358) );
NAND2X1TS U2705 ( .A(n4111), .B(DMP_SFG[12]), .Y(n1964) );
NAND2X1TS U2706 ( .A(n4110), .B(DMP_SFG[13]), .Y(n3332) );
NAND2X1TS U2707 ( .A(n4109), .B(DMP_SFG[14]), .Y(n1966) );
AOI21X1TS U2708 ( .A0(n1969), .A1(n3328), .B0(n1968), .Y(n1970) );
OAI21X1TS U2709 ( .A0(n3325), .A1(n1971), .B0(n1970), .Y(n1972) );
AOI21X1TS U2710 ( .A0(n3324), .A1(n1973), .B0(n1972), .Y(n3185) );
NAND2X1TS U2711 ( .A(n3520), .B(n1980), .Y(n3186) );
NAND2X1TS U2712 ( .A(n3551), .B(n1986), .Y(n1988) );
NOR2X1TS U2713 ( .A(n3186), .B(n1988), .Y(n3203) );
INVX2TS U2714 ( .A(n3566), .Y(n1974) );
NAND2X1TS U2715 ( .A(n1974), .B(n1991), .Y(n3204) );
NAND2X1TS U2716 ( .A(n3203), .B(n1995), .Y(n1997) );
NAND2X1TS U2717 ( .A(n4275), .B(DMP_SFG[15]), .Y(n3295) );
NAND2X1TS U2718 ( .A(n4108), .B(DMP_SFG[16]), .Y(n1975) );
NAND2X1TS U2719 ( .A(n4096), .B(DMP_SFG[17]), .Y(n3522) );
NAND2X1TS U2720 ( .A(n4107), .B(DMP_SFG[18]), .Y(n1977) );
AOI21X1TS U2721 ( .A0(n1980), .A1(n3519), .B0(n1979), .Y(n3187) );
NAND2X1TS U2722 ( .A(n4106), .B(DMP_SFG[19]), .Y(n3505) );
NAND2X1TS U2723 ( .A(n4105), .B(DMP_SFG[20]), .Y(n1981) );
NAND2X1TS U2724 ( .A(n4119), .B(DMP_SFG[21]), .Y(n3578) );
NAND2X1TS U2725 ( .A(n4118), .B(DMP_SFG[22]), .Y(n1983) );
AOI21X1TS U2726 ( .A0(n1986), .A1(n3550), .B0(n1985), .Y(n1987) );
OAI21X1TS U2727 ( .A0(n3187), .A1(n1988), .B0(n1987), .Y(n3202) );
NAND2X1TS U2728 ( .A(n4274), .B(DMP_SFG[23]), .Y(n3565) );
INVX2TS U2729 ( .A(n3565), .Y(n1990) );
CLKAND2X2TS U2730 ( .A(n4117), .B(DMP_SFG[24]), .Y(n1989) );
AOI21X1TS U2731 ( .A0(n1991), .A1(n1990), .B0(n1989), .Y(n3205) );
NAND2X1TS U2732 ( .A(n4104), .B(DMP_SFG[25]), .Y(n1992) );
AOI21X1TS U2733 ( .A0(n3202), .A1(n1995), .B0(n1994), .Y(n1996) );
ACHCONX4TS U2734 ( .A(DmP_mant_SFG_SWR[39]), .B(n1938), .CI(n3232), .CON(
n3225) );
CLKAND2X2TS U2735 ( .A(n4169), .B(DMP_SFG[46]), .Y(n2001) );
NAND2X1TS U2736 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n3624) );
NAND2X1TS U2737 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n3621) );
NAND2X1TS U2738 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n3669) );
NAND2X1TS U2739 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n3666) );
AOI21X1TS U2740 ( .A0(n2007), .A1(n3651), .B0(n2006), .Y(n3452) );
NAND2X1TS U2741 ( .A(n3454), .B(n2009), .Y(n2011) );
NAND2X1TS U2742 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n3688) );
NAND2X1TS U2743 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n3488) );
NAND2X1TS U2744 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n3471) );
NAND2X1TS U2745 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n3448) );
AOI21X1TS U2746 ( .A0(n3453), .A1(n2009), .B0(n2008), .Y(n2010) );
OAI21X1TS U2747 ( .A0(n3452), .A1(n2011), .B0(n2010), .Y(n3306) );
NAND2X1TS U2748 ( .A(n3376), .B(n2013), .Y(n3308) );
NOR2X1TS U2749 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n3349) );
NOR2X1TS U2750 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n3344) );
NOR2X1TS U2751 ( .A(n3349), .B(n3344), .Y(n3309) );
NAND2X1TS U2752 ( .A(n3309), .B(n2015), .Y(n2017) );
NOR2X1TS U2753 ( .A(n3308), .B(n2017), .Y(n2019) );
NAND2X1TS U2754 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n3429) );
NAND2X1TS U2755 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n3411) );
NAND2X1TS U2756 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n3395) );
NAND2X1TS U2757 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n3372) );
AOI21X1TS U2758 ( .A0(n2013), .A1(n3377), .B0(n2012), .Y(n3307) );
NAND2X1TS U2759 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n3362) );
NAND2X1TS U2760 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n3345) );
OAI21X1TS U2761 ( .A0(n3344), .A1(n3362), .B0(n3345), .Y(n3310) );
NAND2X1TS U2762 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n3335) );
NAND2X1TS U2763 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n3316) );
AOI21X1TS U2764 ( .A0(n2015), .A1(n3310), .B0(n2014), .Y(n2016) );
NOR2X1TS U2765 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n3524) );
NAND2X1TS U2766 ( .A(n3196), .B(n2021), .Y(n3511) );
NOR2X1TS U2767 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n3558) );
NOR2X1TS U2768 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n3594) );
NAND2X1TS U2769 ( .A(n3585), .B(n2023), .Y(n2025) );
NOR2X1TS U2770 ( .A(n3511), .B(n2025), .Y(n3214) );
NAND2X1TS U2771 ( .A(n3214), .B(n2027), .Y(n2029) );
NAND2X1TS U2772 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n3540) );
NAND2X1TS U2773 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n3536) );
NAND2X1TS U2774 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n3525) );
NAND2X1TS U2775 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n3191) );
AOI21X1TS U2776 ( .A0(n2021), .A1(n3195), .B0(n2020), .Y(n3512) );
NAND2X1TS U2777 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n3557) );
NAND2X1TS U2778 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n3554) );
NAND2X1TS U2779 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n3591) );
NAND2X1TS U2780 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n3595) );
AOI21X1TS U2781 ( .A0(n2023), .A1(n3584), .B0(n2022), .Y(n2024) );
OAI21X1TS U2782 ( .A0(n3512), .A1(n2025), .B0(n2024), .Y(n3213) );
NAND2X1TS U2783 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n3569) );
NAND2X1TS U2784 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n3209) );
AOI21X1TS U2785 ( .A0(n3213), .A1(n2027), .B0(n2026), .Y(n2028) );
CLKBUFX2TS U2786 ( .A(n4013), .Y(n3701) );
CLKBUFX2TS U2787 ( .A(n3863), .Y(n3702) );
AOI22X1TS U2788 ( .A0(n2040), .A1(n3702), .B0(Raw_mant_NRM_SWR[54]), .B1(
n3701), .Y(n2041) );
INVX2TS U2789 ( .A(n2909), .Y(n2903) );
CLKBUFX2TS U2790 ( .A(n4276), .Y(n3951) );
INVX2TS U2791 ( .A(n3951), .Y(n3173) );
INVX2TS U2792 ( .A(n2078), .Y(n3169) );
CLKBUFX2TS U2793 ( .A(n2896), .Y(n3866) );
NOR2X1TS U2794 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(
n2279) );
NAND2X1TS U2795 ( .A(n2274), .B(n2279), .Y(n2072) );
NOR2X1TS U2796 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2273) );
NAND2X1TS U2797 ( .A(n4120), .B(n2273), .Y(n2070) );
NOR2X1TS U2798 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n2272) );
NAND2X1TS U2799 ( .A(n4016), .B(n2272), .Y(n2752) );
NOR2X1TS U2800 ( .A(n2752), .B(Raw_mant_NRM_SWR[47]), .Y(n2043) );
NAND2X1TS U2801 ( .A(n4019), .B(n2101), .Y(n2049) );
NAND2X1TS U2802 ( .A(n2759), .B(n4024), .Y(n2054) );
OR2X1TS U2803 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2057)
);
NOR2XLTS U2804 ( .A(n2774), .B(n4044), .Y(n2060) );
NOR2XLTS U2805 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[42]), .Y(
n2311) );
OAI22X1TS U2806 ( .A0(n2081), .A1(n4074), .B0(n2311), .B1(n2058), .Y(n2059)
);
AOI211XLTS U2807 ( .A0(n2295), .A1(Raw_mant_NRM_SWR[4]), .B0(n2060), .C0(
n2059), .Y(n2763) );
NOR2XLTS U2808 ( .A(n4031), .B(Raw_mant_NRM_SWR[4]), .Y(n2061) );
OAI21XLTS U2809 ( .A0(n2061), .A1(Raw_mant_NRM_SWR[5]), .B0(n4044), .Y(n2066) );
OAI21XLTS U2810 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n4165), .B0(n4020), .Y(
n2064) );
AOI21X1TS U2811 ( .A0(n4030), .A1(Raw_mant_NRM_SWR[39]), .B0(
Raw_mant_NRM_SWR[41]), .Y(n2063) );
OAI22X1TS U2812 ( .A0(n2755), .A1(n4167), .B0(n2098), .B1(n4029), .Y(n2088)
);
NOR2XLTS U2813 ( .A(n2299), .B(n4078), .Y(n2105) );
NOR2BX1TS U2814 ( .AN(n2105), .B(Raw_mant_NRM_SWR[23]), .Y(n2075) );
OAI21XLTS U2815 ( .A0(Raw_mant_NRM_SWR[34]), .A1(Raw_mant_NRM_SWR[32]), .B0(
n2084), .Y(n2071) );
OAI211XLTS U2816 ( .A0(n2073), .A1(n2072), .B0(n2284), .C0(n2071), .Y(n2074)
);
AOI211XLTS U2817 ( .A0(n2076), .A1(Raw_mant_NRM_SWR[14]), .B0(n2075), .C0(
n2074), .Y(n2077) );
CLKBUFX2TS U2818 ( .A(n2912), .Y(n2908) );
INVX2TS U2819 ( .A(n3169), .Y(n2882) );
AOI222XLTS U2820 ( .A0(n3868), .A1(n2079), .B0(n2781), .B1(
Shift_amount_SHT1_EWR[2]), .C0(n2078), .C1(shift_value_SHT2_EWR[2]),
.Y(n2080) );
NOR2XLTS U2821 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n2111)
);
NOR2X1TS U2822 ( .A(n2110), .B(Raw_mant_NRM_SWR[2]), .Y(n2776) );
NAND3X1TS U2823 ( .A(n2776), .B(Raw_mant_NRM_SWR[0]), .C(n4189), .Y(n2091)
);
OAI21XLTS U2824 ( .A0(Raw_mant_NRM_SWR[24]), .A1(Raw_mant_NRM_SWR[23]), .B0(
n2750), .Y(n2087) );
OAI21XLTS U2825 ( .A0(Raw_mant_NRM_SWR[36]), .A1(Raw_mant_NRM_SWR[35]), .B0(
n2082), .Y(n2086) );
AOI21X1TS U2826 ( .A0(n2319), .A1(n2317), .B0(n2089), .Y(n2090) );
NAND2X1TS U2827 ( .A(n2091), .B(n2090), .Y(n2298) );
NAND2X1TS U2828 ( .A(n2316), .B(Raw_mant_NRM_SWR[34]), .Y(n2093) );
OAI211XLTS U2829 ( .A0(n2096), .A1(n2095), .B0(n2094), .C0(n2093), .Y(n2099)
);
NOR2XLTS U2830 ( .A(n2098), .B(n2097), .Y(n2751) );
AOI211XLTS U2831 ( .A0(Raw_mant_NRM_SWR[26]), .A1(n2100), .B0(n2099), .C0(
n2751), .Y(n2104) );
AOI211XLTS U2832 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2107), .B0(n2106), .C0(
n2105), .Y(n2108) );
INVX2TS U2833 ( .A(n2908), .Y(n2905) );
AOI222XLTS U2834 ( .A0(n3867), .A1(n2905), .B0(n2781), .B1(
Shift_amount_SHT1_EWR[4]), .C0(n2882), .C1(shift_value_SHT2_EWR[4]),
.Y(n2112) );
NOR2BX1TS U2835 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2222) );
AOI21X1TS U2836 ( .A0(intDX_EWSW[38]), .A1(n4205), .B0(n2222), .Y(n2221) );
NAND2X1TS U2837 ( .A(n4204), .B(intDX_EWSW[37]), .Y(n2210) );
OA22X1TS U2838 ( .A0(n4151), .A1(intDY_EWSW[42]), .B0(n4022), .B1(
intDY_EWSW[43]), .Y(n2201) );
OAI22X1TS U2839 ( .A0(n4268), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n4095), .Y(n2228) );
NOR2BX1TS U2840 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2116) );
NAND2X1TS U2841 ( .A(n4215), .B(intDX_EWSW[61]), .Y(n2188) );
NOR4XLTS U2842 ( .A(n2182), .B(n2116), .C(n2194), .D(n2186), .Y(n2239) );
AOI211XLTS U2843 ( .A0(intDX_EWSW[48]), .A1(n4192), .B0(n2231), .C0(n2237),
.Y(n2117) );
OA22X1TS U2844 ( .A0(n4152), .A1(intDY_EWSW[34]), .B0(n4023), .B1(
intDY_EWSW[35]), .Y(n2216) );
OAI211XLTS U2845 ( .A0(n4140), .A1(intDY_EWSW[33]), .B0(n2118), .C0(n2216),
.Y(n2119) );
NOR4XLTS U2846 ( .A(n2212), .B(n2245), .C(n2247), .D(n2119), .Y(n2251) );
OA22X1TS U2847 ( .A0(n4163), .A1(intDY_EWSW[30]), .B0(n4025), .B1(
intDY_EWSW[31]), .Y(n2691) );
OAI21XLTS U2848 ( .A0(intDY_EWSW[29]), .A1(n4143), .B0(intDY_EWSW[28]), .Y(
n2120) );
OAI2BB2XLTS U2849 ( .B0(intDX_EWSW[28]), .B1(n2120), .A0N(intDY_EWSW[29]),
.A1N(n4143), .Y(n2129) );
NOR2XLTS U2850 ( .A(intDX_EWSW[24]), .B(n2174), .Y(n2122) );
AOI22X1TS U2851 ( .A0(intDY_EWSW[24]), .A1(n2122), .B0(intDY_EWSW[25]), .B1(
n4154), .Y(n2125) );
AOI32X1TS U2852 ( .A0(n2123), .A1(n4050), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n4161), .Y(n2124) );
OAI32X1TS U2853 ( .A0(n2177), .A1(n2176), .A2(n2125), .B0(n2124), .B1(n2176),
.Y(n2128) );
OAI21XLTS U2854 ( .A0(intDY_EWSW[31]), .A1(n4025), .B0(intDY_EWSW[30]), .Y(
n2126) );
OAI2BB2XLTS U2855 ( .B0(intDX_EWSW[30]), .B1(n2126), .A0N(intDY_EWSW[31]),
.A1N(n4025), .Y(n2127) );
OA22X1TS U2856 ( .A0(n4164), .A1(intDY_EWSW[22]), .B0(n4027), .B1(
intDY_EWSW[23]), .Y(n2699) );
OA22X1TS U2857 ( .A0(n4133), .A1(intDY_EWSW[14]), .B0(n4026), .B1(
intDY_EWSW[15]), .Y(n2707) );
OAI2BB1X1TS U2858 ( .A0N(n4207), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2132) );
OAI22X1TS U2859 ( .A0(intDX_EWSW[4]), .A1(n2132), .B0(n4207), .B1(
intDX_EWSW[5]), .Y(n2142) );
OAI2BB1X1TS U2860 ( .A0N(n4219), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2133) );
OAI22X1TS U2861 ( .A0(intDX_EWSW[6]), .A1(n2133), .B0(n4219), .B1(
intDX_EWSW[7]), .Y(n2141) );
NAND2BXLTS U2862 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2136) );
OAI21XLTS U2863 ( .A0(intDX_EWSW[1]), .A1(n4210), .B0(intDX_EWSW[0]), .Y(
n2134) );
AOI2BB2XLTS U2864 ( .B0(intDX_EWSW[1]), .B1(n4210), .A0N(intDY_EWSW[0]),
.A1N(n2134), .Y(n2135) );
OAI21XLTS U2865 ( .A0(intDY_EWSW[3]), .A1(n4131), .B0(intDY_EWSW[2]), .Y(
n2137) );
AOI2BB2XLTS U2866 ( .B0(intDY_EWSW[3]), .B1(n4131), .A0N(intDX_EWSW[2]),
.A1N(n2137), .Y(n2138) );
AOI222XLTS U2867 ( .A0(intDX_EWSW[4]), .A1(n4052), .B0(intDX_EWSW[5]), .B1(
n4207), .C0(n2139), .C1(n2138), .Y(n2140) );
AOI22X1TS U2868 ( .A0(intDX_EWSW[7]), .A1(n4219), .B0(intDX_EWSW[6]), .B1(
n4066), .Y(n2715) );
OAI32X1TS U2869 ( .A0(n2142), .A1(n2141), .A2(n2140), .B0(n2715), .B1(n2141),
.Y(n2158) );
AOI21X1TS U2870 ( .A0(intDX_EWSW[10]), .A1(n4173), .B0(n2144), .Y(n2149) );
OAI2BB2XLTS U2871 ( .B0(intDX_EWSW[12]), .B1(n2143), .A0N(intDY_EWSW[13]),
.A1N(n4144), .Y(n2155) );
AOI22X1TS U2872 ( .A0(intDY_EWSW[10]), .A1(n2145), .B0(intDY_EWSW[11]), .B1(
n4155), .Y(n2151) );
AOI21X1TS U2873 ( .A0(n2148), .A1(n2147), .B0(n2159), .Y(n2150) );
OAI2BB2XLTS U2874 ( .B0(n2151), .B1(n2159), .A0N(n2150), .A1N(n2149), .Y(
n2154) );
OAI2BB2XLTS U2875 ( .B0(intDX_EWSW[14]), .B1(n2152), .A0N(intDY_EWSW[15]),
.A1N(n4026), .Y(n2153) );
OAI31X1TS U2876 ( .A0(n2159), .A1(n2158), .A2(n2157), .B0(n2156), .Y(n2161)
);
AOI211XLTS U2877 ( .A0(intDX_EWSW[16]), .A1(n4193), .B0(n2163), .C0(n2169),
.Y(n2160) );
OAI2BB2XLTS U2878 ( .B0(intDX_EWSW[20]), .B1(n2162), .A0N(intDY_EWSW[21]),
.A1N(n4145), .Y(n2173) );
AOI22X1TS U2879 ( .A0(n2164), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n4156), .Y(n2167) );
AOI32X1TS U2880 ( .A0(n4049), .A1(n2165), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n4162), .Y(n2166) );
OAI32X1TS U2881 ( .A0(n2169), .A1(n2168), .A2(n2167), .B0(n2166), .B1(n2168),
.Y(n2172) );
OAI21XLTS U2882 ( .A0(intDY_EWSW[23]), .A1(n4027), .B0(intDY_EWSW[22]), .Y(
n2170) );
OAI2BB2XLTS U2883 ( .B0(intDX_EWSW[22]), .B1(n2170), .A0N(intDY_EWSW[23]),
.A1N(n4027), .Y(n2171) );
NOR2BX1TS U2884 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2175) );
OR4X2TS U2885 ( .A(n2177), .B(n2176), .C(n2175), .D(n2174), .Y(n2178) );
AOI32X1TS U2886 ( .A0(n2181), .A1(n2180), .A2(n2179), .B0(n2178), .B1(n2181),
.Y(n2250) );
AOI22X1TS U2887 ( .A0(intDY_EWSW[56]), .A1(n2183), .B0(intDY_EWSW[57]), .B1(
n4160), .Y(n2187) );
AOI32X1TS U2888 ( .A0(n2184), .A1(n4035), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n4191), .Y(n2185) );
OA21XLTS U2889 ( .A0(n2187), .A1(n2186), .B0(n2185), .Y(n2193) );
OAI211XLTS U2890 ( .A0(intDX_EWSW[61]), .A1(n4215), .B0(n2190), .C0(n2189),
.Y(n2191) );
OAI2BB2XLTS U2891 ( .B0(n2194), .B1(n2193), .A0N(n2192), .A1N(n2191), .Y(
n2249) );
NOR2BX1TS U2892 ( .AN(n2195), .B(intDX_EWSW[46]), .Y(n2209) );
NOR2XLTS U2893 ( .A(intDX_EWSW[44]), .B(n2196), .Y(n2197) );
AOI22X1TS U2894 ( .A0(intDY_EWSW[44]), .A1(n2197), .B0(intDY_EWSW[45]), .B1(
n4153), .Y(n2206) );
OAI21XLTS U2895 ( .A0(intDY_EWSW[41]), .A1(n4141), .B0(intDY_EWSW[40]), .Y(
n2198) );
OAI2BB2XLTS U2896 ( .B0(intDX_EWSW[40]), .B1(n2198), .A0N(intDY_EWSW[41]),
.A1N(n4141), .Y(n2202) );
OAI21XLTS U2897 ( .A0(intDY_EWSW[43]), .A1(n4022), .B0(intDY_EWSW[42]), .Y(
n2199) );
OAI2BB2XLTS U2898 ( .B0(intDX_EWSW[42]), .B1(n2199), .A0N(intDY_EWSW[43]),
.A1N(n4022), .Y(n2200) );
AOI32X1TS U2899 ( .A0(n2203), .A1(n2202), .A2(n2201), .B0(n2200), .B1(n2203),
.Y(n2204) );
NOR2BX1TS U2900 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2207) );
OAI21XLTS U2901 ( .A0(intDX_EWSW[37]), .A1(n4204), .B0(n2211), .Y(n2220) );
OAI21XLTS U2902 ( .A0(intDY_EWSW[33]), .A1(n4140), .B0(intDY_EWSW[32]), .Y(
n2213) );
OAI2BB2XLTS U2903 ( .B0(intDX_EWSW[32]), .B1(n2213), .A0N(intDY_EWSW[33]),
.A1N(n4140), .Y(n2217) );
OAI2BB2XLTS U2904 ( .B0(intDX_EWSW[34]), .B1(n2214), .A0N(intDY_EWSW[35]),
.A1N(n4023), .Y(n2215) );
AOI32X1TS U2905 ( .A0(n2218), .A1(n2217), .A2(n2216), .B0(n2215), .B1(n2218),
.Y(n2219) );
OAI2BB1X1TS U2906 ( .A0N(n2221), .A1N(n2220), .B0(n2219), .Y(n2226) );
NOR3XLTS U2907 ( .A(n4205), .B(intDX_EWSW[38]), .C(n2222), .Y(n2225) );
NOR2BX1TS U2908 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2224) );
OAI31X1TS U2909 ( .A0(n2226), .A1(n2225), .A2(n2224), .B0(n2223), .Y(n2244)
);
OAI21XLTS U2910 ( .A0(intDY_EWSW[53]), .A1(n4267), .B0(intDY_EWSW[52]), .Y(
n2227) );
NOR2XLTS U2911 ( .A(intDX_EWSW[48]), .B(n2231), .Y(n2232) );
AOI22X1TS U2912 ( .A0(intDY_EWSW[48]), .A1(n2232), .B0(intDY_EWSW[49]), .B1(
n4159), .Y(n2235) );
AOI32X1TS U2913 ( .A0(n2233), .A1(n4047), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n4157), .Y(n2234) );
OAI32X1TS U2914 ( .A0(n2237), .A1(n2236), .A2(n2235), .B0(n2234), .B1(n2236),
.Y(n2241) );
OAI21XLTS U2915 ( .A0(intDY_EWSW[55]), .A1(n4268), .B0(intDY_EWSW[54]), .Y(
n2238) );
OAI2BB2XLTS U2916 ( .B0(intDX_EWSW[54]), .B1(n2238), .A0N(intDY_EWSW[55]),
.A1N(n4268), .Y(n2240) );
OAI31X1TS U2917 ( .A0(n2242), .A1(n2241), .A2(n2240), .B0(n2239), .Y(n2243)
);
OAI221XLTS U2918 ( .A0(n2247), .A1(n2246), .B0(n2245), .B1(n2244), .C0(n2243), .Y(n2248) );
NAND2X1TS U2919 ( .A(n1926), .B(n2252), .Y(n2658) );
CLKBUFX2TS U2920 ( .A(n2658), .Y(n2536) );
CLKBUFX2TS U2921 ( .A(n4065), .Y(n2456) );
CLKBUFX2TS U2922 ( .A(n2456), .Y(n3938) );
CLKBUFX2TS U2923 ( .A(n2425), .Y(n2512) );
CLKBUFX2TS U2924 ( .A(n4065), .Y(n3884) );
AOI22X1TS U2925 ( .A0(intDX_EWSW[49]), .A1(n2512), .B0(DmP_EXP_EWSW[49]),
.B1(n3884), .Y(n2253) );
OAI21XLTS U2926 ( .A0(n4208), .A1(n2536), .B0(n2253), .Y(n1299) );
CLKBUFX2TS U2927 ( .A(n2425), .Y(n3131) );
AOI22X1TS U2928 ( .A0(intDX_EWSW[46]), .A1(n3131), .B0(DmP_EXP_EWSW[46]),
.B1(n3884), .Y(n2254) );
OAI21XLTS U2929 ( .A0(n4057), .A1(n2536), .B0(n2254), .Y(n1305) );
AOI22X1TS U2930 ( .A0(intDX_EWSW[47]), .A1(n3131), .B0(DmP_EXP_EWSW[47]),
.B1(n3884), .Y(n2255) );
OAI21XLTS U2931 ( .A0(n4203), .A1(n2536), .B0(n2255), .Y(n1303) );
CLKBUFX2TS U2932 ( .A(n2658), .Y(n2359) );
CLKBUFX2TS U2933 ( .A(n2425), .Y(n2430) );
CLKBUFX2TS U2934 ( .A(n2430), .Y(n3135) );
AOI22X1TS U2935 ( .A0(DmP_EXP_EWSW[57]), .A1(n3884), .B0(intDX_EWSW[57]),
.B1(n3135), .Y(n2256) );
OAI21XLTS U2936 ( .A0(n4206), .A1(n2359), .B0(n2256), .Y(n1288) );
CLKBUFX2TS U2937 ( .A(n2430), .Y(n2531) );
AOI22X1TS U2938 ( .A0(intDX_EWSW[50]), .A1(n2531), .B0(DmP_EXP_EWSW[50]),
.B1(n3884), .Y(n2257) );
OAI21XLTS U2939 ( .A0(n4059), .A1(n2536), .B0(n2257), .Y(n1297) );
AOI22X1TS U2940 ( .A0(intDX_EWSW[51]), .A1(n2531), .B0(DmP_EXP_EWSW[51]),
.B1(n3884), .Y(n2258) );
OAI21XLTS U2941 ( .A0(n4198), .A1(n2536), .B0(n2258), .Y(n1295) );
CLKBUFX2TS U2942 ( .A(n4065), .Y(n2360) );
AOI22X1TS U2943 ( .A0(intDX_EWSW[31]), .A1(n3135), .B0(DmP_EXP_EWSW[31]),
.B1(n2360), .Y(n2259) );
OAI21XLTS U2944 ( .A0(n4064), .A1(n2359), .B0(n2259), .Y(n1335) );
AOI22X1TS U2945 ( .A0(intDX_EWSW[30]), .A1(n3135), .B0(DmP_EXP_EWSW[30]),
.B1(n2360), .Y(n2260) );
OAI21XLTS U2946 ( .A0(n4218), .A1(n2359), .B0(n2260), .Y(n1337) );
AOI22X1TS U2947 ( .A0(intDX_EWSW[33]), .A1(n2425), .B0(DmP_EXP_EWSW[33]),
.B1(n2360), .Y(n2261) );
OAI21XLTS U2948 ( .A0(n4054), .A1(n2359), .B0(n2261), .Y(n1331) );
AOI22X1TS U2949 ( .A0(intDX_EWSW[35]), .A1(n2430), .B0(DmP_EXP_EWSW[35]),
.B1(n2360), .Y(n2262) );
OAI21XLTS U2950 ( .A0(n4055), .A1(n2359), .B0(n2262), .Y(n1327) );
CLKBUFX2TS U2951 ( .A(n2658), .Y(n3133) );
CLKBUFX2TS U2952 ( .A(n4065), .Y(n3130) );
AOI22X1TS U2953 ( .A0(intDX_EWSW[36]), .A1(n2425), .B0(DmP_EXP_EWSW[36]),
.B1(n3130), .Y(n2263) );
OAI21XLTS U2954 ( .A0(n4196), .A1(n3133), .B0(n2263), .Y(n1325) );
AOI22X1TS U2955 ( .A0(intDX_EWSW[28]), .A1(n2425), .B0(DmP_EXP_EWSW[28]),
.B1(n2360), .Y(n2264) );
OAI21XLTS U2956 ( .A0(n4177), .A1(n2359), .B0(n2264), .Y(n1341) );
AOI22X1TS U2957 ( .A0(intDX_EWSW[29]), .A1(n2425), .B0(DmP_EXP_EWSW[29]),
.B1(n2360), .Y(n2265) );
OAI21XLTS U2958 ( .A0(n4038), .A1(n2359), .B0(n2265), .Y(n1339) );
AOI22X1TS U2959 ( .A0(intDX_EWSW[34]), .A1(n2425), .B0(DmP_EXP_EWSW[34]),
.B1(n3130), .Y(n2266) );
OAI21XLTS U2960 ( .A0(n4199), .A1(n2359), .B0(n2266), .Y(n1329) );
AOI22X1TS U2961 ( .A0(intDX_EWSW[32]), .A1(n2430), .B0(DmP_EXP_EWSW[32]),
.B1(n2360), .Y(n2267) );
OAI21XLTS U2962 ( .A0(n4183), .A1(n2359), .B0(n2267), .Y(n1333) );
CLKBUFX2TS U2963 ( .A(n2512), .Y(n2361) );
AOI22X1TS U2964 ( .A0(intDX_EWSW[39]), .A1(n2361), .B0(DmP_EXP_EWSW[39]),
.B1(n3130), .Y(n2268) );
OAI21XLTS U2965 ( .A0(n4201), .A1(n3133), .B0(n2268), .Y(n1319) );
INVX2TS U2966 ( .A(n2908), .Y(n2856) );
INVX2TS U2967 ( .A(n2910), .Y(n2878) );
OAI22X1TS U2968 ( .A0(n4286), .A1(n2864), .B0(n4018), .B1(n2878), .Y(n2269)
);
AOI21X1TS U2969 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[30]), .B0(n2269), .Y(
n3010) );
OR2X1TS U2970 ( .A(Raw_mant_NRM_SWR[47]), .B(Raw_mant_NRM_SWR[48]), .Y(n2271) );
AOI21X1TS U2971 ( .A0(n2272), .A1(Raw_mant_NRM_SWR[44]), .B0(n2271), .Y(
n2276) );
AOI21X1TS U2972 ( .A0(n2279), .A1(n2278), .B0(n2300), .Y(n2280) );
NOR2XLTS U2973 ( .A(n2287), .B(Raw_mant_NRM_SWR[9]), .Y(n2288) );
AOI21X1TS U2974 ( .A0(n2295), .A1(n2294), .B0(n2293), .Y(n2779) );
OAI22X1TS U2975 ( .A0(n2424), .A1(n2908), .B0(n2903), .B1(n4265), .Y(n2330)
);
INVX2TS U2976 ( .A(n3169), .Y(n2999) );
NAND2X1TS U2977 ( .A(n2776), .B(Raw_mant_NRM_SWR[1]), .Y(n2326) );
AOI21X1TS U2978 ( .A0(n4051), .A1(Raw_mant_NRM_SWR[7]), .B0(
Raw_mant_NRM_SWR[9]), .Y(n2306) );
NAND2X1TS U2979 ( .A(n2302), .B(n2301), .Y(n2303) );
AOI21X1TS U2980 ( .A0(n2304), .A1(Raw_mant_NRM_SWR[23]), .B0(n2303), .Y(
n2305) );
NOR3XLTS U2981 ( .A(n2749), .B(Raw_mant_NRM_SWR[12]), .C(n4190), .Y(n2323)
);
AOI21X1TS U2982 ( .A0(n2308), .A1(n4028), .B0(Raw_mant_NRM_SWR[53]), .Y(
n2310) );
AOI21X1TS U2983 ( .A0(n2316), .A1(Raw_mant_NRM_SWR[35]), .B0(n2315), .Y(
n2320) );
NOR3XLTS U2984 ( .A(n2317), .B(Raw_mant_NRM_SWR[18]), .C(n4032), .Y(n2318)
);
NAND2X1TS U2985 ( .A(n2319), .B(n2318), .Y(n2768) );
NAND2X1TS U2986 ( .A(n2327), .B(n2903), .Y(n3869) );
CLKBUFX2TS U2987 ( .A(n2910), .Y(n2906) );
AOI21X1TS U2988 ( .A0(n2896), .A1(Shift_amount_SHT1_EWR[0]), .B0(n2906), .Y(
n2328) );
INVX2TS U2989 ( .A(n2811), .Y(n2804) );
INVX2TS U2990 ( .A(n2912), .Y(n2895) );
OAI22X1TS U2991 ( .A0(n4298), .A1(n2864), .B0(n4019), .B1(n2878), .Y(n2329)
);
AOI21X1TS U2992 ( .A0(n2895), .A1(Raw_mant_NRM_SWR[29]), .B0(n2329), .Y(
n2817) );
INVX2TS U2993 ( .A(n2817), .Y(n3053) );
INVX2TS U2994 ( .A(n3169), .Y(n3636) );
AOI22X1TS U2995 ( .A0(n2997), .A1(n3053), .B0(n3636), .B1(Data_array_SWR[24]), .Y(n2333) );
NAND2BX1TS U2996 ( .AN(n2882), .B(n2330), .Y(n2805) );
CLKINVX1TS U2997 ( .A(n2805), .Y(n3015) );
CLKBUFX2TS U2998 ( .A(n2910), .Y(n2867) );
INVX2TS U2999 ( .A(n2867), .Y(n2902) );
OAI22X1TS U3000 ( .A0(n4259), .A1(n2864), .B0(n4070), .B1(n2902), .Y(n2331)
);
AOI21X1TS U3001 ( .A0(n2895), .A1(Raw_mant_NRM_SWR[28]), .B0(n2331), .Y(
n3018) );
NAND2X1TS U3002 ( .A(n3015), .B(n2807), .Y(n2332) );
CLKBUFX2TS U3003 ( .A(n3606), .Y(n3629) );
XNOR2X1TS U3004 ( .A(n4252), .B(DMP_SFG[51]), .Y(n2334) );
XNOR2X1TS U3005 ( .A(n2335), .B(n2334), .Y(n2339) );
CLKBUFX2TS U3006 ( .A(n3863), .Y(n3674) );
CLKBUFX2TS U3007 ( .A(n4013), .Y(n3653) );
AOI22X1TS U3008 ( .A0(n2337), .A1(n3674), .B0(Raw_mant_NRM_SWR[53]), .B1(
n3653), .Y(n2338) );
AOI2BB2XLTS U3009 ( .B0(beg_OP), .B1(n4060), .A0N(n4060), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2340) );
CLKBUFX2TS U3010 ( .A(n2658), .Y(n3137) );
CLKBUFX2TS U3011 ( .A(n4065), .Y(n2731) );
AOI22X1TS U3012 ( .A0(intDX_EWSW[0]), .A1(n2430), .B0(DmP_EXP_EWSW[0]), .B1(
n2731), .Y(n2341) );
OAI21XLTS U3013 ( .A0(n4043), .A1(n3137), .B0(n2341), .Y(n1397) );
AOI22X1TS U3014 ( .A0(intDX_EWSW[43]), .A1(n3131), .B0(DmP_EXP_EWSW[43]),
.B1(n3130), .Y(n2342) );
OAI21XLTS U3015 ( .A0(n4056), .A1(n3133), .B0(n2342), .Y(n1311) );
AOI22X1TS U3016 ( .A0(intDX_EWSW[45]), .A1(n3131), .B0(DmP_EXP_EWSW[45]),
.B1(n3130), .Y(n2343) );
OAI21XLTS U3017 ( .A0(n4195), .A1(n3133), .B0(n2343), .Y(n1307) );
AOI22X1TS U3018 ( .A0(intDX_EWSW[42]), .A1(n3131), .B0(DmP_EXP_EWSW[42]),
.B1(n3130), .Y(n2344) );
OAI21XLTS U3019 ( .A0(n4200), .A1(n3133), .B0(n2344), .Y(n1313) );
AOI22X1TS U3020 ( .A0(intDX_EWSW[41]), .A1(n3131), .B0(DmP_EXP_EWSW[41]),
.B1(n3130), .Y(n2345) );
OAI21XLTS U3021 ( .A0(n4058), .A1(n3133), .B0(n2345), .Y(n1315) );
AOI22X1TS U3022 ( .A0(intDX_EWSW[40]), .A1(n3131), .B0(DmP_EXP_EWSW[40]),
.B1(n3130), .Y(n2346) );
OAI21XLTS U3023 ( .A0(n4202), .A1(n3133), .B0(n2346), .Y(n1317) );
CLKBUFX2TS U3024 ( .A(n2658), .Y(n2534) );
CLKBUFX2TS U3025 ( .A(n2534), .Y(n2533) );
CLKBUFX2TS U3026 ( .A(n4065), .Y(n2511) );
AOI22X1TS U3027 ( .A0(intDX_EWSW[15]), .A1(n2430), .B0(DmP_EXP_EWSW[15]),
.B1(n2511), .Y(n2347) );
OAI21XLTS U3028 ( .A0(n4062), .A1(n2533), .B0(n2347), .Y(n1367) );
CLKBUFX2TS U3029 ( .A(n2658), .Y(n2363) );
AOI22X1TS U3030 ( .A0(intDX_EWSW[17]), .A1(n3135), .B0(DmP_EXP_EWSW[17]),
.B1(n2511), .Y(n2348) );
OAI21XLTS U3031 ( .A0(n4039), .A1(n2363), .B0(n2348), .Y(n1363) );
AOI22X1TS U3032 ( .A0(intDX_EWSW[14]), .A1(n2531), .B0(DmP_EXP_EWSW[14]),
.B1(n2511), .Y(n2349) );
OAI21XLTS U3033 ( .A0(n4216), .A1(n2533), .B0(n2349), .Y(n1369) );
AOI22X1TS U3034 ( .A0(intDX_EWSW[18]), .A1(n2531), .B0(DmP_EXP_EWSW[18]),
.B1(n2511), .Y(n2350) );
OAI21XLTS U3035 ( .A0(n4179), .A1(n2363), .B0(n2350), .Y(n1361) );
AOI22X1TS U3036 ( .A0(intDX_EWSW[23]), .A1(n2361), .B0(DmP_EXP_EWSW[23]),
.B1(n2731), .Y(n2351) );
OAI21XLTS U3037 ( .A0(n4063), .A1(n2363), .B0(n2351), .Y(n1351) );
AOI22X1TS U3038 ( .A0(intDX_EWSW[22]), .A1(n2361), .B0(DmP_EXP_EWSW[22]),
.B1(n2511), .Y(n2352) );
OAI21XLTS U3039 ( .A0(n4217), .A1(n2363), .B0(n2352), .Y(n1353) );
AOI22X1TS U3040 ( .A0(intDX_EWSW[26]), .A1(n2361), .B0(DmP_EXP_EWSW[26]),
.B1(n2360), .Y(n2353) );
OAI21XLTS U3041 ( .A0(n4180), .A1(n2363), .B0(n2353), .Y(n1345) );
AOI22X1TS U3042 ( .A0(intDX_EWSW[25]), .A1(n2361), .B0(DmP_EXP_EWSW[25]),
.B1(n2511), .Y(n2354) );
OAI21XLTS U3043 ( .A0(n4040), .A1(n2363), .B0(n2354), .Y(n1347) );
AOI22X1TS U3044 ( .A0(intDX_EWSW[20]), .A1(n2361), .B0(DmP_EXP_EWSW[20]),
.B1(n2511), .Y(n2355) );
OAI21XLTS U3045 ( .A0(n4176), .A1(n2363), .B0(n2355), .Y(n1357) );
AOI22X1TS U3046 ( .A0(intDX_EWSW[21]), .A1(n2361), .B0(DmP_EXP_EWSW[21]),
.B1(n2511), .Y(n2356) );
OAI21XLTS U3047 ( .A0(n4172), .A1(n2363), .B0(n2356), .Y(n1355) );
AOI22X1TS U3048 ( .A0(intDX_EWSW[19]), .A1(n2361), .B0(DmP_EXP_EWSW[19]),
.B1(n2511), .Y(n2357) );
OAI21XLTS U3049 ( .A0(n4041), .A1(n2363), .B0(n2357), .Y(n1359) );
AOI22X1TS U3050 ( .A0(intDX_EWSW[27]), .A1(n2361), .B0(DmP_EXP_EWSW[27]),
.B1(n2360), .Y(n2358) );
OAI21XLTS U3051 ( .A0(n4042), .A1(n2359), .B0(n2358), .Y(n1343) );
AOI22X1TS U3052 ( .A0(intDX_EWSW[24]), .A1(n2361), .B0(DmP_EXP_EWSW[24]),
.B1(n2360), .Y(n2362) );
OAI21XLTS U3053 ( .A0(n4181), .A1(n2363), .B0(n2362), .Y(n1349) );
INVX2TS U3054 ( .A(n2534), .Y(n3162) );
AOI222XLTS U3055 ( .A0(n3162), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n3938), .C0(intDY_EWSW[52]), .C1(n3135), .Y(n2364) );
AOI222XLTS U3056 ( .A0(n3135), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n3938), .C0(intDY_EWSW[52]), .C1(n3162), .Y(n2365) );
CLKBUFX2TS U3057 ( .A(n4065), .Y(n3134) );
AOI22X1TS U3058 ( .A0(intDX_EWSW[6]), .A1(n2425), .B0(DmP_EXP_EWSW[6]), .B1(
n3134), .Y(n2366) );
OAI21XLTS U3059 ( .A0(n4066), .A1(n3137), .B0(n2366), .Y(n1385) );
NAND2X1TS U3060 ( .A(shift_value_SHT2_EWR[4]), .B(n4187), .Y(n3777) );
INVX2TS U3061 ( .A(n3739), .Y(n3723) );
NAND2X1TS U3062 ( .A(n4021), .B(shift_value_SHT2_EWR[3]), .Y(n3727) );
OAI22X1TS U3063 ( .A0(n4083), .A1(n3723), .B0(n4239), .B1(n3727), .Y(n2368)
);
NAND2X1TS U3064 ( .A(n4021), .B(n4136), .Y(n3724) );
NAND2X1TS U3065 ( .A(n4136), .B(shift_value_SHT2_EWR[2]), .Y(n2598) );
OAI22X1TS U3066 ( .A0(n1905), .A1(n4082), .B0(n4236), .B1(n2598), .Y(n2367)
);
INVX2TS U3067 ( .A(n3838), .Y(n2369) );
NAND2X1TS U3068 ( .A(shift_value_SHT2_EWR[5]), .B(bit_shift_SHT2), .Y(n2746)
);
CLKBUFX2TS U3069 ( .A(n2370), .Y(n3809) );
CLKBUFX2TS U3070 ( .A(n1904), .Y(n3710) );
AOI22X1TS U3071 ( .A0(Data_array_SWR[24]), .A1(n3710), .B0(
Data_array_SWR[36]), .B1(n1933), .Y(n2372) );
INVX2TS U3072 ( .A(n3727), .Y(n2742) );
INVX2TS U3073 ( .A(n2598), .Y(n2392) );
CLKBUFX2TS U3074 ( .A(n2392), .Y(n3726) );
AOI22X1TS U3075 ( .A0(Data_array_SWR[32]), .A1(n2742), .B0(
Data_array_SWR[28]), .B1(n3726), .Y(n2371) );
NAND2X1TS U3076 ( .A(n2372), .B(n2371), .Y(n2612) );
CLKBUFX2TS U3077 ( .A(n3843), .Y(n3720) );
INVX2TS U3078 ( .A(n3720), .Y(n3858) );
CLKBUFX2TS U3079 ( .A(n3979), .Y(n3886) );
INVX2TS U3080 ( .A(n3963), .Y(n3970) );
INVX2TS U3081 ( .A(n3970), .Y(n2642) );
NOR2BX1TS U3082 ( .AN(n3858), .B(n2642), .Y(n2375) );
INVX2TS U3083 ( .A(n3970), .Y(n2649) );
CLKBUFX2TS U3084 ( .A(n2392), .Y(n3734) );
AOI22X1TS U3085 ( .A0(Data_array_SWR[38]), .A1(n2742), .B0(
Data_array_SWR[34]), .B1(n3734), .Y(n2377) );
CLKBUFX2TS U3086 ( .A(n1904), .Y(n3740) );
AOI22X1TS U3087 ( .A0(Data_array_SWR[30]), .A1(n3740), .B0(
Data_array_SWR[42]), .B1(n1933), .Y(n2376) );
NAND2X1TS U3088 ( .A(n2377), .B(n2376), .Y(n3763) );
CLKBUFX2TS U3089 ( .A(n1906), .Y(n3797) );
CLKBUFX2TS U3090 ( .A(n2742), .Y(n3733) );
AOI22X1TS U3091 ( .A0(Data_array_SWR[54]), .A1(n3733), .B0(
Data_array_SWR[50]), .B1(n3726), .Y(n2379) );
CLKBUFX2TS U3092 ( .A(n1904), .Y(n3138) );
AOI21X1TS U3093 ( .A0(Data_array_SWR[46]), .A1(n3138), .B0(n2625), .Y(n2378)
);
NAND2X1TS U3094 ( .A(n2379), .B(n2378), .Y(n3762) );
AOI22X1TS U3095 ( .A0(n1902), .A1(n3763), .B0(n3797), .B1(n3762), .Y(n2380)
);
NAND2X1TS U3096 ( .A(n2380), .B(n1901), .Y(n2957) );
INVX2TS U3097 ( .A(n3963), .Y(n3175) );
INVX2TS U3098 ( .A(n3175), .Y(n3969) );
AOI222XLTS U3099 ( .A0(n2787), .A1(n1920), .B0(n1930), .B1(n2957), .C0(n3969), .C1(DmP_mant_SFG_SWR[30]), .Y(n2381) );
INVX2TS U3100 ( .A(n2381), .Y(n1125) );
OAI22X1TS U3101 ( .A0(n4240), .A1(n3723), .B0(n4072), .B1(n3727), .Y(n2383)
);
OAI22X1TS U3102 ( .A0(n1905), .A1(n4231), .B0(n4071), .B1(n2598), .Y(n2382)
);
INVX2TS U3103 ( .A(n3835), .Y(n2384) );
AOI22X1TS U3104 ( .A0(Data_array_SWR[35]), .A1(n1932), .B0(
Data_array_SWR[23]), .B1(n3710), .Y(n2386) );
AOI22X1TS U3105 ( .A0(Data_array_SWR[27]), .A1(n3734), .B0(
Data_array_SWR[31]), .B1(n3733), .Y(n2385) );
NAND2X1TS U3106 ( .A(n2386), .B(n2385), .Y(n2606) );
NAND2X1TS U3107 ( .A(n3809), .B(n2606), .Y(n2387) );
AOI22X1TS U3108 ( .A0(Data_array_SWR[39]), .A1(n2742), .B0(
Data_array_SWR[35]), .B1(n3734), .Y(n2390) );
AOI22X1TS U3109 ( .A0(Data_array_SWR[43]), .A1(n1932), .B0(
Data_array_SWR[31]), .B1(n3710), .Y(n2389) );
NAND2X1TS U3110 ( .A(n2390), .B(n2389), .Y(n3770) );
NAND2X1TS U3111 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n3146)
);
INVX2TS U3112 ( .A(n3146), .Y(n2391) );
AOI21X1TS U3113 ( .A0(Data_array_SWR[47]), .A1(n3138), .B0(n2391), .Y(n2394)
);
CLKBUFX2TS U3114 ( .A(n2392), .Y(n3738) );
NAND2X1TS U3115 ( .A(Data_array_SWR[51]), .B(n3738), .Y(n2393) );
NAND2X1TS U3116 ( .A(n2394), .B(n2393), .Y(n3769) );
AOI22X1TS U3117 ( .A0(n1902), .A1(n3770), .B0(n3797), .B1(n3769), .Y(n2395)
);
NAND2X1TS U3118 ( .A(n2395), .B(n1901), .Y(n2942) );
AOI222XLTS U3119 ( .A0(n2796), .A1(n1920), .B0(n1929), .B1(n2942), .C0(n3969), .C1(DmP_mant_SFG_SWR[31]), .Y(n2396) );
INVX2TS U3120 ( .A(n2396), .Y(n1124) );
OAI22X1TS U3121 ( .A0(n4243), .A1(n3723), .B0(n4084), .B1(n3727), .Y(n2398)
);
OAI22X1TS U3122 ( .A0(n1905), .A1(n4237), .B0(n4080), .B1(n2598), .Y(n2397)
);
INVX2TS U3123 ( .A(n3846), .Y(n2399) );
AOI22X1TS U3124 ( .A0(Data_array_SWR[26]), .A1(n3740), .B0(
Data_array_SWR[38]), .B1(n1932), .Y(n2401) );
AOI22X1TS U3125 ( .A0(Data_array_SWR[30]), .A1(n3734), .B0(
Data_array_SWR[34]), .B1(n3733), .Y(n2400) );
NAND2X1TS U3126 ( .A(n2401), .B(n2400), .Y(n2636) );
AOI22X1TS U3127 ( .A0(Data_array_SWR[36]), .A1(n2742), .B0(
Data_array_SWR[32]), .B1(n3734), .Y(n2405) );
AOI22X1TS U3128 ( .A0(Data_array_SWR[40]), .A1(n1933), .B0(
Data_array_SWR[28]), .B1(n3710), .Y(n2404) );
NAND2X1TS U3129 ( .A(n2405), .B(n2404), .Y(n3751) );
AOI22X1TS U3130 ( .A0(Data_array_SWR[52]), .A1(n2742), .B0(
Data_array_SWR[48]), .B1(n3726), .Y(n2407) );
AOI21X1TS U3131 ( .A0(Data_array_SWR[44]), .A1(n3138), .B0(n2625), .Y(n2406)
);
NAND2X1TS U3132 ( .A(n2407), .B(n2406), .Y(n3750) );
AOI22X1TS U3133 ( .A0(n3809), .A1(n3751), .B0(n3797), .B1(n3750), .Y(n2408)
);
NAND2X1TS U3134 ( .A(n2408), .B(n1901), .Y(n2951) );
INVX2TS U3135 ( .A(n3175), .Y(n3171) );
AOI222XLTS U3136 ( .A0(n2792), .A1(n2375), .B0(n1930), .B1(n2951), .C0(n3171), .C1(DmP_mant_SFG_SWR[28]), .Y(n2409) );
INVX2TS U3137 ( .A(n2409), .Y(n1127) );
AOI222XLTS U3138 ( .A0(n2787), .A1(n1929), .B0(n1920), .B1(n2957), .C0(n3969), .C1(DmP_mant_SFG_SWR[24]), .Y(n2410) );
INVX2TS U3139 ( .A(n2410), .Y(n1131) );
AOI222XLTS U3140 ( .A0(n2796), .A1(n1930), .B0(n2942), .B1(n1920), .C0(n3171), .C1(DmP_mant_SFG_SWR[23]), .Y(n2411) );
INVX2TS U3141 ( .A(n2411), .Y(n1132) );
AOI222XLTS U3142 ( .A0(n2792), .A1(n1929), .B0(n2951), .B1(n1920), .C0(n3969), .C1(DmP_mant_SFG_SWR[26]), .Y(n2412) );
INVX2TS U3143 ( .A(n2412), .Y(n1129) );
AOI22X1TS U3144 ( .A0(intDX_EWSW[3]), .A1(n2430), .B0(DmP_EXP_EWSW[3]), .B1(
n2731), .Y(n2413) );
OAI21XLTS U3145 ( .A0(n4037), .A1(n3137), .B0(n2413), .Y(n1391) );
AOI22X1TS U3146 ( .A0(intDX_EWSW[2]), .A1(n2430), .B0(DmP_EXP_EWSW[2]), .B1(
n2731), .Y(n2414) );
OAI21XLTS U3147 ( .A0(n4182), .A1(n3137), .B0(n2414), .Y(n1393) );
AOI22X1TS U3148 ( .A0(intDX_EWSW[12]), .A1(n2512), .B0(DmP_EXP_EWSW[12]),
.B1(n3134), .Y(n2415) );
OAI21XLTS U3149 ( .A0(n4175), .A1(n2533), .B0(n2415), .Y(n1373) );
INVX2TS U3150 ( .A(n2512), .Y(n2521) );
CLKBUFX2TS U3151 ( .A(n4065), .Y(n2518) );
AOI22X1TS U3152 ( .A0(intDX_EWSW[30]), .A1(n2519), .B0(DMP_EXP_EWSW[30]),
.B1(n2518), .Y(n2416) );
OAI21XLTS U3153 ( .A0(n4218), .A1(n2521), .B0(n2416), .Y(n1644) );
AOI22X1TS U3154 ( .A0(intDX_EWSW[31]), .A1(n2519), .B0(DMP_EXP_EWSW[31]),
.B1(n2518), .Y(n2417) );
OAI21XLTS U3155 ( .A0(n4064), .A1(n2521), .B0(n2417), .Y(n1643) );
AOI22X1TS U3156 ( .A0(intDX_EWSW[8]), .A1(n2531), .B0(DmP_EXP_EWSW[8]), .B1(
n3134), .Y(n2418) );
OAI21XLTS U3157 ( .A0(n4178), .A1(n2533), .B0(n2418), .Y(n1381) );
INVX2TS U3158 ( .A(n2531), .Y(n2544) );
INVX2TS U3159 ( .A(n2534), .Y(n2542) );
AOI22X1TS U3160 ( .A0(intDX_EWSW[14]), .A1(n2542), .B0(DMP_EXP_EWSW[14]),
.B1(n3161), .Y(n2419) );
OAI21XLTS U3161 ( .A0(n4216), .A1(n2544), .B0(n2419), .Y(n1660) );
INVX2TS U3162 ( .A(n2531), .Y(n2467) );
INVX2TS U3163 ( .A(n2534), .Y(n2465) );
AOI22X1TS U3164 ( .A0(intDX_EWSW[23]), .A1(n2465), .B0(DMP_EXP_EWSW[23]),
.B1(n2518), .Y(n2420) );
OAI21XLTS U3165 ( .A0(n4063), .A1(n2467), .B0(n2420), .Y(n1651) );
CLKBUFX2TS U3166 ( .A(n2456), .Y(n2541) );
AOI22X1TS U3167 ( .A0(intDX_EWSW[15]), .A1(n2542), .B0(DMP_EXP_EWSW[15]),
.B1(n2541), .Y(n2421) );
OAI21XLTS U3168 ( .A0(n4062), .A1(n2544), .B0(n2421), .Y(n1659) );
AOI22X1TS U3169 ( .A0(intDX_EWSW[22]), .A1(n2465), .B0(DMP_EXP_EWSW[22]),
.B1(n2518), .Y(n2422) );
OAI21XLTS U3170 ( .A0(n4217), .A1(n2467), .B0(n2422), .Y(n1652) );
OAI21XLTS U3171 ( .A0(n2424), .A1(n3866), .B0(n2423), .Y(n1211) );
CLKBUFX2TS U3172 ( .A(n4276), .Y(n3968) );
INVX2TS U3173 ( .A(n3968), .Y(busy) );
AOI22X1TS U3174 ( .A0(intDX_EWSW[4]), .A1(n2425), .B0(DmP_EXP_EWSW[4]), .B1(
n3134), .Y(n2426) );
OAI21XLTS U3175 ( .A0(n4052), .A1(n3137), .B0(n2426), .Y(n1389) );
AOI22X1TS U3176 ( .A0(intDX_EWSW[1]), .A1(n2430), .B0(DmP_EXP_EWSW[1]), .B1(
n2731), .Y(n2427) );
OAI21XLTS U3177 ( .A0(n4210), .A1(n3137), .B0(n2427), .Y(n1395) );
AOI22X1TS U3178 ( .A0(intDX_EWSW[48]), .A1(n2512), .B0(DmP_EXP_EWSW[48]),
.B1(n3884), .Y(n2428) );
OAI21XLTS U3179 ( .A0(n4192), .A1(n2536), .B0(n2428), .Y(n1301) );
AOI22X1TS U3180 ( .A0(intDX_EWSW[13]), .A1(n2512), .B0(DmP_EXP_EWSW[13]),
.B1(n3134), .Y(n2429) );
OAI21XLTS U3181 ( .A0(n4171), .A1(n2533), .B0(n2429), .Y(n1371) );
AOI22X1TS U3182 ( .A0(intDX_EWSW[9]), .A1(n2430), .B0(DmP_EXP_EWSW[9]), .B1(
n3134), .Y(n2431) );
OAI21XLTS U3183 ( .A0(n4174), .A1(n2533), .B0(n2431), .Y(n1379) );
CLKBUFX2TS U3184 ( .A(n4065), .Y(n2527) );
AOI22X1TS U3185 ( .A0(intDX_EWSW[32]), .A1(n2519), .B0(DMP_EXP_EWSW[32]),
.B1(n2527), .Y(n2432) );
OAI21XLTS U3186 ( .A0(n4183), .A1(n2521), .B0(n2432), .Y(n1642) );
AOI22X1TS U3187 ( .A0(intDX_EWSW[35]), .A1(n2519), .B0(DMP_EXP_EWSW[35]),
.B1(n2527), .Y(n2433) );
OAI21XLTS U3188 ( .A0(n4055), .A1(n2521), .B0(n2433), .Y(n1639) );
AOI22X1TS U3189 ( .A0(intDX_EWSW[33]), .A1(n2519), .B0(DMP_EXP_EWSW[33]),
.B1(n2527), .Y(n2434) );
OAI21XLTS U3190 ( .A0(n4054), .A1(n2521), .B0(n2434), .Y(n1641) );
INVX2TS U3191 ( .A(n2512), .Y(n2530) );
INVX2TS U3192 ( .A(n2534), .Y(n2528) );
AOI22X1TS U3193 ( .A0(intDX_EWSW[39]), .A1(n2528), .B0(DMP_EXP_EWSW[39]),
.B1(n2527), .Y(n2435) );
OAI21XLTS U3194 ( .A0(n4201), .A1(n2530), .B0(n2435), .Y(n1635) );
AOI22X1TS U3195 ( .A0(intDX_EWSW[41]), .A1(n2528), .B0(DMP_EXP_EWSW[41]),
.B1(n2527), .Y(n2436) );
OAI21XLTS U3196 ( .A0(n4058), .A1(n2530), .B0(n2436), .Y(n1633) );
CLKBUFX2TS U3197 ( .A(n4065), .Y(n2652) );
AOI22X1TS U3198 ( .A0(intDX_EWSW[42]), .A1(n2528), .B0(DMP_EXP_EWSW[42]),
.B1(n2652), .Y(n2437) );
OAI21XLTS U3199 ( .A0(n4200), .A1(n2530), .B0(n2437), .Y(n1632) );
AOI22X1TS U3200 ( .A0(intDX_EWSW[43]), .A1(n2528), .B0(DMP_EXP_EWSW[43]),
.B1(n2652), .Y(n2438) );
OAI21XLTS U3201 ( .A0(n4056), .A1(n2530), .B0(n2438), .Y(n1631) );
AOI22X1TS U3202 ( .A0(intDX_EWSW[45]), .A1(n2528), .B0(DMP_EXP_EWSW[45]),
.B1(n2652), .Y(n2439) );
OAI21XLTS U3203 ( .A0(n4195), .A1(n2530), .B0(n2439), .Y(n1629) );
AOI22X1TS U3204 ( .A0(intDX_EWSW[28]), .A1(n2519), .B0(DMP_EXP_EWSW[28]),
.B1(n2518), .Y(n2440) );
OAI21XLTS U3205 ( .A0(n4177), .A1(n2521), .B0(n2440), .Y(n1646) );
AOI22X1TS U3206 ( .A0(intDX_EWSW[46]), .A1(n2528), .B0(DMP_EXP_EWSW[46]),
.B1(n2652), .Y(n2441) );
OAI21XLTS U3207 ( .A0(n4057), .A1(n2530), .B0(n2441), .Y(n1628) );
INVX2TS U3208 ( .A(n2512), .Y(n2655) );
INVX2TS U3209 ( .A(n2534), .Y(n2656) );
AOI22X1TS U3210 ( .A0(intDX_EWSW[47]), .A1(n2656), .B0(DMP_EXP_EWSW[47]),
.B1(n2652), .Y(n2442) );
OAI21XLTS U3211 ( .A0(n4203), .A1(n2655), .B0(n2442), .Y(n1627) );
AOI22X1TS U3212 ( .A0(intDX_EWSW[49]), .A1(n2656), .B0(DMP_EXP_EWSW[49]),
.B1(n2652), .Y(n2443) );
OAI21XLTS U3213 ( .A0(n4208), .A1(n2655), .B0(n2443), .Y(n1625) );
AOI22X1TS U3214 ( .A0(intDX_EWSW[50]), .A1(n2656), .B0(DMP_EXP_EWSW[50]),
.B1(n2652), .Y(n2444) );
OAI21XLTS U3215 ( .A0(n4059), .A1(n2521), .B0(n2444), .Y(n1624) );
AOI22X1TS U3216 ( .A0(intDX_EWSW[51]), .A1(n2656), .B0(DMP_EXP_EWSW[51]),
.B1(n2652), .Y(n2445) );
OAI21XLTS U3217 ( .A0(n4198), .A1(n2655), .B0(n2445), .Y(n1623) );
AOI22X1TS U3218 ( .A0(DMP_EXP_EWSW[57]), .A1(n3884), .B0(intDX_EWSW[57]),
.B1(n3162), .Y(n2446) );
OAI21XLTS U3219 ( .A0(n4206), .A1(n2655), .B0(n2446), .Y(n1617) );
AOI22X1TS U3220 ( .A0(intDX_EWSW[11]), .A1(n2531), .B0(DmP_EXP_EWSW[11]),
.B1(n3134), .Y(n2447) );
OAI21XLTS U3221 ( .A0(n4061), .A1(n2533), .B0(n2447), .Y(n1375) );
INVX2TS U3222 ( .A(n2531), .Y(n3164) );
AOI22X1TS U3223 ( .A0(intDX_EWSW[3]), .A1(n3162), .B0(DMP_EXP_EWSW[3]), .B1(
n3161), .Y(n2448) );
OAI21XLTS U3224 ( .A0(n4037), .A1(n3164), .B0(n2448), .Y(n1671) );
AOI22X1TS U3225 ( .A0(intDX_EWSW[2]), .A1(n3162), .B0(DMP_EXP_EWSW[2]), .B1(
n3161), .Y(n2449) );
OAI21XLTS U3226 ( .A0(n4182), .A1(n3164), .B0(n2449), .Y(n1672) );
AOI22X1TS U3227 ( .A0(intDX_EWSW[6]), .A1(n3162), .B0(DMP_EXP_EWSW[6]), .B1(
n3161), .Y(n2450) );
OAI21XLTS U3228 ( .A0(n4066), .A1(n3164), .B0(n2450), .Y(n1668) );
AOI22X1TS U3229 ( .A0(intDX_EWSW[26]), .A1(n2465), .B0(DMP_EXP_EWSW[26]),
.B1(n2518), .Y(n2451) );
OAI21XLTS U3230 ( .A0(n4180), .A1(n2467), .B0(n2451), .Y(n1648) );
AOI22X1TS U3231 ( .A0(intDX_EWSW[17]), .A1(n2542), .B0(DMP_EXP_EWSW[17]),
.B1(n2541), .Y(n2452) );
OAI21XLTS U3232 ( .A0(n4039), .A1(n2544), .B0(n2452), .Y(n1657) );
AOI22X1TS U3233 ( .A0(intDX_EWSW[9]), .A1(n2542), .B0(DMP_EXP_EWSW[9]), .B1(
n3161), .Y(n2453) );
OAI21XLTS U3234 ( .A0(n4174), .A1(n2544), .B0(n2453), .Y(n1665) );
AOI22X1TS U3235 ( .A0(intDX_EWSW[13]), .A1(n2542), .B0(DMP_EXP_EWSW[13]),
.B1(n2541), .Y(n2454) );
OAI21XLTS U3236 ( .A0(n4171), .A1(n2544), .B0(n2454), .Y(n1661) );
AOI22X1TS U3237 ( .A0(intDX_EWSW[11]), .A1(n2542), .B0(DMP_EXP_EWSW[11]),
.B1(n3161), .Y(n2455) );
OAI21XLTS U3238 ( .A0(n4061), .A1(n2544), .B0(n2455), .Y(n1663) );
AOI22X1TS U3239 ( .A0(intDX_EWSW[8]), .A1(n2542), .B0(DMP_EXP_EWSW[8]), .B1(
n2456), .Y(n2457) );
OAI21XLTS U3240 ( .A0(n4178), .A1(n2544), .B0(n2457), .Y(n1666) );
AOI22X1TS U3241 ( .A0(intDX_EWSW[12]), .A1(n2542), .B0(DMP_EXP_EWSW[12]),
.B1(n2541), .Y(n2458) );
OAI21XLTS U3242 ( .A0(n4175), .A1(n2544), .B0(n2458), .Y(n1662) );
AOI22X1TS U3243 ( .A0(intDX_EWSW[18]), .A1(n2465), .B0(DMP_EXP_EWSW[18]),
.B1(n2541), .Y(n2459) );
OAI21XLTS U3244 ( .A0(n4179), .A1(n2467), .B0(n2459), .Y(n1656) );
AOI22X1TS U3245 ( .A0(intDX_EWSW[21]), .A1(n2465), .B0(DMP_EXP_EWSW[21]),
.B1(n2541), .Y(n2460) );
OAI21XLTS U3246 ( .A0(n4172), .A1(n2467), .B0(n2460), .Y(n1653) );
AOI22X1TS U3247 ( .A0(intDX_EWSW[27]), .A1(n2465), .B0(DMP_EXP_EWSW[27]),
.B1(n2518), .Y(n2461) );
OAI21XLTS U3248 ( .A0(n4042), .A1(n2467), .B0(n2461), .Y(n1647) );
AOI22X1TS U3249 ( .A0(intDX_EWSW[25]), .A1(n2465), .B0(DMP_EXP_EWSW[25]),
.B1(n2518), .Y(n2462) );
OAI21XLTS U3250 ( .A0(n4040), .A1(n2467), .B0(n2462), .Y(n1649) );
AOI22X1TS U3251 ( .A0(intDX_EWSW[24]), .A1(n2465), .B0(DMP_EXP_EWSW[24]),
.B1(n2541), .Y(n2463) );
OAI21XLTS U3252 ( .A0(n4181), .A1(n2467), .B0(n2463), .Y(n1650) );
AOI22X1TS U3253 ( .A0(intDX_EWSW[19]), .A1(n2465), .B0(DMP_EXP_EWSW[19]),
.B1(n2541), .Y(n2464) );
OAI21XLTS U3254 ( .A0(n4041), .A1(n2467), .B0(n2464), .Y(n1655) );
AOI22X1TS U3255 ( .A0(intDX_EWSW[20]), .A1(n2465), .B0(DMP_EXP_EWSW[20]),
.B1(n2541), .Y(n2466) );
OAI21XLTS U3256 ( .A0(n4176), .A1(n2467), .B0(n2466), .Y(n1654) );
INVX2TS U3257 ( .A(rst), .Y(n4386) );
CLKBUFX2TS U3258 ( .A(n4386), .Y(n4384) );
CLKBUFX2TS U3259 ( .A(n4384), .Y(n4376) );
CLKBUFX2TS U3260 ( .A(n4386), .Y(n2468) );
CLKBUFX2TS U3261 ( .A(n2468), .Y(n4341) );
CLKBUFX2TS U3262 ( .A(n4386), .Y(n2469) );
CLKBUFX2TS U3263 ( .A(n2469), .Y(n4327) );
CLKBUFX2TS U3264 ( .A(n2468), .Y(n4342) );
CLKBUFX2TS U3265 ( .A(n2468), .Y(n4343) );
CLKBUFX2TS U3266 ( .A(n2469), .Y(n4326) );
CLKBUFX2TS U3267 ( .A(n2469), .Y(n4325) );
CLKBUFX2TS U3268 ( .A(n2468), .Y(n4344) );
CLKBUFX2TS U3269 ( .A(n4386), .Y(n2472) );
CLKBUFX2TS U3270 ( .A(n2472), .Y(n4324) );
CLKBUFX2TS U3271 ( .A(n2472), .Y(n4323) );
CLKBUFX2TS U3272 ( .A(n2472), .Y(n4322) );
CLKBUFX2TS U3273 ( .A(n2469), .Y(n4333) );
CLKBUFX2TS U3274 ( .A(n2469), .Y(n4331) );
CLKBUFX2TS U3275 ( .A(n2469), .Y(n4334) );
CLKBUFX2TS U3276 ( .A(n2469), .Y(n4330) );
CLKBUFX2TS U3277 ( .A(n2468), .Y(n4335) );
CLKBUFX2TS U3278 ( .A(n4384), .Y(n4381) );
CLKBUFX2TS U3279 ( .A(n2468), .Y(n4336) );
CLKBUFX2TS U3280 ( .A(n4384), .Y(n4380) );
CLKBUFX2TS U3281 ( .A(n2469), .Y(n4329) );
CLKBUFX2TS U3282 ( .A(n2468), .Y(n4337) );
CLKBUFX2TS U3283 ( .A(n4384), .Y(n4379) );
CLKBUFX2TS U3284 ( .A(n2468), .Y(n4338) );
CLKBUFX2TS U3285 ( .A(n4384), .Y(n4378) );
CLKBUFX2TS U3286 ( .A(n2468), .Y(n4339) );
CLKBUFX2TS U3287 ( .A(n2469), .Y(n4328) );
CLKBUFX2TS U3288 ( .A(n4384), .Y(n4377) );
CLKBUFX2TS U3289 ( .A(n2468), .Y(n4340) );
CLKBUFX2TS U3290 ( .A(n2469), .Y(n4332) );
CLKBUFX2TS U3291 ( .A(n4386), .Y(n2474) );
CLKBUFX2TS U3292 ( .A(n2474), .Y(n4313) );
CLKBUFX2TS U3293 ( .A(n2474), .Y(n4312) );
CLKBUFX2TS U3294 ( .A(n2474), .Y(n4311) );
CLKBUFX2TS U3295 ( .A(n2474), .Y(n4310) );
CLKBUFX2TS U3296 ( .A(n2474), .Y(n4309) );
CLKBUFX2TS U3297 ( .A(n4386), .Y(n2470) );
CLKBUFX2TS U3298 ( .A(n2470), .Y(n4346) );
CLKBUFX2TS U3299 ( .A(n2470), .Y(n4345) );
CLKBUFX2TS U3300 ( .A(n2470), .Y(n4347) );
CLKBUFX2TS U3301 ( .A(n2474), .Y(n4308) );
CLKBUFX2TS U3302 ( .A(n2470), .Y(n4348) );
CLKBUFX2TS U3303 ( .A(n2474), .Y(n4307) );
CLKBUFX2TS U3304 ( .A(n2470), .Y(n4349) );
CLKBUFX2TS U3305 ( .A(n2470), .Y(n4350) );
CLKBUFX2TS U3306 ( .A(n4384), .Y(n4382) );
CLKBUFX2TS U3307 ( .A(n2470), .Y(n4352) );
CLKBUFX2TS U3308 ( .A(n2470), .Y(n4351) );
CLKBUFX2TS U3309 ( .A(n2474), .Y(n4305) );
CLKBUFX2TS U3310 ( .A(n2472), .Y(n4320) );
CLKBUFX2TS U3311 ( .A(n4386), .Y(n2471) );
CLKBUFX2TS U3312 ( .A(n2471), .Y(n4373) );
CLKBUFX2TS U3313 ( .A(n4384), .Y(n4375) );
CLKBUFX2TS U3314 ( .A(n2471), .Y(n4374) );
CLKBUFX2TS U3315 ( .A(n2471), .Y(n4372) );
CLKBUFX2TS U3316 ( .A(n2471), .Y(n4371) );
CLKBUFX2TS U3317 ( .A(n2471), .Y(n4370) );
CLKBUFX2TS U3318 ( .A(n2471), .Y(n4369) );
CLKBUFX2TS U3319 ( .A(n2470), .Y(n4353) );
CLKBUFX2TS U3320 ( .A(n2471), .Y(n4368) );
CLKBUFX2TS U3321 ( .A(n2470), .Y(n4354) );
CLKBUFX2TS U3322 ( .A(n2471), .Y(n4367) );
CLKBUFX2TS U3323 ( .A(n2472), .Y(n4321) );
CLKBUFX2TS U3324 ( .A(n2471), .Y(n4366) );
CLKBUFX2TS U3325 ( .A(n2472), .Y(n4319) );
CLKBUFX2TS U3326 ( .A(n4386), .Y(n2473) );
CLKBUFX2TS U3327 ( .A(n2473), .Y(n4359) );
CLKBUFX2TS U3328 ( .A(n2472), .Y(n4318) );
CLKBUFX2TS U3329 ( .A(n2473), .Y(n4355) );
CLKBUFX2TS U3330 ( .A(n4384), .Y(n4383) );
CLKBUFX2TS U3331 ( .A(n2472), .Y(n4317) );
CLKBUFX2TS U3332 ( .A(n2473), .Y(n4360) );
CLKBUFX2TS U3333 ( .A(n2473), .Y(n4363) );
CLKBUFX2TS U3334 ( .A(n2471), .Y(n4365) );
CLKBUFX2TS U3335 ( .A(n2472), .Y(n4316) );
CLKBUFX2TS U3336 ( .A(n2473), .Y(n4361) );
CLKBUFX2TS U3337 ( .A(n2473), .Y(n4364) );
CLKBUFX2TS U3338 ( .A(n2473), .Y(n4362) );
CLKBUFX2TS U3339 ( .A(n2473), .Y(n4358) );
CLKBUFX2TS U3340 ( .A(n2473), .Y(n4356) );
CLKBUFX2TS U3341 ( .A(n2472), .Y(n4315) );
CLKBUFX2TS U3342 ( .A(n2473), .Y(n4357) );
CLKBUFX2TS U3343 ( .A(n2474), .Y(n4314) );
AOI22X1TS U3344 ( .A0(Data_array_SWR[45]), .A1(n1933), .B0(
Data_array_SWR[33]), .B1(n3138), .Y(n2476) );
AOI22X1TS U3345 ( .A0(Data_array_SWR[37]), .A1(n3738), .B0(
Data_array_SWR[41]), .B1(n3733), .Y(n2475) );
NAND2X1TS U3346 ( .A(n2476), .B(n2475), .Y(n3816) );
AOI22X1TS U3347 ( .A0(Data_array_SWR[53]), .A1(n3738), .B0(
Data_array_SWR[49]), .B1(n3710), .Y(n2477) );
NAND2X1TS U3348 ( .A(n2477), .B(n3146), .Y(n3851) );
NOR2BX1TS U3349 ( .AN(n3851), .B(n3746), .Y(n2483) );
AOI22X1TS U3350 ( .A0(Data_array_SWR[25]), .A1(n3733), .B0(
Data_array_SWR[21]), .B1(n3734), .Y(n2479) );
AOI22X1TS U3351 ( .A0(Data_array_SWR[17]), .A1(n3740), .B0(
Data_array_SWR[29]), .B1(n1932), .Y(n2478) );
CLKAND2X2TS U3352 ( .A(n2479), .B(n2478), .Y(n2736) );
AOI22X1TS U3353 ( .A0(Data_array_SWR[5]), .A1(n1934), .B0(Data_array_SWR[13]), .B1(n3743), .Y(n2481) );
CLKBUFX2TS U3354 ( .A(n2742), .Y(n3737) );
NAND2X1TS U3355 ( .A(n3809), .B(n3737), .Y(n3795) );
AOI22X1TS U3356 ( .A0(Data_array_SWR[9]), .A1(n1921), .B0(Data_array_SWR[1]),
.B1(n1923), .Y(n2480) );
NOR2BX1TS U3357 ( .AN(n1905), .B(bit_shift_SHT2), .Y(n2484) );
INVX2TS U3358 ( .A(n2484), .Y(n3141) );
NOR2BX1TS U3359 ( .AN(n3138), .B(Data_array_SWR[53]), .Y(n2485) );
INVX2TS U3360 ( .A(n2485), .Y(n2486) );
NAND2X1TS U3361 ( .A(n3141), .B(n2486), .Y(n3790) );
INVX2TS U3362 ( .A(n3142), .Y(n3832) );
AOI22X1TS U3363 ( .A0(n2585), .A1(n2375), .B0(DmP_mant_SFG_SWR[1]), .B1(
n2642), .Y(n2487) );
AOI22X1TS U3364 ( .A0(Data_array_SWR[31]), .A1(n1932), .B0(
Data_array_SWR[19]), .B1(n3138), .Y(n2489) );
AOI22X1TS U3365 ( .A0(Data_array_SWR[27]), .A1(n3737), .B0(
Data_array_SWR[23]), .B1(n3734), .Y(n2488) );
NAND2X1TS U3366 ( .A(n2489), .B(n2488), .Y(n2621) );
OAI21XLTS U3367 ( .A0(Data_array_SWR[51]), .A1(n1905), .B0(n3141), .Y(n2623)
);
AOI22X1TS U3368 ( .A0(Data_array_SWR[15]), .A1(n3743), .B0(Data_array_SWR[7]), .B1(n1934), .Y(n2491) );
AOI22X1TS U3369 ( .A0(Data_array_SWR[11]), .A1(n1921), .B0(Data_array_SWR[3]), .B1(n1923), .Y(n2490) );
OAI22X1TS U3370 ( .A0(n1905), .A1(n4233), .B0(n4072), .B1(n3723), .Y(n2493)
);
OAI22X1TS U3371 ( .A0(n2598), .A1(n4231), .B0(n4071), .B1(n3727), .Y(n2492)
);
INVX2TS U3372 ( .A(n3782), .Y(n3802) );
INVX2TS U3373 ( .A(n1920), .Y(n3159) );
AOI22X1TS U3374 ( .A0(n2591), .A1(n1930), .B0(DmP_mant_SFG_SWR[51]), .B1(
n2649), .Y(n2496) );
AOI22X1TS U3375 ( .A0(n2585), .A1(n1930), .B0(DmP_mant_SFG_SWR[53]), .B1(
n2642), .Y(n2497) );
AOI22X1TS U3376 ( .A0(Data_array_SWR[46]), .A1(n1932), .B0(
Data_array_SWR[34]), .B1(n3138), .Y(n2499) );
AOI22X1TS U3377 ( .A0(Data_array_SWR[38]), .A1(n3738), .B0(
Data_array_SWR[42]), .B1(n3733), .Y(n2498) );
NAND2X1TS U3378 ( .A(n2499), .B(n2498), .Y(n3820) );
AOI22X1TS U3379 ( .A0(Data_array_SWR[54]), .A1(n3738), .B0(
Data_array_SWR[50]), .B1(n3710), .Y(n2500) );
NAND2X1TS U3380 ( .A(n2500), .B(n3146), .Y(n3855) );
NOR2BX1TS U3381 ( .AN(n3855), .B(n3746), .Y(n2506) );
AOI22X1TS U3382 ( .A0(Data_array_SWR[18]), .A1(n3740), .B0(
Data_array_SWR[30]), .B1(n1933), .Y(n2502) );
AOI22X1TS U3383 ( .A0(Data_array_SWR[26]), .A1(n3733), .B0(
Data_array_SWR[22]), .B1(n3726), .Y(n2501) );
CLKAND2X2TS U3384 ( .A(n2502), .B(n2501), .Y(n3784) );
AOI22X1TS U3385 ( .A0(Data_array_SWR[6]), .A1(n1934), .B0(Data_array_SWR[14]), .B1(n1912), .Y(n2504) );
AOI22X1TS U3386 ( .A0(Data_array_SWR[10]), .A1(n1922), .B0(Data_array_SWR[2]), .B1(n1924), .Y(n2503) );
AOI22X1TS U3387 ( .A0(n2588), .A1(n1929), .B0(DmP_mant_SFG_SWR[52]), .B1(
n2642), .Y(n2507) );
AOI22X1TS U3388 ( .A0(n2588), .A1(n2375), .B0(DmP_mant_SFG_SWR[2]), .B1(
n2649), .Y(n2508) );
AOI22X1TS U3389 ( .A0(n2591), .A1(n1920), .B0(DmP_mant_SFG_SWR[3]), .B1(
n2649), .Y(n2509) );
AOI22X1TS U3390 ( .A0(intDX_EWSW[44]), .A1(n3131), .B0(DmP_EXP_EWSW[44]),
.B1(n3884), .Y(n2510) );
OAI21XLTS U3391 ( .A0(n4197), .A1(n3133), .B0(n2510), .Y(n1309) );
AOI22X1TS U3392 ( .A0(intDX_EWSW[16]), .A1(n2512), .B0(DmP_EXP_EWSW[16]),
.B1(n2511), .Y(n2513) );
OAI21XLTS U3393 ( .A0(n4193), .A1(n2533), .B0(n2513), .Y(n1365) );
AOI22X1TS U3394 ( .A0(intDX_EWSW[7]), .A1(n3135), .B0(DmP_EXP_EWSW[7]), .B1(
n3134), .Y(n2514) );
OAI21XLTS U3395 ( .A0(n4219), .A1(n2533), .B0(n2514), .Y(n1383) );
AOI22X1TS U3396 ( .A0(intDX_EWSW[34]), .A1(n2519), .B0(DMP_EXP_EWSW[34]),
.B1(n2518), .Y(n2515) );
OAI21XLTS U3397 ( .A0(n4199), .A1(n2521), .B0(n2515), .Y(n1640) );
AOI22X1TS U3398 ( .A0(intDX_EWSW[0]), .A1(n2519), .B0(DMP_EXP_EWSW[0]), .B1(
n3938), .Y(n2516) );
OAI21XLTS U3399 ( .A0(n4043), .A1(n2655), .B0(n2516), .Y(n1674) );
AOI22X1TS U3400 ( .A0(intDX_EWSW[36]), .A1(n2519), .B0(DMP_EXP_EWSW[36]),
.B1(n2527), .Y(n2517) );
OAI21XLTS U3401 ( .A0(n4196), .A1(n2521), .B0(n2517), .Y(n1638) );
AOI22X1TS U3402 ( .A0(intDX_EWSW[29]), .A1(n2519), .B0(DMP_EXP_EWSW[29]),
.B1(n2518), .Y(n2520) );
OAI21XLTS U3403 ( .A0(n4038), .A1(n2521), .B0(n2520), .Y(n1645) );
AOI22X1TS U3404 ( .A0(intDX_EWSW[40]), .A1(n2528), .B0(DMP_EXP_EWSW[40]),
.B1(n2527), .Y(n2522) );
OAI21XLTS U3405 ( .A0(n4202), .A1(n2530), .B0(n2522), .Y(n1634) );
AOI22X1TS U3406 ( .A0(intDX_EWSW[48]), .A1(n2656), .B0(DMP_EXP_EWSW[48]),
.B1(n2652), .Y(n2523) );
OAI21XLTS U3407 ( .A0(n4192), .A1(n2655), .B0(n2523), .Y(n1626) );
AOI22X1TS U3408 ( .A0(intDX_EWSW[61]), .A1(n2656), .B0(DMP_EXP_EWSW[61]),
.B1(n2731), .Y(n2524) );
OAI21XLTS U3409 ( .A0(n4215), .A1(n2655), .B0(n2524), .Y(n1613) );
AOI22X1TS U3410 ( .A0(intDX_EWSW[44]), .A1(n2528), .B0(DMP_EXP_EWSW[44]),
.B1(n2527), .Y(n2525) );
OAI21XLTS U3411 ( .A0(n4197), .A1(n2530), .B0(n2525), .Y(n1630) );
AOI22X1TS U3412 ( .A0(intDX_EWSW[37]), .A1(n2528), .B0(DMP_EXP_EWSW[37]),
.B1(n2527), .Y(n2526) );
OAI21XLTS U3413 ( .A0(n4204), .A1(n2530), .B0(n2526), .Y(n1637) );
AOI22X1TS U3414 ( .A0(intDX_EWSW[38]), .A1(n2528), .B0(DMP_EXP_EWSW[38]),
.B1(n2527), .Y(n2529) );
OAI21XLTS U3415 ( .A0(n4205), .A1(n2530), .B0(n2529), .Y(n1636) );
AOI22X1TS U3416 ( .A0(intDX_EWSW[10]), .A1(n2531), .B0(DmP_EXP_EWSW[10]),
.B1(n3134), .Y(n2532) );
OAI21XLTS U3417 ( .A0(n4173), .A1(n2533), .B0(n2532), .Y(n1377) );
INVX2TS U3418 ( .A(n3131), .Y(n2734) );
AOI22X1TS U3419 ( .A0(intDX_EWSW[37]), .A1(n2512), .B0(DmP_EXP_EWSW[37]),
.B1(n3130), .Y(n2535) );
OAI21XLTS U3420 ( .A0(n4204), .A1(n3133), .B0(n2535), .Y(n1323) );
AOI22X1TS U3421 ( .A0(intDX_EWSW[4]), .A1(n3162), .B0(DMP_EXP_EWSW[4]), .B1(
n3938), .Y(n2537) );
OAI21XLTS U3422 ( .A0(n4052), .A1(n3164), .B0(n2537), .Y(n1670) );
AOI22X1TS U3423 ( .A0(intDX_EWSW[1]), .A1(n3162), .B0(DMP_EXP_EWSW[1]), .B1(
n3938), .Y(n2538) );
OAI21XLTS U3424 ( .A0(n4210), .A1(n3164), .B0(n2538), .Y(n1673) );
AOI22X1TS U3425 ( .A0(intDX_EWSW[7]), .A1(n3162), .B0(DMP_EXP_EWSW[7]), .B1(
n3161), .Y(n2539) );
OAI21XLTS U3426 ( .A0(n4219), .A1(n3164), .B0(n2539), .Y(n1667) );
AOI22X1TS U3427 ( .A0(intDX_EWSW[10]), .A1(n2542), .B0(DMP_EXP_EWSW[10]),
.B1(n3161), .Y(n2540) );
OAI21XLTS U3428 ( .A0(n4173), .A1(n2544), .B0(n2540), .Y(n1664) );
AOI22X1TS U3429 ( .A0(intDX_EWSW[16]), .A1(n2542), .B0(DMP_EXP_EWSW[16]),
.B1(n2541), .Y(n2543) );
OAI21XLTS U3430 ( .A0(n4193), .A1(n2544), .B0(n2543), .Y(n1658) );
INVX2TS U3431 ( .A(n3720), .Y(n3810) );
NOR2BX1TS U3432 ( .AN(LZD_output_NRM2_EW[5]), .B(ADD_OVRFLW_NRM2), .Y(n2545)
);
NOR2BX1TS U3433 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n2546)
);
NOR2BX1TS U3434 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n2547)
);
NOR2BX1TS U3435 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n2548)
);
NOR2BX1TS U3436 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n2549)
);
CMPR32X2TS U3437 ( .A(n2552), .B(DMP_exp_NRM2_EW[3]), .C(n2551), .CO(n2558),
.S(n3873) );
CMPR32X2TS U3438 ( .A(DMP_exp_NRM2_EW[0]), .B(n1908), .C(n2553), .CO(n2556),
.S(n2576) );
INVX2TS U3439 ( .A(n2576), .Y(n3870) );
CMPR32X2TS U3440 ( .A(n2555), .B(DMP_exp_NRM2_EW[2]), .C(n2554), .CO(n2551),
.S(n2577) );
INVX2TS U3441 ( .A(n2577), .Y(n3872) );
CMPR32X2TS U3442 ( .A(n2557), .B(DMP_exp_NRM2_EW[1]), .C(n2556), .CO(n2554),
.S(n2575) );
INVX2TS U3443 ( .A(n2575), .Y(n3871) );
CMPR32X2TS U3444 ( .A(n2559), .B(DMP_exp_NRM2_EW[4]), .C(n2558), .CO(n2563),
.S(n3874) );
CMPR32X2TS U3445 ( .A(n1908), .B(DMP_exp_NRM2_EW[6]), .C(n2561), .CO(n2566),
.S(n2562) );
INVX2TS U3446 ( .A(n2562), .Y(n3876) );
CMPR32X2TS U3447 ( .A(n2564), .B(DMP_exp_NRM2_EW[5]), .C(n2563), .CO(n2561),
.S(n2579) );
NOR2BX1TS U3448 ( .AN(n2569), .B(n3879), .Y(n2571) );
NOR2BX1TS U3449 ( .AN(n2571), .B(n3880), .Y(n2574) );
XNOR2X1TS U3450 ( .A(n2573), .B(ADD_OVRFLW_NRM2), .Y(n2581) );
CLKBUFX2TS U3451 ( .A(n3979), .Y(n3974) );
AOI22X1TS U3452 ( .A0(n2800), .A1(n2588), .B0(final_result_ieee[50]), .B1(
n3974), .Y(n2583) );
AOI22X1TS U3453 ( .A0(n2800), .A1(n2591), .B0(final_result_ieee[49]), .B1(
n3974), .Y(n2584) );
AOI22X1TS U3454 ( .A0(n2800), .A1(n2585), .B0(final_result_ieee[51]), .B1(
n3886), .Y(n2586) );
AOI22X1TS U3455 ( .A0(n2962), .A1(n2588), .B0(final_result_ieee[0]), .B1(
n3974), .Y(n2589) );
AOI22X1TS U3456 ( .A0(n2962), .A1(n2591), .B0(final_result_ieee[1]), .B1(
n3974), .Y(n2592) );
AOI22X1TS U3457 ( .A0(Data_array_SWR[53]), .A1(n2742), .B0(
Data_array_SWR[49]), .B1(n3726), .Y(n2595) );
AOI21X1TS U3458 ( .A0(Data_array_SWR[45]), .A1(n3138), .B0(n2625), .Y(n2594)
);
NAND2X1TS U3459 ( .A(n2595), .B(n2594), .Y(n3756) );
NAND2X1TS U3460 ( .A(n3832), .B(n1925), .Y(n2635) );
INVX2TS U3461 ( .A(n3768), .Y(n2638) );
NAND2X1TS U3462 ( .A(shift_value_SHT2_EWR[4]), .B(n1900), .Y(n3799) );
OAI22X1TS U3463 ( .A0(n4242), .A1(n3723), .B0(n4085), .B1(n3727), .Y(n2597)
);
OAI22X1TS U3464 ( .A0(n1905), .A1(n4081), .B0(n4235), .B1(n2598), .Y(n2596)
);
OAI22X1TS U3465 ( .A0(n1905), .A1(n4234), .B0(n4067), .B1(n2598), .Y(n2600)
);
OAI22X1TS U3466 ( .A0(n3727), .A1(n4075), .B0(n4232), .B1(n3723), .Y(n2599)
);
OA22X1TS U3467 ( .A0(n3841), .A1(n3802), .B0(n2747), .B1(n1907), .Y(n2601)
);
AOI21X1TS U3468 ( .A0(Data_array_SWR[9]), .A1(n1924), .B0(n2602), .Y(n2604)
);
AOI22X1TS U3469 ( .A0(Data_array_SWR[21]), .A1(n1912), .B0(
Data_array_SWR[17]), .B1(n1921), .Y(n2603) );
NAND2X1TS U3470 ( .A(n2604), .B(n2603), .Y(n2936) );
AOI22X1TS U3471 ( .A0(n2936), .A1(n2375), .B0(DmP_mant_SFG_SWR[45]), .B1(
n2642), .Y(n2605) );
AOI2BB2XLTS U3472 ( .B0(n1906), .B1(n2606), .A0N(n3802), .A1N(n3835), .Y(
n2607) );
AOI21X1TS U3473 ( .A0(Data_array_SWR[7]), .A1(n1924), .B0(n2608), .Y(n2610)
);
AOI22X1TS U3474 ( .A0(Data_array_SWR[11]), .A1(n1934), .B0(
Data_array_SWR[15]), .B1(n1922), .Y(n2609) );
NAND2X1TS U3475 ( .A(n2610), .B(n2609), .Y(n2939) );
AOI22X1TS U3476 ( .A0(n2939), .A1(n2375), .B0(DmP_mant_SFG_SWR[47]), .B1(
n2642), .Y(n2611) );
AOI21X1TS U3477 ( .A0(Data_array_SWR[8]), .A1(n1923), .B0(n2614), .Y(n2616)
);
AOI22X1TS U3478 ( .A0(Data_array_SWR[20]), .A1(n3743), .B0(
Data_array_SWR[16]), .B1(n1922), .Y(n2615) );
NAND2X1TS U3479 ( .A(n2616), .B(n2615), .Y(n2948) );
AOI22X1TS U3480 ( .A0(n2948), .A1(n1920), .B0(DmP_mant_SFG_SWR[46]), .B1(
n2642), .Y(n2617) );
CLKBUFX2TS U3481 ( .A(n1906), .Y(n3806) );
INVX2TS U3482 ( .A(n2623), .Y(n2619) );
AOI21X1TS U3483 ( .A0(n3806), .A1(n2619), .B0(n2618), .Y(n2947) );
AOI22X1TS U3484 ( .A0(n2945), .A1(n1920), .B0(DmP_mant_SFG_SWR[35]), .B1(
n2642), .Y(n2624) );
AOI22X1TS U3485 ( .A0(Data_array_SWR[51]), .A1(n3737), .B0(
Data_array_SWR[47]), .B1(n3726), .Y(n2627) );
AOI21X1TS U3486 ( .A0(Data_array_SWR[43]), .A1(n3138), .B0(n2625), .Y(n2626)
);
NAND2X1TS U3487 ( .A(n2627), .B(n2626), .Y(n3805) );
AOI22X1TS U3488 ( .A0(Data_array_SWR[35]), .A1(n2742), .B0(
Data_array_SWR[31]), .B1(n3726), .Y(n2629) );
AOI22X1TS U3489 ( .A0(Data_array_SWR[27]), .A1(n3740), .B0(
Data_array_SWR[39]), .B1(n1933), .Y(n2628) );
NAND2X1TS U3490 ( .A(n2629), .B(n2628), .Y(n3808) );
AOI22X1TS U3491 ( .A0(n3806), .A1(n3808), .B0(n1936), .B1(n3805), .Y(n2630)
);
AOI21X1TS U3492 ( .A0(Data_array_SWR[11]), .A1(n1923), .B0(n2631), .Y(n2633)
);
AOI22X1TS U3493 ( .A0(Data_array_SWR[23]), .A1(n1912), .B0(
Data_array_SWR[19]), .B1(n1921), .Y(n2632) );
NAND2X1TS U3494 ( .A(n2633), .B(n2632), .Y(n2954) );
AOI22X1TS U3495 ( .A0(n2954), .A1(n1920), .B0(DmP_mant_SFG_SWR[43]), .B1(
n2642), .Y(n2634) );
AOI21X1TS U3496 ( .A0(Data_array_SWR[10]), .A1(n1924), .B0(n2639), .Y(n2641)
);
AOI22X1TS U3497 ( .A0(Data_array_SWR[22]), .A1(n3743), .B0(
Data_array_SWR[18]), .B1(n1922), .Y(n2640) );
NAND2X1TS U3498 ( .A(n2641), .B(n2640), .Y(n2933) );
AOI22X1TS U3499 ( .A0(n2933), .A1(n2375), .B0(DmP_mant_SFG_SWR[44]), .B1(
n2642), .Y(n2643) );
AOI22X1TS U3500 ( .A0(n2948), .A1(n1929), .B0(DmP_mant_SFG_SWR[8]), .B1(
n2649), .Y(n2644) );
AOI22X1TS U3501 ( .A0(n2936), .A1(n1930), .B0(DmP_mant_SFG_SWR[9]), .B1(
n2649), .Y(n2645) );
AOI22X1TS U3502 ( .A0(n2933), .A1(n1929), .B0(DmP_mant_SFG_SWR[10]), .B1(
n2649), .Y(n2646) );
AOI22X1TS U3503 ( .A0(n2939), .A1(n1930), .B0(DmP_mant_SFG_SWR[7]), .B1(
n2649), .Y(n2647) );
AOI22X1TS U3504 ( .A0(n2954), .A1(n1930), .B0(DmP_mant_SFG_SWR[11]), .B1(
n2649), .Y(n2648) );
AOI22X1TS U3505 ( .A0(n2945), .A1(n1929), .B0(DmP_mant_SFG_SWR[19]), .B1(
n2649), .Y(n2650) );
AOI22X1TS U3506 ( .A0(intDX_EWSW[59]), .A1(n2656), .B0(DMP_EXP_EWSW[59]),
.B1(n2731), .Y(n2651) );
AOI22X1TS U3507 ( .A0(intDX_EWSW[58]), .A1(n2656), .B0(DMP_EXP_EWSW[58]),
.B1(n2652), .Y(n2653) );
AOI22X1TS U3508 ( .A0(intDX_EWSW[60]), .A1(n2656), .B0(DMP_EXP_EWSW[60]),
.B1(n2731), .Y(n2654) );
AOI22X1TS U3509 ( .A0(intDX_EWSW[62]), .A1(n2656), .B0(DMP_EXP_EWSW[62]),
.B1(n2731), .Y(n2657) );
AOI22X1TS U3510 ( .A0(n4061), .A1(intDX_EWSW[11]), .B0(n4208), .B1(
intDX_EWSW[49]), .Y(n2659) );
OAI221XLTS U3511 ( .A0(n4061), .A1(intDX_EWSW[11]), .B0(n4208), .B1(
intDX_EWSW[49]), .C0(n2659), .Y(n2660) );
AOI221XLTS U3512 ( .A0(intDY_EWSW[1]), .A1(n4222), .B0(n4210), .B1(
intDX_EWSW[1]), .C0(n2660), .Y(n2674) );
OAI22X1TS U3513 ( .A0(n4220), .A1(intDX_EWSW[52]), .B0(n4053), .B1(
intDX_EWSW[53]), .Y(n2661) );
AOI221XLTS U3514 ( .A0(n4220), .A1(intDX_EWSW[52]), .B0(intDX_EWSW[53]),
.B1(n4053), .C0(n2661), .Y(n2673) );
OAI22X1TS U3515 ( .A0(n4059), .A1(intDX_EWSW[50]), .B0(n4198), .B1(
intDX_EWSW[51]), .Y(n2662) );
AOI221XLTS U3516 ( .A0(n4059), .A1(intDX_EWSW[50]), .B0(intDX_EWSW[51]),
.B1(n4198), .C0(n2662), .Y(n2672) );
AOI22X1TS U3517 ( .A0(n4206), .A1(intDX_EWSW[57]), .B0(n4014), .B1(
intDX_EWSW[56]), .Y(n2663) );
OAI221XLTS U3518 ( .A0(n4206), .A1(intDX_EWSW[57]), .B0(n4014), .B1(
intDX_EWSW[56]), .C0(n2663), .Y(n2670) );
AOI22X1TS U3519 ( .A0(n4012), .A1(intDX_EWSW[55]), .B0(n4036), .B1(
intDX_EWSW[54]), .Y(n2664) );
OAI221XLTS U3520 ( .A0(n4012), .A1(intDX_EWSW[55]), .B0(n4036), .B1(
intDX_EWSW[54]), .C0(n2664), .Y(n2669) );
AOI22X1TS U3521 ( .A0(n4215), .A1(intDX_EWSW[61]), .B0(n4184), .B1(
intDX_EWSW[60]), .Y(n2665) );
OAI221XLTS U3522 ( .A0(n4215), .A1(intDX_EWSW[61]), .B0(n4184), .B1(
intDX_EWSW[60]), .C0(n2665), .Y(n2668) );
AOI22X1TS U3523 ( .A0(n4213), .A1(intDX_EWSW[59]), .B0(n4045), .B1(
intDX_EWSW[58]), .Y(n2666) );
OAI221XLTS U3524 ( .A0(n4213), .A1(intDX_EWSW[59]), .B0(n4045), .B1(
intDX_EWSW[58]), .C0(n2666), .Y(n2667) );
NOR4XLTS U3525 ( .A(n2670), .B(n2669), .C(n2668), .D(n2667), .Y(n2671) );
NAND4XLTS U3526 ( .A(n2674), .B(n2673), .C(n2672), .D(n2671), .Y(n2730) );
OAI22X1TS U3527 ( .A0(n4200), .A1(intDX_EWSW[42]), .B0(n4056), .B1(
intDX_EWSW[43]), .Y(n2675) );
AOI221XLTS U3528 ( .A0(n4200), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n4056), .C0(n2675), .Y(n2682) );
OAI22X1TS U3529 ( .A0(n4202), .A1(intDX_EWSW[40]), .B0(n4058), .B1(
intDX_EWSW[41]), .Y(n2676) );
AOI221XLTS U3530 ( .A0(n4202), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n4058), .C0(n2676), .Y(n2681) );
OAI22X1TS U3531 ( .A0(n4057), .A1(intDX_EWSW[46]), .B0(n4203), .B1(
intDX_EWSW[47]), .Y(n2677) );
AOI221XLTS U3532 ( .A0(n4057), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n4203), .C0(n2677), .Y(n2680) );
OAI22X1TS U3533 ( .A0(n4197), .A1(intDX_EWSW[44]), .B0(n4195), .B1(
intDX_EWSW[45]), .Y(n2678) );
AOI221XLTS U3534 ( .A0(n4197), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n4195), .C0(n2678), .Y(n2679) );
NAND4XLTS U3535 ( .A(n2682), .B(n2681), .C(n2680), .D(n2679), .Y(n2729) );
OAI22X1TS U3536 ( .A0(n4199), .A1(intDX_EWSW[34]), .B0(n4055), .B1(
intDX_EWSW[35]), .Y(n2683) );
AOI221XLTS U3537 ( .A0(n4199), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n4055), .C0(n2683), .Y(n2690) );
OAI22X1TS U3538 ( .A0(n4209), .A1(intDX_EWSW[62]), .B0(n4054), .B1(
intDX_EWSW[33]), .Y(n2684) );
AOI221XLTS U3539 ( .A0(n4209), .A1(intDX_EWSW[62]), .B0(intDX_EWSW[33]),
.B1(n4054), .C0(n2684), .Y(n2689) );
OAI22X1TS U3540 ( .A0(n4205), .A1(intDX_EWSW[38]), .B0(n4201), .B1(
intDX_EWSW[39]), .Y(n2685) );
AOI221XLTS U3541 ( .A0(n4205), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n4201), .C0(n2685), .Y(n2688) );
OAI22X1TS U3542 ( .A0(n4196), .A1(intDX_EWSW[36]), .B0(n4204), .B1(
intDX_EWSW[37]), .Y(n2686) );
AOI221XLTS U3543 ( .A0(n4196), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n4204), .C0(n2686), .Y(n2687) );
NAND4XLTS U3544 ( .A(n2690), .B(n2689), .C(n2688), .D(n2687), .Y(n2728) );
OAI221XLTS U3545 ( .A0(n4064), .A1(intDX_EWSW[31]), .B0(n4218), .B1(
intDX_EWSW[30]), .C0(n2691), .Y(n2698) );
AOI22X1TS U3546 ( .A0(n4038), .A1(intDX_EWSW[29]), .B0(n4176), .B1(
intDX_EWSW[20]), .Y(n2692) );
OAI221XLTS U3547 ( .A0(n4038), .A1(intDX_EWSW[29]), .B0(n4176), .B1(
intDX_EWSW[20]), .C0(n2692), .Y(n2697) );
AOI22X1TS U3548 ( .A0(n4042), .A1(intDX_EWSW[27]), .B0(n4180), .B1(
intDX_EWSW[26]), .Y(n2693) );
OAI221XLTS U3549 ( .A0(n4042), .A1(intDX_EWSW[27]), .B0(n4180), .B1(
intDX_EWSW[26]), .C0(n2693), .Y(n2696) );
AOI22X1TS U3550 ( .A0(n4040), .A1(intDX_EWSW[25]), .B0(n4183), .B1(
intDX_EWSW[32]), .Y(n2694) );
OAI221XLTS U3551 ( .A0(n4040), .A1(intDX_EWSW[25]), .B0(n4183), .B1(
intDX_EWSW[32]), .C0(n2694), .Y(n2695) );
NOR4XLTS U3552 ( .A(n2698), .B(n2697), .C(n2696), .D(n2695), .Y(n2726) );
OAI221XLTS U3553 ( .A0(n4063), .A1(intDX_EWSW[23]), .B0(n4217), .B1(
intDX_EWSW[22]), .C0(n2699), .Y(n2706) );
AOI22X1TS U3554 ( .A0(n4172), .A1(intDX_EWSW[21]), .B0(n4192), .B1(
intDX_EWSW[48]), .Y(n2700) );
OAI221XLTS U3555 ( .A0(n4172), .A1(intDX_EWSW[21]), .B0(n4192), .B1(
intDX_EWSW[48]), .C0(n2700), .Y(n2705) );
AOI22X1TS U3556 ( .A0(n4041), .A1(intDX_EWSW[19]), .B0(n4179), .B1(
intDX_EWSW[18]), .Y(n2701) );
OAI221XLTS U3557 ( .A0(n4041), .A1(intDX_EWSW[19]), .B0(n4179), .B1(
intDX_EWSW[18]), .C0(n2701), .Y(n2704) );
AOI22X1TS U3558 ( .A0(n4039), .A1(intDX_EWSW[17]), .B0(n4181), .B1(
intDX_EWSW[24]), .Y(n2702) );
OAI221XLTS U3559 ( .A0(n4039), .A1(intDX_EWSW[17]), .B0(n4181), .B1(
intDX_EWSW[24]), .C0(n2702), .Y(n2703) );
NOR4XLTS U3560 ( .A(n2706), .B(n2705), .C(n2704), .D(n2703), .Y(n2725) );
OAI221XLTS U3561 ( .A0(n4062), .A1(intDX_EWSW[15]), .B0(n4216), .B1(
intDX_EWSW[14]), .C0(n2707), .Y(n2714) );
AOI22X1TS U3562 ( .A0(n4171), .A1(intDX_EWSW[13]), .B0(n4052), .B1(
intDX_EWSW[4]), .Y(n2708) );
OAI221XLTS U3563 ( .A0(n4171), .A1(intDX_EWSW[13]), .B0(n4052), .B1(
intDX_EWSW[4]), .C0(n2708), .Y(n2713) );
AOI22X1TS U3564 ( .A0(n4173), .A1(intDX_EWSW[10]), .B0(n4175), .B1(
intDX_EWSW[12]), .Y(n2709) );
OAI221XLTS U3565 ( .A0(n4173), .A1(intDX_EWSW[10]), .B0(n4175), .B1(
intDX_EWSW[12]), .C0(n2709), .Y(n2712) );
AOI22X1TS U3566 ( .A0(n4174), .A1(intDX_EWSW[9]), .B0(n4193), .B1(
intDX_EWSW[16]), .Y(n2710) );
OAI221XLTS U3567 ( .A0(n4174), .A1(intDX_EWSW[9]), .B0(n4193), .B1(
intDX_EWSW[16]), .C0(n2710), .Y(n2711) );
NOR4XLTS U3568 ( .A(n2714), .B(n2713), .C(n2712), .D(n2711), .Y(n2724) );
OAI221XLTS U3569 ( .A0(n4219), .A1(intDX_EWSW[7]), .B0(n4066), .B1(
intDX_EWSW[6]), .C0(n2715), .Y(n2722) );
AOI22X1TS U3570 ( .A0(n4207), .A1(intDX_EWSW[5]), .B0(n4177), .B1(
intDX_EWSW[28]), .Y(n2716) );
OAI221XLTS U3571 ( .A0(n4207), .A1(intDX_EWSW[5]), .B0(n4177), .B1(
intDX_EWSW[28]), .C0(n2716), .Y(n2721) );
AOI22X1TS U3572 ( .A0(n4037), .A1(intDX_EWSW[3]), .B0(n4182), .B1(
intDX_EWSW[2]), .Y(n2717) );
OAI221XLTS U3573 ( .A0(n4037), .A1(intDX_EWSW[3]), .B0(n4182), .B1(
intDX_EWSW[2]), .C0(n2717), .Y(n2720) );
AOI22X1TS U3574 ( .A0(n4043), .A1(intDX_EWSW[0]), .B0(n4178), .B1(
intDX_EWSW[8]), .Y(n2718) );
OAI221XLTS U3575 ( .A0(n4043), .A1(intDX_EWSW[0]), .B0(n4178), .B1(
intDX_EWSW[8]), .C0(n2718), .Y(n2719) );
NOR4XLTS U3576 ( .A(n2722), .B(n2721), .C(n2720), .D(n2719), .Y(n2723) );
NAND4XLTS U3577 ( .A(n2726), .B(n2725), .C(n2724), .D(n2723), .Y(n2727) );
NOR4XLTS U3578 ( .A(n2730), .B(n2729), .C(n2728), .D(n2727), .Y(n3940) );
XNOR2X1TS U3579 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n3935) );
AOI22X1TS U3580 ( .A0(intDX_EWSW[63]), .A1(n2732), .B0(SIGN_FLAG_EXP), .B1(
n2731), .Y(n2733) );
OAI31X1TS U3581 ( .A0(n3940), .A1(n3935), .A2(n2734), .B0(n2733), .Y(n1609)
);
AOI22X1TS U3582 ( .A0(n3797), .A1(n3816), .B0(n1936), .B1(n3851), .Y(n2735)
);
INVX2TS U3583 ( .A(n2931), .Y(n3158) );
INVX2TS U3584 ( .A(n3790), .Y(n2737) );
AOI22X1TS U3585 ( .A0(Data_array_SWR[37]), .A1(n3740), .B0(
Data_array_SWR[49]), .B1(n1933), .Y(n2739) );
AOI22X1TS U3586 ( .A0(Data_array_SWR[41]), .A1(n3734), .B0(
Data_array_SWR[45]), .B1(n3733), .Y(n2738) );
NAND2X1TS U3587 ( .A(n2739), .B(n2738), .Y(n3793) );
OAI222X1TS U3588 ( .A0(n1915), .A1(n3158), .B0(n4275), .B1(n3970), .C0(n3159), .C1(n3160), .Y(n1138) );
AOI22X1TS U3589 ( .A0(Data_array_SWR[37]), .A1(n2742), .B0(
Data_array_SWR[33]), .B1(n3734), .Y(n2744) );
AOI22X1TS U3590 ( .A0(Data_array_SWR[41]), .A1(n1932), .B0(
Data_array_SWR[29]), .B1(n3710), .Y(n2743) );
NAND2X1TS U3591 ( .A(n2744), .B(n2743), .Y(n3757) );
AOI22X1TS U3592 ( .A0(n3809), .A1(n3757), .B0(n3797), .B1(n3756), .Y(n2745)
);
NAND2X1TS U3593 ( .A(n2745), .B(n1901), .Y(n2961) );
INVX2TS U3594 ( .A(n2961), .Y(n3155) );
OAI222X1TS U3595 ( .A0(n3159), .A1(n3155), .B0(n4274), .B1(n3175), .C0(n1915), .C1(n3154), .Y(n1130) );
NOR2XLTS U3596 ( .A(n2749), .B(n4024), .Y(n2771) );
OA21XLTS U3597 ( .A0(Raw_mant_NRM_SWR[24]), .A1(Raw_mant_NRM_SWR[22]), .B0(
n2750), .Y(n2757) );
AOI31XLTS U3598 ( .A0(n2753), .A1(n4226), .A2(n2752), .B0(n2751), .Y(n2754)
);
AOI211XLTS U3599 ( .A0(n2773), .A1(Raw_mant_NRM_SWR[8]), .B0(n2757), .C0(
n2756), .Y(n2758) );
OAI2BB1X1TS U3600 ( .A0N(n2759), .A1N(n2771), .B0(n2758), .Y(n2760) );
CLKBUFX2TS U3601 ( .A(n2912), .Y(n2898) );
AOI22X1TS U3602 ( .A0(n2999), .A1(shift_value_SHT2_EWR[3]), .B0(n2781), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n2764) );
AOI211XLTS U3603 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2773), .B0(n2772), .C0(
n2771), .Y(n2780) );
OAI21XLTS U3604 ( .A0(Raw_mant_NRM_SWR[1]), .A1(Raw_mant_NRM_SWR[0]), .B0(
n2776), .Y(n2777) );
AND4X1TS U3605 ( .A(n2780), .B(n2779), .C(n2778), .D(n2777), .Y(n2784) );
AOI22X1TS U3606 ( .A0(n2882), .A1(shift_value_SHT2_EWR[5]), .B0(n2781), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n2782) );
INVX2TS U3607 ( .A(n2908), .Y(n3637) );
AOI21X1TS U3608 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[0]), .B0(n2785), .Y(n3167) );
AOI21X1TS U3609 ( .A0(n2882), .A1(Data_array_SWR[54]), .B0(n2906), .Y(n2786)
);
INVX2TS U3610 ( .A(n2787), .Y(n2959) );
AOI22X1TS U3611 ( .A0(n2800), .A1(n2957), .B0(final_result_ieee[28]), .B1(
n3886), .Y(n2788) );
AOI22X1TS U3612 ( .A0(n2800), .A1(n2939), .B0(final_result_ieee[5]), .B1(
n3974), .Y(n2789) );
CLKBUFX2TS U3613 ( .A(n3979), .Y(n2960) );
AOI22X1TS U3614 ( .A0(n2800), .A1(n2954), .B0(final_result_ieee[9]), .B1(
n2960), .Y(n2790) );
AOI22X1TS U3615 ( .A0(n2800), .A1(n2936), .B0(final_result_ieee[7]), .B1(
n2960), .Y(n2791) );
INVX2TS U3616 ( .A(n2792), .Y(n2953) );
AOI22X1TS U3617 ( .A0(n1928), .A1(n2951), .B0(final_result_ieee[26]), .B1(
n3886), .Y(n2793) );
AOI22X1TS U3618 ( .A0(n1928), .A1(n2933), .B0(final_result_ieee[8]), .B1(
n2960), .Y(n2794) );
AOI22X1TS U3619 ( .A0(n1928), .A1(n2945), .B0(final_result_ieee[17]), .B1(
n2960), .Y(n2795) );
INVX2TS U3620 ( .A(n2796), .Y(n2944) );
AOI22X1TS U3621 ( .A0(n1928), .A1(n2942), .B0(final_result_ieee[29]), .B1(
n3886), .Y(n2797) );
AOI22X1TS U3622 ( .A0(n2800), .A1(n2948), .B0(final_result_ieee[6]), .B1(
n3974), .Y(n2798) );
AOI22X1TS U3623 ( .A0(n1928), .A1(n2961), .B0(final_result_ieee[27]), .B1(
n3886), .Y(n2799) );
AOI22X1TS U3624 ( .A0(n1928), .A1(n2931), .B0(final_result_ieee[15]), .B1(
n2960), .Y(n2801) );
AOI22X1TS U3625 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[28]), .B0(n3866), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2803) );
OA21XLTS U3626 ( .A0(n2912), .A1(n4070), .B0(n2803), .Y(n2820) );
CLKBUFX2TS U3627 ( .A(n2920), .Y(n3113) );
AOI22X1TS U3628 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[29]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[27]), .Y(n2806) );
OA21XLTS U3629 ( .A0(n2912), .A1(n4019), .B0(n2806), .Y(n2824) );
INVX2TS U3630 ( .A(n2824), .Y(n2976) );
INVX2TS U3631 ( .A(n3169), .Y(n3122) );
AOI22X1TS U3632 ( .A0(n3113), .A1(n2976), .B0(n3122), .B1(Data_array_SWR[26]), .Y(n2809) );
CLKBUFX2TS U3633 ( .A(n2920), .Y(n3090) );
AOI22X1TS U3634 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[30]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2810) );
INVX2TS U3635 ( .A(n3169), .Y(n3104) );
AOI22X1TS U3636 ( .A0(n3090), .A1(n3076), .B0(n3104), .B1(Data_array_SWR[27]), .Y(n2815) );
AOI22X1TS U3637 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[23]), .B0(n4271), .B1(
DmP_mant_SHT1_SW[21]), .Y(n2816) );
OA21XLTS U3638 ( .A0(n2898), .A1(n4029), .B0(n2816), .Y(n3056) );
INVX2TS U3639 ( .A(n2997), .Y(n3168) );
OA22X1TS U3640 ( .A0(n3010), .A1(n3168), .B0(n3018), .B1(n3641), .Y(n2819)
);
INVX2TS U3641 ( .A(n2997), .Y(n2901) );
INVX2TS U3642 ( .A(n1917), .Y(n3644) );
CLKBUFX2TS U3643 ( .A(n3644), .Y(n3088) );
AOI22X1TS U3644 ( .A0(n2906), .A1(Raw_mant_NRM_SWR[31]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[29]), .Y(n2821) );
AOI22X1TS U3645 ( .A0(n3063), .A1(n3074), .B0(n3636), .B1(Data_array_SWR[28]), .Y(n2822) );
OAI22X1TS U3646 ( .A0(n4263), .A1(n2893), .B0(n4031), .B1(n2902), .Y(n2825)
);
AOI21X1TS U3647 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n3637), .B0(n2825), .Y(
n3640) );
INVX2TS U3648 ( .A(n2997), .Y(n3116) );
INVX2TS U3649 ( .A(n2910), .Y(n2885) );
OAI22X1TS U3650 ( .A0(n4291), .A1(n2903), .B0(n4073), .B1(n2885), .Y(n2826)
);
AOI21X1TS U3651 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n3637), .B0(n2826), .Y(
n3060) );
INVX2TS U3652 ( .A(n3060), .Y(n2860) );
AOI22X1TS U3653 ( .A0(n2910), .A1(Raw_mant_NRM_SWR[2]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2827) );
OA21XLTS U3654 ( .A0(n2912), .A1(n4028), .B0(n2827), .Y(n3635) );
CLKBUFX2TS U3655 ( .A(n2920), .Y(n3124) );
OAI22X1TS U3656 ( .A0(n4290), .A1(n2893), .B0(n4079), .B1(n2885), .Y(n2828)
);
AOI21X1TS U3657 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n3637), .B0(n2828), .Y(
n2890) );
INVX2TS U3658 ( .A(n2890), .Y(n3081) );
AOI22X1TS U3659 ( .A0(n3124), .A1(n3081), .B0(n3122), .B1(Data_array_SWR[2]),
.Y(n2829) );
OAI22X1TS U3660 ( .A0(n4304), .A1(n2903), .B0(n4033), .B1(n2885), .Y(n2831)
);
AOI21X1TS U3661 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[3]), .B0(n2831), .Y(n2923) );
OAI22X1TS U3662 ( .A0(n4302), .A1(n2864), .B0(n4089), .B1(n2885), .Y(n2832)
);
AOI21X1TS U3663 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[1]), .B0(n2832), .Y(n3165) );
OA22X1TS U3664 ( .A0(n2923), .A1(n1931), .B0(n3165), .B1(n1918), .Y(n2835)
);
OAI22X1TS U3665 ( .A0(n4292), .A1(n2903), .B0(n4028), .B1(n2885), .Y(n2833)
);
AOI21X1TS U3666 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[2]), .B0(n2833), .Y(n2916) );
OAI22X1TS U3667 ( .A0(n4297), .A1(n2864), .B0(n4020), .B1(n2878), .Y(n2836)
);
AOI21X1TS U3668 ( .A0(Raw_mant_NRM_SWR[33]), .A1(n2895), .B0(n2836), .Y(
n2924) );
OAI22X1TS U3669 ( .A0(n4285), .A1(n2864), .B0(n4074), .B1(n2878), .Y(n2837)
);
AOI21X1TS U3670 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2895), .B0(n2837), .Y(
n3062) );
OAI22X1TS U3671 ( .A0(n4258), .A1(n2864), .B0(n4078), .B1(n2878), .Y(n2838)
);
AOI21X1TS U3672 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[32]), .B0(n2838), .Y(
n3013) );
OA22X1TS U3673 ( .A0(n3062), .A1(n3166), .B0(n3013), .B1(n1917), .Y(n2840)
);
INVX2TS U3674 ( .A(n3056), .Y(n3009) );
AOI22X1TS U3675 ( .A0(n2920), .A1(n3009), .B0(n2882), .B1(Data_array_SWR[20]), .Y(n2839) );
OAI22X1TS U3676 ( .A0(n4294), .A1(Shift_reg_FLAGS_7[1]), .B0(n4088), .B1(
n3129), .Y(n2841) );
AOI21X1TS U3677 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[13]), .B0(n2841), .Y(
n2968) );
OAI22X1TS U3678 ( .A0(n4282), .A1(Shift_reg_FLAGS_7[1]), .B0(n4030), .B1(
n3129), .Y(n2842) );
AOI21X1TS U3679 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[14]), .B0(n2842), .Y(
n3020) );
OAI22X1TS U3680 ( .A0(n4255), .A1(n3972), .B0(n4015), .B1(n3129), .Y(n2843)
);
AOI21X1TS U3681 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[12]), .B0(n2843), .Y(
n3006) );
OA22X1TS U3682 ( .A0(n3020), .A1(n3166), .B0(n3006), .B1(n1918), .Y(n2846)
);
AOI22X1TS U3683 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[43]), .B0(n4271), .B1(
DmP_mant_SHT1_SW[41]), .Y(n2844) );
AOI22X1TS U3684 ( .A0(n2920), .A1(n3026), .B0(n2882), .B1(Data_array_SWR[40]), .Y(n2845) );
OAI22X1TS U3685 ( .A0(n4296), .A1(Shift_reg_FLAGS_7[1]), .B0(n4090), .B1(
n2878), .Y(n2847) );
AOI21X1TS U3686 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[21]), .B0(n2847), .Y(
n2927) );
OAI22X1TS U3687 ( .A0(n4284), .A1(n2864), .B0(n2885), .B1(n4077), .Y(n2848)
);
AOI21X1TS U3688 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[22]), .B0(n2848), .Y(
n2977) );
OAI22X1TS U3689 ( .A0(n4257), .A1(n3972), .B0(n4069), .B1(n2878), .Y(n2849)
);
AOI21X1TS U3690 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[20]), .B0(n2849), .Y(
n3036) );
OA22X1TS U3691 ( .A0(n2977), .A1(n3166), .B0(n3036), .B1(n1918), .Y(n2852)
);
AOI22X1TS U3692 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[35]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[33]), .Y(n2850) );
AOI22X1TS U3693 ( .A0(n2920), .A1(n3067), .B0(n2882), .B1(Data_array_SWR[32]), .Y(n2851) );
OAI22X1TS U3694 ( .A0(n4295), .A1(Shift_reg_FLAGS_7[1]), .B0(n4091), .B1(
n3129), .Y(n2853) );
AOI21X1TS U3695 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[9]), .B0(n2853), .Y(n2986) );
OAI22X1TS U3696 ( .A0(n4283), .A1(Shift_reg_FLAGS_7[1]), .B0(n4016), .B1(
n2878), .Y(n2854) );
AOI21X1TS U3697 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[10]), .B0(n2854), .Y(
n3005) );
OAI22X1TS U3698 ( .A0(n4256), .A1(n3972), .B0(n4034), .B1(n2878), .Y(n2855)
);
AOI21X1TS U3699 ( .A0(n2856), .A1(Raw_mant_NRM_SWR[8]), .B0(n2855), .Y(n2991) );
OA22X1TS U3700 ( .A0(n3005), .A1(n3166), .B0(n2991), .B1(n1917), .Y(n2859)
);
AOI22X1TS U3701 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[47]), .B0(n4271), .B1(
DmP_mant_SHT1_SW[45]), .Y(n2857) );
AOI22X1TS U3702 ( .A0(n2920), .A1(n2987), .B0(n2882), .B1(Data_array_SWR[44]), .Y(n2858) );
INVX2TS U3703 ( .A(n2997), .Y(n3086) );
AOI22X1TS U3704 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[1]), .B0(n3637), .B1(
Raw_mant_NRM_SWR[53]), .Y(n3639) );
OA22X1TS U3705 ( .A0(n3639), .A1(n3166), .B0(n3640), .B1(n1918), .Y(n2862)
);
INVX2TS U3706 ( .A(n3169), .Y(n3083) );
AOI22X1TS U3707 ( .A0(n3063), .A1(n2860), .B0(n3083), .B1(Data_array_SWR[1]),
.Y(n2861) );
OAI22X1TS U3708 ( .A0(n4299), .A1(n2864), .B0(n4032), .B1(n2902), .Y(n2863)
);
AOI21X1TS U3709 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2895), .B0(n2863), .Y(
n2992) );
OAI22X1TS U3710 ( .A0(n4287), .A1(n2864), .B0(n2885), .B1(n4046), .Y(n2865)
);
AOI21X1TS U3711 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2895), .B0(n2865), .Y(
n2995) );
OAI22X1TS U3712 ( .A0(n4260), .A1(n2893), .B0(n4076), .B1(n2902), .Y(n2866)
);
AOI21X1TS U3713 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2895), .B0(n2866), .Y(
n3066) );
OA22X1TS U3714 ( .A0(n2995), .A1(n3166), .B0(n3066), .B1(n1918), .Y(n2870)
);
AOI22X1TS U3715 ( .A0(n2867), .A1(Raw_mant_NRM_SWR[19]), .B0(n4271), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2868) );
AOI22X1TS U3716 ( .A0(n2920), .A1(n3109), .B0(n3636), .B1(Data_array_SWR[16]), .Y(n2869) );
OAI22X1TS U3717 ( .A0(n4301), .A1(n2893), .B0(n4092), .B1(n2902), .Y(n2871)
);
AOI21X1TS U3718 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n3637), .B0(n2871), .Y(
n2965) );
OAI22X1TS U3719 ( .A0(n4289), .A1(n2893), .B0(n4086), .B1(n2902), .Y(n2872)
);
AOI21X1TS U3720 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n3637), .B0(n2872), .Y(
n3108) );
OAI22X1TS U3721 ( .A0(n4262), .A1(n2893), .B0(n4048), .B1(n2885), .Y(n2873)
);
AOI21X1TS U3722 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n3637), .B0(n2873), .Y(
n3038) );
OA22X1TS U3723 ( .A0(n3108), .A1(n3166), .B0(n3038), .B1(n1917), .Y(n2876)
);
AOI22X1TS U3724 ( .A0(n2910), .A1(Raw_mant_NRM_SWR[15]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[13]), .Y(n2874) );
AOI22X1TS U3725 ( .A0(n3063), .A1(n3037), .B0(n3636), .B1(Data_array_SWR[12]), .Y(n2875) );
OAI22X1TS U3726 ( .A0(n4293), .A1(n2893), .B0(n4087), .B1(n2885), .Y(n2877)
);
AOI21X1TS U3727 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[17]), .B0(n2877), .Y(
n3019) );
OAI22X1TS U3728 ( .A0(n4281), .A1(Shift_reg_FLAGS_7[1]), .B0(n4017), .B1(
n2878), .Y(n2879) );
AOI21X1TS U3729 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[18]), .B0(n2879), .Y(
n3033) );
OAI22X1TS U3730 ( .A0(n4254), .A1(n3972), .B0(n4093), .B1(n3129), .Y(n2880)
);
AOI21X1TS U3731 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[16]), .B0(n2880), .Y(
n3023) );
OA22X1TS U3732 ( .A0(n3033), .A1(n1931), .B0(n3023), .B1(n1917), .Y(n2884)
);
AOI22X1TS U3733 ( .A0(n2906), .A1(Raw_mant_NRM_SWR[39]), .B0(n4271), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2881) );
AOI22X1TS U3734 ( .A0(n3090), .A1(n3118), .B0(n2882), .B1(Data_array_SWR[36]), .Y(n2883) );
OAI22X1TS U3735 ( .A0(n4264), .A1(n2903), .B0(n4044), .B1(n2885), .Y(n2886)
);
AOI21X1TS U3736 ( .A0(Raw_mant_NRM_SWR[48]), .A1(n3637), .B0(n2886), .Y(
n3087) );
OA22X1TS U3737 ( .A0(n3060), .A1(n3166), .B0(n3087), .B1(n1918), .Y(n2889)
);
AOI22X1TS U3738 ( .A0(n2910), .A1(Raw_mant_NRM_SWR[7]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2887) );
AOI22X1TS U3739 ( .A0(n3063), .A1(n3094), .B0(n3636), .B1(Data_array_SWR[4]),
.Y(n2888) );
OAI22X1TS U3740 ( .A0(n4300), .A1(n2893), .B0(n4068), .B1(n2902), .Y(n2891)
);
AOI21X1TS U3741 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2895), .B0(n2891), .Y(
n3043) );
OAI22X1TS U3742 ( .A0(n4288), .A1(n2893), .B0(n4051), .B1(n2902), .Y(n2892)
);
AOI21X1TS U3743 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n2895), .B0(n2892), .Y(
n3093) );
OAI22X1TS U3744 ( .A0(n4261), .A1(n2893), .B0(n4024), .B1(n2902), .Y(n2894)
);
AOI21X1TS U3745 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2895), .B0(n2894), .Y(
n3046) );
OA22X1TS U3746 ( .A0(n3093), .A1(n3166), .B0(n3046), .B1(n1917), .Y(n2900)
);
AOI22X1TS U3747 ( .A0(n2910), .A1(Raw_mant_NRM_SWR[11]), .B0(n2896), .B1(
DmP_mant_SHT1_SW[9]), .Y(n2897) );
AOI22X1TS U3748 ( .A0(n3063), .A1(n3102), .B0(n3636), .B1(Data_array_SWR[8]),
.Y(n2899) );
OAI22X1TS U3749 ( .A0(n4303), .A1(n2903), .B0(n4011), .B1(n2902), .Y(n2904)
);
AOI21X1TS U3750 ( .A0(n2905), .A1(Raw_mant_NRM_SWR[5]), .B0(n2904), .Y(n2982) );
INVX2TS U3751 ( .A(n3166), .Y(n2981) );
CLKBUFX2TS U3752 ( .A(n2981), .Y(n2928) );
AOI22X1TS U3753 ( .A0(n2906), .A1(Raw_mant_NRM_SWR[48]), .B0(n2909), .B1(
DmP_mant_SHT1_SW[46]), .Y(n2907) );
CLKBUFX2TS U3754 ( .A(n3644), .Y(n3120) );
AOI22X1TS U3755 ( .A0(n2910), .A1(Raw_mant_NRM_SWR[50]), .B0(n2909), .B1(
DmP_mant_SHT1_SW[48]), .Y(n2911) );
AOI22X1TS U3756 ( .A0(n2928), .A1(n2988), .B0(n3120), .B1(n2972), .Y(n2914)
);
INVX2TS U3757 ( .A(n2923), .Y(n2915) );
AOI22X1TS U3758 ( .A0(n3113), .A1(n2915), .B0(n3104), .B1(Data_array_SWR[48]), .Y(n2913) );
INVX2TS U3759 ( .A(n2972), .Y(n2919) );
INVX2TS U3760 ( .A(n2982), .Y(n2971) );
AOI22X1TS U3761 ( .A0(n2928), .A1(n2971), .B0(n3088), .B1(n2915), .Y(n2918)
);
INVX2TS U3762 ( .A(n2916), .Y(n2998) );
AOI22X1TS U3763 ( .A0(n3090), .A1(n2998), .B0(n2999), .B1(Data_array_SWR[49]), .Y(n2917) );
INVX2TS U3764 ( .A(n3165), .Y(n2996) );
AOI22X1TS U3765 ( .A0(n2928), .A1(n2972), .B0(n2920), .B1(n2996), .Y(n2922)
);
AOI22X1TS U3766 ( .A0(n3088), .A1(n2998), .B0(n2999), .B1(Data_array_SWR[50]), .Y(n2921) );
INVX2TS U3767 ( .A(n2924), .Y(n3112) );
AOI22X1TS U3768 ( .A0(n2928), .A1(n3109), .B0(n3120), .B1(n3112), .Y(n2926)
);
INVX2TS U3769 ( .A(n3013), .Y(n3052) );
AOI22X1TS U3770 ( .A0(n3090), .A1(n3052), .B0(n2999), .B1(Data_array_SWR[19]), .Y(n2925) );
INVX2TS U3771 ( .A(n2927), .Y(n3077) );
AOI22X1TS U3772 ( .A0(n2928), .A1(n3074), .B0(n3088), .B1(n3077), .Y(n2930)
);
INVX2TS U3773 ( .A(n3036), .Y(n3069) );
AOI22X1TS U3774 ( .A0(n3090), .A1(n3069), .B0(n2999), .B1(Data_array_SWR[31]), .Y(n2929) );
AOI22X1TS U3775 ( .A0(n2962), .A1(n2931), .B0(final_result_ieee[35]), .B1(
n2960), .Y(n2932) );
AOI22X1TS U3776 ( .A0(n1913), .A1(n2933), .B0(final_result_ieee[42]), .B1(
n2960), .Y(n2934) );
AOI22X1TS U3777 ( .A0(n2962), .A1(n2936), .B0(final_result_ieee[43]), .B1(
n3974), .Y(n2937) );
AOI22X1TS U3778 ( .A0(n2962), .A1(n2939), .B0(final_result_ieee[45]), .B1(
n3974), .Y(n2940) );
AOI22X1TS U3779 ( .A0(n2962), .A1(n2942), .B0(final_result_ieee[21]), .B1(
n3886), .Y(n2943) );
AOI22X1TS U3780 ( .A0(n1913), .A1(n2945), .B0(final_result_ieee[33]), .B1(
n2960), .Y(n2946) );
AOI22X1TS U3781 ( .A0(n2962), .A1(n2948), .B0(final_result_ieee[44]), .B1(
n3974), .Y(n2949) );
AOI22X1TS U3782 ( .A0(n2962), .A1(n2951), .B0(final_result_ieee[24]), .B1(
n3886), .Y(n2952) );
AOI22X1TS U3783 ( .A0(n2962), .A1(n2954), .B0(final_result_ieee[41]), .B1(
n2960), .Y(n2955) );
AOI22X1TS U3784 ( .A0(n2962), .A1(n2957), .B0(final_result_ieee[22]), .B1(
n3886), .Y(n2958) );
AOI22X1TS U3785 ( .A0(n1913), .A1(n2961), .B0(final_result_ieee[23]), .B1(
n2960), .Y(n2963) );
CLKBUFX2TS U3786 ( .A(n2981), .Y(n3082) );
INVX2TS U3787 ( .A(n2965), .Y(n3101) );
AOI22X1TS U3788 ( .A0(n3082), .A1(n3101), .B0(n3644), .B1(n3037), .Y(n2967)
);
INVX2TS U3789 ( .A(n2995), .Y(n3039) );
AOI22X1TS U3790 ( .A0(n3063), .A1(n3039), .B0(n3083), .B1(Data_array_SWR[13]), .Y(n2966) );
INVX2TS U3791 ( .A(n2968), .Y(n3123) );
AOI22X1TS U3792 ( .A0(n3082), .A1(n3123), .B0(n3644), .B1(n3026), .Y(n2970)
);
INVX2TS U3793 ( .A(n3005), .Y(n3027) );
AOI22X1TS U3794 ( .A0(n3113), .A1(n3027), .B0(n3083), .B1(Data_array_SWR[41]), .Y(n2969) );
CLKBUFX2TS U3795 ( .A(n2981), .Y(n3103) );
AOI22X1TS U3796 ( .A0(n3103), .A1(n2987), .B0(n3088), .B1(n2971), .Y(n2974)
);
AOI22X1TS U3797 ( .A0(n3090), .A1(n2972), .B0(n3104), .B1(Data_array_SWR[47]), .Y(n2973) );
INVX2TS U3798 ( .A(n3076), .Y(n2980) );
AOI22X1TS U3799 ( .A0(n3082), .A1(n2976), .B0(n3644), .B1(n3074), .Y(n2979)
);
INVX2TS U3800 ( .A(n2977), .Y(n3075) );
AOI22X1TS U3801 ( .A0(n3063), .A1(n3075), .B0(n3636), .B1(Data_array_SWR[29]), .Y(n2978) );
INVX2TS U3802 ( .A(n2987), .Y(n2985) );
INVX2TS U3803 ( .A(n2997), .Y(n3127) );
INVX2TS U3804 ( .A(n2991), .Y(n3002) );
AOI22X1TS U3805 ( .A0(n2928), .A1(n3002), .B0(n3120), .B1(n2988), .Y(n2984)
);
INVX2TS U3806 ( .A(n2986), .Y(n3029) );
AOI22X1TS U3807 ( .A0(n3082), .A1(n3029), .B0(n1896), .B1(n2987), .Y(n2990)
);
AOI22X1TS U3808 ( .A0(n3113), .A1(n2988), .B0(n3083), .B1(Data_array_SWR[45]), .Y(n2989) );
INVX2TS U3809 ( .A(n2992), .Y(n3061) );
AOI22X1TS U3810 ( .A0(n3103), .A1(n3037), .B0(n3120), .B1(n3061), .Y(n2994)
);
INVX2TS U3811 ( .A(n3066), .Y(n3111) );
AOI22X1TS U3812 ( .A0(n3124), .A1(n3111), .B0(n3104), .B1(Data_array_SWR[15]), .Y(n2993) );
AOI22X1TS U3813 ( .A0(n3103), .A1(n2998), .B0(n2997), .B1(n2996), .Y(n3001)
);
NAND2X1TS U3814 ( .A(n2999), .B(Data_array_SWR[52]), .Y(n3000) );
AOI22X1TS U3815 ( .A0(n3103), .A1(n3026), .B0(n3088), .B1(n3029), .Y(n3004)
);
AOI22X1TS U3816 ( .A0(n3090), .A1(n3002), .B0(n3104), .B1(Data_array_SWR[43]), .Y(n3003) );
AOI22X1TS U3817 ( .A0(n3103), .A1(n3118), .B0(n3088), .B1(n3123), .Y(n3008)
);
INVX2TS U3818 ( .A(n3006), .Y(n3028) );
AOI22X1TS U3819 ( .A0(n3090), .A1(n3028), .B0(n3104), .B1(Data_array_SWR[39]), .Y(n3007) );
AOI22X1TS U3820 ( .A0(n3082), .A1(n3112), .B0(n3644), .B1(n3009), .Y(n3012)
);
INVX2TS U3821 ( .A(n3010), .Y(n3051) );
AOI22X1TS U3822 ( .A0(n3063), .A1(n3051), .B0(n3636), .B1(Data_array_SWR[21]), .Y(n3011) );
AOI22X1TS U3823 ( .A0(n3082), .A1(n3053), .B0(n3636), .B1(Data_array_SWR[25]), .Y(n3017) );
NAND2X1TS U3824 ( .A(n3015), .B(n3014), .Y(n3016) );
INVX2TS U3825 ( .A(n3019), .Y(n3070) );
AOI22X1TS U3826 ( .A0(n3082), .A1(n3070), .B0(n1896), .B1(n3118), .Y(n3022)
);
INVX2TS U3827 ( .A(n3020), .Y(n3119) );
AOI22X1TS U3828 ( .A0(n3113), .A1(n3119), .B0(n3083), .B1(Data_array_SWR[37]), .Y(n3021) );
AOI22X1TS U3829 ( .A0(n3103), .A1(n3067), .B0(n3088), .B1(n3070), .Y(n3025)
);
INVX2TS U3830 ( .A(n3023), .Y(n3121) );
AOI22X1TS U3831 ( .A0(n3090), .A1(n3121), .B0(n3122), .B1(Data_array_SWR[35]), .Y(n3024) );
INVX2TS U3832 ( .A(n3026), .Y(n3032) );
AOI22X1TS U3833 ( .A0(n2981), .A1(n3028), .B0(n3120), .B1(n3027), .Y(n3031)
);
AOI22X1TS U3834 ( .A0(n3124), .A1(n3029), .B0(n3122), .B1(Data_array_SWR[42]), .Y(n3030) );
AOI22X1TS U3835 ( .A0(n2981), .A1(n3077), .B0(n1896), .B1(n3067), .Y(n3035)
);
INVX2TS U3836 ( .A(n3033), .Y(n3068) );
AOI22X1TS U3837 ( .A0(n3113), .A1(n3068), .B0(n3083), .B1(Data_array_SWR[33]), .Y(n3034) );
INVX2TS U3838 ( .A(n3037), .Y(n3042) );
INVX2TS U3839 ( .A(n3038), .Y(n3105) );
AOI22X1TS U3840 ( .A0(n2981), .A1(n3105), .B0(n1896), .B1(n3039), .Y(n3041)
);
AOI22X1TS U3841 ( .A0(n3124), .A1(n3061), .B0(n3122), .B1(Data_array_SWR[14]), .Y(n3040) );
INVX2TS U3842 ( .A(n3043), .Y(n3097) );
AOI22X1TS U3843 ( .A0(n3082), .A1(n3097), .B0(n3644), .B1(n3102), .Y(n3045)
);
INVX2TS U3844 ( .A(n3108), .Y(n3047) );
AOI22X1TS U3845 ( .A0(n3063), .A1(n3047), .B0(n3083), .B1(Data_array_SWR[9]),
.Y(n3044) );
INVX2TS U3846 ( .A(n3102), .Y(n3050) );
INVX2TS U3847 ( .A(n3046), .Y(n3089) );
AOI22X1TS U3848 ( .A0(n2928), .A1(n3089), .B0(n1896), .B1(n3047), .Y(n3049)
);
AOI22X1TS U3849 ( .A0(n3124), .A1(n3101), .B0(n3122), .B1(Data_array_SWR[10]), .Y(n3048) );
AOI22X1TS U3850 ( .A0(n2928), .A1(n3052), .B0(n1896), .B1(n3051), .Y(n3055)
);
AOI22X1TS U3851 ( .A0(n3113), .A1(n3053), .B0(n3083), .B1(Data_array_SWR[22]), .Y(n3054) );
INVX2TS U3852 ( .A(n3640), .Y(n3057) );
AOI22X1TS U3853 ( .A0(n3103), .A1(n3057), .B0(n3120), .B1(n3081), .Y(n3059)
);
INVX2TS U3854 ( .A(n3087), .Y(n3096) );
AOI22X1TS U3855 ( .A0(n3124), .A1(n3096), .B0(n3104), .B1(Data_array_SWR[3]),
.Y(n3058) );
AOI22X1TS U3856 ( .A0(n3082), .A1(n3061), .B0(n3644), .B1(n3109), .Y(n3065)
);
INVX2TS U3857 ( .A(n3062), .Y(n3110) );
AOI22X1TS U3858 ( .A0(n3063), .A1(n3110), .B0(n3083), .B1(Data_array_SWR[17]), .Y(n3064) );
INVX2TS U3859 ( .A(n3067), .Y(n3073) );
AOI22X1TS U3860 ( .A0(n3103), .A1(n3069), .B0(n3120), .B1(n3068), .Y(n3072)
);
AOI22X1TS U3861 ( .A0(n3124), .A1(n3070), .B0(n3104), .B1(Data_array_SWR[34]), .Y(n3071) );
INVX2TS U3862 ( .A(n3074), .Y(n3080) );
AOI22X1TS U3863 ( .A0(n2981), .A1(n3076), .B0(n3644), .B1(n3075), .Y(n3079)
);
AOI22X1TS U3864 ( .A0(n3113), .A1(n3077), .B0(n3122), .B1(Data_array_SWR[30]), .Y(n3078) );
AOI22X1TS U3865 ( .A0(n3082), .A1(n3081), .B0(n1896), .B1(n3094), .Y(n3085)
);
INVX2TS U3866 ( .A(n3093), .Y(n3095) );
AOI22X1TS U3867 ( .A0(n3113), .A1(n3095), .B0(n3083), .B1(Data_array_SWR[5]),
.Y(n3084) );
AOI22X1TS U3868 ( .A0(n3103), .A1(n3094), .B0(n3088), .B1(n3097), .Y(n3092)
);
AOI22X1TS U3869 ( .A0(n3090), .A1(n3089), .B0(n3104), .B1(Data_array_SWR[7]),
.Y(n3091) );
INVX2TS U3870 ( .A(n3094), .Y(n3100) );
AOI22X1TS U3871 ( .A0(n2928), .A1(n3096), .B0(n3120), .B1(n3095), .Y(n3099)
);
AOI22X1TS U3872 ( .A0(n3124), .A1(n3097), .B0(n3122), .B1(Data_array_SWR[6]),
.Y(n3098) );
AOI22X1TS U3873 ( .A0(n3103), .A1(n3102), .B0(n3120), .B1(n3101), .Y(n3107)
);
AOI22X1TS U3874 ( .A0(n3124), .A1(n3105), .B0(n3104), .B1(Data_array_SWR[11]), .Y(n3106) );
INVX2TS U3875 ( .A(n3109), .Y(n3117) );
AOI22X1TS U3876 ( .A0(n2928), .A1(n3111), .B0(n1896), .B1(n3110), .Y(n3115)
);
AOI22X1TS U3877 ( .A0(n3113), .A1(n3112), .B0(n3122), .B1(Data_array_SWR[18]), .Y(n3114) );
AOI22X1TS U3878 ( .A0(n2981), .A1(n3121), .B0(n3120), .B1(n3119), .Y(n3126)
);
AOI22X1TS U3879 ( .A0(n3124), .A1(n3123), .B0(n3122), .B1(Data_array_SWR[38]), .Y(n3125) );
OAI21XLTS U3880 ( .A0(n3865), .A1(n1908), .B0(n3129), .Y(n1275) );
OAI21XLTS U3881 ( .A0(n3169), .A1(n4188), .B0(n3129), .Y(n1753) );
AOI22X1TS U3882 ( .A0(intDX_EWSW[38]), .A1(n3131), .B0(DmP_EXP_EWSW[38]),
.B1(n3130), .Y(n3132) );
OAI21XLTS U3883 ( .A0(n4205), .A1(n3133), .B0(n3132), .Y(n1321) );
AOI22X1TS U3884 ( .A0(intDX_EWSW[5]), .A1(n3135), .B0(DmP_EXP_EWSW[5]), .B1(
n3134), .Y(n3136) );
OAI21XLTS U3885 ( .A0(n4207), .A1(n3137), .B0(n3136), .Y(n1387) );
NOR2BX1TS U3886 ( .AN(n3138), .B(Data_array_SWR[54]), .Y(n3139) );
INVX2TS U3887 ( .A(n3139), .Y(n3140) );
NAND2X1TS U3888 ( .A(n3141), .B(n3140), .Y(n3801) );
INVX2TS U3889 ( .A(n3801), .Y(n3143) );
AOI21X1TS U3890 ( .A0(n3809), .A1(n3143), .B0(n3142), .Y(n3156) );
AOI22X1TS U3891 ( .A0(Data_array_SWR[44]), .A1(n1933), .B0(
Data_array_SWR[32]), .B1(n3710), .Y(n3145) );
AOI22X1TS U3892 ( .A0(Data_array_SWR[36]), .A1(n3738), .B0(
Data_array_SWR[40]), .B1(n3737), .Y(n3144) );
NAND2X1TS U3893 ( .A(n3145), .B(n3144), .Y(n3812) );
AOI22X1TS U3894 ( .A0(Data_array_SWR[52]), .A1(n3738), .B0(
Data_array_SWR[48]), .B1(n3710), .Y(n3147) );
NAND2X1TS U3895 ( .A(n3147), .B(n3146), .Y(n3847) );
NOR2BX1TS U3896 ( .AN(n3847), .B(n3746), .Y(n3153) );
AOI22X1TS U3897 ( .A0(Data_array_SWR[16]), .A1(n3740), .B0(
Data_array_SWR[28]), .B1(n1932), .Y(n3149) );
AOI22X1TS U3898 ( .A0(Data_array_SWR[24]), .A1(n3733), .B0(
Data_array_SWR[20]), .B1(n3726), .Y(n3148) );
CLKAND2X2TS U3899 ( .A(n3149), .B(n3148), .Y(n3779) );
AOI22X1TS U3900 ( .A0(Data_array_SWR[0]), .A1(n1924), .B0(Data_array_SWR[12]), .B1(n1912), .Y(n3151) );
AOI22X1TS U3901 ( .A0(Data_array_SWR[8]), .A1(n1922), .B0(Data_array_SWR[4]),
.B1(n3768), .Y(n3150) );
OAI222X1TS U3902 ( .A0(n1915), .A1(n3156), .B0(n4277), .B1(n3970), .C0(n1919), .C1(n3157), .Y(n1101) );
OAI222X1TS U3903 ( .A0(n1915), .A1(n3155), .B0(n4279), .B1(n3175), .C0(n1919), .C1(n3154), .Y(n1126) );
OAI222X1TS U3904 ( .A0(n1915), .A1(n3157), .B0(n4272), .B1(n3175), .C0(n3159), .C1(n3156), .Y(n1155) );
OAI222X1TS U3905 ( .A0(n1895), .A1(n3160), .B0(n4278), .B1(n3175), .C0(n1919), .C1(n3158), .Y(n1118) );
AOI22X1TS U3906 ( .A0(intDX_EWSW[5]), .A1(n3162), .B0(DMP_EXP_EWSW[5]), .B1(
n3161), .Y(n3163) );
OAI21XLTS U3907 ( .A0(n4207), .A1(n3164), .B0(n3163), .Y(n1669) );
OAI222X1TS U3908 ( .A0(n4242), .A1(n3169), .B0(n3168), .B1(n3167), .C0(n1931), .C1(n3165), .Y(n1698) );
CLKBUFX2TS U3909 ( .A(n4386), .Y(n4306) );
CLKBUFX2TS U3910 ( .A(n4280), .Y(n3966) );
NOR2XLTS U3911 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n3170) );
MX2X1TS U3912 ( .A(Shift_reg_FLAGS_7[2]), .B(Shift_reg_FLAGS_7[3]), .S0(
n3887), .Y(n1885) );
INVX2TS U3913 ( .A(n3970), .Y(n3860) );
MX2X1TS U3914 ( .A(DMP_SHT2_EWSW[51]), .B(DMP_SFG[51]), .S0(n3860), .Y(n1453) );
MX2X1TS U3915 ( .A(DMP_SHT2_EWSW[50]), .B(DMP_SFG[50]), .S0(n3171), .Y(n1456) );
INVX2TS U3916 ( .A(n3175), .Y(n3172) );
MX2X1TS U3917 ( .A(DMP_SHT2_EWSW[49]), .B(DMP_SFG[49]), .S0(n3172), .Y(n1459) );
MX2X1TS U3918 ( .A(DMP_SHT2_EWSW[48]), .B(DMP_SFG[48]), .S0(n3171), .Y(n1462) );
MX2X1TS U3919 ( .A(DMP_SHT2_EWSW[47]), .B(DMP_SFG[47]), .S0(n3172), .Y(n1465) );
MX2X1TS U3920 ( .A(DMP_SHT2_EWSW[46]), .B(DMP_SFG[46]), .S0(n3171), .Y(n1468) );
MX2X1TS U3921 ( .A(DMP_SHT2_EWSW[45]), .B(DMP_SFG[45]), .S0(n3171), .Y(n1471) );
MX2X1TS U3922 ( .A(DMP_SHT2_EWSW[44]), .B(DMP_SFG[44]), .S0(n3171), .Y(n1474) );
MX2X1TS U3923 ( .A(DMP_SHT2_EWSW[43]), .B(DMP_SFG[43]), .S0(n3171), .Y(n1477) );
MX2X1TS U3924 ( .A(DMP_SHT2_EWSW[42]), .B(DMP_SFG[42]), .S0(n3172), .Y(n1480) );
MX2X1TS U3925 ( .A(DMP_SHT2_EWSW[41]), .B(DMP_SFG[41]), .S0(n3171), .Y(n1483) );
MX2X1TS U3926 ( .A(DMP_SHT2_EWSW[40]), .B(DMP_SFG[40]), .S0(n3172), .Y(n1486) );
MX2X1TS U3927 ( .A(DMP_SHT2_EWSW[39]), .B(DMP_SFG[39]), .S0(n3171), .Y(n1489) );
MX2X1TS U3928 ( .A(DMP_SHT2_EWSW[38]), .B(DMP_SFG[38]), .S0(n3172), .Y(n1492) );
MX2X1TS U3929 ( .A(DMP_SHT2_EWSW[37]), .B(DMP_SFG[37]), .S0(n3172), .Y(n1495) );
INVX2TS U3930 ( .A(n3175), .Y(n3174) );
MX2X1TS U3931 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SFG[36]), .S0(n3174), .Y(n1498) );
MX2X1TS U3932 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SFG[35]), .S0(n3172), .Y(n1501) );
MX2X1TS U3933 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SHT1_EWSW[34]), .S0(n3173),
.Y(n1505) );
MX2X1TS U3934 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SFG[34]), .S0(n3172), .Y(n1504) );
MX2X1TS U3935 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SHT1_EWSW[33]), .S0(n3173),
.Y(n1508) );
MX2X1TS U3936 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SFG[33]), .S0(n3172), .Y(n1507) );
MX2X1TS U3937 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SHT1_EWSW[32]), .S0(n3173),
.Y(n1511) );
MX2X1TS U3938 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SFG[32]), .S0(n3172), .Y(n1510) );
MX2X1TS U3939 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SHT1_EWSW[31]), .S0(n3173),
.Y(n1514) );
MX2X1TS U3940 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SFG[31]), .S0(n3174), .Y(n1513) );
MX2X1TS U3941 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n3173),
.Y(n1517) );
MX2X1TS U3942 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SFG[30]), .S0(n3174), .Y(n1516) );
MX2X1TS U3943 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n3173),
.Y(n1520) );
MX2X1TS U3944 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SFG[29]), .S0(n3174), .Y(n1519) );
MX2X1TS U3945 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n3173),
.Y(n1523) );
MX2X1TS U3946 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SFG[28]), .S0(n3174), .Y(n1522) );
MX2X1TS U3947 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n3173),
.Y(n1526) );
MX2X1TS U3948 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SFG[27]), .S0(n3174), .Y(n1525) );
MX2X1TS U3949 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n3173),
.Y(n1529) );
MX2X1TS U3950 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SFG[26]), .S0(n3174), .Y(n1528) );
INVX2TS U3951 ( .A(n3968), .Y(n3176) );
MX2X1TS U3952 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SHT1_EWSW[25]), .S0(n3176),
.Y(n1532) );
MX2X1TS U3953 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SFG[25]), .S0(n3174), .Y(n1531) );
MX2X1TS U3954 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n3176),
.Y(n1535) );
MX2X1TS U3955 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SFG[24]), .S0(n3174), .Y(n1534) );
MX2X1TS U3956 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n3176),
.Y(n1538) );
MX2X1TS U3957 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SFG[23]), .S0(n3174), .Y(n1537) );
MX2X1TS U3958 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n3176),
.Y(n1541) );
INVX2TS U3959 ( .A(n3175), .Y(n3177) );
MX2X1TS U3960 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SFG[22]), .S0(n3177), .Y(n1540) );
MX2X1TS U3961 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n3176),
.Y(n1544) );
MX2X1TS U3962 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SFG[21]), .S0(n3177), .Y(n1543) );
MX2X1TS U3963 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n3176),
.Y(n1547) );
MX2X1TS U3964 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SFG[20]), .S0(n3177), .Y(n1546) );
MX2X1TS U3965 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n3176),
.Y(n1550) );
MX2X1TS U3966 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SFG[19]), .S0(n3177), .Y(n1549) );
MX2X1TS U3967 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n3176),
.Y(n1553) );
MX2X1TS U3968 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SFG[18]), .S0(n3177), .Y(n1552) );
MX2X1TS U3969 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n3176),
.Y(n1556) );
MX2X1TS U3970 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SFG[17]), .S0(n3177), .Y(n1555) );
MX2X1TS U3971 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n3176),
.Y(n1559) );
MX2X1TS U3972 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SFG[16]), .S0(n3177), .Y(n1558) );
INVX2TS U3973 ( .A(n3968), .Y(n3178) );
MX2X1TS U3974 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n3178),
.Y(n1562) );
MX2X1TS U3975 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SFG[15]), .S0(n3177), .Y(n1561) );
MX2X1TS U3976 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n3178),
.Y(n1565) );
MX2X1TS U3977 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SFG[14]), .S0(n3177), .Y(n1564) );
MX2X1TS U3978 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n3178),
.Y(n1568) );
MX2X1TS U3979 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SFG[13]), .S0(n3177), .Y(n1567) );
MX2X1TS U3980 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n3178),
.Y(n1571) );
INVX2TS U3981 ( .A(n3970), .Y(n3179) );
MX2X1TS U3982 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SFG[12]), .S0(n3179), .Y(n1570) );
MX2X1TS U3983 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n3178),
.Y(n1574) );
MX2X1TS U3984 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SFG[11]), .S0(n3179), .Y(n1573) );
MX2X1TS U3985 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n3178),
.Y(n1577) );
MX2X1TS U3986 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SFG[10]), .S0(n3179), .Y(n1576) );
MX2X1TS U3987 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n3178), .Y(
n1580) );
MX2X1TS U3988 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SFG[9]), .S0(n3179), .Y(n1579)
);
MX2X1TS U3989 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n3178), .Y(
n1583) );
MX2X1TS U3990 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SFG[8]), .S0(n3179), .Y(n1582)
);
MX2X1TS U3991 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n3178), .Y(
n1586) );
MX2X1TS U3992 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SFG[7]), .S0(n3179), .Y(n1585)
);
MX2X1TS U3993 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n3178), .Y(
n1589) );
MX2X1TS U3994 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SFG[6]), .S0(n3179), .Y(n1588)
);
INVX2TS U3995 ( .A(n3968), .Y(n3948) );
MX2X1TS U3996 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n3948), .Y(
n1592) );
MX2X1TS U3997 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SFG[5]), .S0(n3179), .Y(n1591)
);
MX2X1TS U3998 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n3948), .Y(
n1595) );
MX2X1TS U3999 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SFG[4]), .S0(n3179), .Y(n1594)
);
MX2X1TS U4000 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n3948), .Y(
n1598) );
MX2X1TS U4001 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SFG[3]), .S0(n3179), .Y(n1597)
);
MX2X1TS U4002 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n3948), .Y(
n1601) );
INVX2TS U4003 ( .A(n3970), .Y(n3827) );
MX2X1TS U4004 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SFG[2]), .S0(n3827), .Y(n1600)
);
MX2X1TS U4005 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n3948), .Y(
n1604) );
MX2X1TS U4006 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SFG[1]), .S0(n3827), .Y(n1603)
);
MX2X1TS U4007 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n3948), .Y(
n1607) );
MX2X1TS U4008 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SFG[0]), .S0(n3827), .Y(n1606)
);
MX2X1TS U4009 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SFG), .S0(n3827), .Y(n1277) );
CLKBUFX2TS U4010 ( .A(n3606), .Y(n3706) );
AOI22X1TS U4011 ( .A0(n3182), .A1(n3702), .B0(Raw_mant_NRM_SWR[33]), .B1(
n3971), .Y(n3183) );
OAI2BB1X1TS U4012 ( .A0N(n3706), .A1N(n3184), .B0(n3183), .Y(n1235) );
CLKBUFX2TS U4013 ( .A(n3606), .Y(n3282) );
AOI21X1TS U4014 ( .A0(n3521), .A1(n3189), .B0(n3188), .Y(n3507) );
INVX2TS U4015 ( .A(n3507), .Y(n3552) );
NAND2X1TS U4016 ( .A(n3192), .B(n3191), .Y(n3197) );
INVX2TS U4017 ( .A(n3197), .Y(n3193) );
XNOR2X1TS U4018 ( .A(n3552), .B(n3193), .Y(n3201) );
AOI21X1TS U4019 ( .A0(n3543), .A1(n3196), .B0(n3195), .Y(n3530) );
XNOR2X1TS U4020 ( .A(n3198), .B(n3197), .Y(n3199) );
CLKBUFX2TS U4021 ( .A(n3863), .Y(n3278) );
AOI22X1TS U4022 ( .A0(n3199), .A1(n3278), .B0(Raw_mant_NRM_SWR[21]), .B1(
n3971), .Y(n3200) );
OAI2BB1X1TS U4023 ( .A0N(n3282), .A1N(n3201), .B0(n3200), .Y(n1247) );
AOI21X1TS U4024 ( .A0(n3521), .A1(n3203), .B0(n3202), .Y(n3567) );
INVX2TS U4025 ( .A(n3567), .Y(n3600) );
AOI21X1TS U4026 ( .A0(n3600), .A1(n3207), .B0(n3206), .Y(n3212) );
NAND2X1TS U4027 ( .A(n3210), .B(n3209), .Y(n3215) );
INVX2TS U4028 ( .A(n3215), .Y(n3211) );
XOR2XLTS U4029 ( .A(n3212), .B(n3211), .Y(n3219) );
AOI21X1TS U4030 ( .A0(n3543), .A1(n3214), .B0(n3213), .Y(n3574) );
XNOR2X1TS U4031 ( .A(n3216), .B(n3215), .Y(n3217) );
AOI22X1TS U4032 ( .A0(n3217), .A1(n3863), .B0(Raw_mant_NRM_SWR[27]), .B1(
n3971), .Y(n3218) );
OAI2BB1X1TS U4033 ( .A0N(n3606), .A1N(n3219), .B0(n3218), .Y(n1241) );
AOI22X1TS U4034 ( .A0(n3222), .A1(n3278), .B0(Raw_mant_NRM_SWR[41]), .B1(
n3971), .Y(n3223) );
OAI2BB1X1TS U4035 ( .A0N(n3606), .A1N(n3224), .B0(n3223), .Y(n1227) );
AFHCONX2TS U4036 ( .A(DMP_SFG[38]), .B(n4129), .CI(n3225), .CON(n3220), .S(
n3230) );
CLKBUFX2TS U4037 ( .A(n4013), .Y(n3302) );
AOI22X1TS U4038 ( .A0(n3228), .A1(n3863), .B0(Raw_mant_NRM_SWR[40]), .B1(
n3302), .Y(n3229) );
OAI2BB1X1TS U4039 ( .A0N(n3606), .A1N(n3230), .B0(n3229), .Y(n1228) );
XNOR2X1TS U4040 ( .A(n4132), .B(DMP_SFG[37]), .Y(n3231) );
AOI22X1TS U4041 ( .A0(n3234), .A1(n3278), .B0(Raw_mant_NRM_SWR[39]), .B1(
n3971), .Y(n3235) );
OAI2BB1X1TS U4042 ( .A0N(n3282), .A1N(n3236), .B0(n3235), .Y(n1229) );
AOI22X1TS U4043 ( .A0(n3239), .A1(n3278), .B0(Raw_mant_NRM_SWR[37]), .B1(
n3971), .Y(n3240) );
OAI2BB1X1TS U4044 ( .A0N(n3282), .A1N(n3241), .B0(n3240), .Y(n1231) );
AFHCONX2TS U4045 ( .A(DMP_SFG[36]), .B(n4130), .CI(n3242), .CON(n3232), .S(
n3247) );
AOI22X1TS U4046 ( .A0(n3245), .A1(n3278), .B0(Raw_mant_NRM_SWR[38]), .B1(
n3302), .Y(n3246) );
OAI2BB1X1TS U4047 ( .A0N(n3282), .A1N(n3247), .B0(n3246), .Y(n1230) );
AFHCONX2TS U4048 ( .A(DMP_SFG[34]), .B(n4124), .CI(n3248), .CON(n3237), .S(
n3253) );
AOI22X1TS U4049 ( .A0(n3251), .A1(n3278), .B0(Raw_mant_NRM_SWR[36]), .B1(
n3302), .Y(n3252) );
OAI2BB1X1TS U4050 ( .A0N(n3282), .A1N(n3253), .B0(n3252), .Y(n1232) );
AOI22X1TS U4051 ( .A0(n3256), .A1(n3278), .B0(Raw_mant_NRM_SWR[35]), .B1(
n3302), .Y(n3257) );
OAI2BB1X1TS U4052 ( .A0N(n3282), .A1N(n3258), .B0(n3257), .Y(n1233) );
AFHCONX2TS U4053 ( .A(DMP_SFG[32]), .B(n4125), .CI(n3259), .CON(n3254), .S(
n3264) );
AOI22X1TS U4054 ( .A0(n3262), .A1(n3278), .B0(Raw_mant_NRM_SWR[34]), .B1(
n3302), .Y(n3263) );
OAI2BB1X1TS U4055 ( .A0N(n3282), .A1N(n3264), .B0(n3263), .Y(n1234) );
AFHCONX2TS U4056 ( .A(DMP_SFG[30]), .B(n4126), .CI(n3265), .CON(n3180), .S(
n3270) );
CLKBUFX2TS U4057 ( .A(n3863), .Y(n3443) );
AOI22X1TS U4058 ( .A0(n3268), .A1(n3443), .B0(Raw_mant_NRM_SWR[32]), .B1(
n3302), .Y(n3269) );
OAI2BB1X1TS U4059 ( .A0N(n3282), .A1N(n3270), .B0(n3269), .Y(n1236) );
AOI22X1TS U4060 ( .A0(n3273), .A1(n3278), .B0(Raw_mant_NRM_SWR[31]), .B1(
n3302), .Y(n3274) );
OAI2BB1X1TS U4061 ( .A0N(n3282), .A1N(n3275), .B0(n3274), .Y(n1237) );
AFHCONX2TS U4062 ( .A(DMP_SFG[28]), .B(n4121), .CI(n3276), .CON(n3271), .S(
n3281) );
AFHCONX2TS U4063 ( .A(DmP_mant_SFG_SWR[30]), .B(DMP_SFG[28]), .CI(n3277),
.CON(n3272), .S(n3279) );
CLKBUFX2TS U4064 ( .A(n4013), .Y(n3531) );
AOI22X1TS U4065 ( .A0(n3279), .A1(n3278), .B0(Raw_mant_NRM_SWR[30]), .B1(
n3531), .Y(n3280) );
OAI2BB1X1TS U4066 ( .A0N(n3282), .A1N(n3281), .B0(n3280), .Y(n1238) );
CLKBUFX2TS U4067 ( .A(n3606), .Y(n3420) );
AFHCINX2TS U4068 ( .CIN(n3284), .B(DMP_SFG[27]), .A(DmP_mant_SFG_SWR[29]),
.S(n3285), .CO(n3277) );
AOI22X1TS U4069 ( .A0(n3285), .A1(n3443), .B0(Raw_mant_NRM_SWR[29]), .B1(
n3302), .Y(n3286) );
OAI2BB1X1TS U4070 ( .A0N(n3420), .A1N(n3287), .B0(n3286), .Y(n1239) );
AFHCONX2TS U4071 ( .A(DMP_SFG[26]), .B(n4122), .CI(n3288), .CON(n3283), .S(
n3293) );
XOR2XLTS U4072 ( .A(DmP_mant_SFG_SWR[28]), .B(DMP_SFG[26]), .Y(n3289) );
AOI22X1TS U4073 ( .A0(n3291), .A1(n3443), .B0(Raw_mant_NRM_SWR[28]), .B1(
n3302), .Y(n3292) );
OAI2BB1X1TS U4074 ( .A0N(n3420), .A1N(n3293), .B0(n3292), .Y(n1240) );
CLKBUFX2TS U4075 ( .A(n4280), .Y(n3958) );
INVX2TS U4076 ( .A(n3958), .Y(n3549) );
MX2X1TS U4077 ( .A(DmP_mant_SHT1_SW[34]), .B(DmP_EXP_EWSW[34]), .S0(n3549),
.Y(n1328) );
INVX2TS U4078 ( .A(n3294), .Y(n3297) );
INVX2TS U4079 ( .A(n3295), .Y(n3296) );
AOI21X1TS U4080 ( .A0(n3521), .A1(n3297), .B0(n3296), .Y(n3300) );
INVX2TS U4081 ( .A(n3298), .Y(n3542) );
NAND2X1TS U4082 ( .A(n3542), .B(n3540), .Y(n3301) );
INVX2TS U4083 ( .A(n3301), .Y(n3299) );
XOR2XLTS U4084 ( .A(n3300), .B(n3299), .Y(n3305) );
XNOR2X1TS U4085 ( .A(n3543), .B(n3301), .Y(n3303) );
AOI22X1TS U4086 ( .A0(n3303), .A1(n3443), .B0(Raw_mant_NRM_SWR[18]), .B1(
n3302), .Y(n3304) );
OAI2BB1X1TS U4087 ( .A0N(n3420), .A1N(n3305), .B0(n3304), .Y(n1250) );
OAI21XLTS U4088 ( .A0(n3434), .A1(n3308), .B0(n3307), .Y(n3351) );
INVX2TS U4089 ( .A(n3351), .Y(n3367) );
INVX2TS U4090 ( .A(n3310), .Y(n3311) );
INVX2TS U4091 ( .A(n3313), .Y(n3336) );
INVX2TS U4092 ( .A(n3335), .Y(n3314) );
AOI21X1TS U4093 ( .A0(n3340), .A1(n3336), .B0(n3314), .Y(n3318) );
NAND2X1TS U4094 ( .A(n3317), .B(n3316), .Y(n3319) );
INVX2TS U4095 ( .A(n3319), .Y(n3320) );
XNOR2X1TS U4096 ( .A(n3521), .B(n3320), .Y(n3321) );
CLKBUFX2TS U4097 ( .A(n4013), .Y(n3435) );
AOI22X1TS U4098 ( .A0(n3321), .A1(n3706), .B0(Raw_mant_NRM_SWR[17]), .B1(
n3435), .Y(n3322) );
OAI2BB1X1TS U4099 ( .A0N(n3863), .A1N(n3323), .B0(n3322), .Y(n1251) );
MX2X1TS U4100 ( .A(DmP_mant_SHT1_SW[36]), .B(DmP_EXP_EWSW[36]), .S0(n3549),
.Y(n1324) );
INVX2TS U4101 ( .A(n3361), .Y(n3375) );
INVX2TS U4102 ( .A(n3328), .Y(n3329) );
INVX2TS U4103 ( .A(n3331), .Y(n3334) );
INVX2TS U4104 ( .A(n3332), .Y(n3333) );
AOI21X1TS U4105 ( .A0(n3348), .A1(n3334), .B0(n3333), .Y(n3338) );
NAND2X1TS U4106 ( .A(n3336), .B(n3335), .Y(n3339) );
INVX2TS U4107 ( .A(n3339), .Y(n3337) );
XOR2XLTS U4108 ( .A(n3338), .B(n3337), .Y(n3343) );
XNOR2X1TS U4109 ( .A(n3340), .B(n3339), .Y(n3341) );
AOI22X1TS U4110 ( .A0(n3341), .A1(n3443), .B0(Raw_mant_NRM_SWR[16]), .B1(
n3435), .Y(n3342) );
OAI2BB1X1TS U4111 ( .A0N(n3420), .A1N(n3343), .B0(n3342), .Y(n1252) );
NAND2X1TS U4112 ( .A(n3346), .B(n3345), .Y(n3352) );
INVX2TS U4113 ( .A(n3352), .Y(n3347) );
XNOR2X1TS U4114 ( .A(n3348), .B(n3347), .Y(n3356) );
CLKBUFX2TS U4115 ( .A(n3863), .Y(n3655) );
INVX2TS U4116 ( .A(n3349), .Y(n3363) );
INVX2TS U4117 ( .A(n3362), .Y(n3350) );
AOI21X1TS U4118 ( .A0(n3351), .A1(n3363), .B0(n3350), .Y(n3353) );
AOI22X1TS U4119 ( .A0(n3655), .A1(n3354), .B0(Raw_mant_NRM_SWR[15]), .B1(
n3435), .Y(n3355) );
OAI2BB1X1TS U4120 ( .A0N(n3420), .A1N(n3356), .B0(n3355), .Y(n1253) );
MX2X1TS U4121 ( .A(DmP_mant_SHT1_SW[38]), .B(DmP_EXP_EWSW[38]), .S0(n3549),
.Y(n1320) );
INVX2TS U4122 ( .A(n3357), .Y(n3360) );
INVX2TS U4123 ( .A(n3358), .Y(n3359) );
AOI21X1TS U4124 ( .A0(n3361), .A1(n3360), .B0(n3359), .Y(n3365) );
NAND2X1TS U4125 ( .A(n3363), .B(n3362), .Y(n3366) );
INVX2TS U4126 ( .A(n3366), .Y(n3364) );
XOR2XLTS U4127 ( .A(n3365), .B(n3364), .Y(n3370) );
AOI22X1TS U4128 ( .A0(n3702), .A1(n3368), .B0(Raw_mant_NRM_SWR[14]), .B1(
n3435), .Y(n3369) );
OAI2BB1X1TS U4129 ( .A0N(n3420), .A1N(n3370), .B0(n3369), .Y(n1254) );
INVX2TS U4130 ( .A(n3371), .Y(n3373) );
NAND2X1TS U4131 ( .A(n3373), .B(n3372), .Y(n3382) );
INVX2TS U4132 ( .A(n3382), .Y(n3374) );
XOR2XLTS U4133 ( .A(n3375), .B(n3374), .Y(n3386) );
INVX2TS U4134 ( .A(n3380), .Y(n3396) );
INVX2TS U4135 ( .A(n3395), .Y(n3381) );
AOI21X1TS U4136 ( .A0(n3400), .A1(n3396), .B0(n3381), .Y(n3383) );
AOI22X1TS U4137 ( .A0(n3655), .A1(n3384), .B0(Raw_mant_NRM_SWR[13]), .B1(
n3435), .Y(n3385) );
OAI2BB1X1TS U4138 ( .A0N(n3420), .A1N(n3386), .B0(n3385), .Y(n1255) );
MX2X1TS U4139 ( .A(DmP_mant_SHT1_SW[40]), .B(DmP_EXP_EWSW[40]), .S0(n3549),
.Y(n1316) );
INVX2TS U4140 ( .A(n3387), .Y(n3390) );
INVX2TS U4141 ( .A(n3388), .Y(n3389) );
OAI21XLTS U4142 ( .A0(n3451), .A1(n3390), .B0(n3389), .Y(n3414) );
INVX2TS U4143 ( .A(n3391), .Y(n3394) );
INVX2TS U4144 ( .A(n3392), .Y(n3393) );
AOI21X1TS U4145 ( .A0(n3414), .A1(n3394), .B0(n3393), .Y(n3398) );
NAND2X1TS U4146 ( .A(n3396), .B(n3395), .Y(n3399) );
INVX2TS U4147 ( .A(n3399), .Y(n3397) );
XOR2XLTS U4148 ( .A(n3398), .B(n3397), .Y(n3403) );
XNOR2X1TS U4149 ( .A(n3400), .B(n3399), .Y(n3401) );
AOI22X1TS U4150 ( .A0(n3401), .A1(n3443), .B0(Raw_mant_NRM_SWR[12]), .B1(
n3435), .Y(n3402) );
OAI2BB1X1TS U4151 ( .A0N(n3420), .A1N(n3403), .B0(n3402), .Y(n1256) );
AOI22X1TS U4152 ( .A0(n3407), .A1(n3443), .B0(Raw_mant_NRM_SWR[42]), .B1(
n3435), .Y(n3408) );
OAI2BB1X1TS U4153 ( .A0N(n3420), .A1N(n3409), .B0(n3408), .Y(n1226) );
INVX2TS U4154 ( .A(n3410), .Y(n3412) );
NAND2X1TS U4155 ( .A(n3412), .B(n3411), .Y(n3415) );
INVX2TS U4156 ( .A(n3415), .Y(n3413) );
XNOR2X1TS U4157 ( .A(n3414), .B(n3413), .Y(n3419) );
OAI21XLTS U4158 ( .A0(n3434), .A1(n3428), .B0(n3429), .Y(n3416) );
XNOR2X1TS U4159 ( .A(n3416), .B(n3415), .Y(n3417) );
AOI22X1TS U4160 ( .A0(n3417), .A1(n3443), .B0(Raw_mant_NRM_SWR[11]), .B1(
n3435), .Y(n3418) );
OAI2BB1X1TS U4161 ( .A0N(n3420), .A1N(n3419), .B0(n3418), .Y(n1257) );
AOI22X1TS U4162 ( .A0(n3423), .A1(n3443), .B0(Raw_mant_NRM_SWR[43]), .B1(
n3435), .Y(n3424) );
OAI2BB1X1TS U4163 ( .A0N(n3504), .A1N(n3425), .B0(n3424), .Y(n1225) );
MX2X1TS U4164 ( .A(DmP_mant_SHT1_SW[42]), .B(DmP_EXP_EWSW[42]), .S0(n3549),
.Y(n1312) );
INVX2TS U4165 ( .A(n3428), .Y(n3430) );
NAND2X1TS U4166 ( .A(n3430), .B(n3429), .Y(n3433) );
INVX2TS U4167 ( .A(n3433), .Y(n3431) );
XNOR2X1TS U4168 ( .A(n3432), .B(n3431), .Y(n3438) );
XOR2XLTS U4169 ( .A(n3434), .B(n3433), .Y(n3436) );
AOI22X1TS U4170 ( .A0(n3702), .A1(n3436), .B0(Raw_mant_NRM_SWR[10]), .B1(
n3435), .Y(n3437) );
OAI2BB1X1TS U4171 ( .A0N(n3504), .A1N(n3438), .B0(n3437), .Y(n1258) );
XNOR2X1TS U4172 ( .A(DmP_mant_SFG_SWR[44]), .B(DMP_SFG[42]), .Y(n3441) );
AOI22X1TS U4173 ( .A0(n3444), .A1(n3443), .B0(Raw_mant_NRM_SWR[44]), .B1(
n3531), .Y(n3445) );
OAI2BB1X1TS U4174 ( .A0N(n3504), .A1N(n3446), .B0(n3445), .Y(n1224) );
INVX2TS U4175 ( .A(n3447), .Y(n3449) );
NAND2X1TS U4176 ( .A(n3449), .B(n3448), .Y(n3455) );
INVX2TS U4177 ( .A(n3455), .Y(n3450) );
XOR2XLTS U4178 ( .A(n3451), .B(n3450), .Y(n3459) );
AOI21X1TS U4179 ( .A0(n3693), .A1(n3454), .B0(n3453), .Y(n3476) );
OAI21XLTS U4180 ( .A0(n3476), .A1(n3470), .B0(n3471), .Y(n3456) );
XNOR2X1TS U4181 ( .A(n3456), .B(n3455), .Y(n3457) );
AOI22X1TS U4182 ( .A0(n3457), .A1(n3674), .B0(Raw_mant_NRM_SWR[9]), .B1(
n3531), .Y(n3458) );
OAI2BB1X1TS U4183 ( .A0N(n3504), .A1N(n3459), .B0(n3458), .Y(n1259) );
AOI22X1TS U4184 ( .A0(n3462), .A1(n3674), .B0(Raw_mant_NRM_SWR[45]), .B1(
n3531), .Y(n3463) );
OAI2BB1X1TS U4185 ( .A0N(n3504), .A1N(n3464), .B0(n3463), .Y(n1223) );
MX2X1TS U4186 ( .A(DmP_mant_SHT1_SW[44]), .B(DmP_EXP_EWSW[44]), .S0(n3549),
.Y(n1308) );
AOI21X1TS U4187 ( .A0(n3687), .A1(n3467), .B0(n3466), .Y(n3491) );
OAI21XLTS U4188 ( .A0(n3491), .A1(n3469), .B0(n3468), .Y(n3474) );
INVX2TS U4189 ( .A(n3470), .Y(n3472) );
NAND2X1TS U4190 ( .A(n3472), .B(n3471), .Y(n3475) );
INVX2TS U4191 ( .A(n3475), .Y(n3473) );
XNOR2X1TS U4192 ( .A(n3474), .B(n3473), .Y(n3479) );
XOR2XLTS U4193 ( .A(n3476), .B(n3475), .Y(n3477) );
AOI22X1TS U4194 ( .A0(n3655), .A1(n3477), .B0(Raw_mant_NRM_SWR[8]), .B1(
n3531), .Y(n3478) );
OAI2BB1X1TS U4195 ( .A0N(n3504), .A1N(n3479), .B0(n3478), .Y(n1260) );
AOI22X1TS U4196 ( .A0(n3484), .A1(n3674), .B0(Raw_mant_NRM_SWR[46]), .B1(
n3531), .Y(n3485) );
OAI2BB1X1TS U4197 ( .A0N(n3504), .A1N(n3486), .B0(n3485), .Y(n1222) );
INVX2TS U4198 ( .A(n3487), .Y(n3489) );
NAND2X1TS U4199 ( .A(n3489), .B(n3488), .Y(n3494) );
INVX2TS U4200 ( .A(n3494), .Y(n3490) );
XOR2XLTS U4201 ( .A(n3491), .B(n3490), .Y(n3498) );
INVX2TS U4202 ( .A(n3492), .Y(n3689) );
INVX2TS U4203 ( .A(n3688), .Y(n3493) );
AOI21X1TS U4204 ( .A0(n3693), .A1(n3689), .B0(n3493), .Y(n3495) );
XOR2XLTS U4205 ( .A(n3495), .B(n3494), .Y(n3496) );
AOI22X1TS U4206 ( .A0(n3655), .A1(n3496), .B0(Raw_mant_NRM_SWR[7]), .B1(
n3531), .Y(n3497) );
OAI2BB1X1TS U4207 ( .A0N(n3504), .A1N(n3498), .B0(n3497), .Y(n1261) );
AOI22X1TS U4208 ( .A0(n3501), .A1(n3674), .B0(Raw_mant_NRM_SWR[47]), .B1(
n3531), .Y(n3502) );
OAI2BB1X1TS U4209 ( .A0N(n3504), .A1N(n3503), .B0(n3502), .Y(n1221) );
MX2X1TS U4210 ( .A(DmP_mant_SHT1_SW[30]), .B(DmP_EXP_EWSW[30]), .S0(n3549),
.Y(n1336) );
OAI21XLTS U4211 ( .A0(n3507), .A1(n3506), .B0(n3505), .Y(n3510) );
NAND2X1TS U4212 ( .A(n3508), .B(n3557), .Y(n3515) );
INVX2TS U4213 ( .A(n3515), .Y(n3509) );
XNOR2X1TS U4214 ( .A(n3510), .B(n3509), .Y(n3518) );
AOI21X1TS U4215 ( .A0(n3543), .A1(n3514), .B0(n3513), .Y(n3559) );
INVX2TS U4216 ( .A(n3559), .Y(n3586) );
XNOR2X1TS U4217 ( .A(n3586), .B(n3515), .Y(n3516) );
AOI22X1TS U4218 ( .A0(n3516), .A1(n3674), .B0(Raw_mant_NRM_SWR[22]), .B1(
n3531), .Y(n3517) );
OAI2BB1X1TS U4219 ( .A0N(n3629), .A1N(n3518), .B0(n3517), .Y(n1246) );
MX2X1TS U4220 ( .A(DmP_mant_SHT1_SW[32]), .B(DmP_EXP_EWSW[32]), .S0(n3549),
.Y(n1332) );
AOI21X1TS U4221 ( .A0(n3521), .A1(n3520), .B0(n3519), .Y(n3539) );
OAI21XLTS U4222 ( .A0(n3539), .A1(n3523), .B0(n3522), .Y(n3528) );
NAND2X1TS U4223 ( .A(n3526), .B(n3525), .Y(n3529) );
INVX2TS U4224 ( .A(n3529), .Y(n3527) );
XNOR2X1TS U4225 ( .A(n3528), .B(n3527), .Y(n3534) );
AOI22X1TS U4226 ( .A0(n3655), .A1(n3532), .B0(Raw_mant_NRM_SWR[20]), .B1(
n3531), .Y(n3533) );
OAI2BB1X1TS U4227 ( .A0N(n3629), .A1N(n3534), .B0(n3533), .Y(n1248) );
NAND2X1TS U4228 ( .A(n3537), .B(n3536), .Y(n3544) );
INVX2TS U4229 ( .A(n3544), .Y(n3538) );
XOR2XLTS U4230 ( .A(n3539), .B(n3538), .Y(n3548) );
INVX2TS U4231 ( .A(n3540), .Y(n3541) );
AOI21X1TS U4232 ( .A0(n3543), .A1(n3542), .B0(n3541), .Y(n3545) );
AOI22X1TS U4233 ( .A0(n3655), .A1(n3546), .B0(Raw_mant_NRM_SWR[19]), .B1(
n3653), .Y(n3547) );
OAI2BB1X1TS U4234 ( .A0N(n3629), .A1N(n3548), .B0(n3547), .Y(n1249) );
MX2X1TS U4235 ( .A(DmP_mant_SHT1_SW[18]), .B(DmP_EXP_EWSW[18]), .S0(n3549),
.Y(n1360) );
MX2X1TS U4236 ( .A(DmP_mant_SHT1_SW[20]), .B(DmP_EXP_EWSW[20]), .S0(n3549),
.Y(n1356) );
AOI21X1TS U4237 ( .A0(n3552), .A1(n3551), .B0(n3550), .Y(n3580) );
NAND2X1TS U4238 ( .A(n3555), .B(n3554), .Y(n3560) );
INVX2TS U4239 ( .A(n3560), .Y(n3556) );
XOR2XLTS U4240 ( .A(n3580), .B(n3556), .Y(n3564) );
XNOR2X1TS U4241 ( .A(n3561), .B(n3560), .Y(n3562) );
AOI22X1TS U4242 ( .A0(n3562), .A1(n3674), .B0(Raw_mant_NRM_SWR[23]), .B1(
n3653), .Y(n3563) );
OAI2BB1X1TS U4243 ( .A0N(n3629), .A1N(n3564), .B0(n3563), .Y(n1245) );
OAI21XLTS U4244 ( .A0(n3567), .A1(n3566), .B0(n3565), .Y(n3572) );
NAND2X1TS U4245 ( .A(n3570), .B(n3569), .Y(n3573) );
INVX2TS U4246 ( .A(n3573), .Y(n3571) );
XNOR2X1TS U4247 ( .A(n3572), .B(n3571), .Y(n3577) );
AOI22X1TS U4248 ( .A0(n3655), .A1(n3575), .B0(Raw_mant_NRM_SWR[26]), .B1(
n3653), .Y(n3576) );
OAI2BB1X1TS U4249 ( .A0N(n3629), .A1N(n3577), .B0(n3576), .Y(n1242) );
INVX2TS U4250 ( .A(n3958), .Y(n3604) );
MX2X1TS U4251 ( .A(DmP_mant_SHT1_SW[24]), .B(DmP_EXP_EWSW[24]), .S0(n3604),
.Y(n1348) );
MX2X1TS U4252 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n3604),
.Y(n1352) );
NAND2X1TS U4253 ( .A(n3581), .B(n3591), .Y(n3587) );
INVX2TS U4254 ( .A(n3587), .Y(n3582) );
XNOR2X1TS U4255 ( .A(n3583), .B(n3582), .Y(n3590) );
AOI21X1TS U4256 ( .A0(n3586), .A1(n3585), .B0(n3584), .Y(n3593) );
AOI22X1TS U4257 ( .A0(n3655), .A1(n3588), .B0(Raw_mant_NRM_SWR[24]), .B1(
n3653), .Y(n3589) );
OAI2BB1X1TS U4258 ( .A0N(n3629), .A1N(n3590), .B0(n3589), .Y(n1244) );
NAND2X1TS U4259 ( .A(n3596), .B(n3595), .Y(n3598) );
XNOR2X1TS U4260 ( .A(n3597), .B(n3598), .Y(n3603) );
INVX2TS U4261 ( .A(n3598), .Y(n3599) );
XNOR2X1TS U4262 ( .A(n3600), .B(n3599), .Y(n3601) );
AOI22X1TS U4263 ( .A0(n3601), .A1(n3706), .B0(Raw_mant_NRM_SWR[25]), .B1(
n3653), .Y(n3602) );
OAI2BB1X1TS U4264 ( .A0N(n3863), .A1N(n3603), .B0(n3602), .Y(n1243) );
MX2X1TS U4265 ( .A(DmP_mant_SHT1_SW[14]), .B(DmP_EXP_EWSW[14]), .S0(n3604),
.Y(n1368) );
MX2X1TS U4266 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n3604),
.Y(n1364) );
MX2X1TS U4267 ( .A(DmP_mant_SHT1_SW[27]), .B(DmP_EXP_EWSW[27]), .S0(n3604),
.Y(n1342) );
MX2X1TS U4268 ( .A(DmP_mant_SHT1_SW[28]), .B(DmP_EXP_EWSW[28]), .S0(n3604),
.Y(n1340) );
MX2X1TS U4269 ( .A(DmP_mant_SHT1_SW[29]), .B(DmP_EXP_EWSW[29]), .S0(n3604),
.Y(n1338) );
MX2X1TS U4270 ( .A(DmP_mant_SHT1_SW[6]), .B(DmP_EXP_EWSW[6]), .S0(n3604),
.Y(n1384) );
MX2X1TS U4271 ( .A(DmP_mant_SHT1_SW[8]), .B(DmP_EXP_EWSW[8]), .S0(n3604),
.Y(n1380) );
MX2X1TS U4272 ( .A(DmP_mant_SHT1_SW[10]), .B(DmP_EXP_EWSW[10]), .S0(n3604),
.Y(n1376) );
INVX2TS U4273 ( .A(n3958), .Y(n3709) );
MX2X1TS U4274 ( .A(DmP_mant_SHT1_SW[12]), .B(DmP_EXP_EWSW[12]), .S0(n3709),
.Y(n1372) );
XNOR2X1TS U4275 ( .A(DmP_mant_SFG_SWR[1]), .B(n4272), .Y(n3607) );
AOI22X1TS U4276 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n3674), .B0(n3701), .B1(
Raw_mant_NRM_SWR[1]), .Y(n3605) );
OAI2BB1X1TS U4277 ( .A0N(n3607), .A1N(n3606), .B0(n3605), .Y(n1267) );
ADDFHX2TS U4278 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .CI(n3610),
.CO(n2336), .S(n3611) );
AOI22X1TS U4279 ( .A0(n3611), .A1(n3674), .B0(Raw_mant_NRM_SWR[52]), .B1(
n3653), .Y(n3612) );
OAI2BB1X1TS U4280 ( .A0N(n3629), .A1N(n3613), .B0(n3612), .Y(n1216) );
OR2X1TS U4281 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n3614) );
CLKAND2X2TS U4282 ( .A(n3614), .B(n3624), .Y(n3616) );
XOR2XLTS U4283 ( .A(n3616), .B(n3615), .Y(n3618) );
AOI22X1TS U4284 ( .A0(n3616), .A1(n3702), .B0(Raw_mant_NRM_SWR[2]), .B1(
n3653), .Y(n3617) );
OAI2BB1X1TS U4285 ( .A0N(n3629), .A1N(n3618), .B0(n3617), .Y(n1266) );
MX2X1TS U4286 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n3709),
.Y(n1396) );
MX2X1TS U4287 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n3709),
.Y(n1394) );
INVX2TS U4288 ( .A(n3619), .Y(n3647) );
INVX2TS U4289 ( .A(n3620), .Y(n3622) );
NAND2X1TS U4290 ( .A(n3622), .B(n3621), .Y(n3625) );
INVX2TS U4291 ( .A(n3625), .Y(n3623) );
XOR2XLTS U4292 ( .A(n3647), .B(n3623), .Y(n3628) );
XOR2XLTS U4293 ( .A(n3625), .B(n3624), .Y(n3626) );
AOI22X1TS U4294 ( .A0(n3655), .A1(n3626), .B0(Raw_mant_NRM_SWR[3]), .B1(
n3653), .Y(n3627) );
OAI2BB1X1TS U4295 ( .A0N(n3629), .A1N(n3628), .B0(n3627), .Y(n1265) );
AFHCINX2TS U4296 ( .CIN(n3630), .B(n4214), .A(DMP_SFG[49]), .S(n3634), .CO(
n3609) );
AFHCINX2TS U4297 ( .CIN(n3631), .B(DMP_SFG[49]), .A(DmP_mant_SFG_SWR[51]),
.S(n3632), .CO(n3610) );
AOI22X1TS U4298 ( .A0(n3632), .A1(n3702), .B0(Raw_mant_NRM_SWR[51]), .B1(
n3701), .Y(n3633) );
OAI2BB1X1TS U4299 ( .A0N(n3706), .A1N(n3634), .B0(n3633), .Y(n1217) );
INVX2TS U4300 ( .A(n3635), .Y(n3643) );
AOI22X1TS U4301 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n3637), .B0(n3636), .B1(
Data_array_SWR[0]), .Y(n3638) );
MX2X1TS U4302 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n3709),
.Y(n1392) );
OAI21XLTS U4303 ( .A0(n3647), .A1(n3646), .B0(n3645), .Y(n3650) );
INVX2TS U4304 ( .A(n3670), .Y(n3648) );
NAND2X1TS U4305 ( .A(n3648), .B(n3669), .Y(n3652) );
INVX2TS U4306 ( .A(n3652), .Y(n3649) );
XNOR2X1TS U4307 ( .A(n3650), .B(n3649), .Y(n3657) );
INVX2TS U4308 ( .A(n3651), .Y(n3671) );
XOR2XLTS U4309 ( .A(n3671), .B(n3652), .Y(n3654) );
AOI22X1TS U4310 ( .A0(n3655), .A1(n3654), .B0(Raw_mant_NRM_SWR[4]), .B1(
n3653), .Y(n3656) );
OAI2BB1X1TS U4311 ( .A0N(n3706), .A1N(n3657), .B0(n3656), .Y(n1264) );
XNOR2X1TS U4312 ( .A(n4168), .B(DMP_SFG[48]), .Y(n3658) );
AOI22X1TS U4313 ( .A0(n3662), .A1(n3702), .B0(Raw_mant_NRM_SWR[50]), .B1(
n3701), .Y(n3663) );
OAI2BB1X1TS U4314 ( .A0N(n3706), .A1N(n3664), .B0(n3663), .Y(n1218) );
MX2X1TS U4315 ( .A(DmP_mant_SHT1_SW[3]), .B(DmP_EXP_EWSW[3]), .S0(n3709),
.Y(n1390) );
INVX2TS U4316 ( .A(n3665), .Y(n3667) );
NAND2X1TS U4317 ( .A(n3667), .B(n3666), .Y(n3672) );
INVX2TS U4318 ( .A(n3672), .Y(n3668) );
XNOR2X1TS U4319 ( .A(n3687), .B(n3668), .Y(n3677) );
XNOR2X1TS U4320 ( .A(n3673), .B(n3672), .Y(n3675) );
AOI22X1TS U4321 ( .A0(n3675), .A1(n3674), .B0(Raw_mant_NRM_SWR[5]), .B1(
n3701), .Y(n3676) );
OAI2BB1X1TS U4322 ( .A0N(n3706), .A1N(n3677), .B0(n3676), .Y(n1263) );
AOI22X1TS U4323 ( .A0(n3680), .A1(n3702), .B0(Raw_mant_NRM_SWR[49]), .B1(
n3701), .Y(n3681) );
OAI2BB1X1TS U4324 ( .A0N(n3706), .A1N(n3682), .B0(n3681), .Y(n1219) );
MX2X1TS U4325 ( .A(DmP_mant_SHT1_SW[4]), .B(DmP_EXP_EWSW[4]), .S0(n3709),
.Y(n1388) );
INVX2TS U4326 ( .A(n3683), .Y(n3686) );
INVX2TS U4327 ( .A(n3684), .Y(n3685) );
AOI21X1TS U4328 ( .A0(n3687), .A1(n3686), .B0(n3685), .Y(n3691) );
NAND2X1TS U4329 ( .A(n3689), .B(n3688), .Y(n3692) );
INVX2TS U4330 ( .A(n3692), .Y(n3690) );
XOR2XLTS U4331 ( .A(n3691), .B(n3690), .Y(n3696) );
XNOR2X1TS U4332 ( .A(n3693), .B(n3692), .Y(n3694) );
AOI22X1TS U4333 ( .A0(n3694), .A1(n3702), .B0(Raw_mant_NRM_SWR[6]), .B1(
n3701), .Y(n3695) );
OAI2BB1X1TS U4334 ( .A0N(n3706), .A1N(n3696), .B0(n3695), .Y(n1262) );
XNOR2X1TS U4335 ( .A(n4169), .B(DMP_SFG[46]), .Y(n3697) );
AOI22X1TS U4336 ( .A0(n3703), .A1(n3702), .B0(Raw_mant_NRM_SWR[48]), .B1(
n3701), .Y(n3704) );
OAI2BB1X1TS U4337 ( .A0N(n3706), .A1N(n3705), .B0(n3704), .Y(n1220) );
NAND2X1TS U4338 ( .A(DmP_EXP_EWSW[52]), .B(n4225), .Y(n3919) );
NAND2X1TS U4339 ( .A(DmP_EXP_EWSW[53]), .B(n4211), .Y(n3918) );
OAI21XLTS U4340 ( .A0(DmP_EXP_EWSW[53]), .A1(n4211), .B0(n3918), .Y(n3707)
);
XNOR2X1TS U4341 ( .A(n3919), .B(n3707), .Y(n3708) );
MX2X1TS U4342 ( .A(Shift_amount_SHT1_EWR[1]), .B(n3708), .S0(n3709), .Y(
n1690) );
MX2X1TS U4343 ( .A(DmP_mant_SHT1_SW[46]), .B(DmP_EXP_EWSW[46]), .S0(n3709),
.Y(n1304) );
MX2X1TS U4344 ( .A(DmP_mant_SHT1_SW[50]), .B(DmP_EXP_EWSW[50]), .S0(n3709),
.Y(n1296) );
MX2X1TS U4345 ( .A(DmP_mant_SHT1_SW[48]), .B(DmP_EXP_EWSW[48]), .S0(n3709),
.Y(n1300) );
AOI22X1TS U4346 ( .A0(Data_array_SWR[24]), .A1(n3738), .B0(
Data_array_SWR[28]), .B1(n3737), .Y(n3712) );
AOI22X1TS U4347 ( .A0(Data_array_SWR[32]), .A1(n1933), .B0(
Data_array_SWR[20]), .B1(n3710), .Y(n3711) );
NAND2X1TS U4348 ( .A(n3712), .B(n3711), .Y(n3786) );
AOI22X1TS U4349 ( .A0(Data_array_SWR[40]), .A1(n3738), .B0(
Data_array_SWR[44]), .B1(n3737), .Y(n3714) );
AOI22X1TS U4350 ( .A0(Data_array_SWR[36]), .A1(n3740), .B0(
Data_array_SWR[48]), .B1(n1932), .Y(n3713) );
NAND2X1TS U4351 ( .A(n3714), .B(n3713), .Y(n3824) );
AOI22X1TS U4352 ( .A0(n3806), .A1(n3786), .B0(n1936), .B1(n3824), .Y(n3718)
);
AOI22X1TS U4353 ( .A0(Data_array_SWR[16]), .A1(n3743), .B0(
Data_array_SWR[12]), .B1(n1922), .Y(n3716) );
AOI22X1TS U4354 ( .A0(Data_array_SWR[8]), .A1(n1934), .B0(Data_array_SWR[4]),
.B1(n1923), .Y(n3715) );
NOR2BX1TS U4355 ( .AN(n3718), .B(n3717), .Y(n3859) );
NAND2X1TS U4356 ( .A(n3720), .B(n3809), .Y(n3776) );
INVX2TS U4357 ( .A(n3776), .Y(n3803) );
NOR2X1TS U4358 ( .A(n3810), .B(n3832), .Y(n3774) );
AOI21X1TS U4359 ( .A0(n3803), .A1(n3855), .B0(n3774), .Y(n3719) );
MX2X1TS U4360 ( .A(n4009), .B(DmP_mant_SFG_SWR[50]), .S0(n3827), .Y(n1105)
);
AOI22X1TS U4361 ( .A0(Data_array_SWR[17]), .A1(n1912), .B0(Data_array_SWR[9]), .B1(n3768), .Y(n3722) );
AOI22X1TS U4362 ( .A0(Data_array_SWR[13]), .A1(n1921), .B0(Data_array_SWR[5]), .B1(n1923), .Y(n3721) );
OAI22X1TS U4363 ( .A0(n3724), .A1(n4238), .B0(n4075), .B1(n3723), .Y(n3725)
);
AOI21X1TS U4364 ( .A0(Data_array_SWR[25]), .A1(n3726), .B0(n3725), .Y(n3791)
);
AOI21X1TS U4365 ( .A0(n1936), .A1(n3793), .B0(n3731), .Y(n3853) );
AOI21X1TS U4366 ( .A0(n3803), .A1(n3851), .B0(n3774), .Y(n3732) );
AOI22X1TS U4367 ( .A0(Data_array_SWR[26]), .A1(n3734), .B0(
Data_array_SWR[30]), .B1(n3733), .Y(n3736) );
AOI22X1TS U4368 ( .A0(Data_array_SWR[22]), .A1(n3740), .B0(
Data_array_SWR[34]), .B1(n1932), .Y(n3735) );
NAND2X1TS U4369 ( .A(n3736), .B(n3735), .Y(n3798) );
AOI22X1TS U4370 ( .A0(Data_array_SWR[42]), .A1(n3738), .B0(
Data_array_SWR[46]), .B1(n3737), .Y(n3742) );
AOI22X1TS U4371 ( .A0(Data_array_SWR[38]), .A1(n3740), .B0(
Data_array_SWR[50]), .B1(n1933), .Y(n3741) );
NAND2X1TS U4372 ( .A(n3742), .B(n3741), .Y(n3829) );
AOI22X1TS U4373 ( .A0(n3806), .A1(n3798), .B0(n3782), .B1(n3829), .Y(n3748)
);
AOI22X1TS U4374 ( .A0(Data_array_SWR[18]), .A1(n3743), .B0(
Data_array_SWR[14]), .B1(n1921), .Y(n3745) );
AOI22X1TS U4375 ( .A0(Data_array_SWR[10]), .A1(n3768), .B0(Data_array_SWR[6]), .B1(n1924), .Y(n3744) );
NOR2BX1TS U4376 ( .AN(n3748), .B(n3747), .Y(n3849) );
AOI21X1TS U4377 ( .A0(n3803), .A1(n3847), .B0(n3774), .Y(n3749) );
OAI21XLTS U4378 ( .A0(n3849), .A1(n4194), .B0(n3749), .Y(n4000) );
MX2X1TS U4379 ( .A(n4000), .B(DmP_mant_SFG_SWR[48]), .S0(n3827), .Y(n1107)
);
AOI22X1TS U4380 ( .A0(Data_array_SWR[24]), .A1(n3743), .B0(
Data_array_SWR[20]), .B1(n1921), .Y(n3754) );
AOI22X1TS U4381 ( .A0(Data_array_SWR[16]), .A1(n1934), .B0(
Data_array_SWR[12]), .B1(n1924), .Y(n3753) );
AOI22X1TS U4382 ( .A0(n3806), .A1(n3751), .B0(n1936), .B1(n3750), .Y(n3752)
);
AOI21X1TS U4383 ( .A0(n3810), .A1(n3842), .B0(n3774), .Y(n3755) );
MX2X1TS U4384 ( .A(n3998), .B(DmP_mant_SFG_SWR[42]), .S0(n3827), .Y(n1113)
);
AOI22X1TS U4385 ( .A0(Data_array_SWR[25]), .A1(n1912), .B0(
Data_array_SWR[21]), .B1(n1922), .Y(n3760) );
AOI22X1TS U4386 ( .A0(Data_array_SWR[17]), .A1(n1934), .B0(
Data_array_SWR[13]), .B1(n1923), .Y(n3759) );
AOI22X1TS U4387 ( .A0(n3806), .A1(n3757), .B0(n1936), .B1(n3756), .Y(n3758)
);
AOI21X1TS U4388 ( .A0(left_right_SHT2), .A1(n3839), .B0(n3774), .Y(n3761) );
MX2X1TS U4389 ( .A(n3996), .B(DmP_mant_SFG_SWR[41]), .S0(n3860), .Y(n1114)
);
AOI22X1TS U4390 ( .A0(Data_array_SWR[26]), .A1(n1912), .B0(
Data_array_SWR[22]), .B1(n1922), .Y(n3766) );
AOI22X1TS U4391 ( .A0(Data_array_SWR[18]), .A1(n1934), .B0(
Data_array_SWR[14]), .B1(n1923), .Y(n3765) );
AOI22X1TS U4392 ( .A0(n3806), .A1(n3763), .B0(n1936), .B1(n3762), .Y(n3764)
);
AOI21X1TS U4393 ( .A0(n3810), .A1(n3836), .B0(n3774), .Y(n3767) );
MX2X1TS U4394 ( .A(n3994), .B(DmP_mant_SFG_SWR[40]), .S0(n3827), .Y(n1115)
);
AOI22X1TS U4395 ( .A0(Data_array_SWR[27]), .A1(n1912), .B0(
Data_array_SWR[23]), .B1(n1921), .Y(n3773) );
AOI22X1TS U4396 ( .A0(Data_array_SWR[15]), .A1(n1924), .B0(
Data_array_SWR[19]), .B1(n3768), .Y(n3772) );
AOI22X1TS U4397 ( .A0(n3806), .A1(n3770), .B0(n3782), .B1(n3769), .Y(n3771)
);
AOI21X1TS U4398 ( .A0(n3810), .A1(n3833), .B0(n3774), .Y(n3775) );
MX2X1TS U4399 ( .A(n3991), .B(DmP_mant_SFG_SWR[39]), .S0(n3860), .Y(n1116)
);
AOI22X1TS U4400 ( .A0(n3797), .A1(n3812), .B0(n3782), .B1(n3847), .Y(n3778)
);
AOI22X1TS U4401 ( .A0(n3858), .A1(n3828), .B0(n3803), .B1(n3829), .Y(n3780)
);
MX2X1TS U4402 ( .A(n3989), .B(DmP_mant_SFG_SWR[38]), .S0(n3860), .Y(n1117)
);
INVX2TS U4403 ( .A(n3788), .Y(n3781) );
AOI21X1TS U4404 ( .A0(n3806), .A1(n3781), .B0(n1900), .Y(n3826) );
AOI22X1TS U4405 ( .A0(n3797), .A1(n3820), .B0(n3782), .B1(n3855), .Y(n3783)
);
AOI22X1TS U4406 ( .A0(n3810), .A1(n3823), .B0(n3803), .B1(n3824), .Y(n3785)
);
MX2X1TS U4407 ( .A(n3987), .B(DmP_mant_SFG_SWR[36]), .S0(n3860), .Y(n1119)
);
AOI21X1TS U4408 ( .A0(n1906), .A1(n3855), .B0(n1900), .Y(n3822) );
AOI22X1TS U4409 ( .A0(n1902), .A1(n3786), .B0(n3797), .B1(n3824), .Y(n3787)
);
AOI22X1TS U4410 ( .A0(n3810), .A1(n3819), .B0(n3803), .B1(n3820), .Y(n3789)
);
MX2X1TS U4411 ( .A(n3985), .B(DmP_mant_SFG_SWR[34]), .S0(n3860), .Y(n1121)
);
OAI22X1TS U4412 ( .A0(n3791), .A1(n1903), .B0(n3802), .B1(n3790), .Y(n3792)
);
AOI21X1TS U4413 ( .A0(n1906), .A1(n3793), .B0(n3792), .Y(n3794) );
AOI21X1TS U4414 ( .A0(n1906), .A1(n3851), .B0(n1900), .Y(n3815) );
OAI2BB1X1TS U4415 ( .A0N(left_right_SHT2), .A1N(n3818), .B0(n3796), .Y(n3983) );
INVX2TS U4416 ( .A(n3970), .Y(n3850) );
MX2X1TS U4417 ( .A(n3983), .B(DmP_mant_SFG_SWR[33]), .S0(n3850), .Y(n1122)
);
AOI21X1TS U4418 ( .A0(n1906), .A1(n3847), .B0(n1900), .Y(n3814) );
AOI22X1TS U4419 ( .A0(n3809), .A1(n3798), .B0(n3797), .B1(n3829), .Y(n3800)
);
AOI22X1TS U4420 ( .A0(n3810), .A1(n3811), .B0(n3803), .B1(n3812), .Y(n3804)
);
MX2X1TS U4421 ( .A(n3981), .B(DmP_mant_SFG_SWR[32]), .S0(n3860), .Y(n1123)
);
AOI21X1TS U4422 ( .A0(n3806), .A1(n3805), .B0(n1900), .Y(n3807) );
OAI2BB1X1TS U4423 ( .A0N(n2370), .A1N(n3808), .B0(n3807), .Y(n3978) );
MX2X1TS U4424 ( .A(n3978), .B(DmP_mant_SFG_SWR[27]), .S0(n3860), .Y(n1128)
);
NAND2X1TS U4425 ( .A(n3810), .B(n1902), .Y(n3845) );
INVX2TS U4426 ( .A(n3845), .Y(n3856) );
AOI22X1TS U4427 ( .A0(n3856), .A1(n3812), .B0(n4194), .B1(n3811), .Y(n3813)
);
OAI21XLTS U4428 ( .A0(n3814), .A1(n4194), .B0(n3813), .Y(n3980) );
MX2X1TS U4429 ( .A(n3980), .B(DmP_mant_SFG_SWR[22]), .S0(n3850), .Y(n1133)
);
OAI2BB1X1TS U4430 ( .A0N(n4194), .A1N(n3818), .B0(n3817), .Y(n3982) );
MX2X1TS U4431 ( .A(n3982), .B(DmP_mant_SFG_SWR[21]), .S0(n3850), .Y(n1134)
);
AOI22X1TS U4432 ( .A0(n3856), .A1(n3820), .B0(n4194), .B1(n3819), .Y(n3821)
);
OAI21XLTS U4433 ( .A0(n3822), .A1(n4194), .B0(n3821), .Y(n3984) );
MX2X1TS U4434 ( .A(n3984), .B(DmP_mant_SFG_SWR[20]), .S0(n3850), .Y(n1135)
);
AOI22X1TS U4435 ( .A0(n3856), .A1(n3824), .B0(n3843), .B1(n3823), .Y(n3825)
);
OAI21XLTS U4436 ( .A0(n3826), .A1(n4194), .B0(n3825), .Y(n3986) );
MX2X1TS U4437 ( .A(n3986), .B(DmP_mant_SFG_SWR[18]), .S0(n3827), .Y(n1137)
);
AOI22X1TS U4438 ( .A0(n3856), .A1(n3829), .B0(n3843), .B1(n3828), .Y(n3830)
);
OAI21XLTS U4439 ( .A0(n3831), .A1(n4194), .B0(n3830), .Y(n3988) );
MX2X1TS U4440 ( .A(n3988), .B(DmP_mant_SFG_SWR[16]), .S0(n3850), .Y(n1139)
);
NOR2X1TS U4441 ( .A(n4194), .B(n3832), .Y(n3854) );
AOI21X1TS U4442 ( .A0(n3843), .A1(n3833), .B0(n3854), .Y(n3834) );
AOI21X1TS U4443 ( .A0(n3843), .A1(n3836), .B0(n3854), .Y(n3837) );
MX2X1TS U4444 ( .A(n3993), .B(DmP_mant_SFG_SWR[14]), .S0(n3850), .Y(n1141)
);
AOI21X1TS U4445 ( .A0(n3843), .A1(n3839), .B0(n3854), .Y(n3840) );
MX2X1TS U4446 ( .A(n3995), .B(DmP_mant_SFG_SWR[13]), .S0(n3850), .Y(n1142)
);
AOI21X1TS U4447 ( .A0(n3843), .A1(n3842), .B0(n3854), .Y(n3844) );
MX2X1TS U4448 ( .A(n3997), .B(DmP_mant_SFG_SWR[12]), .S0(n3850), .Y(n1143)
);
AOI21X1TS U4449 ( .A0(n3856), .A1(n3847), .B0(n3854), .Y(n3848) );
MX2X1TS U4450 ( .A(n3999), .B(DmP_mant_SFG_SWR[6]), .S0(n3850), .Y(n1149) );
AOI21X1TS U4451 ( .A0(n3856), .A1(n3851), .B0(n3854), .Y(n3852) );
AOI21X1TS U4452 ( .A0(n3856), .A1(n3855), .B0(n3854), .Y(n3857) );
MX2X1TS U4453 ( .A(n4007), .B(DmP_mant_SFG_SWR[4]), .S0(n3860), .Y(n1151) );
OAI21XLTS U4454 ( .A0(DmP_EXP_EWSW[52]), .A1(n4225), .B0(n3919), .Y(n3861)
);
CLKBUFX2TS U4455 ( .A(n3958), .Y(n3957) );
MX2X1TS U4456 ( .A(n3861), .B(Shift_amount_SHT1_EWR[0]), .S0(n3957), .Y(
n1691) );
MX2X1TS U4457 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(n3972),
.Y(n1398) );
MX2X1TS U4458 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n3865),
.Y(n1403) );
MX2X1TS U4459 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n3865),
.Y(n1408) );
MX2X1TS U4460 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n3865),
.Y(n1413) );
MX2X1TS U4461 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n3865),
.Y(n1418) );
MX2X1TS U4462 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n3865),
.Y(n1423) );
MX2X1TS U4463 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n3865),
.Y(n1428) );
MX2X1TS U4464 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n3865),
.Y(n1433) );
MX2X1TS U4465 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n3865),
.Y(n1438) );
MX2X1TS U4466 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n3972),
.Y(n1443) );
MX2X1TS U4467 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n3972),
.Y(n1448) );
OAI2BB1X1TS U4468 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n4271), .B0(n3869),
.Y(n1209) );
OA22X1TS U4469 ( .A0(n4001), .A1(n3873), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[55]), .Y(n1682) );
OA22X1TS U4470 ( .A0(n3977), .A1(n3874), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[56]), .Y(n1681) );
OA22X1TS U4471 ( .A0(n3977), .A1(n3877), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[59]), .Y(n1678) );
OA22X1TS U4472 ( .A0(n3977), .A1(n3878), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[60]), .Y(n1677) );
OA22X1TS U4473 ( .A0(n3977), .A1(n3879), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[61]), .Y(n1676) );
OA22X1TS U4474 ( .A0(n3977), .A1(n3880), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[62]), .Y(n1675) );
AOI22X1TS U4475 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3882), .B1(n4060), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U4476 ( .A(n3882), .B(n3881), .Y(n1891) );
AOI22X1TS U4477 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n3883), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n4060), .Y(n3888) );
OAI2BB2XLTS U4478 ( .B0(n3887), .B1(n3938), .A0N(n3887), .A1N(n3888), .Y(
n1889) );
INVX2TS U4479 ( .A(n3887), .Y(n3885) );
AOI22X1TS U4480 ( .A0(n3887), .A1(n3884), .B0(n4280), .B1(n3885), .Y(n1888)
);
OAI2BB2XLTS U4481 ( .B0(n3885), .B1(n3968), .A0N(n3885), .A1N(
Shift_reg_FLAGS_7[3]), .Y(n1886) );
AOI22X1TS U4482 ( .A0(n3887), .A1(n4271), .B0(n3886), .B1(n3885), .Y(n1883)
);
CLKBUFX2TS U4483 ( .A(n3891), .Y(n3907) );
INVX2TS U4484 ( .A(n3907), .Y(n3889) );
CLKBUFX2TS U4485 ( .A(n3891), .Y(n3898) );
AO22XLTS U4486 ( .A0(n3889), .A1(Data_X[0]), .B0(n3898), .B1(intDX_EWSW[0]),
.Y(n1882) );
CLKBUFX2TS U4487 ( .A(n3891), .Y(n3894) );
INVX2TS U4488 ( .A(n3894), .Y(n3913) );
CLKBUFX2TS U4489 ( .A(n3891), .Y(n3904) );
INVX2TS U4490 ( .A(n3904), .Y(n3914) );
OAI2BB2XLTS U4491 ( .B0(n3913), .B1(n4222), .A0N(n3914), .A1N(Data_X[1]),
.Y(n1881) );
AO22XLTS U4492 ( .A0(n3889), .A1(Data_X[2]), .B0(n3898), .B1(intDX_EWSW[2]),
.Y(n1880) );
INVX2TS U4493 ( .A(n3907), .Y(n3917) );
AO22XLTS U4494 ( .A0(n3917), .A1(Data_X[3]), .B0(n3898), .B1(intDX_EWSW[3]),
.Y(n1879) );
AO22XLTS U4495 ( .A0(n3917), .A1(Data_X[4]), .B0(n3904), .B1(intDX_EWSW[4]),
.Y(n1878) );
AO22XLTS U4496 ( .A0(n3917), .A1(Data_X[5]), .B0(n3904), .B1(intDX_EWSW[5]),
.Y(n1877) );
AO22XLTS U4497 ( .A0(n3889), .A1(Data_X[6]), .B0(n3904), .B1(intDX_EWSW[6]),
.Y(n1876) );
AO22XLTS U4498 ( .A0(n3917), .A1(Data_X[7]), .B0(n3907), .B1(intDX_EWSW[7]),
.Y(n1875) );
AO22XLTS U4499 ( .A0(n3889), .A1(Data_X[8]), .B0(n3907), .B1(intDX_EWSW[8]),
.Y(n1874) );
AO22XLTS U4500 ( .A0(n3889), .A1(Data_X[9]), .B0(n3907), .B1(intDX_EWSW[9]),
.Y(n1873) );
CLKBUFX2TS U4501 ( .A(n3891), .Y(n3916) );
CLKBUFX2TS U4502 ( .A(n3916), .Y(n3892) );
AO22XLTS U4503 ( .A0(n3889), .A1(Data_X[10]), .B0(n3892), .B1(intDX_EWSW[10]), .Y(n1872) );
AO22XLTS U4504 ( .A0(n3889), .A1(Data_X[11]), .B0(n3892), .B1(intDX_EWSW[11]), .Y(n1871) );
INVX2TS U4505 ( .A(n3892), .Y(n3890) );
AO22XLTS U4506 ( .A0(n3890), .A1(Data_X[12]), .B0(n3892), .B1(intDX_EWSW[12]), .Y(n1870) );
AO22XLTS U4507 ( .A0(n3889), .A1(Data_X[13]), .B0(n3894), .B1(intDX_EWSW[13]), .Y(n1869) );
AO22XLTS U4508 ( .A0(n3890), .A1(Data_X[14]), .B0(n3894), .B1(intDX_EWSW[14]), .Y(n1868) );
AO22XLTS U4509 ( .A0(n3917), .A1(Data_X[15]), .B0(n3894), .B1(intDX_EWSW[15]), .Y(n1867) );
CLKBUFX2TS U4510 ( .A(n3891), .Y(n3900) );
AO22XLTS U4511 ( .A0(n3890), .A1(Data_X[16]), .B0(n3900), .B1(intDX_EWSW[16]), .Y(n1866) );
AO22XLTS U4512 ( .A0(n3917), .A1(Data_X[17]), .B0(n3900), .B1(intDX_EWSW[17]), .Y(n1865) );
AO22XLTS U4513 ( .A0(n3889), .A1(Data_X[18]), .B0(n3900), .B1(intDX_EWSW[18]), .Y(n1864) );
CLKBUFX2TS U4514 ( .A(n3891), .Y(n3902) );
AO22XLTS U4515 ( .A0(n3917), .A1(Data_X[19]), .B0(n3902), .B1(intDX_EWSW[19]), .Y(n1863) );
AO22XLTS U4516 ( .A0(n3889), .A1(Data_X[20]), .B0(n3902), .B1(intDX_EWSW[20]), .Y(n1862) );
INVX2TS U4517 ( .A(n3894), .Y(n3896) );
AO22XLTS U4518 ( .A0(n3896), .A1(Data_X[21]), .B0(n3902), .B1(intDX_EWSW[21]), .Y(n1861) );
AO22XLTS U4519 ( .A0(n3917), .A1(Data_X[22]), .B0(n3902), .B1(intDX_EWSW[22]), .Y(n1860) );
INVX2TS U4520 ( .A(n3892), .Y(n3895) );
AO22XLTS U4521 ( .A0(n3895), .A1(Data_X[23]), .B0(n3902), .B1(intDX_EWSW[23]), .Y(n1859) );
AO22XLTS U4522 ( .A0(n3890), .A1(Data_X[24]), .B0(n3902), .B1(intDX_EWSW[24]), .Y(n1858) );
AO22XLTS U4523 ( .A0(n3895), .A1(Data_X[25]), .B0(n3902), .B1(intDX_EWSW[25]), .Y(n1857) );
AO22XLTS U4524 ( .A0(n3890), .A1(Data_X[26]), .B0(n3902), .B1(intDX_EWSW[26]), .Y(n1856) );
AO22XLTS U4525 ( .A0(n3890), .A1(Data_X[27]), .B0(n3894), .B1(intDX_EWSW[27]), .Y(n1855) );
AO22XLTS U4526 ( .A0(n3890), .A1(Data_X[28]), .B0(n3898), .B1(intDX_EWSW[28]), .Y(n1854) );
AO22XLTS U4527 ( .A0(n3890), .A1(Data_X[29]), .B0(n3904), .B1(intDX_EWSW[29]), .Y(n1853) );
AO22XLTS U4528 ( .A0(n3895), .A1(Data_X[30]), .B0(n3898), .B1(intDX_EWSW[30]), .Y(n1852) );
AO22XLTS U4529 ( .A0(n3890), .A1(Data_X[31]), .B0(n3904), .B1(intDX_EWSW[31]), .Y(n1851) );
AO22XLTS U4530 ( .A0(n3890), .A1(Data_X[32]), .B0(n3900), .B1(intDX_EWSW[32]), .Y(n1850) );
AO22XLTS U4531 ( .A0(n3895), .A1(Data_X[33]), .B0(n3900), .B1(intDX_EWSW[33]), .Y(n1849) );
INVX2TS U4532 ( .A(n3892), .Y(n3893) );
AO22XLTS U4533 ( .A0(n3893), .A1(Data_X[34]), .B0(n3900), .B1(intDX_EWSW[34]), .Y(n1848) );
AO22XLTS U4534 ( .A0(n3895), .A1(Data_X[35]), .B0(n3904), .B1(intDX_EWSW[35]), .Y(n1847) );
AO22XLTS U4535 ( .A0(n3895), .A1(Data_X[36]), .B0(n3900), .B1(intDX_EWSW[36]), .Y(n1846) );
AO22XLTS U4536 ( .A0(n3895), .A1(Data_X[37]), .B0(n3892), .B1(intDX_EWSW[37]), .Y(n1845) );
AO22XLTS U4537 ( .A0(n3895), .A1(Data_X[38]), .B0(n3916), .B1(intDX_EWSW[38]), .Y(n1844) );
AO22XLTS U4538 ( .A0(n3893), .A1(Data_X[39]), .B0(n3916), .B1(intDX_EWSW[39]), .Y(n1843) );
AO22XLTS U4539 ( .A0(n3895), .A1(Data_X[40]), .B0(n3916), .B1(intDX_EWSW[40]), .Y(n1842) );
AO22XLTS U4540 ( .A0(n3893), .A1(Data_X[41]), .B0(n3891), .B1(intDX_EWSW[41]), .Y(n1841) );
AO22XLTS U4541 ( .A0(n3893), .A1(Data_X[42]), .B0(n3891), .B1(intDX_EWSW[42]), .Y(n1840) );
AO22XLTS U4542 ( .A0(n3893), .A1(Data_X[43]), .B0(n3892), .B1(intDX_EWSW[43]), .Y(n1839) );
AO22XLTS U4543 ( .A0(n3893), .A1(Data_X[44]), .B0(n3891), .B1(intDX_EWSW[44]), .Y(n1838) );
AO22XLTS U4544 ( .A0(n3893), .A1(Data_X[45]), .B0(n3916), .B1(intDX_EWSW[45]), .Y(n1837) );
AO22XLTS U4545 ( .A0(n3893), .A1(Data_X[46]), .B0(n3892), .B1(intDX_EWSW[46]), .Y(n1836) );
AO22XLTS U4546 ( .A0(n3893), .A1(Data_X[47]), .B0(n3907), .B1(intDX_EWSW[47]), .Y(n1835) );
AO22XLTS U4547 ( .A0(n3896), .A1(Data_X[48]), .B0(n3894), .B1(intDX_EWSW[48]), .Y(n1834) );
AO22XLTS U4548 ( .A0(n3893), .A1(Data_X[49]), .B0(n3907), .B1(intDX_EWSW[49]), .Y(n1833) );
AO22XLTS U4549 ( .A0(n3896), .A1(Data_X[50]), .B0(n3907), .B1(intDX_EWSW[50]), .Y(n1832) );
AO22XLTS U4550 ( .A0(n3896), .A1(Data_X[51]), .B0(n3904), .B1(intDX_EWSW[51]), .Y(n1831) );
AO22XLTS U4551 ( .A0(n3896), .A1(Data_X[52]), .B0(n3894), .B1(intDX_EWSW[52]), .Y(n1830) );
INVX2TS U4552 ( .A(n3894), .Y(n3915) );
INVX2TS U4553 ( .A(n3898), .Y(n3897) );
OAI2BB2XLTS U4554 ( .B0(n3915), .B1(n4267), .A0N(n3897), .A1N(Data_X[53]),
.Y(n1829) );
OAI2BB2XLTS U4555 ( .B0(n3915), .B1(n4095), .A0N(n3897), .A1N(Data_X[54]),
.Y(n1828) );
OAI2BB2XLTS U4556 ( .B0(n3915), .B1(n4268), .A0N(n3897), .A1N(Data_X[55]),
.Y(n1827) );
OAI2BB2XLTS U4557 ( .B0(n3915), .B1(n4094), .A0N(n3897), .A1N(Data_X[56]),
.Y(n1826) );
AO22XLTS U4558 ( .A0(n3896), .A1(Data_X[57]), .B0(n3907), .B1(intDX_EWSW[57]), .Y(n1825) );
AO22XLTS U4559 ( .A0(n3896), .A1(Data_X[58]), .B0(n3898), .B1(intDX_EWSW[58]), .Y(n1824) );
AO22XLTS U4560 ( .A0(n3913), .A1(Data_X[59]), .B0(n3894), .B1(intDX_EWSW[59]), .Y(n1823) );
AO22XLTS U4561 ( .A0(n3896), .A1(Data_X[60]), .B0(n3898), .B1(intDX_EWSW[60]), .Y(n1822) );
AO22XLTS U4562 ( .A0(n3896), .A1(Data_X[61]), .B0(n3916), .B1(intDX_EWSW[61]), .Y(n1821) );
AO22XLTS U4563 ( .A0(n3913), .A1(Data_X[63]), .B0(n3916), .B1(intDX_EWSW[63]), .Y(n1819) );
AO22XLTS U4564 ( .A0(n3896), .A1(add_subt), .B0(n3916), .B1(intAS), .Y(n1818) );
OAI2BB2XLTS U4565 ( .B0(n3915), .B1(n4043), .A0N(n3897), .A1N(Data_Y[0]),
.Y(n1817) );
OAI2BB2XLTS U4566 ( .B0(n3913), .B1(n4210), .A0N(n3897), .A1N(Data_Y[1]),
.Y(n1816) );
OAI2BB2XLTS U4567 ( .B0(n3915), .B1(n4182), .A0N(n3897), .A1N(Data_Y[2]),
.Y(n1815) );
INVX2TS U4568 ( .A(n3898), .Y(n3901) );
OAI2BB2XLTS U4569 ( .B0(n3913), .B1(n4037), .A0N(n3901), .A1N(Data_Y[3]),
.Y(n1814) );
OAI2BB2XLTS U4570 ( .B0(n3913), .B1(n4052), .A0N(n3901), .A1N(Data_Y[4]),
.Y(n1813) );
OAI2BB2XLTS U4571 ( .B0(n3915), .B1(n4207), .A0N(n3901), .A1N(Data_Y[5]),
.Y(n1812) );
INVX2TS U4572 ( .A(n3900), .Y(n3911) );
OAI2BB2XLTS U4573 ( .B0(n3911), .B1(n4066), .A0N(n3901), .A1N(Data_Y[6]),
.Y(n1811) );
OAI2BB2XLTS U4574 ( .B0(n3911), .B1(n4219), .A0N(n3901), .A1N(Data_Y[7]),
.Y(n1810) );
OAI2BB2XLTS U4575 ( .B0(n3911), .B1(n4178), .A0N(n3901), .A1N(Data_Y[8]),
.Y(n1809) );
OAI2BB2XLTS U4576 ( .B0(n3911), .B1(n4174), .A0N(n3901), .A1N(Data_Y[9]),
.Y(n1808) );
OAI2BB2XLTS U4577 ( .B0(n3911), .B1(n4173), .A0N(n3897), .A1N(Data_Y[10]),
.Y(n1807) );
OAI2BB2XLTS U4578 ( .B0(n3911), .B1(n4061), .A0N(n3897), .A1N(Data_Y[11]),
.Y(n1806) );
INVX2TS U4579 ( .A(n3902), .Y(n3905) );
OAI2BB2XLTS U4580 ( .B0(n3905), .B1(n4175), .A0N(n3897), .A1N(Data_Y[12]),
.Y(n1805) );
INVX2TS U4581 ( .A(n3900), .Y(n3910) );
INVX2TS U4582 ( .A(n3898), .Y(n3899) );
OAI2BB2XLTS U4583 ( .B0(n3910), .B1(n4171), .A0N(n3899), .A1N(Data_Y[13]),
.Y(n1804) );
OAI2BB2XLTS U4584 ( .B0(n3910), .B1(n4216), .A0N(n3899), .A1N(Data_Y[14]),
.Y(n1803) );
OAI2BB2XLTS U4585 ( .B0(n3910), .B1(n4062), .A0N(n3899), .A1N(Data_Y[15]),
.Y(n1802) );
OAI2BB2XLTS U4586 ( .B0(n3910), .B1(n4193), .A0N(n3899), .A1N(Data_Y[16]),
.Y(n1801) );
OAI2BB2XLTS U4587 ( .B0(n3910), .B1(n4039), .A0N(n3899), .A1N(Data_Y[17]),
.Y(n1800) );
OAI2BB2XLTS U4588 ( .B0(n3910), .B1(n4179), .A0N(n3899), .A1N(Data_Y[18]),
.Y(n1799) );
OAI2BB2XLTS U4589 ( .B0(n3911), .B1(n4041), .A0N(n3899), .A1N(Data_Y[19]),
.Y(n1798) );
INVX2TS U4590 ( .A(n3900), .Y(n3909) );
OAI2BB2XLTS U4591 ( .B0(n3909), .B1(n4176), .A0N(n3901), .A1N(Data_Y[20]),
.Y(n1797) );
OAI2BB2XLTS U4592 ( .B0(n3909), .B1(n4172), .A0N(n3901), .A1N(Data_Y[21]),
.Y(n1796) );
OAI2BB2XLTS U4593 ( .B0(n3909), .B1(n4217), .A0N(n3901), .A1N(Data_Y[22]),
.Y(n1795) );
INVX2TS U4594 ( .A(n3904), .Y(n3903) );
OAI2BB2XLTS U4595 ( .B0(n3909), .B1(n4063), .A0N(n3903), .A1N(Data_Y[23]),
.Y(n1794) );
OAI2BB2XLTS U4596 ( .B0(n3909), .B1(n4181), .A0N(n3903), .A1N(Data_Y[24]),
.Y(n1793) );
OAI2BB2XLTS U4597 ( .B0(n3909), .B1(n4040), .A0N(n3903), .A1N(Data_Y[25]),
.Y(n1792) );
INVX2TS U4598 ( .A(n3902), .Y(n3908) );
OAI2BB2XLTS U4599 ( .B0(n3908), .B1(n4180), .A0N(n3903), .A1N(Data_Y[26]),
.Y(n1791) );
OAI2BB2XLTS U4600 ( .B0(n3908), .B1(n4042), .A0N(n3903), .A1N(Data_Y[27]),
.Y(n1790) );
OAI2BB2XLTS U4601 ( .B0(n3908), .B1(n4177), .A0N(n3903), .A1N(Data_Y[28]),
.Y(n1789) );
OAI2BB2XLTS U4602 ( .B0(n3908), .B1(n4038), .A0N(n3903), .A1N(Data_Y[29]),
.Y(n1788) );
OAI2BB2XLTS U4603 ( .B0(n3908), .B1(n4218), .A0N(n3903), .A1N(Data_Y[30]),
.Y(n1787) );
OAI2BB2XLTS U4604 ( .B0(n3908), .B1(n4064), .A0N(n3903), .A1N(Data_Y[31]),
.Y(n1786) );
OAI2BB2XLTS U4605 ( .B0(n3909), .B1(n4183), .A0N(n3903), .A1N(Data_Y[32]),
.Y(n1785) );
INVX2TS U4606 ( .A(n3904), .Y(n3906) );
OAI2BB2XLTS U4607 ( .B0(n3905), .B1(n4054), .A0N(n3906), .A1N(Data_Y[33]),
.Y(n1784) );
OAI2BB2XLTS U4608 ( .B0(n3905), .B1(n4199), .A0N(n3906), .A1N(Data_Y[34]),
.Y(n1783) );
OAI2BB2XLTS U4609 ( .B0(n3905), .B1(n4055), .A0N(n3906), .A1N(Data_Y[35]),
.Y(n1782) );
OAI2BB2XLTS U4610 ( .B0(n3905), .B1(n4196), .A0N(n3906), .A1N(Data_Y[36]),
.Y(n1781) );
OAI2BB2XLTS U4611 ( .B0(n3905), .B1(n4204), .A0N(n3906), .A1N(Data_Y[37]),
.Y(n1780) );
OAI2BB2XLTS U4612 ( .B0(n3905), .B1(n4205), .A0N(n3906), .A1N(Data_Y[38]),
.Y(n1779) );
OAI2BB2XLTS U4613 ( .B0(n3908), .B1(n4201), .A0N(n3906), .A1N(Data_Y[39]),
.Y(n1778) );
OAI2BB2XLTS U4614 ( .B0(n3913), .B1(n4202), .A0N(n3906), .A1N(Data_Y[40]),
.Y(n1777) );
OAI2BB2XLTS U4615 ( .B0(n3905), .B1(n4058), .A0N(n3906), .A1N(Data_Y[41]),
.Y(n1776) );
OAI2BB2XLTS U4616 ( .B0(n3905), .B1(n4200), .A0N(n3914), .A1N(Data_Y[42]),
.Y(n1775) );
OAI2BB2XLTS U4617 ( .B0(n3905), .B1(n4056), .A0N(n3914), .A1N(Data_Y[43]),
.Y(n1774) );
OAI2BB2XLTS U4618 ( .B0(n3908), .B1(n4197), .A0N(n3906), .A1N(Data_Y[44]),
.Y(n1773) );
OAI2BB2XLTS U4619 ( .B0(n3908), .B1(n4195), .A0N(n3914), .A1N(Data_Y[45]),
.Y(n1772) );
INVX2TS U4620 ( .A(n3907), .Y(n3912) );
OAI2BB2XLTS U4621 ( .B0(n3908), .B1(n4057), .A0N(n3912), .A1N(Data_Y[46]),
.Y(n1771) );
OAI2BB2XLTS U4622 ( .B0(n3910), .B1(n4203), .A0N(n3914), .A1N(Data_Y[47]),
.Y(n1770) );
OAI2BB2XLTS U4623 ( .B0(n3909), .B1(n4192), .A0N(n3912), .A1N(Data_Y[48]),
.Y(n1769) );
OAI2BB2XLTS U4624 ( .B0(n3909), .B1(n4208), .A0N(n3912), .A1N(Data_Y[49]),
.Y(n1768) );
OAI2BB2XLTS U4625 ( .B0(n3909), .B1(n4059), .A0N(n3914), .A1N(Data_Y[50]),
.Y(n1767) );
OAI2BB2XLTS U4626 ( .B0(n3910), .B1(n4198), .A0N(n3912), .A1N(Data_Y[51]),
.Y(n1766) );
OAI2BB2XLTS U4627 ( .B0(n3910), .B1(n4220), .A0N(n3912), .A1N(Data_Y[52]),
.Y(n1765) );
OAI2BB2XLTS U4628 ( .B0(n3910), .B1(n4053), .A0N(n3914), .A1N(Data_Y[53]),
.Y(n1764) );
OAI2BB2XLTS U4629 ( .B0(n3911), .B1(n4036), .A0N(n3912), .A1N(Data_Y[54]),
.Y(n1763) );
OAI2BB2XLTS U4630 ( .B0(n3911), .B1(n4012), .A0N(n3912), .A1N(Data_Y[55]),
.Y(n1762) );
OAI2BB2XLTS U4631 ( .B0(n3911), .B1(n4014), .A0N(n3914), .A1N(Data_Y[56]),
.Y(n1761) );
OAI2BB2XLTS U4632 ( .B0(n3915), .B1(n4206), .A0N(n3912), .A1N(Data_Y[57]),
.Y(n1760) );
OAI2BB2XLTS U4633 ( .B0(n3913), .B1(n4045), .A0N(n3912), .A1N(Data_Y[58]),
.Y(n1759) );
OAI2BB2XLTS U4634 ( .B0(n3913), .B1(n4213), .A0N(n3914), .A1N(Data_Y[59]),
.Y(n1758) );
OAI2BB2XLTS U4635 ( .B0(n3913), .B1(n4184), .A0N(n3912), .A1N(Data_Y[60]),
.Y(n1757) );
OAI2BB2XLTS U4636 ( .B0(n3915), .B1(n4215), .A0N(n3914), .A1N(Data_Y[61]),
.Y(n1756) );
OAI2BB2XLTS U4637 ( .B0(n3915), .B1(n4209), .A0N(n3917), .A1N(Data_Y[62]),
.Y(n1755) );
AO22XLTS U4638 ( .A0(n3917), .A1(Data_Y[63]), .B0(n3916), .B1(intDY_EWSW[63]), .Y(n1754) );
INVX2TS U4639 ( .A(n3957), .Y(n3941) );
AOI22X1TS U4640 ( .A0(DMP_EXP_EWSW[53]), .A1(n4228), .B0(n3919), .B1(n3918),
.Y(n3922) );
AOI21X1TS U4641 ( .A0(DMP_EXP_EWSW[54]), .A1(n4223), .B0(n3923), .Y(n3920)
);
XNOR2X1TS U4642 ( .A(n3922), .B(n3920), .Y(n3921) );
AO22XLTS U4643 ( .A0(n3941), .A1(n3921), .B0(n3966), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1689) );
OAI22X1TS U4644 ( .A0(n3923), .A1(n3922), .B0(DmP_EXP_EWSW[54]), .B1(n4224),
.Y(n3926) );
NAND2X1TS U4645 ( .A(DmP_EXP_EWSW[55]), .B(n4212), .Y(n3927) );
XNOR2X1TS U4646 ( .A(n3926), .B(n3924), .Y(n3925) );
AO22XLTS U4647 ( .A0(n3941), .A1(n3925), .B0(n3966), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1688) );
AOI22X1TS U4648 ( .A0(DMP_EXP_EWSW[55]), .A1(n4270), .B0(n3927), .B1(n3926),
.Y(n3930) );
AOI21X1TS U4649 ( .A0(DMP_EXP_EWSW[56]), .A1(n4266), .B0(n3931), .Y(n3928)
);
XNOR2X1TS U4650 ( .A(n3930), .B(n3928), .Y(n3929) );
AO22XLTS U4651 ( .A0(n3941), .A1(n3929), .B0(n3966), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1687) );
OAI22X1TS U4652 ( .A0(n3931), .A1(n3930), .B0(DmP_EXP_EWSW[56]), .B1(n4269),
.Y(n3933) );
XNOR2X1TS U4653 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n3932) );
XOR2XLTS U4654 ( .A(n3933), .B(n3932), .Y(n3934) );
AO22XLTS U4655 ( .A0(n3941), .A1(n3934), .B0(n3966), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1686) );
INVX2TS U4656 ( .A(n3935), .Y(n3937) );
OAI21XLTS U4657 ( .A0(n3937), .A1(intDX_EWSW[63]), .B0(Shift_reg_FLAGS_7_6),
.Y(n3936) );
AOI21X1TS U4658 ( .A0(n3937), .A1(intDX_EWSW[63]), .B0(n3936), .Y(n3939) );
AO21XLTS U4659 ( .A0(OP_FLAG_EXP), .A1(n3938), .B0(n3939), .Y(n1611) );
AO22XLTS U4660 ( .A0(n3940), .A1(n3939), .B0(ZERO_FLAG_EXP), .B1(n3938), .Y(
n1610) );
AO22XLTS U4661 ( .A0(n3941), .A1(DMP_EXP_EWSW[0]), .B0(n3966), .B1(
DMP_SHT1_EWSW[0]), .Y(n1608) );
CLKBUFX2TS U4662 ( .A(n3964), .Y(n3962) );
CLKBUFX2TS U4663 ( .A(n3962), .Y(n3943) );
AO22XLTS U4664 ( .A0(n3941), .A1(DMP_EXP_EWSW[1]), .B0(n3943), .B1(
DMP_SHT1_EWSW[1]), .Y(n1605) );
AO22XLTS U4665 ( .A0(n3941), .A1(DMP_EXP_EWSW[2]), .B0(n3943), .B1(
DMP_SHT1_EWSW[2]), .Y(n1602) );
AO22XLTS U4666 ( .A0(n3941), .A1(DMP_EXP_EWSW[3]), .B0(n3966), .B1(
DMP_SHT1_EWSW[3]), .Y(n1599) );
AO22XLTS U4667 ( .A0(n3941), .A1(DMP_EXP_EWSW[4]), .B0(n3943), .B1(
DMP_SHT1_EWSW[4]), .Y(n1596) );
AO22XLTS U4668 ( .A0(n3941), .A1(DMP_EXP_EWSW[5]), .B0(n3966), .B1(
DMP_SHT1_EWSW[5]), .Y(n1593) );
INVX2TS U4669 ( .A(n3957), .Y(n3942) );
AO22XLTS U4670 ( .A0(n3942), .A1(DMP_EXP_EWSW[6]), .B0(n3943), .B1(
DMP_SHT1_EWSW[6]), .Y(n1590) );
AO22XLTS U4671 ( .A0(n3942), .A1(DMP_EXP_EWSW[7]), .B0(n3966), .B1(
DMP_SHT1_EWSW[7]), .Y(n1587) );
AO22XLTS U4672 ( .A0(n3942), .A1(DMP_EXP_EWSW[8]), .B0(n3943), .B1(
DMP_SHT1_EWSW[8]), .Y(n1584) );
AO22XLTS U4673 ( .A0(n3942), .A1(DMP_EXP_EWSW[9]), .B0(n3943), .B1(
DMP_SHT1_EWSW[9]), .Y(n1581) );
AO22XLTS U4674 ( .A0(n3942), .A1(DMP_EXP_EWSW[10]), .B0(n3943), .B1(
DMP_SHT1_EWSW[10]), .Y(n1578) );
CLKBUFX2TS U4675 ( .A(n3962), .Y(n3945) );
AO22XLTS U4676 ( .A0(n3942), .A1(DMP_EXP_EWSW[11]), .B0(n3945), .B1(
DMP_SHT1_EWSW[11]), .Y(n1575) );
AO22XLTS U4677 ( .A0(n3942), .A1(DMP_EXP_EWSW[12]), .B0(n3945), .B1(
DMP_SHT1_EWSW[12]), .Y(n1572) );
AO22XLTS U4678 ( .A0(n3942), .A1(DMP_EXP_EWSW[13]), .B0(n3943), .B1(
DMP_SHT1_EWSW[13]), .Y(n1569) );
AO22XLTS U4679 ( .A0(n3942), .A1(DMP_EXP_EWSW[14]), .B0(n3945), .B1(
DMP_SHT1_EWSW[14]), .Y(n1566) );
AO22XLTS U4680 ( .A0(n3942), .A1(DMP_EXP_EWSW[15]), .B0(n3943), .B1(
DMP_SHT1_EWSW[15]), .Y(n1563) );
INVX2TS U4681 ( .A(n3957), .Y(n3944) );
AO22XLTS U4682 ( .A0(n3944), .A1(DMP_EXP_EWSW[16]), .B0(n3945), .B1(
DMP_SHT1_EWSW[16]), .Y(n1560) );
AO22XLTS U4683 ( .A0(n3944), .A1(DMP_EXP_EWSW[17]), .B0(n3943), .B1(
DMP_SHT1_EWSW[17]), .Y(n1557) );
AO22XLTS U4684 ( .A0(n3944), .A1(DMP_EXP_EWSW[18]), .B0(n3945), .B1(
DMP_SHT1_EWSW[18]), .Y(n1554) );
AO22XLTS U4685 ( .A0(n3944), .A1(DMP_EXP_EWSW[19]), .B0(n3945), .B1(
DMP_SHT1_EWSW[19]), .Y(n1551) );
AO22XLTS U4686 ( .A0(n3944), .A1(DMP_EXP_EWSW[20]), .B0(n3945), .B1(
DMP_SHT1_EWSW[20]), .Y(n1548) );
CLKBUFX2TS U4687 ( .A(n3962), .Y(n3946) );
AO22XLTS U4688 ( .A0(n3944), .A1(DMP_EXP_EWSW[21]), .B0(n3946), .B1(
DMP_SHT1_EWSW[21]), .Y(n1545) );
AO22XLTS U4689 ( .A0(n3944), .A1(DMP_EXP_EWSW[22]), .B0(n3946), .B1(
DMP_SHT1_EWSW[22]), .Y(n1542) );
CLKBUFX2TS U4690 ( .A(n4280), .Y(n3949) );
AO22XLTS U4691 ( .A0(n3944), .A1(DMP_EXP_EWSW[23]), .B0(n3949), .B1(
DMP_SHT1_EWSW[23]), .Y(n1539) );
AO22XLTS U4692 ( .A0(n3944), .A1(DMP_EXP_EWSW[24]), .B0(n3946), .B1(
DMP_SHT1_EWSW[24]), .Y(n1536) );
AO22XLTS U4693 ( .A0(n3944), .A1(DMP_EXP_EWSW[25]), .B0(n3945), .B1(
DMP_SHT1_EWSW[25]), .Y(n1533) );
AO22XLTS U4694 ( .A0(n3947), .A1(DMP_EXP_EWSW[26]), .B0(n3946), .B1(
DMP_SHT1_EWSW[26]), .Y(n1530) );
AO22XLTS U4695 ( .A0(n3947), .A1(DMP_EXP_EWSW[27]), .B0(n3945), .B1(
DMP_SHT1_EWSW[27]), .Y(n1527) );
AO22XLTS U4696 ( .A0(n3947), .A1(DMP_EXP_EWSW[28]), .B0(n3945), .B1(
DMP_SHT1_EWSW[28]), .Y(n1524) );
AO22XLTS U4697 ( .A0(n3947), .A1(DMP_EXP_EWSW[29]), .B0(n3946), .B1(
DMP_SHT1_EWSW[29]), .Y(n1521) );
AO22XLTS U4698 ( .A0(n3947), .A1(DMP_EXP_EWSW[30]), .B0(n3946), .B1(
DMP_SHT1_EWSW[30]), .Y(n1518) );
AO22XLTS U4699 ( .A0(n3947), .A1(DMP_EXP_EWSW[31]), .B0(n3946), .B1(
DMP_SHT1_EWSW[31]), .Y(n1515) );
AO22XLTS U4700 ( .A0(n3947), .A1(DMP_EXP_EWSW[32]), .B0(n3946), .B1(
DMP_SHT1_EWSW[32]), .Y(n1512) );
AO22XLTS U4701 ( .A0(n3947), .A1(DMP_EXP_EWSW[33]), .B0(n3946), .B1(
DMP_SHT1_EWSW[33]), .Y(n1509) );
AO22XLTS U4702 ( .A0(n3947), .A1(DMP_EXP_EWSW[34]), .B0(n3946), .B1(
DMP_SHT1_EWSW[34]), .Y(n1506) );
AO22XLTS U4703 ( .A0(n3947), .A1(DMP_EXP_EWSW[35]), .B0(n3949), .B1(
DMP_SHT1_EWSW[35]), .Y(n1503) );
AO22XLTS U4704 ( .A0(n3948), .A1(DMP_SHT1_EWSW[35]), .B0(n4276), .B1(
DMP_SHT2_EWSW[35]), .Y(n1502) );
AO22XLTS U4705 ( .A0(n3950), .A1(DMP_EXP_EWSW[36]), .B0(n3949), .B1(
DMP_SHT1_EWSW[36]), .Y(n1500) );
AO22XLTS U4706 ( .A0(n3948), .A1(DMP_SHT1_EWSW[36]), .B0(n3968), .B1(
DMP_SHT2_EWSW[36]), .Y(n1499) );
AO22XLTS U4707 ( .A0(n3950), .A1(DMP_EXP_EWSW[37]), .B0(n3949), .B1(
DMP_SHT1_EWSW[37]), .Y(n1497) );
AO22XLTS U4708 ( .A0(n3948), .A1(DMP_SHT1_EWSW[37]), .B0(n3968), .B1(
DMP_SHT2_EWSW[37]), .Y(n1496) );
AO22XLTS U4709 ( .A0(n3950), .A1(DMP_EXP_EWSW[38]), .B0(n3949), .B1(
DMP_SHT1_EWSW[38]), .Y(n1494) );
AO22XLTS U4710 ( .A0(n3948), .A1(DMP_SHT1_EWSW[38]), .B0(n3951), .B1(
DMP_SHT2_EWSW[38]), .Y(n1493) );
AO22XLTS U4711 ( .A0(n3950), .A1(DMP_EXP_EWSW[39]), .B0(n3949), .B1(
DMP_SHT1_EWSW[39]), .Y(n1491) );
INVX2TS U4712 ( .A(n3968), .Y(n3952) );
AO22XLTS U4713 ( .A0(n3952), .A1(DMP_SHT1_EWSW[39]), .B0(n3951), .B1(
DMP_SHT2_EWSW[39]), .Y(n1490) );
AO22XLTS U4714 ( .A0(n3950), .A1(DMP_EXP_EWSW[40]), .B0(n3949), .B1(
DMP_SHT1_EWSW[40]), .Y(n1488) );
AO22XLTS U4715 ( .A0(n3952), .A1(DMP_SHT1_EWSW[40]), .B0(n3951), .B1(
DMP_SHT2_EWSW[40]), .Y(n1487) );
AO22XLTS U4716 ( .A0(n3950), .A1(DMP_EXP_EWSW[41]), .B0(n3949), .B1(
DMP_SHT1_EWSW[41]), .Y(n1485) );
AO22XLTS U4717 ( .A0(n3952), .A1(DMP_SHT1_EWSW[41]), .B0(n3951), .B1(
DMP_SHT2_EWSW[41]), .Y(n1484) );
AO22XLTS U4718 ( .A0(n3950), .A1(DMP_EXP_EWSW[42]), .B0(n3949), .B1(
DMP_SHT1_EWSW[42]), .Y(n1482) );
AO22XLTS U4719 ( .A0(n3952), .A1(DMP_SHT1_EWSW[42]), .B0(n3951), .B1(
DMP_SHT2_EWSW[42]), .Y(n1481) );
AO22XLTS U4720 ( .A0(n3950), .A1(DMP_EXP_EWSW[43]), .B0(n3949), .B1(
DMP_SHT1_EWSW[43]), .Y(n1479) );
AO22XLTS U4721 ( .A0(n3952), .A1(DMP_SHT1_EWSW[43]), .B0(n3951), .B1(
DMP_SHT2_EWSW[43]), .Y(n1478) );
CLKBUFX2TS U4722 ( .A(n3962), .Y(n3955) );
AO22XLTS U4723 ( .A0(n3950), .A1(DMP_EXP_EWSW[44]), .B0(n3955), .B1(
DMP_SHT1_EWSW[44]), .Y(n1476) );
CLKBUFX2TS U4724 ( .A(n4276), .Y(n3954) );
AO22XLTS U4725 ( .A0(n3952), .A1(DMP_SHT1_EWSW[44]), .B0(n3954), .B1(
DMP_SHT2_EWSW[44]), .Y(n1475) );
AO22XLTS U4726 ( .A0(n3950), .A1(DMP_EXP_EWSW[45]), .B0(n3955), .B1(
DMP_SHT1_EWSW[45]), .Y(n1473) );
AO22XLTS U4727 ( .A0(n3952), .A1(DMP_SHT1_EWSW[45]), .B0(n3951), .B1(
DMP_SHT2_EWSW[45]), .Y(n1472) );
AO22XLTS U4728 ( .A0(n3956), .A1(DMP_EXP_EWSW[46]), .B0(n3955), .B1(
DMP_SHT1_EWSW[46]), .Y(n1470) );
AO22XLTS U4729 ( .A0(n3952), .A1(DMP_SHT1_EWSW[46]), .B0(n3951), .B1(
DMP_SHT2_EWSW[46]), .Y(n1469) );
AO22XLTS U4730 ( .A0(n3956), .A1(DMP_EXP_EWSW[47]), .B0(n3955), .B1(
DMP_SHT1_EWSW[47]), .Y(n1467) );
AO22XLTS U4731 ( .A0(n3952), .A1(DMP_SHT1_EWSW[47]), .B0(n3954), .B1(
DMP_SHT2_EWSW[47]), .Y(n1466) );
AO22XLTS U4732 ( .A0(n3956), .A1(DMP_EXP_EWSW[48]), .B0(n3955), .B1(
DMP_SHT1_EWSW[48]), .Y(n1464) );
AO22XLTS U4733 ( .A0(n3952), .A1(DMP_SHT1_EWSW[48]), .B0(n3954), .B1(
DMP_SHT2_EWSW[48]), .Y(n1463) );
AO22XLTS U4734 ( .A0(n3956), .A1(DMP_EXP_EWSW[49]), .B0(n3955), .B1(
DMP_SHT1_EWSW[49]), .Y(n1461) );
AO22XLTS U4735 ( .A0(n1943), .A1(DMP_SHT1_EWSW[49]), .B0(n3954), .B1(
DMP_SHT2_EWSW[49]), .Y(n1460) );
AO22XLTS U4736 ( .A0(n3956), .A1(DMP_EXP_EWSW[50]), .B0(n3955), .B1(
DMP_SHT1_EWSW[50]), .Y(n1458) );
AO22XLTS U4737 ( .A0(n1943), .A1(DMP_SHT1_EWSW[50]), .B0(n3954), .B1(
DMP_SHT2_EWSW[50]), .Y(n1457) );
AO22XLTS U4738 ( .A0(n3956), .A1(DMP_EXP_EWSW[51]), .B0(n3955), .B1(
DMP_SHT1_EWSW[51]), .Y(n1455) );
AO22XLTS U4739 ( .A0(n1943), .A1(DMP_SHT1_EWSW[51]), .B0(n3954), .B1(
DMP_SHT2_EWSW[51]), .Y(n1454) );
OAI2BB2XLTS U4740 ( .B0(n4280), .B1(n4225), .A0N(n3962), .A1N(
DMP_SHT1_EWSW[52]), .Y(n1452) );
AO22XLTS U4741 ( .A0(n1943), .A1(DMP_SHT1_EWSW[52]), .B0(n3954), .B1(
DMP_SHT2_EWSW[52]), .Y(n1451) );
AO22XLTS U4742 ( .A0(n3953), .A1(DMP_SHT2_EWSW[52]), .B0(n3969), .B1(
DMP_SFG[52]), .Y(n1450) );
AO22XLTS U4743 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[52]), .B0(n3971),
.B1(DMP_exp_NRM_EW[0]), .Y(n1449) );
OAI2BB2XLTS U4744 ( .B0(n3958), .B1(n4211), .A0N(n3964), .A1N(
DMP_SHT1_EWSW[53]), .Y(n1447) );
AO22XLTS U4745 ( .A0(n1943), .A1(DMP_SHT1_EWSW[53]), .B0(n3954), .B1(
DMP_SHT2_EWSW[53]), .Y(n1446) );
AO22XLTS U4746 ( .A0(n3953), .A1(DMP_SHT2_EWSW[53]), .B0(n3969), .B1(
DMP_SFG[53]), .Y(n1445) );
AO22XLTS U4747 ( .A0(n1910), .A1(DMP_SFG[53]), .B0(n1909), .B1(
DMP_exp_NRM_EW[1]), .Y(n1444) );
OAI2BB2XLTS U4748 ( .B0(n3958), .B1(n4224), .A0N(n3964), .A1N(
DMP_SHT1_EWSW[54]), .Y(n1442) );
AO22XLTS U4749 ( .A0(n1943), .A1(DMP_SHT1_EWSW[54]), .B0(n3954), .B1(
DMP_SHT2_EWSW[54]), .Y(n1441) );
AO22XLTS U4750 ( .A0(n3953), .A1(DMP_SHT2_EWSW[54]), .B0(n3963), .B1(
DMP_SFG[54]), .Y(n1440) );
AO22XLTS U4751 ( .A0(n1910), .A1(DMP_SFG[54]), .B0(n1909), .B1(
DMP_exp_NRM_EW[2]), .Y(n1439) );
OAI2BB2XLTS U4752 ( .B0(n3957), .B1(n4212), .A0N(n3964), .A1N(
DMP_SHT1_EWSW[55]), .Y(n1437) );
AO22XLTS U4753 ( .A0(n1943), .A1(DMP_SHT1_EWSW[55]), .B0(n3954), .B1(
DMP_SHT2_EWSW[55]), .Y(n1436) );
AO22XLTS U4754 ( .A0(n3953), .A1(DMP_SHT2_EWSW[55]), .B0(n3969), .B1(
DMP_SFG[55]), .Y(n1435) );
AO22XLTS U4755 ( .A0(n1910), .A1(DMP_SFG[55]), .B0(n1909), .B1(
DMP_exp_NRM_EW[3]), .Y(n1434) );
OAI2BB2XLTS U4756 ( .B0(n3957), .B1(n4269), .A0N(n3962), .A1N(
DMP_SHT1_EWSW[56]), .Y(n1432) );
CLKBUFX2TS U4757 ( .A(n4276), .Y(n3965) );
AO22XLTS U4758 ( .A0(n1943), .A1(DMP_SHT1_EWSW[56]), .B0(n3965), .B1(
DMP_SHT2_EWSW[56]), .Y(n1431) );
AO22XLTS U4759 ( .A0(n3953), .A1(DMP_SHT2_EWSW[56]), .B0(n3969), .B1(
DMP_SFG[56]), .Y(n1430) );
AO22XLTS U4760 ( .A0(n1910), .A1(DMP_SFG[56]), .B0(n1909), .B1(
DMP_exp_NRM_EW[4]), .Y(n1429) );
AO22XLTS U4761 ( .A0(n3956), .A1(DMP_EXP_EWSW[57]), .B0(n3955), .B1(
DMP_SHT1_EWSW[57]), .Y(n1427) );
AO22XLTS U4762 ( .A0(n1943), .A1(DMP_SHT1_EWSW[57]), .B0(n3965), .B1(
DMP_SHT2_EWSW[57]), .Y(n1426) );
AO22XLTS U4763 ( .A0(n3953), .A1(DMP_SHT2_EWSW[57]), .B0(n3969), .B1(
DMP_SFG[57]), .Y(n1425) );
AO22XLTS U4764 ( .A0(n1910), .A1(DMP_SFG[57]), .B0(n1909), .B1(
DMP_exp_NRM_EW[5]), .Y(n1424) );
CLKBUFX2TS U4765 ( .A(n4280), .Y(n3959) );
AO22XLTS U4766 ( .A0(n3956), .A1(DMP_EXP_EWSW[58]), .B0(n3959), .B1(
DMP_SHT1_EWSW[58]), .Y(n1422) );
AO22XLTS U4767 ( .A0(n1943), .A1(DMP_SHT1_EWSW[58]), .B0(n3965), .B1(
DMP_SHT2_EWSW[58]), .Y(n1421) );
AO22XLTS U4768 ( .A0(n3953), .A1(DMP_SHT2_EWSW[58]), .B0(n3963), .B1(
DMP_SFG[58]), .Y(n1420) );
AO22XLTS U4769 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[58]), .B0(n1909),
.B1(DMP_exp_NRM_EW[6]), .Y(n1419) );
AO22XLTS U4770 ( .A0(n3956), .A1(DMP_EXP_EWSW[59]), .B0(n3955), .B1(
DMP_SHT1_EWSW[59]), .Y(n1417) );
AO22XLTS U4771 ( .A0(busy), .A1(DMP_SHT1_EWSW[59]), .B0(n3965), .B1(
DMP_SHT2_EWSW[59]), .Y(n1416) );
AO22XLTS U4772 ( .A0(n3953), .A1(DMP_SHT2_EWSW[59]), .B0(n3963), .B1(
DMP_SFG[59]), .Y(n1415) );
AO22XLTS U4773 ( .A0(n1910), .A1(DMP_SFG[59]), .B0(n1909), .B1(
DMP_exp_NRM_EW[7]), .Y(n1414) );
AO22XLTS U4774 ( .A0(n3956), .A1(DMP_EXP_EWSW[60]), .B0(n3959), .B1(
DMP_SHT1_EWSW[60]), .Y(n1412) );
AO22XLTS U4775 ( .A0(busy), .A1(DMP_SHT1_EWSW[60]), .B0(n3965), .B1(
DMP_SHT2_EWSW[60]), .Y(n1411) );
AO22XLTS U4776 ( .A0(n3953), .A1(DMP_SHT2_EWSW[60]), .B0(n3963), .B1(
DMP_SFG[60]), .Y(n1410) );
AO22XLTS U4777 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[60]), .B0(n4013),
.B1(DMP_exp_NRM_EW[8]), .Y(n1409) );
INVX2TS U4778 ( .A(n3957), .Y(n3967) );
AO22XLTS U4779 ( .A0(n3967), .A1(DMP_EXP_EWSW[61]), .B0(n3959), .B1(
DMP_SHT1_EWSW[61]), .Y(n1407) );
AO22XLTS U4780 ( .A0(busy), .A1(DMP_SHT1_EWSW[61]), .B0(n3965), .B1(
DMP_SHT2_EWSW[61]), .Y(n1406) );
AO22XLTS U4781 ( .A0(n3953), .A1(DMP_SHT2_EWSW[61]), .B0(n3963), .B1(
DMP_SFG[61]), .Y(n1405) );
AO22XLTS U4782 ( .A0(n1910), .A1(DMP_SFG[61]), .B0(n1909), .B1(
DMP_exp_NRM_EW[9]), .Y(n1404) );
AO22XLTS U4783 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[62]), .B0(n3959),
.B1(DMP_SHT1_EWSW[62]), .Y(n1402) );
AO22XLTS U4784 ( .A0(busy), .A1(DMP_SHT1_EWSW[62]), .B0(n3965), .B1(
DMP_SHT2_EWSW[62]), .Y(n1401) );
AO22XLTS U4785 ( .A0(n3175), .A1(DMP_SHT2_EWSW[62]), .B0(n3963), .B1(
DMP_SFG[62]), .Y(n1400) );
AO22XLTS U4786 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[62]), .B0(n4013),
.B1(DMP_exp_NRM_EW[10]), .Y(n1399) );
AO22XLTS U4787 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[5]), .B0(n3959),
.B1(DmP_mant_SHT1_SW[5]), .Y(n1386) );
AO22XLTS U4788 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[7]), .B0(n3959),
.B1(DmP_mant_SHT1_SW[7]), .Y(n1382) );
AO22XLTS U4789 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[9]), .B0(n3959),
.B1(DmP_mant_SHT1_SW[9]), .Y(n1378) );
AO22XLTS U4790 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[11]), .B0(n3959),
.B1(DmP_mant_SHT1_SW[11]), .Y(n1374) );
AO22XLTS U4791 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[13]), .B0(n3959),
.B1(DmP_mant_SHT1_SW[13]), .Y(n1370) );
CLKBUFX2TS U4792 ( .A(n3962), .Y(n3960) );
AO22XLTS U4793 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[15]), .B0(n3960),
.B1(DmP_mant_SHT1_SW[15]), .Y(n1366) );
AO22XLTS U4794 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[17]), .B0(n3960),
.B1(DmP_mant_SHT1_SW[17]), .Y(n1362) );
AO22XLTS U4795 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[19]), .B0(n3960),
.B1(DmP_mant_SHT1_SW[19]), .Y(n1358) );
AO22XLTS U4796 ( .A0(n3961), .A1(DmP_EXP_EWSW[21]), .B0(n3959), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1354) );
AO22XLTS U4797 ( .A0(n3961), .A1(DmP_EXP_EWSW[23]), .B0(n3960), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1350) );
AO22XLTS U4798 ( .A0(n3961), .A1(DmP_EXP_EWSW[25]), .B0(n3960), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1346) );
AO22XLTS U4799 ( .A0(n3961), .A1(DmP_EXP_EWSW[26]), .B0(n3960), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1344) );
AO22XLTS U4800 ( .A0(n3961), .A1(DmP_EXP_EWSW[31]), .B0(n3960), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1334) );
AO22XLTS U4801 ( .A0(n3961), .A1(DmP_EXP_EWSW[33]), .B0(n3960), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1330) );
AO22XLTS U4802 ( .A0(n3961), .A1(DmP_EXP_EWSW[35]), .B0(n3960), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1326) );
AO22XLTS U4803 ( .A0(n3961), .A1(DmP_EXP_EWSW[37]), .B0(n3962), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1322) );
AO22XLTS U4804 ( .A0(n3961), .A1(DmP_EXP_EWSW[39]), .B0(n3960), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1318) );
AO22XLTS U4805 ( .A0(n3961), .A1(DmP_EXP_EWSW[41]), .B0(n3962), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1314) );
AO22XLTS U4806 ( .A0(n3967), .A1(DmP_EXP_EWSW[43]), .B0(n3964), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1310) );
AO22XLTS U4807 ( .A0(n3967), .A1(DmP_EXP_EWSW[45]), .B0(n3964), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1306) );
AO22XLTS U4808 ( .A0(n3967), .A1(DmP_EXP_EWSW[47]), .B0(n3962), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1302) );
AO22XLTS U4809 ( .A0(n3967), .A1(DmP_EXP_EWSW[49]), .B0(n3964), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1298) );
AO22XLTS U4810 ( .A0(n3967), .A1(DmP_EXP_EWSW[51]), .B0(n3964), .B1(
DmP_mant_SHT1_SW[51]), .Y(n1294) );
CLKBUFX2TS U4811 ( .A(n3979), .Y(n4004) );
OA21XLTS U4812 ( .A0(n1935), .A1(overflow_flag), .B0(n3975), .Y(n1286) );
AO22XLTS U4813 ( .A0(n3967), .A1(ZERO_FLAG_EXP), .B0(n3964), .B1(
ZERO_FLAG_SHT1), .Y(n1285) );
AO22XLTS U4814 ( .A0(busy), .A1(ZERO_FLAG_SHT1), .B0(n3965), .B1(
ZERO_FLAG_SHT2), .Y(n1284) );
AO22XLTS U4815 ( .A0(n3970), .A1(ZERO_FLAG_SHT2), .B0(n3963), .B1(
ZERO_FLAG_SFG), .Y(n1283) );
AO22XLTS U4816 ( .A0(n1910), .A1(ZERO_FLAG_SFG), .B0(n4013), .B1(
ZERO_FLAG_NRM), .Y(n1282) );
AO22XLTS U4817 ( .A0(n3972), .A1(ZERO_FLAG_NRM), .B0(n4271), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1281) );
AO22XLTS U4818 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n4004), .B1(zero_flag), .Y(n1280) );
AO22XLTS U4819 ( .A0(n3967), .A1(OP_FLAG_EXP), .B0(n3964), .B1(OP_FLAG_SHT1),
.Y(n1279) );
AO22XLTS U4820 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(n3965), .B1(OP_FLAG_SHT2),
.Y(n1278) );
AO22XLTS U4821 ( .A0(n3967), .A1(SIGN_FLAG_EXP), .B0(n3966), .B1(
SIGN_FLAG_SHT1), .Y(n1274) );
AO22XLTS U4822 ( .A0(busy), .A1(SIGN_FLAG_SHT1), .B0(n3968), .B1(
SIGN_FLAG_SHT2), .Y(n1273) );
AO22XLTS U4823 ( .A0(n3970), .A1(SIGN_FLAG_SHT2), .B0(n3969), .B1(
SIGN_FLAG_SFG), .Y(n1272) );
AO22XLTS U4824 ( .A0(n1910), .A1(SIGN_FLAG_SFG), .B0(n3971), .B1(
SIGN_FLAG_NRM), .Y(n1271) );
AO22XLTS U4825 ( .A0(n3972), .A1(SIGN_FLAG_NRM), .B0(n4271), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1270) );
NOR2XLTS U4826 ( .A(n3973), .B(SIGN_FLAG_SHT1SHT2), .Y(n3976) );
OAI2BB2XLTS U4827 ( .B0(n3976), .B1(n3975), .A0N(final_result_ieee[63]),
.A1N(n3974), .Y(n1269) );
INVX2TS U4828 ( .A(n3977), .Y(n3992) );
CLKBUFX2TS U4829 ( .A(n3979), .Y(n4005) );
INVX2TS U4830 ( .A(n4001), .Y(n4008) );
endmodule
|
/**
# Configurable PID Controller
Implements a low-logic-footprint PID control block, configurable at compile time.
only.
To save on logic, this controller only implements bit shifts for gain constants.
These gain constants, KI, KP, and KD, are set as number of bits to shift
**down** by. They are thus equivalent to 2^(-KI), etc.
/--->(-)-->(+)----->[z^-1]--+->[KI]---\
| ^ ^ | |
| | | | |
| | \---------------/ |
| \-----------[IF_BLEED]<---------+
| |
| V
inData ----+-------------------->[z^-1]-->[KP]--(+)----> outData
| ^
| /-->[z^-1]-\ |
| | | |
| | V |
\-----+-------->(-)-->[z^-1]-->[KD]---/
*/
module smallPidController #(
parameter WIDTH = 16, ///< Width of data path
parameter KP = 0, ///< Proportional gain
parameter KI = 0, ///< Integral gain
parameter KD = 0, ///< Differential gain
parameter KI_WIDTH = WIDTH, ///< Width of integral path accumulator
parameter ENABLE_KP = 1, ///< Enable Proportional section
parameter ENABLE_KI = 1, ///< Enable Integral section
parameter ENABLE_KD = 0, ///< Enable Differential section
parameter ENABLE_CLAMP = 0, ///< Clamp the integrator to prevent overflow
parameter ENABLE_BLEED = 0 ///< Provide an optional "bleed down" for the integrator
)
(
input wire clk,
input wire reset,
input wire signed [WIDTH-1:0] inData,
output reg signed [WIDTH-1:0] outData
);
wire signed [KI_WIDTH:0] integratorCalc;
reg signed [WIDTH-1:0] inDataD1;
reg signed [WIDTH:0] differentiator;
reg signed [KI_WIDTH-1:0] integrator;
always @(posedge clk) begin
if (reset) begin
inDataD1 <= 'd0;
outData <= 'd0;
differentiator <= 'd0;
integrator <= 'd0;
end
else begin
// Delay input data for proportional and derivative sections
inDataD1 <= inData;
// Calculate output
outData <= ((ENABLE_KP) ? (inDataD1 >>> KP) : 'd0)
+ ((ENABLE_KI) ? (integrator >>> KI) : 'd0)
+ ((ENABLE_KD) ? (differentiator >>> KD) : 'd0);
// Differentiator
if (ENABLE_KD) differentiator <= inData - inDataD1;
else differentiator <= 'd0;
// Integrator
if (ENABLE_KI) begin
if (ENABLE_CLAMP) begin
integrator <= (^integratorCalc[KI_WIDTH -: 2])
? {integratorCalc[KI_WIDTH], {(KI_WIDTH-1){~integratorCalc[KI_WIDTH]}}}
: integratorCalc;
end
else begin
integrator <= integratorCalc;
end
end
else begin
integrator <= 'd0;
end
end
end
endmodule
|
//======================================================================
//
// tb_sha256_axi4.v
// ----------------
// Testbench for the SHA256 AXI4 wrapper.
//
//
// Author: Sanjay A Menon
// Copyright (c) 2020
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_sha256_axi4();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg [7:0] tb_awaddr;
reg [2:0] tb_awprot;
reg tb_awvalid;
wire tb_awready;
reg [31:0] tb_wdata;
reg [3:0] tb_wstrb;
reg tb_wvalid;
wire tb_wready;
wire [1:0] tb_bresp;
wire tb_bvalid;
reg tb_bready;
reg [7:0] tb_araddr;
reg [2:0] tb_arprot;
reg tb_arvalid;
wire tb_arready;
wire [31:0] tb_rdata;
wire [1:0] tb_rresp;
wire tb_rvalid;
reg tb_rready;
wire complete;
reg tb_init;
reg tb_next;
reg tb_mode;
reg [511 : 0] tb_block;
wire tb_ready;
reg [255 : 0] tb_digest;
wire tb_digest_valid;
reg [31:0] i;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha256_axi4 dut(
.hash_complete(complete),
.s00_axi_aclk(tb_clk),
.s00_axi_aresetn(tb_reset_n),
.s00_axi_awaddr(tb_awaddr),
.s00_axi_awprot(tb_awprot),
.s00_axi_awvalid(tb_awvalid),
.s00_axi_awready(tb_awready),
.s00_axi_wdata(tb_wdata),
.s00_axi_wstrb(tb_wstrb),
.s00_axi_wvalid(tb_wvalid),
.s00_axi_wready(tb_wready),
.s00_axi_bresp(tb_bresp),
.s00_axi_bvalid(tb_bvalid),
.s00_axi_bready(tb_bready),
.s00_axi_araddr(tb_araddr),
.s00_axi_arprot(tb_arprot),
.s00_axi_arvalid(tb_arvalid),
.s00_axi_arready(tb_arready),
.s00_axi_rdata(tb_rdata),
.s00_axi_rresp(tb_rresp),
.s00_axi_rvalid(tb_rvalid),
.s00_axi_rready(tb_rready)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(2 * CLK_HALF_PERIOD);
if (DEBUG)
begin
//dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
/*task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("init = 0x%01x, next = 0x%01x",
dut.init, dut.next);
$display("block = 0x%0128x", dut.block);
$display("ready = 0x%01x, valid = 0x%01x",
dut.ready, dut.digest_valid);
$display("digest = 0x%064x", dut.digest);
$display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg);
$display("H4_reg = 0x%08x, H5_reg = 0x%08x, H6_reg = 0x%08x, H7_reg = 0x%08x",
dut.H4_reg, dut.H5_reg, dut.H6_reg, dut.H7_reg);
$display("");
$display("Control signals and counter:");
$display("sha256_ctrl_reg = 0x%02x", dut.sha256_ctrl_reg);
$display("digest_init = 0x%01x, digest_update = 0x%01x",
dut.digest_init, dut.digest_update);
$display("state_init = 0x%01x, state_update = 0x%01x",
dut.state_init, dut.state_update);
$display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
dut.first_block, dut.ready_flag, dut.w_init);
$display("t_ctr_inc = 0x%01x, t_ctr_rst = 0x%01x, t_ctr_reg = 0x%02x",
dut.t_ctr_inc, dut.t_ctr_rst, dut.t_ctr_reg);
$display("");
$display("State registers:");
$display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x",
dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg);
$display("e_reg = 0x%08x, f_reg = 0x%08x, g_reg = 0x%08x, h_reg = 0x%08x",
dut.e_reg, dut.f_reg, dut.g_reg, dut.h_reg);
$display("");
$display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x",
dut.a_new, dut.b_new, dut.c_new, dut.d_new);
$display("e_new = 0x%08x, f_new = 0x%08x, g_new = 0x%08x, h_new = 0x%08x",
dut.e_new, dut.f_new, dut.g_new, dut.h_new);
$display("");
$display("State update values:");
$display("w = 0x%08x, k = 0x%08x", dut.w_data, dut.k_data);
$display("t1 = 0x%08x, t2 = 0x%08x", dut.t1, dut.t2);
$display("");
end
endtask // dump_dut_state */
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_awaddr = 8'h00;
tb_awprot = 3'b000;
tb_awvalid = 0;
tb_wdata = 32'h00000000;
tb_wstrb = 4'h0;
tb_wvalid = 0;
tb_bready = 0;
tb_araddr = 8'h00;
tb_arprot = 3'b000;
tb_arvalid = 0;
tb_rready = 0;
i = 0;
end
endtask // init_dut
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_awready)
begin
#(CLK_PERIOD);
end
end
endtask // wait_ready
task wait_read;
begin
while (!tb_arready)//tb_arready
begin
#(CLK_PERIOD);
end
end
endtask // wait_read
task wait_hash_complete;
begin
while (!complete)
begin
#(CLK_PERIOD);
end
end
endtask // wait_hash_complete
//----------------------------------------------------------------
// single_block_test()
//
// Run a test case spanning a single data block.
//----------------------------------------------------------------
task single_block_test(input [7 : 0] tc_number,
input [511 : 0] block,
input [255 : 0] expected);
begin
$display("*** TC %0d single block test case started.", tc_number);
tc_ctr = tc_ctr + 1;
//Input Section
tb_awprot = 1;
tb_bready = 1;
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1f;
tb_wdata = block[31:0];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1e;
tb_wdata = block[63:32];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1d;
tb_wdata = block[95:64];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1c;
tb_wdata = block[127:96];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1b;
tb_wdata = block[159:128];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1a;
tb_wdata = block[191:160];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h19;
tb_wdata = block[223:192];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h18;
tb_wdata = block[255:224];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h17;
tb_wdata = block[287:256];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h16;
tb_wdata = block[319:288];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h15;
tb_wdata = block[351:320];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h14;
tb_wdata = block[383:352];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h13;
tb_wdata = block[415:384];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h12;
tb_wdata = block[447:416];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h11;
tb_wdata = block[479:448];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h10;
tb_wdata = block[511:480];
#(CLK_PERIOD);
wait_ready();
//Computation initiation by specifying block_init/block_next
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h08;
tb_wdata = 32'h00000005;
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h08;
tb_wdata = 32'h00000004;
#(CLK_PERIOD);
wait_ready();
//output section
wait_hash_complete();
tb_awvalid = 0;
tb_wvalid = 0;
tb_arprot = 1;
tb_arvalid = 1;
tb_rready = 1;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h20;
#(CLK_PERIOD);
wait_read();
tb_digest[255:224] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h21;
#(CLK_PERIOD);
wait_read();
tb_digest[223:192] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h22;
#(CLK_PERIOD);
wait_read();
tb_digest[191:160] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h23;
#(CLK_PERIOD);
wait_read();
tb_digest[159:128] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h24;
#(CLK_PERIOD);
wait_read();
tb_digest[127:96] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h25;
#(CLK_PERIOD);
wait_read();
tb_digest[95:64] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h26;
#(CLK_PERIOD);
wait_read();
tb_digest[63:32] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h27;
#(CLK_PERIOD);
wait_read();
tb_digest[31:0] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h27;
#(CLK_PERIOD);
wait_read();
tb_digest[31:0] <= tb_rdata;
if (tb_digest == expected)
begin
$display("*** TC %0d successful.", tc_number);
end
else
begin
$display("*** ERROR: TC %0d NOT successful.", tc_number);
$display("Expected: 0x%064x", expected);
$display("Got: 0x%064x", tb_digest);
$display("");
error_ctr = error_ctr + 1;
end
end
endtask // single_block_test
//----------------------------------------------------------------
// double_block_test()
//
// Run a test case spanning two data blocks. We check both
// intermediate and final digest.
//----------------------------------------------------------------
task double_block_test(input [7 : 0] tc_number,
input [511 : 0] block1,
input [255 : 0] expected1,
input [511 : 0] block2,
input [255 : 0] expected2);
reg [255 : 0] db_digest1;
reg [255 : 0] db_digest2;
reg db_error;
begin
$display("*** TC %0d double block test case started.", tc_number);
db_error = 0;
tc_ctr = tc_ctr + 1;
$display("*** TC %0d first block started.", tc_number);
tb_block = block1;
tb_init = 1;
#(CLK_PERIOD);
tb_init = 0;
wait_ready();
db_digest1 = tb_digest;
$display("*** TC %0d first block done.", tc_number);
$display("*** TC %0d second block started.", tc_number);
tb_block = block2;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
db_digest2 = tb_digest;
$display("*** TC %0d second block done.", tc_number);
if (DEBUG)
begin
$display("Generated digests:");
$display("Expected 1: 0x%064x", expected1);
$display("Got 1: 0x%064x", db_digest1);
$display("Expected 2: 0x%064x", expected2);
$display("Got 2: 0x%064x", db_digest2);
$display("");
end
if (db_digest1 == expected1)
begin
$display("*** TC %0d first block successful", tc_number);
$display("");
end
else
begin
$display("*** ERROR: TC %0d first block NOT successful", tc_number);
$display("Expected: 0x%064x", expected1);
$display("Got: 0x%064x", db_digest1);
$display("");
db_error = 1;
end
if (db_digest2 == expected2)
begin
$display("*** TC %0d second block successful", tc_number);
$display("");
end
else
begin
$display("*** ERROR: TC %0d second block NOT successful", tc_number);
$display("Expected: 0x%064x", expected2);
$display("Got: 0x%064x", db_digest2);
$display("");
db_error = 1;
end
if (db_error)
begin
error_ctr = error_ctr + 1;
end
end
endtask // double_block_test
//----------------------------------------------------------------
// issue_test()
//----------------------------------------------------------------
task issue_test;
reg [511 : 0] block0;
reg [511 : 0] block1;
reg [511 : 0] block2;
reg [511 : 0] block3;
reg [511 : 0] block4;
reg [511 : 0] block5;
reg [511 : 0] block6;
reg [511 : 0] block7;
reg [511 : 0] block8;
reg [255 : 0] expected;
begin : issue_test;
block0 = 512'h6b900001_496e2074_68652061_72656120_6f662049_6f542028_496e7465_726e6574_206f6620_5468696e_6773292c_206d6f72_6520616e_64206d6f_7265626f_6f6d2c20;
block1 = 512'h69742068_61732062_65656e20_6120756e_69766572_73616c20_636f6e73_656e7375_73207468_61742064_61746120_69732074_69732061_206e6577_20746563_686e6f6c;
block2 = 512'h6f677920_74686174_20696e74_65677261_74657320_64656365_6e747261_6c697a61_74696f6e_2c496e20_74686520_61726561_206f6620_496f5420_28496e74_65726e65;
block3 = 512'h74206f66_20546869_6e677329_2c206d6f_72652061_6e64206d_6f726562_6f6f6d2c_20697420_68617320_6265656e_20612075_6e697665_7273616c_20636f6e_73656e73;
block4 = 512'h75732074_68617420_64617461_20697320_74697320_61206e65_77207465_63686e6f_6c6f6779_20746861_7420696e_74656772_61746573_20646563_656e7472_616c697a;
block5 = 512'h6174696f_6e2c496e_20746865_20617265_61206f66_20496f54_2028496e_7465726e_6574206f_66205468_696e6773_292c206d_6f726520_616e6420_6d6f7265_626f6f6d;
block6 = 512'h2c206974_20686173_20626565_6e206120_756e6976_65727361_6c20636f_6e73656e_73757320_74686174_20646174_61206973_20746973_2061206e_65772074_6563686e;
block7 = 512'h6f6c6f67_79207468_61742069_6e746567_72617465_73206465_63656e74_72616c69_7a617469_6f6e2c49_6e207468_65206172_6561206f_6620496f_54202849_6e746572;
block8 = 512'h6e657420_6f662054_68696e67_73292c20_6d6f7265_20616e64_206d6f72_65800000_00000000_00000000_00000000_00000000_00000000_00000000_00000000_000010e8;
expected = 256'h7758a30bbdfc9cd92b284b05e9be9ca3d269d3d149e7e82ab4a9ed5e81fbcf9d;
$display("Running test for 9 block issue.");
tc_ctr = tc_ctr + 1;
tb_block = block0;
tb_init = 1;
#(CLK_PERIOD);
tb_init = 0;
wait_ready();
tb_block = block1;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block2;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block3;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block4;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block5;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block6;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block7;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block8;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
if (tb_digest == expected)
begin
$display("Digest ok.");
end
else
begin
error_ctr = error_ctr + 1;
$display("Error! Got: 0x%064x", tb_digest);
$display("Error! Expected: 0x%064x", expected);
end
end
endtask // issue_test
//----------------------------------------------------------------
// sha256_core_test
// Test cases taken from:
// http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA256.pdf
//----------------------------------------------------------------
task sha256_core_test;
reg [511 : 0] tc1;
reg [255 : 0] res1;
reg [511 : 0] tc2_1;
reg [255 : 0] res2_1;
reg [511 : 0] tc2_2;
reg [255 : 0] res2_2;
begin : sha256_core_test
// TC1: Single block message: "abc".
tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
res1 = 256'hBA7816BF8F01CFEA414140DE5DAE2223B00361A396177A9CB410FF61F20015AD;
//single_block_test(1, tc1, res1);
// TC2: Double block message.
// "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
res2_1 = 256'h85E655D6417A17953363376A624CDE5C76E09589CAC5F811CC4B32C1F20E533A;
tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
res2_2 = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
//double_block_test(2, tc2_1, res2_1, tc2_2, res2_2);
single_block_test(1, tc1, res1);
//issue_test();
end
endtask // sha256_core_test
//----------------------------------------------------------------
// main()
//----------------------------------------------------------------
initial
begin : main
$display(" -- Testbench for sha256_axi4 started --");
init_sim();
//dump_dut_state();
reset_dut();
//dump_dut_state();
sha256_core_test();
//issue_test();
display_test_result();
$display("*** Simulation done.");
$finish;
end // main
endmodule // tb_sha256_axi4
//======================================================================
// EOF tb_sha256_axi4.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V |
/*
* Front-end instruction pre-fetch unit with umi master interface
* Copyright (C) 2013 Charley Picker <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_front_prefetch_umi (
// common signals
input clk,
input rst,
// UMI master interface - fetch
output [19:0] umi_adr_o,
input [15:0] umi_dat_i,
output reg umi_stb_o,
output umi_by_o,
input umi_ack_i,
// Invalidate current fetch cycle
input flush,
// Address stearing from back-end
input load_cs_ip,
input [15:0] requested_cs,
input [15:0] requested_ip,
// Output to instruction fifo stage
output reg [15:0] cs,
output reg [15:0] ip,
output reg [15:0] fifo_dat_o,
output reg wr_fifo,
input fifo_full
);
// Registers and nets
wire stalled;
// Continuous assignments
// The flush, load_cs_ip and fifo_full signals will cause the fetch to be stalled
// Any other time, it should be ok to start another fetch cycle
assign stalled = flush || load_cs_ip || fifo_full;
// Calculate address for wb_adr_o
assign umi_adr_o = (cs << 4) + ip;
// We are always fetching two bytes at a time
assign umi_by_o = 1'b0;
// behaviour
// cs and ip logic
always @(posedge clk)
if (rst) begin
cs <= 16'hf000;
ip <= 16'hfff0;
end
else begin
if (flush) begin
cs <= requested_cs;
ip <= requested_ip;
end
else if (load_cs_ip) begin
cs <= requested_cs;
ip <= requested_ip;
end
else if (!stalled & umi_ack_i)
ip <= ip + 2;
end
// wb_stb_o
// When a stall condition is encountered at or during wb strobe,
// follow through until wishbone cycle completes. This essentially forces one
// complete wb cycle before the stall condition is acknowledge.
always @(posedge clk)
if (rst) umi_stb_o <= 1'b0;
else umi_stb_o <= !stalled ? 1'b1 : (umi_ack_i ? 1'b0 : umi_stb_o);
// write fifo
always @(posedge clk)
if (rst) wr_fifo <= 1'b0;
else wr_fifo <= (!stalled & umi_ack_i);
// Pass wishbone data to fifo
always @(posedge clk)
if (rst) wr_fifo <= 1'b0;
else fifo_dat_o <= umi_dat_i;
endmodule |
`timescale 1ns / 10ps
module usb_controller_testbench;
reg clk;
reg reset_n;
reg [15:0] panel_switches_raw;
reg rxf_n_raw;
reg txe_n_raw;
reg [7:0] data_bus_in_raw;
wire [7:0] data_bus_out;
wire rd_n;
wire wr_n;
wire data_out_enable;
wire [31:0] chunk_data;
wire [3:0] chunk_addr;
wire chunk_write_enable;
wire [3:0] row_addr;
wire [1:0] panel_addr;
wire [4:0] state_out;
usb_controller uut
(.clk(clk), .reset_n(reset_n), .panel_switches_raw(panel_switches_raw),
.rxf_n_raw(rxf_n_raw), .txe_n_raw(txe_n_raw),
.data_bus_in_raw(data_bus_in_raw), .data_bus_out(data_bus_out),
.rd_n(rd_n), .wr_n(wr_n), .data_out_enable(data_out_enable),
.chunk_data(chunk_data), .chunk_addr(chunk_addr),
.chunk_write_enable(chunk_write_enable), .row_addr(row_addr),
.panel_addr(panel_addr), .state_out(state_out));
always begin // 50MHz clock
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end
initial begin
// Initial conditions
reset_n = 0; // start out in reset mode
panel_switches_raw = 16'hfdec;
rxf_n_raw = 1; // no data to read for now
txe_n_raw = 0; // there is room in the tx buffer
data_bus_in_raw = 8'h00; // no data on bus
#100;
reset_n = 1; // enter run mode
data_bus_in_raw = 8'h23;
#100;
rxf_n_raw = 0; // indicate data to be read
#110;
rxf_n_raw = 1;
data_bus_in_raw = 8'h40;
#70;
rxf_n_raw = 0; // indicate data to be read
#110;
rxf_n_raw = 1;
#200
$stop;
end
endmodule // usb_controller_testbench
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "block_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "block_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRAN\
S_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=\
12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_processing_system7_0_0 (
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [0 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(),
.TTC0_WAVE1_OUT(),
.TTC0_WAVE2_OUT(),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(),
.USB0_VBUS_PWRSELECT(),
.USB0_VBUS_PWRFAULT(1'B0),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: frame_rate.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module frame_rate (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 10000,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 5000,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=frame_rate",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "10000"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.005000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.010000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.00500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.01000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "frame_rate.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5000"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frame_rate_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:49:09 02/26/2016
// Design Name:
// Module Name: dataMemory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dataMemory(
input clock_in,
input [31:0] address,
input [31:0] writeData,
output wire [31:0] readData,
input memWrite,
input memRead //memRead is actually not used
);
initial $readmemh("./src/memFile.txt",memFile); //intialize memory
wire [31:0] index;
assign index = address>>2; //data is fetched wordwise
reg [31:0] memFile [127:0];
assign readData= memFile[index];
always @(negedge clock_in)
if(memWrite) memFile[index] <= writeData;
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult_unit.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_unit (
dataa,
datab,
result);
input [35:0] dataa;
input [35:0] datab;
output [71:0] result;
wire [71:0] sub_wire0;
wire [71:0] result = sub_wire0[71:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 36,
lpm_mult_component.lpm_widthb = 36,
lpm_mult_component.lpm_widthp = 72;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
// Retrieval info: PRIVATE: WidthA NUMERIC "36"
// Retrieval info: PRIVATE: WidthB NUMERIC "36"
// Retrieval info: PRIVATE: WidthP NUMERIC "72"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "72"
// Retrieval info: USED_PORT: dataa 0 0 36 0 INPUT NODEFVAL "dataa[35..0]"
// Retrieval info: USED_PORT: datab 0 0 36 0 INPUT NODEFVAL "datab[35..0]"
// Retrieval info: USED_PORT: result 0 0 72 0 OUTPUT NODEFVAL "result[71..0]"
// Retrieval info: CONNECT: @dataa 0 0 36 0 dataa 0 0 36 0
// Retrieval info: CONNECT: @datab 0 0 36 0 datab 0 0 36 0
// Retrieval info: CONNECT: result 0 0 72 0 @result 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_99x128.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_99x128 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [98:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [98:0] q;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire [98:0] sub_wire2;
wire sub_wire3;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire [98:0] q = sub_wire2[98:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 99,
scfifo_component.lpm_widthu = 7,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "99"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "99"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "99"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 99 0 INPUT NODEFVAL data[98..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 99 0 OUTPUT NODEFVAL q[98..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 99 0 data 0 0 99 0
// Retrieval info: CONNECT: q 0 0 99 0 @q 0 0 99 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_99x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine 3D Registers
// File : de3d_reg.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This is the 3D Register block.
// It handles the different levels of registers.
// To reduce storage some floating point operations are done on the way in.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
// u_flt_mult_comb flt_mult_comb Floating Point Multiply
// u_flt_add_sub_comb flt_add_sub_comb Floating Point Add/ Subtract
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_reg
(
// Host Interface.
input hb_rstn, // clock input
input hb_clk, // host bus clock input
input [31:0] hb_din_p, // host bus data
input [8:2] hb_adr_p, // host bus address
input [8:2] hb_adr_r, // host bus read address
input hb_wstrb_p, // host bus write strobes
input [3:0] hb_ben_p, // host bus byte enables.
input hb_cp_csn, // host bus chip select.
input de_clk, // DE clock input
input de_rstn, // DE resetn input
input go_sup, // Setup is starting.
input load_actv_3d, // Setup done.
input [1:0] ps_15, // Pixel Size Level 15.
input load_actvn,
input load_15,
// Level 1.5 to the setup input.
output [351:0] vertex0_15, // Vertex 0.
output [351:0] vertex1_15, // Vertex 1.
output [351:0] vertex2_15, // Vertex 2.
output reg bc_pol_15, // Backface Culling Polarity
output reg color_mode_15, // 0 = ARGB, 1 = Float.
output reg bce_15, // Backface Cull enable
output rect_15, // Rectangle Mode.
output line_3d_actv_15, // Line is active
// Level 2 Pipe line signals.
output reg [209:0] lod_2, // LOD [9:0] origin
output reg [27:0] zorg_2, // Z origin pointer
output reg [11:0] zptch_2, // Z pitch register output
output reg [20:0] tporg_2, // Texture palette origin
output reg [20:0] tporg_1, // Texture palette origin
output reg [11:0] tptch_2, // Texture pitch register output
output reg [31:0] hith_2, // clipping hither.
output reg [31:0] yon_2, // clipping yon.
output reg [31:0] fcol_2, // Fog color
output reg [31:0] texbc_2, // Texture Boarder Color
output reg [23:0] key3dlo_2, // Alpha value register
output reg [23:0] key3dhi_2, // Alpha value register
output reg [31:0] c3d_2, // 3D Control Register
output reg [31:0] tex_2, // Texture Control Register
output reg [31:0] blendc_2, // OpenGL blending constant
output reg [31:0] pptr3d_2, // Pattern Pointer 3D output XY1 or CP1
output reg [23:0] alpha_2, // Alpha register
output reg [17:0] acntrl_2, // Alpha control
output reg actv_3d_2, // 3D command active
// Host read back data.
output reg [31:0] cp_hb_dout // Register readback
);
// _2 signals are the currently active command signals
// _15 are the signals in 3D for setup
// _1 is the next command
`include "define_3d.h"
////////////////////////////////////////////////////////////////
//
// Register Address Parameters.
//
// These are the original register locations for backward compatibility
// with the Imagine series of graphics processors. They can easily be
// changed for custom drivers.
parameter
CMDR = 7'b0_0100_10, // 0x048
OPC = 7'b0_0101_00, // 0x050
CMD_3D = 7'b1_0110_10, // 0x168
ROP = 7'b0_0101_01, // 0x054
LOD0 = 7'b0_1101_00, // 0x0d0
LOD1 = 7'b0_1101_01, // 0x0d4
LOD2 = 7'b0_1101_10, // 0x0d8
LOD3 = 7'b0_1101_11, // 0x0dc
LOD4 = 7'b0_1110_00, // 0x0e0
LOD5 = 7'b0_1110_01, // 0x0e4
LOD6 = 7'b0_1110_10, // 0x0e8
LOD7 = 7'b0_1110_11, // 0x0ec
LOD8 = 7'b0_1111_00, // 0x0f0
LOD9 = 7'b0_1111_01, // 0x0f4
TPTCH = 7'b0_0011_10, // 0x038
ZPTCH = 7'b0_0011_11, // 0x03c
ZORG = 7'b1_0000_00, // 0x100
TPAL = 7'b1_0001_10, // 0x118
HITH = 7'b1_0001_11, // 0x11c
YON = 7'b1_0010_00, // 0x120
FCOL = 7'b1_0010_01, // 0x124
ALPHA = 7'b1_0010_10, // 0x128
TBOARD = 7'b1_0010_11, // 0x12c
V0AF = 7'b1_0011_00, // 0x130
V0RF = 7'b1_0011_01, // 0x134
V0GF = 7'b1_0011_10, // 0x138
V0BF = 7'b1_0011_11, // 0x13c
V1AF = 7'b1_0100_00, // 0x140
V1RF = 7'b1_0100_01, // 0x144
V1GF = 7'b1_0100_10, // 0x148
V1BF = 7'b1_0100_11, // 0x14c
V2AF = 7'b1_0101_00, // 0x150
V2RF = 7'b1_0101_01, // 0x154
V2GF = 7'b1_0101_10, // 0x158
V2BF = 7'b1_0101_11, // 0x15c
KY3DLO = 7'b1_0110_00, // 0x160
KY3DHI = 7'b1_0110_01, // 0x164
ACNTRL = 7'b1_0110_11, // 0x16c
C3D = 7'b1_0111_00, // 0x170
TEX = 7'b1_0111_01, // 0x174
CP0 = 7'b1_0111_10, // 0x178
CP1 = 7'b1_0111_11, // 0x17c
CP2 = 7'b1_1000_00, // 0x180
CP3 = 7'b1_1000_01, // 0x184
CP4 = 7'b1_1000_10, // 0x188
CP5 = 7'b1_1000_11, // 0x18c
CP6 = 7'b1_1001_00, // 0x190
CP7 = 7'b1_1001_01, // 0x194
CP8 = 7'b1_1001_10, // 0x198
CP9 = 7'b1_1001_11, // 0x19c
CP10 = 7'b1_1010_00, // 0x1a0
CP11 = 7'b1_1010_01, // 0x1a4
CP12 = 7'b1_1010_10, // 0x1a8
CP13 = 7'b1_1010_11, // 0x1ac
CP14 = 7'b1_1011_00, // 0x1b0
CP15 = 7'b1_1011_01, // 0x1b4
CP16 = 7'b1_1011_10, // 0x1b8
CP17 = 7'b1_1011_11, // 0x1bc
CP18 = 7'b1_1100_00, // 0x1c0
CP19 = 7'b1_1100_01, // 0x1c4
CP20 = 7'b1_1100_10, // 0x1c8
CP21 = 7'b1_1100_11, // 0x1cc
CP22 = 7'b1_1101_00, // 0x1d0
CP23 = 7'b1_1101_01, // 0x1d4
CP24 = 7'b1_1101_10, // 0x1d8
TRG3D = 7'b1_1101_11, // 0x1dc
BLENDC = 7'b1_1110_00, // 0x1e0
LINE_3D = 4'b1000, // Line 3D command.
TRIAN_3D = 4'b1001; // Triangle 3D command.
/////////////////////////////////////////////////////////////////
wire [31:0] vertex0_w;
wire [31:0] vertex1_w;
wire [31:0] vertex2_w;
wire [31:0] uvout; // UV from multiplier to UV of vertices
wire [31:0] bias_space;
wire [31:0] xy_in;
wire not_zero_u0;
wire not_zero_v0;
wire not_zero_u1;
wire not_zero_v1;
wire not_zero_u2;
wire not_zero_v2;
reg [351:0] vertex0_u; // Vertex 0, un-sorted.
reg [351:0] vertex1_u; // Vertex 1, un-sorted.
reg [351:0] vertex2_u; // Vertex 2, un-sorted.
reg [20:0] lod9_r;
reg [20:0] lod8_r;
reg [20:0] lod7_r;
reg [20:0] lod6_r;
reg [20:0] lod5_r;
reg [20:0] lod4_r;
reg [20:0] lod3_r;
reg [20:0] lod2_r;
reg [20:0] lod1_r;
reg [20:0] lod0_r;
reg [31:0] win;
reg [7:0] asrcreg_r; // Alpha blend source alpha override
reg [7:0] adstreg_r; // Alpha blend dest alpha override
reg [7:0] atest_r; // Alpha test register
reg [3:0] asrc_r; // Alpha blending src factor
reg [3:0] adst_r; // Alpha blending dst factor
reg sre_r; // Use source register
reg dre_r; // Use dest register
reg be_r; // enable blending
reg aen_r; // alpha enable
reg [2:0] aop_r; // Alpha operator
reg da_r;
reg amd_r;
reg asl_r;
reg [2:0] key_ctrl_r;
reg [31:0] pptr3d_1;
reg color_mode_1;
reg [27:0] zorg_1;
reg [11:0] zptch_1;
reg [11:0] tptch_1;
reg [31:0] hith_1;
reg [31:0] yon_1;
reg [31:0] fcol_1;
reg [31:0] texbc_1;
reg [23:0] key3dlo_1;
reg [23:0] key3dhi_1;
reg [31:0] c3d_1;
reg [31:0] tex_1;
reg [31:0] blendc_1;
reg [3:0] opc_r;
reg [3:0] opc_15;
wire bce_1;
wire [23:0] alpha_1;
wire [17:0] acntrl_1;
wire bc_pol_1;
wire [351:0] vertex0_1;
wire [351:0] vertex1_1;
wire [351:0] vertex2_1;
wire not_zero_z0;
wire not_zero_z1;
wire not_zero_z2;
wire [31:0] z0_fp;
wire [31:0] z1_fp;
wire [31:0] z2_fp;
wire [31:0] u0_fp;
wire [31:0] v0_fp;
wire [31:0] u1_fp;
wire [31:0] v1_fp;
wire [31:0] u2_fp;
wire [31:0] v2_fp;
wire [31:0] p0z_fp;
wire [31:0] p1z_fp;
wire [31:0] p2z_fp;
wire [31:0] p0uw_fp;
wire [31:0] p0vw_fp;
wire [31:0] p1uw_fp;
wire [31:0] p1vw_fp;
wire [31:0] p2uw_fp;
wire [31:0] p2vw_fp;
reg [209:0] lod_15; // LOD [9:0] origin
reg [31:0] hith_15; // clipping hither.
reg [31:0] yon_15; // clipping yon.
reg [27:0] zorg_15; // Z origin pointer
reg [11:0] zptch_15; // Z pitch register output
reg [20:0] tporg_15; // Texture palette origin
reg [11:0] tptch_15; // Texture pitch register output
reg [31:0] fcol_15; // Fog color
reg [31:0] texbc_15; // Texture Boarder Color
reg [23:0] key3dlo_15; // Alpha value register
reg [23:0] key3dhi_15; // Alpha value register
reg [31:0] c3d_15; // 3D Control Register
reg [31:0] tex_15; // Texture Control Register
reg [31:0] blendc_15; // OpenGL blending constant
reg [23:0] alpha_15;
reg [17:0] acntrl_15;
reg [31:0] pptr3d_15;
reg [1:0] zsc_add;
reg [351:0] vertex0_15u; // Vertex 0.
reg [351:0] vertex1_15u; // Vertex 1.
reg [351:0] vertex2_15u; // Vertex 2.
/************************************************************************/
/* Transfer non sorted vertices to rdmux */
/************************************************************************/
assign rect_15 = c3d_15[28]; // Rectangle Mode.
wire line_3d_1 = (opc_r == LINE_3D);
wire trian_3d_1 = (opc_r == TRIAN_3D);
wire line_3d_15 = (opc_15 == LINE_3D);
wire trian_3d_15 = (opc_15 == TRIAN_3D);
wire cmd_3d = trian_3d_1 | line_3d_1;
wire cull_polarity_1;
wire sort_on = trian_3d_1 & ~c3d_1[28];
assign line_3d_actv_15 = (opc_15 == LINE_3D);
assign bc_pol_1 = ~(cull_polarity_1 ^ c3d_1[22]);
assign bce_1 = trian_3d_1 & c3d_1[23];
assign alpha_1[15:0] = {adstreg_r,asrcreg_r};
assign alpha_1[23:16] = atest_r;
assign acntrl_1[10:0] = {be_r,dre_r,sre_r, adst_r,asrc_r};
assign acntrl_1[17:11] = {da_r,amd_r,asl_r,aen_r,aop_r};
// Pipeline all the goodies from the hb/dlp
// It has been looking like we will have trouble getting from
// hb/dlp through des_mulf and setup in 15ns. The 3d_trig
// register is in der_reg.
reg [31:0] hb_din; // host bus data
reg [8:2] hb_adr; // host bus address
reg hb_wstrb; // host bus write strobes
reg [3:0] hb_ben; // host bus byte enables.
reg hb_csn; // host bus chip select.
always @(posedge hb_clk) begin
hb_din <= hb_din_p;
hb_adr <= hb_adr_p;
hb_wstrb <= hb_wstrb_p;
hb_ben <= hb_ben_p;
hb_csn <= hb_cp_csn;
end //
//////////////////////////////////////////////////////////////////////////
//
// OPCODE Register.
// Mirror of the OPCODE register in the 2D core.
always @(posedge hb_clk, negedge hb_rstn)
if(!hb_rstn) opc_r <= 4'h0;
else if(hb_wstrb && !hb_csn && !hb_ben[0] &&
((hb_adr==CMDR) || (hb_adr==CMD_3D) || (hb_adr==OPC)))
opc_r <= hb_din[3:0];
// CMDR = 7'b0_0100_10, // 0x048
// OPC = 7'b0_0101_00, // 0x050
// CMD_3D = 7'b1_0110_10, // 0x168
//////////////////////////////////////////////////////////////////////////
//
// Sort Verticies.
assign {cull_polarity_1, vertex2_1, vertex1_1, vertex0_1}
= vertex_sort(vertex2_u, vertex1_u, vertex0_u, sort_on, line_3d_1);
// For orthogonal mode, we mux in a 1.0 (3f800000) for all W values
assign vertex0_w = (~tex_1`T_PCM) ? 32'h3f800000 : vertex0_u`VWW;
assign vertex1_w = (~tex_1`T_PCM) ? 32'h3f800000 : vertex1_u`VWW;
assign vertex2_w = (~tex_1`T_PCM) ? 32'h3f800000 : vertex2_u`VWW;
///////////////////////////////////////////////////////////////////////////
// Multiply all inputs by W coming in, if opc_r = TRIAN_3D and register
// written in is the UV coordinates for Vertex 0,1 or 2
//
always @*
case(hb_adr)
CP9, CP8, CP7, CP6: win = vertex0_w;
CP17, CP16, CP15, CP14: win = vertex1_w;
CP24, CP23, CP22, TRG3D: win = vertex2_w;
default: win = 32'h3f80_0000; // 1.0 in floating point
endcase
flt_mult_comb u_flt_mult_comb
(win, hb_din[31:0], uvout);
///////////////////////////////////////////////////////////////////////////
// subtract .5 to X,Y
flt_add_sub_comb u_flt_add_sub_comb
(1'b1,hb_din[31:0], {2'b00,{6{c3d_1[21] & cmd_3d}},24'h0}, bias_space);
// assign xy_in = (!bias_space[31]) ? bias_space : 32'h0;
assign xy_in = bias_space;
///////////////////////////////////////////////////////////////////////////
// Control Registers.
always @(posedge hb_clk, negedge hb_rstn)
if(!hb_rstn) begin
tex_1 <= 32'h0;
c3d_1 <= 32'h0;
asl_r <= 0;
amd_r <= 0;
da_r <= 0;
color_mode_1 <= 0;
{adst_r,asrc_r} <= 8'h0;
{be_r, dre_r,sre_r} <= 3'h0;
{aen_r, aop_r} <= 4'h0;
c3d_1 <= 32'h0;
tex_1 <= 32'h0;
tptch_1 <= 12'h0;
zptch_1 <= 12'h0;
zorg_1 <= 28'h0;
lod0_r <= 21'h0;
lod1_r <= 21'h0;
lod2_r <= 21'h0;
lod3_r <= 21'h0;
lod4_r <= 21'h0;
lod5_r <= 21'h0;
lod6_r <= 21'h0;
lod7_r <= 21'h0;
lod8_r <= 21'h0;
lod9_r <= 21'h0;
tporg_1 <= 21'h0;
hith_1 <= 32'h0;
yon_1 <= 32'h0;
fcol_1 <= 32'h0;
asrcreg_r <= 8'h0;
adstreg_r <= 8'h0;
atest_r <= 8'h0;
texbc_1 <= 32'h0;
key3dlo_1 <= 24'h0;
key3dhi_1 <= 24'h0;
blendc_1 <= 24'h0;
pptr3d_1 <= 32'h0;
vertex0_u`VALL <= 352'h0;
vertex1_u`VALL <= 352'h0;
vertex2_u`VALL <= 352'h0;
end else begin // if (!hb_rstn)
if (~tex_1`T_PCM) begin
vertex0_u`VWW <= 32'h3f800000;
vertex1_u`VWW <= 32'h3f800000;
vertex2_u`VWW <= 32'h3f800000;
end
if (!hb_csn && hb_wstrb) begin
if(hb_adr==ACNTRL) begin
if(!hb_ben[0]){adst_r,asrc_r} <= hb_din[7:0];
if(!hb_ben[1]){be_r, dre_r,sre_r} <= hb_din[10:8];
if(!hb_ben[2]) {aen_r, aop_r} <= hb_din[19:16];
if(!hb_ben[3]) {da_r,amd_r,asl_r} <= hb_din[26:24];
end
if(hb_adr==C3D) begin
if (!hb_ben[0]) c3d_1[7:0] <= hb_din[7:0];
if (!hb_ben[1]) c3d_1[15:8] <= hb_din[15:8];
if (!hb_ben[2]) c3d_1[23:16] <= hb_din[23:16];
if (!hb_ben[3]) c3d_1[31:24] <= hb_din[31:24];
end
if(hb_adr==TEX) begin
if (!hb_ben[0]) tex_1[7:0] <= hb_din[7:0];
if (!hb_ben[1]) tex_1[15:8] <= hb_din[15:8];
if (!hb_ben[2]) tex_1[23:16] <= hb_din[23:16];
if (!hb_ben[3]) tex_1[31:24] <= hb_din[31:24];
end
if(hb_adr==TPTCH) begin
if(!hb_ben[0])tptch_1[3:0] <= hb_din[7:4];
if(!hb_ben[1])tptch_1[11:4] <= hb_din[15:8];
end
if(hb_adr==ZPTCH) begin
if(!hb_ben[0])zptch_1[3:0] <= hb_din[7:4];
if(!hb_ben[1])zptch_1[11:4] <= hb_din[15:8];
end
if(hb_adr==ZORG) begin
if(!hb_ben[0])zorg_1[3:0] <= hb_din[7:4];
if(!hb_ben[1])zorg_1[11:4] <= hb_din[15:8];
if(!hb_ben[2])zorg_1[19:12] <= hb_din[23:16];
if(!hb_ben[3])zorg_1[27:20] <= hb_din[31:24];
end
if(hb_adr==LOD0) begin
if(!hb_ben[0])lod0_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod0_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod0_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod0_r[20] <= hb_din[24];
end
if(hb_adr==LOD1) begin
if(!hb_ben[0])lod1_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod1_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod1_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod1_r[20] <= hb_din[24];
end
if(hb_adr==LOD2) begin
if(!hb_ben[0])lod2_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod2_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod2_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod2_r[20] <= hb_din[24];
end
if(hb_adr==LOD3) begin
if(!hb_ben[0])lod3_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod3_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod3_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod3_r[20] <= hb_din[24];
end
if(hb_adr==LOD4) begin
if(!hb_ben[0])lod4_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod4_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod4_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod4_r[20] <= hb_din[24];
end
if(hb_adr==LOD5) begin
if(!hb_ben[0])lod5_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod5_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod5_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod5_r[20] <= hb_din[24];
end
if(hb_adr==LOD6) begin
if(!hb_ben[0])lod6_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod6_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod6_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod6_r[20] <= hb_din[24];
end
if(hb_adr==LOD7) begin
if(!hb_ben[0])lod7_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod7_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod7_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod7_r[20] <= hb_din[24];
end
if(hb_adr==LOD8) begin
if(!hb_ben[0])lod8_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod8_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod8_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod8_r[20] <= hb_din[24];
end
if(hb_adr==LOD9) begin
if(!hb_ben[0])lod9_r[3:0] <= hb_din[7:4];
if(!hb_ben[1])lod9_r[11:4] <= hb_din[15:8];
if(!hb_ben[2])lod9_r[19:12] <= hb_din[23:16];
if(!hb_ben[3])lod9_r[20] <= hb_din[24];
end
if(hb_adr==TPAL) begin
if(!hb_ben[0])tporg_1[3:0] <= hb_din[7:4];
if(!hb_ben[1])tporg_1[11:4] <= hb_din[15:8];
if(!hb_ben[2])tporg_1[19:12] <= hb_din[23:16];
if(!hb_ben[3])tporg_1[20] <= hb_din[24];
end
if(hb_adr==HITH) begin
if(!hb_ben[0])hith_1[7:0] <= hb_din[7:0];
if(!hb_ben[1])hith_1[15:8] <= hb_din[15:8];
if(!hb_ben[2])hith_1[23:16] <= hb_din[23:16];
if(!hb_ben[3])hith_1[31:24] <= hb_din[31:24];
end
if(hb_adr==YON) begin
if(!hb_ben[0])yon_1[7:0] <= hb_din[7:0];
if(!hb_ben[1])yon_1[15:8] <= hb_din[15:8];
if(!hb_ben[2])yon_1[23:16] <= hb_din[23:16];
if(!hb_ben[3])yon_1[31:24] <= hb_din[31:24];
end
if(hb_adr==FCOL) begin
if(!hb_ben[0])fcol_1[7:0] <= hb_din[7:0];
if(!hb_ben[1])fcol_1[15:8] <= hb_din[15:8];
if(!hb_ben[2])fcol_1[23:16] <= hb_din[23:16];
if(!hb_ben[3])fcol_1[31:24] <= hb_din[31:24];
end
if(hb_adr==ALPHA) begin
if(!hb_ben[0])asrcreg_r <= hb_din[7:0];
if(!hb_ben[1])adstreg_r <= hb_din[15:8];
if(!hb_ben[2])atest_r <= hb_din[23:16];
end
if(hb_adr==TBOARD) begin
if(!hb_ben[0])texbc_1[7:0] <= hb_din[7:0];
if(!hb_ben[1])texbc_1[15:8] <= hb_din[15:8];
if(!hb_ben[2])texbc_1[23:16] <= hb_din[23:16];
if(!hb_ben[3])texbc_1[31:24] <= hb_din[31:24];
end
if(hb_adr==KY3DLO) begin
if(!hb_ben[0])key3dlo_1[7:0] <= hb_din[7:0];
if(!hb_ben[1])key3dlo_1[15:8] <= hb_din[15:8];
if(!hb_ben[2])key3dlo_1[23:16] <= hb_din[23:16];
end
if(hb_adr==KY3DHI) begin
if(!hb_ben[0])key3dhi_1[7:0] <= hb_din[7:0];
if(!hb_ben[1])key3dhi_1[15:8] <= hb_din[15:8];
if(!hb_ben[2])key3dhi_1[23:16] <= hb_din[23:16];
end
if(hb_adr==BLENDC) begin
if(!hb_ben[0])blendc_1[7:0] <= hb_din[7:0];
if(!hb_ben[1])blendc_1[15:8] <= hb_din[15:8];
if(!hb_ben[2])blendc_1[23:16] <= hb_din[23:16];
if(!hb_ben[3])blendc_1[31:24] <= hb_din[31:24];
end
if (hb_adr==CP0) begin
if (!hb_ben[0]) pptr3d_1[7:0] <= hb_din[7:0];
if (!hb_ben[1]) pptr3d_1[15:8] <= hb_din[15:8];
if (!hb_ben[2]) pptr3d_1[23:16] <= hb_din[23:16];
if (!hb_ben[3]) pptr3d_1[31:24] <= hb_din[31:24];
end
if (hb_adr==CP1) begin // V0X
if (!hb_ben[0]) vertex0_u`VXB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex0_u`VXB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex0_u`VXB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex0_u`VXB3 <= xy_in[31:24];
end
if (hb_adr==CP2) begin // V0Y
if (!hb_ben[0]) vertex0_u`VYB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex0_u`VYB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex0_u`VYB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex0_u`VYB3 <= xy_in[31:24];
end
if (hb_adr==CP3) begin // V0Z
if (!hb_ben[0]) vertex0_u`VZB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex0_u`VZB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex0_u`VZB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex0_u`VZB3 <= xy_in[31:24];
end
if (hb_adr==CP4) begin // V0W
if (!hb_ben[0]) vertex0_u`VWB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex0_u`VWB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex0_u`VWB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex0_u`VWB3 <= hb_din[31:24];
end
if (hb_adr==CP5) begin // Color Int.
if(~&hb_ben[3:0]) color_mode_1 <= 1'b0;
if (!hb_ben[0]) vertex0_u`VBB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex0_u`VGB0 <= hb_din[15:8];
if (!hb_ben[2]) vertex0_u`VRB0 <= hb_din[23:16];
if (!hb_ben[3]) vertex0_u`VAB0 <= hb_din[31:24];
end
if (hb_adr==CP6) begin // Specular Color Int Fog, Rs, Gs, Bs.
if (!hb_ben[0]) vertex0_u`VSB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex0_u`VSB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex0_u`VSB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex0_u`VSB3 <= hb_din[31:24];
end
if (hb_adr==CP7) begin // V0U
if (!hb_ben[0]) vertex0_u`VUB0 <= uvout[7:0];
if (!hb_ben[1]) vertex0_u`VUB1 <= uvout[15:8];
if (!hb_ben[2]) vertex0_u`VUB2 <= uvout[23:16];
if (!hb_ben[3]) vertex0_u`VUB3 <= uvout[31:24];
end
if (hb_adr==CP8) begin // V0V
if (!hb_ben[0]) vertex0_u`VVB0 <= uvout[7:0];
if (!hb_ben[1]) vertex0_u`VVB1 <= uvout[15:8];
if (!hb_ben[2]) vertex0_u`VVB2 <= uvout[23:16];
if (!hb_ben[3]) vertex0_u`VVB3 <= uvout[31:24];
end
if (hb_adr==CP9) begin // V1X
if (!hb_ben[0]) vertex1_u`VXB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex1_u`VXB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex1_u`VXB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex1_u`VXB3 <= xy_in[31:24];
end
if (hb_adr==CP10) begin // V1Y
if (!hb_ben[0]) vertex1_u`VYB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex1_u`VYB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex1_u`VYB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex1_u`VYB3 <= xy_in[31:24];
end
if (hb_adr==CP11) begin // V1Z
if (!hb_ben[0]) vertex1_u`VZB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex1_u`VZB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex1_u`VZB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex1_u`VZB3 <= hb_din[31:24];
end
if (hb_adr==CP12) begin // V1W
if (!hb_ben[0]) vertex1_u`VWB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex1_u`VWB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex1_u`VWB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex1_u`VWB3 <= xy_in[31:24];
end
if (hb_adr==CP13) begin // V1 Color Int.
if(~&hb_ben[3:0]) color_mode_1 <= 1'b0;
if (!hb_ben[0]) vertex1_u`VBB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex1_u`VGB0 <= hb_din[15:8];
if (!hb_ben[2]) vertex1_u`VRB0 <= hb_din[23:16];
if (!hb_ben[3]) vertex1_u`VAB0 <= hb_din[31:24];
end
if (hb_adr==CP14) begin // V1 Specular Fog, Rs, Gs, Bs.
if (!hb_ben[0]) vertex1_u`VSB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex1_u`VSB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex1_u`VSB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex1_u`VSB3 <= hb_din[31:24];
end
if (hb_adr==CP15) begin // V1U
if (!hb_ben[0]) vertex1_u`VUB0 <= uvout[7:0];
if (!hb_ben[1]) vertex1_u`VUB1 <= uvout[15:8];
if (!hb_ben[2]) vertex1_u`VUB2 <= uvout[23:16];
if (!hb_ben[3]) vertex1_u`VUB3 <= uvout[31:24];
end
if (hb_adr==CP16) begin // V1V
if (!hb_ben[0]) vertex1_u`VVB0 <= uvout[7:0];
if (!hb_ben[1]) vertex1_u`VVB1 <= uvout[15:8];
if (!hb_ben[2]) vertex1_u`VVB2 <= uvout[23:16];
if (!hb_ben[3]) vertex1_u`VVB3 <= uvout[31:24];
end
if (hb_adr==CP17) begin // V2X
if (!hb_ben[0]) vertex2_u`VXB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex2_u`VXB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex2_u`VXB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex2_u`VXB3 <= xy_in[31:24];
end
if (hb_adr==CP18) begin // V2Y
if (!hb_ben[0]) vertex2_u`VYB0 <= xy_in[7:0];
if (!hb_ben[1]) vertex2_u`VYB1 <= xy_in[15:8];
if (!hb_ben[2]) vertex2_u`VYB2 <= xy_in[23:16];
if (!hb_ben[3]) vertex2_u`VYB3 <= xy_in[31:24];
end
if (hb_adr==CP19) begin // V2Z
if (!hb_ben[0]) vertex2_u`VZB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VZB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VZB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VZB3 <= hb_din[31:24];
end
if (hb_adr==CP20) begin // V2W
if (!hb_ben[0]) vertex2_u`VWB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VWB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VWB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VWB3 <= hb_din[31:24];
end
if (hb_adr==CP21) begin // V2 Color Int.
if(~&hb_ben[3:0]) color_mode_1 <= 1'b0;
if (!hb_ben[0]) vertex2_u`VBB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VGB0 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VRB0 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VAB0 <= hb_din[31:24];
end
if (hb_adr==CP22) begin // V2 Specular Fog, Rs, Gs, Bs.
if (!hb_ben[0]) vertex2_u`VSB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VSB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VSB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VSB3 <= hb_din[31:24];
end
if (hb_adr==CP23) begin // V2U
if (!hb_ben[0]) vertex2_u`VUB0 <= uvout[7:0];
if (!hb_ben[1]) vertex2_u`VUB1 <= uvout[15:8];
if (!hb_ben[2]) vertex2_u`VUB2 <= uvout[23:16];
if (!hb_ben[3]) vertex2_u`VUB3 <= uvout[31:24];
end
if (hb_adr==CP24) begin
// V2V
if (!hb_ben[0]) vertex2_u`VVB0 <= uvout[7:0];
if (!hb_ben[1]) vertex2_u`VVB1 <= uvout[15:8];
if (!hb_ben[2]) vertex2_u`VVB2 <= uvout[23:16];
if (!hb_ben[3]) vertex2_u`VVB3 <= uvout[31:24];
end
if (hb_adr==V0AF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex0_u`VAB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex0_u`VAB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex0_u`VAB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex0_u`VAB3 <= hb_din[31:24];
end
if (hb_adr==V0RF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex0_u`VRB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex0_u`VRB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex0_u`VRB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex0_u`VRB3 <= hb_din[31:24];
end
if (hb_adr==V0GF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex0_u`VGB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex0_u`VGB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex0_u`VGB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex0_u`VGB3 <= hb_din[31:24];
end
if (hb_adr==V0BF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex0_u`VBB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex0_u`VBB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex0_u`VBB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex0_u`VBB3 <= hb_din[31:24];
end
if (hb_adr==V1AF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex1_u`VAB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex1_u`VAB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex1_u`VAB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex1_u`VAB3 <= hb_din[31:24];
end
if (hb_adr==V1RF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex1_u`VRB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex1_u`VRB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex1_u`VRB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex1_u`VRB3 <= hb_din[31:24];
end
if (hb_adr==V1GF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex1_u`VGB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex1_u`VGB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex1_u`VGB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex1_u`VGB3 <= hb_din[31:24];
end
if (hb_adr==V1BF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex1_u`VBB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex1_u`VBB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex1_u`VBB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex1_u`VBB3 <= hb_din[31:24];
end
if (hb_adr==V2AF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex2_u`VAB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VAB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VAB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VAB3 <= hb_din[31:24];
end
if (hb_adr==V2RF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex2_u`VRB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VRB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VRB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VRB3 <= hb_din[31:24];
end
if (hb_adr==V2GF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex2_u`VGB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VGB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VGB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VGB3 <= hb_din[31:24];
end
if (hb_adr==V2BF) begin
if(~&hb_ben) color_mode_1 <= 1'b1;
if (!hb_ben[0]) vertex2_u`VBB0 <= hb_din[7:0];
if (!hb_ben[1]) vertex2_u`VBB1 <= hb_din[15:8];
if (!hb_ben[2]) vertex2_u`VBB2 <= hb_din[23:16];
if (!hb_ben[3]) vertex2_u`VBB3 <= hb_din[31:24];
end
end // if (!hb_csn && hb_wstrb)
end // else: !if(!hb_rstn)
always @(posedge de_clk, negedge de_rstn)
if(!de_rstn) begin
opc_15 <= 4'h0;
c3d_15 <= 32'h0;
tex_15 <= 32'h0; // Texture Control Register
end else if(go_sup & (line_3d_1 | trian_3d_1)) begin
opc_15 <= opc_r;
c3d_15 <= c3d_1; // 3D Control Register
tex_15 <= tex_1; // Texture Control Register
end else if(load_15 & !(line_3d_1 | trian_3d_1)) begin
opc_15 <= 4'h0;
c3d_15 <= 32'h0;
tex_15 <= 32'h0; // Texture Control Register
end
always @(posedge de_clk, negedge de_rstn)
if(!de_rstn) begin
pptr3d_15 <= 32'h0; // Pattern Pointer 3D output XY1 or CP1
vertex0_15u <= 352'h0; // Vertex 0.
vertex1_15u <= 352'h0; // Vertex 1.
vertex2_15u <= 352'h0; // Vertex 2.
bc_pol_15 <= 1'b0;
color_mode_15 <= 1'b0; // 0 = ARGB, 1 = Float.
lod_15 <= 210'h0;
zorg_15 <= 28'h0; // Z origin pointer
zptch_15 <= 12'h0; // Z pitch register output
tporg_15 <= 21'h0; // Texture palette origin
tptch_15 <= 12'h0; // Texture pitch register output
hith_15 <= 32'h0; // clipping hither.
yon_15 <= 32'h0; // clipping yon.
fcol_15 <= 32'h0; // Fog color
texbc_15 <= 32'h0; // Texture Boarder Color
key3dlo_15 <= 24'h0; // Alpha value register
key3dhi_15 <= 24'h0; // Alpha value register
blendc_15 <= 32'h0; // OpenGL blending constant
bce_15 <= 1'b0; // Backface Cull enable
alpha_15 <= 24'h0;
acntrl_15 <= 18'h0;
end else if(go_sup) begin
pptr3d_15 <= pptr3d_1; // Pattern Pointer 3D output XY1 or CP1
vertex0_15u <= vertex0_1; // Vertex 0.
vertex1_15u <= vertex1_1; // Vertex 1.
vertex2_15u <= vertex2_1; // Vertex 2.
bc_pol_15 <= bc_pol_1;
color_mode_15 <= color_mode_1; // 0 = ARGB, 1 = Float.
lod_15 <= {lod9_r, lod8_r, lod7_r, lod6_r, lod5_r,
lod4_r, lod3_r, lod2_r, lod1_r, lod0_r};
zorg_15 <= zorg_1; // Z origin pointer
zptch_15 <= zptch_1; // Z pitch register output
tporg_15 <= tporg_1; // Texture palette origin
tptch_15 <= tptch_1; // Texture pitch register output
hith_15 <= hith_1; // clipping hither.
yon_15 <= yon_1; // clipping yon.
fcol_15 <= fcol_1; // Fog color
texbc_15 <= texbc_1; // Texture Boarder Color
key3dlo_15 <= key3dlo_1; // Alpha value register
key3dhi_15 <= key3dhi_1; // Alpha value register
blendc_15 <= blendc_1; // OpenGL blending constant
bce_15 <= bce_1; // Backface Cull enable
alpha_15 <= alpha_1;
acntrl_15 <= acntrl_1;
end
// Z Scaling
// Scale to 16bpp for ps16_2
// Otherwise to 34bpz
// Use zsc_15 instead
// ps_1 are the 15 bits for DSIZE
// ps_1[0] is 16 bis per pixel
always @*
casex ({c3d_15`D3_ZS, ps_15[0]})
2'b10: zsc_add = 2'b11; // Add 24 to exponent
2'b11: zsc_add = 2'b10; // Add 16 to exponent
default: zsc_add = 2'b00;
endcase
// Extract the Z.
assign z0_fp = vertex0_15u`VZW;
assign z1_fp = vertex1_15u`VZW;
assign z2_fp = vertex2_15u`VZW;
// detect z not zero
assign not_zero_z0 = |(z0_fp[30:0]);
assign not_zero_z1 = |(z1_fp[30:0]);
assign not_zero_z2 = |(z2_fp[30:0]);
// Add 16 or 24
assign p0z_fp = (not_zero_z0) ? {z0_fp[31], (z0_fp[30:26] + zsc_add), z0_fp[25:0]} : 32'h0;
assign p1z_fp = (not_zero_z1) ? {z1_fp[31], (z1_fp[30:26] + zsc_add), z1_fp[25:0]} : 32'h0;
assign p2z_fp = (not_zero_z2) ? {z2_fp[31], (z2_fp[30:26] + zsc_add), z2_fp[25:0]} : 32'h0;
// Extract uv.
assign u0_fp = vertex0_15u`VUW;
assign v0_fp = vertex0_15u`VVW;
assign u1_fp = vertex1_15u`VUW;
assign v1_fp = vertex1_15u`VVW;
assign u2_fp = vertex2_15u`VUW;
assign v2_fp = vertex2_15u`VVW;
// detect uv not zero
assign not_zero_u0 = |u0_fp[30:0];
assign not_zero_v0 = |v0_fp[30:0];
assign not_zero_u1 = |u1_fp[30:0];
assign not_zero_v1 = |v1_fp[30:0];
assign not_zero_u2 = |u2_fp[30:0];
assign not_zero_v2 = |v2_fp[30:0];
// U,V Scaling
// Use uvsc_15
// Use tex_15
assign p0uw_fp = (tex_15`T_SCL & not_zero_u0) ? {u0_fp[31], (u0_fp[30:23] + tex_15`T_MMSZX), u0_fp[22:0]} : u0_fp;
assign p0vw_fp = (tex_15`T_SCL & not_zero_v0) ? {v0_fp[31], (v0_fp[30:23] + tex_15`T_MMSZY), v0_fp[22:0]} : v0_fp;
assign p1uw_fp = (tex_15`T_SCL & not_zero_u1) ? {u1_fp[31], (u1_fp[30:23] + tex_15`T_MMSZX), u1_fp[22:0]} : u1_fp;
assign p1vw_fp = (tex_15`T_SCL & not_zero_v1) ? {v1_fp[31], (v1_fp[30:23] + tex_15`T_MMSZY), v1_fp[22:0]} : v1_fp;
assign p2uw_fp = (tex_15`T_SCL & not_zero_u2) ? {u2_fp[31], (u2_fp[30:23] + tex_15`T_MMSZX), u2_fp[22:0]} : u2_fp;
assign p2vw_fp = (tex_15`T_SCL & not_zero_v2) ? {v2_fp[31], (v2_fp[30:23] + tex_15`T_MMSZY), v2_fp[22:0]} : v2_fp;
// Merge in the changes.
assign vertex0_15 = {vertex0_15u[351:192], p0vw_fp, p0uw_fp, vertex0_15u[127:96], p0z_fp, vertex0_15u[63:0]};// Vertex 0.
assign vertex1_15 = {vertex1_15u[351:192], p1vw_fp, p1uw_fp, vertex1_15u[127:96], p1z_fp, vertex1_15u[63:0]};// Vertex 1.
assign vertex2_15 = {vertex2_15u[351:192], p2vw_fp, p2uw_fp, vertex2_15u[127:96], p2z_fp, vertex2_15u[63:0]};// Vertex 2.
always @(posedge de_clk, negedge de_rstn)
if(!de_rstn) begin
c3d_2 <= 32'h0;
tex_2 <= 32'h0;
actv_3d_2 <= 1'b0;
end
else if(load_actv_3d & (line_3d_15 | trian_3d_15)) begin
c3d_2 <= c3d_15; // 3D Control Register
tex_2 <= tex_15; // Texture Control Register
actv_3d_2 <= 1'b1;
end
// else if(!load_actvn & !(line_3d_15 | trian_3d_15)) begin
else if(~load_actvn & ~line_3d_15 & ~trian_3d_15) begin
c3d_2 <= 32'h0;
tex_2 <= 32'h0; // Texture Control Register
actv_3d_2 <= 1'b0;
end
always @(posedge de_clk, negedge de_rstn)
if(!de_rstn) begin
pptr3d_2 <= 32'h0;
lod_2 <= 210'h0;
zorg_2 <= 28'h0;
zptch_2 <= 12'h0;
tporg_2 <= 21'h0;
tptch_2 <= 12'h0;
hith_2 <= 32'h0;
yon_2 <= 32'h0;
fcol_2 <= 32'h0;
texbc_2 <= 32'h0;
key3dlo_2 <= 24'h0;
key3dhi_2 <= 24'h0;
blendc_2 <= 32'h0;
alpha_2 <= 24'h0;
acntrl_2 <= 18'h0;
end else if(load_actv_3d) begin
pptr3d_2 <= pptr3d_15;
lod_2 <= lod_15;
zorg_2 <= zorg_15;
zptch_2 <= zptch_15;
tporg_2 <= tporg_15;
tptch_2 <= tptch_15;
hith_2 <= hith_15;
yon_2 <= yon_15;
fcol_2 <= fcol_15;
texbc_2 <= texbc_15;
key3dlo_2 <= key3dlo_15;
key3dhi_2 <= key3dhi_15;
blendc_2 <= blendc_15;
alpha_2 <= alpha_15;
acntrl_2 <= acntrl_15;
end
always @* begin
cp_hb_dout = 32'h0;
case(hb_adr_r)
TPTCH: cp_hb_dout[11:0] = {tptch_1[11:4], tptch_1[3:0]};
ZPTCH: cp_hb_dout[11:0] = {zptch_1[11:4], zptch_1[3:0]};
ZORG: cp_hb_dout = zorg_1;
LOD0: cp_hb_dout[20:0] = lod0_r;
LOD1: cp_hb_dout[20:0] = lod1_r;
LOD2: cp_hb_dout[20:0] = lod2_r;
LOD3: cp_hb_dout[20:0] = lod3_r;
LOD4: cp_hb_dout[20:0] = lod4_r;
LOD5: cp_hb_dout[20:0] = lod5_r;
LOD6: cp_hb_dout[20:0] = lod6_r;
LOD7: cp_hb_dout[20:0] = lod7_r;
LOD8: cp_hb_dout[20:0] = lod8_r;
LOD9: cp_hb_dout[20:0] = lod9_r;
TPAL: cp_hb_dout[24:4] = tporg_1;
HITH: cp_hb_dout = hith_1;
YON: cp_hb_dout = yon_1;
FCOL: cp_hb_dout = fcol_1;
ALPHA: cp_hb_dout[23:0] = {atest_r, adstreg_r, asrcreg_r};
TBOARD: cp_hb_dout[31:0] = texbc_1;
KY3DLO: cp_hb_dout[23:0] = key3dlo_1;
KY3DHI: cp_hb_dout[23:0] = key3dhi_1;
BLENDC: cp_hb_dout[31:0] = blendc_1;
CP0: cp_hb_dout[31:0] = pptr3d_1;
CP1: cp_hb_dout[31:0] = vertex0_u`VXW; // V0X
CP2: cp_hb_dout[31:0] = vertex0_u`VYW; // V0Y
CP3: cp_hb_dout[31:0] = vertex0_u`VZW; // V0Z
CP4: cp_hb_dout[31:0] = vertex0_u`VWW; // V0W
CP5: cp_hb_dout[31:0] = {vertex0_u`VAB0, vertex0_u`VRB0, vertex0_u`VGB0, vertex0_u`VBB0}; // Color Int.
CP6: cp_hb_dout[31:0] = vertex0_u`VSW; // Fog, Rs, Gs, Bs.
CP7: cp_hb_dout[31:0] = vertex0_u`VUW; // V0U
CP8: cp_hb_dout[31:0] = vertex0_u`VVW; // V0V
CP9: cp_hb_dout[31:0] = vertex1_u`VXW; // V1X
CP10: cp_hb_dout[31:0] = vertex1_u`VYW; // V1Y
CP11: cp_hb_dout[31:0] = vertex1_u`VZW; // V1Z
CP12: cp_hb_dout[31:0] = vertex1_u`VWW; // V1W
CP13: cp_hb_dout[31:0] = {vertex1_u`VAB0, vertex1_u`VRB0, vertex1_u`VGB0, vertex1_u`VBB0}; // Color Int.
CP14: cp_hb_dout[31:0] = vertex1_u`VSW; // Fog, Rs, Gs, Bs.
CP15: cp_hb_dout[31:0] = vertex1_u`VUW; // V1U
CP16: cp_hb_dout[31:0] = vertex1_u`VVW; // V1V
CP17: cp_hb_dout[31:0] = vertex2_u`VXW; // V2X
CP18: cp_hb_dout[31:0] = vertex2_u`VYW; // V2Y
CP19: cp_hb_dout[31:0] = vertex2_u`VZW; // V2Z
CP20: cp_hb_dout[31:0] = vertex2_u`VWW; // V2W
CP21: cp_hb_dout[31:0] = {vertex2_u`VAB0, vertex2_u`VRB0, vertex2_u`VGB0, vertex2_u`VBB0}; // V2 Color Int.
CP22: cp_hb_dout[31:0] = vertex2_u`VSW; // Fog, Rs, Gs, Bs.
CP23: cp_hb_dout[31:0] = vertex2_u`VUW; // V2U
CP24: cp_hb_dout[31:0] = vertex2_u`VVW; // V2V
V0AF: cp_hb_dout[31:0] = vertex0_u`VAW;
V0RF: cp_hb_dout[31:0] = vertex0_u`VRW;
V0GF: cp_hb_dout[31:0] = vertex0_u`VGW;
V0BF: cp_hb_dout[31:0] = vertex0_u`VBW;
V1AF: cp_hb_dout[31:0] = vertex1_u`VAW;
V1RF: cp_hb_dout[31:0] = vertex1_u`VRW;
V1GF: cp_hb_dout[31:0] = vertex1_u`VGW;
V1BF: cp_hb_dout[31:0] = vertex1_u`VBW;
V2AF: cp_hb_dout[31:0] = vertex2_u`VAW;
V2RF: cp_hb_dout[31:0] = vertex2_u`VRW;
V2GF: cp_hb_dout[31:0] = vertex2_u`VGW;
V2BF: cp_hb_dout[31:0] = vertex2_u`VBW;
default: cp_hb_dout = 32'h0;
endcase
end
/************************************************************************/
/* vertex_sort is the vertex level sorter which muxes the vertices */
/* into the registers going into the setup engine. smallest vertex goes */
/* into output 0, largest into output 3. */
/************************************************************************/
function [1056:0] vertex_sort;
input [351:0] vertex2; // vertex 2
input [351:0] vertex1; // vertex 1
input [351:0] vertex0; // vertex 0
input trian_3d; // Executing a 3D triangle
input line_3d; // executing a 3D line
//////////////////////////////////////////////////////////////////////////
//
reg [351:0] vertex0_s;
reg [351:0] vertex1_s;
reg [351:0] vertex2_s;
reg cull_polarity; // 0 = sign, 1= ~sign
reg v0_lt_v1; // Vertex 0 is less than Vertex 1
reg v1_lt_v2; // Vertex 1 is less than Vertex 2
reg v0_lt_v2; // Vertex 0 is less than Vertex 2
begin
// Compare the Y values
v0_lt_v1 = fp_comp(vertex0`VYW, vertex1`VYW);
v1_lt_v2 = fp_comp(vertex1`VYW, vertex2`VYW);
v0_lt_v2 = fp_comp(vertex0`VYW, vertex2`VYW);
// cull mux
casex ({v0_lt_v1,v1_lt_v2,v0_lt_v2})
3'b000, 3'b001, 3'b110: cull_polarity = 1;
3'b010: cull_polarity = 0;
3'b011: cull_polarity = 1;
3'b100: cull_polarity = 0;
3'b101: cull_polarity = 1;
3'b111: cull_polarity = 0;
endcase
// Vertex MUX
casex ({line_3d,trian_3d,v0_lt_v1,v1_lt_v2,v0_lt_v2})
5'b01_000, 5'b01_001, 5'b01_110: begin vertex0_s = vertex2; vertex1_s = vertex1; vertex2_s = vertex0; end
5'b01_010: begin vertex0_s = vertex1; vertex1_s = vertex2; vertex2_s = vertex0; end
5'b01_011: begin vertex0_s = vertex1; vertex1_s = vertex0; vertex2_s = vertex2; end
5'b01_100: begin vertex0_s = vertex2; vertex1_s = vertex0; vertex2_s = vertex1; end
5'b01_101: begin vertex0_s = vertex0; vertex1_s = vertex2; vertex2_s = vertex1; end
5'b00_xxx,5'b01_111: begin vertex0_s = vertex0; vertex1_s = vertex1; vertex2_s = vertex2; end
// Lines
// 5'b10_x0x: begin vertex0_s = vertex2; vertex1_s = vertex2; vertex2_s = vertex1; end
// 5'b10_x1x: begin vertex0_s = vertex1; vertex1_s = vertex1; vertex2_s = vertex2; end
5'b1x_xxx: begin vertex0_s = vertex1; vertex1_s = vertex1; vertex2_s = vertex2; end
default: begin vertex0_s = 352'h0; vertex1_s = 352'h0; vertex2_s = 352'h0; end
endcase
vertex_sort = {cull_polarity, vertex2_s, vertex1_s, vertex0_s};
end
endfunction
// Floating Point less than magnitude comparator.
// This module takes two IEEE single precision floating point and does a
// Comparison to determine ehich is smaller.
function fp_comp;
input [31:0] fp1; // IEEE floating point input
input [31:0] fp2; // IEEE floating point input
// Figure out which one is smaller
begin
casex({fp1[31],fp2[31], (fp1[30:23] < fp2[30:23]), (fp1[30:23] == fp2[30:23]), (fp1[22:0] < fp2[22:0])})
5'b10_xxx: fp_comp = 1; // fp1 is neg and fp2 is pos
5'b01_xxx: fp_comp = 0; // fp1 is pos and fp2 is neg
5'b00_1xx: fp_comp = 1; // exp1 < exp2
5'b00_00x: fp_comp = 0; // exp1 > exp2
5'b00_011: fp_comp = 1; // exp1 = exp2, mant1 < mant2
5'b00_010: fp_comp = 0; // exp1 = exp2, mant1 >= mant2
5'b11_1xx: fp_comp = 0; // exp1 < exp2
5'b11_00x: fp_comp = 1; // exp1 > exp2
5'b11_011: fp_comp = 0; // exp1 = exp2, mant1 < mant2
5'b11_010: fp_comp = 1; // exp1 = exp2, mant1 >= mant2
endcase
end
endfunction
//////////////////////////////////////////////////////////////////////////////
// Simulation debug stuff.
`ifdef RTL_SIM
always @* begin
if (go_sup) begin
$display($stime, " Executing 3D Command\n");
// $display("\t\tFORE: %h", fore_1);
// $display("\t\tBACK: %h", back_1);
// $display("\t\tXY0: %h", xy0_1);
// $display("\t\tTPTCH: cp_hb_dout[11:0] = {tptch_1[11:4], tptch_1[3:0]};
// $display("\t\tZPTCH: cp_hb_dout[11:0] = {zptch_1[11:4], zptch_1[3:0]};
// $display("\t\tZORG: cp_hb_dout = zorg_1;
// $display("\t\tLOD0: cp_hb_dout[20:0] = lod0_r;
// $display("\t\tLOD1: cp_hb_dout[20:0] = lod1_r;
// $display("\t\tLOD2: cp_hb_dout[20:0] = lod2_r;
// $display("\t\tLOD3: cp_hb_dout[20:0] = lod3_r;
// $display("\t\tLOD4: cp_hb_dout[20:0] = lod4_r;
// $display("\t\tLOD5: cp_hb_dout[20:0] = lod5_r;
// $display("\t\tLOD6: cp_hb_dout[20:0] = lod6_r;
// $display("\t\tLOD7: cp_hb_dout[20:0] = lod7_r;
// $display("\t\tLOD8: cp_hb_dout[20:0] = lod8_r;
// $display("\t\tLOD9: cp_hb_dout[20:0] = lod9_r;
// $display("\t\tTPAL: cp_hb_dout[24:4] = tporg_1;
// $display("\t\tHITH: cp_hb_dout[24:4] = hith_1;
// $display("\t\tYON: cp_hb_dout = yon_1;
// $display("\t\tFCOL: cp_hb_dout = fcol_1;
// $display("\t\tALPHA: cp_hb_dout[23:0] = {atest_r, adstreg_r, asrcreg_r};
// $display("\t\tTBOARD: cp_hb_dout[31:0] = texbc_1;
// $display("\t\tKY3DLO: cp_hb_dout[23:0] = key3dlo_1;
// $display("\t\tKY3DHI: cp_hb_dout[23:0] = key3dhi_1;
// $display("\t\tBLENDC: cp_hb_dout[31:0] = blendc_1;
$display("\t\tPPTR3D: %h", pptr3d_1);
$display("\t\tV0X: %h", vertex0_u`VXW); // V0X
$display("\t\tVOY: %h", vertex0_u`VYW); // V0Y
$display("\t\tV0Z: %h", vertex0_u`VZW); // V0Z
$display("\t\tV0W: %h", vertex0_u`VWW); // V0W
$display("\t\tV0CI: %h", {vertex0_u`VAB0, vertex0_u`VRB0, vertex0_u`VGB0, vertex0_u`VBB0}); // Color Int.
$display("\t\tV0S: %h", vertex0_u`VSW); // Fog, Rs, Gs, Bs.
$display("\t\tV0U: %h", vertex0_u`VUW); // V0U
$display("\t\tV0V: %h", vertex0_u`VVW); // V0V
$display("\t\tV1X: %h", vertex1_u`VXW); // V1X
$display("\t\tV1Y: %h", vertex1_u`VYW); // V1Y
$display("\t\tV1Z: %h", vertex1_u`VZW); // V1Z
$display("\t\tV1W: %h", vertex1_u`VWW); // V1W
$display("\t\tV1CI: %h", {vertex1_u`VAB0, vertex1_u`VRB0, vertex1_u`VGB0, vertex1_u`VBB0}); // Color Int.
$display("\t\tV1S: %h", vertex1_u`VSW); // Fog, Rs, Gs, Bs.
$display("\t\tV1U: %h", vertex1_u`VUW); // V1U
$display("\t\tV1V: %h", vertex1_u`VVW); // V1V
$display("\t\tV2X: %h", vertex2_u`VXW); // V2X
$display("\t\tV2Y: %h", vertex2_u`VYW); // V2Y
$display("\t\tV2Z: %h", vertex2_u`VZW); // V2Z
$display("\t\tV2W: %h", vertex2_u`VWW); // V2W
$display("\t\tV2CI: %h", {vertex2_u`VAB0, vertex2_u`VRB0, vertex2_u`VGB0, vertex2_u`VBB0}); // Color Int.
$display("\t\tV2S: %h", vertex2_u`VSW); // Fog, Rs, Gs, Bs.
$display("\t\tV2U: %h", vertex2_u`VUW); // V2U
$display("\t\tV2V: %h", vertex2_u`VVW); // V2V
$display("\t\tV0AF: %h", vertex0_u`VAW);
$display("\t\tV0RF: %h", vertex0_u`VRW);
$display("\t\tV0GF: %h", vertex0_u`VGW);
$display("\t\tV0BF: %h", vertex0_u`VBW);
$display("\t\tV1AF: %h", vertex1_u`VAW);
$display("\t\tV1RF: %h", vertex1_u`VRW);
$display("\t\tV1GF: %h", vertex1_u`VGW);
$display("\t\tV1BF: %h", vertex1_u`VBW);
$display("\t\tV2AF: %h", vertex2_u`VAW);
$display("\t\tV2RF: %h", vertex2_u`VRW);
$display("\t\tV2GF: %h", vertex2_u`VGW);
$display("\t\tV2BF: %h", vertex2_u`VBW);
end // if (cmdack)
end // always @ *
`endif
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_delay_cntrl (
// delay interface
delay_clk,
delay_rst,
delay_locked,
// io interface
up_dld,
up_dwdata,
up_drdata,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter DATA_WIDTH = 8;
parameter BASE_ADDRESS = 6'h02;
// delay interface
input delay_clk;
output delay_rst;
input delay_locked;
// io interface
output [(DATA_WIDTH-1):0] up_dld;
output [((DATA_WIDTH*5)-1):0] up_dwdata;
input [((DATA_WIDTH*5)-1):0] up_drdata;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_preset = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_dlocked_m1 = 'd0;
reg up_dlocked = 'd0;
reg [(DATA_WIDTH-1):0] up_dld = 'd0;
reg [((DATA_WIDTH*5)-1):0] up_dwdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 4:0] up_rdata_s;
wire [(DATA_WIDTH-1):0] up_drdata4_s;
wire [(DATA_WIDTH-1):0] up_drdata3_s;
wire [(DATA_WIDTH-1):0] up_drdata2_s;
wire [(DATA_WIDTH-1):0] up_drdata1_s;
wire [(DATA_WIDTH-1):0] up_drdata0_s;
// variables
genvar n;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0;
assign up_rdata_s[4] = | up_drdata4_s;
assign up_rdata_s[3] = | up_drdata3_s;
assign up_rdata_s[2] = | up_drdata2_s;
assign up_rdata_s[1] = | up_drdata1_s;
assign up_rdata_s[0] = | up_drdata0_s;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_drd
assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0;
assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0;
assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0;
assign up_drdata1_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+1)] : 1'd0;
assign up_drdata0_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+0)] : 1'd0;
end
endgenerate
// processor interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_preset <= 1'd1;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
up_dlocked_m1 <= 'd0;
up_dlocked <= 'd0;
end else begin
up_preset <= 1'd0;
up_wack <= up_wreq_s;
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
if (up_dlocked == 1'b0) begin
up_rdata <= 32'hffffffff;
end else begin
up_rdata <= {27'd0, up_rdata_s};
end
end else begin
up_rdata <= 32'd0;
end
up_dlocked_m1 <= delay_locked;
up_dlocked <= up_dlocked_m1;
end
end
// write does not hold- read back what goes into effect.
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dld[n] <= 'd0;
up_dwdata[((n*5)+4):(n*5)] <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
up_dld[n] <= 1'd1;
up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
end else begin
up_dld[n] <= 1'd0;
up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
end
end
end
end
endgenerate
// resets
ad_rst i_delay_rst_reg (
.preset (up_preset),
.clk (delay_clk),
.rst (delay_rst));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_4_V
`define SKY130_FD_SC_HS__A22O_4_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_4_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "riffa.vh"
module channel
#(
parameter C_DATA_WIDTH = 128,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
generate
if(C_DATA_WIDTH == 32) begin
channel_32
#(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(/*AUTOINST*/
// Outputs
.SG_RX_BUF_RECVD (SG_RX_BUF_RECVD),
.SG_TX_BUF_RECVD (SG_TX_BUF_RECVD),
.TXN_RX_DONE_LEN (TXN_RX_DONE_LEN[31:0]),
.TXN_RX_DONE (TXN_RX_DONE),
.TXN_TX (TXN_TX),
.TXN_TX_LEN (TXN_TX_LEN[31:0]),
.TXN_TX_OFF_LAST (TXN_TX_OFF_LAST[31:0]),
.TXN_TX_DONE_LEN (TXN_TX_DONE_LEN[31:0]),
.TXN_TX_DONE (TXN_TX_DONE),
.RX_REQ (RX_REQ),
.RX_REQ_TAG (RX_REQ_TAG[1:0]),
.RX_REQ_ADDR (RX_REQ_ADDR[63:0]),
.RX_REQ_LEN (RX_REQ_LEN[9:0]),
.TX_REQ (TX_REQ),
.TX_ADDR (TX_ADDR[63:0]),
.TX_LEN (TX_LEN[9:0]),
.TX_DATA (TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX (CHNL_RX),
.CHNL_RX_LAST (CHNL_RX_LAST),
.CHNL_RX_LEN (CHNL_RX_LEN[31:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[30:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID),
.CHNL_TX_ACK (CHNL_TX_ACK),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN),
// Inputs
.CLK (CLK),
.RST (RST),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.PIO_DATA (PIO_DATA[31:0]),
.ENG_DATA (ENG_DATA[C_DATA_WIDTH-1:0]),
.SG_RX_BUF_LEN_VALID (SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID (SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID (SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_LEN_VALID (SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID (SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID (SG_TX_BUF_ADDR_LO_VALID),
.TXN_RX_LEN_VALID (TXN_RX_LEN_VALID),
.TXN_RX_OFF_LAST_VALID (TXN_RX_OFF_LAST_VALID),
.TXN_RX_DONE_ACK (TXN_RX_DONE_ACK),
.TXN_TX_ACK (TXN_TX_ACK),
.TXN_TX_DONE_ACK (TXN_TX_DONE_ACK),
.RX_REQ_ACK (RX_REQ_ACK),
.TX_REQ_ACK (TX_REQ_ACK),
.TX_DATA_REN (TX_DATA_REN),
.TX_SENT (TX_SENT),
.MAIN_DATA_EN (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.MAIN_DONE (MAIN_DONE),
.MAIN_ERR (MAIN_ERR),
.SG_RX_DATA_EN (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_RX_DONE (SG_RX_DONE),
.SG_RX_ERR (SG_RX_ERR),
.SG_TX_DATA_EN (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_TX_DONE (SG_TX_DONE),
.SG_TX_ERR (SG_TX_ERR),
.CHNL_RX_CLK (CHNL_RX_CLK),
.CHNL_RX_ACK (CHNL_RX_ACK),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN),
.CHNL_TX_CLK (CHNL_TX_CLK),
.CHNL_TX (CHNL_TX),
.CHNL_TX_LAST (CHNL_TX_LAST),
.CHNL_TX_LEN (CHNL_TX_LEN[31:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[30:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID));
end else if(C_DATA_WIDTH == 64) begin
channel_64
#(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(/*AUTOINST*/
// Outputs
.SG_RX_BUF_RECVD (SG_RX_BUF_RECVD),
.SG_TX_BUF_RECVD (SG_TX_BUF_RECVD),
.TXN_RX_DONE_LEN (TXN_RX_DONE_LEN[31:0]),
.TXN_RX_DONE (TXN_RX_DONE),
.TXN_TX (TXN_TX),
.TXN_TX_LEN (TXN_TX_LEN[31:0]),
.TXN_TX_OFF_LAST (TXN_TX_OFF_LAST[31:0]),
.TXN_TX_DONE_LEN (TXN_TX_DONE_LEN[31:0]),
.TXN_TX_DONE (TXN_TX_DONE),
.RX_REQ (RX_REQ),
.RX_REQ_TAG (RX_REQ_TAG[1:0]),
.RX_REQ_ADDR (RX_REQ_ADDR[63:0]),
.RX_REQ_LEN (RX_REQ_LEN[9:0]),
.TX_REQ (TX_REQ),
.TX_ADDR (TX_ADDR[63:0]),
.TX_LEN (TX_LEN[9:0]),
.TX_DATA (TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX (CHNL_RX),
.CHNL_RX_LAST (CHNL_RX_LAST),
.CHNL_RX_LEN (CHNL_RX_LEN[31:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[30:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID),
.CHNL_TX_ACK (CHNL_TX_ACK),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN),
// Inputs
.CLK (CLK),
.RST (RST),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.PIO_DATA (PIO_DATA[31:0]),
.ENG_DATA (ENG_DATA[C_DATA_WIDTH-1:0]),
.SG_RX_BUF_LEN_VALID (SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID (SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID (SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_LEN_VALID (SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID (SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID (SG_TX_BUF_ADDR_LO_VALID),
.TXN_RX_LEN_VALID (TXN_RX_LEN_VALID),
.TXN_RX_OFF_LAST_VALID (TXN_RX_OFF_LAST_VALID),
.TXN_RX_DONE_ACK (TXN_RX_DONE_ACK),
.TXN_TX_ACK (TXN_TX_ACK),
.TXN_TX_DONE_ACK (TXN_TX_DONE_ACK),
.RX_REQ_ACK (RX_REQ_ACK),
.TX_REQ_ACK (TX_REQ_ACK),
.TX_DATA_REN (TX_DATA_REN),
.TX_SENT (TX_SENT),
.MAIN_DATA_EN (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.MAIN_DONE (MAIN_DONE),
.MAIN_ERR (MAIN_ERR),
.SG_RX_DATA_EN (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_RX_DONE (SG_RX_DONE),
.SG_RX_ERR (SG_RX_ERR),
.SG_TX_DATA_EN (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_TX_DONE (SG_TX_DONE),
.SG_TX_ERR (SG_TX_ERR),
.CHNL_RX_CLK (CHNL_RX_CLK),
.CHNL_RX_ACK (CHNL_RX_ACK),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN),
.CHNL_TX_CLK (CHNL_TX_CLK),
.CHNL_TX (CHNL_TX),
.CHNL_TX_LAST (CHNL_TX_LAST),
.CHNL_TX_LEN (CHNL_TX_LEN[31:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[30:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID));
end else if(C_DATA_WIDTH == 128) begin
channel_128
#(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(/*AUTOINST*/
// Outputs
.SG_RX_BUF_RECVD (SG_RX_BUF_RECVD),
.SG_TX_BUF_RECVD (SG_TX_BUF_RECVD),
.TXN_RX_DONE_LEN (TXN_RX_DONE_LEN[31:0]),
.TXN_RX_DONE (TXN_RX_DONE),
.TXN_TX (TXN_TX),
.TXN_TX_LEN (TXN_TX_LEN[31:0]),
.TXN_TX_OFF_LAST (TXN_TX_OFF_LAST[31:0]),
.TXN_TX_DONE_LEN (TXN_TX_DONE_LEN[31:0]),
.TXN_TX_DONE (TXN_TX_DONE),
.RX_REQ (RX_REQ),
.RX_REQ_TAG (RX_REQ_TAG[1:0]),
.RX_REQ_ADDR (RX_REQ_ADDR[63:0]),
.RX_REQ_LEN (RX_REQ_LEN[9:0]),
.TX_REQ (TX_REQ),
.TX_ADDR (TX_ADDR[63:0]),
.TX_LEN (TX_LEN[9:0]),
.TX_DATA (TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX (CHNL_RX),
.CHNL_RX_LAST (CHNL_RX_LAST),
.CHNL_RX_LEN (CHNL_RX_LEN[31:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[30:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID),
.CHNL_TX_ACK (CHNL_TX_ACK),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN),
// Inputs
.CLK (CLK),
.RST (RST),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.PIO_DATA (PIO_DATA[31:0]),
.ENG_DATA (ENG_DATA[C_DATA_WIDTH-1:0]),
.SG_RX_BUF_LEN_VALID (SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID (SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID (SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_LEN_VALID (SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID (SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID (SG_TX_BUF_ADDR_LO_VALID),
.TXN_RX_LEN_VALID (TXN_RX_LEN_VALID),
.TXN_RX_OFF_LAST_VALID (TXN_RX_OFF_LAST_VALID),
.TXN_RX_DONE_ACK (TXN_RX_DONE_ACK),
.TXN_TX_ACK (TXN_TX_ACK),
.TXN_TX_DONE_ACK (TXN_TX_DONE_ACK),
.RX_REQ_ACK (RX_REQ_ACK),
.TX_REQ_ACK (TX_REQ_ACK),
.TX_DATA_REN (TX_DATA_REN),
.TX_SENT (TX_SENT),
.MAIN_DATA_EN (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.MAIN_DONE (MAIN_DONE),
.MAIN_ERR (MAIN_ERR),
.SG_RX_DATA_EN (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_RX_DONE (SG_RX_DONE),
.SG_RX_ERR (SG_RX_ERR),
.SG_TX_DATA_EN (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_TX_DONE (SG_TX_DONE),
.SG_TX_ERR (SG_TX_ERR),
.CHNL_RX_CLK (CHNL_RX_CLK),
.CHNL_RX_ACK (CHNL_RX_ACK),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN),
.CHNL_TX_CLK (CHNL_TX_CLK),
.CHNL_TX (CHNL_TX),
.CHNL_TX_LAST (CHNL_TX_LAST),
.CHNL_TX_LEN (CHNL_TX_LEN[31:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[30:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID));
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "import")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_2_V
`define SKY130_FD_SC_LS__SEDFXBP_2_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxbp_2 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__AND4_FUNCTIONAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_FUNCTIONAL_V |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "cpu_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "cpu_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module cpu_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_jesd_align_1 (
// jesd interface
rx_clk,
rx_sof,
rx_eof,
rx_ferr,
rx_fdata,
// aligned data
rx_err,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_sof;
input [ 3:0] rx_eof;
input [ 3:0] rx_ferr;
input [31:0] rx_fdata;
// aligned data
output rx_err;
output [31:0] rx_data;
reg rx_err = 'd0;
reg [31:0] rx_data = 'd0;
wire rx_err_s;
// error conditions- sof & eof are the same - 1 byte per frame!
assign rx_err_s = ((rx_sof == rx_eof) && (rx_ferr == 4'd0)) ? 1'b0 : 1'b1;
// 1 bytes per frame - so only 1 combination
always @(posedge rx_clk) begin
case (rx_sof)
4'b1111: begin
rx_err <= rx_err_s;
rx_data <= rx_fdata;
end
default: begin
rx_err <= 1'b1;
rx_data <= 32'hffff;
end
endcase
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_PP_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_PP_V |
/**
# CordicRectToPolar_tb - Tests CordicRectToPolar #
Only tests with full amplitude x & y. Smaller amplitudes will yield larger angle
& magnitude errors. It is assumed that an implementation that satisfies at full
amplitude will perform the same algorithm at smaller amplitudes.
Test parameters let one set desired criteria for passing.
*/
module CordicRectToPolar_tb ();
//////////////////////////////////////////////////////////////////////////////
// UUT Parameters
//////////////////////////////////////////////////////////////////////////////
parameter IN_WIDTH = 16; ///< Input coordinate pair width
parameter ANGLE_WIDTH = 16; ///< Output angle register width
parameter SCALE_MAGNITUDE = 0; ///< Set to 1 to scale magnitude to true value
parameter MULT_WIDTH = 16; ///< Number of bits to use for magnitude scaling word, if SCALE_MAGNITUDE is 1
//////////////////////////////////////////////////////////////////////////////
// UUT Signal Declarations
//////////////////////////////////////////////////////////////////////////////
reg clk; ///< System clock
reg rst; ///< Reset, active high and synchronous
reg inStrobe; ///< Input data strobe
reg signed [IN_WIDTH-1:0] x; ///< X coordinate
reg signed [IN_WIDTH-1:0] y; ///< Y coordinate
wire [ANGLE_WIDTH-1:0] angle; ///< Angle
wire signed [IN_WIDTH:0] magnitude; ///< Magnitude
wire outStrobe; ///< Output data strobe
//////////////////////////////////////////////////////////////////////////////
// Test Parameter Declarations
//////////////////////////////////////////////////////////////////////////////
parameter ITER_NUM = (IN_WIDTH > (ANGLE_WIDTH-1)) ? (ANGLE_WIDTH-1) : IN_WIDTH;
parameter M_PI = $acos(-1.0);
// Goals
parameter TEST_ANGLES = 2048;
parameter MAX_ANGLE_ERR_AVG = 3.0;
parameter MAX_ANGLE_ERR_STD_DEV = 3.0;
parameter MAX_MAGNITUDE_ERR_AVG = 3.0;
parameter MAX_MAGNITUDE_ERR_STD_DEV = 3.0;
//////////////////////////////////////////////////////////////////////////////
// Test Signal Declarations
//////////////////////////////////////////////////////////////////////////////
reg signed [IN_WIDTH:0] magSamples [TEST_ANGLES-1:0];
reg signed [ANGLE_WIDTH-1:0] angSamples [TEST_ANGLES-1:0];
real angleErrAvg;
real angleErrStdDev;
real magnitudeErrAvg;
real magnitudeErrStdDev;
real realX;
real realY;
real realAngle;
real realMagnitude;
real MAG_SCALAR;
integer i;
integer seed;
integer pass;
//////////////////////////////////////////////////////////////////////////////
// Test Code
//////////////////////////////////////////////////////////////////////////////
function real abs (
input real val
);
begin
abs = (val < 0) ? -val : val;
end
endfunction
always #1 clk = ~clk;
initial begin
// Initialize variables
pass = 1;
clk = 1'b0;
rst = 1'b1;
inStrobe = 1'b0;
x = 'd0;
y = 'd0;
MAG_SCALAR = 1.0;
seed = 345;
for (i=0; i<ITER_NUM; i=i+1) begin
MAG_SCALAR = MAG_SCALAR * (1.0 + 2.0**(-2.0*i))**(-0.5);
end
angleErrAvg = 0.0;
angleErrStdDev = 0.0;
magnitudeErrAvg = 0.0;
magnitudeErrStdDev = 0.0;
// Reset module
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b0;
@(posedge clk) rst = 1'b0;
// Gather data
realMagnitude = 2.0**(IN_WIDTH-1)-1;
for (i=0; i<TEST_ANGLES; i=i+1) begin
realAngle = $dist_uniform(seed, 0, (1<<ANGLE_WIDTH)-1) * 2.0 * M_PI / (1<<ANGLE_WIDTH);
realX = realMagnitude * $cos(realAngle);
realY = realMagnitude * $sin(realAngle);
x = $rtoi(realX+0.5);
y = $rtoi(realY+0.5);
@(posedge clk) inStrobe = 1'b1;
@(posedge clk) inStrobe = 1'b0;
wait(outStrobe);
if (SCALE_MAGNITUDE) begin
magSamples[i] = $itor(magnitude) - realMagnitude;
end
else begin
magSamples[i] = $itor(magnitude) - realMagnitude / MAG_SCALAR;
end
angSamples[i] = $itor(angle) - (realAngle*2.0**(ANGLE_WIDTH-1)/M_PI);
magnitudeErrAvg = magnitudeErrAvg + magSamples[i];
angleErrAvg = angleErrAvg + angSamples[i];
wait(~outStrobe);
end
// Calculate mean & standard deviation
angleErrAvg = angleErrAvg / TEST_ANGLES;
magnitudeErrAvg = magnitudeErrAvg / TEST_ANGLES;
for (i=0; i<TEST_ANGLES; i=i+1) begin
angleErrStdDev = angleErrStdDev + (angSamples[i] - angleErrAvg)**(2.0);
magnitudeErrStdDev = magnitudeErrStdDev + (magSamples[i] - magnitudeErrAvg)**(2.0);
end
angleErrStdDev = $sqrt(angleErrStdDev / (TEST_ANGLES-1));
magnitudeErrStdDev = $sqrt(magnitudeErrStdDev / (TEST_ANGLES-1));
$display("Number of angle bits: %d", ANGLE_WIDTH);
$display("Number of input bits: %d", IN_WIDTH);
$display("Magnitude Average Error: %f", magnitudeErrAvg);
$display("Magnitude Standard Deviation of Error: %f", magnitudeErrStdDev);
$display("Angle Average Error: %f", angleErrAvg);
$display("Angle Standard Deviation of Error: %f", angleErrStdDev);
if (abs(magnitudeErrAvg) > MAX_MAGNITUDE_ERR_AVG) begin
pass = 0;
$display("FAIL: Magnitude average error is too high");
end
if (magnitudeErrStdDev > MAX_MAGNITUDE_ERR_STD_DEV) begin
pass = 0;
$display("FAIL: Magnitude standard deviation is too high");
end
if (abs(angleErrAvg) > MAX_ANGLE_ERR_AVG) begin
pass = 0;
$display("FAIL: angle average error is too high");
end
if (angleErrStdDev > MAX_ANGLE_ERR_STD_DEV) begin
pass = 0;
$display("FAIL: angle standard deviation is too high");
end
if (pass) begin
$display("PASS");
end
$stop;
end
//////////////////////////////////////////////////////////////////////////////
// UUT
//////////////////////////////////////////////////////////////////////////////
CordicRectToPolar #(
.IN_WIDTH (IN_WIDTH ), ///< Input coordinate pair width
.ANGLE_WIDTH (ANGLE_WIDTH ), ///< Output angle register width
.SCALE_MAGNITUDE(SCALE_MAGNITUDE), ///< Set to 1 to scale magnitude to true value
.MULT_WIDTH (MULT_WIDTH ) ///< Number of bits to use for magnitude scaling word, if SCALE_MAGNITUDE is 1
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.inStrobe(inStrobe), ///< Input data strobe
.x(x), ///< [IN_WIDTH-1:0] X coordinate
.y(y), ///< [IN_WIDTH-1:0] Y coordinate
.angle(angle), ///< [ANGLE_WIDTH-1:0] Angle
.magnitude(magnitude), ///< [IN_WIDTH:0] Magnitude
.outStrobe(outStrobe) ///< Output data strobe
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: regfileparam_synthesis.v
// /___/ /\ Timestamp: Sun Apr 05 19:24:18 2015
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -tm regfileparamsynthesis -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim regfileparam.ngc regfileparam_synthesis.v
// Device : xc6slx16-3-csg324
// Input file : regfileparam.ngc
// Output file : C:\Users\Joseph\Documents\Xilinx\HW2\netgen\synthesis\regfileparam_synthesis.v
// # of Modules : 1
// Design Name : regfileparam
// Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module regfileparamsynthesis (
wren, clk, rst, ra, rb, rw, wdat, adat, bdat
);
input wren;
input clk;
input rst;
input [3 : 0] ra;
input [3 : 0] rb;
input [3 : 0] rw;
input [15 : 0] wdat;
output [15 : 0] adat;
output [15 : 0] bdat;
wire ra_3_IBUF_0;
wire ra_2_IBUF_1;
wire ra_1_IBUF_2;
wire ra_0_IBUF_3;
wire rb_3_IBUF_4;
wire rb_2_IBUF_5;
wire rb_1_IBUF_6;
wire rb_0_IBUF_7;
wire rw_3_IBUF_8;
wire rw_2_IBUF_9;
wire rw_1_IBUF_10;
wire rw_0_IBUF_11;
wire wdat_15_IBUF_12;
wire wdat_14_IBUF_13;
wire wdat_13_IBUF_14;
wire wdat_12_IBUF_15;
wire wdat_11_IBUF_16;
wire wdat_10_IBUF_17;
wire wdat_9_IBUF_18;
wire wdat_8_IBUF_19;
wire wdat_7_IBUF_20;
wire wdat_6_IBUF_21;
wire wdat_5_IBUF_22;
wire wdat_4_IBUF_23;
wire wdat_3_IBUF_24;
wire wdat_2_IBUF_25;
wire wdat_1_IBUF_26;
wire wdat_0_IBUF_27;
wire wren_IBUF_28;
wire clk_BUFGP_29;
wire rst_IBUF_30;
wire adat_15_OBUF_31;
wire adat_14_OBUF_32;
wire adat_13_OBUF_33;
wire adat_12_OBUF_34;
wire adat_11_OBUF_35;
wire adat_10_OBUF_36;
wire adat_9_OBUF_37;
wire adat_8_OBUF_38;
wire adat_7_OBUF_39;
wire adat_6_OBUF_40;
wire adat_5_OBUF_41;
wire adat_4_OBUF_42;
wire adat_3_OBUF_43;
wire adat_2_OBUF_44;
wire adat_1_OBUF_45;
wire adat_0_OBUF_46;
wire bdat_15_OBUF_47;
wire bdat_14_OBUF_48;
wire bdat_13_OBUF_49;
wire bdat_12_OBUF_50;
wire bdat_11_OBUF_51;
wire bdat_10_OBUF_52;
wire bdat_9_OBUF_53;
wire bdat_8_OBUF_54;
wire bdat_7_OBUF_55;
wire bdat_6_OBUF_56;
wire bdat_5_OBUF_57;
wire bdat_4_OBUF_58;
wire bdat_3_OBUF_59;
wire bdat_2_OBUF_60;
wire bdat_1_OBUF_61;
wire bdat_0_OBUF_62;
wire \GEN_REGS[0].regs/Q<15> ;
wire \GEN_REGS[0].regs/Q<14> ;
wire \GEN_REGS[0].regs/Q<13> ;
wire \GEN_REGS[0].regs/Q<12> ;
wire \GEN_REGS[0].regs/Q<11> ;
wire \GEN_REGS[0].regs/Q<10> ;
wire \GEN_REGS[0].regs/Q<9> ;
wire \GEN_REGS[0].regs/Q<8> ;
wire \GEN_REGS[0].regs/Q<7> ;
wire \GEN_REGS[0].regs/Q<6> ;
wire \GEN_REGS[0].regs/Q<5> ;
wire \GEN_REGS[0].regs/Q<4> ;
wire \GEN_REGS[0].regs/Q<3> ;
wire \GEN_REGS[0].regs/Q<2> ;
wire \GEN_REGS[0].regs/Q<1> ;
wire \GEN_REGS[0].regs/Q<0> ;
wire \GEN_REGS[1].regs/Q<15> ;
wire \GEN_REGS[1].regs/Q<14> ;
wire \GEN_REGS[1].regs/Q<13> ;
wire \GEN_REGS[1].regs/Q<12> ;
wire \GEN_REGS[1].regs/Q<11> ;
wire \GEN_REGS[1].regs/Q<10> ;
wire \GEN_REGS[1].regs/Q<9> ;
wire \GEN_REGS[1].regs/Q<8> ;
wire \GEN_REGS[1].regs/Q<7> ;
wire \GEN_REGS[1].regs/Q<6> ;
wire \GEN_REGS[1].regs/Q<5> ;
wire \GEN_REGS[1].regs/Q<4> ;
wire \GEN_REGS[1].regs/Q<3> ;
wire \GEN_REGS[1].regs/Q<2> ;
wire \GEN_REGS[1].regs/Q<1> ;
wire \GEN_REGS[1].regs/Q<0> ;
wire \GEN_REGS[2].regs/Q<15> ;
wire \GEN_REGS[2].regs/Q<14> ;
wire \GEN_REGS[2].regs/Q<13> ;
wire \GEN_REGS[2].regs/Q<12> ;
wire \GEN_REGS[2].regs/Q<11> ;
wire \GEN_REGS[2].regs/Q<10> ;
wire \GEN_REGS[2].regs/Q<9> ;
wire \GEN_REGS[2].regs/Q<8> ;
wire \GEN_REGS[2].regs/Q<7> ;
wire \GEN_REGS[2].regs/Q<6> ;
wire \GEN_REGS[2].regs/Q<5> ;
wire \GEN_REGS[2].regs/Q<4> ;
wire \GEN_REGS[2].regs/Q<3> ;
wire \GEN_REGS[2].regs/Q<2> ;
wire \GEN_REGS[2].regs/Q<1> ;
wire \GEN_REGS[2].regs/Q<0> ;
wire \GEN_REGS[3].regs/Q<15> ;
wire \GEN_REGS[3].regs/Q<14> ;
wire \GEN_REGS[3].regs/Q<13> ;
wire \GEN_REGS[3].regs/Q<12> ;
wire \GEN_REGS[3].regs/Q<11> ;
wire \GEN_REGS[3].regs/Q<10> ;
wire \GEN_REGS[3].regs/Q<9> ;
wire \GEN_REGS[3].regs/Q<8> ;
wire \GEN_REGS[3].regs/Q<7> ;
wire \GEN_REGS[3].regs/Q<6> ;
wire \GEN_REGS[3].regs/Q<5> ;
wire \GEN_REGS[3].regs/Q<4> ;
wire \GEN_REGS[3].regs/Q<3> ;
wire \GEN_REGS[3].regs/Q<2> ;
wire \GEN_REGS[3].regs/Q<1> ;
wire \GEN_REGS[3].regs/Q<0> ;
wire \GEN_REGS[4].regs/Q<15> ;
wire \GEN_REGS[4].regs/Q<14> ;
wire \GEN_REGS[4].regs/Q<13> ;
wire \GEN_REGS[4].regs/Q<12> ;
wire \GEN_REGS[4].regs/Q<11> ;
wire \GEN_REGS[4].regs/Q<10> ;
wire \GEN_REGS[4].regs/Q<9> ;
wire \GEN_REGS[4].regs/Q<8> ;
wire \GEN_REGS[4].regs/Q<7> ;
wire \GEN_REGS[4].regs/Q<6> ;
wire \GEN_REGS[4].regs/Q<5> ;
wire \GEN_REGS[4].regs/Q<4> ;
wire \GEN_REGS[4].regs/Q<3> ;
wire \GEN_REGS[4].regs/Q<2> ;
wire \GEN_REGS[4].regs/Q<1> ;
wire \GEN_REGS[4].regs/Q<0> ;
wire \GEN_REGS[5].regs/Q<15> ;
wire \GEN_REGS[5].regs/Q<14> ;
wire \GEN_REGS[5].regs/Q<13> ;
wire \GEN_REGS[5].regs/Q<12> ;
wire \GEN_REGS[5].regs/Q<11> ;
wire \GEN_REGS[5].regs/Q<10> ;
wire \GEN_REGS[5].regs/Q<9> ;
wire \GEN_REGS[5].regs/Q<8> ;
wire \GEN_REGS[5].regs/Q<7> ;
wire \GEN_REGS[5].regs/Q<6> ;
wire \GEN_REGS[5].regs/Q<5> ;
wire \GEN_REGS[5].regs/Q<4> ;
wire \GEN_REGS[5].regs/Q<3> ;
wire \GEN_REGS[5].regs/Q<2> ;
wire \GEN_REGS[5].regs/Q<1> ;
wire \GEN_REGS[5].regs/Q<0> ;
wire \GEN_REGS[6].regs/Q<15> ;
wire \GEN_REGS[6].regs/Q<14> ;
wire \GEN_REGS[6].regs/Q<13> ;
wire \GEN_REGS[6].regs/Q<12> ;
wire \GEN_REGS[6].regs/Q<11> ;
wire \GEN_REGS[6].regs/Q<10> ;
wire \GEN_REGS[6].regs/Q<9> ;
wire \GEN_REGS[6].regs/Q<8> ;
wire \GEN_REGS[6].regs/Q<7> ;
wire \GEN_REGS[6].regs/Q<6> ;
wire \GEN_REGS[6].regs/Q<5> ;
wire \GEN_REGS[6].regs/Q<4> ;
wire \GEN_REGS[6].regs/Q<3> ;
wire \GEN_REGS[6].regs/Q<2> ;
wire \GEN_REGS[6].regs/Q<1> ;
wire \GEN_REGS[6].regs/Q<0> ;
wire \GEN_REGS[7].regs/Q<15> ;
wire \GEN_REGS[7].regs/Q<14> ;
wire \GEN_REGS[7].regs/Q<13> ;
wire \GEN_REGS[7].regs/Q<12> ;
wire \GEN_REGS[7].regs/Q<11> ;
wire \GEN_REGS[7].regs/Q<10> ;
wire \GEN_REGS[7].regs/Q<9> ;
wire \GEN_REGS[7].regs/Q<8> ;
wire \GEN_REGS[7].regs/Q<7> ;
wire \GEN_REGS[7].regs/Q<6> ;
wire \GEN_REGS[7].regs/Q<5> ;
wire \GEN_REGS[7].regs/Q<4> ;
wire \GEN_REGS[7].regs/Q<3> ;
wire \GEN_REGS[7].regs/Q<2> ;
wire \GEN_REGS[7].regs/Q<1> ;
wire \GEN_REGS[7].regs/Q<0> ;
wire \GEN_REGS[8].regs/Q<15> ;
wire \GEN_REGS[8].regs/Q<14> ;
wire \GEN_REGS[8].regs/Q<13> ;
wire \GEN_REGS[8].regs/Q<12> ;
wire \GEN_REGS[8].regs/Q<11> ;
wire \GEN_REGS[8].regs/Q<10> ;
wire \GEN_REGS[8].regs/Q<9> ;
wire \GEN_REGS[8].regs/Q<8> ;
wire \GEN_REGS[8].regs/Q<7> ;
wire \GEN_REGS[8].regs/Q<6> ;
wire \GEN_REGS[8].regs/Q<5> ;
wire \GEN_REGS[8].regs/Q<4> ;
wire \GEN_REGS[8].regs/Q<3> ;
wire \GEN_REGS[8].regs/Q<2> ;
wire \GEN_REGS[8].regs/Q<1> ;
wire \GEN_REGS[8].regs/Q<0> ;
wire \GEN_REGS[9].regs/Q<15> ;
wire \GEN_REGS[9].regs/Q<14> ;
wire \GEN_REGS[9].regs/Q<13> ;
wire \GEN_REGS[9].regs/Q<12> ;
wire \GEN_REGS[9].regs/Q<11> ;
wire \GEN_REGS[9].regs/Q<10> ;
wire \GEN_REGS[9].regs/Q<9> ;
wire \GEN_REGS[9].regs/Q<8> ;
wire \GEN_REGS[9].regs/Q<7> ;
wire \GEN_REGS[9].regs/Q<6> ;
wire \GEN_REGS[9].regs/Q<5> ;
wire \GEN_REGS[9].regs/Q<4> ;
wire \GEN_REGS[9].regs/Q<3> ;
wire \GEN_REGS[9].regs/Q<2> ;
wire \GEN_REGS[9].regs/Q<1> ;
wire \GEN_REGS[9].regs/Q<0> ;
wire \GEN_REGS[10].regs/Q<15> ;
wire \GEN_REGS[10].regs/Q<14> ;
wire \GEN_REGS[10].regs/Q<13> ;
wire \GEN_REGS[10].regs/Q<12> ;
wire \GEN_REGS[10].regs/Q<11> ;
wire \GEN_REGS[10].regs/Q<10> ;
wire \GEN_REGS[10].regs/Q<9> ;
wire \GEN_REGS[10].regs/Q<8> ;
wire \GEN_REGS[10].regs/Q<7> ;
wire \GEN_REGS[10].regs/Q<6> ;
wire \GEN_REGS[10].regs/Q<5> ;
wire \GEN_REGS[10].regs/Q<4> ;
wire \GEN_REGS[10].regs/Q<3> ;
wire \GEN_REGS[10].regs/Q<2> ;
wire \GEN_REGS[10].regs/Q<1> ;
wire \GEN_REGS[10].regs/Q<0> ;
wire \GEN_REGS[11].regs/Q<15> ;
wire \GEN_REGS[11].regs/Q<14> ;
wire \GEN_REGS[11].regs/Q<13> ;
wire \GEN_REGS[11].regs/Q<12> ;
wire \GEN_REGS[11].regs/Q<11> ;
wire \GEN_REGS[11].regs/Q<10> ;
wire \GEN_REGS[11].regs/Q<9> ;
wire \GEN_REGS[11].regs/Q<8> ;
wire \GEN_REGS[11].regs/Q<7> ;
wire \GEN_REGS[11].regs/Q<6> ;
wire \GEN_REGS[11].regs/Q<5> ;
wire \GEN_REGS[11].regs/Q<4> ;
wire \GEN_REGS[11].regs/Q<3> ;
wire \GEN_REGS[11].regs/Q<2> ;
wire \GEN_REGS[11].regs/Q<1> ;
wire \GEN_REGS[11].regs/Q<0> ;
wire \GEN_REGS[12].regs/Q<15> ;
wire \GEN_REGS[12].regs/Q<14> ;
wire \GEN_REGS[12].regs/Q<13> ;
wire \GEN_REGS[12].regs/Q<12> ;
wire \GEN_REGS[12].regs/Q<11> ;
wire \GEN_REGS[12].regs/Q<10> ;
wire \GEN_REGS[12].regs/Q<9> ;
wire \GEN_REGS[12].regs/Q<8> ;
wire \GEN_REGS[12].regs/Q<7> ;
wire \GEN_REGS[12].regs/Q<6> ;
wire \GEN_REGS[12].regs/Q<5> ;
wire \GEN_REGS[12].regs/Q<4> ;
wire \GEN_REGS[12].regs/Q<3> ;
wire \GEN_REGS[12].regs/Q<2> ;
wire \GEN_REGS[12].regs/Q<1> ;
wire \GEN_REGS[12].regs/Q<0> ;
wire \GEN_REGS[13].regs/Q<15> ;
wire \GEN_REGS[13].regs/Q<14> ;
wire \GEN_REGS[13].regs/Q<13> ;
wire \GEN_REGS[13].regs/Q<12> ;
wire \GEN_REGS[13].regs/Q<11> ;
wire \GEN_REGS[13].regs/Q<10> ;
wire \GEN_REGS[13].regs/Q<9> ;
wire \GEN_REGS[13].regs/Q<8> ;
wire \GEN_REGS[13].regs/Q<7> ;
wire \GEN_REGS[13].regs/Q<6> ;
wire \GEN_REGS[13].regs/Q<5> ;
wire \GEN_REGS[13].regs/Q<4> ;
wire \GEN_REGS[13].regs/Q<3> ;
wire \GEN_REGS[13].regs/Q<2> ;
wire \GEN_REGS[13].regs/Q<1> ;
wire \GEN_REGS[13].regs/Q<0> ;
wire \GEN_REGS[14].regs/Q<15> ;
wire \GEN_REGS[14].regs/Q<14> ;
wire \GEN_REGS[14].regs/Q<13> ;
wire \GEN_REGS[14].regs/Q<12> ;
wire \GEN_REGS[14].regs/Q<11> ;
wire \GEN_REGS[14].regs/Q<10> ;
wire \GEN_REGS[14].regs/Q<9> ;
wire \GEN_REGS[14].regs/Q<8> ;
wire \GEN_REGS[14].regs/Q<7> ;
wire \GEN_REGS[14].regs/Q<6> ;
wire \GEN_REGS[14].regs/Q<5> ;
wire \GEN_REGS[14].regs/Q<4> ;
wire \GEN_REGS[14].regs/Q<3> ;
wire \GEN_REGS[14].regs/Q<2> ;
wire \GEN_REGS[14].regs/Q<1> ;
wire \GEN_REGS[14].regs/Q<0> ;
wire \GEN_REGS[15].regs/Q<15> ;
wire \GEN_REGS[15].regs/Q<14> ;
wire \GEN_REGS[15].regs/Q<13> ;
wire \GEN_REGS[15].regs/Q<12> ;
wire \GEN_REGS[15].regs/Q<11> ;
wire \GEN_REGS[15].regs/Q<10> ;
wire \GEN_REGS[15].regs/Q<9> ;
wire \GEN_REGS[15].regs/Q<8> ;
wire \GEN_REGS[15].regs/Q<7> ;
wire \GEN_REGS[15].regs/Q<6> ;
wire \GEN_REGS[15].regs/Q<5> ;
wire \GEN_REGS[15].regs/Q<4> ;
wire \GEN_REGS[15].regs/Q<3> ;
wire \GEN_REGS[15].regs/Q<2> ;
wire \GEN_REGS[15].regs/Q<1> ;
wire \GEN_REGS[15].regs/Q<0> ;
wire \read2/GND_4_o_GND_4_o_equal_31_o ;
wire \read2/GND_4_o_GND_4_o_equal_30_o ;
wire \read1/GND_4_o_GND_4_o_equal_31_o ;
wire \read1/GND_4_o_GND_4_o_equal_30_o ;
wire \GEN_REGS[0].regs/rst_inv ;
wire \read2/Mmux_y_4_f715 ;
wire \read2/Mmux_y_615_341 ;
wire \read2/Mmux_y_531_342 ;
wire \read2/Mmux_y_3_f715 ;
wire \read2/Mmux_y_530_344 ;
wire \read2/Mmux_y_415_345 ;
wire \read2/Mmux_y_4_f714 ;
wire \read2/Mmux_y_614_347 ;
wire \read2/Mmux_y_529_348 ;
wire \read2/Mmux_y_3_f714 ;
wire \read2/Mmux_y_528_350 ;
wire \read2/Mmux_y_414_351 ;
wire \read2/Mmux_y_4_f713 ;
wire \read2/Mmux_y_613_353 ;
wire \read2/Mmux_y_527_354 ;
wire \read2/Mmux_y_3_f713 ;
wire \read2/Mmux_y_526_356 ;
wire \read2/Mmux_y_413_357 ;
wire \read2/Mmux_y_4_f712 ;
wire \read2/Mmux_y_612_359 ;
wire \read2/Mmux_y_525_360 ;
wire \read2/Mmux_y_3_f712 ;
wire \read2/Mmux_y_524_362 ;
wire \read2/Mmux_y_412_363 ;
wire \read2/Mmux_y_4_f711 ;
wire \read2/Mmux_y_611_365 ;
wire \read2/Mmux_y_523_366 ;
wire \read2/Mmux_y_3_f711 ;
wire \read2/Mmux_y_522_368 ;
wire \read2/Mmux_y_411_369 ;
wire \read2/Mmux_y_4_f710 ;
wire \read2/Mmux_y_610_371 ;
wire \read2/Mmux_y_521_372 ;
wire \read2/Mmux_y_3_f710 ;
wire \read2/Mmux_y_520_374 ;
wire \read2/Mmux_y_410_375 ;
wire \read2/Mmux_y_4_f79 ;
wire \read2/Mmux_y_69_377 ;
wire \read2/Mmux_y_519_378 ;
wire \read2/Mmux_y_3_f79 ;
wire \read2/Mmux_y_518_380 ;
wire \read2/Mmux_y_49_381 ;
wire \read2/Mmux_y_4_f78 ;
wire \read2/Mmux_y_68_383 ;
wire \read2/Mmux_y_517_384 ;
wire \read2/Mmux_y_3_f78 ;
wire \read2/Mmux_y_516_386 ;
wire \read2/Mmux_y_48_387 ;
wire \read2/Mmux_y_4_f77 ;
wire \read2/Mmux_y_67_389 ;
wire \read2/Mmux_y_515_390 ;
wire \read2/Mmux_y_3_f77 ;
wire \read2/Mmux_y_514_392 ;
wire \read2/Mmux_y_47_393 ;
wire \read2/Mmux_y_4_f76 ;
wire \read2/Mmux_y_66_395 ;
wire \read2/Mmux_y_513_396 ;
wire \read2/Mmux_y_3_f76 ;
wire \read2/Mmux_y_512_398 ;
wire \read2/Mmux_y_46_399 ;
wire \read2/Mmux_y_4_f75 ;
wire \read2/Mmux_y_65_401 ;
wire \read2/Mmux_y_511_402 ;
wire \read2/Mmux_y_3_f75 ;
wire \read2/Mmux_y_510_404 ;
wire \read2/Mmux_y_45_405 ;
wire \read2/Mmux_y_4_f74 ;
wire \read2/Mmux_y_64_407 ;
wire \read2/Mmux_y_59_408 ;
wire \read2/Mmux_y_3_f74 ;
wire \read2/Mmux_y_58_410 ;
wire \read2/Mmux_y_44_411 ;
wire \read2/Mmux_y_4_f73 ;
wire \read2/Mmux_y_63_413 ;
wire \read2/Mmux_y_57_414 ;
wire \read2/Mmux_y_3_f73 ;
wire \read2/Mmux_y_56_416 ;
wire \read2/Mmux_y_43_417 ;
wire \read2/Mmux_y_4_f72 ;
wire \read2/Mmux_y_62_419 ;
wire \read2/Mmux_y_55_420 ;
wire \read2/Mmux_y_3_f72 ;
wire \read2/Mmux_y_54_422 ;
wire \read2/Mmux_y_42_423 ;
wire \read2/Mmux_y_4_f71 ;
wire \read2/Mmux_y_61_425 ;
wire \read2/Mmux_y_53_426 ;
wire \read2/Mmux_y_3_f71 ;
wire \read2/Mmux_y_52_428 ;
wire \read2/Mmux_y_41_429 ;
wire \read2/Mmux_y_4_f7_430 ;
wire \read2/Mmux_y_6_431 ;
wire \read2/Mmux_y_51_432 ;
wire \read2/Mmux_y_3_f7_433 ;
wire \read2/Mmux_y_5_434 ;
wire \read2/Mmux_y_4_435 ;
wire \read1/Mmux_y_4_f715 ;
wire \read1/Mmux_y_615_437 ;
wire \read1/Mmux_y_531_438 ;
wire \read1/Mmux_y_3_f715 ;
wire \read1/Mmux_y_530_440 ;
wire \read1/Mmux_y_415_441 ;
wire \read1/Mmux_y_4_f714 ;
wire \read1/Mmux_y_614_443 ;
wire \read1/Mmux_y_529_444 ;
wire \read1/Mmux_y_3_f714 ;
wire \read1/Mmux_y_528_446 ;
wire \read1/Mmux_y_414_447 ;
wire \read1/Mmux_y_4_f713 ;
wire \read1/Mmux_y_613_449 ;
wire \read1/Mmux_y_527_450 ;
wire \read1/Mmux_y_3_f713 ;
wire \read1/Mmux_y_526_452 ;
wire \read1/Mmux_y_413_453 ;
wire \read1/Mmux_y_4_f712 ;
wire \read1/Mmux_y_612_455 ;
wire \read1/Mmux_y_525_456 ;
wire \read1/Mmux_y_3_f712 ;
wire \read1/Mmux_y_524_458 ;
wire \read1/Mmux_y_412_459 ;
wire \read1/Mmux_y_4_f711 ;
wire \read1/Mmux_y_611_461 ;
wire \read1/Mmux_y_523_462 ;
wire \read1/Mmux_y_3_f711 ;
wire \read1/Mmux_y_522_464 ;
wire \read1/Mmux_y_411_465 ;
wire \read1/Mmux_y_4_f710 ;
wire \read1/Mmux_y_610_467 ;
wire \read1/Mmux_y_521_468 ;
wire \read1/Mmux_y_3_f710 ;
wire \read1/Mmux_y_520_470 ;
wire \read1/Mmux_y_410_471 ;
wire \read1/Mmux_y_4_f79 ;
wire \read1/Mmux_y_69_473 ;
wire \read1/Mmux_y_519_474 ;
wire \read1/Mmux_y_3_f79 ;
wire \read1/Mmux_y_518_476 ;
wire \read1/Mmux_y_49_477 ;
wire \read1/Mmux_y_4_f78 ;
wire \read1/Mmux_y_68_479 ;
wire \read1/Mmux_y_517_480 ;
wire \read1/Mmux_y_3_f78 ;
wire \read1/Mmux_y_516_482 ;
wire \read1/Mmux_y_48_483 ;
wire \read1/Mmux_y_4_f77 ;
wire \read1/Mmux_y_67_485 ;
wire \read1/Mmux_y_515_486 ;
wire \read1/Mmux_y_3_f77 ;
wire \read1/Mmux_y_514_488 ;
wire \read1/Mmux_y_47_489 ;
wire \read1/Mmux_y_4_f76 ;
wire \read1/Mmux_y_66_491 ;
wire \read1/Mmux_y_513_492 ;
wire \read1/Mmux_y_3_f76 ;
wire \read1/Mmux_y_512_494 ;
wire \read1/Mmux_y_46_495 ;
wire \read1/Mmux_y_4_f75 ;
wire \read1/Mmux_y_65_497 ;
wire \read1/Mmux_y_511_498 ;
wire \read1/Mmux_y_3_f75 ;
wire \read1/Mmux_y_510_500 ;
wire \read1/Mmux_y_45_501 ;
wire \read1/Mmux_y_4_f74 ;
wire \read1/Mmux_y_64_503 ;
wire \read1/Mmux_y_59_504 ;
wire \read1/Mmux_y_3_f74 ;
wire \read1/Mmux_y_58_506 ;
wire \read1/Mmux_y_44_507 ;
wire \read1/Mmux_y_4_f73 ;
wire \read1/Mmux_y_63_509 ;
wire \read1/Mmux_y_57_510 ;
wire \read1/Mmux_y_3_f73 ;
wire \read1/Mmux_y_56_512 ;
wire \read1/Mmux_y_43_513 ;
wire \read1/Mmux_y_4_f72 ;
wire \read1/Mmux_y_62_515 ;
wire \read1/Mmux_y_55_516 ;
wire \read1/Mmux_y_3_f72 ;
wire \read1/Mmux_y_54_518 ;
wire \read1/Mmux_y_42_519 ;
wire \read1/Mmux_y_4_f71 ;
wire \read1/Mmux_y_61_521 ;
wire \read1/Mmux_y_53_522 ;
wire \read1/Mmux_y_3_f71 ;
wire \read1/Mmux_y_52_524 ;
wire \read1/Mmux_y_41_525 ;
wire \read1/Mmux_y_4_f7_526 ;
wire \read1/Mmux_y_6_527 ;
wire \read1/Mmux_y_51_528 ;
wire \read1/Mmux_y_3_f7_529 ;
wire \read1/Mmux_y_5_530 ;
wire \read1/Mmux_y_4_531 ;
wire [15 : 0] decodout;
FDCE \GEN_REGS[15].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[15].regs/Q<15> )
);
FDCE \GEN_REGS[15].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[15].regs/Q<14> )
);
FDCE \GEN_REGS[15].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[15].regs/Q<13> )
);
FDCE \GEN_REGS[15].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[15].regs/Q<12> )
);
FDCE \GEN_REGS[15].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[15].regs/Q<11> )
);
FDCE \GEN_REGS[15].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[15].regs/Q<10> )
);
FDCE \GEN_REGS[15].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[15].regs/Q<9> )
);
FDCE \GEN_REGS[15].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[15].regs/Q<8> )
);
FDCE \GEN_REGS[15].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[15].regs/Q<7> )
);
FDCE \GEN_REGS[15].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[15].regs/Q<6> )
);
FDCE \GEN_REGS[15].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[15].regs/Q<5> )
);
FDCE \GEN_REGS[15].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[15].regs/Q<4> )
);
FDCE \GEN_REGS[15].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[15].regs/Q<3> )
);
FDCE \GEN_REGS[15].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[15].regs/Q<2> )
);
FDCE \GEN_REGS[15].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[15].regs/Q<1> )
);
FDCE \GEN_REGS[15].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[15]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[15].regs/Q<0> )
);
FDCE \GEN_REGS[14].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[14].regs/Q<15> )
);
FDCE \GEN_REGS[14].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[14].regs/Q<14> )
);
FDCE \GEN_REGS[14].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[14].regs/Q<13> )
);
FDCE \GEN_REGS[14].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[14].regs/Q<12> )
);
FDCE \GEN_REGS[14].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[14].regs/Q<11> )
);
FDCE \GEN_REGS[14].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[14].regs/Q<10> )
);
FDCE \GEN_REGS[14].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[14].regs/Q<9> )
);
FDCE \GEN_REGS[14].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[14].regs/Q<8> )
);
FDCE \GEN_REGS[14].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[14].regs/Q<7> )
);
FDCE \GEN_REGS[14].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[14].regs/Q<6> )
);
FDCE \GEN_REGS[14].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[14].regs/Q<5> )
);
FDCE \GEN_REGS[14].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[14].regs/Q<4> )
);
FDCE \GEN_REGS[14].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[14].regs/Q<3> )
);
FDCE \GEN_REGS[14].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[14].regs/Q<2> )
);
FDCE \GEN_REGS[14].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[14].regs/Q<1> )
);
FDCE \GEN_REGS[14].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[14]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[14].regs/Q<0> )
);
FDCE \GEN_REGS[13].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[13].regs/Q<15> )
);
FDCE \GEN_REGS[13].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[13].regs/Q<14> )
);
FDCE \GEN_REGS[13].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[13].regs/Q<13> )
);
FDCE \GEN_REGS[13].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[13].regs/Q<12> )
);
FDCE \GEN_REGS[13].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[13].regs/Q<11> )
);
FDCE \GEN_REGS[13].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[13].regs/Q<10> )
);
FDCE \GEN_REGS[13].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[13].regs/Q<9> )
);
FDCE \GEN_REGS[13].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[13].regs/Q<8> )
);
FDCE \GEN_REGS[13].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[13].regs/Q<7> )
);
FDCE \GEN_REGS[13].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[13].regs/Q<6> )
);
FDCE \GEN_REGS[13].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[13].regs/Q<5> )
);
FDCE \GEN_REGS[13].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[13].regs/Q<4> )
);
FDCE \GEN_REGS[13].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[13].regs/Q<3> )
);
FDCE \GEN_REGS[13].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[13].regs/Q<2> )
);
FDCE \GEN_REGS[13].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[13].regs/Q<1> )
);
FDCE \GEN_REGS[13].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[13]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[13].regs/Q<0> )
);
FDCE \GEN_REGS[12].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[12].regs/Q<15> )
);
FDCE \GEN_REGS[12].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[12].regs/Q<14> )
);
FDCE \GEN_REGS[12].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[12].regs/Q<13> )
);
FDCE \GEN_REGS[12].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[12].regs/Q<12> )
);
FDCE \GEN_REGS[12].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[12].regs/Q<11> )
);
FDCE \GEN_REGS[12].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[12].regs/Q<10> )
);
FDCE \GEN_REGS[12].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[12].regs/Q<9> )
);
FDCE \GEN_REGS[12].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[12].regs/Q<8> )
);
FDCE \GEN_REGS[12].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[12].regs/Q<7> )
);
FDCE \GEN_REGS[12].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[12].regs/Q<6> )
);
FDCE \GEN_REGS[12].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[12].regs/Q<5> )
);
FDCE \GEN_REGS[12].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[12].regs/Q<4> )
);
FDCE \GEN_REGS[12].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[12].regs/Q<3> )
);
FDCE \GEN_REGS[12].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[12].regs/Q<2> )
);
FDCE \GEN_REGS[12].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[12].regs/Q<1> )
);
FDCE \GEN_REGS[12].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[12]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[12].regs/Q<0> )
);
FDCE \GEN_REGS[11].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[11].regs/Q<15> )
);
FDCE \GEN_REGS[11].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[11].regs/Q<14> )
);
FDCE \GEN_REGS[11].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[11].regs/Q<13> )
);
FDCE \GEN_REGS[11].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[11].regs/Q<12> )
);
FDCE \GEN_REGS[11].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[11].regs/Q<11> )
);
FDCE \GEN_REGS[11].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[11].regs/Q<10> )
);
FDCE \GEN_REGS[11].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[11].regs/Q<9> )
);
FDCE \GEN_REGS[11].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[11].regs/Q<8> )
);
FDCE \GEN_REGS[11].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[11].regs/Q<7> )
);
FDCE \GEN_REGS[11].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[11].regs/Q<6> )
);
FDCE \GEN_REGS[11].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[11].regs/Q<5> )
);
FDCE \GEN_REGS[11].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[11].regs/Q<4> )
);
FDCE \GEN_REGS[11].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[11].regs/Q<3> )
);
FDCE \GEN_REGS[11].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[11].regs/Q<2> )
);
FDCE \GEN_REGS[11].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[11].regs/Q<1> )
);
FDCE \GEN_REGS[11].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[11]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[11].regs/Q<0> )
);
FDCE \GEN_REGS[10].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[10].regs/Q<15> )
);
FDCE \GEN_REGS[10].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[10].regs/Q<14> )
);
FDCE \GEN_REGS[10].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[10].regs/Q<13> )
);
FDCE \GEN_REGS[10].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[10].regs/Q<12> )
);
FDCE \GEN_REGS[10].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[10].regs/Q<11> )
);
FDCE \GEN_REGS[10].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[10].regs/Q<10> )
);
FDCE \GEN_REGS[10].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[10].regs/Q<9> )
);
FDCE \GEN_REGS[10].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[10].regs/Q<8> )
);
FDCE \GEN_REGS[10].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[10].regs/Q<7> )
);
FDCE \GEN_REGS[10].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[10].regs/Q<6> )
);
FDCE \GEN_REGS[10].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[10].regs/Q<5> )
);
FDCE \GEN_REGS[10].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[10].regs/Q<4> )
);
FDCE \GEN_REGS[10].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[10].regs/Q<3> )
);
FDCE \GEN_REGS[10].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[10].regs/Q<2> )
);
FDCE \GEN_REGS[10].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[10].regs/Q<1> )
);
FDCE \GEN_REGS[10].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[10]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[10].regs/Q<0> )
);
FDCE \GEN_REGS[9].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[9].regs/Q<15> )
);
FDCE \GEN_REGS[9].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[9].regs/Q<14> )
);
FDCE \GEN_REGS[9].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[9].regs/Q<13> )
);
FDCE \GEN_REGS[9].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[9].regs/Q<12> )
);
FDCE \GEN_REGS[9].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[9].regs/Q<11> )
);
FDCE \GEN_REGS[9].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[9].regs/Q<10> )
);
FDCE \GEN_REGS[9].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[9].regs/Q<9> )
);
FDCE \GEN_REGS[9].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[9].regs/Q<8> )
);
FDCE \GEN_REGS[9].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[9].regs/Q<7> )
);
FDCE \GEN_REGS[9].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[9].regs/Q<6> )
);
FDCE \GEN_REGS[9].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[9].regs/Q<5> )
);
FDCE \GEN_REGS[9].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[9].regs/Q<4> )
);
FDCE \GEN_REGS[9].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[9].regs/Q<3> )
);
FDCE \GEN_REGS[9].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[9].regs/Q<2> )
);
FDCE \GEN_REGS[9].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[9].regs/Q<1> )
);
FDCE \GEN_REGS[9].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[9]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[9].regs/Q<0> )
);
FDCE \GEN_REGS[8].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[8].regs/Q<15> )
);
FDCE \GEN_REGS[8].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[8].regs/Q<14> )
);
FDCE \GEN_REGS[8].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[8].regs/Q<13> )
);
FDCE \GEN_REGS[8].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[8].regs/Q<12> )
);
FDCE \GEN_REGS[8].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[8].regs/Q<11> )
);
FDCE \GEN_REGS[8].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[8].regs/Q<10> )
);
FDCE \GEN_REGS[8].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[8].regs/Q<9> )
);
FDCE \GEN_REGS[8].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[8].regs/Q<8> )
);
FDCE \GEN_REGS[8].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[8].regs/Q<7> )
);
FDCE \GEN_REGS[8].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[8].regs/Q<6> )
);
FDCE \GEN_REGS[8].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[8].regs/Q<5> )
);
FDCE \GEN_REGS[8].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[8].regs/Q<4> )
);
FDCE \GEN_REGS[8].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[8].regs/Q<3> )
);
FDCE \GEN_REGS[8].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[8].regs/Q<2> )
);
FDCE \GEN_REGS[8].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[8].regs/Q<1> )
);
FDCE \GEN_REGS[8].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[8]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[8].regs/Q<0> )
);
FDCE \GEN_REGS[7].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[7].regs/Q<15> )
);
FDCE \GEN_REGS[7].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[7].regs/Q<14> )
);
FDCE \GEN_REGS[7].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[7].regs/Q<13> )
);
FDCE \GEN_REGS[7].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[7].regs/Q<12> )
);
FDCE \GEN_REGS[7].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[7].regs/Q<11> )
);
FDCE \GEN_REGS[7].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[7].regs/Q<10> )
);
FDCE \GEN_REGS[7].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[7].regs/Q<9> )
);
FDCE \GEN_REGS[7].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[7].regs/Q<8> )
);
FDCE \GEN_REGS[7].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[7].regs/Q<7> )
);
FDCE \GEN_REGS[7].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[7].regs/Q<6> )
);
FDCE \GEN_REGS[7].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[7].regs/Q<5> )
);
FDCE \GEN_REGS[7].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[7].regs/Q<4> )
);
FDCE \GEN_REGS[7].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[7].regs/Q<3> )
);
FDCE \GEN_REGS[7].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[7].regs/Q<2> )
);
FDCE \GEN_REGS[7].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[7].regs/Q<1> )
);
FDCE \GEN_REGS[7].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[7]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[7].regs/Q<0> )
);
FDCE \GEN_REGS[6].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[6].regs/Q<15> )
);
FDCE \GEN_REGS[6].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[6].regs/Q<14> )
);
FDCE \GEN_REGS[6].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[6].regs/Q<13> )
);
FDCE \GEN_REGS[6].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[6].regs/Q<12> )
);
FDCE \GEN_REGS[6].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[6].regs/Q<11> )
);
FDCE \GEN_REGS[6].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[6].regs/Q<10> )
);
FDCE \GEN_REGS[6].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[6].regs/Q<9> )
);
FDCE \GEN_REGS[6].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[6].regs/Q<8> )
);
FDCE \GEN_REGS[6].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[6].regs/Q<7> )
);
FDCE \GEN_REGS[6].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[6].regs/Q<6> )
);
FDCE \GEN_REGS[6].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[6].regs/Q<5> )
);
FDCE \GEN_REGS[6].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[6].regs/Q<4> )
);
FDCE \GEN_REGS[6].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[6].regs/Q<3> )
);
FDCE \GEN_REGS[6].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[6].regs/Q<2> )
);
FDCE \GEN_REGS[6].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[6].regs/Q<1> )
);
FDCE \GEN_REGS[6].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[6]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[6].regs/Q<0> )
);
FDCE \GEN_REGS[5].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[5].regs/Q<15> )
);
FDCE \GEN_REGS[5].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[5].regs/Q<14> )
);
FDCE \GEN_REGS[5].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[5].regs/Q<13> )
);
FDCE \GEN_REGS[5].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[5].regs/Q<12> )
);
FDCE \GEN_REGS[5].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[5].regs/Q<11> )
);
FDCE \GEN_REGS[5].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[5].regs/Q<10> )
);
FDCE \GEN_REGS[5].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[5].regs/Q<9> )
);
FDCE \GEN_REGS[5].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[5].regs/Q<8> )
);
FDCE \GEN_REGS[5].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[5].regs/Q<7> )
);
FDCE \GEN_REGS[5].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[5].regs/Q<6> )
);
FDCE \GEN_REGS[5].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[5].regs/Q<5> )
);
FDCE \GEN_REGS[5].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[5].regs/Q<4> )
);
FDCE \GEN_REGS[5].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[5].regs/Q<3> )
);
FDCE \GEN_REGS[5].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[5].regs/Q<2> )
);
FDCE \GEN_REGS[5].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[5].regs/Q<1> )
);
FDCE \GEN_REGS[5].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[5]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[5].regs/Q<0> )
);
FDCE \GEN_REGS[4].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[4].regs/Q<15> )
);
FDCE \GEN_REGS[4].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[4].regs/Q<14> )
);
FDCE \GEN_REGS[4].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[4].regs/Q<13> )
);
FDCE \GEN_REGS[4].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[4].regs/Q<12> )
);
FDCE \GEN_REGS[4].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[4].regs/Q<11> )
);
FDCE \GEN_REGS[4].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[4].regs/Q<10> )
);
FDCE \GEN_REGS[4].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[4].regs/Q<9> )
);
FDCE \GEN_REGS[4].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[4].regs/Q<8> )
);
FDCE \GEN_REGS[4].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[4].regs/Q<7> )
);
FDCE \GEN_REGS[4].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[4].regs/Q<6> )
);
FDCE \GEN_REGS[4].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[4].regs/Q<5> )
);
FDCE \GEN_REGS[4].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[4].regs/Q<4> )
);
FDCE \GEN_REGS[4].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[4].regs/Q<3> )
);
FDCE \GEN_REGS[4].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[4].regs/Q<2> )
);
FDCE \GEN_REGS[4].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[4].regs/Q<1> )
);
FDCE \GEN_REGS[4].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[4]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[4].regs/Q<0> )
);
FDCE \GEN_REGS[3].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[3].regs/Q<15> )
);
FDCE \GEN_REGS[3].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[3].regs/Q<14> )
);
FDCE \GEN_REGS[3].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[3].regs/Q<13> )
);
FDCE \GEN_REGS[3].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[3].regs/Q<12> )
);
FDCE \GEN_REGS[3].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[3].regs/Q<11> )
);
FDCE \GEN_REGS[3].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[3].regs/Q<10> )
);
FDCE \GEN_REGS[3].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[3].regs/Q<9> )
);
FDCE \GEN_REGS[3].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[3].regs/Q<8> )
);
FDCE \GEN_REGS[3].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[3].regs/Q<7> )
);
FDCE \GEN_REGS[3].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[3].regs/Q<6> )
);
FDCE \GEN_REGS[3].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[3].regs/Q<5> )
);
FDCE \GEN_REGS[3].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[3].regs/Q<4> )
);
FDCE \GEN_REGS[3].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[3].regs/Q<3> )
);
FDCE \GEN_REGS[3].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[3].regs/Q<2> )
);
FDCE \GEN_REGS[3].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[3].regs/Q<1> )
);
FDCE \GEN_REGS[3].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[3]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[3].regs/Q<0> )
);
FDCE \GEN_REGS[2].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[2].regs/Q<15> )
);
FDCE \GEN_REGS[2].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[2].regs/Q<14> )
);
FDCE \GEN_REGS[2].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[2].regs/Q<13> )
);
FDCE \GEN_REGS[2].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[2].regs/Q<12> )
);
FDCE \GEN_REGS[2].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[2].regs/Q<11> )
);
FDCE \GEN_REGS[2].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[2].regs/Q<10> )
);
FDCE \GEN_REGS[2].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[2].regs/Q<9> )
);
FDCE \GEN_REGS[2].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[2].regs/Q<8> )
);
FDCE \GEN_REGS[2].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[2].regs/Q<7> )
);
FDCE \GEN_REGS[2].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[2].regs/Q<6> )
);
FDCE \GEN_REGS[2].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[2].regs/Q<5> )
);
FDCE \GEN_REGS[2].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[2].regs/Q<4> )
);
FDCE \GEN_REGS[2].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[2].regs/Q<3> )
);
FDCE \GEN_REGS[2].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[2].regs/Q<2> )
);
FDCE \GEN_REGS[2].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[2].regs/Q<1> )
);
FDCE \GEN_REGS[2].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[2]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[2].regs/Q<0> )
);
FDCE \GEN_REGS[1].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[1].regs/Q<15> )
);
FDCE \GEN_REGS[1].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[1].regs/Q<14> )
);
FDCE \GEN_REGS[1].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[1].regs/Q<13> )
);
FDCE \GEN_REGS[1].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[1].regs/Q<12> )
);
FDCE \GEN_REGS[1].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[1].regs/Q<11> )
);
FDCE \GEN_REGS[1].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[1].regs/Q<10> )
);
FDCE \GEN_REGS[1].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[1].regs/Q<9> )
);
FDCE \GEN_REGS[1].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[1].regs/Q<8> )
);
FDCE \GEN_REGS[1].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[1].regs/Q<7> )
);
FDCE \GEN_REGS[1].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[1].regs/Q<6> )
);
FDCE \GEN_REGS[1].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[1].regs/Q<5> )
);
FDCE \GEN_REGS[1].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[1].regs/Q<4> )
);
FDCE \GEN_REGS[1].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[1].regs/Q<3> )
);
FDCE \GEN_REGS[1].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[1].regs/Q<2> )
);
FDCE \GEN_REGS[1].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[1].regs/Q<1> )
);
FDCE \GEN_REGS[1].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[1]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[1].regs/Q<0> )
);
FDCE \GEN_REGS[0].regs/Q_15 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_15_IBUF_12),
.Q(\GEN_REGS[0].regs/Q<15> )
);
FDCE \GEN_REGS[0].regs/Q_14 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_14_IBUF_13),
.Q(\GEN_REGS[0].regs/Q<14> )
);
FDCE \GEN_REGS[0].regs/Q_13 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_13_IBUF_14),
.Q(\GEN_REGS[0].regs/Q<13> )
);
FDCE \GEN_REGS[0].regs/Q_12 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_12_IBUF_15),
.Q(\GEN_REGS[0].regs/Q<12> )
);
FDCE \GEN_REGS[0].regs/Q_11 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_11_IBUF_16),
.Q(\GEN_REGS[0].regs/Q<11> )
);
FDCE \GEN_REGS[0].regs/Q_10 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_10_IBUF_17),
.Q(\GEN_REGS[0].regs/Q<10> )
);
FDCE \GEN_REGS[0].regs/Q_9 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_9_IBUF_18),
.Q(\GEN_REGS[0].regs/Q<9> )
);
FDCE \GEN_REGS[0].regs/Q_8 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_8_IBUF_19),
.Q(\GEN_REGS[0].regs/Q<8> )
);
FDCE \GEN_REGS[0].regs/Q_7 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_7_IBUF_20),
.Q(\GEN_REGS[0].regs/Q<7> )
);
FDCE \GEN_REGS[0].regs/Q_6 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_6_IBUF_21),
.Q(\GEN_REGS[0].regs/Q<6> )
);
FDCE \GEN_REGS[0].regs/Q_5 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_5_IBUF_22),
.Q(\GEN_REGS[0].regs/Q<5> )
);
FDCE \GEN_REGS[0].regs/Q_4 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_4_IBUF_23),
.Q(\GEN_REGS[0].regs/Q<4> )
);
FDCE \GEN_REGS[0].regs/Q_3 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_3_IBUF_24),
.Q(\GEN_REGS[0].regs/Q<3> )
);
FDCE \GEN_REGS[0].regs/Q_2 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_2_IBUF_25),
.Q(\GEN_REGS[0].regs/Q<2> )
);
FDCE \GEN_REGS[0].regs/Q_1 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_1_IBUF_26),
.Q(\GEN_REGS[0].regs/Q<1> )
);
FDCE \GEN_REGS[0].regs/Q_0 (
.C(clk_BUFGP_29),
.CE(decodout[0]),
.CLR(\GEN_REGS[0].regs/rst_inv ),
.D(wdat_0_IBUF_27),
.Q(\GEN_REGS[0].regs/Q<0> )
);
MUXF8 \read2/Mmux_y_2_f8_14 (
.I0(\read2/Mmux_y_4_f715 ),
.I1(\read2/Mmux_y_3_f715 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_9_OBUF_53)
);
MUXF7 \read2/Mmux_y_4_f7_14 (
.I0(\read2/Mmux_y_615_341 ),
.I1(\read2/Mmux_y_531_342 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f715 )
);
MUXF7 \read2/Mmux_y_3_f7_14 (
.I0(\read2/Mmux_y_530_344 ),
.I1(\read2/Mmux_y_415_345 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f715 )
);
MUXF8 \read2/Mmux_y_2_f8_13 (
.I0(\read2/Mmux_y_4_f714 ),
.I1(\read2/Mmux_y_3_f714 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_8_OBUF_54)
);
MUXF7 \read2/Mmux_y_4_f7_13 (
.I0(\read2/Mmux_y_614_347 ),
.I1(\read2/Mmux_y_529_348 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f714 )
);
MUXF7 \read2/Mmux_y_3_f7_13 (
.I0(\read2/Mmux_y_528_350 ),
.I1(\read2/Mmux_y_414_351 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f714 )
);
MUXF8 \read2/Mmux_y_2_f8_12 (
.I0(\read2/Mmux_y_4_f713 ),
.I1(\read2/Mmux_y_3_f713 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_7_OBUF_55)
);
MUXF7 \read2/Mmux_y_4_f7_12 (
.I0(\read2/Mmux_y_613_353 ),
.I1(\read2/Mmux_y_527_354 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f713 )
);
MUXF7 \read2/Mmux_y_3_f7_12 (
.I0(\read2/Mmux_y_526_356 ),
.I1(\read2/Mmux_y_413_357 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f713 )
);
MUXF8 \read2/Mmux_y_2_f8_11 (
.I0(\read2/Mmux_y_4_f712 ),
.I1(\read2/Mmux_y_3_f712 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_6_OBUF_56)
);
MUXF7 \read2/Mmux_y_4_f7_11 (
.I0(\read2/Mmux_y_612_359 ),
.I1(\read2/Mmux_y_525_360 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f712 )
);
MUXF7 \read2/Mmux_y_3_f7_11 (
.I0(\read2/Mmux_y_524_362 ),
.I1(\read2/Mmux_y_412_363 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f712 )
);
MUXF8 \read2/Mmux_y_2_f8_10 (
.I0(\read2/Mmux_y_4_f711 ),
.I1(\read2/Mmux_y_3_f711 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_5_OBUF_57)
);
MUXF7 \read2/Mmux_y_4_f7_10 (
.I0(\read2/Mmux_y_611_365 ),
.I1(\read2/Mmux_y_523_366 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f711 )
);
MUXF7 \read2/Mmux_y_3_f7_10 (
.I0(\read2/Mmux_y_522_368 ),
.I1(\read2/Mmux_y_411_369 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f711 )
);
MUXF8 \read2/Mmux_y_2_f8_9 (
.I0(\read2/Mmux_y_4_f710 ),
.I1(\read2/Mmux_y_3_f710 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_4_OBUF_58)
);
MUXF7 \read2/Mmux_y_4_f7_9 (
.I0(\read2/Mmux_y_610_371 ),
.I1(\read2/Mmux_y_521_372 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f710 )
);
MUXF7 \read2/Mmux_y_3_f7_9 (
.I0(\read2/Mmux_y_520_374 ),
.I1(\read2/Mmux_y_410_375 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f710 )
);
MUXF8 \read2/Mmux_y_2_f8_8 (
.I0(\read2/Mmux_y_4_f79 ),
.I1(\read2/Mmux_y_3_f79 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_3_OBUF_59)
);
MUXF7 \read2/Mmux_y_4_f7_8 (
.I0(\read2/Mmux_y_69_377 ),
.I1(\read2/Mmux_y_519_378 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f79 )
);
MUXF7 \read2/Mmux_y_3_f7_8 (
.I0(\read2/Mmux_y_518_380 ),
.I1(\read2/Mmux_y_49_381 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f79 )
);
MUXF8 \read2/Mmux_y_2_f8_7 (
.I0(\read2/Mmux_y_4_f78 ),
.I1(\read2/Mmux_y_3_f78 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_2_OBUF_60)
);
MUXF7 \read2/Mmux_y_4_f7_7 (
.I0(\read2/Mmux_y_68_383 ),
.I1(\read2/Mmux_y_517_384 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f78 )
);
MUXF7 \read2/Mmux_y_3_f7_7 (
.I0(\read2/Mmux_y_516_386 ),
.I1(\read2/Mmux_y_48_387 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f78 )
);
MUXF8 \read2/Mmux_y_2_f8_6 (
.I0(\read2/Mmux_y_4_f77 ),
.I1(\read2/Mmux_y_3_f77 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_1_OBUF_61)
);
MUXF7 \read2/Mmux_y_4_f7_6 (
.I0(\read2/Mmux_y_67_389 ),
.I1(\read2/Mmux_y_515_390 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f77 )
);
MUXF7 \read2/Mmux_y_3_f7_6 (
.I0(\read2/Mmux_y_514_392 ),
.I1(\read2/Mmux_y_47_393 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f77 )
);
MUXF8 \read2/Mmux_y_2_f8_5 (
.I0(\read2/Mmux_y_4_f76 ),
.I1(\read2/Mmux_y_3_f76 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_15_OBUF_47)
);
MUXF7 \read2/Mmux_y_4_f7_5 (
.I0(\read2/Mmux_y_66_395 ),
.I1(\read2/Mmux_y_513_396 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f76 )
);
MUXF7 \read2/Mmux_y_3_f7_5 (
.I0(\read2/Mmux_y_512_398 ),
.I1(\read2/Mmux_y_46_399 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f76 )
);
MUXF8 \read2/Mmux_y_2_f8_4 (
.I0(\read2/Mmux_y_4_f75 ),
.I1(\read2/Mmux_y_3_f75 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_14_OBUF_48)
);
MUXF7 \read2/Mmux_y_4_f7_4 (
.I0(\read2/Mmux_y_65_401 ),
.I1(\read2/Mmux_y_511_402 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f75 )
);
MUXF7 \read2/Mmux_y_3_f7_4 (
.I0(\read2/Mmux_y_510_404 ),
.I1(\read2/Mmux_y_45_405 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f75 )
);
MUXF8 \read2/Mmux_y_2_f8_3 (
.I0(\read2/Mmux_y_4_f74 ),
.I1(\read2/Mmux_y_3_f74 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_13_OBUF_49)
);
MUXF7 \read2/Mmux_y_4_f7_3 (
.I0(\read2/Mmux_y_64_407 ),
.I1(\read2/Mmux_y_59_408 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f74 )
);
MUXF7 \read2/Mmux_y_3_f7_3 (
.I0(\read2/Mmux_y_58_410 ),
.I1(\read2/Mmux_y_44_411 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f74 )
);
MUXF8 \read2/Mmux_y_2_f8_2 (
.I0(\read2/Mmux_y_4_f73 ),
.I1(\read2/Mmux_y_3_f73 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_12_OBUF_50)
);
MUXF7 \read2/Mmux_y_4_f7_2 (
.I0(\read2/Mmux_y_63_413 ),
.I1(\read2/Mmux_y_57_414 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f73 )
);
MUXF7 \read2/Mmux_y_3_f7_2 (
.I0(\read2/Mmux_y_56_416 ),
.I1(\read2/Mmux_y_43_417 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f73 )
);
MUXF8 \read2/Mmux_y_2_f8_1 (
.I0(\read2/Mmux_y_4_f72 ),
.I1(\read2/Mmux_y_3_f72 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_11_OBUF_51)
);
MUXF7 \read2/Mmux_y_4_f7_1 (
.I0(\read2/Mmux_y_62_419 ),
.I1(\read2/Mmux_y_55_420 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f72 )
);
MUXF7 \read2/Mmux_y_3_f7_1 (
.I0(\read2/Mmux_y_54_422 ),
.I1(\read2/Mmux_y_42_423 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f72 )
);
MUXF8 \read2/Mmux_y_2_f8_0 (
.I0(\read2/Mmux_y_4_f71 ),
.I1(\read2/Mmux_y_3_f71 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_10_OBUF_52)
);
MUXF7 \read2/Mmux_y_4_f7_0 (
.I0(\read2/Mmux_y_61_425 ),
.I1(\read2/Mmux_y_53_426 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f71 )
);
MUXF7 \read2/Mmux_y_3_f7_0 (
.I0(\read2/Mmux_y_52_428 ),
.I1(\read2/Mmux_y_41_429 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f71 )
);
MUXF8 \read2/Mmux_y_2_f8 (
.I0(\read2/Mmux_y_4_f7_430 ),
.I1(\read2/Mmux_y_3_f7_433 ),
.S(\read2/GND_4_o_GND_4_o_equal_31_o ),
.O(bdat_0_OBUF_62)
);
MUXF7 \read2/Mmux_y_4_f7 (
.I0(\read2/Mmux_y_6_431 ),
.I1(\read2/Mmux_y_51_432 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_4_f7_430 )
);
MUXF7 \read2/Mmux_y_3_f7 (
.I0(\read2/Mmux_y_5_434 ),
.I1(\read2/Mmux_y_4_435 ),
.S(\read2/GND_4_o_GND_4_o_equal_30_o ),
.O(\read2/Mmux_y_3_f7_433 )
);
MUXF8 \read1/Mmux_y_2_f8_14 (
.I0(\read1/Mmux_y_4_f715 ),
.I1(\read1/Mmux_y_3_f715 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_9_OBUF_37)
);
MUXF7 \read1/Mmux_y_4_f7_14 (
.I0(\read1/Mmux_y_615_437 ),
.I1(\read1/Mmux_y_531_438 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f715 )
);
MUXF7 \read1/Mmux_y_3_f7_14 (
.I0(\read1/Mmux_y_530_440 ),
.I1(\read1/Mmux_y_415_441 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f715 )
);
MUXF8 \read1/Mmux_y_2_f8_13 (
.I0(\read1/Mmux_y_4_f714 ),
.I1(\read1/Mmux_y_3_f714 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_8_OBUF_38)
);
MUXF7 \read1/Mmux_y_4_f7_13 (
.I0(\read1/Mmux_y_614_443 ),
.I1(\read1/Mmux_y_529_444 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f714 )
);
MUXF7 \read1/Mmux_y_3_f7_13 (
.I0(\read1/Mmux_y_528_446 ),
.I1(\read1/Mmux_y_414_447 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f714 )
);
MUXF8 \read1/Mmux_y_2_f8_12 (
.I0(\read1/Mmux_y_4_f713 ),
.I1(\read1/Mmux_y_3_f713 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_7_OBUF_39)
);
MUXF7 \read1/Mmux_y_4_f7_12 (
.I0(\read1/Mmux_y_613_449 ),
.I1(\read1/Mmux_y_527_450 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f713 )
);
MUXF7 \read1/Mmux_y_3_f7_12 (
.I0(\read1/Mmux_y_526_452 ),
.I1(\read1/Mmux_y_413_453 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f713 )
);
MUXF8 \read1/Mmux_y_2_f8_11 (
.I0(\read1/Mmux_y_4_f712 ),
.I1(\read1/Mmux_y_3_f712 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_6_OBUF_40)
);
MUXF7 \read1/Mmux_y_4_f7_11 (
.I0(\read1/Mmux_y_612_455 ),
.I1(\read1/Mmux_y_525_456 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f712 )
);
MUXF7 \read1/Mmux_y_3_f7_11 (
.I0(\read1/Mmux_y_524_458 ),
.I1(\read1/Mmux_y_412_459 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f712 )
);
MUXF8 \read1/Mmux_y_2_f8_10 (
.I0(\read1/Mmux_y_4_f711 ),
.I1(\read1/Mmux_y_3_f711 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_5_OBUF_41)
);
MUXF7 \read1/Mmux_y_4_f7_10 (
.I0(\read1/Mmux_y_611_461 ),
.I1(\read1/Mmux_y_523_462 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f711 )
);
MUXF7 \read1/Mmux_y_3_f7_10 (
.I0(\read1/Mmux_y_522_464 ),
.I1(\read1/Mmux_y_411_465 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f711 )
);
MUXF8 \read1/Mmux_y_2_f8_9 (
.I0(\read1/Mmux_y_4_f710 ),
.I1(\read1/Mmux_y_3_f710 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_4_OBUF_42)
);
MUXF7 \read1/Mmux_y_4_f7_9 (
.I0(\read1/Mmux_y_610_467 ),
.I1(\read1/Mmux_y_521_468 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f710 )
);
MUXF7 \read1/Mmux_y_3_f7_9 (
.I0(\read1/Mmux_y_520_470 ),
.I1(\read1/Mmux_y_410_471 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f710 )
);
MUXF8 \read1/Mmux_y_2_f8_8 (
.I0(\read1/Mmux_y_4_f79 ),
.I1(\read1/Mmux_y_3_f79 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_3_OBUF_43)
);
MUXF7 \read1/Mmux_y_4_f7_8 (
.I0(\read1/Mmux_y_69_473 ),
.I1(\read1/Mmux_y_519_474 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f79 )
);
MUXF7 \read1/Mmux_y_3_f7_8 (
.I0(\read1/Mmux_y_518_476 ),
.I1(\read1/Mmux_y_49_477 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f79 )
);
MUXF8 \read1/Mmux_y_2_f8_7 (
.I0(\read1/Mmux_y_4_f78 ),
.I1(\read1/Mmux_y_3_f78 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_2_OBUF_44)
);
MUXF7 \read1/Mmux_y_4_f7_7 (
.I0(\read1/Mmux_y_68_479 ),
.I1(\read1/Mmux_y_517_480 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f78 )
);
MUXF7 \read1/Mmux_y_3_f7_7 (
.I0(\read1/Mmux_y_516_482 ),
.I1(\read1/Mmux_y_48_483 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f78 )
);
MUXF8 \read1/Mmux_y_2_f8_6 (
.I0(\read1/Mmux_y_4_f77 ),
.I1(\read1/Mmux_y_3_f77 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_1_OBUF_45)
);
MUXF7 \read1/Mmux_y_4_f7_6 (
.I0(\read1/Mmux_y_67_485 ),
.I1(\read1/Mmux_y_515_486 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f77 )
);
MUXF7 \read1/Mmux_y_3_f7_6 (
.I0(\read1/Mmux_y_514_488 ),
.I1(\read1/Mmux_y_47_489 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f77 )
);
MUXF8 \read1/Mmux_y_2_f8_5 (
.I0(\read1/Mmux_y_4_f76 ),
.I1(\read1/Mmux_y_3_f76 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_15_OBUF_31)
);
MUXF7 \read1/Mmux_y_4_f7_5 (
.I0(\read1/Mmux_y_66_491 ),
.I1(\read1/Mmux_y_513_492 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f76 )
);
MUXF7 \read1/Mmux_y_3_f7_5 (
.I0(\read1/Mmux_y_512_494 ),
.I1(\read1/Mmux_y_46_495 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f76 )
);
MUXF8 \read1/Mmux_y_2_f8_4 (
.I0(\read1/Mmux_y_4_f75 ),
.I1(\read1/Mmux_y_3_f75 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_14_OBUF_32)
);
MUXF7 \read1/Mmux_y_4_f7_4 (
.I0(\read1/Mmux_y_65_497 ),
.I1(\read1/Mmux_y_511_498 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f75 )
);
MUXF7 \read1/Mmux_y_3_f7_4 (
.I0(\read1/Mmux_y_510_500 ),
.I1(\read1/Mmux_y_45_501 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f75 )
);
MUXF8 \read1/Mmux_y_2_f8_3 (
.I0(\read1/Mmux_y_4_f74 ),
.I1(\read1/Mmux_y_3_f74 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_13_OBUF_33)
);
MUXF7 \read1/Mmux_y_4_f7_3 (
.I0(\read1/Mmux_y_64_503 ),
.I1(\read1/Mmux_y_59_504 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f74 )
);
MUXF7 \read1/Mmux_y_3_f7_3 (
.I0(\read1/Mmux_y_58_506 ),
.I1(\read1/Mmux_y_44_507 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f74 )
);
MUXF8 \read1/Mmux_y_2_f8_2 (
.I0(\read1/Mmux_y_4_f73 ),
.I1(\read1/Mmux_y_3_f73 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_12_OBUF_34)
);
MUXF7 \read1/Mmux_y_4_f7_2 (
.I0(\read1/Mmux_y_63_509 ),
.I1(\read1/Mmux_y_57_510 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f73 )
);
MUXF7 \read1/Mmux_y_3_f7_2 (
.I0(\read1/Mmux_y_56_512 ),
.I1(\read1/Mmux_y_43_513 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f73 )
);
MUXF8 \read1/Mmux_y_2_f8_1 (
.I0(\read1/Mmux_y_4_f72 ),
.I1(\read1/Mmux_y_3_f72 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_11_OBUF_35)
);
MUXF7 \read1/Mmux_y_4_f7_1 (
.I0(\read1/Mmux_y_62_515 ),
.I1(\read1/Mmux_y_55_516 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f72 )
);
MUXF7 \read1/Mmux_y_3_f7_1 (
.I0(\read1/Mmux_y_54_518 ),
.I1(\read1/Mmux_y_42_519 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f72 )
);
MUXF8 \read1/Mmux_y_2_f8_0 (
.I0(\read1/Mmux_y_4_f71 ),
.I1(\read1/Mmux_y_3_f71 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_10_OBUF_36)
);
MUXF7 \read1/Mmux_y_4_f7_0 (
.I0(\read1/Mmux_y_61_521 ),
.I1(\read1/Mmux_y_53_522 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f71 )
);
MUXF7 \read1/Mmux_y_3_f7_0 (
.I0(\read1/Mmux_y_52_524 ),
.I1(\read1/Mmux_y_41_525 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f71 )
);
MUXF8 \read1/Mmux_y_2_f8 (
.I0(\read1/Mmux_y_4_f7_526 ),
.I1(\read1/Mmux_y_3_f7_529 ),
.S(\read1/GND_4_o_GND_4_o_equal_31_o ),
.O(adat_0_OBUF_46)
);
MUXF7 \read1/Mmux_y_4_f7 (
.I0(\read1/Mmux_y_6_527 ),
.I1(\read1/Mmux_y_51_528 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_4_f7_526 )
);
MUXF7 \read1/Mmux_y_3_f7 (
.I0(\read1/Mmux_y_5_530 ),
.I1(\read1/Mmux_y_4_531 ),
.S(\read1/GND_4_o_GND_4_o_equal_30_o ),
.O(\read1/Mmux_y_3_f7_529 )
);
LUT5 #(
.INIT ( 32'h00010000 ))
\inputdecoder/p<0>1 (
.I0(rw_0_IBUF_11),
.I1(rw_1_IBUF_10),
.I2(rw_2_IBUF_9),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[0])
);
LUT5 #(
.INIT ( 32'h00040000 ))
\inputdecoder/p<2>1 (
.I0(rw_0_IBUF_11),
.I1(rw_1_IBUF_10),
.I2(rw_2_IBUF_9),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[2])
);
LUT5 #(
.INIT ( 32'h00080000 ))
\inputdecoder/p<3>1 (
.I0(rw_0_IBUF_11),
.I1(rw_1_IBUF_10),
.I2(rw_2_IBUF_9),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[3])
);
LUT5 #(
.INIT ( 32'h00040000 ))
\inputdecoder/p<1>1 (
.I0(rw_1_IBUF_10),
.I1(rw_0_IBUF_11),
.I2(rw_2_IBUF_9),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[1])
);
LUT5 #(
.INIT ( 32'h00040000 ))
\inputdecoder/p<4>1 (
.I0(rw_0_IBUF_11),
.I1(rw_2_IBUF_9),
.I2(rw_1_IBUF_10),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[4])
);
LUT5 #(
.INIT ( 32'h00080000 ))
\inputdecoder/p<6>1 (
.I0(rw_2_IBUF_9),
.I1(rw_1_IBUF_10),
.I2(rw_0_IBUF_11),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[6])
);
LUT5 #(
.INIT ( 32'h00800000 ))
\inputdecoder/p<7>1 (
.I0(rw_0_IBUF_11),
.I1(rw_1_IBUF_10),
.I2(rw_2_IBUF_9),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[7])
);
LUT5 #(
.INIT ( 32'h00080000 ))
\inputdecoder/p<5>1 (
.I0(rw_2_IBUF_9),
.I1(rw_0_IBUF_11),
.I2(rw_1_IBUF_10),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[5])
);
LUT5 #(
.INIT ( 32'h00040000 ))
\inputdecoder/p<8>1 (
.I0(rw_0_IBUF_11),
.I1(rw_3_IBUF_8),
.I2(rw_1_IBUF_10),
.I3(rw_2_IBUF_9),
.I4(wren_IBUF_28),
.O(decodout[8])
);
LUT5 #(
.INIT ( 32'h00080000 ))
\inputdecoder/p<10>1 (
.I0(rw_1_IBUF_10),
.I1(rw_3_IBUF_8),
.I2(rw_0_IBUF_11),
.I3(rw_2_IBUF_9),
.I4(wren_IBUF_28),
.O(decodout[10])
);
LUT5 #(
.INIT ( 32'h00800000 ))
\inputdecoder/p<11>1 (
.I0(rw_3_IBUF_8),
.I1(rw_1_IBUF_10),
.I2(rw_0_IBUF_11),
.I3(rw_2_IBUF_9),
.I4(wren_IBUF_28),
.O(decodout[11])
);
LUT5 #(
.INIT ( 32'h00080000 ))
\inputdecoder/p<9>1 (
.I0(rw_0_IBUF_11),
.I1(rw_3_IBUF_8),
.I2(rw_1_IBUF_10),
.I3(rw_2_IBUF_9),
.I4(wren_IBUF_28),
.O(decodout[9])
);
LUT5 #(
.INIT ( 32'h00080000 ))
\inputdecoder/p<12>1 (
.I0(rw_2_IBUF_9),
.I1(rw_3_IBUF_8),
.I2(rw_0_IBUF_11),
.I3(rw_1_IBUF_10),
.I4(wren_IBUF_28),
.O(decodout[12])
);
LUT5 #(
.INIT ( 32'h00800000 ))
\inputdecoder/p<14>1 (
.I0(rw_3_IBUF_8),
.I1(rw_1_IBUF_10),
.I2(rw_2_IBUF_9),
.I3(rw_0_IBUF_11),
.I4(wren_IBUF_28),
.O(decodout[14])
);
LUT5 #(
.INIT ( 32'h80000000 ))
\inputdecoder/p<15>1 (
.I0(rw_0_IBUF_11),
.I1(rw_1_IBUF_10),
.I2(rw_2_IBUF_9),
.I3(rw_3_IBUF_8),
.I4(wren_IBUF_28),
.O(decodout[15])
);
LUT5 #(
.INIT ( 32'h00800000 ))
\inputdecoder/p<13>1 (
.I0(rw_3_IBUF_8),
.I1(rw_0_IBUF_11),
.I2(rw_2_IBUF_9),
.I3(rw_1_IBUF_10),
.I4(wren_IBUF_28),
.O(decodout[13])
);
IBUF ra_3_IBUF (
.I(ra[3]),
.O(ra_3_IBUF_0)
);
IBUF ra_2_IBUF (
.I(ra[2]),
.O(ra_2_IBUF_1)
);
IBUF ra_1_IBUF (
.I(ra[1]),
.O(ra_1_IBUF_2)
);
IBUF ra_0_IBUF (
.I(ra[0]),
.O(ra_0_IBUF_3)
);
IBUF rb_3_IBUF (
.I(rb[3]),
.O(rb_3_IBUF_4)
);
IBUF rb_2_IBUF (
.I(rb[2]),
.O(rb_2_IBUF_5)
);
IBUF rb_1_IBUF (
.I(rb[1]),
.O(rb_1_IBUF_6)
);
IBUF rb_0_IBUF (
.I(rb[0]),
.O(rb_0_IBUF_7)
);
IBUF rw_3_IBUF (
.I(rw[3]),
.O(rw_3_IBUF_8)
);
IBUF rw_2_IBUF (
.I(rw[2]),
.O(rw_2_IBUF_9)
);
IBUF rw_1_IBUF (
.I(rw[1]),
.O(rw_1_IBUF_10)
);
IBUF rw_0_IBUF (
.I(rw[0]),
.O(rw_0_IBUF_11)
);
IBUF wdat_15_IBUF (
.I(wdat[15]),
.O(wdat_15_IBUF_12)
);
IBUF wdat_14_IBUF (
.I(wdat[14]),
.O(wdat_14_IBUF_13)
);
IBUF wdat_13_IBUF (
.I(wdat[13]),
.O(wdat_13_IBUF_14)
);
IBUF wdat_12_IBUF (
.I(wdat[12]),
.O(wdat_12_IBUF_15)
);
IBUF wdat_11_IBUF (
.I(wdat[11]),
.O(wdat_11_IBUF_16)
);
IBUF wdat_10_IBUF (
.I(wdat[10]),
.O(wdat_10_IBUF_17)
);
IBUF wdat_9_IBUF (
.I(wdat[9]),
.O(wdat_9_IBUF_18)
);
IBUF wdat_8_IBUF (
.I(wdat[8]),
.O(wdat_8_IBUF_19)
);
IBUF wdat_7_IBUF (
.I(wdat[7]),
.O(wdat_7_IBUF_20)
);
IBUF wdat_6_IBUF (
.I(wdat[6]),
.O(wdat_6_IBUF_21)
);
IBUF wdat_5_IBUF (
.I(wdat[5]),
.O(wdat_5_IBUF_22)
);
IBUF wdat_4_IBUF (
.I(wdat[4]),
.O(wdat_4_IBUF_23)
);
IBUF wdat_3_IBUF (
.I(wdat[3]),
.O(wdat_3_IBUF_24)
);
IBUF wdat_2_IBUF (
.I(wdat[2]),
.O(wdat_2_IBUF_25)
);
IBUF wdat_1_IBUF (
.I(wdat[1]),
.O(wdat_1_IBUF_26)
);
IBUF wdat_0_IBUF (
.I(wdat[0]),
.O(wdat_0_IBUF_27)
);
IBUF wren_IBUF (
.I(wren),
.O(wren_IBUF_28)
);
IBUF rst_IBUF (
.I(rst),
.O(rst_IBUF_30)
);
OBUF adat_15_OBUF (
.I(adat_15_OBUF_31),
.O(adat[15])
);
OBUF adat_14_OBUF (
.I(adat_14_OBUF_32),
.O(adat[14])
);
OBUF adat_13_OBUF (
.I(adat_13_OBUF_33),
.O(adat[13])
);
OBUF adat_12_OBUF (
.I(adat_12_OBUF_34),
.O(adat[12])
);
OBUF adat_11_OBUF (
.I(adat_11_OBUF_35),
.O(adat[11])
);
OBUF adat_10_OBUF (
.I(adat_10_OBUF_36),
.O(adat[10])
);
OBUF adat_9_OBUF (
.I(adat_9_OBUF_37),
.O(adat[9])
);
OBUF adat_8_OBUF (
.I(adat_8_OBUF_38),
.O(adat[8])
);
OBUF adat_7_OBUF (
.I(adat_7_OBUF_39),
.O(adat[7])
);
OBUF adat_6_OBUF (
.I(adat_6_OBUF_40),
.O(adat[6])
);
OBUF adat_5_OBUF (
.I(adat_5_OBUF_41),
.O(adat[5])
);
OBUF adat_4_OBUF (
.I(adat_4_OBUF_42),
.O(adat[4])
);
OBUF adat_3_OBUF (
.I(adat_3_OBUF_43),
.O(adat[3])
);
OBUF adat_2_OBUF (
.I(adat_2_OBUF_44),
.O(adat[2])
);
OBUF adat_1_OBUF (
.I(adat_1_OBUF_45),
.O(adat[1])
);
OBUF adat_0_OBUF (
.I(adat_0_OBUF_46),
.O(adat[0])
);
OBUF bdat_15_OBUF (
.I(bdat_15_OBUF_47),
.O(bdat[15])
);
OBUF bdat_14_OBUF (
.I(bdat_14_OBUF_48),
.O(bdat[14])
);
OBUF bdat_13_OBUF (
.I(bdat_13_OBUF_49),
.O(bdat[13])
);
OBUF bdat_12_OBUF (
.I(bdat_12_OBUF_50),
.O(bdat[12])
);
OBUF bdat_11_OBUF (
.I(bdat_11_OBUF_51),
.O(bdat[11])
);
OBUF bdat_10_OBUF (
.I(bdat_10_OBUF_52),
.O(bdat[10])
);
OBUF bdat_9_OBUF (
.I(bdat_9_OBUF_53),
.O(bdat[9])
);
OBUF bdat_8_OBUF (
.I(bdat_8_OBUF_54),
.O(bdat[8])
);
OBUF bdat_7_OBUF (
.I(bdat_7_OBUF_55),
.O(bdat[7])
);
OBUF bdat_6_OBUF (
.I(bdat_6_OBUF_56),
.O(bdat[6])
);
OBUF bdat_5_OBUF (
.I(bdat_5_OBUF_57),
.O(bdat[5])
);
OBUF bdat_4_OBUF (
.I(bdat_4_OBUF_58),
.O(bdat[4])
);
OBUF bdat_3_OBUF (
.I(bdat_3_OBUF_59),
.O(bdat[3])
);
OBUF bdat_2_OBUF (
.I(bdat_2_OBUF_60),
.O(bdat[2])
);
OBUF bdat_1_OBUF (
.I(bdat_1_OBUF_61),
.O(bdat[1])
);
OBUF bdat_0_OBUF (
.I(bdat_0_OBUF_62),
.O(bdat[0])
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_615 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<9> ),
.I3(\GEN_REGS[15].regs/Q<9> ),
.I4(\GEN_REGS[13].regs/Q<9> ),
.I5(\GEN_REGS[12].regs/Q<9> ),
.O(\read2/Mmux_y_615_341 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_531 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<9> ),
.I3(\GEN_REGS[11].regs/Q<9> ),
.I4(\GEN_REGS[9].regs/Q<9> ),
.I5(\GEN_REGS[8].regs/Q<9> ),
.O(\read2/Mmux_y_531_342 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_530 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<9> ),
.I3(\GEN_REGS[7].regs/Q<9> ),
.I4(\GEN_REGS[5].regs/Q<9> ),
.I5(\GEN_REGS[4].regs/Q<9> ),
.O(\read2/Mmux_y_530_344 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_415 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<9> ),
.I3(\GEN_REGS[3].regs/Q<9> ),
.I4(\GEN_REGS[1].regs/Q<9> ),
.I5(\GEN_REGS[0].regs/Q<9> ),
.O(\read2/Mmux_y_415_345 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_614 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<8> ),
.I3(\GEN_REGS[15].regs/Q<8> ),
.I4(\GEN_REGS[13].regs/Q<8> ),
.I5(\GEN_REGS[12].regs/Q<8> ),
.O(\read2/Mmux_y_614_347 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_529 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<8> ),
.I3(\GEN_REGS[11].regs/Q<8> ),
.I4(\GEN_REGS[9].regs/Q<8> ),
.I5(\GEN_REGS[8].regs/Q<8> ),
.O(\read2/Mmux_y_529_348 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_528 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<8> ),
.I3(\GEN_REGS[7].regs/Q<8> ),
.I4(\GEN_REGS[5].regs/Q<8> ),
.I5(\GEN_REGS[4].regs/Q<8> ),
.O(\read2/Mmux_y_528_350 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_414 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<8> ),
.I3(\GEN_REGS[3].regs/Q<8> ),
.I4(\GEN_REGS[1].regs/Q<8> ),
.I5(\GEN_REGS[0].regs/Q<8> ),
.O(\read2/Mmux_y_414_351 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_613 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<7> ),
.I3(\GEN_REGS[15].regs/Q<7> ),
.I4(\GEN_REGS[13].regs/Q<7> ),
.I5(\GEN_REGS[12].regs/Q<7> ),
.O(\read2/Mmux_y_613_353 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_527 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<7> ),
.I3(\GEN_REGS[11].regs/Q<7> ),
.I4(\GEN_REGS[9].regs/Q<7> ),
.I5(\GEN_REGS[8].regs/Q<7> ),
.O(\read2/Mmux_y_527_354 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_526 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<7> ),
.I3(\GEN_REGS[7].regs/Q<7> ),
.I4(\GEN_REGS[5].regs/Q<7> ),
.I5(\GEN_REGS[4].regs/Q<7> ),
.O(\read2/Mmux_y_526_356 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_413 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<7> ),
.I3(\GEN_REGS[3].regs/Q<7> ),
.I4(\GEN_REGS[1].regs/Q<7> ),
.I5(\GEN_REGS[0].regs/Q<7> ),
.O(\read2/Mmux_y_413_357 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_612 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<6> ),
.I3(\GEN_REGS[15].regs/Q<6> ),
.I4(\GEN_REGS[13].regs/Q<6> ),
.I5(\GEN_REGS[12].regs/Q<6> ),
.O(\read2/Mmux_y_612_359 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_525 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<6> ),
.I3(\GEN_REGS[11].regs/Q<6> ),
.I4(\GEN_REGS[9].regs/Q<6> ),
.I5(\GEN_REGS[8].regs/Q<6> ),
.O(\read2/Mmux_y_525_360 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_524 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<6> ),
.I3(\GEN_REGS[7].regs/Q<6> ),
.I4(\GEN_REGS[5].regs/Q<6> ),
.I5(\GEN_REGS[4].regs/Q<6> ),
.O(\read2/Mmux_y_524_362 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_412 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<6> ),
.I3(\GEN_REGS[3].regs/Q<6> ),
.I4(\GEN_REGS[1].regs/Q<6> ),
.I5(\GEN_REGS[0].regs/Q<6> ),
.O(\read2/Mmux_y_412_363 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_611 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<5> ),
.I3(\GEN_REGS[15].regs/Q<5> ),
.I4(\GEN_REGS[13].regs/Q<5> ),
.I5(\GEN_REGS[12].regs/Q<5> ),
.O(\read2/Mmux_y_611_365 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_523 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<5> ),
.I3(\GEN_REGS[11].regs/Q<5> ),
.I4(\GEN_REGS[9].regs/Q<5> ),
.I5(\GEN_REGS[8].regs/Q<5> ),
.O(\read2/Mmux_y_523_366 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_522 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<5> ),
.I3(\GEN_REGS[7].regs/Q<5> ),
.I4(\GEN_REGS[5].regs/Q<5> ),
.I5(\GEN_REGS[4].regs/Q<5> ),
.O(\read2/Mmux_y_522_368 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_411 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<5> ),
.I3(\GEN_REGS[3].regs/Q<5> ),
.I4(\GEN_REGS[1].regs/Q<5> ),
.I5(\GEN_REGS[0].regs/Q<5> ),
.O(\read2/Mmux_y_411_369 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_610 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<4> ),
.I3(\GEN_REGS[15].regs/Q<4> ),
.I4(\GEN_REGS[13].regs/Q<4> ),
.I5(\GEN_REGS[12].regs/Q<4> ),
.O(\read2/Mmux_y_610_371 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_521 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<4> ),
.I3(\GEN_REGS[11].regs/Q<4> ),
.I4(\GEN_REGS[9].regs/Q<4> ),
.I5(\GEN_REGS[8].regs/Q<4> ),
.O(\read2/Mmux_y_521_372 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_520 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<4> ),
.I3(\GEN_REGS[7].regs/Q<4> ),
.I4(\GEN_REGS[5].regs/Q<4> ),
.I5(\GEN_REGS[4].regs/Q<4> ),
.O(\read2/Mmux_y_520_374 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_410 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<4> ),
.I3(\GEN_REGS[3].regs/Q<4> ),
.I4(\GEN_REGS[1].regs/Q<4> ),
.I5(\GEN_REGS[0].regs/Q<4> ),
.O(\read2/Mmux_y_410_375 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_69 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<3> ),
.I3(\GEN_REGS[15].regs/Q<3> ),
.I4(\GEN_REGS[13].regs/Q<3> ),
.I5(\GEN_REGS[12].regs/Q<3> ),
.O(\read2/Mmux_y_69_377 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_519 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<3> ),
.I3(\GEN_REGS[11].regs/Q<3> ),
.I4(\GEN_REGS[9].regs/Q<3> ),
.I5(\GEN_REGS[8].regs/Q<3> ),
.O(\read2/Mmux_y_519_378 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_518 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<3> ),
.I3(\GEN_REGS[7].regs/Q<3> ),
.I4(\GEN_REGS[5].regs/Q<3> ),
.I5(\GEN_REGS[4].regs/Q<3> ),
.O(\read2/Mmux_y_518_380 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_49 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<3> ),
.I3(\GEN_REGS[3].regs/Q<3> ),
.I4(\GEN_REGS[1].regs/Q<3> ),
.I5(\GEN_REGS[0].regs/Q<3> ),
.O(\read2/Mmux_y_49_381 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_68 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<2> ),
.I3(\GEN_REGS[15].regs/Q<2> ),
.I4(\GEN_REGS[13].regs/Q<2> ),
.I5(\GEN_REGS[12].regs/Q<2> ),
.O(\read2/Mmux_y_68_383 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_517 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<2> ),
.I3(\GEN_REGS[11].regs/Q<2> ),
.I4(\GEN_REGS[9].regs/Q<2> ),
.I5(\GEN_REGS[8].regs/Q<2> ),
.O(\read2/Mmux_y_517_384 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_516 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<2> ),
.I3(\GEN_REGS[7].regs/Q<2> ),
.I4(\GEN_REGS[5].regs/Q<2> ),
.I5(\GEN_REGS[4].regs/Q<2> ),
.O(\read2/Mmux_y_516_386 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_48 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<2> ),
.I3(\GEN_REGS[3].regs/Q<2> ),
.I4(\GEN_REGS[1].regs/Q<2> ),
.I5(\GEN_REGS[0].regs/Q<2> ),
.O(\read2/Mmux_y_48_387 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_67 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<1> ),
.I3(\GEN_REGS[15].regs/Q<1> ),
.I4(\GEN_REGS[13].regs/Q<1> ),
.I5(\GEN_REGS[12].regs/Q<1> ),
.O(\read2/Mmux_y_67_389 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_515 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<1> ),
.I3(\GEN_REGS[11].regs/Q<1> ),
.I4(\GEN_REGS[9].regs/Q<1> ),
.I5(\GEN_REGS[8].regs/Q<1> ),
.O(\read2/Mmux_y_515_390 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_514 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<1> ),
.I3(\GEN_REGS[7].regs/Q<1> ),
.I4(\GEN_REGS[5].regs/Q<1> ),
.I5(\GEN_REGS[4].regs/Q<1> ),
.O(\read2/Mmux_y_514_392 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_47 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<1> ),
.I3(\GEN_REGS[3].regs/Q<1> ),
.I4(\GEN_REGS[1].regs/Q<1> ),
.I5(\GEN_REGS[0].regs/Q<1> ),
.O(\read2/Mmux_y_47_393 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_66 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<15> ),
.I3(\GEN_REGS[15].regs/Q<15> ),
.I4(\GEN_REGS[13].regs/Q<15> ),
.I5(\GEN_REGS[12].regs/Q<15> ),
.O(\read2/Mmux_y_66_395 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_513 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<15> ),
.I3(\GEN_REGS[11].regs/Q<15> ),
.I4(\GEN_REGS[9].regs/Q<15> ),
.I5(\GEN_REGS[8].regs/Q<15> ),
.O(\read2/Mmux_y_513_396 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_512 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<15> ),
.I3(\GEN_REGS[7].regs/Q<15> ),
.I4(\GEN_REGS[5].regs/Q<15> ),
.I5(\GEN_REGS[4].regs/Q<15> ),
.O(\read2/Mmux_y_512_398 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_46 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<15> ),
.I3(\GEN_REGS[3].regs/Q<15> ),
.I4(\GEN_REGS[1].regs/Q<15> ),
.I5(\GEN_REGS[0].regs/Q<15> ),
.O(\read2/Mmux_y_46_399 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_65 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<14> ),
.I3(\GEN_REGS[15].regs/Q<14> ),
.I4(\GEN_REGS[13].regs/Q<14> ),
.I5(\GEN_REGS[12].regs/Q<14> ),
.O(\read2/Mmux_y_65_401 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_511 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<14> ),
.I3(\GEN_REGS[11].regs/Q<14> ),
.I4(\GEN_REGS[9].regs/Q<14> ),
.I5(\GEN_REGS[8].regs/Q<14> ),
.O(\read2/Mmux_y_511_402 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_510 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<14> ),
.I3(\GEN_REGS[7].regs/Q<14> ),
.I4(\GEN_REGS[5].regs/Q<14> ),
.I5(\GEN_REGS[4].regs/Q<14> ),
.O(\read2/Mmux_y_510_404 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_45 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<14> ),
.I3(\GEN_REGS[3].regs/Q<14> ),
.I4(\GEN_REGS[1].regs/Q<14> ),
.I5(\GEN_REGS[0].regs/Q<14> ),
.O(\read2/Mmux_y_45_405 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_64 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<13> ),
.I3(\GEN_REGS[15].regs/Q<13> ),
.I4(\GEN_REGS[13].regs/Q<13> ),
.I5(\GEN_REGS[12].regs/Q<13> ),
.O(\read2/Mmux_y_64_407 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_59 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<13> ),
.I3(\GEN_REGS[11].regs/Q<13> ),
.I4(\GEN_REGS[9].regs/Q<13> ),
.I5(\GEN_REGS[8].regs/Q<13> ),
.O(\read2/Mmux_y_59_408 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_58 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<13> ),
.I3(\GEN_REGS[7].regs/Q<13> ),
.I4(\GEN_REGS[5].regs/Q<13> ),
.I5(\GEN_REGS[4].regs/Q<13> ),
.O(\read2/Mmux_y_58_410 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_44 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<13> ),
.I3(\GEN_REGS[3].regs/Q<13> ),
.I4(\GEN_REGS[1].regs/Q<13> ),
.I5(\GEN_REGS[0].regs/Q<13> ),
.O(\read2/Mmux_y_44_411 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_63 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<12> ),
.I3(\GEN_REGS[15].regs/Q<12> ),
.I4(\GEN_REGS[13].regs/Q<12> ),
.I5(\GEN_REGS[12].regs/Q<12> ),
.O(\read2/Mmux_y_63_413 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_57 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<12> ),
.I3(\GEN_REGS[11].regs/Q<12> ),
.I4(\GEN_REGS[9].regs/Q<12> ),
.I5(\GEN_REGS[8].regs/Q<12> ),
.O(\read2/Mmux_y_57_414 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_56 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<12> ),
.I3(\GEN_REGS[7].regs/Q<12> ),
.I4(\GEN_REGS[5].regs/Q<12> ),
.I5(\GEN_REGS[4].regs/Q<12> ),
.O(\read2/Mmux_y_56_416 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_43 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<12> ),
.I3(\GEN_REGS[3].regs/Q<12> ),
.I4(\GEN_REGS[1].regs/Q<12> ),
.I5(\GEN_REGS[0].regs/Q<12> ),
.O(\read2/Mmux_y_43_417 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_62 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<11> ),
.I3(\GEN_REGS[15].regs/Q<11> ),
.I4(\GEN_REGS[13].regs/Q<11> ),
.I5(\GEN_REGS[12].regs/Q<11> ),
.O(\read2/Mmux_y_62_419 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_55 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<11> ),
.I3(\GEN_REGS[11].regs/Q<11> ),
.I4(\GEN_REGS[9].regs/Q<11> ),
.I5(\GEN_REGS[8].regs/Q<11> ),
.O(\read2/Mmux_y_55_420 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_54 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<11> ),
.I3(\GEN_REGS[7].regs/Q<11> ),
.I4(\GEN_REGS[5].regs/Q<11> ),
.I5(\GEN_REGS[4].regs/Q<11> ),
.O(\read2/Mmux_y_54_422 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_42 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<11> ),
.I3(\GEN_REGS[3].regs/Q<11> ),
.I4(\GEN_REGS[1].regs/Q<11> ),
.I5(\GEN_REGS[0].regs/Q<11> ),
.O(\read2/Mmux_y_42_423 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_61 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<10> ),
.I3(\GEN_REGS[15].regs/Q<10> ),
.I4(\GEN_REGS[13].regs/Q<10> ),
.I5(\GEN_REGS[12].regs/Q<10> ),
.O(\read2/Mmux_y_61_425 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_53 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<10> ),
.I3(\GEN_REGS[11].regs/Q<10> ),
.I4(\GEN_REGS[9].regs/Q<10> ),
.I5(\GEN_REGS[8].regs/Q<10> ),
.O(\read2/Mmux_y_53_426 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_52 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<10> ),
.I3(\GEN_REGS[7].regs/Q<10> ),
.I4(\GEN_REGS[5].regs/Q<10> ),
.I5(\GEN_REGS[4].regs/Q<10> ),
.O(\read2/Mmux_y_52_428 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_41 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<10> ),
.I3(\GEN_REGS[3].regs/Q<10> ),
.I4(\GEN_REGS[1].regs/Q<10> ),
.I5(\GEN_REGS[0].regs/Q<10> ),
.O(\read2/Mmux_y_41_429 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_6 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[14].regs/Q<0> ),
.I3(\GEN_REGS[15].regs/Q<0> ),
.I4(\GEN_REGS[13].regs/Q<0> ),
.I5(\GEN_REGS[12].regs/Q<0> ),
.O(\read2/Mmux_y_6_431 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_51 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[10].regs/Q<0> ),
.I3(\GEN_REGS[11].regs/Q<0> ),
.I4(\GEN_REGS[9].regs/Q<0> ),
.I5(\GEN_REGS[8].regs/Q<0> ),
.O(\read2/Mmux_y_51_432 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_5 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[6].regs/Q<0> ),
.I3(\GEN_REGS[7].regs/Q<0> ),
.I4(\GEN_REGS[5].regs/Q<0> ),
.I5(\GEN_REGS[4].regs/Q<0> ),
.O(\read2/Mmux_y_5_434 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read2/Mmux_y_4 (
.I0(rb_1_IBUF_6),
.I1(rb_0_IBUF_7),
.I2(\GEN_REGS[2].regs/Q<0> ),
.I3(\GEN_REGS[3].regs/Q<0> ),
.I4(\GEN_REGS[1].regs/Q<0> ),
.I5(\GEN_REGS[0].regs/Q<0> ),
.O(\read2/Mmux_y_4_435 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_615 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<9> ),
.I3(\GEN_REGS[15].regs/Q<9> ),
.I4(\GEN_REGS[13].regs/Q<9> ),
.I5(\GEN_REGS[12].regs/Q<9> ),
.O(\read1/Mmux_y_615_437 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_531 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<9> ),
.I3(\GEN_REGS[11].regs/Q<9> ),
.I4(\GEN_REGS[9].regs/Q<9> ),
.I5(\GEN_REGS[8].regs/Q<9> ),
.O(\read1/Mmux_y_531_438 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_530 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<9> ),
.I3(\GEN_REGS[7].regs/Q<9> ),
.I4(\GEN_REGS[5].regs/Q<9> ),
.I5(\GEN_REGS[4].regs/Q<9> ),
.O(\read1/Mmux_y_530_440 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_415 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<9> ),
.I3(\GEN_REGS[3].regs/Q<9> ),
.I4(\GEN_REGS[1].regs/Q<9> ),
.I5(\GEN_REGS[0].regs/Q<9> ),
.O(\read1/Mmux_y_415_441 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_614 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<8> ),
.I3(\GEN_REGS[15].regs/Q<8> ),
.I4(\GEN_REGS[13].regs/Q<8> ),
.I5(\GEN_REGS[12].regs/Q<8> ),
.O(\read1/Mmux_y_614_443 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_529 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<8> ),
.I3(\GEN_REGS[11].regs/Q<8> ),
.I4(\GEN_REGS[9].regs/Q<8> ),
.I5(\GEN_REGS[8].regs/Q<8> ),
.O(\read1/Mmux_y_529_444 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_528 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<8> ),
.I3(\GEN_REGS[7].regs/Q<8> ),
.I4(\GEN_REGS[5].regs/Q<8> ),
.I5(\GEN_REGS[4].regs/Q<8> ),
.O(\read1/Mmux_y_528_446 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_414 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<8> ),
.I3(\GEN_REGS[3].regs/Q<8> ),
.I4(\GEN_REGS[1].regs/Q<8> ),
.I5(\GEN_REGS[0].regs/Q<8> ),
.O(\read1/Mmux_y_414_447 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_613 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<7> ),
.I3(\GEN_REGS[15].regs/Q<7> ),
.I4(\GEN_REGS[13].regs/Q<7> ),
.I5(\GEN_REGS[12].regs/Q<7> ),
.O(\read1/Mmux_y_613_449 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_527 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<7> ),
.I3(\GEN_REGS[11].regs/Q<7> ),
.I4(\GEN_REGS[9].regs/Q<7> ),
.I5(\GEN_REGS[8].regs/Q<7> ),
.O(\read1/Mmux_y_527_450 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_526 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<7> ),
.I3(\GEN_REGS[7].regs/Q<7> ),
.I4(\GEN_REGS[5].regs/Q<7> ),
.I5(\GEN_REGS[4].regs/Q<7> ),
.O(\read1/Mmux_y_526_452 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_413 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<7> ),
.I3(\GEN_REGS[3].regs/Q<7> ),
.I4(\GEN_REGS[1].regs/Q<7> ),
.I5(\GEN_REGS[0].regs/Q<7> ),
.O(\read1/Mmux_y_413_453 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_612 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<6> ),
.I3(\GEN_REGS[15].regs/Q<6> ),
.I4(\GEN_REGS[13].regs/Q<6> ),
.I5(\GEN_REGS[12].regs/Q<6> ),
.O(\read1/Mmux_y_612_455 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_525 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<6> ),
.I3(\GEN_REGS[11].regs/Q<6> ),
.I4(\GEN_REGS[9].regs/Q<6> ),
.I5(\GEN_REGS[8].regs/Q<6> ),
.O(\read1/Mmux_y_525_456 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_524 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<6> ),
.I3(\GEN_REGS[7].regs/Q<6> ),
.I4(\GEN_REGS[5].regs/Q<6> ),
.I5(\GEN_REGS[4].regs/Q<6> ),
.O(\read1/Mmux_y_524_458 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_412 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<6> ),
.I3(\GEN_REGS[3].regs/Q<6> ),
.I4(\GEN_REGS[1].regs/Q<6> ),
.I5(\GEN_REGS[0].regs/Q<6> ),
.O(\read1/Mmux_y_412_459 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_611 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<5> ),
.I3(\GEN_REGS[15].regs/Q<5> ),
.I4(\GEN_REGS[13].regs/Q<5> ),
.I5(\GEN_REGS[12].regs/Q<5> ),
.O(\read1/Mmux_y_611_461 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_523 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<5> ),
.I3(\GEN_REGS[11].regs/Q<5> ),
.I4(\GEN_REGS[9].regs/Q<5> ),
.I5(\GEN_REGS[8].regs/Q<5> ),
.O(\read1/Mmux_y_523_462 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_522 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<5> ),
.I3(\GEN_REGS[7].regs/Q<5> ),
.I4(\GEN_REGS[5].regs/Q<5> ),
.I5(\GEN_REGS[4].regs/Q<5> ),
.O(\read1/Mmux_y_522_464 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_411 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<5> ),
.I3(\GEN_REGS[3].regs/Q<5> ),
.I4(\GEN_REGS[1].regs/Q<5> ),
.I5(\GEN_REGS[0].regs/Q<5> ),
.O(\read1/Mmux_y_411_465 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_610 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<4> ),
.I3(\GEN_REGS[15].regs/Q<4> ),
.I4(\GEN_REGS[13].regs/Q<4> ),
.I5(\GEN_REGS[12].regs/Q<4> ),
.O(\read1/Mmux_y_610_467 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_521 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<4> ),
.I3(\GEN_REGS[11].regs/Q<4> ),
.I4(\GEN_REGS[9].regs/Q<4> ),
.I5(\GEN_REGS[8].regs/Q<4> ),
.O(\read1/Mmux_y_521_468 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_520 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<4> ),
.I3(\GEN_REGS[7].regs/Q<4> ),
.I4(\GEN_REGS[5].regs/Q<4> ),
.I5(\GEN_REGS[4].regs/Q<4> ),
.O(\read1/Mmux_y_520_470 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_410 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<4> ),
.I3(\GEN_REGS[3].regs/Q<4> ),
.I4(\GEN_REGS[1].regs/Q<4> ),
.I5(\GEN_REGS[0].regs/Q<4> ),
.O(\read1/Mmux_y_410_471 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_69 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<3> ),
.I3(\GEN_REGS[15].regs/Q<3> ),
.I4(\GEN_REGS[13].regs/Q<3> ),
.I5(\GEN_REGS[12].regs/Q<3> ),
.O(\read1/Mmux_y_69_473 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_519 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<3> ),
.I3(\GEN_REGS[11].regs/Q<3> ),
.I4(\GEN_REGS[9].regs/Q<3> ),
.I5(\GEN_REGS[8].regs/Q<3> ),
.O(\read1/Mmux_y_519_474 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_518 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<3> ),
.I3(\GEN_REGS[7].regs/Q<3> ),
.I4(\GEN_REGS[5].regs/Q<3> ),
.I5(\GEN_REGS[4].regs/Q<3> ),
.O(\read1/Mmux_y_518_476 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_49 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<3> ),
.I3(\GEN_REGS[3].regs/Q<3> ),
.I4(\GEN_REGS[1].regs/Q<3> ),
.I5(\GEN_REGS[0].regs/Q<3> ),
.O(\read1/Mmux_y_49_477 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_68 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<2> ),
.I3(\GEN_REGS[15].regs/Q<2> ),
.I4(\GEN_REGS[13].regs/Q<2> ),
.I5(\GEN_REGS[12].regs/Q<2> ),
.O(\read1/Mmux_y_68_479 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_517 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<2> ),
.I3(\GEN_REGS[11].regs/Q<2> ),
.I4(\GEN_REGS[9].regs/Q<2> ),
.I5(\GEN_REGS[8].regs/Q<2> ),
.O(\read1/Mmux_y_517_480 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_516 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<2> ),
.I3(\GEN_REGS[7].regs/Q<2> ),
.I4(\GEN_REGS[5].regs/Q<2> ),
.I5(\GEN_REGS[4].regs/Q<2> ),
.O(\read1/Mmux_y_516_482 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_48 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<2> ),
.I3(\GEN_REGS[3].regs/Q<2> ),
.I4(\GEN_REGS[1].regs/Q<2> ),
.I5(\GEN_REGS[0].regs/Q<2> ),
.O(\read1/Mmux_y_48_483 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_67 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<1> ),
.I3(\GEN_REGS[15].regs/Q<1> ),
.I4(\GEN_REGS[13].regs/Q<1> ),
.I5(\GEN_REGS[12].regs/Q<1> ),
.O(\read1/Mmux_y_67_485 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_515 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<1> ),
.I3(\GEN_REGS[11].regs/Q<1> ),
.I4(\GEN_REGS[9].regs/Q<1> ),
.I5(\GEN_REGS[8].regs/Q<1> ),
.O(\read1/Mmux_y_515_486 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_514 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<1> ),
.I3(\GEN_REGS[7].regs/Q<1> ),
.I4(\GEN_REGS[5].regs/Q<1> ),
.I5(\GEN_REGS[4].regs/Q<1> ),
.O(\read1/Mmux_y_514_488 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_47 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<1> ),
.I3(\GEN_REGS[3].regs/Q<1> ),
.I4(\GEN_REGS[1].regs/Q<1> ),
.I5(\GEN_REGS[0].regs/Q<1> ),
.O(\read1/Mmux_y_47_489 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_66 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<15> ),
.I3(\GEN_REGS[15].regs/Q<15> ),
.I4(\GEN_REGS[13].regs/Q<15> ),
.I5(\GEN_REGS[12].regs/Q<15> ),
.O(\read1/Mmux_y_66_491 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_513 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<15> ),
.I3(\GEN_REGS[11].regs/Q<15> ),
.I4(\GEN_REGS[9].regs/Q<15> ),
.I5(\GEN_REGS[8].regs/Q<15> ),
.O(\read1/Mmux_y_513_492 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_512 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<15> ),
.I3(\GEN_REGS[7].regs/Q<15> ),
.I4(\GEN_REGS[5].regs/Q<15> ),
.I5(\GEN_REGS[4].regs/Q<15> ),
.O(\read1/Mmux_y_512_494 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_46 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<15> ),
.I3(\GEN_REGS[3].regs/Q<15> ),
.I4(\GEN_REGS[1].regs/Q<15> ),
.I5(\GEN_REGS[0].regs/Q<15> ),
.O(\read1/Mmux_y_46_495 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_65 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<14> ),
.I3(\GEN_REGS[15].regs/Q<14> ),
.I4(\GEN_REGS[13].regs/Q<14> ),
.I5(\GEN_REGS[12].regs/Q<14> ),
.O(\read1/Mmux_y_65_497 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_511 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<14> ),
.I3(\GEN_REGS[11].regs/Q<14> ),
.I4(\GEN_REGS[9].regs/Q<14> ),
.I5(\GEN_REGS[8].regs/Q<14> ),
.O(\read1/Mmux_y_511_498 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_510 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<14> ),
.I3(\GEN_REGS[7].regs/Q<14> ),
.I4(\GEN_REGS[5].regs/Q<14> ),
.I5(\GEN_REGS[4].regs/Q<14> ),
.O(\read1/Mmux_y_510_500 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_45 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<14> ),
.I3(\GEN_REGS[3].regs/Q<14> ),
.I4(\GEN_REGS[1].regs/Q<14> ),
.I5(\GEN_REGS[0].regs/Q<14> ),
.O(\read1/Mmux_y_45_501 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_64 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<13> ),
.I3(\GEN_REGS[15].regs/Q<13> ),
.I4(\GEN_REGS[13].regs/Q<13> ),
.I5(\GEN_REGS[12].regs/Q<13> ),
.O(\read1/Mmux_y_64_503 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_59 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<13> ),
.I3(\GEN_REGS[11].regs/Q<13> ),
.I4(\GEN_REGS[9].regs/Q<13> ),
.I5(\GEN_REGS[8].regs/Q<13> ),
.O(\read1/Mmux_y_59_504 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_58 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<13> ),
.I3(\GEN_REGS[7].regs/Q<13> ),
.I4(\GEN_REGS[5].regs/Q<13> ),
.I5(\GEN_REGS[4].regs/Q<13> ),
.O(\read1/Mmux_y_58_506 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_44 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<13> ),
.I3(\GEN_REGS[3].regs/Q<13> ),
.I4(\GEN_REGS[1].regs/Q<13> ),
.I5(\GEN_REGS[0].regs/Q<13> ),
.O(\read1/Mmux_y_44_507 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_63 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<12> ),
.I3(\GEN_REGS[15].regs/Q<12> ),
.I4(\GEN_REGS[13].regs/Q<12> ),
.I5(\GEN_REGS[12].regs/Q<12> ),
.O(\read1/Mmux_y_63_509 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_57 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<12> ),
.I3(\GEN_REGS[11].regs/Q<12> ),
.I4(\GEN_REGS[9].regs/Q<12> ),
.I5(\GEN_REGS[8].regs/Q<12> ),
.O(\read1/Mmux_y_57_510 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_56 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<12> ),
.I3(\GEN_REGS[7].regs/Q<12> ),
.I4(\GEN_REGS[5].regs/Q<12> ),
.I5(\GEN_REGS[4].regs/Q<12> ),
.O(\read1/Mmux_y_56_512 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_43 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<12> ),
.I3(\GEN_REGS[3].regs/Q<12> ),
.I4(\GEN_REGS[1].regs/Q<12> ),
.I5(\GEN_REGS[0].regs/Q<12> ),
.O(\read1/Mmux_y_43_513 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_62 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<11> ),
.I3(\GEN_REGS[15].regs/Q<11> ),
.I4(\GEN_REGS[13].regs/Q<11> ),
.I5(\GEN_REGS[12].regs/Q<11> ),
.O(\read1/Mmux_y_62_515 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_55 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<11> ),
.I3(\GEN_REGS[11].regs/Q<11> ),
.I4(\GEN_REGS[9].regs/Q<11> ),
.I5(\GEN_REGS[8].regs/Q<11> ),
.O(\read1/Mmux_y_55_516 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_54 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<11> ),
.I3(\GEN_REGS[7].regs/Q<11> ),
.I4(\GEN_REGS[5].regs/Q<11> ),
.I5(\GEN_REGS[4].regs/Q<11> ),
.O(\read1/Mmux_y_54_518 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_42 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<11> ),
.I3(\GEN_REGS[3].regs/Q<11> ),
.I4(\GEN_REGS[1].regs/Q<11> ),
.I5(\GEN_REGS[0].regs/Q<11> ),
.O(\read1/Mmux_y_42_519 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_61 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<10> ),
.I3(\GEN_REGS[15].regs/Q<10> ),
.I4(\GEN_REGS[13].regs/Q<10> ),
.I5(\GEN_REGS[12].regs/Q<10> ),
.O(\read1/Mmux_y_61_521 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_53 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<10> ),
.I3(\GEN_REGS[11].regs/Q<10> ),
.I4(\GEN_REGS[9].regs/Q<10> ),
.I5(\GEN_REGS[8].regs/Q<10> ),
.O(\read1/Mmux_y_53_522 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_52 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<10> ),
.I3(\GEN_REGS[7].regs/Q<10> ),
.I4(\GEN_REGS[5].regs/Q<10> ),
.I5(\GEN_REGS[4].regs/Q<10> ),
.O(\read1/Mmux_y_52_524 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_41 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<10> ),
.I3(\GEN_REGS[3].regs/Q<10> ),
.I4(\GEN_REGS[1].regs/Q<10> ),
.I5(\GEN_REGS[0].regs/Q<10> ),
.O(\read1/Mmux_y_41_525 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_6 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[14].regs/Q<0> ),
.I3(\GEN_REGS[15].regs/Q<0> ),
.I4(\GEN_REGS[13].regs/Q<0> ),
.I5(\GEN_REGS[12].regs/Q<0> ),
.O(\read1/Mmux_y_6_527 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_51 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[10].regs/Q<0> ),
.I3(\GEN_REGS[11].regs/Q<0> ),
.I4(\GEN_REGS[9].regs/Q<0> ),
.I5(\GEN_REGS[8].regs/Q<0> ),
.O(\read1/Mmux_y_51_528 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_5 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[6].regs/Q<0> ),
.I3(\GEN_REGS[7].regs/Q<0> ),
.I4(\GEN_REGS[5].regs/Q<0> ),
.I5(\GEN_REGS[4].regs/Q<0> ),
.O(\read1/Mmux_y_5_530 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\read1/Mmux_y_4 (
.I0(ra_1_IBUF_2),
.I1(ra_0_IBUF_3),
.I2(\GEN_REGS[2].regs/Q<0> ),
.I3(\GEN_REGS[3].regs/Q<0> ),
.I4(\GEN_REGS[1].regs/Q<0> ),
.I5(\GEN_REGS[0].regs/Q<0> ),
.O(\read1/Mmux_y_4_531 )
);
BUFGP clk_BUFGP (
.I(clk),
.O(clk_BUFGP_29)
);
INV \read2/GND_4_o_GND_4_o_equal_31_o<3>1_INV_0 (
.I(rb_3_IBUF_4),
.O(\read2/GND_4_o_GND_4_o_equal_31_o )
);
INV \read2/GND_4_o_GND_4_o_equal_30_o<2>1_INV_0 (
.I(rb_2_IBUF_5),
.O(\read2/GND_4_o_GND_4_o_equal_30_o )
);
INV \read1/GND_4_o_GND_4_o_equal_31_o<3>1_INV_0 (
.I(ra_3_IBUF_0),
.O(\read1/GND_4_o_GND_4_o_equal_31_o )
);
INV \read1/GND_4_o_GND_4_o_equal_30_o<2>1_INV_0 (
.I(ra_2_IBUF_1),
.O(\read1/GND_4_o_GND_4_o_equal_30_o )
);
INV \GEN_REGS[0].regs/rst_inv1_INV_0 (
.I(rst_IBUF_30),
.O(\GEN_REGS[0].regs/rst_inv )
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 18:40:36
// Design Name:
// Module Name: can
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module can
(
input wire GCLK,
inout wire CANH,
inout wire CANL,
input wire RES,
// Input queue
input wire [107:0] tx_q,
input wire tx_q_push,
output wire tx_q_ovf,
// Output qeue
output reg [107:0] rx_q,
input wire rx_q_pull,
output wire rx_q_ovf
);
assign CANL = ~CANH;
reg [107:0] to_transmit_buf;
reg [107:0] to_receive_buf;
wire refresh_tx;
wire refresh_rx;
queue Q_TX (
.GCLK(GCLK),
.RES(RES),
.get(refresh_tx),
.put(tx_q_push),
.full(tx_q_ovf),
.DIN(tx_q),
.DOUT(to_transmit_buf)
);
queue Q_RX (
.GCLK(GCLK),
.RES(RES),
.get(rx_q_pull),
.put(refresh_rx),
.full(rx_q_ovf),
.DIN(to_receive_buf),
.DOUT(rx_q)
);
endmodule
|
module testbench();
reg [6:0] in_val; //7 bit
reg tb_clk;
wire [31:0] ADDER;
note2dds dds_adder(tb_clk, in_val, ADDER);
// note div 12 ( * 0,08333333333333333333333333333333)
//; Add input / 16 to accumulator >>> 4
//; Add input / 64 to accumulator >>> 6
//; Add input / 256 to accumulator >>> 8
//; Add input / 1024 to accumulator >>> 10
//ìóòü, ïðîùå ñäåëàòü case
wire [3:0] x_div12 = (in_val < 12) ? 0 :
(in_val < 24) ? 1 :
(in_val < 36) ? 2 :
(in_val < 48) ? 3 :
(in_val < 60) ? 4 :
(in_val < 72) ? 5 :
(in_val < 84) ? 6 :
(in_val < 96) ? 7 :
(in_val < 108) ? 8 :
(in_val < 120) ? 9 : 10 ;
initial
begin
$dumpfile("bench.vcd");
$dumpvars(0,testbench);
$display("starting testbench!!!!");
in_val = 0;
repeat (128) begin
#20;
$display("in=", in_val, " div 12 = ", x_div12, " mod12 = ", );
in_val = in_val + 1'b1;
end
$display("finished OK!");
$finish;
end
initial
begin
tb_clk <= 0;
repeat (200000) begin
#1;
tb_clk <= 1;
#1;
tb_clk <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O41A_PP_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Engineers: Robert Keenan and Ciaran Nolan
//
// Design Name: count4
// Module Name: TBcount4ud.v
// Project Name: Lab Assignment
// Description: Verilog testbench for 4-bit up-down counter.
// Generates clock and stimulus signals, but no checking of outputs.
////////////////////////////////////////////////////////////////////////////////
module TBcount4ud;
// Inputs to module being verified
reg clk, rst, en, dir;
// Outputs from module being verified
wire [3:0] cnt;
wire ovw;
// Instantiate the module to be verified
count4 uut (
.clk(clk),
.rst(rst),
.en(en),
.dir(dir),
.cnt(cnt),
.ovw(ovw)
);
// Generate clock signal
initial
begin
clk = 1'b0;
#100; // Wait 100 ns for global reset to finish
forever
#50 clk = ~clk; // 10 MHz clock signal
end
// Generate other input signals
initial
begin
rst = 1'b0; // set initial value of input signals
en = 1'b0;
dir = 1'b1;
#100 rst = 1'b1; // reset pulse begins after 100 ns
@(negedge clk) rst = 1'b0; // ends at next clk falling edge
#200; // wait 2 clock cycles
en = 1'b1; // enable the counter
repeat(10)
@(negedge clk); // wait 10 clock cycles to see counting
en = 1'b0; // disable count
#200 en = 1'b1; // resume after 2 clock cycles
wait (cnt == 4'd3); // wait until count is 3
@(negedge clk) dir = 1'b0; // then change to down counting
wait (cnt == 4'd0); // wait until count gets to 0
@(negedge clk) en = 1'b0; // then disable counting
#200 en = 1'b1; // enable again
#300 rst = 1'b1; // after 3 clock cycles, reset
#100 dir = 1'b1; // change direction while reset active
#100 rst = 1'b0; // normal operation again
#200 dir = 1'b0; // counting down again
wait (cnt == 4'd0) // wait for zero
#350 dir = 1'b1; // after 3.5 clock cycles, count up again
wait (cnt == 4'd15) // wait for max value
@(negedge clk) dir = 1'b0; // then change direction
#300;
$stop;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V |
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:22:21 06/07/2015
// Design Name:
// Module Name: coreid
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module coreid (
input wire clk,
input wire rst_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire regaddr_changed,
output reg [7:0] dout,
output wire oe_n
);
reg [7:0] text[0:15];
integer i;
initial begin
for (i=0;i<16;i=i+1)
text[i] = 8'h00;
text[ 0] = "T";
text[ 1] = "2";
text[ 2] = "4";
text[ 3] = "-";
text[ 4] = "0";
text[ 5] = "7";
text[ 6] = "1";
text[ 7] = "1";
text[ 8] = "2";
text[ 9] = "0";
text[10] = "1";
text[11] = "6";
end
reg [3:0] textindx = 4'h0;
reg reading = 1'b0;
assign oe_n = !(zxuno_addr == 8'hFF && zxuno_regrd==1'b1);
always @(posedge clk) begin
if (rst_n == 1'b0 || (regaddr_changed==1'b1 && zxuno_addr==8'hFF)) begin
textindx <= 4'h0;
reading <= 1'b0;
end
else if (oe_n==1'b0) begin
reading <= 1'b1;
end
else if (reading == 1'b1 && oe_n==1'b1) begin
reading <= 1'b0;
textindx <= textindx + 1;
end
dout <= text[textindx];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_TB_V
`define SKY130_FD_SC_HVL__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_TB_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:22 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_rst_ps7_0_100M_0_stub.v
// Design : zynq_design_1_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
/* Calculate syndromes for S_j for 1 .. 2t-1 */
module bch_syndrome #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Accept first syndrome bit (assumes ce) */
input ce,
input [BITS-1:0] data_in,
output ready,
output [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output reg done = 0
);
localparam M = `BCH_M(P);
localparam [`MAX_M*(1<<(`MAX_M-1))-1:0] TBL = syndrome_build_table(M, `BCH_T(P));
`include "bch_syndrome.vh"
localparam TCQ = 1;
genvar idx;
localparam CYCLES = PIPELINE_STAGES + (`BCH_CODE_BITS(P)+BITS-1) / BITS;
localparam DONE = lfsr_count(M, CYCLES - 2);
localparam REM = `BCH_CODE_BITS(P) % BITS;
localparam RUNT = BITS - REM;
localparam SYN_COUNT = TBL[0+:`MAX_M];
wire [M-1:0] count;
wire [BITS-1:0] data_pipelined;
wire [BITS-1:0] shifted_in;
wire [BITS-1:0] shifted_pipelined;
wire start_pipelined;
reg busy = 0;
if (CYCLES > 2) begin : COUNTER
lfsr_counter #(M) u_counter(
.clk(clk),
.reset(start && ce),
.ce(busy && ce),
.count(count)
);
end else
assign count = DONE;
assign ready = !busy;
always @(posedge clk) begin
if (ce) begin
if (start) begin
done <= #TCQ CYCLES == 1;
busy <= #TCQ CYCLES > 1;
end else if (busy && count == DONE) begin
done <= #TCQ 1;
busy <= #TCQ 0;
end else
done <= #TCQ 0;
end
end
/*
* Method 1 requires data to be aligned to the first transmitted bit,
* which is how input is received. Method 2 requires data to be
* aligned to the last received bit, so we may need to insert some
* zeros in the first word, and shift the remaining bits
*/
generate
if (REM) begin
reg [RUNT-1:0] runt = 0;
assign shifted_in = {start ? {RUNT{1'b0}} : runt, data_in[BITS-1:RUNT]};
always @(posedge clk)
if (ce)
runt <= #TCQ data_in;
end else
assign shifted_in = data_in;
endgenerate
/* Pipelined data for method1 */
pipeline_ce #(PIPELINE_STAGES > 1) u_data_pipeline [BITS-1:0] (
.clk(clk),
.ce(ce),
.i(data_in),
.o(data_pipelined)
);
/* Pipelined data for method2 */
pipeline_ce #(PIPELINE_STAGES > 0) u_shifted_pipeline [BITS-1:0] (
.clk(clk),
.ce(ce),
.i(shifted_in),
.o(shifted_pipelined)
);
pipeline_ce #(PIPELINE_STAGES > 1) u_start_pipeline (
.clk(clk),
.ce(ce),
.i(start),
.o(start_pipelined)
);
/* LFSR registers */
generate
for (idx = 0; idx < SYN_COUNT; idx = idx + 1) begin : SYNDROMES
localparam SYN = idx2syn(idx);
if (syndrome_method(`BCH_T(P), SYN) == 0) begin : METHOD1
dsynN_method1 #(P, SYN, BITS, REG_RATIO, PIPELINE_STAGES) u_syn1a(
.clk(clk),
.start(start),
.start_pipelined(start_pipelined),
.ce((busy || start) && ce),
.data_pipelined(data_pipelined),
.synN(syndromes[idx*M+:M])
);
end else begin : METHOD2
dsynN_method2 #(P, SYN, syndrome_degree(M, SYN), BITS, PIPELINE_STAGES) u_syn2a(
.clk(clk),
.start(start),
.start_pipelined(start_pipelined),
.ce((busy || start) && ce),
.data_in(shifted_in),
.data_pipelined(shifted_pipelined),
.synN(syndromes[idx*M+:M])
);
end
end
endgenerate
endmodule
/* Syndrome expansion/shuffling */
module bch_syndrome_shuffle #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE
) (
input clk,
input start, /* Accept first syndrome bit */
input ce, /* Shuffle cycle */
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output reg [(2*`BCH_T(P)-1)*`BCH_M(P)-1:0] syn_shuffled = 0
);
localparam M = `BCH_M(P);
localparam [`MAX_M*(1<<(`MAX_M-1))-1:0] TBL = syndrome_build_table(M, `BCH_T(P));
`include "bch_syndrome.vh"
localparam TCQ = 1;
localparam T = `BCH_T(P);
genvar i;
wire [(2*T-1)*M-1:0] bypass_in_shifted;
wire [(2*T-1)*M-1:0] syndromes_pre_expand;
wire [(2*T-1)*M-1:0] expand_in;
wire [(2*T-1)*M-1:0] expand_in1;
wire [(2*T-1)*M-1:0] syn_expanded;
for (i = 0; i < 2 * T - 1; i = i + 1) begin : ASSIGN
assign syndromes_pre_expand[i*M+:M] = syndromes[dat2idx(i+1)*M+:M] & {M{start}};
end
/* Shuffle syndromes */
rotate_right #((2*T-1)*M, 3*M) u_rol_e(syndromes_pre_expand, expand_in1);
reverse_words #(M, 2*T-1) u_rev(expand_in1, expand_in);
rotate_left #((2*T-1)*M, 2*M) u_rol_b(syn_shuffled, bypass_in_shifted);
/*
* We need to combine syndrome expansion and shuffling into a single
* operation so we can optimize LUT usage for an XOR carry chain. It
* causes a little confusion as we need to select expansion method
* based on the pre-shuffled indexes as well as pass in the pre-
* shuffled index to the expand method.
*/
for (i = 0; i < 2 * T - 1; i = i + 1) begin : EXPAND
localparam PRE = (2 * T - 1 + 2 - i) % (2 * T - 1); /* Pre-shuffle value */
if (syndrome_method(T, dat2syn(PRE+1)) == 0) begin : METHOD1
syndrome_expand_method1 #(P) u_expand(
.in(expand_in[i*M+:M]),
.out(syn_expanded[i*M+:M])
);
end else begin : METHOD2
syndrome_expand_method2 #(P, PRE+1) u_expand(
.in(expand_in[i*M+:M]),
.out(syn_expanded[i*M+:M])
);
end
end
always @(posedge clk)
if (start || ce)
syn_shuffled <= #TCQ syn_expanded ^ ({(2*T-1)*M{!start}} & bypass_in_shifted);
endmodule
module bch_errors_present #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start,
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output done,
output errors_present /* Valid during done cycle */
);
localparam M = `BCH_M(P);
genvar i;
wire [(`BCH_SYNDROMES_SZ(P)/M)-1:0] syndrome_zero;
wire [(`BCH_SYNDROMES_SZ(P)/M)-1:0] syndrome_zero_pipelined;
generate
for (i = 0; i < `BCH_SYNDROMES_SZ(P)/M; i = i + 1) begin : ZEROS
assign syndrome_zero[i] = |syndromes[i*M+:M];
end
endgenerate
pipeline #(PIPELINE_STAGES > 0) u_sz_pipeline [`BCH_SYNDROMES_SZ(P)/M-1:0] (
.clk(clk),
.i(syndrome_zero),
.o(syndrome_zero_pipelined)
);
pipeline #(PIPELINE_STAGES > 1) u_present_pipeline (
.clk(clk),
.i(|syndrome_zero_pipelined),
.o(errors_present)
);
pipeline #(PIPELINE_STAGES) u_done_pipeline (
.clk(clk),
.i(start),
.o(done)
);
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module timestamp640
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001,
parameter CLKDV = 4
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK320,
input wire CLK160,
input wire CLK40,
input wire DI,
input wire [63:0] EXT_TIMESTAMP,
output wire [63:0] TIMESTAMP_OUT,
input wire EXT_ENABLE,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire FIFO_READ_TRAILING,
output wire FIFO_EMPTY_TRAILING,
output wire [31:0] FIFO_DATA_TRAILING
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
timestamp640_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(IDENTIFIER),
.CLKDV(4)
) i_timestamp640_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK320(CLK320),
.CLK160(CLK160),
.CLK40(CLK40),
.DI(DI),
.TIMESTAMP_OUT(TIMESTAMP_OUT),
.EXT_TIMESTAMP(EXT_TIMESTAMP),
.EXT_ENABLE(EXT_ENABLE),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_READ_TRAILING(FIFO_READ_TRAILING),
.FIFO_EMPTY_TRAILING(FIFO_EMPTY_TRAILING),
.FIFO_DATA_TRAILING(FIFO_DATA_TRAILING)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: John Adams Institute at the University of Oxford
// Engineer: Glenn Christian
//
// Create Date: 09:24:59 10/24/2009
// Design Name: font5-firmware
// Module Name: FONT5_base
// Project Name: font5_base
// Target Devices: xc5vlx50t-3ff1136
// Tool versions: Xilinx ISE14.7
// Description: Pseudo top-level for the FONT5 digital signal processing gateware
//
// Dependencies:
//
//
//////////////////////////////////////////////////////////////////////////////////
module FONT5_base(
`ifdef XILINX_ISIM
output store_strb,
`endif
//Inputs from top level wrapper
input clk357,
input clk40,
input clk40_ibufg,
input signed [12:0] ch1_data_in_del,
input signed [12:0] ch2_data_in_del,
input signed [12:0] ch3_data_in_del,
input signed [12:0] ch4_data_in_del,
input signed [12:0] ch5_data_in_del,
input signed [12:0] ch6_data_in_del,
input signed [12:0] ch7_data_in_del,
input signed [12:0] ch8_data_in_del,
input signed [12:0] ch9_data_in_del,
input rs232_in,
//Inputs/Outputs to top level pins
//output amp_trig,
//output amp_trig2,
(* IOB = "TRUE" *) output reg adc_powerdown = 1'b1,
(* shreg_extract = "no" *) output reg iddr_ce = 1'b0,
//output dcm200_rst, //output to xlnx
output signed [12:0] dac1_out,
output dac1_clk,
output signed [12:0] dac2_out,
output dac2_clk,
// output signed [12:0] dac3_out,
// output dac3_clk,
// output signed [12:0] dac4_out,
// output dac4_clk,
//(* IOB = "TRUE" *) output reg [12:0] dac1_out,
//(* IOB = "TRUE" *) output reg dac1_clk,
//(* IOB = "TRUE" *) output reg [12:0] dac2_out,
//(* IOB = "TRUE" *) output reg dac2_clk,
//(* IOB = "TRUE" *) output reg [12:0] dac3_out,
//(* IOB = "TRUE" *) output reg dac3_clk,
//(* IOB = "TRUE" *) output reg [12:0] dac4_out,
//(* IOB = "TRUE" *) output reg dac4_clk,
output rs232_out,
(* IOB = "TRUE" *) output reg led0_out,
(* IOB = "TRUE" *) output reg led1_out,
(* IOB = "TRUE" *) output reg led2_out,
output trim_cs_ld,
output trim_sck,
output trim_sdi,
(* IOB = "TRUE" *) output reg diginput1A,
(* IOB = "TRUE" *) output reg diginput1B,
input diginput1,
(* IOB = "TRUE" *) output reg diginput2A,
(* IOB = "TRUE" *) output reg diginput2B,
input diginput2,
//(* IOB = "TRUE" *) output reg auxOutA,
output reg auxOutA,
//output auxOutA,
//(* IOB = "TRUE" *) output reg auxOutB,
output reg auxOutB,
//output diginput2_loopback, //For monitoring digital input
//Internal control I/Os to top level
input dcm200_locked, //input to top
output reg clk_blk = 1'b0, //output to xlnx
input idelayctrl_rdy, //input to top
output clk357_idelay_ce, //output to xlnx
output clk357_idelay_rst, //output to xlnx
output idelay_rst, //output to xlnx
`ifdef FASTCLK_INT
input dcm360_locked, //input to top
output fastClk_sel, //output to xlnx
`endif
`ifdef CLK357_PLL
output dcm200_rst, //output to xlnx
input pll_clk357_locked, //input to top
output reg clkPLL_sel_a, //output to xlnx
`endif
output run, //output to xlnx
output delay_calc_strb1, //output to xlnx from ADC_block
output delay_calc_strb2, //output to xlnx from ADC_block
output delay_calc_strb3, //output to xlnx from ADC_block
output delay_trig1, //output to xlnx from top (UART decoder)
output delay_trig2, //output to xlnx from top (UART decoder)
output delay_trig3, //output to xlnx from top (UART decoder)
output adc1_drdy_delay_ce, //output to xlnx from ADC_block
output adc2_drdy_delay_ce, //output to xlnx from ADC_block
output adc3_drdy_delay_ce, //output to xlnx from ADC_block
output adc1_clk_delay_ce, //output to xlnx from ADC_block
output adc2_clk_delay_ce, //output to xlnx from ADC_block
output adc3_clk_delay_ce, //output to xlnx from ADC_block
output adc1_data_delay_ce, //output to xlnx from ADC_block
output adc2_data_delay_ce, //output to xlnx from ADC_block
output adc3_data_delay_ce, //output to xlnx from ADC_block
input IDDR1_Q1, //input to top (to Alignment monitors via ADC block)
input IDDR1_Q2, //input to top (to Alignment monitors via ADC block)
input IDDR2_Q1, //input to top (to Alignment monitors via ADC block)
input IDDR2_Q2, //input to top (to Alignment monitors via ADC block)
input IDDR3_Q1, //input to top (to Alignment monitors via ADC block)
input IDDR3_Q2, //input to top (to Alignment monitors via ADC block)
//inout DirectIO1 //Bi-directional I/O port for synchronisation
output DirIOB,
input auxInA,
output auxOutC
);
//parameters and defintions
parameter DSP_WIDTH = 16;
//`include "font5_base_top.vh"
//`include "definitions.vh" // NO NEED TO INCLUDE ANYMORE AS IT IS DEFINED AS GLOBAL
`ifdef FASTCLK_192MHZ
parameter FASTCLK_PERIOD = 5.208;
`else
parameter FASTCLK_PERIOD = 2.800;
`endif
//`define INCLUDE_TESTBENCH
//`define DOUBLE_CONTROL_REGS
//`define ADDPIPEREGS
//`define DISABLE_AUXOUTS;
//`define LOAD_ATF_DEFAULTS
`define LOAD_ATF_DEFAULTS
`ifdef DOUBLE_CONTROL_REGS
parameter N_CTRL_REGS = 128;
parameter CR_WIDTH = 7;
parameter ADDROFF = 64;
`else
parameter N_CTRL_REGS = 64;
parameter CR_WIDTH = 6;
parameter ADDROFF = 0;
`endif
reg [CR_WIDTH-1:0] ctrl_regs [0:N_CTRL_REGS-1];
reg [CR_WIDTH-1:0] ctrl_regs_mem [0:N_CTRL_REGS-1];
//`include "H:\Firmware\FONT5_base\sources\verilog\ctrl_regs.v"
//`ifdef BUILD_ATF //temporary solution until ctrl_regs module is tidied up
`include "ctrl_regs.v"
//`else
// `include "ctrl_regs_CTF.v"
//`endif
//`ifdef XILINX_ISIM
// `include "H:\Firmware\FONT5_base\sources\verilog\ctrl_regs_init_sim.v"
//`else
// `include "H:\Firmware\FONT5_base\sources\verilog\ctrl_regs_init.v"
//`endif
/*`ifdef LOAD_ATF_DEFAULTS
`include "H:\Firmware\FONT5_base\sources\verilog\ctrl_regs_init_ATF.v"
`else
`ifdef LOAD_CTF_DEFAULTS
`include "H:\Firmware\FONT5_base\sources\verilog\ctrl_regs_init_CTF.v"
`else
`include "H:\Firmware\FONT5_base\sources\verilog\ctrl_regs_init.v"
`endif
`endif*/
`ifdef LOAD_ATF_DEFAULTS
`include "ctrl_regs_init_ATF.v"
`else
`ifdef LOAD_CTF_DEFAULTS
`include "ctrl_regs_init_CTF.v"
`else
`include "ctrl_regs_init.v"
`endif
`endif
//Instantiate USR_ACCESS register
//wire [31:0] usr_access;
// USR_ACCESS_VIRTEX5: Configuration Data Memory Access Port
// Virtex-5
// Xilinx HDL Language Template, version 13.2
/* USR_ACCESS_VIRTEX5 USR_ACCESS_VIRTEX5_inst (
.CFGCLK(), // 1-bit configuration clock output
.DATA(usr_access), // 32-bit config data output
.DATAVALID() // 1-bit data valid output
);*/
// End of USR_ACCESS_VIRTEX5_inst instantiation
// %%%%%%%%%%% WIRE DIGITAL INPUT TO TRIGGER LOOPBACK %%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire clk2_16_ext = (use_trigSyncExt) ? diginput1 : 1'b0;
wire trig = diginput2;
//assign diginput2_loopback = diginput2;
//wire diginput2_loopback = diginput2;
//assign auxOutA = diginput2;
// **** Reset controller ****
// Deals with resetting DCM, idelayctrl and iodelay elements
wire full_rst_trig;
reset_ctrl reset_ctrl1(
.clk40(clk40_ibufg),
.idelay_rst_trig(1'b0), //Always perform a full DCM reset
.full_rst_trig(full_rst_trig),
.dcm_rst(dcm200_rst),
.idelay_rst(idelay_rst)
);
wire rst_state;
reset_detector reset_detector1(clk40, dcm200_rst, rst_state);
//always @(posedge clk2_16_tmp) clk_align <= (clk357_delayed) ? 1 : 0;
// **** incrementor for 357MHz IODELAY ****
wire [5:0] clk357_idelay_value;
wire [5:0] clk357_idelay_mon;
wire clk357_idelay_trig;
iodelay_incrementor clk357_idelay_inc(
.clk40(clk40),
.rst(clk357_idelay_rst | idelay_rst),
.count_trig(clk357_idelay_trig),
.spec_delay(clk357_idelay_value),
.inc_en(clk357_idelay_ce),
.actual_delay(clk357_idelay_mon)
);
// *** Instantiate Internal Testbench ***//
/*wire auxOut_en;
`ifdef DISABLE_AUXOUTS assign auxOut_en = 1'b0;
`else assign auxOut_en = 1'b1;
`endif*/
/*reg auxOutA_a, auxOutB_a;
always @(posedge clk357) begin
auxOutA <= auxOutA_a;
auxOutB <= auxOutB_a;
end*/
wire [3:0] TFSMstate;
`ifdef INCLUDE_TESTBENCH
wire tb_trigOut, tb_dataOut;
supply0 gnd;
always @(posedge clk357) begin
//auxOutA <= tb_trigOut;
//auxOutA <= diginput2_loopback;
//auxOutA <= (auxOut_en) ? gnd : 1'bz;
//auxOutB <= (auxOut_en) ? tb_dataOut : 1'bz;
auxOutA <= gnd;
auxOutB <= tb_dataOut;
//auxOutB <= gnd;
end
bench #(
.MAX_CNT(21'd1402596),
.RING_CLK_HOLDOFF(8'd82),
.DOUT_OFFSET(8'd27),
.OPWIDTH(10'd1000)) bench(clk357, tb_trigOut, tb_dataOut);
`elsif BUILD_ATF
wire tb_trig_out, amp1_trig, amp2_trig;
(* ASYNC_REG = "TRUE" *) reg trig_out_en_a = 1'b0, trig_out_en_b = 1'b0;
//reg trig_out_en_c = 1'b0;
always @ (posedge clk357) begin
trig_out_en_a <= trig_out_en;
trig_out_en_b <= trig_out_en_a;
//trig_out_en_c <= trig_out_en_b;
auxOutA <= amp1_trig & trig_out_en_b;
auxOutB <= amp2_trig & trig_out_en_b;
end
assign tb_trigOut = 1'b0;
`elsif BUILD_CTF
wire tb_trigOut, amp1_trig, amp2_trig;
AmpTrig2 #(26) AmpTrig1(clk357, TFSMstate[1], trig_out_en, trig_out1_delay, amp1_trig);
AmpTrig2 #(26) AmpTrig2(clk357, TFSMstate[1], trig_out_en, trig_out2_delay, amp2_trig);
assign tb_trigOut = 1'b0;
always @ (posedge clk357) begin
auxOutA <= amp1_trig;
auxOutB <= amp2_trig;
end
`else
supply0 gnd;
wire tb_trig_out;
always @ (posedge clk357) begin
auxOutA <= gnd;
auxOutB <= gnd;
end
`endif
// %%%%%%%% TRIGGER DIVIDER %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire trigger, trig_strb;
//wire trig_mux;
wire trig_rdy;
/*reg trig_rdy_a, trig_rdy_b, blocked;
reg run_a, run_b;
always @(posedge clk357) begin
run_a <= run;
run_b <= run_a;
trig_rdy_a <= trig_rdy;
trig_rdy_b <= trig_rdy_a;
if (trigger) blocked <= 1'b1;
else if (trig_rdy_a && ~trig_rdy_b) blocked <= 1'b0;
else blocked <= blocked;
end
*/
wire [5:0] pulse_ctr;
wire pulse_ctr_rst;
wire pile_up;
trigger_divider trig_div (
.clk(clk357),
.trig_ext(trig),
.trig_int(tb_trigOut),
.trig_int_en(trig_int_en),
.empty_trig_blk(empty_trig_blk),
//.trig_blk((trig_blk && blocked) || ~run_b),
.trig_blk(trig_blk),
.trig_max_cnt(cr_trig_max_cnt),
.trig_seq_sel(cr_trig_seq_sel),
.pulse_ctr_rst_b(pulse_ctr_rst),
.run(run),
.trig_rdy(trig_rdy),
.trig_out(trigger),
//.trig_strb(trig_strb)
.trig_strb(trig_strb),
.pulse_ctr(pulse_ctr),
.pile_up(pile_up)
);
// %%%%%%%%%%%%%%%%% TIMING & SYNCHRONISATION MODULE %%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Brings trigger and ring clock onto 357 domain. Uses them to produce the
// strobes and triggers for ADCs, DAQ and amplifier.
// All control signals from 357MHz control registers
wire store_strb;
wire adc_align_en;
// Control register wires
//wire cr_clk2_16_edge_sel;
//wire [11:0] cr_trig_delay;
//wire [6:0] cr_trig_out_delay;
//wire [6:0] cr_trig_out_delay2;
//wire cr_trig_out_en;
//wire trig_out_temp;
//wire trig_out_temp2;
//wire [7:0] cr_p1_b1_pos;
//wire [7:0] cr_p1_b2_pos;
//wire [7:0] cr_p1_b3_pos;
//wire [7:0] cr_p2_b1_pos;
//wire [7:0] cr_p2_b2_pos;
//wire [7:0] cr_p2_b3_pos;
//wire [7:0] cr_p3_b1_pos;
//wire [7:0] cr_p3_b2_pos;
//wire [7:0] cr_p3_b3_pos;
//wire [6:0] cr_sample_hold_off;
wire led1_strb;
//wire p1_bunch_strb;
//wire p2_bunch_strb;
//wire p3_bunch_strb;
wire adc_powerup;
//wire [3:0] TFSMstate;
timing_synch_fsm #(.FASTCLK_PERIOD(FASTCLK_PERIOD)) timing_synch1 (
.fastClk(clk357),
.slowClk(clk40),
//.rst(dcm200_rst),
.trigSyncExt(clk2_16_ext),
.trigSyncExt_edge_sel(cr_clk2_16_edge_sel),
.trig(trigger),
//.trig(trigger && run),
.trig_delay(cr_trig_delay),
.sample_hold_off(cr_sample_hold_off),
.num_smpls(num_smpls),
.trigSync_size_b(trigSync_size),
.use_trigSyncExt_b(use_trigSyncExt),
/*.p1_b1_pos(),
.p1_b2_pos(),
.p1_b3_pos(),
.p2_b1_pos(),
.p2_b2_pos(),
.p2_b3_pos(),
.p3_b1_pos(),
.p3_b2_pos(),
.p3_b3_pos(),
.trig_out_delay(),
.trig_out_delay2(),
.amp_trig(),
.amp_trig2(),*/
// .p1_b1_pos(cr_p1_b1_pos),
// .p1_b2_pos(cr_p1_b2_pos),
// .p1_b3_pos(cr_p1_b3_pos),
// .p2_b1_pos(cr_p2_b1_pos),
// .p2_b2_pos(cr_p2_b2_pos),
// .p2_b3_pos(cr_p2_b3_pos),
// .p3_b1_pos(cr_p3_b1_pos),
// .p3_b2_pos(cr_p3_b2_pos),
// .p3_b3_pos(cr_p3_b3_pos),
// .trig_out_delay(cr_trig_out_delay),
// .trig_out_delay2(cr_trig_out_delay2),
// .amp_trig(trig_out_temp),
// .amp_trig2(trig_out_temp2),
`ifdef BUILD_ATF
.trig_out1_delay(trig_out1_delay),
.trig_out2_delay(trig_out2_delay),
.amp_trig1_out(amp1_trig),
.amp_trig2_out(amp2_trig),
`endif
.store_strb_b(store_strb),
.adc_powerup(adc_powerup),
.adc_align_en(adc_align_en),
//.p1_bunch_strb(),
//.p2_bunch_strb(),
//.p3_bunch_strb(),
//.p2_bunch_strb(p2_bunch_strb),
//.p3_bunch_strb(p3_bunch_strb),
.trig_led_strb(led2_strb),
.clk2_16_led_strb(led1_strb),
.state(TFSMstate)
);
// Register amp trig, powerdown and align_en for timing
//reg trig_out_temp_a, trig_out_temp_b, trig_out_temp_c, trig_out_temp_d;
//reg trig_out_temp2_a, trig_out_temp2_b, trig_out_temp2_c, trig_out_temp2_d;
reg adc_align_en_a = 1'b0, adc_align_en_b = 1'b0;//adc_align_en_c, adc_align_en_d;
//(* shreg_extract = "no" *) reg adc_powerup_c = 1'b0, adc_powerup_b = 1'b0, adc_powerup_a = 1'b0;
//(* shreg_extract = "no" *) reg adc_powerup_a = 1'b1, adc_powerup_b = 1'b1, adc_powerup_c = 1'b1;
always @(posedge clk357) begin
/*
trig_out_temp_a <= trig_out_temp;
// synthesis attribute shreg_extract of trig_out_temp_a is "no";
trig_out_temp_b <= trig_out_temp_a;
// synthesis attribute shreg_extract of trig_out_temp_b is "no";
trig_out_temp_c <= trig_out_temp_b;
// synthesis attribute shreg_extract of trig_out_temp_c is "no";
trig_out_temp_d <= trig_out_temp_c;
// synthesis attribute shreg_extract of trig_out_temp_d is "no";
trig_out_temp2_a <= trig_out_temp2;
// synthesis attribute shreg_extract of trig_out_temp2_a is "no";
trig_out_temp2_b <= trig_out_temp2_a;
// synthesis attribute shreg_extract of trig_out_temp2_b is "no";
trig_out_temp2_c <= trig_out_temp2_b;
// synthesis attribute shreg_extract of trig_out_temp2_c is "no";
trig_out_temp2_d <= trig_out_temp2_c;
// synthesis attribute shreg_extract of trig_out_temp2_d is "no";
*/
adc_align_en_a <= adc_align_en;
// synthesis attribute shreg_extract of align_en_a is "no";
adc_align_en_b <= adc_align_en_a;
// synthesis attribute shreg_extract of align_en_b is "no";
//adc_align_en_c <= adc_align_en_b;
// synthesis attribute shreg_extract of align_en_b is "no";
//adc_align_en_d <= adc_align_en_c;
// synthesis attribute shreg_extract of align_en_d is "no";
//adc_powerup_a <= adc_powerup;
// adc_powerup_a <= ~adc_powerup;
// adc_powerup_b <= adc_powerup_a;
// adc_powerup_c <= adc_powerup_b;
// adc_powerdown <= adc_powerup_c;
//adc_powerdown <= ~adc_powerup_a;
end
// Synchronise the ADC_powerdown and ADC_powerup on the 40 MHz domain
(* ASYNC_REG = "true" *) reg adc_powerup_slow_a = 1'b0, adc_powerup_slow_b = 1'b0;
always @(posedge clk40) begin
adc_powerup_slow_a <= adc_powerup; //Sync first stage
adc_powerup_slow_b <= adc_powerup_slow_a; // Sync second stage
adc_powerdown <= ~adc_powerup_slow_b; //Extra stage needed as this REG in IOB, can't be used in synchroniser + inverter (logic) usage
iddr_ce <= adc_powerup_slow_b; // Output register for CE of IDDR, *_slow_b used in logic!
end
//assign amp_trig = trig_out_temp_d & cr_trig_out_en;
//assign amp_trig2 = trig_out_temp2_d & cr_trig_out_en;
//assign adc_powerdown = ~adc_powerup_d;
// %%%%%%%%%%%%%%%%%%%%%%% STORE STROBE FAN OUT %%%%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Relax timing by duplicating sotre strobe register for each ADC group
reg p1_store_strb = 1'b0, p2_store_strb = 1'b0, p3_store_strb = 1'b0;
always @(posedge clk357) begin
p1_store_strb <= store_strb;
// synthesis attribute shreg_extract of p1_store_strb is "no";
p2_store_strb <= store_strb;
// synthesis attribute shreg_extract of p2_store_strb is "no";
p3_store_strb <= store_strb;
// synthesis attribute shreg_extract of p3_store_strb is "no";
clk_blk <= store_strb;
// synthesis attribute shreg_extract of clk_blk is "no";
end
//Match bunch strobes to store_strb
/*
reg p3_bunch_strb_a, p2_bunch_strb_a, p1_bunch_strb_a;
always @(posedge clk357) begin
p3_bunch_strb_a <= p3_bunch_strb;
p2_bunch_strb_a <= p2_bunch_strb;
p1_bunch_strb_a <= p1_bunch_strb;
end
*/
// %%%%%%%%%%%%%%%%%%%%%%%%%% LIGHT LEDS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Light when 357MHz is present
// Flash ~200ms on trigger
//reg led2_out;
reg [22:0] led2_count = 23'd0;
always @(posedge clk40) begin
`ifdef CLK357_PLL
led0_out <= pll_clk357_locked;
`else
led0_out <= 1'b1;
`endif
if (dcm200_rst) begin
led2_out <= 0;
led2_count <= 0;
end else begin
case (led2_count)
23'd0: if (led2_strb) led2_count <= 23'd1;
23'd1: begin
led2_out <= 1;
led2_count <= led2_count + 1;
end
23'd8388607: begin
led2_out <= 0;
led2_count <= 0;
end
default: led2_count <= led2_count + 1;
endcase
end
end
// Flash just over a ring clock cycle on ring clock edge. Will be lit
// all the time the clock is present
//reg led1_out;
reg [4:0] led1_count = 5'd0;
always @(posedge clk40) begin
if (dcm200_rst) begin
led1_out <= 0;
led1_count <= 0;
end else begin
if (led1_strb) begin
led1_count <= 5'd1;
led1_out <= led1_out;
end else begin
case (led1_count)
5'd0: begin
led1_count <= 0;
led1_out <= led1_out;
end
5'd1: begin
led1_out <= 1;
led1_count <= led1_count + 1;
end
5'd31: begin
led1_out <= 0;
led1_count <= 0;
end
default: begin
led1_count <= led1_count + 1;
led1_out <= led1_out;
end
endcase
end
end
end
/////////////////////////////////////////////////////////////////////////////
///// Channel Offset De-multiplexer /////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
wire signed [12:0] chan1_offset, chan2_offset, chan3_offset;
wire signed [12:0] chan4_offset, chan5_offset, chan6_offset;
wire signed [12:0] chan7_offset, chan8_offset, chan9_offset;
chanOffsetMUX chanOffsetDeMUX (
.clk(clk357),
.chanOffset(chanOffset),
.chanOffsetSel(chanOffsetSel),
.chan1_offset(chan1_offset),
.chan2_offset(chan2_offset),
.chan3_offset(chan3_offset),
.chan4_offset(chan4_offset),
.chan5_offset(chan5_offset),
.chan6_offset(chan6_offset),
.chan7_offset(chan7_offset),
.chan8_offset(chan8_offset),
.chan9_offset(chan9_offset)
);
// %%%%%%%%%%%%%%%%%% P1 ADC GROUP ADC_BLOCK MODULE %%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Bring the data from the 3 ADCs for P1 into the module via an adc_clock
// The adc block ensures the adc data is aligned with the 357MHz clock
// All control signals from 40MHz control registers
reg [6:0] cr_p1_offset_delay = 7'd0;
wire [5:0] cr_p1_scan_delay;
wire [1:0] cr_p1_align_ch_sel;
wire signed [13:0] chan1_data;
wire signed [13:0] chan2_data;
wire signed [13:0] chan3_data;
wire p1_mon_strb;
wire p1_mon_saturated;
wire [5:0] p1_mon_total_data_del;
wire [5:0] p1_mon_total_drdy_del;
wire [6:0] p1_mon_delay_mod;
wire [6:0] p1_mon_count1;
wire [6:0] p1_mon_count2;
wire [6:0] p1_mon_count3;
wire [5:0] p1_mon_adc_clk_del;
adc_block p1_adc_block(
.clk357(clk357),
.clk40(clk40),
.rst(dcm200_rst),
.align_en(adc_align_en_b), // From time/synch mod.
.align_ch_sel(cr_p1_align_ch_sel),
//.ch1_data_in_del(ch1_data_in_del),
//.ch2_data_in_del(ch2_data_in_del),
//.ch3_data_in_del(ch3_data_in_del),
.data_offset_delay(cr_p1_offset_delay),
.scan_delay(cr_p1_scan_delay),
.delay_trig(delay_trig1),
.IDDR_Q1(IDDR1_Q1),
.IDDR_Q2(IDDR1_Q2),
//.ch1_data_out(p1_xdif_data),
//.ch2_data_out(p1_ydif_data),
//.ch3_data_out(p1_sum_data),
.saturated(p1_mon_saturated),
.adc_data_delay(p1_mon_total_data_del), //Monitoring
.adc_drdy_delay(p1_mon_total_drdy_del), //Monitoring
.delay_modifier(p1_mon_delay_mod), //Monitoring
.monitor_strb(p1_mon_strb), //Monitoring
.count1(p1_mon_count1), //Monitoring
.count2(p1_mon_count2), //Monitoring
.count3(p1_mon_count3), //Monitoring
.adc_clk_delay_mon(p1_mon_adc_clk_del), //Monitoring
.delay_calc_strb(delay_calc_strb1),
.adc_drdy_delay_ce(adc1_drdy_delay_ce),
.adc_clk_delay_ce(adc1_clk_delay_ce),
.adc_data_delay_ce(adc1_data_delay_ce)
);
parameter ch1_bitflip = ~13'b1011010000101;
parameter ch2_bitflip = ~13'b0101110001000;
parameter ch3_bitflip = ~13'b0001011110100;
(* shreg_extract = "no" *) reg [4:0] bank1_sr_tap_a = 5'd2, bank1_sr_tap_b = 5'd2, bank1_sr_tap_c = 5'd2;
reg [1:0] bank1_sr_bypass = 2'b11;
dataRegConvert #(13, ch1_bitflip ^ -13'sd4096) ch1_dataRegConvert(clk357, bank1_sr_bypass, ch1_data_in_del, chan1_offset, bank1_sr_tap_c, chan1_data);
dataRegConvert #(13, ch2_bitflip ^ -13'sd4096) ch2_dataRegConvert(clk357, bank1_sr_bypass, ch2_data_in_del, chan2_offset, bank1_sr_tap_c, chan2_data);
dataRegConvert #(13, ch3_bitflip ^ -13'sd4096) ch3_dataRegConvert(clk357, bank1_sr_bypass, ch3_data_in_del, chan3_offset, bank1_sr_tap_c, chan3_data);
//dataRegConvert #(13) ch1_dataRegConvert(clk357, ch1_data_in_del, p1_xdif_data);
//dataRegConvert #(13) ch2_dataRegConvert(clk357, ch2_data_in_del, p1_ydif_data);
//dataRegConvert #(13) ch3_dataRegConvert(clk357, ch3_data_in_del, p1_sum_data);
// Flip the signals which were incorrect polarity at LVDS inputs
//`include "p1_adcblock_flip_signals.v"
//Insert Droop Correction Filter
//wire signed [DSP_WIDTH-1:0] chan1_IIR_out, chan1_RAM_data;
//wire signed [DSP_WIDTH-1:0] p1_ydif_IIR_out, p1_ydif_RAM_data;
wire signed [DSP_WIDTH-1:0] chan1_IIR_out, chan2_IIR_out, chan3_IIR_out;
wire signed [DSP_WIDTH-1:0] chan1_RAM_data, chan2_RAM_data, chan3_RAM_data;
//reg signed [DSP_WIDTH:0] chan1_RAM_data = 17'd0, chan2_RAM_data = 17'd0, chan3_RAM_data = 17'd0;
//wire signed [DSP_WIDTH-1:0] chan1_RAM_data, chan3_RAM_data;
//wire signed [DSP_WIDTH:0] chan2_RAM_data;
//reg signed [DSP_WIDTH-1:0] chan1_RAM_data = 14'd0, chan2_RAM_data = 14'd0, chan3_RAM_data = 14'd0;
//wire signed [DSP_WIDTH-1:0] chan3_IIR_out, chan3_RAM_data;
wire ch1_oflowDet, ch2_oflowDet, ch3_oflowDet;
//synchronise signals coming in from uart
//(* shreg_extract = "no" *) reg [10:0] IIRbypass_a = 11'd0, IIRbypass_b = 11'd0;
reg [10:0] IIRbypass_a = 11'd0, IIRbypass_b = 11'd0;
//reg [12:0] p1_xdif_data_reg, p1_ydif_data_reg, p1_sum_data_reg;
//reg [12:0] p1_xdif_corr, p1_ydif_corr, p1_sum_corr;
always @(posedge clk357) begin
bank1_sr_tap_a <= bank1_sr_tap;
bank1_sr_tap_b <= bank1_sr_tap_a;
bank1_sr_tap_c <= bank1_sr_tap_b;
case (bank1_sr_tap_b)
5'd0: bank1_sr_bypass <= 2'b01;
5'd1: bank1_sr_bypass <= 2'b10;
default: bank1_sr_bypass <= 2'b00;
endcase
IIRbypass_a <= IIRbypass;
IIRbypass_b <= IIRbypass_a;
// p1_xdif_data_reg <= p1_xdif_data;
// p1_ydif_data_reg <= p1_ydif_data;
// p1_sum_data_reg <= p1_sum_data;
// p1_xdif_corr <= p1_xdif_IIR_out + p1_xdif_data_reg;
// p1_ydif_corr <= p1_ydif_IIR_out + p1_ydif_data_reg;
// p1_sum_corr <= p1_sum_IIR_out + p1_sum_data_reg;
end
antiDroopIIR #(17) antiDroopIIR_ch1(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p1_xdif_data_fix),
.din(chan1_data[12:0]),
.tapWeight(ch1_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch1_oflowDet),
.dout(chan1_IIR_out)
);
antiDroopIIR #(17) antiDroopIIR_ch2(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p1_ydif_data_fix),
.din(chan2_data[12:0]),
.tapWeight(ch2_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch2_oflowDet),
.dout(chan2_IIR_out)
);
antiDroopIIR #(17) antiDroopIIR_ch3(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p1_sum_data_fix),
.din(chan3_data[12:0]),
.tapWeight(ch3_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch3_oflowDet),
.dout(chan3_IIR_out)
);
reg bank1_oflowDet = 1'b0;
wire chan1_offset_oflow, chan2_offset_oflow, chan3_offset_oflow;
//wire chan2_offset_oflow;
//reg signed [12:0] chan2_offset_a = 13'd0, chan2_offset_b = 13'd0;
//reg signed [12:0] chan5_offset_a = 13'd0, chan5_offset_b = 13'd0;
always @(posedge clk357) begin
//chan2_offset_a <= chan2_offset;
//chan2_offset_b <= chan2_offset_a;
//chan5_offset_a <= chan5_offset;
//chan5_offset_b <= chan5_offset_a;
//chan1_RAM_data <= ((~IIRbypass_b[0]) ? {chan1_data[12:0], 3'b000} : chan1_IIR_out);// + {chan1_offset, 3'b000};
//chan2_RAM_data <= ((~IIRbypass_b[1]) ? {chan2_data[12:0], 3'b000} : chan2_IIR_out);// + {chan2_offset, 3'b000};
//chan3_RAM_data <= ((~IIRbypass_b[2]) ? {chan3_data[12:0], 3'b000} : chan3_IIR_out);// + {chan3_offset, 3'b000};
//chan1_RAM_data <= chan1_RAM_data_b + {chan1_offset, 3'b000};
//chan2_RAM_data <= chan2_RAM_data_b + {chan2_offset, 3'b000};
//chan3_RAM_data <= chan3_RAM_data_b + {chan3_offset, 3'b000};
bank1_oflowDet <= (ch1_oflowDet | ch2_oflowDet | ch3_oflowDet | chan1_offset_oflow | chan2_offset_oflow | chan3_offset_oflow);
//bank1_oflowDet <= (ch1_oflowDet | ch2_oflowDet | ch3_oflowDet);
end
//assign p1_xdif_RAM_data = (~IIRbypass_b[0]) ? p1_xdif_data_fix : p1_xdif_IIR_out;
//assign p1_ydif_RAM_data = (~IIRbypass_b[1]) ? p1_ydif_data_fix : p1_ydif_IIR_out;
//assign p1_sum_RAM_data = (~IIRbypass_b[2]) ? p1_sum_data_fix : p1_sum_IIR_out;
`ifdef BUILD_ATF
assign chan1_RAM_data = {chan1_data, 3'b000};
assign chan2_RAM_data = {chan2_data, 3'b000};
assign chan3_RAM_data = {chan3_data, 3'b000};
`else
assign chan1_RAM_data = ((~IIRbypass_b[0]) ? {chan1_data, 3'b000} : chan1_IIR_out);// + {chan1_offset, 3'b000};
assign chan2_RAM_data = ((~IIRbypass_b[1]) ? {chan2_data, 3'b000} : chan2_IIR_out);// + {chan2_offset, 3'b000};
assign chan3_RAM_data = ((~IIRbypass_b[2]) ? {chan3_data, 3'b000} : chan3_IIR_out);// + {chan3_offset, 3'b000};
`endif
//assign p1_xdif_RAM_data = (~IIRbypass_b[0]) ? p1_xdif_data : p1_xdif_IIR_out;
//assign p1_ydif_RAM_data = (~IIRbypass_b[1]) ? p1_ydif_data : p1_ydif_IIR_out;
//assign p1_sum_RAM_data = (~IIRbypass_b[2]) ? p1_sum_data : p1_sum_IIR_out;
//assign p1_xdif_RAM_data = (~IIRbypass_b[0]) ? p1_xdif_data : p1_xdif_IIR_out + p1_xdif_data_reg;
//assign p1_ydif_RAM_data = (~IIRbypass_b[1]) ? p1_ydif_data : p1_ydif_IIR_out + p1_ydif_data_reg;
//assign p1_sum_RAM_data = (~IIRbypass_b[2]) ? p1_sum_data : p1_sum_IIR_out + p1_sum_data_reg;
//assign p1_xdif_RAM_data = (~IIRbypass_b[0]) ? p1_xdif_data : p1_xdif_corr;
//assign p1_ydif_RAM_data = (~IIRbypass_b[1]) ? p1_ydif_data : p1_ydif_corr;
//assign p1_sum_RAM_data = (~IIRbypass_b[2]) ? p1_sum_data : p1_sum_corr;
//assign chan1_offset_oflow = (^chan1_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
assign chan1_offset_oflow = (^chan1_data[13:12]) ? 1'b1 : 1'b0;
assign chan2_offset_oflow = (^chan2_data[13:12]) ? 1'b1 : 1'b0;
assign chan3_offset_oflow = (^chan3_data[13:12]) ? 1'b1 : 1'b0;
//assign chan2_offset_oflow = (^chan2_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
//assign chan3_offset_oflow = (^chan3_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
// %%%%%%%%%%%%%%%%%% P1 ADC GROUP DAQ_RAM MODULES %%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Three RAM modules with self contained transmission logic. Data are written
// at 357MHz and number of samples tracked. When tx_en goes high, data are sent
// to the UART
wire daq_ram_rst;
wire uart_tx_empty;
reg daq_chan1_tx_en = 1'b0;
wire daq_chan1_tx_done;
//wire [7:0] daq_p1_xdif_tx_data;
wire [6:0] daq_chan1_tx_data;
wire daq_chan1_tx_load;
DAQ_RAM daq_ram_chan1(
.reset(daq_ram_rst),
.tx_en(daq_chan1_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan1_tx_load),
.tx_data(daq_chan1_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan1_tx_done),
.wr_clk(clk357),
.wr_en(p1_store_strb),
.wr_data({chan1_RAM_data[DSP_WIDTH-1], chan1_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
reg daq_chan2_tx_en = 1'b0;
wire daq_chan2_tx_done;
//wire [7:0] daq_p1_ydif_tx_data;
wire [6:0] daq_chan2_tx_data;
wire daq_chan2_tx_load;
DAQ_RAM daq_ram_chan2(
.reset(daq_ram_rst),
.tx_en(daq_chan2_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan2_tx_load),
.tx_data(daq_chan2_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan2_tx_done),
.wr_clk(clk357),
.wr_en(p1_store_strb),
.wr_data({chan2_RAM_data[DSP_WIDTH-1], chan2_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
reg daq_chan3_tx_en = 1'b0;
wire daq_chan3_tx_done;
//wire [7:0] daq_p1_sum_tx_data;
wire [6:0] daq_chan3_tx_data;
wire daq_chan3_tx_load;
DAQ_RAM daq_ram_chan3(
.reset(daq_ram_rst),
.tx_en(daq_chan3_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan3_tx_load),
.tx_data(daq_chan3_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan3_tx_done),
.wr_clk(clk357),
.wr_en(p1_store_strb),
.wr_data({chan3_RAM_data[DSP_WIDTH-1], chan3_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
// %%%%%%%%%%%%%%%%%% P2 ADC GROUP ADC_BLOCK MODULE %%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Bring the data from the 3 ADCs for P2 into the module via an adc_clock
// The adc block ensures the adc data is aligned with the 357MHz clock
// All control signals from 40MHz control registers
reg [6:0] cr_p2_offset_delay = 7'd0;
wire [5:0] cr_p2_scan_delay;
wire [1:0] cr_p2_align_ch_sel;
wire signed [13:0] chan4_data;
wire signed [13:0] chan5_data;
wire signed [13:0] chan6_data;
wire p2_mon_strb;
wire p2_mon_saturated;
wire [5:0] p2_mon_total_data_del;
wire [5:0] p2_mon_total_drdy_del;
wire [6:0] p2_mon_delay_mod;
wire [6:0] p2_mon_count1;
wire [6:0] p2_mon_count2;
wire [6:0] p2_mon_count3;
wire [5:0] p2_mon_adc_clk_del;
adc_block p2_adc_block(
.clk357(clk357),
.clk40(clk40),
.rst(dcm200_rst),
.align_en(adc_align_en_b), // From time/synch mod.
.align_ch_sel(cr_p2_align_ch_sel),
//.ch1_data_in_del(ch4_data_in_del),
//.ch2_data_in_del(ch5_data_in_del),
//.ch3_data_in_del(ch6_data_in_del),
.data_offset_delay(cr_p2_offset_delay),
.scan_delay(cr_p2_scan_delay),
.delay_trig(delay_trig2),
.IDDR_Q1(IDDR2_Q1),
.IDDR_Q2(IDDR2_Q2),
//.ch1_data_out(p2_xdif_data),
//.ch2_data_out(p2_ydif_data),
//.ch3_data_out(p2_sum_data),
.saturated(p2_mon_saturated),
.adc_data_delay(p2_mon_total_data_del), //Monitoring
.adc_drdy_delay(p2_mon_total_drdy_del), //Monitoring
.delay_modifier(p2_mon_delay_mod), //Monitoring
.monitor_strb(p2_mon_strb), //Monitoring
.count1(p2_mon_count1), //Monitoring
.count2(p2_mon_count2), //Monitoring
.count3(p2_mon_count3), //Monitoring
.adc_clk_delay_mon(p2_mon_adc_clk_del), //Monitoring
.delay_calc_strb(delay_calc_strb2),
.adc_drdy_delay_ce(adc2_drdy_delay_ce),
.adc_clk_delay_ce(adc2_clk_delay_ce),
.adc_data_delay_ce(adc2_data_delay_ce)
);
parameter ch4_bitflip = ~13'b0111100000000;
parameter ch5_bitflip = ~13'b0100110011010;
parameter ch6_bitflip = ~13'b1111111010110;
(* shreg_extract = "no" *) reg [4:0] bank2_sr_tap_a = 5'd2, bank2_sr_tap_b = 5'd2, bank2_sr_tap_c = 5'd2;
reg [1:0] bank2_sr_bypass = 2'b11;
dataRegConvert #(13, ch4_bitflip ^ -13'sd4096) ch4_dataRegConvert(clk357, bank2_sr_bypass, ch4_data_in_del, chan4_offset, bank2_sr_tap_c, chan4_data);
dataRegConvert #(13, ch5_bitflip ^ -13'sd4096) ch5_dataRegConvert(clk357, bank2_sr_bypass, ch5_data_in_del, chan5_offset, bank2_sr_tap_c, chan5_data);
dataRegConvert #(13, ch6_bitflip ^ -13'sd4096) ch6_dataRegConvert(clk357, bank2_sr_bypass, ch6_data_in_del, chan6_offset, bank2_sr_tap_c, chan6_data);
// Flip the signals which were incorrect polarity at LVDS inputs
//`include "p2_adcblock_flip_signals.v"
//Insert P2 Droop Correction Filters
//wire signed [DSP_WIDTH-1:0] chan4_IIR_out, chan4_RAM_data;
//wire signed [DSP_WIDTH-1:0] p2_ydif_IIR_out, p2_ydif_RAM_data;
//wire signed [DSP_WIDTH-1:0] chan5_IIR_out;
//wire signed [DSP_WIDTH:0] chan5_RAM_data;
wire signed [DSP_WIDTH-1:0] chan4_IIR_out, chan5_IIR_out, chan6_IIR_out;
//reg signed [DSP_WIDTH:0] chan4_RAM_data = 17'd0, chan5_RAM_data = 17'd0, chan6_RAM_data = 17'd0;
wire signed [DSP_WIDTH-1:0] chan4_RAM_data, chan5_RAM_data, chan6_RAM_data;
//wire signed [DSP_WIDTH-1:0] chan4_RAM_data, chan6_RAM_data;
//wire signed [DSP_WIDTH:0] chan5_RAM_data;
//wire signed [DSP_WIDTH-1:0] chan6_IIR_out, chan6_RAM_data;
wire ch4_oflowDet, ch5_oflowDet, ch6_oflowDet;
antiDroopIIR #(17) antiDroopIIR_ch4(
.clk(clk357),
.trig(TFSMstate[2]),
// .din(p2_xdif_data_fix),
.din(chan4_data[12:0]),
.tapWeight(ch4_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch4_oflowDet),
.dout(chan4_IIR_out)
);
antiDroopIIR #(17) antiDroopIIR_ch5(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p2_ydif_data_fix),
.din(chan5_data[12:0]),
.tapWeight(ch5_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch5_oflowDet),
.dout(chan5_IIR_out)
);
antiDroopIIR #(17) antiDroopIIR_ch6(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p2_sum_data_fix),
.din(chan6_data[12:0]),
.tapWeight(ch6_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch6_oflowDet),
.dout(chan6_IIR_out)
);
reg bank2_oflowDet = 1'b0;
wire chan4_offset_oflow, chan5_offset_oflow, chan6_offset_oflow;
//wire chan5_offset_oflow;
always @(posedge clk357) begin
bank2_sr_tap_a <= bank2_sr_tap;
bank2_sr_tap_b <= bank2_sr_tap_a;
bank2_sr_tap_c <= bank2_sr_tap_b;
case (bank2_sr_tap_b)
5'd0: bank2_sr_bypass <= 2'b01;
5'd1: bank2_sr_bypass <= 2'b10;
default: bank2_sr_bypass <= 2'b00;
endcase
bank2_oflowDet <= (ch4_oflowDet | ch5_oflowDet | ch6_oflowDet | chan4_offset_oflow | chan5_offset_oflow | chan6_offset_oflow);
//bank2_oflowDet <= (ch4_oflowDet | ch5_oflowDet | ch6_oflowDet);
//chan4_RAM_data <= ((~IIRbypass_b[3]) ? {chan4_data, 3'b000} : chan4_IIR_out);// + {chan4_offset, 3'b000};
//chan5_RAM_data <= ((~IIRbypass_b[4]) ? {chan5_data, 3'b000} : chan5_IIR_out);// + {chan5_offset, 3'b000};
//chan6_RAM_data <= ((~IIRbypass_b[5]) ? {chan6_data, 3'b000} : chan6_IIR_out);// + {chan6_offset, 3'b000};
//chan4_RAM_data <= chan4_RAM_data_b + {chan4_offset, 3'b000};
//chan5_RAM_data <= chan5_RAM_data_b + {chan5_offset, 3'b000};
//chan6_RAM_data <= chan6_RAM_data_b + {chan6_offset, 3'b000};
end
//assign p2_xdif_RAM_data = (~IIRbypass_b[3]) ? p2_xdif_data_fix : p2_xdif_IIR_out;
//assign p2_ydif_RAM_data = (~IIRbypass_b[4]) ? p2_ydif_data_fix : p2_ydif_IIR_out;
//assign p2_sum_RAM_data = (~IIRbypass_b[5]) ? p2_sum_data_fix : p2_sum_IIR_out;
`ifdef BUILD_ATF
assign chan4_RAM_data = {chan4_data, 3'b000};
assign chan5_RAM_data = {chan5_data, 3'b000};
assign chan6_RAM_data = {chan6_data, 3'b000};
`else
assign chan4_RAM_data = ((~IIRbypass_b[3]) ? {chan4_data, 3'b000} : chan4_IIR_out);// + {chan4_offset, 3'b000};
assign chan5_RAM_data = ((~IIRbypass_b[4]) ? {chan5_data, 3'b000} : chan5_IIR_out);// + {chan5_offset, 3'b000};
//assign p2_ydif_RAM_data = (~IIRbypass_b[4]) ? {p2_ydif_data, 3'b000} : p2_ydif_IIR_out;
assign chan6_RAM_data = ((~IIRbypass_b[5]) ? {chan6_data, 3'b000} : chan6_IIR_out);// + {chan6_offset, 3'b000};
//assign p2_xdif_RAM_data = (~IIRbypass_b[3]) ? p2_xdif_data : p2_xdif_IIR_out;
//assign p2_ydif_RAM_data = (~IIRbypass_b[4]) ? p2_ydif_data : p2_ydif_IIR_out;
//assign p2_sum_RAM_data = (~IIRbypass_b[5]) ? p2_sum_data : p2_sum_IIR_out;
`endif
//assign chan4_offset_oflow = (^chan4_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
//assign chan5_offset_oflow = (^chan5_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
//assign chan6_offset_oflow = (^chan6_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
assign chan4_offset_oflow = (^chan4_data[13:12]) ? 1'b1 : 1'b0;
assign chan5_offset_oflow = (^chan5_data[13:12]) ? 1'b1 : 1'b0;
assign chan6_offset_oflow = (^chan6_data[13:12]) ? 1'b1 : 1'b0;
// %%%%%%%%%%%%%%%%%% P2 ADC GROUP DAQ_RAM MODULES %%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Three RAM modules with self contained transmission logic. Data are written
// at 357MHz and number of samples tracked. When tx_en goes high, data are sent
// to the UART
reg daq_chan4_tx_en = 1'b0;
wire daq_chan4_tx_done;
//wire [7:0] daq_p2_xdif_tx_data;
wire [6:0] daq_chan4_tx_data;
wire daq_chan4_tx_load;
DAQ_RAM daq_ram_chan4(
.reset(daq_ram_rst),
.tx_en(daq_chan4_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan4_tx_load),
.tx_data(daq_chan4_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan4_tx_done),
.wr_clk(clk357),
.wr_en(p2_store_strb),
.wr_data({chan4_RAM_data[DSP_WIDTH-1], chan4_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
reg daq_chan5_tx_en = 1'b0;
wire daq_chan5_tx_done;
//wire [7:0] daq_p2_ydif_tx_data;
wire [6:0] daq_chan5_tx_data;
wire daq_chan5_tx_load;
DAQ_RAM daq_ram_chan5(
.reset(daq_ram_rst),
.tx_en(daq_chan5_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan5_tx_load),
.tx_data(daq_chan5_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan5_tx_done),
.wr_clk(clk357),
.wr_en(p2_store_strb),
.wr_data({chan5_RAM_data[DSP_WIDTH-1], chan5_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
reg daq_chan6_tx_en = 1'b0;
wire daq_chan6_tx_done;
//wire [7:0] daq_p2_sum_tx_data;
wire [6:0] daq_chan6_tx_data;
wire daq_chan6_tx_load;
DAQ_RAM daq_ram_chan6(
.reset(daq_ram_rst),
.tx_en(daq_chan6_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan6_tx_load),
.tx_data(daq_chan6_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan6_tx_done),
.wr_clk(clk357),
.wr_en(p2_store_strb),
.wr_data({chan6_RAM_data[DSP_WIDTH-1], chan6_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
// %%%%%%%%%%%%%%%%%% P3 ADC GROUP ADC_BLOCK MODULE %%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Bring the data from the 3 ADCs for P3 into the module via an adc_clock
// The adc block ensures the adc data is aligned with the 357MHz clock
// All control signals from 40MHz control registers
reg [6:0] cr_p3_offset_delay = 7'd0;
wire [5:0] cr_p3_scan_delay;
wire [1:0] cr_p3_align_ch_sel;
wire signed [13:0] chan7_data;
wire signed [13:0] chan8_data;
wire signed [13:0] chan9_data;
wire p3_mon_strb;
wire p3_mon_saturated;
wire [5:0] p3_mon_total_data_del;
wire [5:0] p3_mon_total_drdy_del;
wire [6:0] p3_mon_delay_mod;
wire [6:0] p3_mon_count1;
wire [6:0] p3_mon_count2;
wire [6:0] p3_mon_count3;
wire [5:0] p3_mon_adc_clk_del;
adc_block p3_adc_block(
.clk357(clk357),
.clk40(clk40),
.rst(dcm200_rst),
.align_en(adc_align_en_b), // From time/synch mod.
.align_ch_sel(cr_p3_align_ch_sel),
//.ch1_data_in_del(ch7_data_in_del),
//.ch2_data_in_del(ch8_data_in_del),
//.ch3_data_in_del(ch9_data_in_del),
.data_offset_delay(cr_p3_offset_delay),
.scan_delay(cr_p3_scan_delay),
.delay_trig(delay_trig3),
.IDDR_Q1(IDDR3_Q1),
.IDDR_Q2(IDDR3_Q2),
//.ch1_data_out(p3_xdif_data),
//.ch2_data_out(p3_ydif_data),
//.ch3_data_out(p3_sum_data),
.saturated(p3_mon_saturated),
.adc_data_delay(p3_mon_total_data_del), //Monitoring
.adc_drdy_delay(p3_mon_total_drdy_del), //Monitoring
.delay_modifier(p3_mon_delay_mod), //Monitoring
.monitor_strb(p3_mon_strb), //Monitoring
.count1(p3_mon_count1), //Monitoring
.count2(p3_mon_count2), //Monitoring
.count3(p3_mon_count3), //Monitoring
.adc_clk_delay_mon(p3_mon_adc_clk_del), //Monitoring
.delay_calc_strb(delay_calc_strb3),
.adc_drdy_delay_ce(adc3_drdy_delay_ce),
.adc_clk_delay_ce(adc3_clk_delay_ce),
.adc_data_delay_ce(adc3_data_delay_ce)
);
parameter ch7_bitflip = ~13'b0001101000010;
parameter ch8_bitflip = ~13'b1000011100001;
parameter ch9_bitflip = ~13'b0001001111010;
(* shreg_extract = "no" *) reg [4:0] bank3_sr_tap_a = 5'd2, bank3_sr_tap_b = 5'd2, bank3_sr_tap_c = 5'd2;
reg [1:0] bank3_sr_bypass = 2'b11;
dataRegConvert #(13, ch7_bitflip ^ -13'sd4096) ch7_dataRegConvert(clk357, bank3_sr_bypass, ch7_data_in_del, chan7_offset, bank3_sr_tap_c, chan7_data);
dataRegConvert #(13, ch8_bitflip ^ -13'sd4096) ch8_dataRegConvert(clk357, bank3_sr_bypass, ch8_data_in_del, chan8_offset, bank3_sr_tap_c, chan8_data);
dataRegConvert #(13, ch9_bitflip ^ -13'sd4096) ch9_dataRegConvert(clk357, bank3_sr_bypass, ch9_data_in_del, chan9_offset, bank3_sr_tap_c, chan9_data);
// Flip the signals which were incorrect polarity at LVDS inputs
//`include "p3_adcblock_flip_signals.v"
//Insert P3 Droop Correction Filters
//wire signed [DSP_WIDTH-1:0] chan7_IIR_out, chan7_RAM_data;
//wire signed [DSP_WIDTH-1:0] chan8_IIR_out, chan8_RAM_data;
//wire signed [DSP_WIDTH-1:0] chan9_IIR_out, chan9_RAM_data;
wire signed [DSP_WIDTH-1:0] chan7_IIR_out, chan8_IIR_out, chan9_IIR_out;
wire signed [DSP_WIDTH-1:0] chan7_RAM_data, chan8_RAM_data, chan9_RAM_data;
//reg signed [DSP_WIDTH:0] chan7_RAM_data = 17'd0, chan8_RAM_data = 17'd0, chan9_RAM_data = 17'd0;
wire ch7_oflowDet, ch8_oflowDet, ch9_oflowDet;
antiDroopIIR #(17) antiDroopIIR_ch7(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p3_xdif_data_fix),
.din(chan7_data[12:0]),
.tapWeight(ch7_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch7_oflowDet),
.dout(chan7_IIR_out)
);
antiDroopIIR #(17) antiDroopIIR_ch8(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p3_ydif_data_fix),
.din(chan8_data[12:0]),
.tapWeight(ch8_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch8_oflowDet),
.dout(chan8_IIR_out)
);
antiDroopIIR #(17) antiDroopIIR_ch9(
.clk(clk357),
.trig(TFSMstate[2]),
//.din(p3_sum_data_fix),
.din(chan9_data[12:0]),
.tapWeight(ch9_IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(ch9_oflowDet),
.dout(chan9_IIR_out)
);
reg bank3_oflowDet = 1'b0;
wire chan7_offset_oflow, chan8_offset_oflow, chan9_offset_oflow;
always @(posedge clk357) begin
bank3_sr_tap_a <= bank3_sr_tap;
bank3_sr_tap_b <= bank3_sr_tap_a;
bank3_sr_tap_c <= bank3_sr_tap_b;
case (bank3_sr_tap_b)
5'd0: bank3_sr_bypass <= 2'b01;
5'd1: bank3_sr_bypass <= 2'b10;
default: bank3_sr_bypass <= 2'b00;
endcase
bank3_oflowDet <= (ch7_oflowDet | ch8_oflowDet | ch9_oflowDet | chan7_offset_oflow | chan8_offset_oflow | chan9_offset_oflow);
//bank3_oflowDet <= (ch7_oflowDet | ch8_oflowDet | ch9_oflowDet);
//chan7_RAM_data <= ((~IIRbypass_b[6]) ? {chan7_data, 3'b000} : chan7_IIR_out);// + {chan7_offset, 3'b000};
//chan8_RAM_data <= ((~IIRbypass_b[7]) ? {chan8_data, 3'b000} : chan8_IIR_out);// + {chan8_offset, 3'b000};
//chan9_RAM_data <= ((~IIRbypass_b[8]) ? {chan9_data, 3'b000} : chan9_IIR_out);// + {chan9_offset, 3'b000};
//chan7_RAM_data <= chan7_RAM_data_b + {chan7_offset, 3'b000};
//chan8_RAM_data <= chan8_RAM_data_b + {chan8_offset, 3'b000};
//chan9_RAM_data <= chan9_RAM_data_b + {chan9_offset, 3'b000};
end
//assign p3_xdif_RAM_data = (~IIRbypass_b[6]) ? p3_xdif_data_fix : p3_xdif_IIR_out;
//assign p3_ydif_RAM_data = (~IIRbypass_b[7]) ? p3_ydif_data_fix : p3_ydif_IIR_out;
//assign p3_sum_RAM_data = (~IIRbypass_b[8]) ? p3_sum_data_fix : p3_sum_IIR_out;
`ifdef BUILD_ATF
assign chan7_RAM_data = {chan7_data, 3'b000};
assign chan8_RAM_data = {chan8_data, 3'b000};
assign chan9_RAM_data = {chan9_data, 3'b000};
`else
assign chan7_RAM_data = ((~IIRbypass_b[6]) ? {chan7_data, 3'b000} : chan7_IIR_out);// + {chan7_offset, 3'b000};
assign chan8_RAM_data = ((~IIRbypass_b[7]) ? {chan8_data, 3'b000} : chan8_IIR_out);// + {chan8_offset, 3'b000};
assign chan9_RAM_data = ((~IIRbypass_b[8]) ? {chan9_data, 3'b000} : chan9_IIR_out);// + {chan9_offset, 3'b000};
`endif
//assign p3_xdif_RAM_data = (~IIRbypass_b[6]) ? p3_xdif_data : p3_xdif_IIR_out;
//assign p3_ydif_RAM_data = (~IIRbypass_b[7]) ? p3_ydif_data : p3_ydif_IIR_out;
//assign p3_sum_RAM_data = (~IIRbypass_b[8]) ? p3_sum_data : p3_sum_IIR_out;
//assign chan7_offset_oflow = (^chan7_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
//assign chan8_offset_oflow = (^chan8_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
//assign chan9_offset_oflow = (^chan9_RAM_data[DSP_WIDTH:DSP_WIDTH-1]) ? 1'b1 : 1'b0;
assign chan7_offset_oflow = (^chan7_data[13:12]) ? 1'b1 : 1'b0;
assign chan8_offset_oflow = (^chan8_data[13:12]) ? 1'b1 : 1'b0;
assign chan9_offset_oflow = (^chan9_data[13:12]) ? 1'b1 : 1'b0;
// %%%%%%%%%%%%%%%%%% P3 ADC GROUP DAQ_RAM MODULES %%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Three RAM modules with self contained transmission logic. Data are written
// at 357MHz and number of samples tracked. When tx_en goes high, data are sent
// to the UART
reg daq_chan7_tx_en = 1'b0;
wire daq_chan7_tx_done;
//wire [7:0] daq_p3_xdif_tx_data;
wire [6:0] daq_chan7_tx_data;
wire daq_chan7_tx_load;
DAQ_RAM daq_ram_chan7(
.reset(daq_ram_rst),
.tx_en(daq_chan7_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan7_tx_load),
.tx_data(daq_chan7_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan7_tx_done),
.wr_clk(clk357),
.wr_en(p3_store_strb),
.wr_data({chan7_RAM_data[DSP_WIDTH-1], chan7_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
reg daq_chan8_tx_en = 1'b0;
wire daq_chan8_tx_done;
//wire [7:0] daq_p3_ydif_tx_data;
wire [6:0] daq_chan8_tx_data;
wire daq_chan8_tx_load;
DAQ_RAM daq_ram_chan8(
.reset(daq_ram_rst),
.tx_en(daq_chan8_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan8_tx_load),
.tx_data(daq_chan8_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan8_tx_done),
.wr_clk(clk357),
.wr_en(p3_store_strb),
.wr_data({chan8_RAM_data[DSP_WIDTH-1], chan8_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
reg daq_chan9_tx_en = 1'b0;
wire daq_chan9_tx_done;
//wire [7:0] daq_p3_sum_tx_data;
wire [6:0] daq_chan9_tx_data;
wire daq_chan9_tx_load;
DAQ_RAM daq_ram_chan9(
.reset(daq_ram_rst),
.tx_en(daq_chan9_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_chan9_tx_load),
.tx_data(daq_chan9_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_chan9_tx_done),
.wr_clk(clk357),
.wr_en(p3_store_strb),
.wr_data({chan9_RAM_data[DSP_WIDTH-1], chan9_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]})
);
// %%%%%%%%%%%%%%%%%%%%%%%%%%%% DAC READBACKS %%%%%%%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Use DAQ RAMS to log and transmit the values put out onto dacs 1 & 3. Using the
// dac clocks as write strobes means that each dac code will be written twice (clocks
// are 5.6ns pulses) for 6 values per dac per pulse
//Temporarily switched DAC 3 for DAC 2 due to available BNC conections
reg daq_dac1_tx_en = 1'b0;
wire daq_dac1_tx_done;
//wire [7:0] daq_dac1_tx_data;
wire [6:0] daq_dac1_tx_data;
wire daq_dac1_tx_load;
DAQ_RAM daq_dac1_sum(
.reset(daq_ram_rst),
.tx_en(daq_dac1_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_dac1_tx_load),
.tx_data(daq_dac1_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_dac1_tx_done),
.wr_clk(clk357),
.wr_en(dac1_clk),
.wr_data({dac1_out[12], dac1_out})
//.wr_en(1'b0),
//.wr_data(14'b0)
);
reg daq_dac3_tx_en = 1'b0;
wire daq_dac3_tx_done;
//wire [7:0] daq_dac3_tx_data;
wire [6:0] daq_dac3_tx_data;
wire daq_dac3_tx_load;
DAQ_RAM daq_dac3_sum(
.reset(daq_ram_rst),
.tx_en(daq_dac3_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_dac3_tx_load),
.tx_data(daq_dac3_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_dac3_tx_done),
.wr_clk(clk357),
.wr_en(dac2_clk),
.wr_data({dac2_out[12], dac2_out})
//.wr_en(1'b0),
//.wr_data(14'b0)
);
wire [14:0] gainlut_ld_addr;
wire [6:0] gainlut_ld_data;
//Trigger Interleaver
wire output_en;
Interleaver Interleaver1(clk357, trig_strb, Interleave, FF_en, output_en);
//Amplifier trigger control
//`ifndef INCLUDE_TESTBENCH
// AmpTrig2 #(26) AmpTrig1(clk357, TFSMstate[1], trig_out_en, trig_out1_delay, amp1_trig);
// AmpTrig2 #(26) AmpTrig2(clk357, TFSMstate[1], trig_out_en, trig_out2_delay, amp2_trig);
//`endif
//Instance FF module
wire loop_oflowDet;
//%%%%%%%%%%%%%%%%%%% INCLUDE UART ON DIGINA %%%%%%%%%%%%%%%%%%////////
wire digIn1_uart = (use_trigSyncExt) ? 1'b0 : diginput1;
wire uart2_byte_rdy, uart2_rx_unload;
wire [7:0] uart2_rx_data;
/*uart2_rx #(8, 9600) uart2_rx (
.reset(dcm200_rst),
.clk(clk40_ibufg),
.uld_rx_data(uart2_rx_unload),
.rx_enable(1'b1),
.rx_data(uart2_rx_data),
.rx_in(digIn1_uart),
.byte_rdy(uart2_byte_rdy)
);*/
uart3_rx uart3_rx (
//.reset(dcm200_rst),
.clk(clk357),
.uld_rx_data(uart2_rx_unload),
//.rx_enable(1'b1),
.rx_data(uart2_rx_data),
.rx_in(digIn1_uart),
.byte_rdy(uart2_byte_rdy)
);
//uart_unload #(.BYTE_WIDTH(8),.WORD_WIDTH(13)) uart2_uld (.rst(dcm200_rst), .clk(clk40_ibufg), .byte_rdy(uart2_byte_rdy), .unload_uart(uart2_rx_unload));
uart_unload #(.BYTE_WIDTH(8),.WORD_WIDTH(13)) uart2_uld (.rst(dcm200_rst), .clk(clk357), .byte_rdy(uart2_byte_rdy), .unload_uart(uart2_rx_unload));
wire [12:0] k1constDAC = (constDAC1UARTor) ? {uart2_rx_data, 5'd0} : k1_const;
wire [12:0] k2constDAC = (constDAC2UARTor) ? {uart2_rx_data, 5'd0} : k2_const;
`ifdef UART2_SELF_CHECK
uart2_tx #(8, 9600) uart2_tx (
.reset(dcm200_rst),
.clk(clk40_ibufg),
//.baud_rate(baud_rate),
.ld_tx_data(~use_trigSyncExt),
.tx_data(8'd42),
.tx_enable(1'b1),
.tx_out(DirIOB),
.tx_empty()
);
`else assign DirIOB = 1'bz;
`endif
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ////
`ifdef BUILD_CTF
PFF_DSP_16 loop (
.clk(clk357),
.store_strb(store_strb),
.feedfwd_en_b(output_en),
//.feedfwd_en_b(FF_en && output_en),
//.useDiode_b(1'b1),
.useDiode_b(useDiode),
.loop2_useDiode_b(loop2_useDiode),
.diodeGating_b(diodeGating),
.loop2_diodeGating_b(loop2_diodeGating),
.use_strobes_b(use_strbs),
.start_proc_b(start_addr),
.end_proc_b(end_addr),
.kick1_delay_b(k1_del),
.kick2_delay_b(k2_del),
.opMode_b(FFOpMode),
//.oflowMode_b(2'd2),
.oflowMode_b(oflowMode),
.kick1_constDac_val_b(k1constDAC),
.kick2_constDac_val_b(k2constDAC),
//.kick1_constDac_val_b(k1_const),
//.kick2_constDac_val_b(k2_const),
//.diodeIn(p1_xdif_RAM_data[15:3]),
.diodeIn(chan1_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]),
.loop2_diodeIn(chan4_RAM_data[DSP_WIDTH-1:DSP_WIDTH-13]),
.MixerIn(chan2_RAM_data[DSP_WIDTH-1:0]),
//.loop2_mixerIn(p2_ydif_RAM_data),
.loop2_MixerIn(chan5_RAM_data[DSP_WIDTH-1:0]),
//.mixerIn({p1_ydif_RAM_data, 3'b000}),
.kick1_gain_b(k1_gain),
.kick2_gain_b(k2_gain),
.loop2_kick1_gain_b(loop2_k1_gain),
.loop2_kick2_gain_b(loop2_k2_gain),
.DAC1clkPhase_b(DAC1phase),
.DAC2clkPhase_b(DAC2phase),
.oflowClr(1'b0),
.DAC1_IIRtapWeight(DAC1_IIRtapWeight),
.DAC2_IIRtapWeight(DAC2_IIRtapWeight),
//.IIRbypass(IIRbypass_b[10:9]),
//.amp1lim_b(amp1lim),
.oflowDetect(loop_oflowDet),
.kick1_dout(dac1_out),
.kick2_dout(dac2_out),
//.kick3_dout(dac3_out),
//.kick4_dout(dac4_out),
.DAC1_en(dac1_clk),
.DAC2_en(dac2_clk)
//.DAC3_en(dac3_clk),
//.DAC4_en(dac4_clk)
);
`endif
`ifdef BUILD_ATF
wire k1_p2_lut_wr_en;
wire k1_p3_lut_wr_en;
wire k2_p2_lut_wr_en;
wire k2_p3_lut_wr_en;
`ifdef LUTRAMreadout
wire [14:0] daq_lutram_addr;
reg [14:0] bpm_lut_addrb;
always @(posedge clk40) bpm_lut_addrb <= (LUTRAMreadout) ? daq_lutram_addr : gainlut_ld_addr;
wire [6:0] bpm1_i_lut_doutb;
wire [6:0] bpm1_q_lut_doutb;
wire [6:0] bpm2_i_lut_doutb;
wire [6:0] bpm2_q_lut_doutb;
`endif
FBModule my_FBmod(
.clk(clk357),
.sel(bpm_sel),
.ai_in(chan4_RAM_data[15:3]),
.aq_in(chan5_RAM_data[15:3]),
.bi_in(chan1_RAM_data[15:3]),
.bq_in(chan2_RAM_data[15:3]),
.ci_in(chan7_RAM_data[15:3]),
.cq_in(chan8_RAM_data[15:3]),
.q_signal(chan9_RAM_data[15:3]),
.bpm_lut_dinb(gainlut_ld_data),
.bpm1_i_lut_web(k1_p2_lut_wr_en),
.bpm1_q_lut_web(k1_p3_lut_wr_en),
.bpm2_i_lut_web(k2_p2_lut_wr_en),
.bpm2_q_lut_web(k2_p3_lut_wr_en),
`ifdef LUTRAMreadout
.bpm_lut_addrb(bpm_lut_addrb),
.bpm1_i_lut_doutb(bpm1_i_lut_doutb),
.bpm1_q_lut_doutb(bpm1_q_lut_doutb),
.bpm2_i_lut_doutb(bpm2_i_lut_doutb),
.bpm2_q_lut_doutb(bpm2_q_lut_doutb),
`else
.bpm_lut_addrb(gainlut_ld_addr),
.bpm1_i_lut_doutb(),
.bpm1_q_lut_doutb(),
.bpm2_i_lut_doutb(),
.bpm2_q_lut_doutb(),
`endif
.fb_sgnl(dac1_out),
.fb_en_b(output_en),
.b1_strobe_b(b1_strobe),
.b2_strobe_b(b2_strobe),
.delay_en(k1_delayloop_on),
.store_strb(store_strb),
.slow_clk(clk40),
.banana_corr_temp_b(k1_b2_offset),
.const_dac_b(k1constDAC),
.const_dac_en_b(k1_const_dac_en),
.dac_clk(dac1_clk),
.no_bunches_b(no_bunches),
.no_samples_b(no_samples),
.sample_spacing_b(sample_spacing),
.oflow(loop_oflowDet)
//.oflow()
);
`endif
//assign dac3_clk = dac1_clk;
//assign dac4_clk = dac2_clk;
//assign dac3_out = dac1_out;
//assign dac4_out = dac2_out;
/*
// %%%%%%%%%%%%%%%% PROCESS DATA TO PRODUCE FB SIGNAL %%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Modules contain lookup tables with Gain / Sum. The output is multiplied
// by Y Difference to form FB signal. This is passed to the DAC, and a DAC enable
// provided. P2 drives K1, P3 drives K2
//
// REPLACED WITH COUPLED FEEDBACK LOOPS. K1 AND K2 KICKS ARE LINEAR COMBINATION
// OF P2 AND P3 POSITIONS. TWO LOOKUP TABLES PER LOOP NOW
//
// Multiplexed ingoing bunch strobes so any can be used in the loops. The 'p2'
// input in the feedback loop is a high latency path, while 'p3' has minimal
// latency. The multiplexer should send p2 & p3 bunch strobes respectively in
// normal operation
wire [14:0] gainlut_ld_addr;
wire [6:0] gainlut_ld_data;
// Multiplex strobes
wire cr_k1_bunch_strb_sel;
//wire k1_low_lat_strb;
//wire k1_high_lat_strb;
//assign k1_high_lat_strb = cr_k1_bunch_strb_sel[0] ? p1_bunch_strb_a :
// cr_k1_bunch_strb_sel[1] ? p2_bunch_strb_a :
// p3_bunch_strb_a;
//assign k1_low_lat_strb = cr_k1_bunch_strb_sel[3] ? p1_bunch_strb_a :
// cr_k1_bunch_strb_sel[4] ? p2_bunch_strb_a :
// p3_bunch_strb_a;
// **** P2 to K1 feedback ****
reg [12:0] cr_k1_const_dac_out;
wire cr_k1_const_dac_en;
wire cr_k1_fb_en;
wire cr_k1_delay_loop_en;
wire k1_p2_lut_wr_en;
wire k1_p3_lut_wr_en;
wire [12:0] k1_dac_out;
wire k1_dac_en;
reg [12:0] cr_k1_b2_offset;
reg [12:0] cr_k1_b3_offset;
wire [6:0] cr_k1_fir_k1;
coupled_data_processing K1_FB (
.clk(clk357),
.rst(dcm200_rst),
.slow_clk(clk40),
.p2_sigma_in(p2_sum_data),
.p2_delta_in(p2_ydif_data),
.p3_sigma_in(cr_k1_bunch_strb_sel ? p3_sum_data : p2_sum_data),
.p3_delta_in(cr_k1_bunch_strb_sel ? p3_ydif_data : p2_ydif_data),
.store_strb(p2_store_strb),
.p2_bunch_strb(p2_bunch_strb_a),
.p3_bunch_strb(cr_k1_bunch_strb_sel ? p3_bunch_strb_a : p2_bunch_strb_a),
.feedbck_en(cr_k1_fb_en),
.delay_loop_en(cr_k1_delay_loop_en),
.const_dac_en(cr_k1_const_dac_en),
.const_dac_out(cr_k1_const_dac_out),
.b2_offset(cr_k1_b2_offset),
.b3_offset(cr_k1_b3_offset),
.fir_k1(cr_k1_fir_k1),
.p2_lut_dinb(gainlut_ld_data),
.p2_lut_addrb(gainlut_ld_addr),
.p2_lut_web(k1_p2_lut_wr_en),
.p2_lut_doutb(),
.p3_lut_dinb(gainlut_ld_data),
.p3_lut_addrb(gainlut_ld_addr),
.p3_lut_web(k1_p3_lut_wr_en),
.p3_lut_doutb(),
.amp_drive(k1_dac_out),
.dac_en(k1_dac_en)
);
//data_processing P2_to_K1_FB (
// .clk(clk357),
// .rst(dcm200_rst),
// .slow_clk(clk40),
// .sigma_in(p2_sum_data),
// .delta_in(p2_ydif_data),
// .store_strb(p2_store_strb),
// .bunch_strb(p2_bunch_strb_a),
// .feedbck_en(cr_k1_fb_en),
// .delay_loop_en(cr_k1_delay_loop_en),
// .const_dac_en(cr_k1_const_dac_en),
// .const_dac_out(cr_k1_const_dac_out),
// .b2_offset(cr_k1_b2_offset),
// .b3_offset(cr_k1_b3_offset),
// .fir_k1(cr_k1_fir_k1),
// .lut_dinb(gainlut_ld_data),
// .lut_addrb(gainlut_ld_addr),
// .lut_web(p2_lut_wr_en),
// .lut_doutb(),
// .amp_drive(k1_dac_out),
// .dac_en(k1_dac_en)
//);
// **** Assign to two DAC outputs ****
assign dac1_out = k1_dac_out;
//assign dac3_out = k1_dac_out;
assign dac1_clk = k1_dac_en;
//assign dac3_clk = k1_dac_en;
// Multiplex strobes
//wire [5:0] cr_k2_bunch_strb_sel;
//wire k2_low_lat_strb;
//wire k2_high_lat_strb;
//assign k2_high_lat_strb = cr_k2_bunch_strb_sel[0] ? p1_bunch_strb_a :
// cr_k2_bunch_strb_sel[1] ? p2_bunch_strb_a :
// p3_bunch_strb_a;
//assign k2_low_lat_strb = cr_k2_bunch_strb_sel[3] ? p1_bunch_strb_a :
// cr_k2_bunch_strb_sel[4] ? p2_bunch_strb_a :
// p3_bunch_strb_a;
// **** P3 to K2 feedback ****
reg [12:0] cr_k2_const_dac_out;
wire cr_k2_const_dac_en;
wire cr_k2_fb_en;
wire cr_k2_delay_loop_en;
wire k2_p2_lut_wr_en;
wire k2_p3_lut_wr_en;
wire [12:0] k2_dac_out;
wire k2_dac_en;
reg [12:0] cr_k2_b2_offset;
reg [12:0] cr_k2_b3_offset;
wire [6:0] cr_k2_fir_k1;
coupled_data_processing K2_FB (
.clk(clk357),
.rst(dcm200_rst),
.slow_clk(clk40),
.p2_sigma_in(p2_sum_data),
.p2_delta_in(p2_ydif_data),
.p3_sigma_in(p3_sum_data),
.p3_delta_in(p3_ydif_data),
.store_strb(p3_store_strb),
.p2_bunch_strb(p2_bunch_strb_a),
.p3_bunch_strb(p3_bunch_strb_a),
.feedbck_en(cr_k2_fb_en),
.delay_loop_en(cr_k2_delay_loop_en),
.const_dac_en(cr_k2_const_dac_en),
.const_dac_out(cr_k2_const_dac_out),
.b2_offset(cr_k2_b2_offset),
.b3_offset(cr_k2_b3_offset),
.fir_k1(cr_k2_fir_k1),
.p2_lut_dinb(gainlut_ld_data),
.p2_lut_addrb(gainlut_ld_addr),
.p2_lut_web(k2_p2_lut_wr_en),
.p2_lut_doutb(),
.p3_lut_dinb(gainlut_ld_data),
.p3_lut_addrb(gainlut_ld_addr),
.p3_lut_web(k2_p3_lut_wr_en),
.p3_lut_doutb(),
.amp_drive(k2_dac_out),
.dac_en(k2_dac_en)
);
//data_processing P3_to_K2_FB (
// .clk(clk357),
// .rst(dcm200_rst),
// .slow_clk(clk40),
// .sigma_in(p3_sum_data),
// .delta_in(p3_ydif_data),
// .store_strb(p3_store_strb),
// .bunch_strb(p3_bunch_strb_a),
// .feedbck_en(cr_k2_fb_en),
// .delay_loop_en(cr_k2_delay_loop_en),
// .const_dac_en(cr_k2_const_dac_en),
// .const_dac_out(cr_k2_const_dac_out),
// .b2_offset(cr_k2_b2_offset),
// .b3_offset(cr_k2_b3_offset),
// .fir_k1(cr_k2_fir_k1),
// .lut_dinb(gainlut_ld_data),
// .lut_addrb(gainlut_ld_addr),
// .lut_web(p3_lut_wr_en),
// .lut_doutb(),
// .amp_drive(k2_dac_out),
// .dac_en(k2_dac_en)
//);
// **** Assign to two DAC outputs ****
assign dac2_out = k2_dac_out;
//assign dac4_out = k2_dac_out;
assign dac2_clk = k2_dac_en;
//assign dac4_clk = k2_dac_en;
*/
// %%%%%%%%%%%%%%%%%%%%%%%% DAQ SEQUENCER CONTROL %%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// State machine keeps track of the current transmission state, transmits
// timestamp and framing bytes, and enables DAQ_RAM transmission as appropriate
// The sequence begins on the falling edge of store strobe
`ifdef LUTRAMreadout
localparam TRANS_STATE_WIDTH = 6;
`else
localparam TRANS_STATE_WIDTH = 5;
`endif
// Sequence state parametrisation
//parameter [TRANS_STATE_WIDTH-1:0] TRANS_WAIT = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd0};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_STAMP = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd2};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN1 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd4};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN2 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd6};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN3 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd8};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN4 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd10};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN5 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd12};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN6 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd14};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN7 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd16};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN8 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd18};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_CHAN9 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd20};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_DAC_K1 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd22};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_DAC_K2 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd24};
//parameter [TRANS_STATE_WIDTH-1:0] TRANS_357_RB = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd26};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_40_RB = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd28};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_MON_RB = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd30};
`ifdef LUTRAMreadout
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K1P2 = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd32};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K1P3 = {{(TRANS_STATE_WIDTH-6){1'b0}},6'd34};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K2P2 = {{(TRANS_STATE_WIDTH-6){1'b0}},6'd36};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K2P3 = {{(TRANS_STATE_WIDTH-6){1'b0}},6'd38};
wire daq_lutram_tx_done;
wire daq_lutram_tx_load;
reg daq_lutram_tx_en = 1'b0;
`endif
// Control register readback control wires
wire daq_readback_tx_done;
wire daq_readback_tx_load;
//wire [7:0] daq_readback_tx_data;
wire [6:0] daq_readback_tx_data;
reg daq_readback_tx_en = 1'b0;
//wire daq_readback40_tx_done;
//wire daq_readback40_tx_load;
//wire [7:0] daq_readback40_tx_data;
//reg daq_readback40_tx_en;
// Monitor readback control wires
wire daq_readback_mon_tx_done;
wire daq_readback_mon_tx_load;
//wire [7:0] daq_readback_mon_tx_data;
wire [6:0] daq_readback_mon_tx_data;
reg daq_readback_mon_tx_en = 1'b0;
wire [TRANS_STATE_WIDTH-1:0] daq_trans_state;
wire daq_ram_tx_en;
reg current_daq_ram_tx_done = 1'b0;
//wire [7:0] daq_seq_tx_data;
wire [6:0] daq_seq_tx_data;
wire daq_seq_tx_ld;
wire poll_uart;
DAQ_sequencer2 DAQ_sequencer(
.clk40(clk40_ibufg),
// .clk40(clk40),
.rst(dcm200_rst),
.strobe(p1_store_strb),
.poll_uart(poll_uart && ~run),
`ifdef LUTRAMreadout
.LUTRAMreadout(LUTRAMreadout),
`endif
.trans_done(current_daq_ram_tx_done),
.num_chans(num_chans),
.trans_state(daq_trans_state),
.trans_en(daq_ram_tx_en),
.rst_out(daq_ram_rst),
.trig_rdy(trig_rdy),
.rs232_tx_empty(uart_tx_empty),
.rs232_tx_buffer(daq_seq_tx_data),
.rs232_tx_ld(daq_seq_tx_ld)
);
// %%%%%%%%%%%%% (DE)MULTIPLEX THE DAQ_RAM TX CONTROL SIGNALS %%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
always @(posedge clk40) begin
daq_chan1_tx_en <= 0;
daq_chan2_tx_en <= 0;
daq_chan3_tx_en <= 0;
daq_chan4_tx_en <= 0;
daq_chan5_tx_en <= 0;
daq_chan6_tx_en <= 0;
daq_chan7_tx_en <= 0;
daq_chan8_tx_en <= 0;
daq_chan9_tx_en <= 0;
daq_dac1_tx_en <= 0;
daq_dac3_tx_en <= 0;
//daq_readback357_tx_en <= 0;
daq_readback_tx_en <= 0;
daq_readback_mon_tx_en <= 0;
`ifdef LUTRAMreadout
daq_lutram_tx_en <= 0;
`endif
case(daq_trans_state)
TRANS_CHAN1 : daq_chan1_tx_en <= daq_ram_tx_en;
TRANS_CHAN2 : daq_chan2_tx_en <= daq_ram_tx_en;
TRANS_CHAN3 : daq_chan3_tx_en <= daq_ram_tx_en;
TRANS_CHAN4 : daq_chan4_tx_en <= daq_ram_tx_en;
TRANS_CHAN5 : daq_chan5_tx_en <= daq_ram_tx_en;
TRANS_CHAN6 : daq_chan6_tx_en <= daq_ram_tx_en;
TRANS_CHAN7 : daq_chan7_tx_en <= daq_ram_tx_en;
TRANS_CHAN8 : daq_chan8_tx_en <= daq_ram_tx_en;
TRANS_CHAN9 : daq_chan9_tx_en <= daq_ram_tx_en;
TRANS_DAC_K1 : daq_dac1_tx_en <= daq_ram_tx_en;
TRANS_DAC_K2 : daq_dac3_tx_en <= daq_ram_tx_en;
//TRANS_357_RB : daq_readback357_tx_en <= daq_ram_tx_en;
TRANS_40_RB : daq_readback_tx_en <= daq_ram_tx_en;
TRANS_MON_RB : daq_readback_mon_tx_en <= daq_ram_tx_en;
`ifdef LUTRAMreadout
TRANS_K1P2 : daq_lutram_tx_en <= daq_ram_tx_en;
TRANS_K1P3 : daq_lutram_tx_en <= daq_ram_tx_en;
TRANS_K2P2 : daq_lutram_tx_en <= daq_ram_tx_en;
TRANS_K2P3 : daq_lutram_tx_en <= daq_ram_tx_en;
`endif
endcase
end
always @(posedge clk40) begin
case(daq_trans_state)
TRANS_CHAN1 : current_daq_ram_tx_done <= daq_chan1_tx_done;
TRANS_CHAN2 : current_daq_ram_tx_done <= daq_chan2_tx_done;
TRANS_CHAN3 : current_daq_ram_tx_done <= daq_chan3_tx_done;
TRANS_CHAN4 : current_daq_ram_tx_done <= daq_chan4_tx_done;
TRANS_CHAN5 : current_daq_ram_tx_done <= daq_chan5_tx_done;
TRANS_CHAN6 : current_daq_ram_tx_done <= daq_chan6_tx_done;
TRANS_CHAN7 : current_daq_ram_tx_done <= daq_chan7_tx_done;
TRANS_CHAN8 : current_daq_ram_tx_done <= daq_chan8_tx_done;
TRANS_CHAN9 : current_daq_ram_tx_done <= daq_chan9_tx_done;
TRANS_DAC_K1 : current_daq_ram_tx_done <= daq_dac1_tx_done;
TRANS_DAC_K2 : current_daq_ram_tx_done <= daq_dac3_tx_done;
//TRANS_357_RB : current_daq_ram_tx_done <= daq_readback357_tx_done;
TRANS_40_RB : current_daq_ram_tx_done <= daq_readback_tx_done;
TRANS_MON_RB : current_daq_ram_tx_done <= daq_readback_mon_tx_done;
`ifdef LUTRAMreadout
TRANS_K1P2 : current_daq_ram_tx_done <= daq_lutram_tx_done;
TRANS_K1P3 : current_daq_ram_tx_done <= daq_lutram_tx_done;
TRANS_K2P2 : current_daq_ram_tx_done <= daq_lutram_tx_done;
TRANS_K2P3 : current_daq_ram_tx_done <= daq_lutram_tx_done;
`endif
default : current_daq_ram_tx_done <= 0;
endcase
end
// %%%%%%%%%%%%%%%%%% MULITPLEX UART TX SIGNALS FOR DAQ %%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
reg uart_tx_load = 1'b0;
reg [7:0] uart_tx_data = 8'd0;
always @(posedge clk40) begin
case(daq_trans_state)
TRANS_CHAN1 : uart_tx_load <= daq_chan1_tx_load;
TRANS_CHAN2 : uart_tx_load <= daq_chan2_tx_load;
TRANS_CHAN3 : uart_tx_load <= daq_chan3_tx_load;
TRANS_CHAN4 : uart_tx_load <= daq_chan4_tx_load;
TRANS_CHAN5 : uart_tx_load <= daq_chan5_tx_load;
TRANS_CHAN6 : uart_tx_load <= daq_chan6_tx_load;
TRANS_CHAN7 : uart_tx_load <= daq_chan7_tx_load;
TRANS_CHAN8 : uart_tx_load <= daq_chan8_tx_load;
TRANS_CHAN9 : uart_tx_load <= daq_chan9_tx_load;
TRANS_DAC_K1 : uart_tx_load <= daq_dac1_tx_load;
TRANS_DAC_K2 : uart_tx_load <= daq_dac3_tx_load;
//TRANS_357_RB : uart_tx_load <= daq_readback357_tx_load;
TRANS_40_RB : uart_tx_load <= daq_readback_tx_load;
TRANS_MON_RB : uart_tx_load <= daq_readback_mon_tx_load;
`ifdef LUTRAMreadout
TRANS_K1P2 : uart_tx_load <= daq_lutram_tx_load;
TRANS_K1P3 : uart_tx_load <= daq_lutram_tx_load;
TRANS_K2P2 : uart_tx_load <= daq_lutram_tx_load;
TRANS_K2P3 : uart_tx_load <= daq_lutram_tx_load;
`endif
//By default pass the sequencer's load signal
default : uart_tx_load <= daq_seq_tx_ld;
endcase
end
always @(posedge clk40) begin
case(daq_trans_state)
TRANS_STAMP : uart_tx_data <= {1'b1, daq_seq_tx_data};
TRANS_CHAN1 : uart_tx_data <= {1'b1, daq_chan1_tx_data};
TRANS_CHAN2 : uart_tx_data <= {1'b1, daq_chan2_tx_data};
TRANS_CHAN3 : uart_tx_data <= {1'b1, daq_chan3_tx_data};
TRANS_CHAN4 : uart_tx_data <= {1'b1, daq_chan4_tx_data};
TRANS_CHAN5 : uart_tx_data <= {1'b1, daq_chan5_tx_data};
TRANS_CHAN6 : uart_tx_data <= {1'b1, daq_chan6_tx_data};
TRANS_CHAN7 : uart_tx_data <= {1'b1, daq_chan7_tx_data};
TRANS_CHAN8 : uart_tx_data <= {1'b1, daq_chan8_tx_data};
TRANS_CHAN9 : uart_tx_data <= {1'b1, daq_chan9_tx_data};
TRANS_DAC_K1 : uart_tx_data <= {1'b1, daq_dac1_tx_data};
TRANS_DAC_K2 : uart_tx_data <= {1'b1, daq_dac3_tx_data};
//TRANS_357_RB : uart_tx_data <= daq_readback357_tx_data;
TRANS_40_RB : uart_tx_data <= {1'b1, daq_readback_tx_data};
TRANS_MON_RB : uart_tx_data <= {1'b1, daq_readback_mon_tx_data};
`ifdef LUTRAMreadout
TRANS_K1P2 : uart_tx_data <= {1'b1, bpm1_i_lut_doutb};
TRANS_K1P3 : uart_tx_data <= {1'b1, bpm1_q_lut_doutb};
TRANS_K2P2 : uart_tx_data <= {1'b1, bpm2_i_lut_doutb};
TRANS_K2P3 : uart_tx_data <= {1'b1, bpm2_q_lut_doutb};
`endif
//By default pass the sequencer's data signal
default : uart_tx_data <= {1'b0, daq_seq_tx_data};
endcase
end
// %%%%%%%%%%%%%%%%%%% UART AND CONTROL REGISTERS %%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// **** Generate 115200 baud from the 40MHz clock ****
// **** MODIFIED FOR 460800 BAUD ****
/*reg baud_115200;
reg [7:0] baud_cnt;
always @(posedge clk40) begin
if (dcm200_rst) begin
baud_115200 <= 0;
baud_cnt <= 0;
end else begin
//
//if (baud_cnt == 8'd174) begin
//if (baud_cnt == 8'd87) begin
if (baud_cnt == 8'd43) begin
baud_115200 <= ~baud_115200;
baud_cnt <= 0;
end else begin
baud_cnt <= baud_cnt + 1;
end
end
end*/
// **** Instantiate UART ****
wire uart_rx_unload;
wire uart_rx_empty;
wire [7:0] uart_rx_data;
//wire [1:0] baud_rate;
/*uart uart1 (
.reset(dcm200_rst),
.txclk(baud_115200),
.ld_tx_data(uart_tx_load),
.tx_data(uart_tx_data),
.tx_enable(1'b1),
.tx_out(rs232_out),
.tx_empty(uart_tx_empty),
.rxclk(clk40_ibufg),
.uld_rx_data(uart_rx_unload),
.rx_data(uart_rx_data),
.rx_enable(1'b1),
.rx_in(rs232_in),
.rx_empty(uart_rx_empty)
);
*/
/*uart2_rx #(8, 9600) uart_rx (
.reset(dcm200_rst),
.clk(clk40_ibufg),
//.baud_rate(baud_rate),
.uld_rx_data(uart_rx_unload),
.rx_enable(1'b1),
.rx_data(uart_rx_data),
.rx_in(rs232_in),
//.rx_empty(uart_rx_empty)
.byte_rdy(uart_rx_empty)
);*/
uart_rx #(0) uart_rx (
.reset(dcm200_rst),
.clk(clk40_ibufg),
.baud_rate(baud_rate),
.uld_rx_data(uart_rx_unload),
.rx_enable(1'b1),
.rx_data(uart_rx_data),
.rx_in(rs232_in),
.rx_empty(uart_rx_empty)
//.byte_rdy(uart_rx_empty)
);
// **** Instantiate UART TX ****
/*uart2_tx #(8, 9600) uart_tx (
.reset(dcm200_rst),
.clk(clk40),
//.baud_rate(baud_rate),
.ld_tx_data(uart_tx_load),
.tx_data(uart_tx_data),
.tx_enable(1'b1),
.tx_out(rs232_out),
.tx_empty(uart_tx_empty)
);
*/
uart_tx #(0) uart_tx (
.reset(dcm200_rst),
.clk(clk40),
.baud_rate(baud_rate),
.ld_tx_data(uart_tx_load),
.tx_data(uart_tx_data),
.tx_enable(1'b1),
.tx_out(rs232_out),
.tx_empty(uart_tx_empty)
);
// **** Instantiate UART decoder ****
//wire [4:0] ctrl_reg_addr_357;
//wire [6:0] ctrl_reg_data_357;
//wire ctrl_reg_strb_357;
wire [6:0] ctrl_reg_addr;
wire [6:0] ctrl_reg_data;
wire ctrl_reg_strb;
wire gainlut_ld_en;
wire [4:0] gainlut_ld_select;
wire trim_lut_wr_en;
wire trim_dac_trig;
uart_decoder3 uart_decoder (
.clk(clk40_ibufg),
.rst(dcm200_rst),
.data_in(uart_rx_data),
.byte_rdy(~uart_rx_empty),
.byte_uld(uart_rx_unload),
//.current_addr_357(ctrl_reg_addr_357),
//.data_strobe_357(ctrl_reg_strb_357),
//.data_out_357(ctrl_reg_data_357),
.current_addr(ctrl_reg_addr),
.data_strobe(ctrl_reg_strb),
.data_out(ctrl_reg_data),
.ram_addr(gainlut_ld_addr),
.ram_select(gainlut_ld_select),
.ram_data(gainlut_ld_data),
.ram_data_strobe(gainlut_ld_en),
.full_reset(full_rst_trig),
.p1_delay_trig(delay_trig1),
.p2_delay_trig(delay_trig2),
.p3_delay_trig(delay_trig3),
.clk357_idelay_rst(clk357_idelay_rst),
.clk357_idelay_trig(clk357_idelay_trig),
.trim_dac_trig(trim_dac_trig),
//.poll_uart(poll_uart)
.poll_uart(poll_uart),
.pulse_ctr_rst(pulse_ctr_rst)
);
// **** Multiplex the gain lut load strobe ****
assign trim_lut_wr_en = (gainlut_ld_select == 5'd2) ? gainlut_ld_en : 1'b0;
`ifdef BUILD_ATF
assign k1_p2_lut_wr_en = (gainlut_ld_select == 5'd0) ? gainlut_ld_en : 1'b0;
assign k1_p3_lut_wr_en = (gainlut_ld_select == 5'd1) ? gainlut_ld_en : 1'b0;
assign k2_p2_lut_wr_en = (gainlut_ld_select == 5'd3) ? gainlut_ld_en : 1'b0;
assign k2_p3_lut_wr_en = (gainlut_ld_select == 5'd4) ? gainlut_ld_en : 1'b0;
`endif
`ifdef LUTRAMreadout
ctrl_reg_readback #(15,32768) lutram_readback (
.clk(clk40),
.rst(dcm200_rst),
.tx_en(daq_lutram_tx_en),
.tx_data_loaded(~uart_tx_empty),
.tx_data_ready(daq_lutram_tx_load),
.tx_complete(daq_lutram_tx_done),
.tx_cnt(daq_lutram_addr)
);
`endif
// ******* Control Registers *******************
//integer i;
wire [CR_WIDTH-1:0] ctrl_reg_addr_cnt;
always @(posedge clk40) begin
//Port A
//if (dcm200_rst) for (i=0; i < N_CTRL_REGS; i=i+1) ctrl_regs[i] <= 0;
/*else */ ctrl_regs[ctrl_reg_addr] <= (ctrl_reg_strb) ? ctrl_reg_data : ctrl_regs[ctrl_reg_addr];
ctrl_regs_mem[ctrl_reg_addr] <= (ctrl_reg_strb) ? ctrl_reg_data : ctrl_regs_mem[ctrl_reg_addr];
end
ctrl_reg_readback #(CR_WIDTH, N_CTRL_REGS) ctrl_reg_readback (
.clk(clk40),
.rst(dcm200_rst),
//.data(ctrl_regs[ctrl_reg_addr_cnt]),
.tx_en(daq_readback_tx_en),
.tx_data_loaded(~uart_tx_empty),
.tx_data_ready(daq_readback_tx_load),
//.tx_data(daq_readback_tx_data),
.tx_complete(daq_readback_tx_done),
.tx_cnt(ctrl_reg_addr_cnt)
);
//assign daq_readback_tx_data = {1'b1, ctrl_regs_mem[ctrl_reg_addr_cnt]};
assign daq_readback_tx_data = ctrl_regs_mem[ctrl_reg_addr_cnt];
//assign daq_readback_tx_data = {1'b1, ctrl_regs[ctrl_reg_addr_cnt]};
// **** Instantiate the 40MHz control registers ****
//wire [2:0] diginput1_code, diginput2_code;
/*
wire [12:0] tmp_a_k1_b2_offset, tmp_a_k1_b3_offset;
reg [12:0] tmp_b_k1_b2_offset, tmp_b_k1_b3_offset;
reg [12:0] tmp_c_k1_b2_offset, tmp_c_k1_b3_offset;
wire [12:0] tmp_a_k2_b2_offset, tmp_a_k2_b3_offset;
reg [12:0] tmp_b_k2_b2_offset, tmp_b_k2_b3_offset;
reg [12:0] tmp_c_k2_b2_offset, tmp_c_k2_b3_offset;
*/
wire [6:0] tmp_a_p1_offset, tmp_a_p2_offset, tmp_a_p3_offset;
reg [6:0] tmp_b_p1_offset = 7'd0, tmp_b_p2_offset = 7'd0, tmp_b_p3_offset = 7'd0;
/*font5_ctrl_reg_40 font5_ctrl_reg_40_1 (
.clk(clk40),
.rst(dcm200_rst),
.addr(ctrl_reg_addr_40),
.data(ctrl_reg_data_40),
.data_strb(ctrl_reg_strb_40),
.tx_en(daq_readback40_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_readback40_tx_load),
.tx_data(daq_readback40_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_readback40_tx_done),
.p1_align_ch_sel(cr_p1_align_ch_sel),
.p2_align_ch_sel(cr_p2_align_ch_sel),
.p3_align_ch_sel(cr_p3_align_ch_sel),
.p1_offset_delay(tmp_a_p1_offset),
.p2_offset_delay(tmp_a_p2_offset),
.p3_offset_delay(tmp_a_p3_offset),
.p1_scan_delay(cr_p1_scan_delay),
.p2_scan_delay(cr_p2_scan_delay),
.p3_scan_delay(cr_p3_scan_delay),
.master357_delay(clk357_idelay_value),
.k1_b2_offset(),
.k1_b3_offset(),
//.k1_b2_offset(tmp_a_k1_b2_offset),
//.k1_b3_offset(tmp_a_k1_b3_offset),
.ring_clk_thresh_code(diginput1_code),
.trig_thresh_code(diginput2_code),
//.k1_fir_k1(cr_k1_fir_k1),
.k1_fir_k1(),
.k2_b2_offset(),
.k2_b3_offset(),
//.k2_b2_offset(tmp_a_k2_b2_offset),
//.k2_b3_offset(tmp_a_k2_b3_offset),
.k2_fir_k1(),
//.k2_fir_k1(cr_k2_fir_k1),
//.k1_bunch_strb_sel(cr_k1_bunch_strb_sel)
.k1_bunch_strb_sel()
//.slow_clk_gate_en(slow_clk_gate_en)
// .k2_bunch_strb_sel(cr_k2_bunch_strb_sel)
);*/
//Temporary 40 MHz compatability assigns - MUST BE CHANGED!!
assign cr_p1_align_ch_sel = p1_align_ch_sel;
assign cr_p2_align_ch_sel = p2_align_ch_sel;
assign cr_p3_align_ch_sel = p3_align_ch_sel;
assign tmp_a_p1_offset = p1_offset_delay;
assign tmp_a_p2_offset = p2_offset_delay;
assign tmp_a_p3_offset = p3_offset_delay;
assign cr_p1_scan_delay = p1_scan_delay;
assign cr_p2_scan_delay = p2_scan_delay;
assign cr_p3_scan_delay = p3_scan_delay;
assign clk357_idelay_value = master357_delay;
//assign diginput1_code = ring_clk_thresh_code;
//assign diginput2_code = trig_thresh_code;
// Register for timing
always @(posedge clk357) begin
tmp_b_p1_offset <= tmp_a_p1_offset;
// synthesis attribute shreg_extract of tmp_b_p1_offset is "no";
tmp_b_p2_offset <= tmp_a_p2_offset;
// synthesis attribute shreg_extract of tmp_b_p2_offset is "no";
tmp_b_p3_offset <= tmp_a_p3_offset;
// synthesis attribute shreg_extract of tmp_b_p3_offset is "no";
cr_p1_offset_delay <= tmp_b_p1_offset;
// synthesis attribute shreg_extract of cr_p1_offset_delay is "no";
cr_p2_offset_delay <= tmp_b_p2_offset;
// synthesis attribute shreg_extract of cr_p2_offset_delay is "no";
cr_p3_offset_delay <= tmp_b_p3_offset;
// synthesis attribute shreg_extract of cr_p3_offset_delay is "no";
/*
cr_k1_b2_offset <= tmp_c_k1_b2_offset;
// synthesis attribute shreg_extract of cr_k1_b2_offset is "no";
cr_k1_b3_offset <= tmp_c_k1_b3_offset;
// synthesis attribute shreg_extract of cr_k1_b3_offset is "no";
tmp_c_k1_b2_offset <= tmp_b_k1_b2_offset;
// synthesis attribute shreg_extract of tmp_c_k1_b2_offset is "no";
tmp_c_k1_b3_offset <= tmp_b_k1_b3_offset;
// synthesis attribute shreg_extract of tmp_c_k1_b3_offset is "no";
tmp_b_k1_b2_offset <= tmp_a_k1_b2_offset;
// synthesis attribute shreg_extract of tmp_b_k1_b2_offset is "no";
tmp_b_k1_b3_offset <= tmp_a_k1_b3_offset;
// synthesis attribute shreg_extract of tmp_b_k1_b3_offset is "no";
cr_k2_b2_offset <= tmp_c_k2_b2_offset;
// synthesis attribute shreg_extract of cr_k2_b2_offset is "no";
cr_k2_b3_offset <= tmp_c_k2_b3_offset;
// synthesis attribute shreg_extract of cr_k2_b3_offset is "no";
tmp_c_k2_b2_offset <= tmp_b_k2_b2_offset;
// synthesis attribute shreg_extract of tmp_c_k2_b2_offset is "no";
tmp_c_k2_b3_offset <= tmp_b_k2_b3_offset;
// synthesis attribute shreg_extract of tmp_c_k2_b3_offset is "no";
tmp_b_k2_b2_offset <= tmp_a_k2_b2_offset;
// synthesis attribute shreg_extract of tmp_b_k2_b2_offset is "no";
tmp_b_k2_b3_offset <= tmp_a_k2_b3_offset;
// synthesis attribute shreg_extract of tmp_b_k2_b3_offset is "no";
*/
end
// **** Instantiate the 357MHz control registers ****
//wire [12:0] temp_k1_const_dac_out;
//wire [12:0] temp_k2_const_dac_out;
/*font5_ctrl_reg_357 font4_ctrl_reg_357_1 (
.clk(clk357),
.rst(dcm200_rst),
.addr(ctrl_reg_addr_357),
.data(ctrl_reg_data_357),
.data_strb(ctrl_reg_strb_357),
.tx_en(daq_readback357_tx_en),
.tx_clk(clk40),
.tx_data_ready(daq_readback357_tx_load),
.tx_data(daq_readback357_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_readback357_tx_done),
.trig_delay(),
.trig_out_delay(),
.trig_out_delay2(),
.trig_out_en(),
// .trig_out_delay(cr_trig_out_delay),
// .trig_out_delay2(cr_trig_out_delay2),
// .trig_out_en(cr_trig_out_en),
.p1_bunch1pos(),
.p1_bunch2pos(),
.p1_bunch3pos(),
.p2_bunch1pos(),
.p2_bunch2pos(),
.p2_bunch3pos(),
.p3_bunch1pos(),
.p3_bunch2pos(),
.p3_bunch3pos(),
// .p1_bunch1pos(cr_p1_b1_pos),
// .p1_bunch2pos(cr_p1_b2_pos),
// .p1_bunch3pos(cr_p1_b3_pos),
// .p2_bunch1pos(cr_p2_b1_pos),
// .p2_bunch2pos(cr_p2_b2_pos),
// .p2_bunch3pos(cr_p2_b3_pos),
// .p3_bunch1pos(cr_p3_b1_pos),
// .p3_bunch2pos(cr_p3_b2_pos),
// .p3_bunch3pos(cr_p3_b3_pos),
.k1_fb_on(),
.k2_fb_on(),
//.k1_fb_on(cr_k1_fb_en),
//.k2_fb_on(cr_k2_fb_en),
.k1_delayloop_on(),
.k2_delayloop_on(),
//.k1_delayloop_on(cr_k1_delay_loop_en),
//.k2_delayloop_on(cr_k2_delay_loop_en),
.k1_const_dac_en(),
.k2_const_dac_en(),
//.k1_const_dac_en(cr_k1_const_dac_en),
//.k2_const_dac_en(cr_k2_const_dac_en),
.k1_const_dac_out(),
.k2_const_dac_out(),
//.k1_const_dac_out(temp_k1_const_dac_out),
//.k2_const_dac_out(temp_k2_const_dac_out),
.clk2_16_edge_sel(cr_clk2_16_edge_sel),
.sample_hold_off(cr_sample_hold_off),
.big_trig_delay(cr_trig_delay)
//.sync_en(sync_en)
);*/
// **** Register the const_dac outputs for timing and ****
/*
always @(posedge clk357) begin
cr_k1_const_dac_out <= temp_k1_const_dac_out;
cr_k2_const_dac_out <= temp_k2_const_dac_out;
end
*/
// %%%%%%%%%%%%%%%%%%%%%%%% BOARD SYNCHRONISER %%%%%%%%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire [1:0] syncStatus;
wire syncOut;
boardSynchroniser3 synchro1(clk40, synch_en, trig_rdy, sync_cnt_n, sync_cnt_m, auxInA, syncOut, syncStatus[0], syncStatus[1]);
//boardSynchroniser synchro1(clk40, synch_en, trig_rdy, sync_cnt_n, sync_cnt_m, sync_opMode, syncStatus, syncInOut);
//boardSynchroniser synchro1(clk40, synch_en, trig_rdy, sync_cnt_n, sync_cnt_m, sync_opMode, DirectIO1);
//assign DirectIO1 = syncInOut;
assign auxOutC = syncOut;
// %%%%%%%%%%%%%%%%%%%%%% READBACK MONITORS FOR DAQ %%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Load important monitor signals into monitor_readback. They are transmitted
// as part of the DAQ
// 357MHz signals registered to aid timing
wire [6:0] status;
reg dcm200_locked_a = 1'b0, idelayctrl_rdy_a = 1'b0; //clk_align_a, clk_align_b;
`ifdef CLK357_PLL
reg pll_clk357_locked_a = 1'b0;
`endif
`ifdef FASTCLK_INT
reg dcm360_locked_a = 1'b0;
`endif
//reg pll_clk357_locked_a, idelayctrl_rdy_a; //clk_align_a, clk_align_b;
reg rst_state_a = 1'b1, oflowDet = 1'b0, loop_oflowDet_b = 1'b0;
wire oflow_state;
(* shreg_extract = "no" *) reg oflow_state_a = 1'b0;
always @(posedge clk357) begin
loop_oflowDet_b <= loop_oflowDet;
oflowDet <= (loop_oflowDet_b | bank1_oflowDet | bank2_oflowDet | bank3_oflowDet);
`ifdef CLK357_PLL
pll_clk357_locked_a <= pll_clk357_locked;
`endif
dcm200_locked_a <= dcm200_locked;
`ifdef FASTCLK_INT
dcm360_locked_a <= dcm360_locked;
`endif
idelayctrl_rdy_a <= idelayctrl_rdy;
//clk_align_a <= clk_align;
//clk_align_b <= clk_align_a;
end
`ifdef CLK357_PLL
assign status = {pll_clk357_locked_a, dcm200_locked_a, idelayctrl_rdy_a, led1_out, p3_mon_saturated, p2_mon_saturated, p1_mon_saturated};
`else
assign status = {1'b0, dcm200_locked_a, idelayctrl_rdy_a, led1_out, p3_mon_saturated, p2_mon_saturated, p1_mon_saturated};
`endif
//overflow_detector oflowDet1(clk357, poll_uart || dcm200_rst, oflowDet && TFSMstate[2], oflow_state);
//overflow_detector oflowDet1(clk357, poll_uart || dcm200_rst, oflowDet, TFSMstate[2], oflow_state);
overflow_detector oflowDet1(clk357, poll_uart || dcm200_rst, oflowDet, store_strb, oflow_state);
`ifdef CLK357_PLL
(* equivalent_register_removal = "no", shreg_extract = "no" *) reg clkPLL_sel_b, clkPLL_sel_c;
`endif
always @(posedge clk40) begin
oflow_state_a <= oflow_state;
rst_state_a <= rst_state;
`ifdef CLK357_PLL
clkPLL_sel_c <= ~clkPLL_sel;
clkPLL_sel_b <= clkPLL_sel_c;
clkPLL_sel_a <= clkPLL_sel_b;
`endif
end
monitor_readback monitor_readback1 (
.clk(clk40),
.rst(dcm200_rst),
.tx_en(daq_readback_mon_tx_en),
//.tx_clk(clk40),
.tx_data_ready(daq_readback_mon_tx_load),
.tx_data(daq_readback_mon_tx_data),
.tx_data_loaded(~uart_tx_empty),
.tx_complete(daq_readback_mon_tx_done),
.rb0(status),
.rb1(p1_mon_count1),
.rb2(p1_mon_count2),
.rb3(p1_mon_count3),
`ifdef FASTCLK_INT
.rb4({dcm360_locked_a, p1_mon_total_data_del}),
`else
.rb4({1'b0, p1_mon_total_data_del}),
`endif
//.rb4({clk_align_b, p1_mon_total_data_del}),
.rb5(p2_mon_count1),
.rb6(p2_mon_count2),
.rb7(p2_mon_count3),
//.rb8({1'b0, p2_mon_total_data_del}),
.rb8({rst_state_a, p2_mon_total_data_del}),
.rb9(p3_mon_count1),
.rb10(p3_mon_count2),
.rb11(p3_mon_count3),
.rb12({oflow_state_a, p3_mon_total_data_del}),
//.rb13({6'b000000,clk_align_b})
.rb13({pulse_ctr,output_en}),
.rb14({4'b0000, pile_up, syncStatus})
);
// %%%%%%%%%%%%%%%%%%%%%%%%% TRIM DAC CONTROLS %%%%%%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Instantiate the control logic for the trim dacs
trim_dac_ctrl trims (
.clk40(clk40),
.rst(dcm200_rst),
.lut_in(gainlut_ld_data),
.lut_addr(gainlut_ld_addr[4:0]),
.lut_we(trim_lut_wr_en),
.load_dacs(trim_dac_trig),
.serial_out(trim_sdi),
.clk_out(trim_sck),
.enable_out(trim_cs_ld)
);
// %%%%%%%%%%%%%%%%%%%% DIGITAL INPUT THRESHOLDS %%%%%%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// The digital inputs have variable thresholds. Each has two control lines
// diginputnA/B. The signals are tristate giving 9 values using 0,1,z
//
// The 4 bit code from the control regs specifies which combination
//
//reg diginput1A, diginput1B;
always @(posedge clk40) begin
case(diginput1_code[2:0])
3'd0 : begin
diginput1A <= 0;
diginput1B <= 0;
end
3'd1 : begin
diginput1A <= 1;
diginput1B <= 0;
end
3'd2 : begin
diginput1A <= 0;
diginput1B <= 1;
end
3'd3 : begin
diginput1A <= 1;
diginput1B <= 1;
end
3'd4 : begin
diginput1A <= 1'bz;
diginput1B <= 0;
end
3'd5 : begin
diginput1A <= 0;
diginput1B <= 1'bz;
end
3'd6 : begin
diginput1A <= 1'bz;
diginput1B <= 1;
end
3'd7 : begin
diginput1A <= 1;
diginput1B <= 1'bz;
end
default : begin
diginput1A <= 1'bz;
diginput1B <= 1'bz;
end
endcase
end
always @(posedge clk40) begin
case(diginput2_code[2:0])
3'd0 : begin
diginput2A <= 0;
diginput2B <= 0;
end
3'd1 : begin
diginput2A <= 1;
diginput2B <= 0;
end
3'd2 : begin
diginput2A <= 0;
diginput2B <= 1;
end
3'd3 : begin
diginput2A <= 1;
diginput2B <= 1;
end
3'd4 : begin
diginput2A <= 1'bz;
diginput2B <= 0;
end
3'd5 : begin
diginput2A <= 0;
diginput2B <= 1'bz;
end
3'd6 : begin
diginput2A <= 1'bz;
diginput2B <= 1;
end
3'd7 : begin
diginput2A <= 1;
diginput2B <= 1'bz;
end
default : begin
diginput2A <= 1'bz;
diginput2B <= 1'bz;
end
endcase
end
/*
wire [35:0] control0, control1;
wire [255:0] trig0;
// Instantiate the module
chipscope_icon icon1 (
.CONTROL0(control0),
.CONTROL1(control1)
);
// Instantiate the module
chipscope_vio vio1 (
.CONTROL(control0),
.CLK(),
.ASYNC_IN(),
.ASYNC_OUT(),
.SYNC_IN(),
.SYNC_OUT()
);
// Instantiate the module
chipscope_ila ila1 (
.CONTROL(control1),
.CLK(clk357),
.TRIG0(trig0)
);
assign trig0={242'd0, p1_xdif_data, store_strb};
*/
// %%%%%%%%%%%%%%%%%%% CHIPSCOPE CORES FOR DEBUGGING %%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
/*
// **** ICON controller ****
wire [35:0] control0;
wire [35:0] control1;
wire [35:0] control2;
font5_icon i_font5_icon
(
.control0(control0),
.control1(control1),
.control2(control2)
);
// **** VIO I/O ****
wire [127:0] async_in;
wire [127:0] async_out;
font5_vio i_font5_vio
(
.control(control0),
.async_in(async_in),
.async_out(async_out)
);
// **** ILA for P1 data ****
wire [47:0] ila_p1_data_trig;
font5_p1_ila i_font5_p1_ila
(
.control(control1),
.clk(clk357),
.trig0(ila_p1_data_trig)
);
assign ila_p1_data_trig = {18'b0, p1_xdif_data, p1_store_strb};
// **** ILA for p1 ADC block monitoring ****
wire [41:0] ila_p1_monitor_trigger;
font5_p1_mon_ila i_font5_p1_mon_ila
(
.control(control2),
.clk(clk40),
.trig0(ila_p1_monitor_trigger)
);
assign ila_p1_monitor_trigger ={p1_mon_total_drdy_del, p1_mon_total_data_del, p1_mon_delay_mod, p1_mon_count1, p1_mon_count2, p1_mon_count3, p1_mon_saturated, p1_mon_strb};
// Assign VIO signals for debugging (128 bits for now)
//assign p1_xdif_polarity = async_out[12:0];
//assign p1_ydif_polarity = async_out[25:13];
//assign p1_sum_polarity = async_out[38:26];
//assign cr_p1_offset_delay = async_out[5:0];
//assign trim_cnt_stop = async_out[8:0];
//assign trim_dac_addr = async_out[12:9];
//assign trim_dac_cmd = async_out[16:13];
//assign trim_ld_polarity = async_out[17];
// Assign VIO signals to monitor (~128 bits total)
assign async_in[5:0] = clk357_idelay_mon;
assign async_in[6] = pll_clk357_locked;
assign async_in[7] = dcm200_locked;
assign async_in[8] = idelayctrl_rdy;
assign async_in[15:9] = cr_trig_delay;
assign async_in[22:16] = cr_trig_out_delay;
assign async_in[23] = cr_trig_out_en;
assign async_in[24] = cr_clk2_16_edge_sel;
assign async_in[30:25] = cr_p1_offset_delay;
assign async_in[36:31] = cr_p1_scan_delay;
assign async_in[42:37] = p1_mon_adc_clk_del;
//output [7:0] p1_bunch1pos;
//output [7:0] p1_bunch2pos;
//output [7:0] p1_bunch3pos;
//output [7:0] p2_bunch1pos;
//output [7:0] p2_bunch2pos;
//output [7:0] p2_bunch3pos;
//output [7:0] p3_bunch1pos;
//output [7:0] p3_bunch2pos;
//output [7:0] p3_bunch3pos;
//output k1_fb_on;
//output k2_fb_on;
//output k1_delayloop_on;
//output k2_delayloop_on;
//output k1_const_dac_en;
//output k2_const_dac_en;
//output [13:0] k1_const_dac_out;
//output [13:0] k2_const_dac_out;
*/
endmodule
/*
module font5_icon
(
control0,
control1,
control2
);
output [35:0] control0;
output [35:0] control1;
output [35:0] control2;
endmodule
module font5_vio
(
control,
async_in,
async_out
);
input [35:0] control;
input [127:0] async_in;
output [127:0] async_out;
endmodule
module font5_p1_ila
(
control,
clk,
trig0
);
input [35:0] control;
input clk;
input [47:0] trig0;
endmodule
module font5_p1_mon_ila
(
control,
clk,
trig0
);
input [35:0] control;
input clk;
input [41:0] trig0;
endmodule
*/
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
//
// Main module
/*
4000_0000 - 400F_FFFF Extern SRAM (1 MiB)
BFC0_0000 - BFC0_3FFF Boot ROM (16 KiB) (Preloaded I$ cache)
FF00_0000 - FF00_1FFF Peripherals
Read Write
0 rs232out busy rs232out data
1 rs232in data
2 rs232in count
3 TSC
*/
`timescale 1ns/10ps
`include "../../soclib/pipeconnect.h"
module main(
input wire clk,
//
// serial interface
//
output wire ser_txd,
input wire ser_rxd,
input wire ser_ncts,
output wire ser_nrts,
//
// watchdog
//
output wire wd,
//
// two ram banks
//
output wire [17:0] rama_a,
inout wire [15:0] rama_d,
output wire rama_ncs,
output wire rama_noe,
output wire rama_nlb,
output wire rama_nub,
output wire rama_nwe,
output wire [17:0] ramb_a,
inout wire [15:0] ramb_d,
output wire ramb_ncs,
output wire ramb_noe,
output wire ramb_nlb,
output wire ramb_nub,
output wire ramb_nwe);
wire clock;
pll pll(.inclk0(clk), // 20 MHz on Cycore
.c0(clock)); // xx MHz output
assign wd = rst_counter[22];
reg [26:0] rst_counter = 0;
always @(posedge clock)
// if (~USER_PB[0])
// rst_counter <= 'd48_000_000;
// else if (~rst_counter[26])
if (~rst_counter[26])
rst_counter <= rst_counter - 1;
wire rst = ~rst_counter[26];
assign ramb_a = rama_a;
assign ramb_ncs = rama_ncs;
assign ramb_noe = rama_noe;
assign ramb_nwe = rama_nwe;
parameter FREQ = 80_000_000; // match clock frequency
parameter BPS = 115_200; // Serial speed
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire mem_waitrequest;
wire [1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
yari yari_inst(
.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
sram_ctrl sram_ctrl
(.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(rama_a)
,.sram_d({rama_d,ramb_d})
,.sram_cs_n(rama_ncs)
,.sram_be_n({rama_nub,rama_nlb,ramb_nub,ramb_nlb})
,.sram_oe_n(rama_noe)
,.sram_we_n(rama_nwe)
);
defparam sram_ctrl.need_wait = 1;
rs232out rs232out_inst
(.clock(clock),
.serial_out(ser_txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clock),
.serial_in(ser_rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clock),
.rst(rst),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_2_V
`define SKY130_FD_SC_HD__SDFXBP_2_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfxbp_2 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_2_V
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: tx_crc_combine
*
*/
`default_nettype none
module tx_crc_combine #(
parameter LOG_FPW = 2,
parameter FPW = 4,
parameter DWIDTH = 512
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----Input data
//----------------------------------
input wire [FPW-1:0] d_in_hdr,
input wire [FPW-1:0] d_in_tail,
input wire [DWIDTH-1:0] d_in_data,
//----------------------------------
//----Outputs
//----------------------------------
output wire [DWIDTH-1:0] d_out_data
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
`include "hmc_field_functions.h"
//------------------------------------------------------------------------------------General Assignments
integer i_f; //counts to FPW
integer i_f2; //counts to FPW inside another i_f loop
integer i_c; //depth of the crc data pipeline
genvar f, f2;
//------------------------------------------------------------------------------------Split input data into FLITs
wire [128-1:0] d_in_flit [FPW-1:0];
generate
for(f = 0; f < (FPW); f = f + 1) begin
assign d_in_flit[f] = d_in_data[(f*128)+128-1:f*128];
end
endgenerate
reg [3:0] d_in_flit_lng_dly [FPW-1:0];
reg [DWIDTH-1:0] d_in_data_dly;
reg [FPW-1:0] d_in_tail_dly;
reg [FPW-1:0] d_in_hdr_dly;
reg [LOG_FPW-1:0] d_in_flit_target_crc [FPW-1:0];
//------------------------------------------------------------------------------------CRC Target Assignment
reg swap_crc;
//Retrieve the target crc from the header and assign to corresponding tail
reg [LOG_FPW-1:0] target_crc_per_tail [FPW-1:0];
reg [LOG_FPW-1:0] target_crc_per_tail1 [FPW-1:0];
reg [LOG_FPW-1:0] target_crc_per_tail_comb [FPW-1:0];
reg [LOG_FPW-1:0] target_crc_comb;
reg [LOG_FPW-1:0] target_crc_temp;
//------------------------------------------------------------------------------------CRC Modules Input stage
wire [31:0] crc_init_out [FPW-1:0];
reg [31:0] crc_accu_in [FPW-1:0];
reg [FPW-1:0] crc_accu_in_valid [FPW-1:0];
reg [FPW-1:0] crc_accu_in_tail [FPW-1:0];
wire [31:0] crc_per_flit [FPW-1:0];
//------------------------------------------------------------------------------------Inter CRC stage
reg [3:0] payload_remain [FPW-1:0];
wire [(FPW*32)-1:0] crc_accu_in_combined [FPW-1:0];
generate
for(f=0;f<FPW;f=f+1) begin
for(f2=0;f2<FPW;f2=f2+1) begin
assign crc_accu_in_combined[f][(f2*32)+31:(f2*32)] = crc_accu_in_valid[f][f2] ? crc_accu_in[f2] : 32'h0;
end
end
endgenerate
//------------------------------------------------------------------------------------Data Pipeline signals
reg [DWIDTH-1:0] crc_data_pipe_in_data [1:0];
reg [FPW-1:0] crc_data_pipe_in_tail [1:0];
wire [128-1:0] crc_data_pipe_out_data_flit [FPW-1:0];
generate
for(f = 0; f < (FPW); f = f + 1) begin : assign_data_pipe_output
assign crc_data_pipe_out_data_flit[f] = crc_data_pipe_in_data[1][(f*128)+127:f*128];
end
endgenerate
reg [128-1:0] data_rdy_flit [FPW-1:0];
generate
for(f = 0; f < (FPW); f = f + 1) begin : reorder_flits_to_word
assign d_out_data[(f*128)+128-1:(f*128)] = data_rdy_flit[f];
end
endgenerate
//==================================================================================
//---------------------------------Retrieve the lengths to invalide FLITs
//==================================================================================
always @(*) begin
//Retrieve the length from the header and assign it to the tail. This information will be used in the
//invalidation stage to the correct number of FLITs
target_crc_comb = target_crc_temp;
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if(d_in_hdr_dly[i_f]) begin
target_crc_comb = d_in_flit_target_crc[i_f];
end
if(d_in_tail_dly[i_f]) begin
target_crc_per_tail_comb[i_f] = target_crc_comb;
end else begin
target_crc_per_tail_comb[i_f] = {4{1'b0}};
end
end
end
//Register combinational values
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
target_crc_per_tail[i_f] <= 0;
end
target_crc_temp <= {4{1'b0}};
end else begin
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
target_crc_per_tail[i_f] <= target_crc_per_tail_comb[i_f];
end
target_crc_temp <= target_crc_comb;
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//====================================================================
//---------------------------------Assign input data stream to target CRCs
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_target_crc[i_f] <= {LOG_FPW{1'b0}};
end
swap_crc <= 1'b0;
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_target_crc[i_f] <= {LOG_FPW{1'b0}};
end
//Reset if seen a tail
if(|d_in_tail) begin
swap_crc <= 1'b0;
end
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(d_in_hdr[i_f])begin
if(i_f+lng(d_in_flit[i_f])>FPW) begin
//If the current packet spreads over multiple cycles
if(swap_crc) begin
//If the last packet was swapped and the current packet also spreads over the more than 1 cycle use crc 0 now
d_in_flit_target_crc[i_f] <= 3'h0;
end else begin
d_in_flit_target_crc[i_f] <= FPW-1'b1;
swap_crc <= 1'b1;
end
end else begin
d_in_flit_target_crc[i_f] <= i_f;
//If the highest order CRC contains a data packet that ends in this cycle, dont use this crc
//It's ok always to decrement by 1 since we know the lowest order CRC would not be used (at least FLIT0 goes to highest order CRC)
if(swap_crc && !(d_in_hdr > d_in_tail)) begin
d_in_flit_target_crc[i_f] <= i_f-1;
end
end
end
end
end
end
//Register input values to be used in CRC assignment logic after crc init stage
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
//------------Data Propagation
`ifdef RESET_ALL
if(!res_n) d_in_data_dly <= {DWIDTH{1'b0}};
else
`endif
d_in_data_dly <= d_in_data;
//----------------------------
`ifdef RESET_ALL
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_lng_dly[i_f] <= 4'h0;
end
d_in_tail_dly <= {FPW{1'b0}};
d_in_hdr_dly <= {FPW{1'b0}};
end else
`endif
begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
d_in_flit_lng_dly[i_f] <= lng(d_in_flit[i_f]);
end
d_in_tail_dly <= d_in_tail;
d_in_hdr_dly <= d_in_hdr;
end
end
//====================================================================
//---------------------------------Inter CRC stage, CRC assignment Logic
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
//------------Data Propagation
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
`ifdef RESET_ALL
if(!res_n) crc_accu_in[i_f] <= {32{1'b0}};
else
`endif
crc_accu_in[i_f] <= crc_init_out[i_f];
end
//----------------------------
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
crc_accu_in_valid[i_f] <= {FPW{1'b0}};
crc_accu_in_tail[i_f] <= {FPW{1'b0}};
payload_remain[i_f] <= 4'h0;
end
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
crc_accu_in_valid[i_f] <= 4'h0;
crc_accu_in_tail[i_f] <= 4'h0;
end
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
//First go through accu crcs
if(|payload_remain[i_f]) begin
if(payload_remain[i_f] > FPW) begin
crc_accu_in_valid[i_f] <= {FPW{1'b1}};
payload_remain[i_f] <= payload_remain[i_f]-FPW;
end else begin
crc_accu_in_valid[i_f] <= {FPW{1'b1}} >> (FPW-payload_remain[i_f]);
crc_accu_in_tail[i_f] <= 1'b1 << (payload_remain[i_f]-1);
payload_remain[i_f] <= 4'h0;
end
end
for(i_f2=0;i_f2<FPW;i_f2=i_f2+1)begin
if(i_f==d_in_flit_target_crc[i_f2] && d_in_hdr_dly[i_f2]) begin
//Then go through all input crcs from the init crc and find the crc's that must be assigned to the currently selected crc
if( (i_f2+d_in_flit_lng_dly[i_f2]) >FPW ) begin
payload_remain[i_f] <= (d_in_flit_lng_dly[i_f2]-FPW+i_f2);
crc_accu_in_valid[i_f] <= {FPW{1'b1}} >> i_f2 << i_f2;
end else begin
crc_accu_in_tail[i_f] <= 1'b1 << d_in_flit_lng_dly[i_f2]+i_f2-1;
crc_accu_in_valid[i_f] <= ({FPW{1'b1}} >> (FPW-i_f2-d_in_flit_lng_dly[i_f2])) >> i_f2 << i_f2;
end
end
end
end
end
end
//====================================================================
//---------------------------------Constant propagation of the data pipeline
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
//------------Data Propagation
`ifdef RESET_ALL
if (!res_n) begin
for(i_c=0;i_c<2;i_c=i_c+1)begin
crc_data_pipe_in_data[i_c] <= {DWIDTH{1'b0}};
end
end else
`endif
begin
crc_data_pipe_in_data[0] <= d_in_data_dly;
crc_data_pipe_in_data[1] <= crc_data_pipe_in_data[0];
end
//----------------------------
`ifdef RESET_ALL
if(!res_n) begin
for(i_c=0;i_c<2;i_c=i_c+1)begin
crc_data_pipe_in_tail[i_c] <= {FPW{1'b0}};
end
for(i_f=0;i_f<(FPW);i_f=i_f+ 1) begin
target_crc_per_tail1[i_f] <= {LOG_FPW{1'b0}};
end
end else
`endif
begin
//We keep the tails per FLIT so they are not part of the data pipe
for(i_f=0;i_f<(FPW);i_f=i_f+ 1) begin
target_crc_per_tail1[i_f] <= target_crc_per_tail[i_f];
end
//Set the first stage of the data pipeline
crc_data_pipe_in_tail[0] <= d_in_tail_dly;
//Data Pipeline propagation
crc_data_pipe_in_tail[1] <= crc_data_pipe_in_tail[0];
end
end
//====================================================================
//---------------------------------At the end of the data pipeline get and add CRCs
//====================================================================
//Data Pipeline output stage to final FLIT reg
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
`ifdef RESET_ALL
if(!res_n) begin
data_rdy_flit[i_f] <= {128{1'b0}};
end else
`endif
begin
data_rdy_flit[i_f] <= crc_data_pipe_out_data_flit[i_f];
if(crc_data_pipe_in_tail[1][i_f])begin //Finally add the crc
data_rdy_flit[i_f][128-1:128-32] <= crc_per_flit[target_crc_per_tail1[i_f]];
end
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//Init CRC: Calculate the remainders of each input FLIT individually
generate
for(f=0;f<FPW;f=f+1) begin : crc_init_gen
crc_128_init crc_init_I
(
.clk(clk),
`ifdef RESET_ALL
.res_n(res_n),
`endif
.inData(d_in_flit[f]),
.crc(crc_init_out[f])
);
end
endgenerate
//Calculate the actual CRC over all valid remainders
generate
for(f=0;f<FPW;f=f+1) begin : crc_accu_gen
crc_accu #(
.FPW(FPW)
)
crc_accu_I
(
.clk(clk),
.res_n(res_n),
.tail(crc_accu_in_tail[f]),
.d_in(crc_accu_in_combined[f]),
.crc_out(crc_per_flit[f])
);
end
endgenerate
endmodule
`default_nettype wire |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__PROBE_P_PP_BLACKBOX_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_PP_BLACKBOX_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_top,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "triangle_intersect_auto_us_2,axi_dwidth_converter_v2_1_top,{}" *)
(* CORE_GENERATION_INFO = "triangle_intersect_auto_us_2,axi_dwidth_converter_v2_1_top,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module triangle_intersect_auto_us_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*!
* <b>Module:</b>ahci_ctrl_stat
* @file ahci_ctrl_stat.v
* @date 2016-01-12
* @author Andrey Filippov
*
* @brief Copy of significant register fields, updating them in
* axi_ahci_regs registers (software accessible)
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_ctrl_stat.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_ctrl_stat.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
module ahci_ctrl_stat #(
// parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10 // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
)(
input mrst, // @posedge mclk, generated by phy
input mclk, // for command/status
input was_hba_rst, // last reset was hba reset (not counting system reset)
input was_port_rst, // last reset was port reset(not counting system reset)
// notification from axi_ahci_regs that software has written data to register
input [ADDRESS_BITS-1:0] soft_write_addr, // register address written by software
input [31:0] soft_write_data, // register data written (after applying wstb and type (RO, RW, RWC, RW1)
input soft_write_en, // write enable for data write
// input soft_arst, // reset SATA PHY not relying on SATA clock
// R/W access to AXI/AHCI registers, shared with ahci_fis_receive and ahci_fis_transmit modules
output reg [ADDRESS_BITS-1:0] regs_addr,
output reg regs_we,
// output [3:0] regs_wstb, Needed?
// output [1:0] regs_re, // [0] - re, [1] - regen
output reg [31:0] regs_din,
// input [31:0] regs_dout,
// update register inputs (will write to register memory current value of the corresponding register)
output update_pending,
input update_all,
output update_busy, // valid same cycle as update_all
input update_gis, // these following individual may be unneeded - just use universal update_all
input update_pis,
input update_ssts,
input update_serr,
input update_pcmd,
input update_pci,
input update_ghc,
/// output reg st01_pending, // software turned PxCMD.ST from 0 to 1
/// output reg st10_pending, // software turned PxCMD.ST from 1 to 0
/// input st_pending_reset,// reset both st01_pending and st10_pending
// PxCMD
// input pcmd_clear_icc, // clear PxCMD.ICC field (generated here)
input pcmd_esp, // external SATA port (just forward value)
output pcmd_cr, // command list run - current
input pcmd_cr_set, // command list run set
input pcmd_cr_reset, // command list run reset
input pcmd_fr, // ahci_fis_receive:get_fis_busy - change to HAB set/reset (set, do, reset)
output pcmd_fre, // FIS enable copy to memory
input pcmd_clear_bsy_drq, // == ahci_fis_receive:clear_bsy_drq
output pcmd_clo, //RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
input pcmd_clear_st, // RW clear ST (start) bit
output pcmd_st, // current value
input pfsm_started, // H: FSM done, P: FSM started (enable sensing pcmd_st_cleared)
output reg pcmd_st_cleared,// ST bit cleared by software; TODO: check not in H:Init (5.3.2.10)
//clear_bsy_drq
// Interrupt inputs
input sirq_TFE, // RWC: Task File Error Status
input sirq_IF, // RWC: Interface Fatal Error Status (sect. 6.1.2)
input sirq_INF, // RWC: Interface Non-Fatal Error Status (sect. 6.1.2)
input sirq_OF, // RWC: Overflow Status
input sirq_PRC, // RO: PhyRdy changed Status
input sirq_PC, // RO: Port Connect Change Status
input sirq_DP, // RWC: Descriptor Processed with "I" bit on
input sirq_UF, // RO: Unknown FIS
input sirq_SDB, // RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set
input sirq_DS, // RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set
input sirq_PS, // RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set
input sirq_DHR, // RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set
// SCR1:SError (only inputs that are not available in sirq_* ones
//sirq_PC,
//sirq_UF
input serr_DT, // RWC: Transport state transition error
input serr_DS, // RWC: Link sequence error
input serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
input serr_DC, // RWC: CRC error in Link layer
input serr_DB, // RWC: 10B to 8B decode error
input serr_DW, // RWC: COMMWAKE signal was detected
input serr_DI, // RWC: PHY Internal Error
// sirq_PRC,
// sirq_IF || // sirq_INF
input serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
input serr_EC, // RWC: Persistent Communication or Data Integrity Error
input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
input serr_EM, // RWC: Communication between the device and host was lost but re-established
input serr_EI, // RWC: Recovered Data integrity Error
output serr_diag_X, // value of PxSERR.DIAG.X
// SCR0: SStatus
input ssts_ipm_dnp, // device not present or communication not established
input ssts_ipm_active, // device in active state
input ssts_ipm_part, // device in partial state
input ssts_ipm_slumb, // device in slumber state
input ssts_ipm_devsleep, // device in DevSleep state
input ssts_spd_dnp, // device not present or communication not established
input ssts_spd_gen1, // Gen 1 rate negotiated
input ssts_spd_gen2, // Gen 2 rate negotiated
input ssts_spd_gen3, // Gen 3 rate negotiated
input ssts_det_ndnp, // no device detected, phy communication not established
input ssts_det_dnp, // device detected, but phy communication not established
input ssts_det_dp, // device detected, phy communication established
input ssts_det_offline, // device offline or BIST
output [3:0] ssts_det, // current value of PxSSTS.DET
// SCR2:SControl (written by software only)
output reg [3:0] sctl_ipm, // Interface power management transitions allowed
output reg [3:0] sctl_spd, // Interface maximal speed
output reg [3:0] sctl_det, // Device detection initialization requested
output reg sctl_det_changed, // Software had written new value to sctl_det
input sctl_det_reset, // clear sctl_det_changed
input pxci0_clear, // PxCI clear
output pxci0, // pxCI current value
input hba_reset_done, // at the end of the HBA reset, clear GHC.HR, GHC.IE
output unsolicited_en, // enable processing of cominit_got and PxERR.DIAG.W interrupts from
// this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4
/*
*/
output reg irq
// Many I/Os to add
);
`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
// wire swr_GHC__IE = soft_write_en && (soft_write_addr == GHC__GHC__IE__ADDR);
wire swr_GHC__IS = soft_write_en && (soft_write_addr == GHC__IS__IPS__ADDR);
wire swr_HBA_PORT__PxCMD = soft_write_en && (soft_write_addr == HBA_PORT__PxCMD__ST__ADDR);
wire swr_HBA_PORT__PxIS = soft_write_en && (soft_write_addr == HBA_PORT__PxIS__CPDS__ADDR);
wire swr_HBA_PORT__PxIE = soft_write_en && (soft_write_addr == HBA_PORT__PxIE__CPDE__ADDR);
wire swr_HBA_PORT__PxSCTL = soft_write_en && (soft_write_addr == HBA_PORT__PxSCTL__SPD__ADDR);
// wire swr_HBA_PORT__PxSSTS = soft_write_en && (soft_write_addr == HBA_PORT__PxSSTS__SPD__ADDR);
wire swr_HBA_PORT__PxSERR = soft_write_en && (soft_write_addr == HBA_PORT__PxSERR__DIAG__X__ADDR);
wire swr_HBA_PORT__PxCI = soft_write_en && (soft_write_addr == HBA_PORT__PxCI__CI__ADDR);
wire swr_GHC__GHC = soft_write_en && (soft_write_addr == GHC__GHC__HR__ADDR);
reg hba_rst_r = 1;
reg rst_por;
reg rst_hba; // @SuppressThisWarning VEditor : Unused, maybe will be used later
reg rst_port; // @SuppressThisWarning VEditor : Unused, maybe will be used later
// reg ghc_ie_r;
reg ghc_is_r;
reg set_ghc_is_r; // active next cycle after one of individual non-masked bits in PxIS is set
reg cleared_ghc; // active next cycle after ghc[1:0] is cleared
reg [31:0] PxIE_r; // some bits will be unused by PxIS_MASK
reg [31:0] PxIS_r; // some bits will be unused by PxIS_MASK
reg [11:0] PxSSTS_r;
reg [31:0] PxSERR_r; // Assuming it is not needed for HBA, just for the software
reg [31:0] PxCMD_r;
reg pxci0_r;
reg [ 1:0] GHC_r; // only 2 bits are used here
wire ghc_ie = GHC_r[1]; // bit 1 of GHC__GHC
reg cirq_PRC; // clear PRC bit when clearing PxSERR.DIAG.N
reg cirq_PC; // clear PC bit when clearing PxSERR.DIAG.X
wire [31:0] cirq ={32{cirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK | // 'h400000;
{32{cirq_PC}} & HBA_PORT__PxIS__PCS__MASK; // 'h40;;};
wire [31:0] sirq = {32{sirq_TFE}} & HBA_PORT__PxIS__TFES__MASK | // 'h40000000;
{32{sirq_IF }} & HBA_PORT__PxIS__IFS__MASK | // 'h8000000;
{32{sirq_INF}} & HBA_PORT__PxIS__INFS__MASK | // 'h4000000;
{32{sirq_OF }} & HBA_PORT__PxIS__OFS__MASK | // 'h1000000;
{32{sirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK | // 'h400000;
{32{sirq_PC & unsolicited_en}} & HBA_PORT__PxIS__PCS__MASK | // 'h40;
{32{sirq_DP}} & HBA_PORT__PxIS__DPS__MASK | // 'h20;
{32{sirq_UF }} & HBA_PORT__PxIS__UFS__MASK | // 'h10;
{32{sirq_SDB}} & HBA_PORT__PxIS__SDBS__MASK | // 'h8;
{32{sirq_DS }} & HBA_PORT__PxIS__DSS__MASK | // 'h4;
{32{sirq_PS }} & HBA_PORT__PxIS__PSS__MASK | // 'h2;
{32{sirq_DHR}} & HBA_PORT__PxIS__DHRS__MASK; // 'h1;
// See if sirq_PC should also be enabled by unsolicited_en. Or not?
wire [31:0] serr = {32{sirq_PC & unsolicited_en}} & HBA_PORT__PxSERR__DIAG__X__MASK | // 'h4000000;
{32{sirq_UF }} & HBA_PORT__PxSERR__DIAG__F__MASK | // 'h2000000;
{32{serr_DT }} & HBA_PORT__PxSERR__DIAG__T__MASK | // 'h1000000;
{32{serr_DS }} & HBA_PORT__PxSERR__DIAG__S__MASK | // 'h800000;
{32{serr_DH }} & HBA_PORT__PxSERR__DIAG__H__MASK | // 'h400000;
{32{serr_DC }} & HBA_PORT__PxSERR__DIAG__C__MASK | // 'h200000;
{32{serr_DB }} & HBA_PORT__PxSERR__DIAG__B__MASK | // 'h80000;
{32{serr_DW & unsolicited_en}} & HBA_PORT__PxSERR__DIAG__W__MASK | // 'h40000;
{32{serr_DI }} & HBA_PORT__PxSERR__DIAG__I__MASK | // 'h20000;
{32{sirq_PRC}} & HBA_PORT__PxSERR__DIAG__N__MASK | // 'h10000;
// {32{sirq_IF | sirq_INF }} & HBA_PORT__PxSERR__ERR__E__MASK | // 'h800;
{32{serr_EE}} & HBA_PORT__PxSERR__ERR__E__MASK | // 'h800;
{32{serr_EP }} & HBA_PORT__PxSERR__ERR__P__MASK | // 'h400;
{32{serr_EC }} & HBA_PORT__PxSERR__ERR__C__MASK | // 'h200;
{32{serr_ET }} & HBA_PORT__PxSERR__ERR__T__MASK | // 'h100;
{32{serr_EM }} & HBA_PORT__PxSERR__ERR__M__MASK | // 'h2;
{32{serr_EI }} & HBA_PORT__PxSERR__ERR__I__MASK; // 'h0;
wire [11:8] sssts_ipm = ({4{ssts_ipm_active}} & 4'h1) |
({4{ssts_ipm_part}} & 4'h2) |
({4{ssts_ipm_slumb}} & 4'h6) |
({4{ssts_ipm_devsleep}} & 4'h8);
wire [ 7:4] sssts_spd = ({4{ssts_spd_gen1}} & 4'h1) |
({4{ssts_spd_gen2}} & 4'h2) |
({4{ssts_spd_gen3}} & 4'h3);
wire [ 3:0] sssts_det = ({4{ssts_det_dnp}} & 4'h1) |
({4{ssts_det_dp}} & 4'h3) |
({4{ssts_det_offline}} & 4'h4);
reg pcmd_clear_icc_r;
wire pcmd_clear_icc = !pcmd_clear_icc_r &&
((PxCMD_r & HBA_PORT__PxCMD__ICC__MASK) == 32'h10000000) &&
((PxSSTS_r & HBA_PORT__PxSSTS__IPM__MASK) == 12'h100) ;
// PxSSTS_r[11:8] HBA_PORT__PxSSTS__IPM__MASK ;
// to update only HBA/async changed bits (not by the software)
wire set_ssts_ipm = ssts_ipm_dnp || ssts_ipm_active || ssts_ipm_part || ssts_ipm_slumb || ssts_ipm_devsleep;
wire set_ssts_spd = ssts_spd_dnp || ssts_spd_gen1 || ssts_spd_gen2|| ssts_spd_gen3;
wire set_ssts_det = ssts_det_ndnp || ssts_det_dnp || ssts_det_dp || ssts_det_offline;
wire set_pxcmd = pcmd_clear_icc || pcmd_esp || pcmd_cr_reset || pcmd_fr || pcmd_clear_bsy_drq || pcmd_clear_st ;
reg pxci_changed;
reg ssts_changed;
reg serr_changed;
reg sirq_changed;
reg pxcmd_changed;
reg ghc_is_changed;
reg ghc_ghc_changed;
// wire [5:0] regs_changed={pxcmd_changed, serr_changed, ssts_changed, pxci_changed, sirq_changed,ghc_is_changed };
wire [6:0] regs_changed={ghc_ghc_changed, pxci_changed, pxcmd_changed, serr_changed, ssts_changed, sirq_changed,ghc_is_changed };
// wire [5:0] update;
reg [6:1] updating;
wire [6:0] update_first = {7{update_all}} &
{regs_changed[6] && ~(|regs_changed[5:0]),
regs_changed[5] && ~(|regs_changed[4:0]),
regs_changed[4] && ~(|regs_changed[3:0]),
regs_changed[3] && ~(|regs_changed[2:0]),
regs_changed[2] && ~(|regs_changed[1:0]),
regs_changed[1] && ~ regs_changed[0],
regs_changed[0]};
wire [6:1] update_next = {updating[6] && ~(|updating[5:1]),
updating[5] && ~(|updating[4:1]),
updating[4] && ~(|updating[3:1]),
updating[3] && ~(|updating[2:1]),
updating[2] && ~ updating[1],
updating[1]};
wire update_GHC__IS = update_gis || update_first[0];
wire update_HBA_PORT__PxIS = update_pis || update_first[1] || update_next[1];
wire update_HBA_PORT__PxSSTS = update_ssts || update_first[2] || update_next[2];
wire update_HBA_PORT__PxSERR = update_serr || update_first[3] || update_next[3];
wire update_HBA_PORT__PxCMD = update_pcmd || update_first[4] || update_next[4];
wire update_HBA_PORT__PxCI = update_pci || update_first[5] || update_next[5];
wire update_GHC_GHC = update_ghc || update_first[6] || update_next[6];
reg pfsm_started_r;
reg unsolicited_en_r;
assign update_busy = (update_all && (|regs_changed)) || (|updating[6:1]);
assign update_pending = | regs_changed;
assign pcmd_fre = |(HBA_PORT__PxCMD__FRE__MASK & PxCMD_r);
assign serr_diag_X = |(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r);
assign ssts_det = PxSSTS_r[3:0];
assign unsolicited_en = unsolicited_en_r;
// assign cirq_PRC = swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);
// assign cirq_PC = swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);
localparam PxIE_MASK = HBA_PORT__PxIE__TFEE__MASK | // 'h40000000;
HBA_PORT__PxIE__IFE__MASK | // 'h8000000;
HBA_PORT__PxIE__INFE__MASK | // 'h4000000;
HBA_PORT__PxIE__OFE__MASK | // 'h1000000;
HBA_PORT__PxIE__PRCE__MASK | // 'h400000;
HBA_PORT__PxIE__PCE__MASK | // 'h40;
HBA_PORT__PxIE__DPE__MASK | // 'h20
HBA_PORT__PxIE__UFE__MASK | // 'h10;
HBA_PORT__PxIE__SDBE__MASK | // 'h8;
HBA_PORT__PxIE__DSE__MASK | // 'h4;
HBA_PORT__PxIE__PSE__MASK | // 'h2;
HBA_PORT__PxIE__DHRE__MASK; // 'h1;
localparam PxIS_MASK = HBA_PORT__PxIS__TFES__MASK | // 'h40000000;
HBA_PORT__PxIS__IFS__MASK | // 'h8000000;
HBA_PORT__PxIS__INFS__MASK | // 'h4000000;
HBA_PORT__PxIS__OFS__MASK | // 'h1000000;
HBA_PORT__PxIS__PRCS__MASK | // 'h400000;
HBA_PORT__PxIS__PCS__MASK | // 'h40;
HBA_PORT__PxIS__DPS__MASK | // 'h20
HBA_PORT__PxIS__UFS__MASK | // 'h10;
HBA_PORT__PxIS__SDBS__MASK | // 'h8;
HBA_PORT__PxIS__DSS__MASK | // 'h4;
HBA_PORT__PxIS__PSS__MASK | // 'h2;
HBA_PORT__PxIS__DHRS__MASK; // 'h1;
localparam PxSERR_MASK = HBA_PORT__PxSERR__DIAG__X__MASK | // 'h4000000;
HBA_PORT__PxSERR__DIAG__F__MASK | // 'h2000000;
HBA_PORT__PxSERR__DIAG__T__MASK | // 'h1000000;
HBA_PORT__PxSERR__DIAG__S__MASK | // 'h800000;
HBA_PORT__PxSERR__DIAG__H__MASK | // 'h400000;
HBA_PORT__PxSERR__DIAG__C__MASK | // 'h200000;
HBA_PORT__PxSERR__DIAG__B__MASK | // 'h80000;
HBA_PORT__PxSERR__DIAG__W__MASK | // 'h40000;
HBA_PORT__PxSERR__DIAG__I__MASK | // 'h20000;
HBA_PORT__PxSERR__DIAG__N__MASK | // 'h10000;
HBA_PORT__PxSERR__ERR__E__MASK | // 'h800;
HBA_PORT__PxSERR__ERR__P__MASK | // 'h400;
HBA_PORT__PxSERR__ERR__C__MASK | // 'h200;
HBA_PORT__PxSERR__ERR__T__MASK | // 'h100;
HBA_PORT__PxSERR__ERR__M__MASK | // 'h2;
HBA_PORT__PxSERR__ERR__I__MASK; // 'h0;
localparam PxCMD_DFLT = HBA_PORT__PxCMD__ICC__DFLT | // 'h0;
HBA_PORT__PxCMD__ASP__DFLT | // 'h0;
HBA_PORT__PxCMD__ALPE__DFLT | // 'h0;
HBA_PORT__PxCMD__DLAE__DFLT | // 'h0;
HBA_PORT__PxCMD__ATAPI__DFLT | // 'h0;
HBA_PORT__PxCMD__APSTE__DFLT | // 'h0;
HBA_PORT__PxCMD__FBSCP__DFLT | // 'h0;
HBA_PORT__PxCMD__ESP__DFLT | // 'h200000;
HBA_PORT__PxCMD__CPD__DFLT | // 'h0;
HBA_PORT__PxCMD__MPSP__DFLT | // 'h0;
HBA_PORT__PxCMD__HPCP__DFLT | // 'h40000;
HBA_PORT__PxCMD__PMA__DFLT | // 'h0;
HBA_PORT__PxCMD__CPS__DFLT | // 'h0;
HBA_PORT__PxCMD__CR__DFLT | // 'h0;
HBA_PORT__PxCMD__FR__DFLT | // 'h0;
HBA_PORT__PxCMD__MPSS__DFLT | // 'h0;
HBA_PORT__PxCMD__CCS__DFLT | // 'h0;
HBA_PORT__PxCMD__FRE__DFLT | // 'h0;
HBA_PORT__PxCMD__CLO__DFLT | // 'h0;
HBA_PORT__PxCMD__POD__DFLT | // 'h4;
HBA_PORT__PxCMD__SUD__DFLT | // 'h2;
HBA_PORT__PxCMD__ST__DFLT; // 'h0;
localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
// HBA_PORT__PxCMD__ASP__MASK | // 'h8000000;
// HBA_PORT__PxCMD__ALPE__MASK | // 'h4000000;
// HBA_PORT__PxCMD__DLAE__MASK | // 'h2000000;
// HBA_PORT__PxCMD__ATAPI__MASK | // 'h1000000;
// HBA_PORT__PxCMD__APSTE__MASK | // 'h800000;
// HBA_PORT__PxCMD__FBSCP__MASK | // 'h400000;
HBA_PORT__PxCMD__ESP__MASK | // 'h200000;
// HBA_PORT__PxCMD__CPD__MASK | // 'h100000;
// HBA_PORT__PxCMD__MPSP__MASK | // 'h80000;
// HBA_PORT__PxCMD__HPCP__MASK | // 'h40000;
// HBA_PORT__PxCMD__PMA__MASK | // 'h20000;
// HBA_PORT__PxCMD__CPS__MASK | // 'h10000;
HBA_PORT__PxCMD__CR__MASK | // 'h8000;
HBA_PORT__PxCMD__FR__MASK | // 'h4000;
// HBA_PORT__PxCMD__MPSS__MASK | // 'h2000;
// HBA_PORT__PxCMD__CCS__MASK | // 'h1f00;
HBA_PORT__PxCMD__FRE__MASK | // 'h10;
HBA_PORT__PxCMD__CLO__MASK | // 'h8;
// HBA_PORT__PxCMD__POD__MASK | // 'h4;
// HBA_PORT__PxCMD__SUD__MASK | // 'h2;
HBA_PORT__PxCMD__ST__MASK; // 'h1;
assign pxci0 = pxci0_r;
assign pcmd_cr = PxCMD_r[15]; // command list run - current
assign pcmd_clo = PxCMD_r[3]; // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
assign pcmd_st = PxCMD_r[0]; // current value
always @(posedge mclk) begin
if (mrst) unsolicited_en_r <= 0;
else if (((PxSSTS_r & HBA_PORT__PxSSTS__DET__MASK) == 3) ||
(sctl_det == 4)) unsolicited_en_r <= 1;
end
always @(posedge mclk) begin
pcmd_clear_icc_r <= pcmd_clear_icc;
end
always @(posedge mclk) begin // Here we do not have data written by soft, only the result (cleared). If bit is 0, it is
// either cleared, or was 0. If it was 0, then IS bit was also 0, so clearing will not hurt.
cirq_PRC <= swr_HBA_PORT__PxSERR && |(~soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);
cirq_PC <= swr_HBA_PORT__PxSERR && |(~soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);
end
always @(posedge mclk) begin
if (mrst) irq <= 0;
// else irq <= ghc_ie_r && ghc_is_r;
else irq <= ghc_ie && ghc_is_r;
end
// generate reset types
always @ (posedge mclk) begin
hba_rst_r <= mrst;
rst_por <= !mrst && hba_rst_r && !was_hba_rst && !was_port_rst;
rst_hba <= !mrst && hba_rst_r && was_hba_rst;
rst_port <= !mrst && hba_rst_r && was_port_rst;
end
// GHC_IE register (just one bit)
// always @(posedge mclk) begin
// if (rst_por) ghc_ie_r <= 0;
// else if (swr_GHC__IE) ghc_ie_r <= |(soft_write_data & GHC__GHC__IE__MASK);
// end
// swr_GHC__IS register (just one bit)
always @(posedge mclk) begin
if (mrst || hba_reset_done) ghc_is_r <= 0; // any reset?
else if (set_ghc_is_r) ghc_is_r <= 1;
else if (swr_GHC__IS) ghc_is_r <= soft_write_data[0];
end
// HBA_PORT__PxIE register
always @(posedge mclk) begin
if (rst_por) PxIE_r <= 0;
else if (swr_HBA_PORT__PxIE) PxIE_r <= PxIE_MASK & soft_write_data;
end
// HBA_PORT__PxIS register
always @(posedge mclk) begin
if (rst_por) PxIS_r <= 0;
else PxIS_r <= PxIS_MASK & ((swr_HBA_PORT__PxIS ? soft_write_data : (PxIS_r & ~cirq)) | sirq);
end
// HBA_PORT__PxIE register
always @(posedge mclk) begin
if (rst_por) set_ghc_is_r <= 0;
// TODO: Not exactly clear - when ghc_is_r should be set after being RWC? After setting some not masked new individual interrupt?
else set_ghc_is_r <= |(sirq & PxIE_r) || hba_reset_done;
end
// GHC__GHC register
always @(posedge mclk) begin
if (rst_por) cleared_ghc <= 0;
else cleared_ghc <= hba_reset_done;
if (rst_por) GHC_r <= 0;
else if (cleared_ghc) GHC_r <= 0;
else if (swr_GHC__GHC) GHC_r <= soft_write_data[1:0];
end
// HBA_PORT__PxSSTS register - updated from the HOST only
always @(posedge mclk) begin
if (mrst) PxSSTS_r[11:8] <= 0;
else if (set_ssts_ipm) PxSSTS_r[11:8] <= sssts_ipm[11:8];
if (mrst) PxSSTS_r[ 7:4] <= 0;
else if (set_ssts_spd) PxSSTS_r[ 7:4] <= sssts_spd[ 7:4];
if (mrst) PxSSTS_r[ 3:0] <= 0;
else if (set_ssts_det) PxSSTS_r[ 3:0] <= sssts_det[ 3:0];
end
// HBA_PORT__PxSCTL register - updated by the software only
always @ (posedge mclk) begin
if (rst_por) {sctl_ipm, sctl_spd, sctl_det} <= 0;
else if (swr_HBA_PORT__PxSCTL) {sctl_ipm, sctl_spd, sctl_det} <= soft_write_data [11:0];
if (rst_por || sctl_det_reset) sctl_det_changed <= 0;
else if (swr_HBA_PORT__PxSCTL && (soft_write_data[3:0] != sctl_det)) sctl_det_changed <= 1;
end
// HBA_PORT__PxSERR register
always @(posedge mclk) begin
if (rst_por) PxSERR_r <= 0;
else PxSERR_r <= PxSERR_MASK & ((swr_HBA_PORT__PxSERR ? soft_write_data : PxSERR_r) | serr);
end
// HBA_PORT__PxCI[0] register - cleared by HBA, set by software
always @(posedge mclk) begin
if (mrst || pxci0_clear) pxci0_r <= 0;
else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0];
end
// HBA_PORT__PxCMD register - different behaviors of different fields
// use PxCMD_MASK to prevent generation of unneeded register bits
always @(posedge mclk) begin
if (mrst) PxCMD_r <= PxCMD_DFLT;
else PxCMD_r <= (~PxCMD_MASK & PxCMD_DFLT ) | (PxCMD_MASK & ( swr_HBA_PORT__PxCMD? soft_write_data : (
(pcmd_clear_icc ? 0 : (PxCMD_r & HBA_PORT__PxCMD__ICC__MASK)) |
(pcmd_esp ? HBA_PORT__PxCMD__ESP__MASK : 0) |
(pcmd_cr_reset ? 0 : (HBA_PORT__PxCMD__CR__MASK & (pcmd_cr_set? (~0):(PxCMD_r)))) |
(pcmd_fr? HBA_PORT__PxCMD__FR__MASK : 0 ) |
(HBA_PORT__PxCMD__FRE__MASK & PxCMD_r) | // no HBA control
(pcmd_clear_bsy_drq ? 0 : (PxCMD_r & HBA_PORT__PxCMD__CLO__MASK)) |
(pcmd_clear_st ? 0 : (PxCMD_r & HBA_PORT__PxCMD__ST__MASK)) )));
if (mrst) pfsm_started_r <= 0;
else if (pfsm_started) pfsm_started_r <= 1;
if (!pfsm_started_r) pcmd_st_cleared <= 0;
// else if (swr_HBA_PORT__PxCMD) pcmd_st_cleared <= |(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data);
else pcmd_st_cleared <= swr_HBA_PORT__PxCMD && (|(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data));
end
// Update AXI registers with the current local data
always @ (posedge mclk) begin
regs_addr <= ({ADDRESS_BITS{update_GHC__IS}} & GHC__IS__IPS__ADDR) |
({ADDRESS_BITS{update_HBA_PORT__PxIS}} & HBA_PORT__PxIS__CPDS__ADDR) |
({ADDRESS_BITS{update_HBA_PORT__PxSSTS}} & HBA_PORT__PxSSTS__SPD__ADDR) |
({ADDRESS_BITS{update_HBA_PORT__PxSERR}} & HBA_PORT__PxSERR__DIAG__X__ADDR) |
({ADDRESS_BITS{update_HBA_PORT__PxCMD}} & HBA_PORT__PxCMD__ICC__ADDR) |
({ADDRESS_BITS{update_HBA_PORT__PxCI}} & HBA_PORT__PxCI__CI__ADDR) |
({ADDRESS_BITS{update_GHC_GHC}} & GHC__GHC__AE__ADDR);
//update_HBA_PORT__PxCI
regs_din <= ({32{update_GHC__IS}} & {31'b0, ghc_is_r}) |
({32{update_HBA_PORT__PxIS}} & PxIS_r) |
({32{update_HBA_PORT__PxSSTS}} & {20'b0, PxSSTS_r[11:0]}) |
({32{update_HBA_PORT__PxSERR}} & PxSERR_r) |
({32{update_HBA_PORT__PxCMD}} & PxCMD_r) |
({32{update_HBA_PORT__PxCI}} & {31'b0, pxci0}) |
({32{update_GHC_GHC}} & (GHC__GHC__AE__DFLT | {30'b0, GHC_r})) ;
regs_we <= update_GHC__IS || update_HBA_PORT__PxIS || update_HBA_PORT__PxSSTS || update_HBA_PORT__PxSERR | update_HBA_PORT__PxCMD || update_HBA_PORT__PxCI || update_GHC_GHC;
// pending updates
if (mrst) pxci_changed <= 1; //0;
else if (pxci0_clear) pxci_changed <= 1;
else if (update_HBA_PORT__PxCI) pxci_changed <= 0;
if (mrst) ssts_changed <= 1; //0;
else if (set_ssts_ipm || set_ssts_spd || set_ssts_det) ssts_changed <= 1;
else if (update_HBA_PORT__PxSSTS) ssts_changed <= 0;
if (mrst) serr_changed <= 1; //0;
else if (|serr) serr_changed <= 1;
else if (update_HBA_PORT__PxSERR) serr_changed <= 0;
if (mrst) sirq_changed <= 1; //0;
else if ((|sirq) || (|cirq)) sirq_changed <= 1;
else if (update_HBA_PORT__PxIS) sirq_changed <= 0;
if (mrst) pxcmd_changed <= 1; //0;
else if (set_pxcmd) pxcmd_changed <= 1;
else if (update_HBA_PORT__PxCMD) pxcmd_changed <= 0;
if (mrst) ghc_is_changed <= 1; //0;
else if (set_ghc_is_r) ghc_is_changed <= 1;
else if (update_GHC__IS) ghc_is_changed <= 0;
if (mrst) ghc_ghc_changed <= 1; //0;
else if (set_ghc_is_r) ghc_ghc_changed <= 1;
else if (update_GHC_GHC) ghc_ghc_changed <= 0;
// updating registers if needed, 0 to 6 cycles, in priority sequence
if (mrst) updating[6:1] <= 0;
else if (update_all) updating[6:1] <= regs_changed[6:1] & ~update_first[6:1];
else updating[6:1] <= updating[6:1] & ~ update_next[6:1];
// detect software setting for PxCMD.ST 0->1 and 1->0
/*
if (mrst) st01_pending <= 0;
else if (swr_HBA_PORT__PxCMD && (HBA_PORT__PxCMD__ST__MASK & soft_write_data & ~PxCMD_r)) st01_pending <= 1;
if (st_pending_reset) st01_pending <= 0;
if (mrst) st10_pending <= 0;
else if (swr_HBA_PORT__PxCMD && (HBA_PORT__PxCMD__ST__MASK & ~soft_write_data & PxCMD_r)) st10_pending <= 1;
if (st_pending_reset) st10_pending <= 0;
*/
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Data Path Mask Generator
// File : ded_mskgen.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_mskgen
#(parameter BYTES = 4)
(
input de_clk, // drawing engine clock
de_rstn, // drawing engine reset
mclock, // memory controller clock
mc_acken, // memory controller pop enable
mc_popen, // memory controller pop enable
input ld_msk, // load mask registers
input line_actv_4, // line command active bit
blt_actv_4, // blt command active bit
input [1:0] clp_4, // clipping control register
input mem_req, // memory request signal
input mem_rd, // memory read signal
input [BYTES-1:0] pc_msk_in, // pixel cache mask
input [31:0] clpx_bus_2, // clipping {xmax[15:4],xmin[15:4]}
input [15:0] x_bus, // bus from execution X dest counter
input [6:0] xalu_bus, // bus from execution unit X alu
input trnsp_4, // Transparent bit
input [BYTES-1:0] trns_msk_in, // Transparentcy mask
input ps16_2, // pixel size equals 16
input ps32_2, // pixel size equals 32
input mc_eop, // mc end of page delayed
input [3:0] mask_4, // plane mask
input [6:0] lft_enc_4,
input [6:0] rht_enc_4,
input [11:0] clp_min_4, // left clipping pointer
input [11:0] clp_max_4, // right clipping pointer
input [3:0] cmin_enc_4,
input [3:0] cmax_enc_4,
input y_clip_4,
input sol_4,
input eol_4,
input [13:0] x_count_4, // current X position
input mc_eop4,
output reg [BYTES-1:0] pixel_msk, // pixel mask for the memory controller
output reg clip_ind, // Clip indicator
output reg [6:0] lft_enc_2,
output reg [6:0] rht_enc_2,
output [11:0] clp_min_2, // left clipping pointer
output [11:0] clp_max_2, // right clipping pointer
output reg [3:0] cmin_enc_2,
output reg [3:0] cmax_enc_2
);
wire iclip_ind; // Clip indicator
wire [BYTES-1:0] trns_msk; // Transparentcy mask
reg last_mask; // end of line pulse level 4
/* register the mask bits from the execution unit. */
reg mc_eop_del;
reg [15:0] pixel_msk_2d_del;// pixel mask for the memory controller
reg [15:0] pixel_msk_2d_del2;// pixel mask for the memory controller
reg blt_actv_4_d, sol_4_d;
reg [BYTES-1:0] pc_msk_del;
reg [15:0] clp_msk;
wire [15:0] cmin_msk;
wire [15:0] cmax_msk;
reg [15:0] lft;
reg [15:0] rht;
wire [15:0] rht_msk;
wire [15:0] lft_msk;
wire [15:0] mid_msk;
reg cmin_en; // clipping min mask enable
reg cmax_en; // clipping max mask enable
reg xl_cmin;
reg cmaxl_x;
wire drw_outside_4; // draw outside of clipping box
wire drw_inside_4; // draw inside of clipping box
wire x_clip;
reg [15:0] pixel_msk_0; // pixel mask for the memory controller
reg [1:0] sub_page;
reg [1:0] sub_page_1;
reg [1:0] sub_page_2;
reg [1:0] sub_page_3;
reg [1:0] sub_page_4;
// Latch the mask values
always @(posedge de_clk or negedge de_rstn) begin
if (!de_rstn) begin
lft_enc_2<=0;
rht_enc_2 <=0;
end else if (ld_msk) begin
lft_enc_2 <=x_bus[6:0];
rht_enc_2<=xalu_bus-7'b1;
end
end
assign clp_min_2 = clpx_bus_2[15:4];
assign clp_max_2 = clpx_bus_2[31:20];
// Latch the encode mask values
// clpx_bus_2 = {xmax,xmin}
always @* begin
cmin_enc_2 = clpx_bus_2[3:0];
casex ({ps16_2, ps32_2})
2'b1x: cmax_enc_2 = clpx_bus_2[19:16]+4'b0001; // 16 bpp
2'b01: cmax_enc_2 = clpx_bus_2[19:16]+4'b0011; // 32 bpp
2'b00: cmax_enc_2 = clpx_bus_2[19:16]; // 8 bpp
endcase
end
always @* begin
// create the mask enable control bits
`ifdef BYTE16
cmin_en = (x_count_4 == clp_min_4);
cmax_en = (x_count_4 == clp_max_4);
`endif
`ifdef BYTE8
cmin_en = (x_count_4[12:1] == clp_min_4);
cmax_en = (x_count_4[12:1] == clp_max_4);
`endif
`ifdef BYTE4
cmin_en = (x_count_4[13:2] == clp_min_4);
cmax_en = (x_count_4[13:2] == clp_max_4);
`endif
end
`ifdef BYTE4
always @* begin
if (x_count_4[13] & !clp_min_4[11]) xl_cmin = 1;
else if (!x_count_4[13] & clp_min_4[11]) xl_cmin = 0;
else if (x_count_4[13:2] < clp_min_4) xl_cmin = 1;
else xl_cmin = 0;
end
always @* begin
if (x_count_4[13] & !clp_max_4[11]) cmaxl_x = 0;
else if (!x_count_4[13] & clp_max_4[11]) cmaxl_x = 1;
else if (x_count_4[13:2] > clp_max_4) cmaxl_x = 1;
else cmaxl_x = 0;
end
`endif
`ifdef BYTE8
always @* begin
if (x_count_4[12] & !clp_min_4[11]) xl_cmin = 1;
else if (!x_count_4[12] & clp_min_4[11]) xl_cmin = 0;
else if (x_count_4[12:1] < clp_min_4) xl_cmin = 1;
else xl_cmin = 0;
end
always @* begin
if (x_count_4[12] & !clp_max_4[11]) cmaxl_x = 0;
else if (!x_count_4[12] & clp_max_4[11]) cmaxl_x = 1;
else if (x_count_4[12:1] > clp_max_4) cmaxl_x = 1;
else cmaxl_x = 0;
end
`endif
`ifdef BYTE16
always @* begin
if (x_count_4[11] & !clp_min_4[11]) xl_cmin = 1;
else if (!x_count_4[11] & clp_min_4[11]) xl_cmin = 0;
else if (x_count_4[11:0] < clp_min_4) xl_cmin = 1;
else xl_cmin = 0;
end
always @* begin
if (x_count_4[11] & !clp_max_4[11]) cmaxl_x = 0;
else if (!x_count_4[11] & clp_max_4[11]) cmaxl_x = 1;
else if (x_count_4[11:0] > clp_max_4) cmaxl_x = 1;
else cmaxl_x = 0;
end
`endif
assign drw_outside_4 = (clp_4[1] & clp_4[0]);
assign drw_inside_4 = (clp_4[1] & ~clp_4[0]);
assign x_clip = (drw_outside_4 & !(xl_cmin | cmaxl_x)) ||
(drw_inside_4 & (xl_cmin | cmaxl_x));
always @(posedge mclock) mc_eop_del <= mc_eop;
always @(posedge mclock or negedge de_rstn) begin
if (!de_rstn) clip_ind <= 0;
else if (mc_eop_del) clip_ind <= 0;
else if (iclip_ind & mc_popen) clip_ind <= 1;
end
// combine all of the masks
assign cmin_msk = left_clip(drw_outside_4,cmin_enc_4);
assign cmax_msk = rght_clip(drw_outside_4,cmax_enc_4);
assign iclip_ind =
(blt_actv_4 & drw_outside_4 & x_clip & y_clip_4 &
!(cmin_en | cmax_en)) |
(blt_actv_4 & drw_inside_4 & y_clip_4) |
(blt_actv_4 & drw_inside_4 & x_clip & !(cmin_en | cmax_en)) |
(blt_actv_4 & drw_inside_4 & cmin_en & cmax_en & !y_clip_4) |
(blt_actv_4 & drw_outside_4 & cmin_en & cmax_en & y_clip_4) |
(blt_actv_4 & drw_inside_4 & cmin_en & !y_clip_4) |
(blt_actv_4 & drw_outside_4 & cmin_en & y_clip_4) |
(blt_actv_4 & drw_inside_4 & cmax_en & !y_clip_4) |
(blt_actv_4 & drw_outside_4 & cmax_en & y_clip_4);
assign rht_msk = ((blt_actv_4_d) & last_mask & sol_4_d) ? (rht | lft) :
((blt_actv_4_d) & last_mask) ? rht : 16'hFFFF;
assign lft_msk = ((blt_actv_4_d) & sol_4_d & !last_mask) ? lft : 16'hFFFF;
assign mid_msk = (blt_actv_4_d & last_mask) ? 16'hFFFF :
((blt_actv_4_d & sol_4_d) ? 16'hFFFF :
((blt_actv_4_d) ? 16'h0 : 16'hFFFF));
assign trns_msk = (trnsp_4 && !line_actv_4) ? ~trns_msk_in : 16'h0;
always @(posedge mclock) begin
// Delay Controls
blt_actv_4_d <= blt_actv_4;
sol_4_d <= sol_4;
// Delay the rht, lft mask, and the last_mask signal
lft <= {1'b0, {15{1'b1}}} >> (~lft_enc_4[3:0]);
rht <= {{15{1'b1}}, 1'b0} << (rht_enc_4[3:0]);
last_mask <= (eol_4 & mc_eop4);
clp_msk <= (blt_actv_4 & drw_outside_4 & x_clip & y_clip_4 & !(cmin_en | cmax_en)) ? {16{1'b1}} :
(blt_actv_4 & drw_inside_4 & y_clip_4) ? {16{1'b1}} :
(blt_actv_4 & drw_inside_4 & x_clip & !(cmin_en | cmax_en)) ? {16{1'b1}} :
(blt_actv_4 & drw_inside_4 & cmin_en & cmax_en & !y_clip_4) ? (cmin_msk | cmax_msk) :
(blt_actv_4 & drw_outside_4 & cmin_en & cmax_en & y_clip_4) ? (cmin_msk & cmax_msk) :
(blt_actv_4 & drw_inside_4 & cmin_en & !y_clip_4) ? cmin_msk :
(blt_actv_4 & drw_outside_4 & cmin_en & y_clip_4) ? cmin_msk :
(blt_actv_4 & drw_inside_4 & cmax_en & !y_clip_4) ? cmax_msk :
(blt_actv_4 & drw_outside_4 & cmax_en & y_clip_4) ? cmax_msk :
16'h0;
sub_page_4 <= sub_page_3;
sub_page_3 <= sub_page_2;
sub_page_2 <= sub_page_1;
sub_page_1 <= sub_page;
if(mc_acken) sub_page <= 1'b0;
else if(mc_popen) sub_page <= sub_page + 1'b1;
pixel_msk_2d_del <= (lft_msk & rht_msk & mid_msk) | clp_msk;
pixel_msk_2d_del2 <= pixel_msk_2d_del;
pc_msk_del <= pc_msk_in;
// Pipe stage added to increase MC clock speed
// trans mask has to be last because of delays of cx_reg
// pixel_msk_0 <= line_actv_4 ? pc_msk_del : (pixel_msk_0 | trns_msk | ~{(BYTES/2){mask_4}});
`ifdef BYTE16 pixel_msk_0 <= line_actv_4 ? pc_msk_del : pixel_msk_2d_del2; `endif
`ifdef BYTE8 pixel_msk_0 <= line_actv_4 ? {2{pc_msk_del}} : pixel_msk_2d_del2; `endif
`ifdef BYTE4 pixel_msk_0 <= line_actv_4 ? {4{pc_msk_del}} : pixel_msk_2d_del2; `endif
if (BYTES == 16)
pixel_msk <= pixel_msk_0 | ((!line_actv_4) ? trns_msk : 16'h0) | ~{4{mask_4}};
else if (BYTES == 8)
case (sub_page_4[0])
1'b0: pixel_msk <= pixel_msk_0[7:0] | ((!line_actv_4) ? trns_msk : 8'h0) | ~{2{mask_4}};
1'b1: pixel_msk <= pixel_msk_0[15:8] | ((!line_actv_4) ? trns_msk : 8'h0) | ~{2{mask_4}};
endcase
else
case (sub_page_4[1:0])
2'b00: pixel_msk <= pixel_msk_0[3:0] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
2'b01: pixel_msk <= pixel_msk_0[7:4] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
2'b10: pixel_msk <= pixel_msk_0[11:8] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
2'b11: pixel_msk <= pixel_msk_0[15:12] | ((!line_actv_4) ? trns_msk : 4'h0) | ~mask_4;
endcase
end
// function to generate the left clipping mask
function [15:0] left_clip;
input inv_msk;
input [3:0] msk_in;
reg [15:0] mask;
begin
/* left clip mask */
case(msk_in) /* synopsys full_case parallel_case */
0: mask = 16'b0000000000000000;
1: mask = 16'b0000000000000001;
2: mask = 16'b0000000000000011;
3: mask = 16'b0000000000000111;
4: mask = 16'b0000000000001111;
5: mask = 16'b0000000000011111;
6: mask = 16'b0000000000111111;
7: mask = 16'b0000000001111111;
8: mask = 16'b0000000011111111;
9: mask = 16'b0000000111111111;
10: mask = 16'b0000001111111111;
11: mask = 16'b0000011111111111;
12: mask = 16'b0000111111111111;
13: mask = 16'b0001111111111111;
14: mask = 16'b0011111111111111;
15: mask = 16'b0111111111111111;
endcase
if(inv_msk)left_clip=~mask;
else left_clip=mask;
end
endfunction
// function to generate the right clipping mask and window max.
function [15:0] rght_clip;
input inv_msk;
input [3:0] msk_in;
reg [15:0] mask;
begin
/* right mask */
case(msk_in) /* synopsys full_case parallel_case */
0: mask = 16'b1111111111111110;
1: mask = 16'b1111111111111100;
2: mask = 16'b1111111111111000;
3: mask = 16'b1111111111110000;
4: mask = 16'b1111111111100000;
5: mask = 16'b1111111111000000;
6: mask = 16'b1111111110000000;
7: mask = 16'b1111111100000000;
8: mask = 16'b1111111000000000;
9: mask = 16'b1111110000000000;
10: mask = 16'b1111100000000000;
11: mask = 16'b1111000000000000;
12: mask = 16'b1110000000000000;
13: mask = 16'b1100000000000000;
14: mask = 16'b1000000000000000;
15: mask = 16'b0000000000000000;
endcase
if(inv_msk)rght_clip=~mask;
else rght_clip=mask;
end
endfunction
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_BLACKBOX_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_BLACKBOX_V
|
Require Import Verdi.Verdi.
Require Import Verdi.LabeledNet.
Require Import Verdi.TotalMapSimulations.
Require Import Verdi.PartialMapSimulations.
Require Import Verdi.TotalMapExecutionSimulations.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.map.
Require Import InfSeqExt.exteq.
Require Import FunctionalExtensionality.
Local Arguments update {_} {_} _ _ _ _ _ : simpl never.
Require Import Verdi.Ssrexport.
Require Import ssr.ssrbool.
Set Implicit Arguments.
Class LabeledMultiParamsPartialMapCongruency
(B0 : BaseParams) (B1 : BaseParams)
(P0 : LabeledMultiParams B0) (P1 : LabeledMultiParams B1)
(B : BaseParamsPartialMap B0 B1)
(N : MultiParamsNameTotalMap (@unlabeled_multi_params _ P0) (@unlabeled_multi_params _ P1))
(P : MultiParamsMsgPartialMap (@unlabeled_multi_params _ P0) (@unlabeled_multi_params _ P1))
(L : LabeledMultiParamsLabelTotalMap P0 P1) : Prop :=
{
pt_lb_label_silent_fst_snd : tot_map_label label_silent = label_silent ;
pt_lb_net_handlers_some : forall me src m st m' out st' ps lb,
pt_map_msg m = Some m' ->
lb_net_handlers (tot_map_name me) (tot_map_name src) m' (pt_map_data st) = (lb, out, st', ps) ->
lb <> label_silent /\ tot_mapped_lb_net_handlers_label me src m st = lb ;
pt_lb_net_handlers_none : forall me src m st,
pt_map_msg m = None ->
tot_mapped_lb_net_handlers_label me src m st = label_silent ;
pt_lb_input_handlers_some : forall me inp st inp' out st' ps lb,
pt_map_input inp = Some inp' ->
lb_input_handlers (tot_map_name me) inp' (pt_map_data st) = (lb, out, st', ps) ->
lb <> label_silent /\ tot_mapped_lb_input_handlers_label me inp st = lb ;
pt_lb_input_handlers_none : forall me inp st,
pt_map_input inp = None ->
tot_mapped_lb_input_handlers_label me inp st = label_silent
}.
Section PartialMapExecutionSimulations.
Context {base_fst : BaseParams}.
Context {base_snd : BaseParams}.
Context {labeled_multi_fst : LabeledMultiParams base_fst}.
Context {labeled_multi_snd : LabeledMultiParams base_snd}.
Context {base_map : BaseParamsPartialMap base_fst base_snd}.
Context {name_map : MultiParamsNameTotalMap (@unlabeled_multi_params _ labeled_multi_fst) (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {msg_map : MultiParamsMsgPartialMap (@unlabeled_multi_params _ labeled_multi_fst) (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {label_map : LabeledMultiParamsLabelTotalMap labeled_multi_fst labeled_multi_snd}.
Context {name_map_bijective : MultiParamsNameTotalMapBijective name_map}.
Context {multi_map_congr : MultiParamsPartialMapCongruency base_map name_map msg_map}.
Context {multi_map_lb_congr : LabeledMultiParamsPartialMapCongruency base_map name_map msg_map label_map}.
Hypothesis label_eq_dec : forall x y : label, {x = y} + {x <> y}.
Hypothesis tot_map_label_injective :
forall l l', tot_map_label l = tot_map_label l' -> l = l'.
Hypothesis label_tot_mapped :
forall l, exists l', l = tot_map_label l'.
(* lb_step_failure *)
Theorem lb_step_failure_pt_mapped_simulation_1_non_silent :
forall net net' failed failed' lb tr,
tot_map_label lb <> label_silent ->
@lb_step_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_failure _ labeled_multi_snd (List.map tot_map_name failed, pt_map_net net) (tot_map_label lb) (List.map tot_map_name failed', pt_map_net net') (filterMap pt_map_trace_occ tr).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_neq H_step.
have H_neq': lb <> label_silent.
rewrite -pt_lb_label_silent_fst_snd in H_neq.
move => H_eq.
by rewrite H_eq in H_neq.
invcs H_step => //=.
- destruct (pt_map_packet p) eqn:?; last first.
destruct p.
simpl in *.
break_match => //.
have H_q := @pt_lb_net_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr pDst pSrc _ (nwState net pDst) Heqo0.
rewrite /tot_mapped_lb_net_handlers_label in H_q.
repeat break_let.
by tuple_inversion.
have H_eq_n: tot_map_name (pDst p) = pDst p0.
destruct p.
simpl in *.
break_match => //.
by find_injection.
rewrite H_eq_n.
apply (@LabeledStepFailure_deliver _ _ _ _ _ _ (filterMap pt_map_packet xs) (filterMap pt_map_packet ys) (filterMap pt_map_output out) (pt_map_data d) (filterMap (@pt_map_name_msg _ _ _ _ _ msg_map) l)).
* rewrite /pt_map_net /=.
find_rewrite.
by rewrite filterMap_app /= Heqo.
* rewrite -H_eq_n.
exact: not_in_failed_not_in.
* rewrite /pt_map_net /= -{2}H_eq_n tot_map_name_inv_inverse.
destruct p, p0.
simpl in *.
break_match => //.
find_injection.
clean.
have H_q := @pt_net_handlers_some _ _ _ _ _ _ _ multi_map_congr pDst pSrc pBody (nwState net pDst) _ Heqo0.
rewrite /pt_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_net_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ _ Heqo0 Heqp1.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
break_and.
by repeat tuple_inversion.
* rewrite /pt_map_net /= 2!filterMap_app.
by rewrite (filterMap_pt_map_packet_map_eq_some _ _ Heqo) (pt_map_update_eq_some _ _ _ Heqo).
- case H_i: pt_map_input => [inp'|]; last first.
have H_q := @pt_lb_input_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr h _ (nwState net h) H_i.
rewrite /tot_mapped_lb_input_handlers_label /= in H_q.
repeat break_let.
by tuple_inversion.
apply (@LabeledStepFailure_input _ _ _ _ _ _ _ _ (pt_map_data d) (filterMap (@pt_map_name_msg _ _ _ _ _ msg_map) l)).
* exact: not_in_failed_not_in.
* have H_q := @pt_input_handlers_some _ _ _ _ _ _ _ multi_map_congr h _ (nwState net h) _ H_i.
rewrite /pt_mapped_input_handlers /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_input_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ H_i Heqp1.
break_and.
unfold tot_mapped_lb_input_handlers_label in *.
repeat break_let.
repeat tuple_inversion.
by rewrite /pt_map_net /= tot_map_name_inv_inverse.
* rewrite /pt_map_net /=.
rewrite filterMap_app filterMap_pt_map_packet_map_eq.
by rewrite -(@pt_map_update_eq _ _ _ _ _ _ name_map_bijective).
Qed.
Theorem lb_step_failure_pt_mapped_simulation_1_silent :
forall net net' failed failed' lb tr,
tot_map_label lb = label_silent ->
@lb_step_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_failure _ labeled_multi_snd (List.map tot_map_name failed, pt_map_net net) label_silent (List.map tot_map_name failed', pt_map_net net') [] /\ filterMap trace_non_empty_out (filterMap pt_map_trace_occ tr) = [].
Proof using multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_eq H_step.
invcs H_step => //=.
- destruct (pt_map_packet p) eqn:?.
destruct p, p0.
simpl in *.
break_match_hyp => //.
find_injection.
have H_q := @pt_net_handlers_some _ _ _ _ _ _ _ multi_map_congr pDst pSrc pBody (nwState net pDst) _ Heqo0.
rewrite /pt_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_net_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ _ Heqo0 Heqp1.
break_and.
unfold tot_mapped_lb_net_handlers_label in *.
repeat break_let.
by repeat tuple_inversion.
destruct p.
simpl in *.
break_match_hyp => //.
have H_q := @pt_net_handlers_none _ _ _ _ _ _ _ multi_map_congr pDst pSrc pBody (nwState net pDst) out d l Heqo0.
rewrite /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
concludes.
break_and.
have H_q' := @pt_lb_net_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr pDst pSrc _ (nwState net pDst) Heqo0.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
repeat tuple_inversion.
rewrite /pt_map_net /=.
rewrite filterMap_app.
rewrite filterMap_pt_map_name_msg_empty_eq //=.
rewrite H3.
rewrite filterMap_app /=.
repeat break_match => //.
rewrite -filterMap_app.
set s1 := fun _ => _.
set s2 := fun _ => _.
have H_eq_s: s1 = s2.
rewrite /s1 /s2.
apply functional_extensionality => n.
rewrite /update.
by break_if; first by rewrite H e.
rewrite -H_eq_s /s1 {s1 s2 H_eq_s}.
split => //.
exact: LabeledStepFailure_stutter.
- case H_i: (pt_map_input inp) => [inp'|].
have H_q := @pt_input_handlers_some _ _ _ _ _ _ _ multi_map_congr h _ (nwState net h) _ H_i.
rewrite /pt_mapped_input_handlers /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_input_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ H_i Heqp1.
break_and.
unfold tot_mapped_lb_input_handlers_label in *.
repeat break_let.
by tuple_inversion.
have H_q := @pt_input_handlers_none _ _ _ _ _ _ _ multi_map_congr h _ (nwState net h) out d l H_i.
rewrite /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
concludes.
break_and.
have H_q' := @pt_lb_input_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr h _ (nwState net h) H_i.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
repeat tuple_inversion.
rewrite /pt_map_net /=.
rewrite filterMap_app.
rewrite filterMap_pt_map_name_msg_empty_eq //=.
set s1 := fun _ => _.
set s2 := fun _ => _.
have H_eq_s: s1 = s2.
rewrite /s1 /s2.
apply functional_extensionality => n.
rewrite /update.
by break_if; first by rewrite H e.
rewrite -H_eq_s /s1 {s1 s2 H_eq_s}.
split; first exact: LabeledStepFailure_stutter.
by repeat find_rewrite.
- split => //; exact: LabeledStepFailure_stutter.
Qed.
(* lb_step_ordered_failure *)
Theorem lb_step_ordered_failure_pt_mapped_simulation_1_non_silent :
forall net net' failed failed' lb tr,
tot_map_label lb <> label_silent ->
@lb_step_ordered_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_ordered_failure _ labeled_multi_snd (List.map tot_map_name failed, pt_map_onet net) (tot_map_label lb) (List.map tot_map_name failed', pt_map_onet net') (filterMap pt_map_trace_ev tr).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_neq H_step.
have H_neq': lb <> label_silent.
rewrite -pt_lb_label_silent_fst_snd in H_neq.
move => H_eq.
by rewrite H_eq in H_neq.
invcs H_step => //=.
- rewrite {2}/pt_map_onet /=.
case H_m: (@pt_map_msg _ _ _ _ msg_map m) => [m'|]; last first.
have H_q := @pt_lb_net_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr to from _ (onwState net to) H_m.
rewrite /tot_mapped_lb_net_handlers_label in H_q.
repeat break_let.
by tuple_inversion.
apply (@LabeledStepOrderedFailure_deliver _ _ _ _ _ _ m' (filterMap (@pt_map_msg _ _ _ _ msg_map) ms) (filterMap pt_map_output out) (pt_map_data d) (filterMap (@pt_map_name_msg _ _ _ _ _ msg_map) l) (@tot_map_name _ _ _ _ name_map from) (@tot_map_name _ _ _ _ name_map to)).
* by rewrite /= 2!tot_map_name_inv_inverse /= H3 /= H_m.
* exact: not_in_failed_not_in.
* rewrite /pt_map_onet /= tot_map_name_inv_inverse.
have H_q := @pt_net_handlers_some _ _ _ _ _ _ _ multi_map_congr to from m (onwState net to) _ H_m.
rewrite /pt_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_net_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ _ H_m Heqp1.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
break_and.
by repeat tuple_inversion.
* rewrite (@collate_pt_map_update2_eq _ _ _ _ name_map).
set f1 := fun _ => pt_map_data _.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2.
apply functional_extensionality => n.
rewrite /update.
break_if; break_if => //=; first by rewrite -e tot_map_name_inverse_inv in n0.
by rewrite e tot_map_name_inv_inverse in n0.
by rewrite H_eq_f.
* by rewrite -filterMap_pt_map_trace_ev_outputs_eq.
- rewrite {2}/pt_map_onet /=.
case H_i: pt_map_input => [inp'|]; last first.
have H_q := @pt_lb_input_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr h inp (onwState net h) H_i.
rewrite /tot_mapped_lb_input_handlers_label in H_q.
repeat break_let.
by tuple_inversion.
apply (@LabeledStepOrderedFailure_input _ _ (@tot_map_name _ _ _ _ name_map h) _ _ _ _ (filterMap pt_map_output out) inp' (pt_map_data d) (filterMap (@pt_map_name_msg _ _ _ _ _ msg_map) l)).
* exact: not_in_failed_not_in.
* rewrite /pt_map_onet /= tot_map_name_inv_inverse.
have H_q := @pt_input_handlers_some _ _ _ _ _ _ _ multi_map_congr h inp (onwState net h) _ H_i.
rewrite /pt_mapped_input_handlers /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_input_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ H_i Heqp1.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
break_and.
by repeat tuple_inversion.
* rewrite {2}/pt_map_onet /=.
rewrite (@collate_pt_map_eq _ _ _ _ name_map).
set f1 := fun _ => pt_map_data _.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2.
apply functional_extensionality => n.
rewrite /update.
break_if; break_if => //=; first by rewrite -e tot_map_name_inverse_inv in n0.
by rewrite e tot_map_name_inv_inverse in n0.
by rewrite H_eq_f.
* by rewrite -(@filterMap_pt_map_trace_ev_outputs_eq _ _ _ _ _ name_map out h).
Qed.
Theorem lb_step_ordered_failure_pt_mapped_simulation_1_silent :
forall net net' failed failed' lb tr,
tot_map_label lb = label_silent ->
@lb_step_ordered_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_ordered_failure _ labeled_multi_snd (List.map tot_map_name failed, pt_map_onet net) label_silent (List.map tot_map_name failed', pt_map_onet net') [] /\ filterMap pt_map_trace_ev tr = [].
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_eq H_step.
invcs H_step => //=.
- rewrite {2}/pt_map_onet /=.
case H_m: (@pt_map_msg _ _ _ _ msg_map m) => [m'|].
have H_q := @pt_net_handlers_some _ _ _ _ _ _ _ multi_map_congr to from m (onwState net to) _ H_m.
rewrite /pt_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_net_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ _ H_m Heqp1.
break_and.
unfold tot_mapped_lb_net_handlers_label in *.
repeat break_let.
by repeat tuple_inversion.
have H_q := @pt_net_handlers_none _ _ _ _ _ _ _ multi_map_congr to from m (onwState net to) out d l H_m.
rewrite /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
concludes.
break_and.
have H_q' := @pt_lb_net_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr to from _ (onwState net to) H_m.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
repeat tuple_inversion.
rewrite /pt_map_onet /=.
rewrite (@collate_pt_map_update2_eq _ _ _ _ name_map) /=.
rewrite H0 /=.
set p1 := fun _ _ => _.
set p2 := update2 _ _ _ _ _.
set s1 := fun _ => _.
set s2 := fun _ => _.
have H_eq_p: p1 = p2.
rewrite /p1 /p2 /update2.
apply functional_extensionality => src.
apply functional_extensionality => dst.
break_if => //.
break_and.
by rewrite -H2 -H5 2!tot_map_name_inv_inverse H3 /= H_m.
have H_eq_s: s1 = s2.
rewrite /s1 /s2 /update.
apply functional_extensionality => n.
break_if => //.
by rewrite H e.
rewrite H_eq_p H_eq_s.
split; first exact: LabeledStepOrderedFailure_stutter.
rewrite (@filterMap_pt_map_trace_ev_outputs_eq _ _ _ _ _ name_map out to).
by repeat find_rewrite.
- case H_i: (pt_map_input inp) => [inp'|].
have H_q := @pt_input_handlers_some _ _ _ _ _ _ _ multi_map_congr h _ (onwState net h) _ H_i.
rewrite /pt_mapped_input_handlers /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_input_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ H_i Heqp1.
break_and.
unfold tot_mapped_lb_input_handlers_label in *.
repeat break_let.
by tuple_inversion.
have H_q := @pt_input_handlers_none _ _ _ _ _ _ _ multi_map_congr h _ (onwState net h) out d l H_i.
rewrite /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
concludes.
break_and.
have H_q' := @pt_lb_input_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr h _ (onwState net h) H_i.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
repeat tuple_inversion.
rewrite /pt_map_onet /=.
rewrite (@collate_pt_map_eq _ _ _ _ name_map) H0 /=.
set s1 := fun _ => pt_map_data _.
set s2 := fun _ => pt_map_data _.
have H_eq_s: s1 = s2.
rewrite /s1 /s2.
apply functional_extensionality => n.
rewrite /update.
by break_if; first by rewrite H e.
rewrite -H_eq_s /s1 {s1 s2 H_eq_s}.
split; first exact: LabeledStepOrderedFailure_stutter.
rewrite (@filterMap_pt_map_trace_ev_outputs_eq _ _ _ _ _ name_map).
by repeat find_rewrite.
- by split => //; exact: LabeledStepOrderedFailure_stutter.
Qed.
Definition pt_map_onet_event e :=
{| evt_a := (List.map tot_map_name (fst e.(evt_a)), pt_map_onet (snd e.(evt_a))) ;
evt_l := tot_map_label e.(evt_l) ;
evt_trace := filterMap pt_map_trace_ev e.(evt_trace) |}.
Lemma pt_map_onet_event_Map_unfold : forall s,
Cons (pt_map_onet_event (hd s)) (map pt_map_onet_event (tl s)) = map pt_map_onet_event s.
Proof using.
by move => s; rewrite -map_Cons /= -{3}(recons s).
Qed.
Lemma lb_step_execution_lb_step_ordered_failure_pt_map_onet_infseq : forall s,
lb_step_execution lb_step_ordered_failure s ->
lb_step_execution lb_step_ordered_failure (map pt_map_onet_event s).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr label_eq_dec.
cofix c.
move => s H_exec.
rewrite -pt_map_onet_event_Map_unfold {1}/pt_map_onet_event /=.
inversion H_exec; subst => /=.
rewrite -pt_map_onet_event_Map_unfold /= /pt_map_onet_event /=.
case (label_eq_dec (tot_map_label (evt_l e)) label_silent) => H_eq.
apply: Cons_lb_step_exec.
- rewrite H_eq.
destruct e, e'.
destruct evt_a, evt_a0.
simpl in *.
by eapply lb_step_ordered_failure_pt_mapped_simulation_1_silent; eauto.
- destruct e, e'.
destruct evt_a, evt_a0.
apply (lb_step_ordered_failure_pt_mapped_simulation_1_silent H_eq) in H.
break_and.
simpl in *.
rewrite H0 filterMap_app.
by aggressive_rewrite_goal.
- pose s' := Cons e' s0.
rewrite (pt_map_onet_event_Map_unfold s').
exact: c.
apply: Cons_lb_step_exec => /=.
- destruct e, e'.
destruct evt_a, evt_a0.
simpl in *.
by eapply lb_step_ordered_failure_pt_mapped_simulation_1_non_silent; eauto.
- by rewrite H0 filterMap_app.
- pose s' := Cons e' s0.
rewrite (pt_map_onet_event_Map_unfold s').
exact: c.
Qed.
Lemma pt_map_onet_tot_map_label_event_inf_often_occurred :
forall l s,
inf_often (now (occurred l)) s ->
inf_often (now (occurred (tot_map_label l))) (map pt_map_onet_event s).
Proof using.
move => l.
apply: always_map.
apply: eventually_map.
case => e s.
rewrite /= /occurred /evt_l /=.
move => H_eq.
by rewrite H_eq.
Qed.
Lemma pt_map_onet_tot_map_label_event_inf_often_occurred_conv :
forall l s,
inf_often (now (occurred (tot_map_label l))) (map pt_map_onet_event s) ->
inf_often (now (occurred l)) s.
Proof using tot_map_label_injective.
move => l.
apply: always_map_conv.
apply: eventually_map_conv => //.
- exact: extensional_now.
- exact: extensional_now.
- case => e s.
rewrite /= /occurred /=.
move => H_eq.
exact: tot_map_label_injective.
Qed.
Hypothesis lb_step_ordered_failure_strong_fairness_enabled_pt_map_onet_eventually :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_failure s ->
strong_fairness lb_step_ordered_failure label_silent s ->
enabled lb_step_ordered_failure (tot_map_label l) (pt_map_onet_event (hd s)) ->
eventually (now (enabled lb_step_ordered_failure l)) s.
Lemma pt_map_onet_tot_map_labeled_event_inf_often_enabled :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_failure s ->
strong_fairness lb_step_ordered_failure label_silent s ->
inf_often (now (enabled lb_step_ordered_failure (tot_map_label l))) (map pt_map_onet_event s) ->
inf_often (now (enabled lb_step_ordered_failure l)) s.
Proof using lb_step_ordered_failure_strong_fairness_enabled_pt_map_onet_eventually.
move => l H_neq s H_exec H_fair.
have H_a: ((lb_step_execution lb_step_ordered_failure) /\_ (strong_fairness lb_step_ordered_failure label_silent)) s by auto.
move: H_a {H_exec H_fair}.
apply: always_map_conv_ext => {s}.
rewrite /and_tl /=.
move => x s0 [H_e H_w].
apply lb_step_execution_invar in H_e.
by apply strong_fairness_invar in H_w.
apply: eventually_map_conv_ext.
- exact: extensional_now.
- exact: extensional_now.
- apply extensional_and_tl.
* exact: lb_step_execution_extensional.
* exact: strong_fairness_extensional.
- rewrite /and_tl /=.
move => x s [H_e H_w].
apply lb_step_execution_invar in H_e.
by apply strong_fairness_invar in H_w.
- rewrite /and_tl.
case => /= x s [H_a H_w] H_en.
exact: lb_step_ordered_failure_strong_fairness_enabled_pt_map_onet_eventually.
Qed.
Hypothesis lb_step_ordered_failure_weak_fairness_always_enabled_pt_map_onet_continuously :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
always (now (enabled lb_step_ordered_failure (tot_map_label l))) (map pt_map_onet_event s) ->
continuously (now (enabled lb_step_ordered_failure l)) s.
Lemma pt_map_onet_tot_map_labeled_event_state_continuously_enabled :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
continuously (now (enabled lb_step_ordered_failure (tot_map_label l))) (map pt_map_onet_event s) ->
continuously (now (enabled lb_step_ordered_failure l)) s.
Proof using lb_step_ordered_failure_weak_fairness_always_enabled_pt_map_onet_continuously.
move => l H_neq s H_exec H_fair.
have H_a: ((lb_step_execution lb_step_ordered_failure) /\_ (weak_fairness lb_step_ordered_failure label_silent)) s by auto.
move: H_a {H_exec H_fair}.
apply: eventually_map_conv_ext => {s}.
- apply extensional_always.
exact: extensional_now.
- apply extensional_always.
exact: extensional_now.
- apply extensional_and_tl.
* exact: lb_step_execution_extensional.
* exact: weak_fairness_extensional.
- rewrite /and_tl /=.
move => x s [H_e H_w].
apply lb_step_execution_invar in H_e.
by apply weak_fairness_invar in H_w.
- case => x s [H_a H_w] H_al.
simpl in *.
exact: lb_step_ordered_failure_weak_fairness_always_enabled_pt_map_onet_continuously.
Qed.
Lemma pt_map_onet_tot_map_label_event_strong_fairness :
forall s, lb_step_execution lb_step_ordered_failure s ->
strong_fairness lb_step_ordered_failure label_silent s ->
strong_fairness lb_step_ordered_failure label_silent (map pt_map_onet_event s).
Proof using multi_map_lb_congr lb_step_ordered_failure_strong_fairness_enabled_pt_map_onet_eventually label_tot_mapped.
move => s.
rewrite /strong_fairness => H_exec H_fair l H_neq H_en.
have [l' H_l] := label_tot_mapped l.
rewrite H_l.
apply pt_map_onet_tot_map_label_event_inf_often_occurred.
apply H_fair; first by move => H_eq; rewrite H_eq pt_lb_label_silent_fst_snd in H_l.
rewrite H_l in H_en.
unfold inf_enabled in *.
apply: pt_map_onet_tot_map_labeled_event_inf_often_enabled => //.
move => H_eq.
by rewrite -H_l in H_eq.
Qed.
Lemma pt_map_onet_tot_map_label_event_state_weak_fairness :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_fairness lb_step_ordered_failure label_silent s ->
weak_fairness lb_step_ordered_failure label_silent (map pt_map_onet_event s).
Proof using multi_map_lb_congr lb_step_ordered_failure_weak_fairness_always_enabled_pt_map_onet_continuously label_tot_mapped.
move => s.
rewrite /weak_fairness => H_exec H_fair l H_neq H_en.
have [l' H_l] := label_tot_mapped l.
rewrite H_l.
apply pt_map_onet_tot_map_label_event_inf_often_occurred.
apply H_fair; first by move => H_eq; rewrite H_eq pt_lb_label_silent_fst_snd in H_l.
rewrite H_l in H_en.
unfold cont_enabled in *.
apply: pt_map_onet_tot_map_labeled_event_state_continuously_enabled => //.
move => H_eq.
by rewrite -H_l in H_eq.
Qed.
Context {overlay_fst : NameOverlayParams (@unlabeled_multi_params _ labeled_multi_fst)}.
Context {overlay_snd : NameOverlayParams (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {overlay_map_congr : NameOverlayParamsTotalMapCongruency overlay_fst overlay_snd name_map}.
Context {fail_msg_fst : FailMsgParams (@unlabeled_multi_params _ labeled_multi_fst)}.
Context {fail_msg_snd : FailMsgParams (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {fail_msg_map_congr : FailMsgParamsPartialMapCongruency fail_msg_fst fail_msg_snd msg_map}.
Lemma pt_map_onet_hd_step_ordered_failure_star :
forall e, event_step_star step_ordered_failure step_ordered_failure_init e ->
event_step_star step_ordered_failure step_ordered_failure_init (pt_map_onet_event e).
Proof using overlay_map_congr name_map_bijective multi_map_congr fail_msg_map_congr.
move => e.
rewrite /= /pt_map_onet_event /= /event_step_star /=.
move => H_star.
destruct e, evt_a.
simpl in *.
exact: step_ordered_failure_pt_mapped_simulation_star_1.
Qed.
Lemma pt_map_onet_hd_step_ordered_failure_star_always :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
always (now (event_step_star step_ordered_failure step_ordered_failure_init)) (map pt_map_onet_event s).
Proof using overlay_map_congr name_map_bijective multi_map_lb_congr multi_map_congr label_eq_dec fail_msg_map_congr.
case => e s H_star H_exec.
apply: step_ordered_failure_star_lb_step_execution; first exact: pt_map_onet_hd_step_ordered_failure_star.
exact: lb_step_execution_lb_step_ordered_failure_pt_map_onet_infseq.
Qed.
(* lb_step_ordered_dynamic_failure *)
Theorem lb_step_ordered_dynamic_failure_pt_mapped_simulation_1_non_silent :
forall net net' failed failed' lb tr,
tot_map_label lb <> label_silent ->
@lb_step_ordered_dynamic_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_ordered_dynamic_failure _ labeled_multi_snd (List.map tot_map_name failed, pt_map_odnet net) (tot_map_label lb) (List.map tot_map_name failed', pt_map_odnet net') (filterMap pt_map_trace_ev tr).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_neq H_step.
have H_neq': lb <> label_silent.
rewrite -pt_lb_label_silent_fst_snd in H_neq.
move => H_eq.
by rewrite H_eq in H_neq.
invcs H_step => //=.
- rewrite {2}/pt_map_odnet /=.
case H_m: (@pt_map_msg _ _ _ _ msg_map m) => [m'|]; last first.
have H_q := @pt_lb_net_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr to from _ d H_m.
rewrite /tot_mapped_lb_net_handlers_label in H_q.
repeat break_let.
by tuple_inversion.
apply (@LabeledStepOrderedDynamicFailure_deliver _ _ _ _ _ _ m' (filterMap (@pt_map_msg _ _ _ _ msg_map) ms) (filterMap pt_map_output out) (pt_map_data d) (pt_map_data d') (filterMap (@pt_map_name_msg _ _ _ _ _ msg_map) l) (@tot_map_name _ _ _ _ name_map from) (@tot_map_name _ _ _ _ name_map to)).
* exact: not_in_failed_not_in.
* exact: in_failed_in.
* by rewrite /pt_map_odnet /= tot_map_name_inv_inverse H5.
* by rewrite /pt_map_odnet /= 2!tot_map_name_inv_inverse H6 /= H_m.
* have H_q := @pt_net_handlers_some _ _ _ _ _ _ _ multi_map_congr to from m d _ H_m.
rewrite /pt_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_net_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ _ H_m Heqp1.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
break_and.
by repeat tuple_inversion.
* rewrite {2}/pt_map_odnet /=.
rewrite (@collate_pt_map_update2_eq _ _ _ _ name_map).
set f1 := fun _ => match _ with _ => _ end.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2.
apply functional_extensionality => n.
rewrite /update.
break_if; break_if => //=; first by rewrite -e tot_map_name_inverse_inv in n0.
by rewrite e tot_map_name_inv_inverse in n0.
by rewrite H_eq_f.
* by rewrite (@filterMap_pt_map_trace_ev_outputs_eq _ _ _ _ _ name_map).
- rewrite {2}/pt_map_odnet /=.
case H_i: pt_map_input => [inp'|]; last first.
have H_q := @pt_lb_input_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr h inp d H_i.
rewrite /tot_mapped_lb_input_handlers_label in H_q.
repeat break_let.
by tuple_inversion.
apply (@LabeledStepOrderedDynamicFailure_input _ _ (@tot_map_name _ _ _ _ name_map h) _ _ _ _ (filterMap pt_map_output out) inp' (pt_map_data d) (pt_map_data d') (filterMap (@pt_map_name_msg _ _ _ _ _ msg_map) l)).
* exact: not_in_failed_not_in.
* exact: in_failed_in.
* by rewrite /pt_map_odnet /= tot_map_name_inv_inverse H5.
* have H_q := @pt_input_handlers_some _ _ _ _ _ _ _ multi_map_congr h inp d _ H_i.
rewrite /pt_mapped_input_handlers /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_input_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ H_i Heqp1.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
break_and.
by repeat tuple_inversion.
* rewrite {2}/pt_map_odnet /=.
rewrite (@collate_pt_map_eq _ _ _ _ name_map).
set f1 := fun _ => match _ with _ => _ end.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2.
apply functional_extensionality => n.
rewrite /update.
break_if; break_if => //=; first by rewrite -e tot_map_name_inverse_inv in n0.
by rewrite e tot_map_name_inv_inverse in n0.
by rewrite H_eq_f.
* by rewrite (@filterMap_pt_map_trace_ev_outputs_eq _ _ _ _ _ name_map).
Qed.
Theorem lb_step_ordered_dynamic_failure_pt_mapped_simulation_1_silent :
forall net net' failed failed' lb tr,
tot_map_label lb = label_silent ->
@lb_step_ordered_dynamic_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_ordered_dynamic_failure _ labeled_multi_snd (List.map tot_map_name failed, pt_map_odnet net) label_silent (List.map tot_map_name failed', pt_map_odnet net') [] /\ filterMap pt_map_trace_ev tr = [].
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_eq H_step.
invcs H_step => //=.
- rewrite {2}/pt_map_odnet /=.
case H_m: (@pt_map_msg _ _ _ _ msg_map m) => [m'|].
have H_q := @pt_net_handlers_some _ _ _ _ _ _ _ multi_map_congr to from m d _ H_m.
rewrite /pt_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_net_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ _ H_m Heqp1.
break_and.
unfold tot_mapped_lb_net_handlers_label in *.
repeat break_let.
by repeat tuple_inversion.
have H_q := @pt_net_handlers_none _ _ _ _ _ _ _ multi_map_congr to from m d out d' l H_m.
rewrite /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
concludes.
break_and.
have H_q' := @pt_lb_net_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr to from _ d H_m.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
repeat tuple_inversion.
rewrite /pt_map_odnet /=.
rewrite (@collate_pt_map_update2_eq _ _ _ _ name_map) /=.
rewrite H0 /=.
set p1 := fun _ _ => _.
set p2 := update2 _ _ _ _ _.
set s1 := fun _ => _.
set s2 := fun _ => _.
have H_eq_p: p1 = p2.
rewrite /p1 /p2 /update2.
apply functional_extensionality => src.
apply functional_extensionality => dst.
break_if => //.
break_and.
by rewrite -H2 -H7 2!tot_map_name_inv_inverse H6 /= H_m.
have H_eq_s: s1 = s2.
rewrite /s1 /s2 /update.
apply functional_extensionality => n.
break_if => //.
by rewrite e H5 H.
rewrite H_eq_p H_eq_s.
split; first exact: LabeledStepOrderedDynamicFailure_stutter.
rewrite (@filterMap_pt_map_trace_ev_outputs_eq _ _ _ _ _ name_map).
by repeat find_rewrite.
- case H_i: (pt_map_input inp) => [inp'|].
have H_q := @pt_input_handlers_some _ _ _ _ _ _ _ multi_map_congr h _ d _ H_i.
rewrite /pt_mapped_input_handlers /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @pt_lb_input_handlers_some _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ H_i Heqp1.
break_and.
unfold tot_mapped_lb_input_handlers_label in *.
repeat break_let.
by tuple_inversion.
have H_q := @pt_input_handlers_none _ _ _ _ _ _ _ multi_map_congr h _ d out d' l H_i.
rewrite /input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
concludes.
break_and.
have H_q' := @pt_lb_input_handlers_none _ _ _ _ _ _ _ _ multi_map_lb_congr h _ d H_i.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
repeat tuple_inversion.
rewrite /pt_map_odnet /=.
rewrite (@collate_pt_map_eq _ _ _ _ name_map) H0 /=.
set s1 := fun _ => match _ with _ => _ end.
set s2 := fun _ => match _ with _ => _ end.
have H_eq_s: s1 = s2.
rewrite /s1 /s2.
apply functional_extensionality => n.
rewrite /update.
by break_if; first by rewrite e H5 H.
rewrite -H_eq_s /s1 {s1 s2 H_eq_s}.
split; first exact: LabeledStepOrderedDynamicFailure_stutter.
rewrite (@filterMap_pt_map_trace_ev_outputs_eq _ _ _ _ _ name_map).
by repeat find_rewrite.
- split => //; exact: LabeledStepOrderedDynamicFailure_stutter.
Qed.
Definition pt_map_odnet_event e :=
{| evt_a := (List.map tot_map_name (fst e.(evt_a)), pt_map_odnet (snd e.(evt_a))) ;
evt_l := tot_map_label e.(evt_l) ;
evt_trace := filterMap pt_map_trace_ev e.(evt_trace) |}.
Lemma pt_map_odnet_event_Map_unfold : forall s,
Cons (pt_map_odnet_event (hd s)) (map pt_map_odnet_event (tl s)) = map pt_map_odnet_event s.
Proof using.
by move => s; rewrite -map_Cons /= -{3}(recons s).
Qed.
Lemma lb_step_execution_lb_step_ordered_dynamic_failure_pt_map_odnet_infseq : forall s,
lb_step_execution lb_step_ordered_dynamic_failure s ->
lb_step_execution lb_step_ordered_dynamic_failure (map pt_map_odnet_event s).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr label_eq_dec.
cofix c.
move => s H_exec.
rewrite -pt_map_odnet_event_Map_unfold {1}/pt_map_odnet_event /=.
inversion H_exec; subst => /=.
rewrite -pt_map_odnet_event_Map_unfold /= /pt_map_odnet_event /=.
case (label_eq_dec (tot_map_label (evt_l e)) label_silent) => H_eq.
apply: Cons_lb_step_exec => /=.
- rewrite H_eq.
destruct e, e'.
destruct evt_a, evt_a0.
simpl in *.
by eapply lb_step_ordered_dynamic_failure_pt_mapped_simulation_1_silent; eauto.
- destruct e, e'.
destruct evt_a, evt_a0.
simpl in *.
apply (lb_step_ordered_dynamic_failure_pt_mapped_simulation_1_silent H_eq) in H.
break_and.
simpl in *.
rewrite H0 filterMap_app.
by aggressive_rewrite_goal.
- pose s' := Cons e' s0.
rewrite (pt_map_odnet_event_Map_unfold s').
exact: c.
apply: Cons_lb_step_exec => /=.
- destruct e, e'.
destruct evt_a, evt_a0.
simpl in *.
by eapply lb_step_ordered_dynamic_failure_pt_mapped_simulation_1_non_silent; eauto.
- by rewrite H0 filterMap_app.
- pose s' := Cons e' s0.
rewrite (pt_map_odnet_event_Map_unfold s').
exact: c.
Qed.
Lemma pt_map_odnet_tot_map_label_event_inf_often_occurred :
forall l s,
inf_often (now (occurred l)) s ->
inf_often (now (occurred (tot_map_label l))) (map pt_map_odnet_event s).
Proof using.
move => l.
apply: always_map.
apply: eventually_map.
case => e s.
rewrite /= /occurred /evt_l /=.
move => H_eq.
by rewrite H_eq.
Qed.
Lemma pt_map_odnet_tot_map_label_event_inf_often_occurred_conv :
forall l s,
inf_often (now (occurred (tot_map_label l))) (map pt_map_odnet_event s) ->
inf_often (now (occurred l)) s.
Proof using tot_map_label_injective.
move => l.
apply: always_map_conv.
apply: eventually_map_conv => //.
- exact: extensional_now.
- exact: extensional_now.
- case => e s.
rewrite /= /occurred /=.
move => H_eq.
exact: tot_map_label_injective.
Qed.
Hypothesis lb_step_ordered_dynamic_failure_strong_fairness_enabled_pt_map_onet_eventually :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_dynamic_failure s ->
strong_fairness lb_step_ordered_dynamic_failure label_silent s ->
enabled lb_step_ordered_dynamic_failure (tot_map_label l) (pt_map_odnet_event (hd s)) ->
eventually (now (enabled lb_step_ordered_dynamic_failure l)) s.
Lemma pt_map_odnet_tot_map_labeled_event_inf_often_enabled :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_dynamic_failure s ->
strong_fairness lb_step_ordered_dynamic_failure label_silent s ->
inf_often (now (enabled lb_step_ordered_dynamic_failure (tot_map_label l))) (map pt_map_odnet_event s) ->
inf_often (now (enabled lb_step_ordered_dynamic_failure l)) s.
Proof using lb_step_ordered_dynamic_failure_strong_fairness_enabled_pt_map_onet_eventually.
move => l H_neq s H_exec H_fair.
have H_a: ((lb_step_execution lb_step_ordered_dynamic_failure) /\_ (strong_fairness lb_step_ordered_dynamic_failure label_silent)) s by auto.
move: H_a {H_exec H_fair}.
apply: always_map_conv_ext => {s}.
rewrite /and_tl /=.
move => x s0 [H_e H_w].
apply lb_step_execution_invar in H_e.
by apply strong_fairness_invar in H_w.
apply: eventually_map_conv_ext.
- exact: extensional_now.
- exact: extensional_now.
- apply extensional_and_tl.
* exact: lb_step_execution_extensional.
* exact: strong_fairness_extensional.
- rewrite /and_tl /=.
move => x s [H_e H_w].
apply lb_step_execution_invar in H_e.
by apply strong_fairness_invar in H_w.
- rewrite /and_tl.
case => /= x s [H_a H_w] H_en.
exact: lb_step_ordered_dynamic_failure_strong_fairness_enabled_pt_map_onet_eventually.
Qed.
Hypothesis lb_step_ordered_dynamic_failure_weak_fairness_always_enabled_pt_map_onet_continuously :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_dynamic_failure s ->
weak_fairness lb_step_ordered_dynamic_failure label_silent s ->
always (now (enabled lb_step_ordered_dynamic_failure (tot_map_label l))) (map pt_map_odnet_event s) ->
continuously (now (enabled lb_step_ordered_dynamic_failure l)) s.
Lemma pt_map_odnet_tot_map_labeled_event_state_continuously_enabled :
forall l, tot_map_label l <> label_silent ->
forall s, lb_step_execution lb_step_ordered_dynamic_failure s ->
weak_fairness lb_step_ordered_dynamic_failure label_silent s ->
continuously (now (enabled lb_step_ordered_dynamic_failure (tot_map_label l))) (map pt_map_odnet_event s) ->
continuously (now (enabled lb_step_ordered_dynamic_failure l)) s.
Proof using lb_step_ordered_dynamic_failure_weak_fairness_always_enabled_pt_map_onet_continuously.
move => l H_neq s H_exec H_fair.
have H_a: ((lb_step_execution lb_step_ordered_dynamic_failure) /\_ (weak_fairness lb_step_ordered_dynamic_failure label_silent)) s by auto.
move: H_a {H_exec H_fair}.
apply: eventually_map_conv_ext => {s}.
- apply extensional_always.
exact: extensional_now.
- apply extensional_always.
exact: extensional_now.
- apply extensional_and_tl.
* exact: lb_step_execution_extensional.
* exact: weak_fairness_extensional.
- rewrite /and_tl /=.
move => x s [H_e H_w].
apply lb_step_execution_invar in H_e.
by apply weak_fairness_invar in H_w.
- case => x s [H_a H_w] H_al.
simpl in *.
exact: lb_step_ordered_dynamic_failure_weak_fairness_always_enabled_pt_map_onet_continuously.
Qed.
Lemma pt_map_odnet_tot_map_label_event_strong_fairness :
forall s, lb_step_execution lb_step_ordered_dynamic_failure s ->
strong_fairness lb_step_ordered_dynamic_failure label_silent s ->
strong_fairness lb_step_ordered_dynamic_failure label_silent (map pt_map_odnet_event s).
Proof using multi_map_lb_congr lb_step_ordered_dynamic_failure_strong_fairness_enabled_pt_map_onet_eventually label_tot_mapped.
move => s.
rewrite /strong_fairness => H_exec H_fair l H_neq H_en.
have [l' H_l] := label_tot_mapped l.
rewrite H_l.
apply pt_map_odnet_tot_map_label_event_inf_often_occurred.
apply H_fair; first by move => H_eq; rewrite H_eq pt_lb_label_silent_fst_snd in H_l.
rewrite H_l in H_en.
unfold inf_enabled in *.
apply: pt_map_odnet_tot_map_labeled_event_inf_often_enabled => //.
move => H_eq.
by rewrite -H_l in H_eq.
Qed.
Lemma pt_map_odnet_tot_map_label_event_state_weak_fairness :
forall s, lb_step_execution lb_step_ordered_dynamic_failure s ->
weak_fairness lb_step_ordered_dynamic_failure label_silent s ->
weak_fairness lb_step_ordered_dynamic_failure label_silent (map pt_map_odnet_event s).
Proof using multi_map_lb_congr lb_step_ordered_dynamic_failure_weak_fairness_always_enabled_pt_map_onet_continuously label_tot_mapped.
move => s.
rewrite /weak_fairness => H_exec H_fair l H_neq H_en.
have [l' H_l] := label_tot_mapped l.
rewrite H_l.
apply pt_map_odnet_tot_map_label_event_inf_often_occurred.
apply H_fair; first by move => H_eq; rewrite H_eq pt_lb_label_silent_fst_snd in H_l.
rewrite H_l in H_en.
unfold cont_enabled in *.
apply: pt_map_odnet_tot_map_labeled_event_state_continuously_enabled => //.
move => H_eq.
by rewrite -H_l in H_eq.
Qed.
Context {new_msg_fst : NewMsgParams (@unlabeled_multi_params _ labeled_multi_fst)}.
Context {new_msg_snd : NewMsgParams (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {new_msg_map_congr : NewMsgParamsPartialMapCongruency new_msg_fst new_msg_snd msg_map}.
Lemma pt_map_odnet_hd_step_ordered_dynamic_failure_star :
forall e, event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init e ->
event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init (pt_map_odnet_event e).
Proof using overlay_map_congr new_msg_map_congr name_map_bijective multi_map_congr fail_msg_map_congr.
move => e.
rewrite /= /pt_map_odnet_event /= /event_step_star /=.
move => H_star.
break_exists.
destruct e, evt_a.
simpl in *.
exact: step_ordered_dynamic_failure_pt_mapped_simulation_star_1.
Qed.
Lemma pt_map_odnet_hd_step_ordered_dynamic_failure_star_always :
forall s, event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init (hd s) ->
lb_step_execution lb_step_ordered_dynamic_failure s ->
always (now (event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init)) (map pt_map_odnet_event s).
Proof using overlay_map_congr new_msg_map_congr name_map_bijective multi_map_lb_congr multi_map_congr label_eq_dec fail_msg_map_congr.
case => e s H_star H_exec.
apply: step_ordered_dynamic_failure_star_lb_step_execution; first exact: pt_map_odnet_hd_step_ordered_dynamic_failure_star.
exact: lb_step_execution_lb_step_ordered_dynamic_failure_pt_map_odnet_infseq.
Qed.
End PartialMapExecutionSimulations.
|
/*******************************************************************************
* Module: fifo_cross_clocks
* Date:2014-05-20
* Author: Andrey Filippov
* Description: Configurable FIFO with separate read and write clocks
*
* Copyright (c) 2014 Elphel, Inc.
* fifo_cross_clocks.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fifo_cross_clocks.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module fifo_cross_clocks
#(
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4 // >=3
) (
input rst, // async reset, active high (global)
input rrst, // @ posedge rclk - sync reset
input wrst, // @ posedge wclk - sync reset
input rclk, // read clock - positive edge
input wclk, // write clock - positive edge
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output [DATA_WIDTH-1:0] data_out, // output data
output nempty, // FIFO has some data (sync to rclk)
output half_empty // FIFO half full (wclk) -(not more than 5/8 full)
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg [DATA_DEPTH-1:0] raddr;
reg [DATA_DEPTH-1:0] waddr;
reg [DATA_DEPTH-1:0] waddr_gray; //SuppressThisWarning ISExst VivadoSynthesis : MSB(waddr_gray) == MSB(waddr)
reg [DATA_DEPTH-1:0] waddr_gray_rclk;
wire [DATA_DEPTH-1:0] waddr_plus1 = waddr +1;
wire [DATA_DEPTH-1:0] waddr_plus1_gray = waddr_plus1 ^ {1'b0,waddr_plus1[DATA_DEPTH-1:1]};
wire [DATA_DEPTH-1:0] raddr_gray = raddr ^ {1'b0,raddr[DATA_DEPTH-1:1]};
wire [DATA_DEPTH-1:0] raddr_plus1 = raddr +1;
wire [2:0] raddr_plus1_gray_top3 = raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-3] ^ {1'b0,raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-2]};
reg [2:0] raddr_gray_top3; //SuppressThisWarning ISExst VivadoSynthesis : MSB(raddr_gray_top3) == MSB(raddr)
reg [2:0] raddr_gray_top3_wclk;
wire [2:0] raddr_top3_wclk = {
raddr_gray_top3_wclk[2],
raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1],
raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1]^raddr_gray_top3_wclk[0]};
wire [2:0] waddr_top3=waddr[DATA_DEPTH-1:DATA_DEPTH-3];
wire [2:0] addr_diff=waddr_top3[2:0]-raddr_top3_wclk[2:0];
// half-empty does not need to be precise, it uses 3 MSBs of the write address
// converting to Gray code (easy) and then back (can not be done parallel easily).
// Comparing to 1/8'th of the depth with one-bit Gray code error results in uncertainty
// of +/-1/8, so half_empty means "no more than 5/8 full"
assign half_empty=~addr_diff[2];
// False positive in nempty can only happen if
// a) it is transitioning from empty to non-empty due to we pulse
// b) it is transitioning to overrun - too bad already
// false negative - OK, just wait for the next rclk
// assign nempty=waddr_gray_rclk != raddr_gray;
// assign nempty=waddr_gray_rclk[3:0] != raddr_gray[3:0];
assign nempty= (waddr_gray_rclk[3:0] ^ raddr_gray[3:0]) != 4'b0;
assign data_out=ram[raddr];
always @ (posedge wclk or posedge rst) begin
if (rst) waddr <= 0;
else if (wrst) waddr <= 0;
else if (we) waddr <= waddr_plus1;
if (rst) waddr_gray <= 0;
else if (wrst) waddr_gray <= 0;
else if (we) waddr_gray [3:0] <= waddr_plus1_gray[3:0];
end
always @ (posedge rclk or posedge rst) begin
// making rrst set FIFO to empty regardless of current waddr (write should be stopped)
if (rst) raddr <= waddr; // 0;
else if (rrst) raddr <= waddr; // 0;
else if (re) raddr <= raddr_plus1;
if (rst) raddr_gray_top3 <= waddr[DATA_DEPTH-1 -: 3] ^ {1'b0,waddr[DATA_DEPTH-1 -: 2]}; // 0;
else if (rrst) raddr_gray_top3 <= waddr[DATA_DEPTH-1 -: 3] ^ {1'b0,waddr[DATA_DEPTH-1 -: 2]}; // 0;
else if (re) raddr_gray_top3 <= raddr_plus1_gray_top3;
end
always @ (posedge rclk) begin
waddr_gray_rclk[3:0] <= waddr_gray[3:0];
end
always @ (posedge wclk) begin
raddr_gray_top3_wclk[2:0] <= raddr_gray_top3[2:0];
if (we) ram[waddr] <= data_in;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__XNOR2_FUNCTIONAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xnor2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire xnor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKBUF_BEHAVIORAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_BEHAVIORAL_V |
module sdram_tb ();
reg clk, rst;
wire sdram_clk;
wire sdram_cle;
wire sdram_cs;
wire sdram_cas;
wire sdram_ras;
wire sdram_we;
wire sdram_dqm;
wire [1:0] sdram_ba;
wire [12:0] sdram_a;
wire [7:0] sdram_dq;
wire [24:0] addr;
wire rw;
wire [31:0] data_in, data_out;
wire busy;
wire in_valid, out_valid;
wire [7:0] leds;
sdram DUT (
.clk(clk),
.rst(rst),
.sdram_clk(sdram_clk),
.sdram_cle(sdram_cle),
.sdram_cs(sdram_cs),
.sdram_cas(sdram_cas),
.sdram_ras(sdram_ras),
.sdram_we(sdram_we),
.sdram_dqm(sdram_dqm),
.sdram_ba(sdram_ba),
.sdram_a(sdram_a),
.sdram_dq(sdram_dq),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid)
);
ram_test ram_test (
.clk(clk),
.rst(rst),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid),
.leds(leds)
);
initial begin
clk = 1'b0;
rst = 1'b1;
repeat(4) #5 clk = ~clk;
rst = 1'b0;
forever #5 clk = ~clk; // generate a clock
end
always @* begin
end
initial begin
#300000
$finish();
end
endmodule |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Module Name: cpx
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx(/*AUTOARG*/
// Outputs
cpx_io_grant_cx2, cpx_sctag0_grant_cx, cpx_sctag1_grant_cx,
cpx_sctag2_grant_cx, cpx_sctag3_grant_cx, cpx_spc0_data_cx2,
cpx_spc0_data_rdy_cx2, cpx_spc1_data_cx2, cpx_spc1_data_rdy_cx2,
cpx_spc2_data_cx2, cpx_spc2_data_rdy_cx2, cpx_spc3_data_cx2,
cpx_spc3_data_rdy_cx2, cpx_spc4_data_cx2, cpx_spc4_data_rdy_cx2,
cpx_spc5_data_cx2, cpx_spc5_data_rdy_cx2, cpx_spc6_data_cx2,
cpx_spc6_data_rdy_cx2, cpx_spc7_data_cx2, cpx_spc7_data_rdy_cx2,
cpx_dp_half_array_odd_so_0, cpx_arb7_so_1, pt1_so_1,
cpx_buf_top_pt0_so_1,
// Inputs
si_1, si_0, se_buf6_middle, se_buf5_middle, se_buf4_top,
se_buf4_middle, se_buf4_bottom, se_buf3_top, se_buf3_middle,
se_buf2_top, se_buf2_bottom, se_buf1_top, se_buf1_bottom,
se_buf0_middle, sctag3_cpx_req_cq, sctag3_cpx_atom_cq,
sctag2_cpx_req_cq, sctag2_cpx_atom_cq, sctag1_cpx_req_cq,
sctag1_cpx_atom_cq, sctag0_cpx_req_cq, sctag0_cpx_atom_cq,
rst_l_buf6_middle, rst_l_buf5_middle, rst_l_buf4_middle,
rst_l_buf3_middle, rclk, pcx_scache2_dat_px2_so_1,
pcx_scache1_dat_px2_so_1, io_cpx_req_cq, fp_cpx_req_cq,
adbginit_l_buf6_middle, adbginit_l_buf5_middle,
adbginit_l_buf4_middle, adbginit_l_buf3_middle,
sctag3_cpx_data_ca, sctag2_cpx_data_ca, sctag1_cpx_data_ca,
sctag0_cpx_data_ca, io_cpx_data_ca, fp_cpx_data_ca
);
// NOTE: remove the following from outputs if output is autogenerated
// io_cpx_data_buf3_ca2; fp_cpx_data_buf_ca; sctag0_cpx_data_buf_ca;
// sctag1_cpx_data_buf_ca; sctag2_cpx_data_buf_ca; sctag3_cpx_data_buf_ca;
/*UTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] cpx_io_grant_cx2; // From buf_top of cpx_buf_top.v
output [7:0] cpx_sctag0_grant_cx; // From buf_top of cpx_buf_top.v
output [7:0] cpx_sctag1_grant_cx; // From buf_top of cpx_buf_top.v
output [7:0] cpx_sctag2_grant_cx; // From buf_top of cpx_buf_top.v
output [7:0] cpx_sctag3_grant_cx; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc0_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc0_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc1_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc1_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc2_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc2_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc3_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc3_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc4_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc4_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc5_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc5_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc6_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc6_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output [`CPX_WIDTH-1:0]cpx_spc7_data_cx2; // From buf_top of cpx_buf_top.v
output cpx_spc7_data_rdy_cx2; // From buf_top of cpx_buf_top.v
output cpx_dp_half_array_odd_so_0;// From cpx_dp_array of cpx_dp_array.v
output cpx_arb7_so_1; // From arb7 of ccx_arbc.v
// End of automatics
output pt1_so_1; // From buf_top of cpx_buf_top.v
output cpx_buf_top_pt0_so_1; // From buf_top of cpx_buf_top.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l_buf3_middle; // To arb6 of ccx_arbc.v, ...
input adbginit_l_buf4_middle; // To arb4 of ccx_arbc.v, ...
input adbginit_l_buf5_middle; // To arb2 of ccx_arbc.v, ...
input adbginit_l_buf6_middle; // To arb0 of ccx_arbc.v, ...
input [7:0] fp_cpx_req_cq; // To buf_top of cpx_buf_top.v
input [7:0] io_cpx_req_cq; // To buf_top of cpx_buf_top.v
input pcx_scache1_dat_px2_so_1;// To arb0 of ccx_arbc.v
input pcx_scache2_dat_px2_so_1;// To buf_top of cpx_buf_top.v
input rclk; // To cpx_dp_array of cpx_dp_array.v, ...
input rst_l_buf3_middle; // To arb6 of ccx_arbc.v, ...
input rst_l_buf4_middle; // To arb4 of ccx_arbc.v, ...
input rst_l_buf5_middle; // To arb2 of ccx_arbc.v, ...
input rst_l_buf6_middle; // To arb0 of ccx_arbc.v, ...
input sctag0_cpx_atom_cq; // To buf_top of cpx_buf_top.v
input [7:0] sctag0_cpx_req_cq; // To buf_top of cpx_buf_top.v
input sctag1_cpx_atom_cq; // To buf_top of cpx_buf_top.v
input [7:0] sctag1_cpx_req_cq; // To buf_top of cpx_buf_top.v
input sctag2_cpx_atom_cq; // To buf_top of cpx_buf_top.v
input [7:0] sctag2_cpx_req_cq; // To buf_top of cpx_buf_top.v
input sctag3_cpx_atom_cq; // To buf_top of cpx_buf_top.v
input [7:0] sctag3_cpx_req_cq; // To buf_top of cpx_buf_top.v
input se_buf0_middle; // To buf_top of cpx_buf_top.v
input se_buf1_bottom; // To cpx_dp_array of cpx_dp_array.v
input se_buf1_top; // To cpx_dp_array of cpx_dp_array.v
input se_buf2_bottom; // To buf_top of cpx_buf_top.v
input se_buf2_top; // To buf_top of cpx_buf_top.v
input se_buf3_middle; // To arb6 of ccx_arbc.v, ...
input se_buf3_top; // To buf_top of cpx_buf_top.v
input se_buf4_bottom; // To buf_top of cpx_buf_top.v
input se_buf4_middle; // To arb4 of ccx_arbc.v, ...
input se_buf4_top; // To buf_top of cpx_buf_top.v
input se_buf5_middle; // To arb2 of ccx_arbc.v, ...
input se_buf6_middle; // To arb0 of ccx_arbc.v, ...
input si_0; // To cpx_dp_array of cpx_dp_array.v
input si_1; // To cpx_dp_array of cpx_dp_array.v
// End of automatics
input [`CPX_WIDTH-1:0]sctag3_cpx_data_ca; // To cpx_dp_array of cpx_dp_array.v
input [`CPX_WIDTH-1:0]sctag2_cpx_data_ca; // To cpx_dp_array of cpx_dp_array.v
input [`CPX_WIDTH-1:0]sctag1_cpx_data_ca; // To cpx_dp_array of cpx_dp_array.v
input [`CPX_WIDTH-1:0]sctag0_cpx_data_ca; // To cpx_dp_array of cpx_dp_array.v
input [`CPX_WIDTH-1:0]io_cpx_data_ca; // To cpx_dp_array of cpx_dp_array.v
input [`CPX_WIDTH-1:0]fp_cpx_data_ca; // To cpx_dp_array of cpx_dp_array.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [5:0] arbcp0_cpxdp_grant_arbbf_ca;// From arb0 of ccx_arbc.v
wire [5:0] arbcp0_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp0_cpxdp_q0_hold_arbbf_ca;// From arb0 of ccx_arbc.v
wire [5:0] arbcp0_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp0_cpxdp_qsel0_arbbf_ca;// From arb0 of ccx_arbc.v
wire [5:0] arbcp0_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp0_cpxdp_qsel1_arbbf_ca;// From arb0 of ccx_arbc.v
wire [5:0] arbcp0_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp0_cpxdp_shift_arbbf_cx;// From arb0 of ccx_arbc.v
wire [5:0] arbcp0_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp1_cpxdp_grant_arbbf_ca;// From arb1 of ccx_arbc.v
wire [5:0] arbcp1_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp1_cpxdp_q0_hold_arbbf_ca;// From arb1 of ccx_arbc.v
wire [5:0] arbcp1_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp1_cpxdp_qsel0_arbbf_ca;// From arb1 of ccx_arbc.v
wire [5:0] arbcp1_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp1_cpxdp_qsel1_arbbf_ca;// From arb1 of ccx_arbc.v
wire [5:0] arbcp1_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp1_cpxdp_shift_arbbf_cx;// From arb1 of ccx_arbc.v
wire [5:0] arbcp1_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp2_cpxdp_grant_arbbf_ca;// From arb2 of ccx_arbc.v
wire [5:0] arbcp2_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp2_cpxdp_q0_hold_arbbf_ca;// From arb2 of ccx_arbc.v
wire [5:0] arbcp2_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp2_cpxdp_qsel0_arbbf_ca;// From arb2 of ccx_arbc.v
wire [5:0] arbcp2_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp2_cpxdp_qsel1_arbbf_ca;// From arb2 of ccx_arbc.v
wire [5:0] arbcp2_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp2_cpxdp_shift_arbbf_cx;// From arb2 of ccx_arbc.v
wire [5:0] arbcp2_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp3_cpxdp_grant_arbbf_ca;// From arb3 of ccx_arbc.v
wire [5:0] arbcp3_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp3_cpxdp_q0_hold_arbbf_ca;// From arb3 of ccx_arbc.v
wire [5:0] arbcp3_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp3_cpxdp_qsel0_arbbf_ca;// From arb3 of ccx_arbc.v
wire [5:0] arbcp3_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp3_cpxdp_qsel1_arbbf_ca;// From arb3 of ccx_arbc.v
wire [5:0] arbcp3_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp3_cpxdp_shift_arbbf_cx;// From arb3 of ccx_arbc.v
wire [5:0] arbcp3_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp4_cpxdp_grant_arbbf_ca;// From arb4 of ccx_arbc.v
wire [5:0] arbcp4_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp4_cpxdp_q0_hold_arbbf_ca;// From arb4 of ccx_arbc.v
wire [5:0] arbcp4_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp4_cpxdp_qsel0_arbbf_ca;// From arb4 of ccx_arbc.v
wire [5:0] arbcp4_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp4_cpxdp_qsel1_arbbf_ca;// From arb4 of ccx_arbc.v
wire [5:0] arbcp4_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp4_cpxdp_shift_arbbf_cx;// From arb4 of ccx_arbc.v
wire [5:0] arbcp4_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp5_cpxdp_grant_arbbf_ca;// From arb5 of ccx_arbc.v
wire [5:0] arbcp5_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp5_cpxdp_q0_hold_arbbf_ca;// From arb5 of ccx_arbc.v
wire [5:0] arbcp5_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp5_cpxdp_qsel0_arbbf_ca;// From arb5 of ccx_arbc.v
wire [5:0] arbcp5_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp5_cpxdp_qsel1_arbbf_ca;// From arb5 of ccx_arbc.v
wire [5:0] arbcp5_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp5_cpxdp_shift_arbbf_cx;// From arb5 of ccx_arbc.v
wire [5:0] arbcp5_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp6_cpxdp_grant_arbbf_ca;// From arb6 of ccx_arbc.v
wire [5:0] arbcp6_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp6_cpxdp_q0_hold_arbbf_ca;// From arb6 of ccx_arbc.v
wire [5:0] arbcp6_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp6_cpxdp_qsel0_arbbf_ca;// From arb6 of ccx_arbc.v
wire [5:0] arbcp6_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp6_cpxdp_qsel1_arbbf_ca;// From arb6 of ccx_arbc.v
wire [5:0] arbcp6_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp6_cpxdp_shift_arbbf_cx;// From arb6 of ccx_arbc.v
wire [5:0] arbcp6_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp7_cpxdp_grant_arbbf_ca;// From arb7 of ccx_arbc.v
wire [5:0] arbcp7_cpxdp_grant_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp7_cpxdp_q0_hold_arbbf_ca;// From arb7 of ccx_arbc.v
wire [5:0] arbcp7_cpxdp_q0_hold_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp7_cpxdp_qsel0_arbbf_ca;// From arb7 of ccx_arbc.v
wire [5:0] arbcp7_cpxdp_qsel0_ca; // From buf_top of cpx_buf_top.v
wire [5:0] arbcp7_cpxdp_qsel1_arbbf_ca;// From arb7 of ccx_arbc.v
wire [5:0] arbcp7_cpxdp_qsel1_ca_l;// From buf_top of cpx_buf_top.v
wire [5:0] arbcp7_cpxdp_shift_arbbf_cx;// From arb7 of ccx_arbc.v
wire [5:0] arbcp7_cpxdp_shift_cx; // From buf_top of cpx_buf_top.v
wire cpx_arb0_so_1; // From arb0 of ccx_arbc.v
wire cpx_arb1_so_1; // From arb1 of ccx_arbc.v
wire cpx_arb2_so_1; // From arb2 of ccx_arbc.v
wire cpx_arb3_so_1; // From arb3 of ccx_arbc.v
wire cpx_arb4_so_1; // From arb4 of ccx_arbc.v
wire cpx_arb5_so_1; // From arb5 of ccx_arbc.v
wire cpx_arb6_so_1; // From arb6 of ccx_arbc.v
wire cpx_dp_half_array_even_so_1;// From cpx_dp_array of cpx_dp_array.v
wire [7:0] cpx_io_grant_ca; // From arb0 of ccx_arbc.v, ...
wire [7:0] cpx_scache0_grant_ca; // From arb0 of ccx_arbc.v, ...
wire [7:0] cpx_scache1_grant_ca; // From arb0 of ccx_arbc.v, ...
wire [7:0] cpx_scache2_grant_ca; // From arb0 of ccx_arbc.v, ...
wire [7:0] cpx_scache3_grant_ca; // From arb0 of ccx_arbc.v, ...
wire [`CPX_WIDTH-1:0]cpx_spc0_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc0_data_rdy_cx; // From arb0 of ccx_arbc.v
wire [`CPX_WIDTH-1:0]cpx_spc1_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc1_data_rdy_cx; // From arb1 of ccx_arbc.v
wire [`CPX_WIDTH-1:0]cpx_spc2_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc2_data_rdy_cx; // From arb2 of ccx_arbc.v
wire [`CPX_WIDTH-1:0]cpx_spc3_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc3_data_rdy_cx; // From arb3 of ccx_arbc.v
wire [`CPX_WIDTH-1:0]cpx_spc4_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc4_data_rdy_cx; // From arb4 of ccx_arbc.v
wire [`CPX_WIDTH-1:0]cpx_spc5_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc5_data_rdy_cx; // From arb5 of ccx_arbc.v
wire [`CPX_WIDTH-1:0]cpx_spc6_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc6_data_rdy_cx; // From arb6 of ccx_arbc.v
wire [`CPX_WIDTH-1:0]cpx_spc7_data_cx_l; // From cpx_dp_array of cpx_dp_array.v
wire cpx_spc7_data_rdy_cx; // From arb7 of ccx_arbc.v
wire [7:0] fp_cpx_req_bufp1_cq; // From buf_top of cpx_buf_top.v
wire [7:0] io_cpx_req_buf1_io_cq; // From buf_top of cpx_buf_top.v
wire [7:0] io_cpx_req_bufp3_cq; // From buf_top of cpx_buf_top.v
wire scache0_cpx_atom_bufp1_cq;// From buf_top of cpx_buf_top.v
wire [7:0] scache0_cpx_req_bufp1_cq;// From buf_top of cpx_buf_top.v
wire scache1_cpx_atom_bufpm_cq;// From buf_top of cpx_buf_top.v
wire [7:0] scache1_cpx_req_bufpm_cq;// From buf_top of cpx_buf_top.v
wire scache2_cpx_atom_bufpm_cq;// From buf_top of cpx_buf_top.v
wire [7:0] scache2_cpx_req_bufpm_cq;// From buf_top of cpx_buf_top.v
wire scache3_cpx_atom_bufp3_cq;// From buf_top of cpx_buf_top.v
wire [7:0] scache3_cpx_req_bufp3_cq;// From buf_top of cpx_buf_top.v
// End of automatics
wire [`CPX_WIDTH-1:0] io_cpx_data_buf1_ca2;
wire [`CPX_WIDTH-1:0] fp_cpx_data_buf_ca;
wire [`CPX_WIDTH-1:0] sctag0_cpx_data_buf_ca;
wire [`CPX_WIDTH-1:0] sctag1_cpx_data_buf_ca;
wire [`CPX_WIDTH-1:0] sctag2_cpx_data_buf_ca;
wire [`CPX_WIDTH-1:0] sctag3_cpx_data_buf_ca;
/*
cpx_dp_array AUTO_TEMPLATE(
.arbcp0_cpxdp_q0_hold_ca(arbcp0_cpxdp_q0_hold_ca_l[5:0]),
.arbcp1_cpxdp_q0_hold_ca(arbcp1_cpxdp_q0_hold_ca_l[5:0]),
.arbcp2_cpxdp_q0_hold_ca(arbcp2_cpxdp_q0_hold_ca_l[5:0]),
.arbcp3_cpxdp_q0_hold_ca(arbcp3_cpxdp_q0_hold_ca_l[5:0]),
.arbcp4_cpxdp_q0_hold_ca(arbcp4_cpxdp_q0_hold_ca_l[5:0]),
.arbcp5_cpxdp_q0_hold_ca(arbcp5_cpxdp_q0_hold_ca_l[5:0]),
.arbcp6_cpxdp_q0_hold_ca(arbcp6_cpxdp_q0_hold_ca_l[5:0]),
.arbcp7_cpxdp_q0_hold_ca(arbcp7_cpxdp_q0_hold_ca_l[5:0]),
.arbcp0_cpxdp_qsel1_ca(arbcp0_cpxdp_qsel1_ca_l[5:0]),
.arbcp1_cpxdp_qsel1_ca(arbcp1_cpxdp_qsel1_ca_l[5:0]),
.arbcp2_cpxdp_qsel1_ca(arbcp2_cpxdp_qsel1_ca_l[5:0]),
.arbcp3_cpxdp_qsel1_ca(arbcp3_cpxdp_qsel1_ca_l[5:0]),
.arbcp4_cpxdp_qsel1_ca(arbcp4_cpxdp_qsel1_ca_l[5:0]),
.arbcp5_cpxdp_qsel1_ca(arbcp5_cpxdp_qsel1_ca_l[5:0]),
.arbcp6_cpxdp_qsel1_ca(arbcp6_cpxdp_qsel1_ca_l[5:0]),
.arbcp7_cpxdp_qsel1_ca(arbcp7_cpxdp_qsel1_ca_l[5:0]),
.fp_cpx_data_ca(fp_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.io_cpx_data_ca(io_cpx_data_buf1_ca2[`CPX_WIDTH-1:0]),
.scache0_cpx_data_ca(sctag0_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.scache1_cpx_data_ca(sctag1_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.scache2_cpx_data_ca(sctag2_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.scache3_cpx_data_ca(sctag3_cpx_data_buf_ca[`CPX_WIDTH-1:0]));
*/
cpx_dp_array cpx_dp_array(/*AUTOINST*/
// Outputs
.cpx_dp_half_array_even_so_1(cpx_dp_half_array_even_so_1),
.cpx_dp_half_array_odd_so_0(cpx_dp_half_array_odd_so_0),
.cpx_spc0_data_cx_l(cpx_spc0_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc1_data_cx_l(cpx_spc1_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc2_data_cx_l(cpx_spc2_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc3_data_cx_l(cpx_spc3_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc4_data_cx_l(cpx_spc4_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc5_data_cx_l(cpx_spc5_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc6_data_cx_l(cpx_spc6_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc7_data_cx_l(cpx_spc7_data_cx_l[`CPX_WIDTH-1:0]),
// Inputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[5:0]),
.arbcp0_cpxdp_q0_hold_ca(arbcp0_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[5:0]),
.arbcp0_cpxdp_qsel1_ca(arbcp0_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[5:0]),
.arbcp1_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[5:0]),
.arbcp1_cpxdp_q0_hold_ca(arbcp1_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp1_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[5:0]),
.arbcp1_cpxdp_qsel1_ca(arbcp1_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp1_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[5:0]),
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[5:0]),
.arbcp2_cpxdp_q0_hold_ca(arbcp2_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[5:0]),
.arbcp2_cpxdp_qsel1_ca(arbcp2_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[5:0]),
.arbcp3_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[5:0]),
.arbcp3_cpxdp_q0_hold_ca(arbcp3_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp3_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[5:0]),
.arbcp3_cpxdp_qsel1_ca(arbcp3_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp3_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[5:0]),
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[5:0]),
.arbcp4_cpxdp_q0_hold_ca(arbcp4_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[5:0]),
.arbcp4_cpxdp_qsel1_ca(arbcp4_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[5:0]),
.arbcp5_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[5:0]),
.arbcp5_cpxdp_q0_hold_ca(arbcp5_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp5_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[5:0]),
.arbcp5_cpxdp_qsel1_ca(arbcp5_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp5_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[5:0]),
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[5:0]),
.arbcp6_cpxdp_q0_hold_ca(arbcp6_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[5:0]),
.arbcp6_cpxdp_qsel1_ca(arbcp6_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[5:0]),
.arbcp7_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[5:0]),
.arbcp7_cpxdp_q0_hold_ca(arbcp7_cpxdp_q0_hold_ca_l[5:0]), // Templated
.arbcp7_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[5:0]),
.arbcp7_cpxdp_qsel1_ca(arbcp7_cpxdp_qsel1_ca_l[5:0]), // Templated
.arbcp7_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[5:0]),
.fp_cpx_data_ca(fp_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
.io_cpx_data_ca(io_cpx_data_buf1_ca2[`CPX_WIDTH-1:0]), // Templated
.rclk (rclk),
.scache0_cpx_data_ca(sctag0_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
.scache1_cpx_data_ca(sctag1_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
.scache2_cpx_data_ca(sctag2_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
.scache3_cpx_data_ca(sctag3_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
.se_buf1_bottom(se_buf1_bottom),
.se_buf1_top(se_buf1_top),
.si_0 (si_0),
.si_1 (si_1));
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb@_so_1),
// Inputs
.reset_l (rst_l_buf6_middle),
.adbginit_l (adbginit_l_buf6_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (pcx_scache1_dat_px2_so_1),
.se (se_buf6_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb0(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[0]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[0]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[0]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[0]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[0]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc0_data_rdy_cx), // Templated
.scan_out (cpx_arb0_so_1), // Templated
.arb_dp_grant_a (arbcp0_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp0_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp0_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp0_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp0_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf6_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf6_middle), // Templated
.scan_in (pcx_scache1_dat_px2_so_1), // Templated
.se (se_buf6_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[0]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[0]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[0]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[0]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[0]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[0])); // Templated
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb1_so_1),
// Inputs
.reset_l (rst_l_buf6_middle),
.adbginit_l (adbginit_l_buf6_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (cpx_arb0_so_1),
.se (se_buf6_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb1(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[1]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[1]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[1]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[1]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[1]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc1_data_rdy_cx), // Templated
.scan_out (cpx_arb1_so_1), // Templated
.arb_dp_grant_a (arbcp1_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp1_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp1_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp1_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp1_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf6_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf6_middle), // Templated
.scan_in (cpx_arb0_so_1), // Templated
.se (se_buf6_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[1]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[1]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[1]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[1]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[1]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[1])); // Templated
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb2_so_1),
// Inputs
.reset_l (rst_l_buf5_middle),
.adbginit_l (adbginit_l_buf5_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (cpx_arb1_so_1),
.se (se_buf5_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb2(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[2]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[2]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[2]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[2]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[2]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc2_data_rdy_cx), // Templated
.scan_out (cpx_arb2_so_1), // Templated
.arb_dp_grant_a (arbcp2_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp2_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp2_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp2_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp2_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf5_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf5_middle), // Templated
.scan_in (cpx_arb1_so_1), // Templated
.se (se_buf5_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[2]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[2]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[2]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[2]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[2]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[2])); // Templated
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb3_so_1),
// Inputs
.reset_l (rst_l_buf5_middle),
.adbginit_l (adbginit_l_buf5_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (cpx_arb2_so_1),
.se (se_buf5_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb3(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[3]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[3]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[3]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[3]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[3]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc3_data_rdy_cx), // Templated
.scan_out (cpx_arb3_so_1), // Templated
.arb_dp_grant_a (arbcp3_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp3_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp3_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp3_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp3_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf5_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf5_middle), // Templated
.scan_in (cpx_arb2_so_1), // Templated
.se (se_buf5_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[3]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[3]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[3]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[3]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[3]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[3])); // Templated
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb4_so_1),
// Inputs
.reset_l (rst_l_buf4_middle),
.adbginit_l (adbginit_l_buf4_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (cpx_arb3_so_1),
.se (se_buf4_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb4(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[4]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[4]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[4]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[4]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[4]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc4_data_rdy_cx), // Templated
.scan_out (cpx_arb4_so_1), // Templated
.arb_dp_grant_a (arbcp4_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp4_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp4_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp4_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp4_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf4_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf4_middle), // Templated
.scan_in (cpx_arb3_so_1), // Templated
.se (se_buf4_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[4]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[4]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[4]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[4]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[4]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[4])); // Templated
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb5_so_1),
// Inputs
.reset_l (rst_l_buf4_middle),
.adbginit_l (adbginit_l_buf4_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (cpx_arb4_so_1),
.se (se_buf4_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb5(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[5]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[5]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[5]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[5]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[5]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc5_data_rdy_cx), // Templated
.scan_out (cpx_arb5_so_1), // Templated
.arb_dp_grant_a (arbcp5_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp5_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp5_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp5_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp5_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf4_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf4_middle), // Templated
.scan_in (cpx_arb4_so_1), // Templated
.se (se_buf4_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[5]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[5]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[5]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[5]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[5]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[5])); // Templated
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb6_so_1),
// Inputs
.reset_l (rst_l_buf3_middle),
.adbginit_l (adbginit_l_buf3_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (cpx_arb5_so_1),
.se (se_buf3_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb6(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[6]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[6]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[6]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[6]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[6]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc6_data_rdy_cx), // Templated
.scan_out (cpx_arb6_so_1), // Templated
.arb_dp_grant_a (arbcp6_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp6_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp6_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp6_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp6_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf3_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf3_middle), // Templated
.scan_in (cpx_arb5_so_1), // Templated
.se (se_buf3_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[6]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[6]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[6]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[6]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[6]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[6])); // Templated
/*
ccx_arbc AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbcp@_cpxdp_grant_arbbf_ca[5:0]),
.arb_dp_q0_hold_a (arbcp@_cpxdp_q0_hold_arbbf_ca[5:0]),
.arb_dp_qsel0_a (arbcp@_cpxdp_qsel0_arbbf_ca[5:0]),
.arb_dp_qsel1_a (arbcp@_cpxdp_qsel1_arbbf_ca[5:0]),
.arb_dp_shift_x (arbcp@_cpxdp_shift_arbbf_cx[5:0]),
.arb_src0_grant_a (cpx_scache0_grant_ca[@]),
.arb_src1_grant_a (cpx_scache1_grant_ca[@]),
.arb_src2_grant_a (cpx_scache2_grant_ca[@]),
.arb_src3_grant_a (cpx_scache3_grant_ca[@]),
.arb_src4_grant_a (cpx_io_grant_ca[@]),
.arb_src5_grant_a (),
.ccx_dest_data_rdy_x (cpx_spc@_data_rdy_cx),
.scan_out (cpx_arb7_so_1),
// Inputs
.reset_l (rst_l_buf3_middle),
.adbginit_l (adbginit_l_buf3_middle),
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq),
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[@]),
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq),
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[@]),
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq),
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[@]),
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq),
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[@]),
.src4_arb_atom_q (1'b0),
.src4_arb_req_q (io_cpx_req_buf1_io_cq[@]),
.src5_arb_atom_q (1'b0),
.src5_arb_req_q (fp_cpx_req_bufp1_cq[@]),
.scan_in (cpx_arb6_so_1),
.se (se_buf3_middle),
//.tmb_l (tmb_l));
*/
ccx_arbc arb7(/*AUTOINST*/
// Outputs
.arb_src0_grant_a (cpx_scache0_grant_ca[7]), // Templated
.arb_src1_grant_a (cpx_scache1_grant_ca[7]), // Templated
.arb_src2_grant_a (cpx_scache2_grant_ca[7]), // Templated
.arb_src3_grant_a (cpx_scache3_grant_ca[7]), // Templated
.arb_src4_grant_a (cpx_io_grant_ca[7]), // Templated
.arb_src5_grant_a (), // Templated
.ccx_dest_data_rdy_x (cpx_spc7_data_rdy_cx), // Templated
.scan_out (cpx_arb7_so_1), // Templated
.arb_dp_grant_a (arbcp7_cpxdp_grant_arbbf_ca[5:0]), // Templated
.arb_dp_q0_hold_a (arbcp7_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arb_dp_qsel0_a (arbcp7_cpxdp_qsel0_arbbf_ca[5:0]), // Templated
.arb_dp_qsel1_a (arbcp7_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arb_dp_shift_x (arbcp7_cpxdp_shift_arbbf_cx[5:0]), // Templated
// Inputs
.adbginit_l (adbginit_l_buf3_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf3_middle), // Templated
.scan_in (cpx_arb6_so_1), // Templated
.se (se_buf3_middle), // Templated
.src0_arb_atom_q (scache0_cpx_atom_bufp1_cq), // Templated
.src0_arb_req_q (scache0_cpx_req_bufp1_cq[7]), // Templated
.src1_arb_atom_q (scache1_cpx_atom_bufpm_cq), // Templated
.src1_arb_req_q (scache1_cpx_req_bufpm_cq[7]), // Templated
.src2_arb_atom_q (scache2_cpx_atom_bufpm_cq), // Templated
.src2_arb_req_q (scache2_cpx_req_bufpm_cq[7]), // Templated
.src3_arb_atom_q (scache3_cpx_atom_bufp3_cq), // Templated
.src3_arb_req_q (scache3_cpx_req_bufp3_cq[7]), // Templated
.src4_arb_atom_q (1'b0), // Templated
.src4_arb_req_q (io_cpx_req_buf1_io_cq[7]), // Templated
.src5_arb_atom_q (1'b0), // Templated
.src5_arb_req_q (fp_cpx_req_bufp1_cq[7])); // Templated
/*
cpx_buf_top AUTO_TEMPLATE(
//.se(shiftenable),
.si_1(cpx_dp_half_array_even_so_1),
.scache0_cpx_atom_cq(sctag0_cpx_atom_cq),
.scache0_cpx_req_cq(sctag0_cpx_req_cq[7:0]),
.scache1_cpx_atom_cq(sctag1_cpx_atom_cq),
.scache1_cpx_req_cq(sctag1_cpx_req_cq[7:0]),
.scache2_cpx_atom_cq(sctag2_cpx_atom_cq),
.scache2_cpx_req_cq(sctag2_cpx_req_cq[7:0]),
.scache3_cpx_atom_cq(sctag3_cpx_atom_cq),
.scache3_cpx_req_cq(sctag3_cpx_req_cq[7:0]),
.arbcp0_cpxdp_q0_hold_arbbf_ca_l(arbcp0_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp1_cpxdp_q0_hold_arbbf_ca_l(arbcp1_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp2_cpxdp_q0_hold_arbbf_ca_l(arbcp2_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp3_cpxdp_q0_hold_arbbf_ca_l(arbcp3_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp4_cpxdp_q0_hold_arbbf_ca_l(arbcp4_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp5_cpxdp_q0_hold_arbbf_ca_l(arbcp5_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp6_cpxdp_q0_hold_arbbf_ca_l(arbcp6_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp7_cpxdp_q0_hold_arbbf_ca_l(arbcp7_cpxdp_q0_hold_arbbf_ca[5:0]),
.arbcp0_cpxdp_qsel1_arbbf_ca_l(arbcp0_cpxdp_qsel1_arbbf_ca[5:0]),
.arbcp1_cpxdp_qsel1_arbbf_ca_l(arbcp1_cpxdp_qsel1_arbbf_ca[5:0]),
.arbcp2_cpxdp_qsel1_arbbf_ca_l(arbcp2_cpxdp_qsel1_arbbf_ca[5:0]),
.arbcp3_cpxdp_qsel1_arbbf_ca_l(arbcp3_cpxdp_qsel1_arbbf_ca[5:0]),
.arbcp4_cpxdp_qsel1_arbbf_ca_l(arbcp4_cpxdp_qsel1_arbbf_ca[5:0]),
.arbcp5_cpxdp_qsel1_arbbf_ca_l(arbcp5_cpxdp_qsel1_arbbf_ca[5:0]),
.arbcp6_cpxdp_qsel1_arbbf_ca_l(arbcp6_cpxdp_qsel1_arbbf_ca[5:0]),
.arbcp7_cpxdp_qsel1_arbbf_ca_l(arbcp7_cpxdp_qsel1_arbbf_ca[5:0]),
.cpx_scache0_grant_cx(cpx_sctag0_grant_cx[7:0]),
.cpx_scache1_grant_cx(cpx_sctag1_grant_cx[7:0]),
.cpx_scache2_grant_cx(cpx_sctag2_grant_cx[7:0]),
.cpx_scache3_grant_cx(cpx_sctag3_grant_cx[7:0]));
*/
cpx_buf_top buf_top(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[5:0]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[5:0]),
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[5:0]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[5:0]),
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[5:0]),
.arbcp1_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[5:0]),
.arbcp1_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[5:0]),
.arbcp1_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[5:0]),
.arbcp1_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[5:0]),
.arbcp1_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[5:0]),
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[5:0]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[5:0]),
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[5:0]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[5:0]),
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[5:0]),
.arbcp3_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[5:0]),
.arbcp3_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[5:0]),
.arbcp3_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[5:0]),
.arbcp3_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[5:0]),
.arbcp3_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[5:0]),
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[5:0]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[5:0]),
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[5:0]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[5:0]),
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[5:0]),
.arbcp5_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[5:0]),
.arbcp5_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[5:0]),
.arbcp5_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[5:0]),
.arbcp5_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[5:0]),
.arbcp5_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[5:0]),
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[5:0]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[5:0]),
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[5:0]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[5:0]),
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[5:0]),
.arbcp7_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[5:0]),
.arbcp7_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[5:0]),
.arbcp7_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[5:0]),
.arbcp7_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[5:0]),
.arbcp7_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[5:0]),
.cpx_buf_top_pt0_so_1(cpx_buf_top_pt0_so_1),
.cpx_io_grant_cx2(cpx_io_grant_cx2[7:0]),
.cpx_scache0_grant_cx(cpx_sctag0_grant_cx[7:0]), // Templated
.cpx_scache1_grant_cx(cpx_sctag1_grant_cx[7:0]), // Templated
.cpx_scache2_grant_cx(cpx_sctag2_grant_cx[7:0]), // Templated
.cpx_scache3_grant_cx(cpx_sctag3_grant_cx[7:0]), // Templated
.cpx_spc0_data_cx2(cpx_spc0_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc0_data_rdy_cx2(cpx_spc0_data_rdy_cx2),
.cpx_spc1_data_cx2(cpx_spc1_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc1_data_rdy_cx2(cpx_spc1_data_rdy_cx2),
.cpx_spc2_data_cx2(cpx_spc2_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc2_data_rdy_cx2(cpx_spc2_data_rdy_cx2),
.cpx_spc3_data_cx2(cpx_spc3_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc3_data_rdy_cx2(cpx_spc3_data_rdy_cx2),
.cpx_spc4_data_cx2(cpx_spc4_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc4_data_rdy_cx2(cpx_spc4_data_rdy_cx2),
.cpx_spc5_data_cx2(cpx_spc5_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc5_data_rdy_cx2(cpx_spc5_data_rdy_cx2),
.cpx_spc6_data_cx2(cpx_spc6_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc6_data_rdy_cx2(cpx_spc6_data_rdy_cx2),
.cpx_spc7_data_cx2(cpx_spc7_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc7_data_rdy_cx2(cpx_spc7_data_rdy_cx2),
.fp_cpx_data_buf_ca(fp_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.fp_cpx_req_bufp1_cq(fp_cpx_req_bufp1_cq[7:0]),
.io_cpx_data_buf1_ca2(io_cpx_data_buf1_ca2[`CPX_WIDTH-1:0]),
.io_cpx_req_buf1_io_cq(io_cpx_req_buf1_io_cq[7:0]),
.io_cpx_req_bufp3_cq(io_cpx_req_bufp3_cq[7:0]),
.pt1_so_1 (pt1_so_1),
.scache0_cpx_atom_bufp1_cq(scache0_cpx_atom_bufp1_cq),
.scache0_cpx_req_bufp1_cq(scache0_cpx_req_bufp1_cq[7:0]),
.scache1_cpx_atom_bufpm_cq(scache1_cpx_atom_bufpm_cq),
.scache1_cpx_req_bufpm_cq(scache1_cpx_req_bufpm_cq[7:0]),
.scache2_cpx_atom_bufpm_cq(scache2_cpx_atom_bufpm_cq),
.scache2_cpx_req_bufpm_cq(scache2_cpx_req_bufpm_cq[7:0]),
.scache3_cpx_atom_bufp3_cq(scache3_cpx_atom_bufp3_cq),
.scache3_cpx_req_bufp3_cq(scache3_cpx_req_bufp3_cq[7:0]),
.sctag0_cpx_data_buf_ca(sctag0_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.sctag1_cpx_data_buf_ca(sctag1_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.sctag2_cpx_data_buf_ca(sctag2_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.sctag3_cpx_data_buf_ca(sctag3_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca(arbcp0_cpxdp_grant_arbbf_ca[5:0]),
.arbcp0_cpxdp_q0_hold_arbbf_ca_l(arbcp0_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca(arbcp0_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp0_cpxdp_qsel1_arbbf_ca_l(arbcp0_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx(arbcp0_cpxdp_shift_arbbf_cx[5:0]),
.arbcp1_cpxdp_grant_arbbf_ca(arbcp1_cpxdp_grant_arbbf_ca[5:0]),
.arbcp1_cpxdp_q0_hold_arbbf_ca_l(arbcp1_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp1_cpxdp_qsel0_arbbf_ca(arbcp1_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp1_cpxdp_qsel1_arbbf_ca_l(arbcp1_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp1_cpxdp_shift_arbbf_cx(arbcp1_cpxdp_shift_arbbf_cx[5:0]),
.arbcp2_cpxdp_grant_arbbf_ca(arbcp2_cpxdp_grant_arbbf_ca[5:0]),
.arbcp2_cpxdp_q0_hold_arbbf_ca_l(arbcp2_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca(arbcp2_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp2_cpxdp_qsel1_arbbf_ca_l(arbcp2_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx(arbcp2_cpxdp_shift_arbbf_cx[5:0]),
.arbcp3_cpxdp_grant_arbbf_ca(arbcp3_cpxdp_grant_arbbf_ca[5:0]),
.arbcp3_cpxdp_q0_hold_arbbf_ca_l(arbcp3_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp3_cpxdp_qsel0_arbbf_ca(arbcp3_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp3_cpxdp_qsel1_arbbf_ca_l(arbcp3_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp3_cpxdp_shift_arbbf_cx(arbcp3_cpxdp_shift_arbbf_cx[5:0]),
.arbcp4_cpxdp_grant_arbbf_ca(arbcp4_cpxdp_grant_arbbf_ca[5:0]),
.arbcp4_cpxdp_q0_hold_arbbf_ca_l(arbcp4_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca(arbcp4_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp4_cpxdp_qsel1_arbbf_ca_l(arbcp4_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx(arbcp4_cpxdp_shift_arbbf_cx[5:0]),
.arbcp5_cpxdp_grant_arbbf_ca(arbcp5_cpxdp_grant_arbbf_ca[5:0]),
.arbcp5_cpxdp_q0_hold_arbbf_ca_l(arbcp5_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp5_cpxdp_qsel0_arbbf_ca(arbcp5_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp5_cpxdp_qsel1_arbbf_ca_l(arbcp5_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp5_cpxdp_shift_arbbf_cx(arbcp5_cpxdp_shift_arbbf_cx[5:0]),
.arbcp6_cpxdp_grant_arbbf_ca(arbcp6_cpxdp_grant_arbbf_ca[5:0]),
.arbcp6_cpxdp_q0_hold_arbbf_ca_l(arbcp6_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca(arbcp6_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp6_cpxdp_qsel1_arbbf_ca_l(arbcp6_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx(arbcp6_cpxdp_shift_arbbf_cx[5:0]),
.arbcp7_cpxdp_grant_arbbf_ca(arbcp7_cpxdp_grant_arbbf_ca[5:0]),
.arbcp7_cpxdp_q0_hold_arbbf_ca_l(arbcp7_cpxdp_q0_hold_arbbf_ca[5:0]), // Templated
.arbcp7_cpxdp_qsel0_arbbf_ca(arbcp7_cpxdp_qsel0_arbbf_ca[5:0]),
.arbcp7_cpxdp_qsel1_arbbf_ca_l(arbcp7_cpxdp_qsel1_arbbf_ca[5:0]), // Templated
.arbcp7_cpxdp_shift_arbbf_cx(arbcp7_cpxdp_shift_arbbf_cx[5:0]),
.cpx_io_grant_ca (cpx_io_grant_ca[7:0]),
.cpx_scache0_grant_ca(cpx_scache0_grant_ca[7:0]),
.cpx_scache1_grant_ca(cpx_scache1_grant_ca[7:0]),
.cpx_scache2_grant_ca(cpx_scache2_grant_ca[7:0]),
.cpx_scache3_grant_ca(cpx_scache3_grant_ca[7:0]),
.cpx_spc0_data_cx_l(cpx_spc0_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc0_data_rdy_cx(cpx_spc0_data_rdy_cx),
.cpx_spc1_data_cx_l(cpx_spc1_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc1_data_rdy_cx(cpx_spc1_data_rdy_cx),
.cpx_spc2_data_cx_l(cpx_spc2_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc2_data_rdy_cx(cpx_spc2_data_rdy_cx),
.cpx_spc3_data_cx_l(cpx_spc3_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc3_data_rdy_cx(cpx_spc3_data_rdy_cx),
.cpx_spc4_data_cx_l(cpx_spc4_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc4_data_rdy_cx(cpx_spc4_data_rdy_cx),
.cpx_spc5_data_cx_l(cpx_spc5_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc5_data_rdy_cx(cpx_spc5_data_rdy_cx),
.cpx_spc6_data_cx_l(cpx_spc6_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc6_data_rdy_cx(cpx_spc6_data_rdy_cx),
.cpx_spc7_data_cx_l(cpx_spc7_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc7_data_rdy_cx(cpx_spc7_data_rdy_cx),
.fp_cpx_data_ca (fp_cpx_data_ca[`CPX_WIDTH-1:0]),
.fp_cpx_req_cq (fp_cpx_req_cq[7:0]),
.io_cpx_data_ca (io_cpx_data_ca[`CPX_WIDTH-1:0]),
.io_cpx_req_cq (io_cpx_req_cq[7:0]),
.pcx_scache2_dat_px2_so_1(pcx_scache2_dat_px2_so_1),
.rclk (rclk),
.scache0_cpx_atom_cq(sctag0_cpx_atom_cq), // Templated
.scache0_cpx_req_cq(sctag0_cpx_req_cq[7:0]), // Templated
.scache1_cpx_atom_cq(sctag1_cpx_atom_cq), // Templated
.scache1_cpx_req_cq(sctag1_cpx_req_cq[7:0]), // Templated
.scache2_cpx_atom_cq(sctag2_cpx_atom_cq), // Templated
.scache2_cpx_req_cq(sctag2_cpx_req_cq[7:0]), // Templated
.scache3_cpx_atom_cq(sctag3_cpx_atom_cq), // Templated
.scache3_cpx_req_cq(sctag3_cpx_req_cq[7:0]), // Templated
.sctag0_cpx_data_ca(sctag0_cpx_data_ca[`CPX_WIDTH-1:0]),
.sctag1_cpx_data_ca(sctag1_cpx_data_ca[`CPX_WIDTH-1:0]),
.sctag2_cpx_data_ca(sctag2_cpx_data_ca[`CPX_WIDTH-1:0]),
.sctag3_cpx_data_ca(sctag3_cpx_data_ca[`CPX_WIDTH-1:0]),
.se_buf0_middle (se_buf0_middle),
.se_buf2_bottom (se_buf2_bottom),
.se_buf2_top (se_buf2_top),
.se_buf3_top (se_buf3_top),
.se_buf4_bottom (se_buf4_bottom),
.se_buf4_top (se_buf4_top),
.si_1 (cpx_dp_half_array_even_so_1)); // Templated
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../../common/rtl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_TB_V
`define SKY130_FD_SC_MS__O31A_TB_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_TB_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ema
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ema.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ema.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ema
//
// No user `defines in this module
module ema
//
// Generated Module ema_i1
//
(
nreset // Async. Reset (CGU,PAD)
);
// Generated Module Inputs:
input nreset;
// Generated Wires:
wire nreset;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ema
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`include "twi_define.v"
module twi(
// system clock and reset
input CLK_I ,
input RST_I ,
// wishbone interface signals
input TWI_CYC_I ,//NC
input TWI_STB_I ,
input TWI_WE_I ,
input TWI_LOCK_I ,//NC
input [2:0] TWI_CTI_I ,//NC
input [1:0] TWI_BTE_I ,//NC
input [5:0] TWI_ADR_I ,
input [31:0] TWI_DAT_I ,
input [3:0] TWI_SEL_I ,
output reg TWI_ACK_O ,
output TWI_ERR_O ,//const 0
output TWI_RTY_O ,//const 0
output [31:0] TWI_DAT_O ,
output TWI_SCL_O ,
input TWI_SDA_I ,
output TWI_SDA_OEN ,
output PWM ,
output WATCH_DOG ,
output SFT_SHCP ,
output SFT_DS ,
output SFT_STCP ,
output SFT_MR_N ,
output SFT_OE_N ,
input FAN_IN0 ,
input FAN_IN1 ,
output TIME0_INT ,
output TIME1_INT ,
output [3:0] GPIO_OUT ,
input [7:0] GPIO_IN ,
output clk25m_on
);
assign TWI_ERR_O = 1'b0 ;
assign TWI_RTY_O = 1'b0 ;
//-----------------------------------------------------
// WB bus ACK
//-----------------------------------------------------
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
TWI_ACK_O <= 1'b0 ;
else if( TWI_STB_I && (~TWI_ACK_O) )
TWI_ACK_O <= 1'b1 ;
else
TWI_ACK_O <= 1'b0 ;
end
wire i2cr_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `I2CR) & ~TWI_ACK_O ;
wire i2wd_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `I2WD) & ~TWI_ACK_O ;
wire pwm_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `PWMC) & ~TWI_ACK_O ;
wire wdg_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `WDG ) & ~TWI_ACK_O ;
wire sft_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `SFT ) & ~TWI_ACK_O ;
wire time_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `TIME) & ~TWI_ACK_O ;
wire gpio_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `GPIO) & ~TWI_ACK_O ;
wire clko_wr_en = TWI_STB_I & TWI_WE_I & ( TWI_ADR_I == `CLKO) & ~TWI_ACK_O ;
wire i2cr_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `I2CR) & ~TWI_ACK_O ;
wire i2rd_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `I2RD) & ~TWI_ACK_O ;
wire wdg_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `WDG ) & ~TWI_ACK_O ;
wire sft_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `SFT ) & ~TWI_ACK_O ;
wire fan0_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `FAN0) & ~TWI_ACK_O ;
wire fan1_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `FAN1) & ~TWI_ACK_O ;
wire time_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `TIME) & ~TWI_ACK_O ;
wire gpio_rd_en = TWI_STB_I & ~TWI_WE_I & ( TWI_ADR_I == `GPIO) & ~TWI_ACK_O ;
//-----------------------------------------------------
// PWM
//-----------------------------------------------------
reg [9:0] reg_pwm ;
reg [9:0] pwm_cnt ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
reg_pwm <= 10'h00 ;
else if( pwm_wr_en )
reg_pwm <= TWI_DAT_I[9:0] ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
pwm_cnt <= 10'b0 ;
else
pwm_cnt <= pwm_cnt + 10'b1 ;
end
assign PWM = pwm_cnt < reg_pwm ;
//-----------------------------------------------------
// WDG
//-----------------------------------------------------
reg wdg_en ;
reg [25:0] wdg_cnt ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
wdg_en <= 1'b0 ;
else if( wdg_wr_en )
wdg_en <= TWI_DAT_I[0] ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
wdg_cnt <= 26'b0 ;
else if( wdg_wr_en && (wdg_en || TWI_DAT_I[0]) )
wdg_cnt <= TWI_DAT_I[26:1] ;
else if( |wdg_cnt )
wdg_cnt <= wdg_cnt - 1 ;
end
assign WATCH_DOG = wdg_en && (wdg_cnt == 1 || wdg_cnt == 2) ;
//-----------------------------------------------------
// SHIFT
//-----------------------------------------------------
/*
00: Set master reset
01: Shift register
10: Storage register
11: Output Enable
*/
wire sft_done ;
reg sft_done_r ;
wire [31:0] reg_sft = {28'b0,sft_done_r,SFT_OE_N,2'b0} ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
sft_done_r <= 1'b0 ;
else if( sft_wr_en )
sft_done_r <= 1'b0 ;
else if( sft_done )
sft_done_r <= 1'b1 ;
end
shift u_shift(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I ) ,
/*input */ .vld (sft_wr_en ) ,
/*input [1:0]*/ .cmd (TWI_DAT_I[1:0] ) ,
/*input */ .cmd_oen (TWI_DAT_I[2] ) ,
/*input [7:0]*/ .din (TWI_DAT_I[15:8]) ,
/*output */ .done (sft_done ) ,
/*output */ .sft_shcp (SFT_SHCP ) ,
/*output */ .sft_ds (SFT_DS ) ,
/*output */ .sft_stcp (SFT_STCP ) ,
/*output */ .sft_mr_n (SFT_MR_N ) ,
/*output */ .sft_oe_n (SFT_OE_N )
);
//-----------------------------------------------------
// fan speed
//-----------------------------------------------------
reg [26:0] sec_cnt ;//1m
reg [26:0] fan_cnt0 ;
reg [26:0] fan_cnt1 ;
reg [26:0] reg_fan0 ;
reg [26:0] reg_fan1 ;
reg [2:0] fan0_f ;
reg [2:0] fan1_f ;
wire fan0_neg = ~fan0_f[1] && fan0_f[2] ;
wire fan1_neg = ~fan1_f[1] && fan1_f[2] ;
always @ ( posedge CLK_I ) begin
fan0_f <= {fan0_f[1:0],FAN_IN0} ;
fan1_f <= {fan1_f[1:0],FAN_IN1} ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
sec_cnt <= 'b0 ;
else if( sec_cnt == `MM_CLK_1S_CNT )
sec_cnt <= 'b0 ;
else
sec_cnt <= 'b1 + sec_cnt ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
fan_cnt0 <= 'b0 ;
else if( sec_cnt == `MM_CLK_1S_CNT ) begin
fan_cnt0 <= 'b0 ;
reg_fan0 <= fan_cnt0 ;
end else if( fan0_neg )
fan_cnt0 <= fan_cnt0 + 'b1 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
fan_cnt1 <= 'b0 ;
else if( sec_cnt == `MM_CLK_1S_CNT ) begin
fan_cnt1 <= 'b0 ;
reg_fan1 <= fan_cnt1 ;
end else if( fan1_neg )
fan_cnt1 <= fan_cnt1 + 'b1 ;
end
//-----------------------------------------------------
// timer
//-----------------------------------------------------
//1s 2faf080 SEC
reg [26:0] tim_cnt ;
reg [5:0] sec_cnt0 ;
reg [5:0] sec_cnt0_f ;
reg tim_done0 ;
reg [5:0] sec_cnt1 ;
reg [5:0] sec_cnt1_f ;
reg tim_done1 ;
reg tim_mask0 ;
reg tim_mask1 ;
wire [31:0] reg_tim = {7'b0,tim_done1,sec_cnt1,tim_mask1,1'b0,7'b0,tim_done0,sec_cnt0,tim_mask0,1'b0} ;
always @ ( posedge CLK_I ) begin
if( tim_cnt == `MM_CLK_1S_CNT )
tim_cnt <= 'b0 ;
else
tim_cnt <= 'b1 + tim_cnt ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
sec_cnt0 <= 'b0 ;
else if( time_wr_en && TWI_DAT_I[0] )
sec_cnt0 <= TWI_DAT_I[7:2] ;
else if( |sec_cnt0 && tim_cnt == `MM_CLK_1S_CNT )
sec_cnt0 <= sec_cnt0 - 6'b1 ;
end
always @ ( posedge CLK_I ) begin
sec_cnt0_f <= sec_cnt0 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
tim_mask0 <= 1'b1 ;
else if( time_wr_en )
tim_mask0 <= TWI_DAT_I[1] ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
sec_cnt1 <= 'b0 ;
else if( time_wr_en && TWI_DAT_I[16] )
sec_cnt1 <= TWI_DAT_I[23:18] ;
else if( |sec_cnt1 && tim_cnt == `MM_CLK_1S_CNT )
sec_cnt1 <= sec_cnt1 - 6'b1 ;
end
always @ ( posedge CLK_I ) begin
sec_cnt1_f <= sec_cnt1 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
tim_done0 <= 1'b0 ;
else if( sec_cnt0 == 0 && sec_cnt0_f == 1 )
tim_done0 <= 1'b1 ;
else if( time_wr_en && TWI_DAT_I[8] )
tim_done0 <= 1'b0 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
tim_done1 <= 1'b0 ;
else if( sec_cnt1 == 0 && sec_cnt1_f == 1 )
tim_done1 <= 1'b1 ;
else if( time_wr_en && TWI_DAT_I[24] )
tim_done1 <= 1'b0 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
tim_mask1 <= 1'b1 ;
else if( time_wr_en )
tim_mask1 <= TWI_DAT_I[17] ;
end
assign TIME0_INT = ~tim_mask0 && tim_done0 ;
assign TIME1_INT = ~tim_mask1 && tim_done1 ;
//-----------------------------------------------------
// GPIO
//-----------------------------------------------------
reg [3:0] reg_gout ;
reg [7:0] reg_gin ;
wire [31:0] reg_gpio = {20'b0,reg_gin,reg_gout} ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
reg_gout <= 'b0 ;
else if( gpio_wr_en )
reg_gout <= TWI_DAT_I[3:0] ;
end
assign GPIO_OUT = reg_gout ;
always @ ( posedge CLK_I ) begin
reg_gin <= GPIO_IN ;
end
//-----------------------------------------------------
// CLK OUT 25M Enable
//-----------------------------------------------------
reg reg_clk25m_on;
assign clk25m_on = reg_clk25m_on;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
reg_clk25m_on <= 1'b0;
else if(clko_wr_en)
reg_clk25m_on <= TWI_DAT_I[0];
end
//-----------------------------------------------------
// read
//-----------------------------------------------------
reg i2cr_rd_en_r ;
reg wdg_rd_en_r ;
reg sft_rd_en_r ;
reg fan0_rd_en_r ;
reg fan1_rd_en_r ;
reg time_rd_en_r ;
reg gpio_rd_en_r ;
wire [7:0] reg_i2cr ;
wire [7:0] reg_i2rd ;
always @ ( posedge CLK_I ) begin
i2cr_rd_en_r <= i2cr_rd_en ;
wdg_rd_en_r <= wdg_rd_en ;
sft_rd_en_r <= sft_rd_en ;
fan0_rd_en_r <= fan0_rd_en ;
fan1_rd_en_r <= fan1_rd_en ;
time_rd_en_r <= time_rd_en ;
gpio_rd_en_r <= gpio_rd_en ;
end
assign TWI_DAT_O = i2cr_rd_en_r ? {24'b0,reg_i2cr} :
wdg_rd_en_r ? {5'b0,wdg_cnt,wdg_en}:
sft_rd_en_r ? reg_sft :
fan0_rd_en_r ? {6'b0,reg_fan0} :
fan1_rd_en_r ? {6'b0,reg_fan1} :
time_rd_en_r ? reg_tim :
gpio_rd_en_r ? reg_gpio :
{24'b0,reg_i2rd} ;
twi_core twi_core (
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I ) ,
/*input */ .wr (i2cr_wr_en|i2wd_wr_en) , //we
/*input [7:0]*/ .data_in (TWI_DAT_I[7:0] ) ,//dat1
/*input [7:0]*/ .wr_addr ({2'b0,TWI_ADR_I} ) ,//adr1
/*output [7:0]*/ .i2cr (reg_i2cr ) ,
/*output [7:0]*/ .i2rd (reg_i2rd ) ,
/*output */ .twi_scl_o (TWI_SCL_O ) ,
/*input */ .twi_sda_i (TWI_SDA_I ) ,
/*output */ .twi_sda_oen (TWI_SDA_OEN )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor2 (
X ,
A ,
B ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_1_V
`define SKY130_FD_SC_LS__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_BLACKBOX_V
`define SKY130_FD_SC_HD__DFRTN_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_top.v
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file blk_mem_gen_v4_2.v when simulating
// the core, blk_mem_gen_v4_2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module blk_mem_gen_v4_2(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [0 : 0] wea;
input [4 : 0] addra;
input [127 : 0] dina;
output [127 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V4_2 #(
.C_ADDRA_WIDTH(5),
.C_ADDRB_WIDTH(5),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32),
.C_READ_DEPTH_B(32),
.C_READ_WIDTH_A(128),
.C_READ_WIDTH_B(128),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32),
.C_WRITE_DEPTH_B(32),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(128),
.C_WRITE_WIDTH_B(128),
.C_XDEVICEFAMILY("spartan3"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of blk_mem_gen_v4_2 is "black_box"
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_V |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: op_lut_hdr_parser.v
// Project: NF2.1
// Description: Checks if the packet is arriving from the CPU or not
//
///////////////////////////////////////////////////////////////////////////////
module op_lut_hdr_parser
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter NUM_QUEUES = 8,
parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES),
parameter INPUT_ARBITER_STAGE_NUM = 2,
parameter IO_QUEUE_STAGE_NUM = `IO_QUEUE_STAGE_NUM
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
// --- Interface to process block
output is_from_cpu,
output [NUM_QUEUES-1:0] to_cpu_output_port, // where to send pkts this pkt if it has to go to the CPU
output [NUM_QUEUES-1:0] from_cpu_output_port, // where to send this pkt if it is coming from the CPU
output [NUM_QUEUES_WIDTH-1:0] input_port_num,
input rd_hdr_parser,
output is_from_cpu_vld,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------------ Internal Parameter ---------------------------
parameter PARSE_HDRS = 0;
parameter WAIT_EOP = 1;
//---------------------- Wires/Regs -------------------------------
reg state, state_next;
reg wr_en;
wire empty;
wire is_from_cpu_found;
wire [NUM_QUEUES-1:0] to_cpu_output_port_result;
wire [NUM_QUEUES-1:0] from_cpu_output_port_result;
wire [NUM_QUEUES-1:0] in_port_decoded;
wire [NUM_QUEUES-1:0] decoded_value[NUM_QUEUES-1:0];
wire [NUM_QUEUES_WIDTH-1:0] input_port_num_result;
//----------------------- Modules ---------------------------------
fallthrough_small_fifo #(.WIDTH(1 + 2*NUM_QUEUES + NUM_QUEUES_WIDTH), .MAX_DEPTH_BITS(2))
is_from_cpu_fifo
(.din ({is_from_cpu_found, to_cpu_output_port_result, from_cpu_output_port_result, input_port_num_result}), // Data in
.wr_en (wr_en), // Write enable
.rd_en (rd_hdr_parser), // Read the next word
.dout ({is_from_cpu, to_cpu_output_port, from_cpu_output_port, input_port_num}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------ Logic ----------------------------------
assign is_from_cpu_vld = !empty;
/* decode the source port number */
generate
genvar i;
for(i=0; i<NUM_QUEUES; i=i+1) begin: decoder
assign decoded_value[i] = 2**i;
end
endgenerate
assign in_port_decoded = decoded_value[input_port_num_result];
// Note: you cannot do [`IOQ_SRC_PORT_POS +: NUM_QUEUES_WIDTH] in the
// statement below as it does not work with ModelSim SE 6.2F
assign input_port_num_result = in_data[`IOQ_SRC_PORT_POS +: 16];
assign is_from_cpu_found = |(in_port_decoded & {(NUM_QUEUES/2){2'b10}}) ;
assign to_cpu_output_port_result = {in_port_decoded[NUM_QUEUES-2:0], 1'b0}; // odd numbers are CPU ports
assign from_cpu_output_port_result = {1'b0, in_port_decoded[NUM_QUEUES-1:1]};// even numbers are MAC ports
always@(*) begin
state_next = state;
wr_en = 0;
case(state)
PARSE_HDRS: begin
if( in_ctrl==0 && in_wr) begin
state_next = WAIT_EOP;
end
if( in_ctrl==IO_QUEUE_STAGE_NUM && in_wr) begin
wr_en = 1;
end
end
WAIT_EOP: begin
if(in_wr && in_ctrl != 0) begin
state_next = PARSE_HDRS;
end
end
endcase // case(state)
end // always@ (*)
always @(posedge clk) begin
if(reset) begin
state <= PARSE_HDRS;
end
else begin
state <= state_next;
end
end
endmodule // eth_parser
|
//oob_controller.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module oob_controller (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output reg platform_error, //Underlyaing physal platform received an error, this should probably be a reset
output reg linkup, //link is finished
output reg tx_comm_reset, //send a init OOB signal
output reg tx_comm_wake, //send a wake OOB signal
input tx_oob_complete, //Phy has said we are finished with this OOB transaction
input comm_init_detect, //detected an init
input comm_wake_detect, //detected a wake on the rx lines
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input rx_byte_is_aligned,
input phy_error,
output reg [31:0] tx_dout,
output reg tx_is_k,
output reg tx_set_elec_idle,
output [3:0] lax_state
);
//platform signals
//Parameters
//States
parameter IDLE = 4'h0;
parameter SEND_RESET = 4'h1;
parameter WAIT_FOR_INIT = 4'h2;
parameter WAIT_FOR_NO_INIT = 4'h3;
parameter WAIT_FOR_CONFIGURE_END = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter WAIT_FOR_WAKE = 4'h6;
parameter WAIT_FOR_NO_WAKE = 4'h7;
parameter WAIT_FOR_IDLE = 4'h8;
parameter WAIT_FOR_ALIGN = 4'h9;
parameter SEND_ALIGN = 4'hA;
parameter DETECT_SYNC = 4'hB;
parameter READY = 4'hC;
//Registers/Wires
reg [3:0] state;
reg [31:0] timer;
reg [1:0] no_align_count;
reg [3:0] retries;
//timer used to send 'INITs', WAKEs' and read them
wire timeout;
wire align_detected;
wire sync_detected;
//Submodules
//Asynchronous Logic
assign timeout = (timer == 0);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && !phy_error);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && rx_byte_is_aligned);
assign sync_detected = ((rx_is_k > 0) && (rx_din == `PRIM_SYNC));
assign lax_state = state;
//Synchronous Logic
initial begin
tx_set_elec_idle <= 1;
end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
linkup <= 0;
timer <= 0;
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_dout <= 0;
tx_is_k <= 0;
tx_set_elec_idle <= 1;
no_align_count <= 0;
platform_error <= 0;
retries <= 0;
end
else begin
//to support strobes, continuously reset the following signals
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_is_k <= 0;
//timer (when reache 0 timeout has occured)
if (timer > 0) begin
timer <= timer - 1;
end
//main state machine, if this reaches ready an initialization sequence has completed
case (state)
IDLE: begin
platform_error <= 0;
linkup <= 0;
tx_set_elec_idle <= 1;
if (platform_ready) begin
$display ("oob_controller: send RESET");
//the platform is ready
// PLL has locked onto a clock
// DCM has generated the correct clocks
timer <= 32'h000000A2;
state <= SEND_RESET;
tx_comm_reset <= 1;
end
end
SEND_RESET: begin
//XXX: In the groundhog COMM RESET was continuously issued for a long period of time
//send the INIT sequence, this will initiate a communication with the
//SATA hard drive, or reset it so that it can be initiated to state
//strobe the comm init so that the platform will send an INIT OOB signal
if (timeout || tx_oob_complete) begin
timer <= `INITIALIZE_TIMEOUT;
state <= WAIT_FOR_INIT;
$display ("oob_controller: wait for INIT");
end
end
WAIT_FOR_INIT: begin
//wait for a response from the SATA harddrive, if the timeout occurs
//go back to the SEND_RESET state
if (comm_init_detect) begin
//HD said 'sup' go to a wake
//timer <= 0;
timer <= 32'h00001000;
state <= WAIT_FOR_NO_INIT;
$display ("oob_controller: wait for INIT to go low");
end
if (timeout) begin
$display ("oob_controller: timed out while waiting for INIT");
state <= IDLE;
end
end
WAIT_FOR_NO_INIT: begin
//wait for the init signal to go low from the device
if (!comm_init_detect && (timeout || tx_oob_complete)) begin
$display ("oob_controller: INIT deasserted");
$display ("oob_controller: start configuration");
state <= WAIT_FOR_CONFIGURE_END;
end
end
WAIT_FOR_CONFIGURE_END: begin
$display ("oob_controller: System is configured");
state <= SEND_WAKE;
timer <= 32'h0000009B;
tx_comm_wake <= 1;
//end
end
SEND_WAKE: begin
//XXX: In the groundhog COMM WAKE was continuously send for a long period of time
//Send the WAKE sequence to the hard drive to initiate a wakeup sequence
//XXX: Is this timeout correct?
//880uS
if (timeout || tx_oob_complete) begin
//timer <= 32'd`INITIALIZE_TIMEOUT;
timer <= 32'h000203AD;
state <= WAIT_FOR_WAKE;
end
end
WAIT_FOR_WAKE: begin
//Wait for the device to send a COMM Wake
if (comm_wake_detect) begin
//Found a comm wake, now wait for the device to stop sending WAKE
timer <= 0;
state <= WAIT_FOR_NO_WAKE;
$display ("oob_controller: WAKE detected");
end
if (timeout) begin
//Timeout occured before reading WAKE
state <= IDLE;
$display ("oob_controller: timed out while waiting for WAKE to be asserted");
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
//The device stopped sending comm wake
//XXX: Is this timeout correct?
//880uS
$display ("oob_controller: detected WAKE deasserted");
$display ("oob_controller: Send Dialtone, wait for ALIGN");
//Going to add more timeout
//timer <= 32'h0203AD;
timer <= 32'h0203AD;
state <= WAIT_FOR_ALIGN;
//state <= WAIT_FOR_IDLE;
retries <= 4;
end
end
/*
WAIT_FOR_IDLE: begin
if (!rx_is_elec_idle) begin
state <= WAIT_FOR_ALIGN;
timer <= 32'h0101D0;
end
else if (timeout) begin
if (retries > 0) begin
timer <= 32'h0203AD;
retries <= retries - 1;
end
if (retries == 0) begin
state <= IDLE;
end
end
end
*/
WAIT_FOR_ALIGN: begin
//transmit the 'dialtone' continuously
//since we need to start sending actual data (not OOB signals, get out
// of tx idle)
tx_set_elec_idle <= 0;
//a sequence of 0's and 1's
tx_dout <= `DIALTONE;
tx_is_k <= 0;
//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
if (align_detected) begin
//we got something from the device!
timer <= 0;
//now send an align from my side
state <= SEND_ALIGN;
no_align_count <= 0;
$display ("oob_controller: ALIGN detected");
$display ("oob_controller: Send out my ALIGNs");
end
if (timeout) begin
//didn't read an align in time :( reset
$display ("oob_controller: timed out while waiting for AIGN");
state <= IDLE;
end
end
SEND_ALIGN: begin
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
if (!align_detected) begin
$display ("oob_controller: detected ALIGN deasserted");
//XXX: Groundhog detects the SYNC primitve before declaring linkup
if (no_align_count == 3) begin
$display ("oob_controller: ready");
state <= READY;
end
else begin
no_align_count <= no_align_count + 2'b01;
end
end
end
DETECT_SYNC: begin
if (sync_detected) begin
state <= READY;
end
end
READY: begin
linkup <= 1;
/*
if (phy_error) begin
platform_error <= 1;
end
*/
if (comm_init_detect) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// MP3 demo Test bench top level ////
//// ////
//// This file is part of the MP3 demo application ////
//// http://www.opencores.org/cores/or1k/mp3/ ////
//// ////
//// Description ////
//// Top level of MP3 demo test bench. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Lior Shtram, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xess_top.v,v $
// Revision 1.2 2002/08/12 05:37:02 lampret
// Fixed reference name
//
// Revision 1.1 2002/03/28 19:59:55 lampret
// Added bench directory
//
// Revision 1.2 2002/01/03 08:40:15 lampret
// Added second clock as RISC main clock. Updated or120_monitor.
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
//
// Xess board - top bench module
`include "rtl/verilog/bench_timescale.v"
`include "bench/verilog/bench_defines.v"
module xess_top (
);
`ifdef SRAM_INIT
sram_init sram_init1();
`endif
or1200_monitor or1200_monitor();
or1200_monitor2 or1200_monitor2();
reg r_rstn;
reg r_clk;
wire rstn;
wire clk;
// SPOOFER
`ifdef SPOOFER
wire [31:0] clk_count;
wire [31:0] spoof_out;
wire trigger;
// SPOOFER
`endif
//reg r_tx_clk;
//reg r_rx_clk;
//wire tx_clk;
//wire rx_clk;
wire flash_rstn;
wire flash_oen;
wire flash_cen;
wire flash_wen;
wire flash_rdy;
wire [7:0] flash_d;
wire [20:0] flash_a;
wire [31:0] flash_vpp; // Special flash inputs
wire [31:0] flash_vcc; // Special flash inputs
wire [1:0] flash_rpblevel; // Special flash inputs
wire sram_r_cen;
wire sram_r0_wen;
wire sram_r1_wen;
wire sram_r_oen;
wire [18:0] sram_r_a;
wire [15:0] sram_r_d;
wire sram_l_cen;
wire sram_l0_wen;
wire sram_l1_wen;
wire sram_l_oen;
wire [18:0] sram_l_a;
wire [15:0] sram_l_d;
wire codec_mclk;
wire codec_lrclk;
wire codec_sclk;
wire codec_sdin;
wire codec_sdout;
wire vga_hsyncn;
wire vga_vsyncn;
wire [1:0] vga_r;
wire [1:0] vga_g;
wire [1:0] vga_b;
wire eth_tx_er;
wire eth_tx_clk;
wire eth_tx_en;
wire [4:0] eth_txd;
wire eth_rx_er;
wire eth_rx_clk;
wire eth_rx_dv;
wire [4:0] eth_rxd;
wire eth_col;
wire eth_crs;
wire eth_trste;
wire eth_fds_mdint;
wire eth_mdio;
wire eth_mdc;
wire [2:1] switch;
wire USB_VPO;
wire USB_VMO;
wire gdb_tms;
wire gdb_tck;
wire gdb_trst;
wire gdb_tdi;
wire gdb_tdo;
wire [6:3] pps;
// Putting here the following blocks
// The xfpga_top
xsv_fpga_top i_xess_fpga(
.clk( clk ),
.rstn( rstn ),
/*
.tx_clk ( tx_clk ),
.rx_clk ( rx_clk ),
*/
// SPOOFER
`ifdef SPOOFER
.clk_count( clk_count ),
.spoof_out( spoof_out ),
.trigger( trigger ),
`endif
.flash_rstn( flash_rstn ),
.flash_cen( flash_cen ),
.flash_oen( flash_oen ),
.flash_wen( flash_wen ),
.flash_rdy( flash_rdy ),
.flash_d( flash_d ),
.flash_a( flash_a ),
.sram_r_cen( sram_r_cen ),
.sram_r_oen( sram_r_oen ),
.sram_r0_wen( sram_r0_wen ),
.sram_r1_wen( sram_r1_wen ),
.sram_r_d( sram_r_d ),
.sram_r_a( sram_r_a ),
.sram_l_cen( sram_l_cen ),
.sram_l_oen( sram_l_oen ),
.sram_l0_wen( sram_l0_wen ),
.sram_l1_wen( sram_l1_wen ),
.sram_l_d( sram_l_d ),
.sram_l_a( sram_l_a ),
/*
.codec_mclk( codec_mclk ),
.codec_lrclk( codec_lrclk ),
.codec_sclk( codec_sclk ),
.codec_sdin( codec_sdin ),
.codec_sdout( codec_sdout ),
.vga_blank(),
.vga_pclk(),
.vga_hsyncn( vga_hsyncn ),
.vga_vsyncn( vga_vsyncn ),
.vga_r( vga_r ),
.vga_g( vga_g ),
.vga_b( vga_b ),
.eth_col( eth_col ),
.eth_crs( eth_crs ),
.eth_trste( eth_trste ),
.eth_tx_clk( eth_tx_clk ),
.eth_tx_en( eth_tx_en ),
.eth_tx_er( eth_tx_er ),
.eth_txd( eth_txd ),
.eth_rx_clk( eth_rx_clk ),
.eth_rx_dv( eth_rx_dv ),
.eth_rx_er( eth_rx_er ),
.eth_rxd( eth_rxd ),
.eth_fds_mdint( eth_fds_mdint ),
.eth_mdc( eth_mdc ),
.eth_mdio( eth_mdio ),
*/
.sw( switch ),
/*
.ps2_clk( ps2_clk ),
.ps2_data( ps2_data ),
*/
.tdmfrm(1'b0),
.tdmrx(1'b0),
.tdmtx()
// .cpld_tdo(cpld_tdo)
);
// The Flash RAM
/*
assign flash_vpp = 32'h00002ee0;
assign flash_vcc = 32'h00001388;
assign flash_rpblevel = 2'b10;
i28f016s3 Flash (
.rpb( flash_rstn ),
.ceb( flash_cen ),
.oeb( flash_oen ),
.web( flash_wen ),
.ryby( flash_rdy ),
.dq( flash_d ),
.addr( flash_a ),
.vpp( flash_vpp ),
.vcc( flash_vcc ),
.rpblevel( flash_rpblevel )
);
*/
// The SRAM
/*
A512Kx8 Sram_r0 (
.CE_bar( sram_r_cen ),
.OE_bar( sram_r_oen ),
.WE_bar( sram_r0_wen ),
.dataIO( sram_r_d[7:0] ),
.Address( sram_r_a )
);
A512Kx8 Sram_r1 (
.CE_bar( sram_r_cen ),
.OE_bar( sram_r_oen ),
.WE_bar( sram_r1_wen ),
.dataIO( sram_r_d[15:8] ),
.Address( sram_r_a )
);
A512Kx8 Sram_l0 (
.CE_bar( sram_l_cen ),
.OE_bar( sram_l_oen ),
.WE_bar( sram_l0_wen ),
.dataIO( sram_l_d[7:0] ),
.Address( sram_l_a )
);
A512Kx8 Sram_l1 (
.CE_bar( sram_l_cen ),
.OE_bar( sram_l_oen ),
.WE_bar( sram_l1_wen ),
.dataIO( sram_l_d[15:8] ),
.Address( sram_l_a )
);
*/
// The Codec
/*
codec_model codec (
.mclk( codec_mclk ),
.lrclk( codec_lrclk ),
.sclk( codec_sclk ),
.sdin( codec_sdin ),
.sdout( codec_sdout )
);
*/
/*
// The VGA
vga_model VGA (
.pclk( clk ),
.hsyncn( vga_hsyncn ),
.vsyncn( vga_vsyncn ),
.r( vga_r ),
.g( vga_g ),
.b( vga_b )
);
*/
/*
// We simulate CPLD because it has GDB JTAG multiplexer that
// works together with demultiplexer in FPGA to connect GDB to
// the RISC
`ifdef UNUSED
config_gdb xcpld (
.clk(clk),
.a(flash_a),
.ceb(),
.oeb(),
.web(),
.resetb(),
.V_progb(),
.V_cclk(),
.V_csb(),
.V_wrb(),
.V_initb(cpld_tdo),
.V_dout(1'b0),
.V_done(1'b1),
.V_m(),
.ppd({2'b00, gdb_tms, gdb_tdi, gdb_trst, gdb_tck, 2'b00}),
.pps(pps),
.ppc(4'h0)
);
assign gdb_tdo = pps[4];
`else
assign flash_a[6] = flash_cen ? gdb_tms : 1'bz;
assign flash_a[7] = flash_cen ? gdb_tdi : 1'bz;
assign flash_a[8] = flash_cen ? gdb_trst : 1'bz;
assign flash_a[9] = flash_cen ? gdb_tck : 1'bz;
//assign gdb_tdo = cpld_tdo;
`endif
*/
// DBG i/f
`ifdef DBG_IF_COMM
dbg_comm dbg_comm(
`else
`ifdef DBG2_IF_COMM
dbg_comm2 dbg_comm(
.P_TMS(gdb_tms),
.P_TCK(gdb_tck),
.P_TRST(gdb_trst),
.P_TDI(gdb_tdi),
.P_TDO(gdb_tdo)
);
`else
assign gdb_tms = 1'b0;
assign gdb_tck = 1'b0;
assign gdb_trst = rstn;
assign gdb_tdi = 1'b0;
`endif
`endif
assign eth_tx_clk = 1'b0;
assign eth_rx_er = 1'b0;
assign eth_rx_clk = 1'b0;
assign eth_rx_dv = 1'b0;
assign eth_rxd = 5'b0;
assign eth_col= 1'b0;
assign eth_crs = 1'b0;
assign eth_fds_mdint = 1'b0;
assign eth_mdio = 1'bZ;
assign switch = 2'b0;
assign ps2_clk = 1'b0;
assign ps2_data = 1'b0;
initial
begin
#0 r_rstn = 1;
#1 r_rstn = 0;
`ifdef SRAM_INIT
sram_init1.init_sram;
`endif
repeat (`BENCH_RESET_TIME) @(negedge r_clk);
r_rstn = 1;
end
assign rstn = r_rstn;
initial begin
r_clk = 1'b0;
//r_tx_clk = 1'b0;
//r_rx_clk = 1'b0;
end
always
begin
#`BENCH_CLK_HALFPERIOD r_clk <= ~r_clk;
end
`ifdef SPOOFER
assign clk_count = 32'b0000000000000000010000000;
`endif
assign clk = r_clk;
//assign tx_clk = r_tx_clk;
//assign rx_clk = r_rx_clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRBP_SYMBOL_V
`define SKY130_FD_SC_HD__DFRBP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRBP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of n0_1
//
// Generated
// by: wig
// on: Tue Apr 1 13:31:51 2008
// cmd: /cygdrive/c/eclipse/MIX/mix_0.pl -strip -nodelta ../noassign.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: n0_1.v,v 1.1 2008/04/01 12:53:30 wig Exp $
// $Date: 2008/04/01 12:53:30 $
// $Log: n0_1.v,v $
// Revision 1.1 2008/04/01 12:53:30 wig
// Added testcase noassign for optimzeassignport feature
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of n0_1
//
// No user `defines in this module
module n0_1
//
// Generated Module N0_1
//
(
input wire clk_i,
input wire data_i,
output wire ready_o,
input wire clk2_i,
input wire data2_i,
output wire ready2_o
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of n0_1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_4_V
`define SKY130_FD_SC_HDLL__A21BO_4_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_4_V
|
module rs232(
reset_n,
clk,
// TRANSMITTER
tx_ready,
tx_data,
tx_start,
cts,
txd,
// RECEIVER
rts,
rxd,
rx_data,
rx_ready,
rx_ack,
debug
);
`include "parameters_global.v"
input reset_n;
input clk;
// TRANSMITTER
output reg tx_ready;
input [`uart_data_width-1:0] tx_data;
input tx_start;
input cts;
output reg txd;
// RECEIVER
output reg rts;
input rxd;
output reg [`uart_data_width-1:0] rx_data;
output reg rx_ready;
input rx_ack;
output [`uart_data_width-1:0] debug;
assign debug = rx_data;
reg [`rs232_state_tx_width-1:0] rs232_state_tx;
reg [`rs232_state_rx_width-1:0] rs232_state_rx;
// SYNCRONIZING
wire cts_sync;
syncronizer sy1 (
.clk(clk),
.reset_n(reset_n),
.input_async(cts),
.output_sync(cts_sync)
);
wire rxd_sync;
syncronizer sy2 (
.clk(clk),
.reset_n(reset_n),
.input_async(rxd),
.output_sync(rxd_sync)
);
// TRANSMITTER
reg timer_tx_start;
rs232_timer timer_tx(
.clk(clk),
.reset_n(reset_n),
.start(timer_tx_start),
.done(timer_tx_done),
.extra_delay(1'b0) // no extra delay
);
reg [`uart_data_width-1:0] tx_latch;
//reg [2:0] tx_bit_pos;
always @(posedge clk or negedge reset_n) begin : fsm_tx
if (~reset_n)
begin
rs232_state_tx <= #`DEL RS232_STATE_TX_RESET;
tx_latch <= #`DEL `uart_data_width'b0;
txd <= #`DEL 1;
timer_tx_start <= #`DEL 0;
//tx_bit_pos <= #`DEL 3'b0;
tx_ready <= #`DEL 0;
end
else
begin
case (rs232_state_tx) // synthesis parallel_case
RS232_STATE_TX_RESET, RS232_STATE_TX_IDLE:
begin
if (cts_sync == cts_asserted) // transmission may start when host signals "clear to send"
begin
rs232_state_tx <= #`DEL RS232_STATE_TX_CTS;
tx_ready <= #`DEL 1;
end
end
RS232_STATE_TX_CTS:
begin
if (tx_start) // transmission start on tx_start
begin
rs232_state_tx <= #`DEL RS232_STATE_TX_START;
tx_latch <= #`DEL tx_data;
tx_ready <= #`DEL 0;
end
end
RS232_STATE_TX_START: // send start bit
begin
txd <= #`DEL 0;
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_0a;
end
RS232_STATE_TX_DATA_0a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[0];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_0b;
end
end
RS232_STATE_TX_DATA_0b:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_1a;
end
RS232_STATE_TX_DATA_1a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[1];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_1b;
end
end
RS232_STATE_TX_DATA_1b:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_2a;
end
RS232_STATE_TX_DATA_2a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[2];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_2b;
end
end
RS232_STATE_TX_DATA_2b:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_3a;
end
RS232_STATE_TX_DATA_3a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[3];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_3b;
end
end
RS232_STATE_TX_DATA_3b:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_4a;
end
RS232_STATE_TX_DATA_4a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[4];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_4b;
end
end
RS232_STATE_TX_DATA_4b:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_5a;
end
RS232_STATE_TX_DATA_5a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[5];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_5b;
end
end
RS232_STATE_TX_DATA_5b: // 15h
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_6a;
end
RS232_STATE_TX_DATA_6a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[6];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_6b;
end
end
RS232_STATE_TX_DATA_6b:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_7a;
end
RS232_STATE_TX_DATA_7a:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL tx_latch[7];
rs232_state_tx <= #`DEL RS232_STATE_TX_DATA_7b;
end
end
RS232_STATE_TX_DATA_7b:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_STOPa;
end
RS232_STATE_TX_STOPa: // send stop bit
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
txd <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_STOPb;
end
end
RS232_STATE_TX_STOPb:
begin
timer_tx_start <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_STOPc;
end
RS232_STATE_TX_STOPc:
begin
timer_tx_start <= #`DEL 0;
if (timer_tx_done)
begin
tx_ready <= #`DEL 1;
rs232_state_tx <= #`DEL RS232_STATE_TX_IDLE;
end
end
endcase
end
end
// RECEIVER
reg rxd_previous;
reg timer_rx_extra_delay;
reg timer_rx_start;
rs232_timer timer_rx(
.clk(clk),
.reset_n(reset_n),
.start(timer_rx_start),
.done(timer_rx_done),
.extra_delay(timer_rx_extra_delay)
);
always @(posedge clk or negedge reset_n) begin : fsm_rx
if (~reset_n)
begin
rs232_state_rx <= #`DEL RS232_STATE_RX_RESET;
timer_rx_start <= #`DEL 0;
timer_rx_extra_delay <= #`DEL 0;
rx_ready <= #`DEL 0;
rx_data <= #`DEL `uart_data_width'b0;
rts <= #`DEL ~rts_asserted;
rxd_previous <= #`DEL 0;
end
else
begin
rxd_previous <= #`DEL rxd_sync;
case (rs232_state_rx) // synthesis parallel_case
RS232_STATE_RX_RESET, RS232_STATE_RX_IDLE:
begin
rts <= #`DEL rts_asserted;
rs232_state_rx <= #`DEL RS232_STATE_RX_RTS;
end
RS232_STATE_RX_RTS: // wait for start bit (H-L transition on rxd_sync)
begin
if ((rxd_previous == 1) && (rxd_sync == 0))
begin
// timer_rx_extra_delay <= #`DEL 1;
// // a half bit time extra is required until lsb is sampled
rs232_state_rx <= #`DEL RS232_STATE_RX_START;
end
end
RS232_STATE_RX_START:
begin
timer_rx_start <= #`DEL 1;
timer_rx_extra_delay <= #`DEL 1;
// a half bit time extra is required until lsb is sampled
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_0a;
end
RS232_STATE_RX_DATA_0a: // 4h // sample bit 0 after 1.5 timer delays
begin
timer_rx_start <= #`DEL 0;
timer_rx_extra_delay <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[0] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_0b;
end
end
RS232_STATE_RX_DATA_0b: // 5h
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_1a;
end
RS232_STATE_RX_DATA_1a: // sample bit 1 after 1.0 timer delay
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[1] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_1b;
end
end
RS232_STATE_RX_DATA_1b:
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_2a;
end
RS232_STATE_RX_DATA_2a: // sample bit 2 after 1.0 timer delay
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[2] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_2b;
end
end
RS232_STATE_RX_DATA_2b:
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_3a;
end
RS232_STATE_RX_DATA_3a: // sample bit 3 after 1.0 timer delay
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[3] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_3b;
end
end
RS232_STATE_RX_DATA_3b:
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_4a;
end
RS232_STATE_RX_DATA_4a: // sample bit 4 after 1.0 timer delay
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[4] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_4b;
end
end
RS232_STATE_RX_DATA_4b:
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_5a;
end
RS232_STATE_RX_DATA_5a: // sample bit 5 after 1.0 timer delay
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[5] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_5b;
end
end
RS232_STATE_RX_DATA_5b:
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_6a;
end
RS232_STATE_RX_DATA_6a: // sample bit 6 after 1.0 timer delay
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[6] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_6b;
end
end
RS232_STATE_RX_DATA_6b:
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_7a;
end
RS232_STATE_RX_DATA_7a: // sample bit 7 after 1.0 timer delay
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
rx_data[7] <= #`DEL rxd_sync;
rs232_state_rx <= #`DEL RS232_STATE_RX_DATA_7b;
end
end
RS232_STATE_RX_DATA_7b: // 19d
begin
timer_rx_start <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_STOPa;
end
RS232_STATE_RX_STOPa: // 20d / 14h
// - wait for stop bit (L-H transition on rxd_sync)
// - signal host, that data is available (rx_ready)
begin
timer_rx_start <= #`DEL 0;
if (timer_rx_done)
begin
//if ((~rxd_previous) && (rxd_sync))
if (rxd_sync)
begin
rx_ready <= #`DEL 1;
rs232_state_rx <= #`DEL RS232_STATE_RX_STOPb;
end
end
//else // stop bit not found -> handle error
end
RS232_STATE_RX_STOPb:
// wait until host acknowledges new data
begin
if (rx_ack)
begin
rx_ready <= #`DEL 0;
rs232_state_rx <= #`DEL RS232_STATE_RX_IDLE;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A22O_PP_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A221OI_BLACKBOX_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_4_V
`define SKY130_FD_SC_HS__NOR4BB_4_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4bb_4 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4bb_4 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_TB_V
`define SKY130_FD_SC_HS__FILL_DIODE_TB_V
/**
* fill_diode: Fill diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill_diode.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hs__fill_diode dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_TB_V
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/11.1sp2/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2011/11/10 $
// $Author: max $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input clk,
output reset_out
);
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
wire merged_reset;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin
assign reset_out = merged_reset;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out)
);
end
endgenerate
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "usb_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 11:21:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_util_ds_buf_1_0 -prefix
// system_util_ds_buf_1_0_ system_util_ds_buf_0_0_stub.v
// Design : system_util_ds_buf_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_ds_buf,Vivado 2016.4" *)
module system_util_ds_buf_1_0(BUFG_I, BUFG_O)
/* synthesis syn_black_box black_box_pad_pin="BUFG_I[0:0],BUFG_O[0:0]" */;
input [0:0]BUFG_I;
output [0:0]BUFG_O;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
assign uart_rts = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 3 11:56:54 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, r_mode,
ready_cordic, overflow_flag, underflow_flag, data_output );
input [63:0] data_in;
input [1:0] shift_region_flag;
input [1:0] r_mode;
output [63:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_63_, cordic_FSM_state_next_1_,
add_subt_module_sign_final_result, add_subt_module_intAS,
add_subt_module_FSM_exp_operation_A_S,
add_subt_module_add_overflow_flag, add_subt_module_FSM_selector_C,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1961, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, DP_OP_92J75_122_9081_n26,
DP_OP_92J75_122_9081_n25, DP_OP_92J75_122_9081_n24,
DP_OP_92J75_122_9081_n23, DP_OP_92J75_122_9081_n22,
DP_OP_92J75_122_9081_n21, DP_OP_92J75_122_9081_n20,
DP_OP_92J75_122_9081_n19, DP_OP_92J75_122_9081_n18,
DP_OP_92J75_122_9081_n17, DP_OP_92J75_122_9081_n16,
DP_OP_92J75_122_9081_n11, DP_OP_92J75_122_9081_n10,
DP_OP_92J75_122_9081_n9, DP_OP_92J75_122_9081_n8,
DP_OP_92J75_122_9081_n7, DP_OP_92J75_122_9081_n6,
DP_OP_92J75_122_9081_n5, DP_OP_92J75_122_9081_n4,
DP_OP_92J75_122_9081_n3, DP_OP_92J75_122_9081_n2,
DP_OP_92J75_122_9081_n1, DP_OP_95J75_125_7728_n114,
DP_OP_95J75_125_7728_n113, DP_OP_95J75_125_7728_n112,
DP_OP_95J75_125_7728_n111, DP_OP_95J75_125_7728_n110,
DP_OP_95J75_125_7728_n109, DP_OP_95J75_125_7728_n108,
DP_OP_95J75_125_7728_n107, DP_OP_95J75_125_7728_n106,
DP_OP_95J75_125_7728_n105, DP_OP_95J75_125_7728_n104,
DP_OP_95J75_125_7728_n103, DP_OP_95J75_125_7728_n102,
DP_OP_95J75_125_7728_n101, DP_OP_95J75_125_7728_n100,
DP_OP_95J75_125_7728_n99, DP_OP_95J75_125_7728_n98,
DP_OP_95J75_125_7728_n97, DP_OP_95J75_125_7728_n96,
DP_OP_95J75_125_7728_n95, DP_OP_95J75_125_7728_n94,
DP_OP_95J75_125_7728_n93, DP_OP_95J75_125_7728_n92,
DP_OP_95J75_125_7728_n91, DP_OP_95J75_125_7728_n90,
DP_OP_95J75_125_7728_n89, DP_OP_95J75_125_7728_n88,
DP_OP_95J75_125_7728_n87, DP_OP_95J75_125_7728_n86,
DP_OP_95J75_125_7728_n85, DP_OP_95J75_125_7728_n84,
DP_OP_95J75_125_7728_n83, DP_OP_95J75_125_7728_n82,
DP_OP_95J75_125_7728_n81, DP_OP_95J75_125_7728_n80,
DP_OP_95J75_125_7728_n79, DP_OP_95J75_125_7728_n78,
DP_OP_95J75_125_7728_n77, DP_OP_95J75_125_7728_n76,
DP_OP_95J75_125_7728_n75, DP_OP_95J75_125_7728_n74,
DP_OP_95J75_125_7728_n73, DP_OP_95J75_125_7728_n72,
DP_OP_95J75_125_7728_n71, DP_OP_95J75_125_7728_n70,
DP_OP_95J75_125_7728_n69, DP_OP_95J75_125_7728_n68,
DP_OP_95J75_125_7728_n67, DP_OP_95J75_125_7728_n66,
DP_OP_95J75_125_7728_n65, DP_OP_95J75_125_7728_n64,
DP_OP_95J75_125_7728_n63, DP_OP_95J75_125_7728_n62,
DP_OP_95J75_125_7728_n61, DP_OP_95J75_125_7728_n60,
DP_OP_95J75_125_7728_n55, DP_OP_95J75_125_7728_n54,
DP_OP_95J75_125_7728_n53, DP_OP_95J75_125_7728_n52,
DP_OP_95J75_125_7728_n51, DP_OP_95J75_125_7728_n50,
DP_OP_95J75_125_7728_n49, DP_OP_95J75_125_7728_n48,
DP_OP_95J75_125_7728_n47, DP_OP_95J75_125_7728_n46,
DP_OP_95J75_125_7728_n45, DP_OP_95J75_125_7728_n44,
DP_OP_95J75_125_7728_n43, DP_OP_95J75_125_7728_n42,
DP_OP_95J75_125_7728_n41, DP_OP_95J75_125_7728_n40,
DP_OP_95J75_125_7728_n39, DP_OP_95J75_125_7728_n38,
DP_OP_95J75_125_7728_n37, DP_OP_95J75_125_7728_n36,
DP_OP_95J75_125_7728_n35, DP_OP_95J75_125_7728_n34,
DP_OP_95J75_125_7728_n33, DP_OP_95J75_125_7728_n32,
DP_OP_95J75_125_7728_n31, DP_OP_95J75_125_7728_n30,
DP_OP_95J75_125_7728_n29, DP_OP_95J75_125_7728_n28,
DP_OP_95J75_125_7728_n27, DP_OP_95J75_125_7728_n26,
DP_OP_95J75_125_7728_n25, DP_OP_95J75_125_7728_n24,
DP_OP_95J75_125_7728_n23, DP_OP_95J75_125_7728_n22,
DP_OP_95J75_125_7728_n21, DP_OP_95J75_125_7728_n20,
DP_OP_95J75_125_7728_n19, DP_OP_95J75_125_7728_n18,
DP_OP_95J75_125_7728_n17, DP_OP_95J75_125_7728_n16,
DP_OP_95J75_125_7728_n15, DP_OP_95J75_125_7728_n14,
DP_OP_95J75_125_7728_n13, DP_OP_95J75_125_7728_n12,
DP_OP_95J75_125_7728_n11, DP_OP_95J75_125_7728_n10,
DP_OP_95J75_125_7728_n9, DP_OP_95J75_125_7728_n8,
DP_OP_95J75_125_7728_n7, DP_OP_95J75_125_7728_n6,
DP_OP_95J75_125_7728_n5, DP_OP_95J75_125_7728_n4,
DP_OP_95J75_125_7728_n3, DP_OP_95J75_125_7728_n2,
DP_OP_95J75_125_7728_n1, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362,
n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372,
n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382,
n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392,
n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402,
n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502,
n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512,
n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522,
n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532,
n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542,
n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652,
n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662,
n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672,
n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682,
n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692,
n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702,
n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712,
n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722,
n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732,
n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742,
n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752,
n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762,
n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772,
n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782,
n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792,
n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802,
n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812,
n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822,
n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832,
n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842,
n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852,
n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862,
n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872,
n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882,
n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892,
n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902,
n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912,
n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922,
n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932,
n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942,
n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952,
n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962,
n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972,
n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982,
n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992,
n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002,
n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012,
n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022,
n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162,
n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172,
n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182,
n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232,
n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242,
n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252,
n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262,
n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272,
n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282,
n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [63:0] result_add_subt;
wire [62:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
wire [54:0] add_subt_module_S_A_S_Oper_A;
wire [54:0] add_subt_module_Sgf_normalized_result;
wire [54:0] add_subt_module_Add_Subt_result;
wire [5:0] add_subt_module_LZA_output;
wire [10:0] add_subt_module_S_Oper_A_exp;
wire [10:0] add_subt_module_exp_oper_result;
wire [62:0] add_subt_module_DmP;
wire [62:0] add_subt_module_DMP;
wire [63:1] add_subt_module_intDY;
wire [63:0] add_subt_module_intDX;
wire [1:0] add_subt_module_FSM_selector_B;
wire [3:0] add_subt_module_FS_Module_state_reg;
wire [10:0] add_subt_module_Exp_Operation_Module_Data_S;
wire [54:0] add_subt_module_Add_Subt_Sgf_module_S_to_D;
wire [109:0] add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n2807), .CK(n5337), .RN(n5517), .Q(
d_ff3_LUT_out[12]), .QN(n5272) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n2819), .CK(n5338), .RN(n5518), .Q(
d_ff3_LUT_out[24]), .QN(n5271) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n2828), .CK(n3009), .RN(n5519), .Q(
d_ff3_LUT_out[33]), .QN(n5270) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]),
.CK(n3265), .RN(n5276), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .QN(
n5269) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n2528), .CK(n5352), .RN(n5511), .Q(
d_ff_Yn[61]), .QN(n5268) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(n2520), .CK(n5353), .RN(n5509), .Q(
d_ff_Yn[59]), .QN(n5267) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(n2512), .CK(n5350), .RN(n5508), .Q(
d_ff_Yn[57]), .QN(n5266) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(n2504), .CK(n5357), .RN(n5506), .Q(
d_ff_Yn[55]), .QN(n5265) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n2500), .CK(n5358), .RN(n5505), .Q(
d_ff_Yn[54]), .QN(n5264) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(n2496), .CK(n5359), .RN(n5505), .Q(
d_ff_Yn[53]), .QN(n5263) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n2488), .CK(n5448), .RN(n5503), .Q(
d_ff_Yn[51]), .QN(n5262) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n2484), .CK(n5363), .RN(n5499), .Q(
d_ff_Yn[50]), .QN(n5261) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n2480), .CK(n5326), .RN(n5496), .Q(
d_ff_Yn[49]), .QN(n5260) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n2476), .CK(n5379), .RN(n5501), .Q(
d_ff_Yn[48]), .QN(n5259) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n2472), .CK(n3261), .RN(n5498), .Q(
d_ff_Yn[47]), .QN(n5258) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n2468), .CK(n5379), .RN(n5492), .Q(
d_ff_Yn[46]), .QN(n5257) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n2464), .CK(n5364), .RN(n5490), .Q(
d_ff_Yn[45]), .QN(n5256) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n2460), .CK(n5368), .RN(n5531), .Q(
d_ff_Yn[44]), .QN(n5255) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n2456), .CK(n5369), .RN(n5486), .Q(
d_ff_Yn[43]), .QN(n5254) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n2452), .CK(n5393), .RN(n3281), .Q(
d_ff_Yn[42]), .QN(n5253) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n2448), .CK(n5392), .RN(n5481), .Q(
d_ff_Yn[41]), .QN(n5252) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n2444), .CK(n5384), .RN(n5484), .Q(
d_ff_Yn[40]), .QN(n5251) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n2440), .CK(n5387), .RN(n5480), .Q(
d_ff_Yn[39]), .QN(n5250) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n2436), .CK(n5402), .RN(n5483), .Q(
d_ff_Yn[38]), .QN(n5249) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n2432), .CK(n5439), .RN(n5479), .Q(
d_ff_Yn[37]), .QN(n5248) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n2428), .CK(n5389), .RN(n5473), .Q(
d_ff_Yn[36]), .QN(n5247) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n2424), .CK(n5401), .RN(n5475), .Q(
d_ff_Yn[35]), .QN(n5246) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n2420), .CK(n3256), .RN(n5477), .Q(
d_ff_Yn[34]), .QN(n5245) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n2416), .CK(n5412), .RN(n5466), .Q(
d_ff_Yn[33]), .QN(n5244) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n2412), .CK(n5418), .RN(n5464), .Q(
d_ff_Yn[32]), .QN(n5243) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n2408), .CK(n5406), .RN(n5470), .Q(
d_ff_Yn[31]), .QN(n5242) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n2404), .CK(n5398), .RN(n5476), .Q(
d_ff_Yn[30]), .QN(n5241) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n2400), .CK(n5407), .RN(n5469), .Q(
d_ff_Yn[29]), .QN(n5240) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n2396), .CK(n5418), .RN(n5461), .Q(
d_ff_Yn[28]), .QN(n5239) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n2392), .CK(n5405), .RN(n5471), .Q(
d_ff_Yn[27]), .QN(n5238) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n2388), .CK(n5419), .RN(n5460), .Q(
d_ff_Yn[26]), .QN(n5237) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n2380), .CK(n5416), .RN(n5463), .Q(
d_ff_Yn[24]), .QN(n5236) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n2376), .CK(n5391), .RN(n5476), .Q(
d_ff_Yn[23]), .QN(n5235) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n2372), .CK(n5417), .RN(n5462), .Q(
d_ff_Yn[22]), .QN(n5234) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n2368), .CK(n5409), .RN(n5468), .Q(
d_ff_Yn[21]), .QN(n5233) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n2364), .CK(n3271), .RN(n5489), .Q(
d_ff_Yn[20]), .QN(n5232) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n2360), .CK(n5397), .RN(n5478), .Q(
d_ff_Yn[19]), .QN(n5231) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n2356), .CK(n5425), .RN(n5467), .Q(
d_ff_Yn[18]), .QN(n5230) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n2352), .CK(n5413), .RN(n5465), .Q(
d_ff_Yn[17]), .QN(n5229) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n2348), .CK(n3271), .RN(n5494), .Q(
d_ff_Yn[16]), .QN(n5228) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n2344), .CK(n5399), .RN(n5474), .Q(
d_ff_Yn[15]), .QN(n5227) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n2340), .CK(n5400), .RN(n5472), .Q(
d_ff_Yn[14]), .QN(n5226) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n2336), .CK(n5381), .RN(n5488), .Q(
d_ff_Yn[13]), .QN(n5225) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n2332), .CK(n5395), .RN(n3279), .Q(
d_ff_Yn[12]), .QN(n5224) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n2328), .CK(n5388), .RN(n3277), .Q(
d_ff_Yn[11]), .QN(n5223) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n2324), .CK(n3273), .RN(n5487), .Q(
d_ff_Yn[10]), .QN(n5222) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n2320), .CK(n5403), .RN(n5493), .Q(
d_ff_Yn[9]), .QN(n5221) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n2316), .CK(n5404), .RN(n5482), .Q(
d_ff_Yn[8]), .QN(n5220) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n2312), .CK(n5385), .RN(n5485), .Q(
d_ff_Yn[7]), .QN(n5219) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n2308), .CK(n5363), .RN(n5491), .Q(
d_ff_Yn[6]), .QN(n5218) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n2304), .CK(n5378), .RN(n5490), .Q(
d_ff_Yn[5]), .QN(n5217) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n2300), .CK(n5364), .RN(n5502), .Q(
d_ff_Yn[4]), .QN(n5216) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n2296), .CK(n5377), .RN(n5497), .Q(
d_ff_Yn[3]), .QN(n5215) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n2292), .CK(n5370), .RN(n5500), .Q(
d_ff_Yn[2]), .QN(n5214) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n2288), .CK(n5372), .RN(n5497), .Q(
d_ff_Yn[1]), .QN(n5213) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n2219), .CK(n5345), .RN(n5503), .Q(
d_ff_Yn[0]), .QN(n5212) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]),
.CK(n5421), .RN(n5274), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .QN(
n5211) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n2818), .CK(n5339), .RN(n5518), .Q(
d_ff3_LUT_out[23]), .QN(n5210) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n2918), .CK(n3261), .RN(n5528), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n5209) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n2099), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_y_out[56]), .QN(n5207) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n2778), .CK(n5434), .RN(n5514), .Q(
d_ff3_sh_x_out[56]), .QN(n5206) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n2803), .CK(n5338), .RN(n5517), .Q(
d_ff3_LUT_out[8]), .QN(n5205) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1786), .CK(n5444), .RN(n5300), .Q(add_subt_module_DmP[15]), .QN(n5204) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(
n2636), .CK(n5326), .RN(n5307), .Q(add_subt_module_Add_Subt_result[40]), .QN(n5203) );
DFFRX2TS add_subt_module_Sel_C_Q_reg_0_ ( .D(n2650), .CK(n5336), .RN(n1959),
.Q(add_subt_module_FSM_selector_C), .QN(n5053) );
DFFRX1TS cont_var_count_reg_0_ ( .D(n2926), .CK(n5373), .RN(n5528), .Q(
cont_var_out[0]), .QN(n5201) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(
n2558), .CK(n5408), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[23]), .QN(n5200) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(
n2559), .CK(n5416), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[24]), .QN(n5199) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(
n2560), .CK(n5397), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[25]), .QN(n5198) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(
n2563), .CK(n5419), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[28]), .QN(n5196) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(
n2564), .CK(n5398), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[29]), .QN(n5195) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(
n2565), .CK(n5417), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[30]), .QN(n5194) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(
n2566), .CK(n5407), .RN(n5317), .Q(
add_subt_module_Sgf_normalized_result[31]), .QN(n5193) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
n2538), .CK(n2996), .RN(n5311), .Q(
add_subt_module_Sgf_normalized_result[3]), .QN(n5192) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
n2539), .CK(n5372), .RN(n5311), .Q(
add_subt_module_Sgf_normalized_result[4]), .QN(n5191) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
n2540), .CK(n5368), .RN(n5311), .Q(
add_subt_module_Sgf_normalized_result[5]), .QN(n5190) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
n2541), .CK(n5360), .RN(n5312), .Q(
add_subt_module_Sgf_normalized_result[6]), .QN(n5189) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(
n2542), .CK(n5379), .RN(n5312), .Q(
add_subt_module_Sgf_normalized_result[7]), .QN(n5188) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(
n2543), .CK(n5376), .RN(n5312), .Q(
add_subt_module_Sgf_normalized_result[8]), .QN(n5187) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(
n2544), .CK(n5384), .RN(n5312), .Q(
add_subt_module_Sgf_normalized_result[9]), .QN(n5186) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(
n2545), .CK(n5396), .RN(n5312), .Q(
add_subt_module_Sgf_normalized_result[10]), .QN(n5185) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(
n2546), .CK(n3271), .RN(n5313), .Q(
add_subt_module_Sgf_normalized_result[11]), .QN(n5184) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(
n2547), .CK(n5385), .RN(n5313), .Q(
add_subt_module_Sgf_normalized_result[12]), .QN(n5183) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(
n2549), .CK(n5389), .RN(n5313), .Q(
add_subt_module_Sgf_normalized_result[14]), .QN(n5181) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(
n2550), .CK(n5381), .RN(n5313), .Q(
add_subt_module_Sgf_normalized_result[15]), .QN(n5180) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
n2551), .CK(n5397), .RN(n5314), .Q(
add_subt_module_Sgf_normalized_result[16]), .QN(n5179) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
n2552), .CK(n5401), .RN(n5314), .Q(
add_subt_module_Sgf_normalized_result[17]), .QN(n5178) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
n2553), .CK(n5367), .RN(n5314), .Q(
add_subt_module_Sgf_normalized_result[18]), .QN(n5177) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
n2554), .CK(n5413), .RN(n5314), .Q(
add_subt_module_Sgf_normalized_result[19]), .QN(n5176) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
n2555), .CK(n5409), .RN(n5314), .Q(
add_subt_module_Sgf_normalized_result[20]), .QN(n5175) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
n2556), .CK(n5393), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[21]), .QN(n5174) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
n2557), .CK(n5367), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[22]), .QN(n5173) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(
n2567), .CK(n5400), .RN(n5317), .Q(
add_subt_module_Sgf_normalized_result[32]), .QN(n5172) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(
n2568), .CK(n5405), .RN(n5317), .Q(
add_subt_module_Sgf_normalized_result[33]), .QN(n5171) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(
n2569), .CK(n5420), .RN(n5317), .Q(
add_subt_module_Sgf_normalized_result[34]), .QN(n5170) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(
n2570), .CK(n5412), .RN(n5317), .Q(
add_subt_module_Sgf_normalized_result[35]), .QN(n5169) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(
n2571), .CK(n5396), .RN(n5318), .Q(
add_subt_module_Sgf_normalized_result[36]), .QN(n5168) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(
n2573), .CK(n5389), .RN(n5318), .Q(
add_subt_module_Sgf_normalized_result[38]), .QN(n5166) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(
n2574), .CK(n5396), .RN(n5318), .Q(
add_subt_module_Sgf_normalized_result[39]), .QN(n5165) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(
n2575), .CK(n5393), .RN(n5318), .Q(
add_subt_module_Sgf_normalized_result[40]), .QN(n5164) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(
n2576), .CK(n5389), .RN(n5319), .Q(
add_subt_module_Sgf_normalized_result[41]), .QN(n5163) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(
n2577), .CK(n5385), .RN(n5319), .Q(
add_subt_module_Sgf_normalized_result[42]), .QN(n5162) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(
n2578), .CK(n5398), .RN(n5319), .Q(
add_subt_module_Sgf_normalized_result[43]), .QN(n5161) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(
n2579), .CK(n5393), .RN(n5319), .Q(
add_subt_module_Sgf_normalized_result[44]), .QN(n5160) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(
n2580), .CK(n5382), .RN(n5319), .Q(
add_subt_module_Sgf_normalized_result[45]), .QN(n5159) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(
n2581), .CK(n5370), .RN(n5320), .Q(
add_subt_module_Sgf_normalized_result[46]), .QN(n5158) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(
n2582), .CK(n5378), .RN(n5320), .Q(
add_subt_module_Sgf_normalized_result[47]), .QN(n5157) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(
n2583), .CK(n5372), .RN(n5320), .Q(
add_subt_module_Sgf_normalized_result[48]), .QN(n5156) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(
n2584), .CK(n5367), .RN(n5320), .Q(
add_subt_module_Sgf_normalized_result[49]), .QN(n5155) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(
n2585), .CK(n5364), .RN(n5320), .Q(
add_subt_module_Sgf_normalized_result[50]), .QN(n5154) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(
n2586), .CK(n5364), .RN(n5321), .Q(
add_subt_module_Sgf_normalized_result[51]), .QN(n5153) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(
n2588), .CK(n5361), .RN(n5321), .Q(
add_subt_module_Sgf_normalized_result[53]), .QN(n5151) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
n2599), .CK(n5403), .RN(n5310), .Q(add_subt_module_Add_Subt_result[3]),
.QN(n5150) );
DFFRX1TS add_subt_module_XRegister_Q_reg_13_ ( .D(n1850), .CK(n5438), .RN(
n5295), .Q(add_subt_module_intDX[13]), .QN(n5147) );
DFFRX1TS add_subt_module_XRegister_Q_reg_40_ ( .D(n1837), .CK(n5438), .RN(
n5296), .Q(add_subt_module_intDX[40]), .QN(n5146) );
DFFRXLTS add_subt_module_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n2934),
.CK(n5327), .RN(n5275), .Q(underflow_flag), .QN(n5145) );
DFFRX1TS add_subt_module_XRegister_Q_reg_20_ ( .D(n1853), .CK(n5427), .RN(
n5294), .Q(add_subt_module_intDX[20]), .QN(n5144) );
DFFRX1TS add_subt_module_XRegister_Q_reg_39_ ( .D(n1812), .CK(n5442), .RN(
n5298), .Q(add_subt_module_intDX[39]), .QN(n5143) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(
n2643), .CK(n5440), .RN(n5309), .Q(add_subt_module_Add_Subt_result[47]), .QN(n5142) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(n2532), .CK(n5351), .RN(n5512), .Q(
d_ff_Yn[62]), .QN(n5141) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n2508), .CK(n5343), .RN(n5507), .Q(
d_ff_Yn[56]), .QN(n5140) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(n2783), .CK(n3010), .RN(n5503),
.Q(d_ff2_X[52]), .QN(n5139) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(
n2639), .CK(n5347), .RN(n5308), .Q(add_subt_module_Add_Subt_result[43]), .QN(n5138) );
DFFRX1TS add_subt_module_XRegister_Q_reg_16_ ( .D(n1873), .CK(n5435), .RN(
n5293), .Q(add_subt_module_intDX[16]), .QN(n5137) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
n2616), .CK(n5446), .RN(n5306), .Q(add_subt_module_Add_Subt_result[20]), .QN(n5136) );
DFFRX1TS add_subt_module_YRegister_Q_reg_16_ ( .D(n1872), .CK(n5341), .RN(
n5293), .Q(add_subt_module_intDY[16]), .QN(n5134) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(
n2629), .CK(n5344), .RN(n5306), .Q(add_subt_module_Add_Subt_result[33]), .QN(n5133) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(
n2649), .CK(n5338), .RN(n5310), .Q(add_subt_module_Add_Subt_result[53]), .QN(n5132) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(
n2638), .CK(n5355), .RN(n5308), .Q(add_subt_module_Add_Subt_result[42]), .QN(n5131) );
DFFRX1TS add_subt_module_YRegister_Q_reg_23_ ( .D(n1797), .CK(n5443), .RN(
n5299), .Q(add_subt_module_intDY[23]), .QN(n5130) );
DFFRX1TS add_subt_module_YRegister_Q_reg_11_ ( .D(n1825), .CK(n5334), .RN(
n5297), .Q(add_subt_module_intDY[11]), .QN(n5129) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(
n2646), .CK(n5339), .RN(n5309), .Q(add_subt_module_Add_Subt_result[50]), .QN(n5128) );
DFFRX1TS add_subt_module_XRegister_Q_reg_46_ ( .D(n1877), .CK(n5437), .RN(
n5286), .Q(add_subt_module_intDX[46]), .QN(n5127) );
DFFRX1TS add_subt_module_XRegister_Q_reg_30_ ( .D(n1795), .CK(n5443), .RN(
n5299), .Q(add_subt_module_intDX[30]), .QN(n5126) );
DFFRX1TS add_subt_module_XRegister_Q_reg_21_ ( .D(n1766), .CK(n5361), .RN(
n5302), .Q(add_subt_module_intDX[21]), .QN(n5125) );
DFFRX1TS add_subt_module_XRegister_Q_reg_18_ ( .D(n1763), .CK(n5446), .RN(
n5302), .Q(add_subt_module_intDX[18]), .QN(n5124) );
DFFRX1TS add_subt_module_YRegister_Q_reg_25_ ( .D(n1759), .CK(n5360), .RN(
n5303), .Q(add_subt_module_intDY[25]), .QN(n5123) );
DFFRX1TS add_subt_module_YRegister_Q_reg_18_ ( .D(n1762), .CK(n5361), .RN(
n5302), .Q(add_subt_module_intDY[18]), .QN(n5122) );
DFFRX1TS add_subt_module_YRegister_Q_reg_21_ ( .D(n1765), .CK(n5334), .RN(
n5302), .Q(add_subt_module_intDY[21]), .QN(n5121) );
DFFRX1TS add_subt_module_XRegister_Q_reg_36_ ( .D(n1785), .CK(n5444), .RN(
n5300), .Q(add_subt_module_intDX[36]), .QN(n5120) );
DFFRX1TS add_subt_module_YRegister_Q_reg_36_ ( .D(n1784), .CK(n5444), .RN(
n5300), .Q(add_subt_module_intDY[36]), .QN(n5119) );
DFFRX1TS add_subt_module_YRegister_Q_reg_30_ ( .D(n1794), .CK(n5443), .RN(
n5300), .Q(add_subt_module_intDY[30]), .QN(n5118) );
DFFRX1TS add_subt_module_YRegister_Q_reg_19_ ( .D(n1803), .CK(n5443), .RN(
n5299), .Q(add_subt_module_intDY[19]), .QN(n5117) );
DFFRX1TS add_subt_module_XRegister_Q_reg_41_ ( .D(n1816), .CK(n5437), .RN(
n5298), .Q(add_subt_module_intDX[41]), .QN(n5116) );
DFFRX1TS add_subt_module_YRegister_Q_reg_42_ ( .D(n1822), .CK(n5435), .RN(
n5297), .Q(add_subt_module_intDY[42]), .QN(n5115) );
DFFRX1TS add_subt_module_YRegister_Q_reg_40_ ( .D(n1836), .CK(n5334), .RN(
n5296), .Q(add_subt_module_intDY[40]), .QN(n5114) );
DFFRX1TS add_subt_module_YRegister_Q_reg_9_ ( .D(n1869), .CK(n5437), .RN(
n5293), .Q(add_subt_module_intDY[9]), .QN(n5113) );
DFFRX1TS add_subt_module_YRegister_Q_reg_49_ ( .D(n1880), .CK(n5435), .RN(
n5292), .Q(add_subt_module_intDY[49]), .QN(n5112) );
DFFRX1TS d_ff4_Yn_Q_reg_63_ ( .D(n2666), .CK(n5343), .RN(n5513), .Q(
d_ff_Yn[63]), .QN(n5111) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n2384), .CK(n5410), .RN(n5467), .Q(
d_ff_Yn[25]), .QN(n5110) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(
n2642), .CK(n3009), .RN(n5309), .Q(add_subt_module_Add_Subt_result[46]), .QN(n5109) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
n2614), .CK(n5448), .RN(n5307), .Q(add_subt_module_Add_Subt_result[18]), .QN(n5108) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
n2602), .CK(n5346), .RN(n5309), .Q(add_subt_module_Add_Subt_result[6]),
.QN(n5107) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
n2609), .CK(n5346), .RN(n5308), .Q(add_subt_module_Add_Subt_result[13]), .QN(n5106) );
DFFRX1TS add_subt_module_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(
n1943), .CK(n5429), .RN(n5288), .Q(add_subt_module_sign_final_result),
.QN(n5105) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
n2601), .CK(n5347), .RN(n5309), .Q(add_subt_module_Add_Subt_result[5]),
.QN(n5104) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(
n2628), .CK(n5344), .RN(n5306), .Q(add_subt_module_Add_Subt_result[32]), .QN(n5103) );
DFFRX1TS add_subt_module_YRegister_Q_reg_58_ ( .D(n1953), .CK(n5426), .RN(
n3030), .Q(add_subt_module_intDY[58]), .QN(n5102) );
DFFRX1TS add_subt_module_XRegister_Q_reg_51_ ( .D(n1907), .CK(n5432), .RN(
n5287), .Q(add_subt_module_intDX[51]), .QN(n5101) );
DFFRX1TS add_subt_module_XRegister_Q_reg_9_ ( .D(n1870), .CK(n5436), .RN(
n5293), .Q(add_subt_module_intDX[9]), .QN(n5100) );
DFFRX1TS add_subt_module_XRegister_Q_reg_25_ ( .D(n1760), .CK(n5336), .RN(
n5302), .Q(add_subt_module_intDX[25]), .QN(n5099) );
DFFRX1TS add_subt_module_YRegister_Q_reg_29_ ( .D(n1769), .CK(n3262), .RN(
n5302), .Q(add_subt_module_intDY[29]), .QN(n5098) );
DFFRX1TS add_subt_module_XRegister_Q_reg_49_ ( .D(n1881), .CK(n5341), .RN(
n3033), .Q(add_subt_module_intDX[49]), .QN(n5097) );
DFFRX1TS add_subt_module_XRegister_Q_reg_57_ ( .D(n1927), .CK(n5430), .RN(
n5289), .Q(add_subt_module_intDX[57]), .QN(n5096) );
DFFRX1TS add_subt_module_XRegister_Q_reg_27_ ( .D(n1778), .CK(n5445), .RN(
n5301), .Q(add_subt_module_intDX[27]), .QN(n5095) );
DFFRX1TS add_subt_module_YRegister_Q_reg_27_ ( .D(n1777), .CK(n5445), .RN(
n5301), .Q(add_subt_module_intDY[27]), .QN(n5094) );
DFFRX1TS add_subt_module_YRegister_Q_reg_15_ ( .D(n1787), .CK(n5444), .RN(
n5300), .Q(add_subt_module_intDY[15]), .QN(n5093) );
DFFRX1TS add_subt_module_YRegister_Q_reg_46_ ( .D(n1876), .CK(n5341), .RN(
n3032), .Q(add_subt_module_intDY[46]), .QN(n5092) );
DFFRX1TS d_ff4_Yn_Q_reg_60_ ( .D(n2524), .CK(n5352), .RN(n5510), .Q(
d_ff_Yn[60]), .QN(n5091) );
DFFRX1TS d_ff4_Yn_Q_reg_52_ ( .D(n2492), .CK(n3010), .RN(n5504), .Q(
d_ff_Yn[52]), .QN(n5089) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_0_ ( .D(n2929), .CK(n5361),
.RN(n5274), .Q(add_subt_module_FS_Module_state_reg[0]), .QN(n5088) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
n2621), .CK(n5345), .RN(n5305), .Q(add_subt_module_Add_Subt_result[25]), .QN(n5087) );
DFFRX1TS add_subt_module_YRegister_Q_reg_1_ ( .D(n1883), .CK(n5341), .RN(
n5290), .Q(add_subt_module_intDY[1]), .QN(n5086) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n2791), .CK(n5353), .RN(n5510),
.Q(d_ff2_X[60]), .QN(n5085) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n2789), .CK(n5343), .RN(n5508),
.Q(d_ff2_X[58]), .QN(n5084) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
n2620), .CK(n5342), .RN(n5305), .Q(add_subt_module_Add_Subt_result[24]), .QN(n5083) );
DFFRX1TS add_subt_module_YRegister_Q_reg_51_ ( .D(n1906), .CK(n5432), .RN(
n5325), .Q(add_subt_module_intDY[51]), .QN(n5082) );
DFFRX1TS add_subt_module_YRegister_Q_reg_57_ ( .D(n1952), .CK(n5415), .RN(
n3030), .Q(add_subt_module_intDY[57]), .QN(n5081) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
n2612), .CK(n5446), .RN(n5307), .Q(add_subt_module_Add_Subt_result[16]), .QN(n5080) );
DFFRX1TS add_subt_module_XRegister_Q_reg_11_ ( .D(n1826), .CK(n5438), .RN(
n5297), .Q(add_subt_module_intDX[11]), .QN(n5079) );
DFFRX1TS add_subt_module_XRegister_Q_reg_23_ ( .D(n1798), .CK(n5443), .RN(
n5299), .Q(add_subt_module_intDX[23]), .QN(n5078) );
DFFRX1TS add_subt_module_XRegister_Q_reg_15_ ( .D(n1788), .CK(n5444), .RN(
n5300), .Q(add_subt_module_intDX[15]), .QN(n5077) );
DFFRX1TS add_subt_module_YRegister_Q_reg_13_ ( .D(n1849), .CK(n5348), .RN(
n5295), .Q(add_subt_module_intDY[13]), .QN(n5076) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_0_ ( .D(n2664), .CK(n5337), .RN(n1959),
.Q(add_subt_module_FSM_selector_B[0]), .QN(n5075) );
DFFRX1TS add_subt_module_YRegister_Q_reg_39_ ( .D(n1811), .CK(n5442), .RN(
n5298), .Q(add_subt_module_intDY[39]), .QN(n5074) );
DFFRX1TS add_subt_module_XRegister_Q_reg_1_ ( .D(n1884), .CK(n5436), .RN(
n3030), .Q(add_subt_module_intDX[1]), .QN(n5073) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(
n2562), .CK(n5426), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[27]), .QN(n5072) );
DFFRX1TS add_subt_module_YRegister_Q_reg_6_ ( .D(n1862), .CK(n5436), .RN(
n5294), .Q(add_subt_module_intDY[6]), .QN(n5071) );
DFFRX1TS add_subt_module_YRegister_Q_reg_44_ ( .D(n1866), .CK(n5441), .RN(
n5293), .Q(add_subt_module_intDY[44]), .QN(n5070) );
DFFRX1TS add_subt_module_XRegister_Q_reg_54_ ( .D(n1918), .CK(n5431), .RN(
n5289), .Q(add_subt_module_intDX[54]), .QN(n5069) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n2925), .CK(n5374), .RN(n5529), .Q(
cont_var_out[1]), .QN(n5068) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_2_ ( .D(n2927), .CK(n5448),
.RN(n5274), .Q(add_subt_module_FS_Module_state_reg[2]), .QN(n5067) );
DFFRX1TS add_subt_module_XRegister_Q_reg_32_ ( .D(n1749), .CK(n5361), .RN(
n5303), .Q(add_subt_module_intDX[32]), .QN(n5066) );
DFFRX1TS add_subt_module_YRegister_Q_reg_4_ ( .D(n1903), .CK(n5433), .RN(
n5292), .Q(add_subt_module_intDY[4]), .QN(n5065) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
n2605), .CK(n5346), .RN(n5308), .Q(add_subt_module_Add_Subt_result[9]),
.QN(n5064) );
DFFRX1TS add_subt_module_XRegister_Q_reg_2_ ( .D(n1897), .CK(n5433), .RN(
n3028), .Q(add_subt_module_intDX[2]), .QN(n5063) );
DFFRX1TS add_subt_module_XRegister_Q_reg_34_ ( .D(n1801), .CK(n5443), .RN(
n5299), .Q(add_subt_module_intDX[34]), .QN(n5062) );
DFFRX2TS add_subt_module_YRegister_Q_reg_0_ ( .D(n1958), .CK(n3265), .RN(
n3278), .QN(n5061) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n2939), .CK(n5421), .RN(n5274),
.Q(cordic_FSM_state_reg[2]), .QN(n5060) );
DFFRX2TS add_subt_module_YRegister_Q_reg_60_ ( .D(n1955), .CK(n5427), .RN(
n5325), .QN(n5059) );
DFFRX2TS add_subt_module_YRegister_Q_reg_62_ ( .D(n1957), .CK(n5440), .RN(
n5287), .QN(n5058) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(
n2633), .CK(n5350), .RN(n5307), .Q(add_subt_module_Add_Subt_result[37]), .QN(n5055) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ (
.D(n2936), .CK(n5345), .RN(n5310), .Q(
add_subt_module_add_overflow_flag), .QN(n5054) );
DFFRX1TS add_subt_module_XRegister_Q_reg_29_ ( .D(n1770), .CK(n5427), .RN(
n5302), .Q(add_subt_module_intDX[29]), .QN(n5052) );
DFFRX1TS add_subt_module_YRegister_Q_reg_41_ ( .D(n1815), .CK(n5341), .RN(
n5298), .Q(add_subt_module_intDY[41]), .QN(n5051) );
DFFRX1TS add_subt_module_XRegister_Q_reg_42_ ( .D(n1823), .CK(n5436), .RN(
n5297), .Q(add_subt_module_intDX[42]), .QN(n5050) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ (
.D(n2933), .CK(n5349), .RN(n5275), .Q(result_add_subt[63]), .QN(n5049)
);
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ (
.D(n2386), .CK(n5410), .RN(n5284), .Q(result_add_subt[25]), .QN(n5048)
);
DFFRX1TS add_subt_module_XRegister_Q_reg_58_ ( .D(n1930), .CK(n5430), .RN(
n5289), .Q(add_subt_module_intDX[58]), .QN(n5047) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_60_ ( .D(n2106), .CK(n5353), .RN(n5510),
.Q(d_ff2_Y[60]), .QN(n5046) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(n2108), .CK(n5354), .RN(n5508),
.Q(d_ff2_Y[58]), .QN(n5045) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n2114), .CK(n3010), .RN(n5504),
.Q(d_ff2_Y[52]), .QN(n5044) );
DFFRX1TS add_subt_module_XRegister_Q_reg_19_ ( .D(n1804), .CK(n5442), .RN(
n5299), .Q(add_subt_module_intDX[19]), .QN(n5043) );
DFFRX1TS add_subt_module_YRegister_Q_reg_20_ ( .D(n1852), .CK(n5420), .RN(
n5294), .Q(add_subt_module_intDY[20]), .QN(n5042) );
DFFRX1TS add_subt_module_YRegister_Q_reg_45_ ( .D(n1856), .CK(n5441), .RN(
n5294), .Q(add_subt_module_intDY[45]), .QN(n5041) );
DFFRX1TS add_subt_module_XRegister_Q_reg_53_ ( .D(n1915), .CK(n5431), .RN(
n5289), .Q(add_subt_module_intDX[53]), .QN(n5040) );
DFFRX1TS add_subt_module_YRegister_Q_reg_50_ ( .D(n1893), .CK(n5441), .RN(
n5291), .Q(add_subt_module_intDY[50]), .QN(n5039) );
DFFRX1TS add_subt_module_YRegister_Q_reg_56_ ( .D(n1951), .CK(n5423), .RN(
n5290), .Q(add_subt_module_intDY[56]), .QN(n5038) );
DFFRX1TS add_subt_module_XRegister_Q_reg_10_ ( .D(n1847), .CK(n5438), .RN(
n5295), .Q(add_subt_module_intDX[10]), .QN(n5037) );
DFFRX1TS add_subt_module_YRegister_Q_reg_59_ ( .D(n1954), .CK(n5394), .RN(
n3033), .Q(add_subt_module_intDY[59]), .QN(n5036) );
DFFRX1TS add_subt_module_YRegister_Q_reg_37_ ( .D(n1808), .CK(n5442), .RN(
n5298), .Q(add_subt_module_intDY[37]), .QN(n5035) );
DFFRX1TS add_subt_module_YRegister_Q_reg_43_ ( .D(n1843), .CK(n5348), .RN(
n5295), .Q(add_subt_module_intDY[43]), .QN(n5034) );
DFFRX1TS add_subt_module_YRegister_Q_reg_5_ ( .D(n1859), .CK(n5437), .RN(
n5294), .Q(add_subt_module_intDY[5]), .QN(n5033) );
DFFRX1TS add_subt_module_YRegister_Q_reg_7_ ( .D(n1839), .CK(n5440), .RN(
n5296), .Q(add_subt_module_intDY[7]), .QN(n5032) );
DFFRX2TS add_subt_module_XRegister_Q_reg_12_ ( .D(n1829), .CK(n5334), .RN(
n5296), .Q(add_subt_module_intDX[12]), .QN(n5031) );
DFFRX2TS add_subt_module_XRegister_Q_reg_47_ ( .D(n1891), .CK(n5434), .RN(
n5291), .Q(add_subt_module_intDX[47]), .QN(n5030) );
DFFRX2TS add_subt_module_YRegister_Q_reg_48_ ( .D(n1900), .CK(n5433), .RN(
n5286), .QN(n5029) );
DFFRX2TS add_subt_module_XRegister_Q_reg_55_ ( .D(n1921), .CK(n5431), .RN(
n5289), .Q(add_subt_module_intDX[55]), .QN(n5028) );
DFFRX2TS add_subt_module_XRegister_Q_reg_3_ ( .D(n1887), .CK(n5434), .RN(
n5291), .Q(add_subt_module_intDX[3]), .QN(n5027) );
DFFRX2TS add_subt_module_YRegister_Q_reg_8_ ( .D(n1818), .CK(n5435), .RN(
n5297), .Q(add_subt_module_intDY[8]), .QN(n5026) );
DFFRX2TS add_subt_module_YRegister_Q_reg_61_ ( .D(n1956), .CK(n5414), .RN(
n5292), .QN(n5025) );
DFFRX2TS cordic_FSM_state_reg_reg_3_ ( .D(n2940), .CK(n5374), .RN(n5274),
.Q(cordic_FSM_state_reg[3]), .QN(n5024) );
DFFRX1TS add_subt_module_XRegister_Q_reg_26_ ( .D(n1735), .CK(n5449), .RN(
n5305), .Q(add_subt_module_intDX[26]), .QN(n5022) );
DFFRX1TS add_subt_module_YRegister_Q_reg_28_ ( .D(n1738), .CK(n5449), .RN(
n5304), .Q(add_subt_module_intDY[28]), .QN(n5021) );
DFFRX1TS add_subt_module_XRegister_Q_reg_52_ ( .D(n1912), .CK(n5432), .RN(
n5289), .Q(add_subt_module_intDX[52]), .QN(n5020) );
DFFRX1TS add_subt_module_YRegister_Q_reg_14_ ( .D(n1780), .CK(n5445), .RN(
n5301), .Q(add_subt_module_intDY[14]), .QN(n5019) );
DFFRX1TS add_subt_module_XRegister_Q_reg_22_ ( .D(n1742), .CK(n5449), .RN(
n5304), .Q(add_subt_module_intDX[22]), .QN(n5018) );
DFFRX1TS add_subt_module_XRegister_Q_reg_33_ ( .D(n1756), .CK(n5448), .RN(
n5303), .Q(add_subt_module_intDX[33]), .QN(n5017) );
DFFRX1TS add_subt_module_XRegister_Q_reg_35_ ( .D(n1792), .CK(n5444), .RN(
n5300), .Q(add_subt_module_intDX[35]), .QN(n5016) );
DFFRX1TS add_subt_module_YRegister_Q_reg_38_ ( .D(n1832), .CK(n3262), .RN(
n5296), .Q(add_subt_module_intDY[38]), .QN(n5015) );
DFFRX2TS add_subt_module_YRegister_Q_reg_17_ ( .D(n1751), .CK(n5345), .RN(
n5303), .Q(add_subt_module_intDY[17]), .QN(n5014) );
DFFRX2TS add_subt_module_YRegister_Q_reg_24_ ( .D(n1744), .CK(n5342), .RN(
n5304), .Q(add_subt_module_intDY[24]), .QN(n5013) );
DFFRX2TS add_subt_module_YRegister_Q_reg_31_ ( .D(n1773), .CK(n5420), .RN(
n5301), .Q(add_subt_module_intDY[31]), .QN(n5012) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n2938), .CK(n5347), .RN(n5274),
.Q(cordic_FSM_state_reg[0]), .QN(n5011) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_3_ ( .D(n2930), .CK(n5342),
.RN(n5274), .Q(add_subt_module_FS_Module_state_reg[3]), .QN(n5010) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
n2613), .CK(n5427), .RN(n5307), .Q(add_subt_module_Add_Subt_result[17]), .QN(n5008) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]),
.CK(n5382), .RN(n5278), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]),
.CK(n5411), .RN(n3028), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]),
.CK(n5424), .RN(n5290), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]),
.CK(n5342), .RN(n5276), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]),
.CK(n5377), .RN(n5277), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]),
.CK(n5370), .RN(n5277), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]),
.CK(n5370), .RN(n5279), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]),
.CK(n5422), .RN(n5290), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n1961), .CK(n5356), .RN(n5512), .Q(
data_output[63]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n1964), .CK(n5351), .RN(n5511), .Q(
data_output[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n1966), .CK(n5352), .RN(n5510), .Q(
data_output[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n1968), .CK(n5353), .RN(n5510), .Q(
data_output[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n1970), .CK(n5354), .RN(n5509), .Q(
data_output[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n1972), .CK(n5349), .RN(n5508), .Q(
data_output[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n1974), .CK(n5356), .RN(n5507), .Q(
data_output[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n1976), .CK(n5357), .RN(n5506), .Q(
data_output[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n1978), .CK(n5357), .RN(n5506), .Q(
data_output[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n1980), .CK(n5358), .RN(n5505), .Q(
data_output[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n1982), .CK(n5359), .RN(n5504), .Q(
data_output[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n1984), .CK(n3010), .RN(n5503), .Q(
data_output[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n1992), .CK(n5365), .RN(n5500), .Q(
data_output[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n1994), .CK(n5375), .RN(n5498), .Q(
data_output[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n1990), .CK(n5380), .RN(n5495), .Q(
data_output[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n1996), .CK(n3271), .RN(n5494), .Q(
data_output[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n2000), .CK(n5376), .RN(n5491), .Q(
data_output[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n1998), .CK(n3269), .RN(n5489), .Q(
data_output[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n2002), .CK(n2996), .RN(n5485), .Q(
data_output[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n2008), .CK(n5385), .RN(n5484), .Q(
data_output[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n2012), .CK(n5389), .RN(n5483), .Q(
data_output[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n2004), .CK(n3256), .RN(n5482), .Q(
data_output[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n2006), .CK(n5392), .RN(n5480), .Q(
data_output[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n2014), .CK(n5389), .RN(n5478), .Q(
data_output[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n2010), .CK(n5388), .RN(n5478), .Q(
data_output[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n2018), .CK(n5398), .RN(n5474), .Q(
data_output[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n2016), .CK(n5394), .RN(n5472), .Q(
data_output[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n2034), .CK(n5405), .RN(n5470), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n2026), .CK(n5407), .RN(n5469), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n2030), .CK(n5408), .RN(n5468), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n2038), .CK(n5410), .RN(n5466), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n2022), .CK(n5413), .RN(n5465), .Q(
data_output[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n2024), .CK(n5428), .RN(n5463), .Q(
data_output[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n2032), .CK(n5419), .RN(n5460), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n2036), .CK(n3265), .RN(n5459), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n2044), .CK(n5414), .RN(n5459), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n2040), .CK(n3260), .RN(n5459), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n2054), .CK(n3259), .RN(n5459), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n2052), .CK(n5334), .RN(n5459), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n2046), .CK(n5447), .RN(n5458), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n2060), .CK(n5414), .RN(n5458), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n2058), .CK(n5428), .RN(n5458), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n2028), .CK(n5428), .RN(n5458), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n2042), .CK(n5410), .RN(n5458), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n2020), .CK(n5428), .RN(n5457), .Q(
data_output[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n2050), .CK(n5428), .RN(n5457), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n2072), .CK(n5411), .RN(n5457), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n2066), .CK(n5422), .RN(n5457), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n2064), .CK(n3263), .RN(n5457), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n2074), .CK(n5410), .RN(n5456), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n2068), .CK(n5415), .RN(n5456), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n2062), .CK(n3263), .RN(n5456), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n2048), .CK(n5423), .RN(n5456), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n2078), .CK(n3263), .RN(n5456), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n2076), .CK(n5422), .RN(n5455), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n2070), .CK(n5422), .RN(n5455), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n2056), .CK(n5423), .RN(n5455), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n2086), .CK(n5424), .RN(n5455), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n2082), .CK(n5426), .RN(n5455), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n1988), .CK(n5428), .RN(n5454), .Q(
data_output[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n2084), .CK(n5426), .RN(n5454), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n2080), .CK(n5415), .RN(n5454), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n1986), .CK(n5428), .RN(n5454), .Q(
data_output[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n2088), .CK(n5440), .RN(n5454), .Q(
data_output[0]) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n2091), .CK(n5349), .RN(n5513), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n2917), .CK(n5403), .RN(n5528), .Q(
d_ff1_Z[62]) );
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n2916), .CK(n5327), .RN(n5528), .Q(
d_ff1_Z[61]) );
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n2915), .CK(n3261), .RN(n5528), .Q(
d_ff1_Z[60]) );
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n2914), .CK(n5373), .RN(n5528), .Q(
d_ff1_Z[59]) );
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n2913), .CK(n5328), .RN(n5528), .Q(
d_ff1_Z[58]) );
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n2912), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[57]) );
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n2911), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[56]) );
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n2910), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[55]) );
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n2909), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[54]) );
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n2908), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[53]) );
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n2907), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[52]) );
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n2906), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[51]) );
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n2905), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[50]) );
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n2904), .CK(n5328), .RN(n5527), .Q(
d_ff1_Z[49]) );
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n2903), .CK(n5326), .RN(n5527), .Q(
d_ff1_Z[48]) );
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n2902), .CK(n5374), .RN(n5526), .Q(
d_ff1_Z[47]) );
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n2901), .CK(n5347), .RN(n5526), .Q(
d_ff1_Z[46]) );
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n2900), .CK(n5326), .RN(n5526), .Q(
d_ff1_Z[45]) );
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n2899), .CK(n5356), .RN(n5526), .Q(
d_ff1_Z[44]) );
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n2898), .CK(n5374), .RN(n5526), .Q(
d_ff1_Z[43]) );
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n2897), .CK(n5356), .RN(n5526), .Q(
d_ff1_Z[42]) );
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n2896), .CK(n5347), .RN(n5526), .Q(
d_ff1_Z[41]) );
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n2895), .CK(n5326), .RN(n5526), .Q(
d_ff1_Z[40]) );
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n2894), .CK(n5326), .RN(n5526), .Q(
d_ff1_Z[39]) );
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n2893), .CK(n3261), .RN(n5526), .Q(
d_ff1_Z[38]) );
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n2892), .CK(n5373), .RN(n5525), .Q(
d_ff1_Z[37]) );
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n2891), .CK(n5349), .RN(n5525), .Q(
d_ff1_Z[36]) );
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n2890), .CK(n5327), .RN(n5525), .Q(
d_ff1_Z[35]) );
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n2889), .CK(n3261), .RN(n5525), .Q(
d_ff1_Z[34]) );
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n2888), .CK(n5373), .RN(n5525), .Q(
d_ff1_Z[33]) );
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n2887), .CK(n5349), .RN(n5525), .Q(
d_ff1_Z[32]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n2886), .CK(n5327), .RN(n5525), .Q(
d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n2885), .CK(n3261), .RN(n5525), .Q(
d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n2884), .CK(n5327), .RN(n5525), .Q(
d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n2883), .CK(n5331), .RN(n5525), .Q(
d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n2882), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n2881), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n2880), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n2879), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n2878), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n2877), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n2876), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n2875), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n2874), .CK(n5331), .RN(n5524), .Q(
d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n2873), .CK(n5447), .RN(n5524), .Q(
d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n2872), .CK(n5336), .RN(n5523), .Q(
d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n2871), .CK(n5440), .RN(n5523), .Q(
d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n2870), .CK(n5336), .RN(n5523), .Q(
d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n2869), .CK(n5332), .RN(n5523), .Q(
d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n2868), .CK(n5332), .RN(n5523), .Q(
d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n2867), .CK(n5332), .RN(n5523), .Q(
d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n2866), .CK(n5332), .RN(n5523), .Q(
d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n2865), .CK(n5332), .RN(n5523), .Q(
d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n2864), .CK(n5332), .RN(n5523), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n2863), .CK(n5333), .RN(n5523), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n2862), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n2861), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n2860), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n2859), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n2858), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n2857), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n2856), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n2855), .CK(n5333), .RN(n5522), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n2854), .CK(n5333), .RN(n5522), .Q(
d_ff1_Z[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n2794), .CK(n5355), .RN(n5513), .Q(
d_ff3_sh_x_out[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n2665), .CK(n5350), .RN(n5512), .Q(
d_ff_Zn[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n2533), .CK(n5373), .RN(n5512), .Q(
d_ff_Zn[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n2529), .CK(n5351), .RN(n5511), .Q(
d_ff_Zn[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n2525), .CK(n5352), .RN(n5510), .Q(
d_ff_Zn[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n2521), .CK(n5353), .RN(n5510), .Q(
d_ff_Zn[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n2517), .CK(n5354), .RN(n5509), .Q(
d_ff_Zn[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n2513), .CK(n5343), .RN(n5508), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n2509), .CK(n5355), .RN(n5507), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n2505), .CK(n5357), .RN(n5506), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n2501), .CK(n5358), .RN(n5506), .Q(
d_ff_Zn[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n2497), .CK(n5359), .RN(n5505), .Q(
d_ff_Zn[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n2493), .CK(n5359), .RN(n5504), .Q(
d_ff_Zn[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n2285), .CK(n3010), .RN(n5503), .Q(
d_ff_Zn[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n2489), .CK(n5361), .RN(n5503), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n2301), .CK(n3266), .RN(n5502), .Q(
d_ff_Zn[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n2477), .CK(n5368), .RN(n5501), .Q(
d_ff_Zn[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n2293), .CK(n5363), .RN(n5500), .Q(
d_ff_Zn[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n2485), .CK(n5368), .RN(n5499), .Q(
d_ff_Zn[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n2473), .CK(n5380), .RN(n5499), .Q(
d_ff_Zn[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n2297), .CK(n5366), .RN(n5498), .Q(
d_ff_Zn[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n2289), .CK(n5385), .RN(n5497), .Q(
d_ff_Zn[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n2481), .CK(n5364), .RN(n5496), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n2469), .CK(n5379), .RN(n5531), .Q(
d_ff_Zn[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n2349), .CK(n3271), .RN(n5494), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n2321), .CK(n5347), .RN(n5493), .Q(
d_ff_Zn[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n2461), .CK(n5366), .RN(n3031), .Q(
d_ff_Zn[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n2309), .CK(n5376), .RN(n5491), .Q(
d_ff_Zn[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n2305), .CK(n5378), .RN(n5491), .Q(
d_ff_Zn[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n2465), .CK(n5375), .RN(n5490), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n2365), .CK(n5367), .RN(n5489), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n2337), .CK(n5381), .RN(n5488), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n2325), .CK(n2996), .RN(n5487), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n2457), .CK(n5369), .RN(n5486), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n2313), .CK(n3273), .RN(n5485), .Q(
d_ff_Zn[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n2445), .CK(n5369), .RN(n5485), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n2437), .CK(n5395), .RN(n5484), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n2333), .CK(n5388), .RN(n5483), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n2329), .CK(n5386), .RN(n3031), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n2317), .CK(n3265), .RN(n5482), .Q(
d_ff_Zn[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n2449), .CK(n5392), .RN(n5481), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n2441), .CK(n5393), .RN(n5480), .Q(
d_ff_Zn[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n2433), .CK(n5397), .RN(n5479), .Q(
d_ff_Zn[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n2361), .CK(n5386), .RN(n5478), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n2421), .CK(n3256), .RN(n5477), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n2377), .CK(n5401), .RN(n5477), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n2405), .CK(n5404), .RN(n5476), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n2425), .CK(n3257), .RN(n5475), .Q(
d_ff_Zn[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n2345), .CK(n5404), .RN(n5474), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n2429), .CK(n5388), .RN(n5473), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n2341), .CK(n5390), .RN(n5472), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n2393), .CK(n5399), .RN(n5471), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n2409), .CK(n5406), .RN(n5470), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n2401), .CK(n5407), .RN(n5469), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n2369), .CK(n5408), .RN(n5468), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n2357), .CK(n5409), .RN(n5468), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n2385), .CK(n5411), .RN(n5467), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n2417), .CK(n5412), .RN(n5466), .Q(
d_ff_Zn[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n2353), .CK(n5413), .RN(n5465), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n2413), .CK(n3260), .RN(n5464), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n2381), .CK(n5415), .RN(n5463), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n2373), .CK(n5417), .RN(n5462), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n2397), .CK(n5438), .RN(n5461), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n2389), .CK(n5419), .RN(n5460), .Q(
d_ff_Zn[26]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ (
.D(n2592), .CK(n5439), .RN(n5274), .Q(add_subt_module_LZA_output[0])
);
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n2795), .CK(n3009), .RN(n5516), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS add_subt_module_ASRegister_Q_reg_0_ ( .D(n1944), .CK(n5423), .RN(
n5288), .Q(add_subt_module_intAS) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n2834), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n2829), .CK(n5336), .RN(n5519), .Q(
d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n2827), .CK(n5338), .RN(n5519), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n2850), .CK(n5439), .RN(n5522), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n2097), .CK(n5340), .RN(n5516), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n2100), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n2101), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n2102), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n2103), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n2779), .CK(n5434), .RN(n5514), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n2780), .CK(n5434), .RN(n5514), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n2781), .CK(n5434), .RN(n5514), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n2782), .CK(n5434), .RN(n5514), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n2115), .CK(n5361), .RN(n5502), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n2209), .CK(n5365), .RN(n5502), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n2676), .CK(n5379), .RN(n5501), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n2121), .CK(n5366), .RN(n5501), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n2213), .CK(n5375), .RN(n5500), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n2672), .CK(n5368), .RN(n5499), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n2117), .CK(n5375), .RN(n5499), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n2768), .CK(n5366), .RN(n5499), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n2123), .CK(n3271), .RN(n5498), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n2762), .CK(n5370), .RN(n5498), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n2211), .CK(n3273), .RN(n5497), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n2674), .CK(n2996), .RN(n5497), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n2215), .CK(n5372), .RN(n5496), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n2670), .CK(n5375), .RN(n5496), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n2119), .CK(n3271), .RN(n5496), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n2766), .CK(n3269), .RN(n5492), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n2125), .CK(n5365), .RN(n5495), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n2760), .CK(n5365), .RN(n5494), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n2185), .CK(n5367), .RN(n5494), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n2700), .CK(n5380), .RN(n5493), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n2199), .CK(n5364), .RN(n5493), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n2686), .CK(n5372), .RN(n3276), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n2129), .CK(n5376), .RN(n5492), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n2756), .CK(n5376), .RN(n5495), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n2205), .CK(n5379), .RN(n5491), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n2680), .CK(n5377), .RN(n5491), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n2207), .CK(n5378), .RN(n5490), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n2678), .CK(n5378), .RN(n5490), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n2127), .CK(n5377), .RN(n5489), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n2758), .CK(n5377), .RN(n5489), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n2177), .CK(n5327), .RN(n5488), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n2708), .CK(n5381), .RN(n5488), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n2191), .CK(n5381), .RN(n5488), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n2694), .CK(n5382), .RN(n5487), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n2197), .CK(n5382), .RN(n5487), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n2131), .CK(n3273), .RN(n5486), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n2754), .CK(n5383), .RN(n5486), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n2203), .CK(n5384), .RN(n5485), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n2137), .CK(n5382), .RN(n5484), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n2748), .CK(n5384), .RN(n5484), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n2141), .CK(n5389), .RN(n5483), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n2744), .CK(n5386), .RN(n5483), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n2193), .CK(n5387), .RN(n5530), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n2692), .CK(n5387), .RN(n3277), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n2195), .CK(n5402), .RN(n5530), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n2690), .CK(n5395), .RN(n5530), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n2752), .CK(n5396), .RN(n5482), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n2201), .CK(n5391), .RN(n5482), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n2684), .CK(n5401), .RN(n5481), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n2135), .CK(n5392), .RN(n5481), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n2139), .CK(n5402), .RN(n5480), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n2143), .CK(n5420), .RN(n5479), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n2742), .CK(n5387), .RN(n5479), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n2179), .CK(n5447), .RN(n5478), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n2706), .CK(n5390), .RN(n5477), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n2149), .CK(n3256), .RN(n5477), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n2171), .CK(n5400), .RN(n5476), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n2714), .CK(n5399), .RN(n5476), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n2157), .CK(n5391), .RN(n5475), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n2728), .CK(n3257), .RN(n5475), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n2147), .CK(n5400), .RN(n5475), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n2738), .CK(n5391), .RN(n5474), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n2187), .CK(n5401), .RN(n5474), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n2698), .CK(n5386), .RN(n5473), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n2145), .CK(n3256), .RN(n5473), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n2740), .CK(n5396), .RN(n5472), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n2189), .CK(n5398), .RN(n5472), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n2696), .CK(n5404), .RN(n5471), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n2163), .CK(n5405), .RN(n5471), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n2722), .CK(n5405), .RN(n5471), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n2155), .CK(n5406), .RN(n5470), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n2159), .CK(n5408), .RN(n5469), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n2726), .CK(n5408), .RN(n5469), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n2175), .CK(n5409), .RN(n5468), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n2181), .CK(n5424), .RN(n5467), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n2167), .CK(n5422), .RN(n5466), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n2718), .CK(n3263), .RN(n5466), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n2151), .CK(n5412), .RN(n5465), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n2734), .CK(n5412), .RN(n5465), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n2183), .CK(n5413), .RN(n5464), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n2702), .CK(n3260), .RN(n5464), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n2153), .CK(n3260), .RN(n5464), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n2169), .CK(n5416), .RN(n5463), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n2716), .CK(n5416), .RN(n5462), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n2173), .CK(n5417), .RN(n5462), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n2161), .CK(n3266), .RN(n5461), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n2724), .CK(n5336), .RN(n5461), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n2165), .CK(n5419), .RN(n5460), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n2720), .CK(n5383), .RN(n5460), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n2217), .CK(n5418), .RN(n5454), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_LUT_Q_reg_30_ ( .D(n2825), .CK(n5337), .RN(n5519), .Q(
d_ff3_LUT_out[30]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n2811), .CK(n5420), .RN(n5518), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n2799), .CK(n3009), .RN(n5516), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_43_ ( .D(n2838), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[43]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n2813), .CK(n5338), .RN(n5518), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n2093), .CK(n5359), .RN(n5516), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n2095), .CK(n5359), .RN(n5516), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1926), .CK(n5430), .RN(n5322), .Q(add_subt_module_DmP[57]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1923), .CK(n5431), .RN(n5322), .Q(add_subt_module_DmP[56]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1920), .CK(n5431), .RN(n5322), .Q(add_subt_module_DmP[55]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1917), .CK(n5431), .RN(n5321), .Q(add_subt_module_DmP[54]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1914), .CK(n5431), .RN(n5321), .Q(add_subt_module_DmP[53]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n2836), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[41]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n2098), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(n1965), .CK(n5351), .RN(n5511), .Q(
sign_inv_out[62]) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(n1967), .CK(n5352), .RN(n5511), .Q(
sign_inv_out[61]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(n1969), .CK(n5353), .RN(n5510), .Q(
sign_inv_out[60]) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(n1971), .CK(n5354), .RN(n5509), .Q(
sign_inv_out[59]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(n1973), .CK(n5421), .RN(n5508), .Q(
sign_inv_out[58]) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(n1975), .CK(n5374), .RN(n5507), .Q(
sign_inv_out[57]) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(n1977), .CK(n5347), .RN(n5507), .Q(
sign_inv_out[56]) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(n1979), .CK(n5357), .RN(n5506), .Q(
sign_inv_out[55]) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(n1981), .CK(n5358), .RN(n5505), .Q(
sign_inv_out[54]) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(n1983), .CK(n5359), .RN(n5504), .Q(
sign_inv_out[53]) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(n1985), .CK(n3010), .RN(n5503), .Q(
sign_inv_out[52]) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(n1993), .CK(n5370), .RN(n5500), .Q(
sign_inv_out[48]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(n1995), .CK(n5365), .RN(n5498), .Q(
sign_inv_out[47]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(n1991), .CK(n5367), .RN(n5531), .Q(
sign_inv_out[49]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(n1997), .CK(n3269), .RN(n5494), .Q(
sign_inv_out[46]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(n2001), .CK(n5376), .RN(n5531), .Q(
sign_inv_out[44]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(n1999), .CK(n5372), .RN(n5489), .Q(
sign_inv_out[45]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(n2003), .CK(n5383), .RN(n5486), .Q(
sign_inv_out[43]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(n2009), .CK(n5385), .RN(n5484), .Q(
sign_inv_out[40]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(n2013), .CK(n5393), .RN(n5483), .Q(
sign_inv_out[38]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(n2005), .CK(n5397), .RN(n5482), .Q(
sign_inv_out[42]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(n2007), .CK(n5392), .RN(n5480), .Q(
sign_inv_out[41]) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(n2015), .CK(n5393), .RN(n5479), .Q(
sign_inv_out[37]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(n2011), .CK(n5402), .RN(n5478), .Q(
sign_inv_out[39]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(n2019), .CK(n5401), .RN(n5474), .Q(
sign_inv_out[35]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(n2017), .CK(n3265), .RN(n5472), .Q(
sign_inv_out[36]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n2035), .CK(n5405), .RN(n5471), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n2027), .CK(n5406), .RN(n5470), .Q(
sign_inv_out[31]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n2031), .CK(n5408), .RN(n5469), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n2039), .CK(n5423), .RN(n5466), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(n2023), .CK(n5413), .RN(n5465), .Q(
sign_inv_out[33]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(n2025), .CK(n5425), .RN(n5463), .Q(
sign_inv_out[32]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n2033), .CK(n5414), .RN(n5461), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n2037), .CK(n3265), .RN(n5460), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n2045), .CK(n5394), .RN(n5459), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n2041), .CK(n5414), .RN(n5459), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n2055), .CK(n5418), .RN(n5459), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n2053), .CK(n3260), .RN(n5459), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n2047), .CK(n5348), .RN(n5459), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n2061), .CK(n3265), .RN(n5458), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n2059), .CK(n5424), .RN(n5458), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n2029), .CK(n5423), .RN(n5458), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n2043), .CK(n5415), .RN(n5458), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(n2021), .CK(n5411), .RN(n5458), .Q(
sign_inv_out[34]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n2051), .CK(n5425), .RN(n5457), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n2073), .CK(n5426), .RN(n5457), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n2067), .CK(n5424), .RN(n5457), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n2065), .CK(n5423), .RN(n5457), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n2075), .CK(n5410), .RN(n5457), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n2069), .CK(n5426), .RN(n5456), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n2063), .CK(n5415), .RN(n5456), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n2049), .CK(n5422), .RN(n5456), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n2079), .CK(n5410), .RN(n5456), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n2077), .CK(n5424), .RN(n5456), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n2071), .CK(n5426), .RN(n5455), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n2057), .CK(n5411), .RN(n5455), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n2087), .CK(n5425), .RN(n5455), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n2083), .CK(n5425), .RN(n5455), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(n1989), .CK(n5425), .RN(n5455), .Q(
sign_inv_out[50]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n2085), .CK(n5426), .RN(n5454), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n2081), .CK(n5424), .RN(n5454), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(n1987), .CK(n5415), .RN(n5454), .Q(
sign_inv_out[51]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n2089), .CK(n3259), .RN(n5454), .Q(
sign_inv_out[0]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n2817), .CK(n5337), .RN(n5518), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n2804), .CK(n5337), .RN(n5517), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n2800), .CK(n5359), .RN(n5517), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n2820), .CK(n5339), .RN(n5519), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_49_ ( .D(n2844), .CK(n5439), .RN(n5521), .Q(
d_ff3_LUT_out[49]) );
DFFRXLTS reg_LUT_Q_reg_46_ ( .D(n2841), .CK(n5439), .RN(n5521), .Q(
d_ff3_LUT_out[46]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n2839), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_38_ ( .D(n2833), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[38]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n2824), .CK(n5339), .RN(n5519), .Q(
d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n2815), .CK(n3009), .RN(n5518), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n2846), .CK(n5439), .RN(n5521), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n2776), .CK(n5434), .RN(n5514), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n2668), .CK(n5439), .RN(n5513), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n2770), .CK(n5362), .RN(n5502), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n2764), .CK(n5363), .RN(n5500), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n2688), .CK(n3273), .RN(n5486), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n2682), .CK(n5384), .RN(n5485), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n2750), .CK(n5392), .RN(n5480), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n2746), .CK(n5390), .RN(n5479), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n2736), .CK(n5396), .RN(n5477), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n2730), .CK(n5406), .RN(n5470), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n2710), .CK(n5409), .RN(n5468), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n2704), .CK(n5415), .RN(n5467), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n2732), .CK(n3263), .RN(n5463), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n2712), .CK(n5417), .RN(n5461), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n2802), .CK(n5339), .RN(n5517), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_40_ ( .D(n2835), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[40]) );
DFFRXLTS reg_LUT_Q_reg_36_ ( .D(n2831), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[36]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n2823), .CK(n5440), .RN(n5519), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n2772), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n2774), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n2094), .CK(n5359), .RN(n5516), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n2096), .CK(n5359), .RN(n5516), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n2816), .CK(n3009), .RN(n5518), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n2805), .CK(n5394), .RN(n5517), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1911), .CK(n5432), .RN(n5289), .Q(add_subt_module_DmP[52]) );
DFFRX1TS reg_LUT_Q_reg_31_ ( .D(n2826), .CK(n5447), .RN(n5519), .Q(
d_ff3_LUT_out[31]) );
DFFRX1TS reg_LUT_Q_reg_54_ ( .D(n2848), .CK(n5360), .RN(n5521), .Q(
d_ff3_LUT_out[54]) );
DFFRX1TS reg_LUT_Q_reg_45_ ( .D(n2840), .CK(n5335), .RN(n5521), .Q(
d_ff3_LUT_out[45]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n2814), .CK(n3009), .RN(n5518), .Q(
d_ff3_LUT_out[19]) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n2808), .CK(n3009), .RN(n5517), .Q(
d_ff3_LUT_out[13]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n2796), .CK(n5338), .RN(n5516), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1941), .CK(n5429), .RN(n5323), .Q(add_subt_module_DmP[62]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1938), .CK(n5429), .RN(n5322), .Q(add_subt_module_DmP[61]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1935), .CK(n5429), .RN(n5322), .Q(add_subt_module_DmP[60]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1932), .CK(n5430), .RN(n5322), .Q(add_subt_module_DmP[59]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1929), .CK(n5430), .RN(n5322), .Q(add_subt_module_DmP[58]) );
DFFRX1TS reg_LUT_Q_reg_55_ ( .D(n2849), .CK(n5427), .RN(n5521), .Q(
d_ff3_LUT_out[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n2222), .CK(n5351), .RN(n5512),
.Q(d_ff2_Z[62]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n2223), .CK(n5351), .RN(n5511),
.Q(d_ff2_Z[61]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n2224), .CK(n5352), .RN(n5510),
.Q(d_ff2_Z[60]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n2225), .CK(n5353), .RN(n5509),
.Q(d_ff2_Z[59]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n2226), .CK(n5354), .RN(n5509),
.Q(d_ff2_Z[58]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n2227), .CK(n3261), .RN(n5508),
.Q(d_ff2_Z[57]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n2228), .CK(n5350), .RN(n5507),
.Q(d_ff2_Z[56]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n2280), .CK(n5427), .RN(n5502),
.Q(d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n2282), .CK(n5366), .RN(n5500),
.Q(d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n2234), .CK(n5375), .RN(n5499),
.Q(d_ff2_Z[50]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n2238), .CK(n5368), .RN(n3034),
.Q(d_ff2_Z[46]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n2275), .CK(n3269), .RN(n5493),
.Q(d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n2278), .CK(n5377), .RN(n5491),
.Q(d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n2271), .CK(n5381), .RN(n5488),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n2274), .CK(n5385), .RN(n5487),
.Q(d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n2242), .CK(n5402), .RN(n3281),
.Q(d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n2269), .CK(n5400), .RN(n5474),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n2270), .CK(n5440), .RN(n5472),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n2255), .CK(n5407), .RN(n5469),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n2266), .CK(n5411), .RN(n5467),
.Q(d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n2259), .CK(n5411), .RN(n5467),
.Q(d_ff2_Z[25]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1905), .CK(n5432), .RN(n5286), .Q(add_subt_module_DmP[51]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1899), .CK(n5433), .RN(n5292), .Q(add_subt_module_DmP[48]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1892), .CK(n5437), .RN(n5291), .Q(add_subt_module_DmP[50]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1889), .CK(n5435), .RN(n5291), .Q(add_subt_module_DmP[47]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1875), .CK(n5341), .RN(n3032), .Q(add_subt_module_DmP[46]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1865), .CK(n5435), .RN(n5293), .Q(add_subt_module_DmP[44]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1842), .CK(n5438), .RN(n5295), .Q(add_subt_module_DmP[43]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1835), .CK(n3266), .RN(n5296), .Q(add_subt_module_DmP[40]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1831), .CK(n3266), .RN(n5296), .Q(add_subt_module_DmP[38]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1810), .CK(n5442), .RN(n5298), .Q(add_subt_module_DmP[39]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1799), .CK(n5443), .RN(n5299), .Q(add_subt_module_DmP[34]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1793), .CK(n5444), .RN(n5300), .Q(add_subt_module_DmP[30]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1790), .CK(n5444), .RN(n5300), .Q(add_subt_module_DmP[35]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1783), .CK(n5445), .RN(n5301), .Q(add_subt_module_DmP[36]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1772), .CK(n5440), .RN(n5301), .Q(add_subt_module_DmP[31]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1747), .CK(n5420), .RN(n5304), .Q(add_subt_module_DmP[32]) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n2821), .CK(n5337), .RN(n5519), .Q(
d_ff3_LUT_out[26]) );
DFFRX1TS reg_LUT_Q_reg_14_ ( .D(n2809), .CK(n5394), .RN(n5517), .Q(
d_ff3_LUT_out[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1723), .CK(n5451), .RN(n5315), .Q(add_subt_module_DMP[23]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1722), .CK(n3258), .RN(n5318), .Q(add_subt_module_DMP[34]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1721), .CK(n5452), .RN(n5315), .Q(add_subt_module_DMP[19]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1720),
.CK(n5451), .RN(n5312), .Q(add_subt_module_DMP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1719), .CK(n5453), .RN(n5313), .Q(add_subt_module_DMP[11]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1717),
.CK(n5451), .RN(n5312), .Q(add_subt_module_DMP[7]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1716), .CK(n3258), .RN(n5313), .Q(add_subt_module_DMP[10]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1715), .CK(n5452), .RN(n5313), .Q(add_subt_module_DMP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1714), .CK(n5452), .RN(n5315), .Q(add_subt_module_DMP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1713),
.CK(n5451), .RN(n5312), .Q(add_subt_module_DMP[5]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1712),
.CK(n5453), .RN(n5312), .Q(add_subt_module_DMP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1711),
.CK(n5452), .RN(n5313), .Q(add_subt_module_DMP[9]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1710), .CK(n5451), .RN(n5314), .Q(add_subt_module_DMP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1709),
.CK(n3258), .RN(n5311), .Q(add_subt_module_DMP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1708),
.CK(n5452), .RN(n5311), .Q(add_subt_module_DMP[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1707), .CK(n5451), .RN(n5321), .Q(add_subt_module_DMP[50]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1706),
.CK(n5453), .RN(n5311), .Q(add_subt_module_DMP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1705),
.CK(n5451), .RN(n5312), .Q(add_subt_module_DMP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1704), .CK(n3258), .RN(n5321), .Q(add_subt_module_DMP[51]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1940), .CK(n5429), .RN(n3028), .Q(add_subt_module_DMP[62]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1937), .CK(n5429), .RN(n5324), .Q(add_subt_module_DMP[61]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1934), .CK(n5429), .RN(n5324), .Q(add_subt_module_DMP[60]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1931), .CK(n5430), .RN(n5324), .Q(add_subt_module_DMP[59]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1928), .CK(n5430), .RN(n5324), .Q(add_subt_module_DMP[58]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1925), .CK(n5430), .RN(n5324), .Q(add_subt_module_DMP[57]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1922), .CK(n5431), .RN(n5323), .Q(add_subt_module_DMP[56]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1919), .CK(n5431), .RN(n5323), .Q(add_subt_module_DMP[55]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1916), .CK(n5431), .RN(n5323), .Q(add_subt_module_DMP[54]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1913), .CK(n5432), .RN(n5323), .Q(add_subt_module_DMP[53]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1910), .CK(n5432), .RN(n5323), .Q(add_subt_module_DMP[52]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1898), .CK(n5433), .RN(n5320), .Q(add_subt_module_DMP[48]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1888), .CK(n5436), .RN(n5320), .Q(add_subt_module_DMP[47]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1878), .CK(n5436), .RN(n5321), .Q(add_subt_module_DMP[49]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1864), .CK(n5341), .RN(n5320), .Q(add_subt_module_DMP[44]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1854), .CK(n5435), .RN(n5320), .Q(add_subt_module_DMP[45]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1841), .CK(n5334), .RN(n5319), .Q(add_subt_module_DMP[43]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1834), .CK(n5360), .RN(n5319), .Q(add_subt_module_DMP[40]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1830), .CK(n5348), .RN(n5318), .Q(add_subt_module_DMP[38]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1820), .CK(n5437), .RN(n5319), .Q(add_subt_module_DMP[42]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1813), .CK(n5442), .RN(n5319), .Q(add_subt_module_DMP[41]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1806), .CK(n5442), .RN(n5318), .Q(add_subt_module_DMP[37]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1805), .CK(n5442), .RN(n5319), .Q(add_subt_module_DMP[39]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1789), .CK(n5444), .RN(n5318), .Q(add_subt_module_DMP[35]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1782), .CK(n5445), .RN(n5318), .Q(add_subt_module_DMP[36]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1775), .CK(n5445), .RN(n5316), .Q(add_subt_module_DMP[27]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1771), .CK(n5448), .RN(n5317), .Q(add_subt_module_DMP[31]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1767), .CK(n5345), .RN(n5317), .Q(add_subt_module_DMP[29]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1753), .CK(n5448), .RN(n5317), .Q(add_subt_module_DMP[33]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1746), .CK(n5345), .RN(n5317), .Q(add_subt_module_DMP[32]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1736), .CK(n5449), .RN(n5316), .Q(add_subt_module_DMP[28]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1732), .CK(n5450), .RN(n5316), .Q(add_subt_module_DMP[26]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1731), .CK(n5450), .RN(n5315), .Q(add_subt_module_DMP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1730), .CK(n5450), .RN(n5316), .Q(add_subt_module_DMP[24]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1729), .CK(n5450), .RN(n5314), .Q(add_subt_module_DMP[17]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1728), .CK(n5450), .RN(n5314), .Q(add_subt_module_DMP[18]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1727), .CK(n5450), .RN(n5315), .Q(add_subt_module_DMP[21]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1726), .CK(n5450), .RN(n5314), .Q(add_subt_module_DMP[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1725), .CK(n5450), .RN(n5314), .Q(add_subt_module_DMP[15]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1724), .CK(n5450), .RN(n5317), .Q(add_subt_module_DMP[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n2229), .CK(n5357), .RN(n5506),
.Q(d_ff2_Z[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n2230), .CK(n5358), .RN(n5505),
.Q(d_ff2_Z[54]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n2231), .CK(n5339), .RN(n5505),
.Q(d_ff2_Z[53]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n2232), .CK(n3010), .RN(n5504),
.Q(d_ff2_Z[52]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n2284), .CK(n3010), .RN(n5503),
.Q(d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n2233), .CK(n5448), .RN(n5503),
.Q(d_ff2_Z[51]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n2236), .CK(n5364), .RN(n5501),
.Q(d_ff2_Z[48]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n2237), .CK(n3261), .RN(n5498),
.Q(d_ff2_Z[47]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n2281), .CK(n5364), .RN(n5497),
.Q(d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n2283), .CK(n5384), .RN(n5497),
.Q(d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n2235), .CK(n5373), .RN(n5496),
.Q(d_ff2_Z[49]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n2268), .CK(n5349), .RN(n5494),
.Q(d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n2240), .CK(n5379), .RN(n5495),
.Q(d_ff2_Z[44]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n2279), .CK(n5378), .RN(n5490),
.Q(d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n2239), .CK(n5377), .RN(n5490),
.Q(d_ff2_Z[45]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n2264), .CK(n5327), .RN(n5489),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n2241), .CK(n5383), .RN(n5486),
.Q(d_ff2_Z[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n2277), .CK(n5384), .RN(n5485),
.Q(d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n2244), .CK(n5382), .RN(n5484),
.Q(d_ff2_Z[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n2246), .CK(n5402), .RN(n5483),
.Q(d_ff2_Z[38]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n2272), .CK(n5388), .RN(n3279),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n2273), .CK(n5402), .RN(n3031),
.Q(d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n2276), .CK(n3257), .RN(n5482),
.Q(d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n2243), .CK(n5392), .RN(n5481),
.Q(d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n2245), .CK(n5388), .RN(n5480),
.Q(d_ff2_Z[39]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n2247), .CK(n5397), .RN(n5479),
.Q(d_ff2_Z[37]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n2265), .CK(n5397), .RN(n5478),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n2250), .CK(n5394), .RN(n5477),
.Q(d_ff2_Z[34]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n2261), .CK(n5399), .RN(n5476),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n2254), .CK(n5399), .RN(n5476),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n2249), .CK(n3257), .RN(n5475),
.Q(d_ff2_Z[35]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n2248), .CK(n5388), .RN(n5473),
.Q(d_ff2_Z[36]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n2257), .CK(n5405), .RN(n5471),
.Q(d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n2253), .CK(n5406), .RN(n5470),
.Q(d_ff2_Z[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n2263), .CK(n5408), .RN(n5468),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n2251), .CK(n5412), .RN(n5466),
.Q(d_ff2_Z[33]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n2267), .CK(n5413), .RN(n5465),
.Q(d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n2252), .CK(n5418), .RN(n5464),
.Q(d_ff2_Z[32]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n2260), .CK(n5416), .RN(n5463),
.Q(d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n2262), .CK(n5417), .RN(n5462),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n2256), .CK(n5362), .RN(n5461),
.Q(d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n2258), .CK(n5419), .RN(n5460),
.Q(d_ff2_Z[26]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1827), .CK(n5447), .RN(n5297), .Q(add_subt_module_DmP[12]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1824), .CK(n3262), .RN(n5297), .Q(add_subt_module_DmP[11]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1879), .CK(n5437), .RN(n3033), .Q(add_subt_module_DmP[49]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1868),
.CK(n5436), .RN(n5293), .Q(add_subt_module_DmP[9]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1858),
.CK(n5341), .RN(n5294), .Q(add_subt_module_DmP[5]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1848), .CK(n5360), .RN(n5295), .Q(add_subt_module_DmP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1814), .CK(n5435), .RN(n5298), .Q(add_subt_module_DmP[41]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1807), .CK(n5442), .RN(n5298), .Q(add_subt_module_DmP[37]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1768), .CK(n5342), .RN(n5302), .Q(add_subt_module_DmP[29]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1764), .CK(n5446), .RN(n5302), .Q(add_subt_module_DmP[21]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1754), .CK(n5342), .RN(n5303), .Q(add_subt_module_DmP[33]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1750), .CK(n5342), .RN(n5303), .Q(add_subt_module_DmP[17]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1743), .CK(n5449), .RN(n5304), .Q(add_subt_module_DmP[24]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1733), .CK(n5451), .RN(n5305), .Q(add_subt_module_DmP[26]) );
DFFRX1TS reg_LUT_Q_reg_53_ ( .D(n2847), .CK(n3262), .RN(n5521), .Q(
d_ff3_LUT_out[53]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]),
.CK(n5381), .RN(n5280), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]),
.CK(n5395), .RN(n5281), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS d_ff5_Q_reg_63_ ( .D(n1963), .CK(n5349), .RN(n5512), .Q(
data_output2_63_) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1895),
.CK(n5433), .RN(n5291), .Q(add_subt_module_DmP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1882),
.CK(n5435), .RN(n5290), .Q(add_subt_module_DmP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1802), .CK(n5443), .RN(n5299), .Q(add_subt_module_DmP[19]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1796), .CK(n5443), .RN(n5299), .Q(add_subt_module_DmP[23]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1776), .CK(n5445), .RN(n5301), .Q(add_subt_module_DmP[27]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1761), .CK(n5446), .RN(n5302), .Q(add_subt_module_DmP[18]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1758), .CK(n3266), .RN(n5303), .Q(add_subt_module_DmP[25]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1740), .CK(n5449), .RN(n5304), .Q(add_subt_module_DmP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1737), .CK(n5449), .RN(n5304), .Q(add_subt_module_DmP[28]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]),
.CK(n5367), .RN(n5278), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]),
.CK(n2996), .RN(n5280), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]),
.CK(n5382), .RN(n5280), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]),
.CK(n5395), .RN(n5281), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]),
.CK(n5428), .RN(n5286), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1908),
.CK(n5432), .RN(n5289), .Q(add_subt_module_DmP[0]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1902),
.CK(n5433), .RN(n5292), .Q(add_subt_module_DmP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1885),
.CK(n5441), .RN(n5287), .Q(add_subt_module_DmP[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1871), .CK(n5441), .RN(n5293), .Q(add_subt_module_DmP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1861),
.CK(n5441), .RN(n5294), .Q(add_subt_module_DmP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1851), .CK(n5348), .RN(n5295), .Q(add_subt_module_DmP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1845), .CK(n5336), .RN(n5295), .Q(add_subt_module_DmP[10]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1838),
.CK(n3262), .RN(n5296), .Q(add_subt_module_DmP[7]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1817),
.CK(n5341), .RN(n5298), .Q(add_subt_module_DmP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1779), .CK(n5445), .RN(n5301), .Q(add_subt_module_DmP[14]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]),
.CK(n5377), .RN(n5279), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n2220), .CK(n5326), .RN(n5512), .Q(
d_ff3_sign_out) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ (
.D(n2589), .CK(n5360), .RN(n5322), .Q(add_subt_module_LZA_output[5])
);
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(
n2652), .CK(n5343), .RN(n5290), .Q(add_subt_module_exp_oper_result[10]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n2662), .CK(n5348), .RN(n5324), .Q(add_subt_module_exp_oper_result[9]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n2661), .CK(n5447), .RN(n5324), .Q(add_subt_module_exp_oper_result[8]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n2660), .CK(n3266), .RN(n5324), .Q(add_subt_module_exp_oper_result[7]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n2659), .CK(n5438), .RN(n5324), .Q(add_subt_module_exp_oper_result[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n2931), .CK(n5327), .RN(n5513),
.Q(d_ff2_X[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n2092), .CK(n5373), .RN(n5513),
.Q(d_ff2_Y[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n2218), .CK(n5345), .RN(n5503),
.Q(d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n2116), .CK(n5342), .RN(n5502),
.Q(d_ff2_Y[51]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n2771), .CK(n3265), .RN(n5502),
.Q(d_ff2_X[51]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n2677), .CK(n5368), .RN(n5501),
.Q(d_ff2_X[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n2122), .CK(n5363), .RN(n5501),
.Q(d_ff2_Y[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n2673), .CK(n5364), .RN(n5500),
.Q(d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n2769), .CK(n5363), .RN(n5499),
.Q(d_ff2_X[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n2124), .CK(n3269), .RN(n5498),
.Q(d_ff2_Y[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n2763), .CK(n5372), .RN(n5498),
.Q(d_ff2_X[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n2212), .CK(n5369), .RN(n5497),
.Q(d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n2216), .CK(n5379), .RN(n5496),
.Q(d_ff2_Y[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n2671), .CK(n5377), .RN(n5496),
.Q(d_ff2_X[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n2120), .CK(n5374), .RN(n5496),
.Q(d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n2186), .CK(n3269), .RN(n5494),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n2701), .CK(n5403), .RN(n5493),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n2130), .CK(n5376), .RN(n3031),
.Q(d_ff2_Y[44]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n2757), .CK(n5376), .RN(n3034),
.Q(d_ff2_X[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n2208), .CK(n5378), .RN(n5490),
.Q(d_ff2_Y[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n2679), .CK(n5378), .RN(n5490),
.Q(d_ff2_X[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n2128), .CK(n5372), .RN(n5489),
.Q(d_ff2_Y[45]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n2178), .CK(n5347), .RN(n5488),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n2709), .CK(n5381), .RN(n5488),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n2689), .CK(n5384), .RN(n5487),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n2132), .CK(n5369), .RN(n5486),
.Q(d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n2204), .CK(n5383), .RN(n5485),
.Q(d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n2138), .CK(n5383), .RN(n5484),
.Q(d_ff2_Y[40]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n2749), .CK(n5385), .RN(n5484),
.Q(d_ff2_X[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n2142), .CK(n5395), .RN(n5483),
.Q(d_ff2_Y[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n2745), .CK(n5389), .RN(n5483),
.Q(d_ff2_X[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n2194), .CK(n5386), .RN(n3277),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n2693), .CK(n5389), .RN(n3279),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n2196), .CK(n5388), .RN(n5492),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n2202), .CK(n5401), .RN(n5482),
.Q(d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n2136), .CK(n5392), .RN(n5481),
.Q(d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n2140), .CK(n5386), .RN(n5480),
.Q(d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n2144), .CK(n5336), .RN(n5479),
.Q(d_ff2_Y[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n2743), .CK(n5402), .RN(n5479),
.Q(d_ff2_X[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n2180), .CK(n5447), .RN(n5478),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n2150), .CK(n5390), .RN(n5477),
.Q(d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n2172), .CK(n5398), .RN(n5476),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n2715), .CK(n3257), .RN(n5476),
.Q(d_ff2_X[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n2158), .CK(n5398), .RN(n5475),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n2729), .CK(n3257), .RN(n5475),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n2148), .CK(n5404), .RN(n5475),
.Q(d_ff2_Y[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n2699), .CK(n5386), .RN(n5473),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n2146), .CK(n5387), .RN(n5473),
.Q(d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n2164), .CK(n5405), .RN(n5471),
.Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n2723), .CK(n5405), .RN(n5471),
.Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n2156), .CK(n5406), .RN(n5470),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n2176), .CK(n5409), .RN(n5468),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n2711), .CK(n5409), .RN(n5468),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n2705), .CK(n5426), .RN(n5467),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n2719), .CK(n5426), .RN(n5466),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n2152), .CK(n5412), .RN(n5465),
.Q(d_ff2_Y[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n2735), .CK(n5412), .RN(n5465),
.Q(d_ff2_X[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n2184), .CK(n5413), .RN(n5464),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n2703), .CK(n5439), .RN(n5464),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n2154), .CK(n3262), .RN(n5464),
.Q(d_ff2_Y[32]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n2170), .CK(n5416), .RN(n5463),
.Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n2174), .CK(n5417), .RN(n5462),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n2713), .CK(n5417), .RN(n5462),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n2162), .CK(n5427), .RN(n5461),
.Q(d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n2166), .CK(n5419), .RN(n5460),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n2853), .CK(n5341), .RN(n5514), .Q(
sel_mux_1_reg) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n2531), .CK(n5351), .RN(n5512), .Q(
d_ff_Xn[62]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n2491), .CK(n3010), .RN(n5504), .Q(
d_ff_Xn[52]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n2523), .CK(n5353), .RN(n5510), .Q(
d_ff_Xn[60]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n2515), .CK(n5354), .RN(n5508), .Q(
d_ff_Xn[58]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n2210), .CK(n5363), .RN(n5502),
.Q(d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n2214), .CK(n5366), .RN(n5500),
.Q(d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n2118), .CK(n5365), .RN(n5499),
.Q(d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n2126), .CK(n5368), .RN(n3034),
.Q(d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n2200), .CK(n5356), .RN(n5493),
.Q(d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n2206), .CK(n5375), .RN(n5491),
.Q(d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n2192), .CK(n5381), .RN(n5488),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n2198), .CK(n5385), .RN(n5487),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n2134), .CK(n5397), .RN(n5530),
.Q(d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n2188), .CK(n5399), .RN(n5474),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n2190), .CK(n3257), .RN(n5472),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n2160), .CK(n5407), .RN(n5469),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n2182), .CK(n5422), .RN(n5467),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n2168), .CK(n5410), .RN(n5466),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n2669), .CK(n5446), .RN(n5513),
.Q(d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n2765), .CK(n5375), .RN(n5501),
.Q(d_ff2_X[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n2675), .CK(n5385), .RN(n5497),
.Q(d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n2767), .CK(n5380), .RN(n3034),
.Q(d_ff2_X[49]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n2761), .CK(n5365), .RN(n5494),
.Q(d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n2687), .CK(n5375), .RN(n5493),
.Q(d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n2681), .CK(n5368), .RN(n5491),
.Q(d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n2759), .CK(n5366), .RN(n5489),
.Q(d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n2695), .CK(n5369), .RN(n5487),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n2755), .CK(n5369), .RN(n5486),
.Q(d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n2683), .CK(n5369), .RN(n5485),
.Q(d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n2691), .CK(n5389), .RN(n3281),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n2753), .CK(n5420), .RN(n5482),
.Q(d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n2685), .CK(n5404), .RN(n5481),
.Q(d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n2751), .CK(n5392), .RN(n5481),
.Q(d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n2747), .CK(n5387), .RN(n5480),
.Q(d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n2707), .CK(n5390), .RN(n5478),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n2737), .CK(n5334), .RN(n5477),
.Q(d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n2739), .CK(n5391), .RN(n5474),
.Q(d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n2741), .CK(n5390), .RN(n5473),
.Q(d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n2697), .CK(n5401), .RN(n5472),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n2731), .CK(n5406), .RN(n5470),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n2727), .CK(n5408), .RN(n5469),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n2733), .CK(n5422), .RN(n5463),
.Q(d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n2717), .CK(n5416), .RN(n5462),
.Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n2725), .CK(n3260), .RN(n5461),
.Q(d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n2721), .CK(n5452), .RN(n5460),
.Q(d_ff2_X[26]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ (
.D(n2590), .CK(n5334), .RN(n5322), .Q(add_subt_module_LZA_output[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n2932), .CK(n5356), .RN(n5513), .Q(
d_ff_Xn[63]) );
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n2487), .CK(n5348), .RN(n5502), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n2299), .CK(n5366), .RN(n5501), .Q(
d_ff_Xn[4]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n2291), .CK(n5365), .RN(n5500), .Q(
d_ff_Xn[2]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n2483), .CK(n5366), .RN(n5499), .Q(
d_ff_Xn[50]) );
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n2471), .CK(n5363), .RN(n5498), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n2287), .CK(n5372), .RN(n5496), .Q(
d_ff_Xn[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n2347), .CK(n5380), .RN(n5493), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n2459), .CK(n5376), .RN(n3034), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n2303), .CK(n5378), .RN(n5490), .Q(
d_ff_Xn[5]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n2363), .CK(n5380), .RN(n5488), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n2323), .CK(n2996), .RN(n5487), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n2443), .CK(n2996), .RN(n5484), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n2435), .CK(n5388), .RN(n5483), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n2331), .CK(n5386), .RN(n3275), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n2431), .CK(n5390), .RN(n5479), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n2375), .CK(n5401), .RN(n5476), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n2403), .CK(n5401), .RN(n5475), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n2343), .CK(n5393), .RN(n5473), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n2391), .CK(n5405), .RN(n5471), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n2367), .CK(n5409), .RN(n5468), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n2355), .CK(n5425), .RN(n5467), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n2383), .CK(n5411), .RN(n5466), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n2415), .CK(n5412), .RN(n5465), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n2351), .CK(n5413), .RN(n5464), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n2371), .CK(n5417), .RN(n5462), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n2090), .CK(n3262), .RN(n5513), .Q(
d_ff_Xn[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n2503), .CK(n5357), .RN(n5506), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n2499), .CK(n5358), .RN(n5505), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n2495), .CK(n3009), .RN(n5504), .Q(
d_ff_Xn[53]) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n2475), .CK(n5370), .RN(n5501), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n2295), .CK(n5382), .RN(n5497), .Q(
d_ff_Xn[3]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n2479), .CK(n3269), .RN(n3034), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n2467), .CK(n5365), .RN(n5494), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n2319), .CK(n5368), .RN(n5493), .Q(
d_ff_Xn[9]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n2307), .CK(n5370), .RN(n5491), .Q(
d_ff_Xn[6]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n2463), .CK(n5370), .RN(n5489), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n2335), .CK(n5384), .RN(n5487), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n2455), .CK(n2996), .RN(n5486), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n2311), .CK(n2996), .RN(n5485), .Q(
d_ff_Xn[7]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n2327), .CK(n5388), .RN(n5495), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n2451), .CK(n5390), .RN(n5482), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n2315), .CK(n5391), .RN(n5481), .Q(
d_ff_Xn[8]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n2447), .CK(n5392), .RN(n5481), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n2439), .CK(n5393), .RN(n5480), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n2359), .CK(n3266), .RN(n5478), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n2419), .CK(n3256), .RN(n5477), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n2423), .CK(n5400), .RN(n5474), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n2427), .CK(n3262), .RN(n5473), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n2339), .CK(n5404), .RN(n5472), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n2407), .CK(n5406), .RN(n5470), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n2399), .CK(n5408), .RN(n5469), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n2411), .CK(n5428), .RN(n5463), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n2379), .CK(n5416), .RN(n5462), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n2395), .CK(n5447), .RN(n5461), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n2387), .CK(n5419), .RN(n5460), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n2527), .CK(n5352), .RN(n5511), .Q(
d_ff_Xn[61]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n2519), .CK(n5354), .RN(n5509), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n2511), .CK(n5374), .RN(n5508), .Q(
d_ff_Xn[57]) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n2507), .CK(n5327), .RN(n5507), .Q(
d_ff_Xn[56]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(
n2937), .CK(n5418), .RN(n5321), .Q(
add_subt_module_Sgf_normalized_result[54]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ (
.D(n2593), .CK(n5343), .RN(n5322), .Q(add_subt_module_LZA_output[3])
);
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ (
.D(n2594), .CK(n5403), .RN(n5321), .Q(add_subt_module_LZA_output[2])
);
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ (
.D(n2591), .CK(n5421), .RN(n5325), .Q(add_subt_module_LZA_output[1])
);
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n2221), .CK(n3261), .RN(n5512),
.Q(d_ff2_Z[63]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n2667), .CK(n5361), .RN(n5513), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n2793), .CK(n5351), .RN(n5511),
.Q(d_ff2_X[62]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_62_ ( .D(n2104), .CK(n5351), .RN(n5512),
.Q(d_ff2_Y[62]) );
DFFRX1TS add_subt_module_XRegister_Q_reg_63_ ( .D(n1945), .CK(n3263), .RN(
n5288), .Q(add_subt_module_intDX[63]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]),
.CK(n3256), .RN(n5282), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]),
.CK(n5404), .RN(n5282), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]),
.CK(n5409), .RN(n5284), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]),
.CK(n5418), .RN(n3032), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n2111), .CK(n5357), .RN(n5506),
.Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n2112), .CK(n5358), .RN(n5505),
.Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n2113), .CK(n5336), .RN(n5504),
.Q(d_ff2_Y[53]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]),
.CK(n5402), .RN(n5283), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]),
.CK(n5334), .RN(n5287), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]),
.CK(n5414), .RN(n5286), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]),
.CK(n3260), .RN(n3028), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n2786), .CK(n5357), .RN(n5506),
.Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n2785), .CK(n5358), .RN(n5505),
.Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n2784), .CK(n5338), .RN(n5504),
.Q(d_ff2_X[53]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n2651),
.CK(n5374), .RN(n5275), .Q(overflow_flag) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ (
.D(n2286), .CK(n3010), .RN(n5276), .Q(result_add_subt[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ (
.D(n2490), .CK(n5446), .RN(n5276), .Q(result_add_subt[51]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ (
.D(n2302), .CK(n5336), .RN(n5277), .Q(result_add_subt[4]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ (
.D(n2478), .CK(n5375), .RN(n5277), .Q(result_add_subt[48]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ (
.D(n2294), .CK(n5372), .RN(n5277), .Q(result_add_subt[2]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ (
.D(n2486), .CK(n5363), .RN(n5277), .Q(result_add_subt[50]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ (
.D(n2474), .CK(n5421), .RN(n5277), .Q(result_add_subt[47]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ (
.D(n2298), .CK(n5366), .RN(n5278), .Q(result_add_subt[3]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ (
.D(n2290), .CK(n2996), .RN(n5278), .Q(result_add_subt[1]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ (
.D(n2482), .CK(n5365), .RN(n5278), .Q(result_add_subt[49]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ (
.D(n2470), .CK(n5364), .RN(n5278), .Q(result_add_subt[46]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ (
.D(n2350), .CK(n5326), .RN(n5278), .Q(result_add_subt[16]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ (
.D(n2322), .CK(n3269), .RN(n5279), .Q(result_add_subt[9]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ (
.D(n2462), .CK(n5370), .RN(n5279), .Q(result_add_subt[44]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ (
.D(n2310), .CK(n5376), .RN(n5279), .Q(result_add_subt[6]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ (
.D(n2306), .CK(n5379), .RN(n5279), .Q(result_add_subt[5]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ (
.D(n2466), .CK(n5379), .RN(n5279), .Q(result_add_subt[45]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ (
.D(n2366), .CK(n3269), .RN(n5279), .Q(result_add_subt[20]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ (
.D(n2338), .CK(n5381), .RN(n5280), .Q(result_add_subt[13]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ (
.D(n2326), .CK(n5384), .RN(n5280), .Q(result_add_subt[10]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ (
.D(n2458), .CK(n5382), .RN(n5280), .Q(result_add_subt[43]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ (
.D(n2314), .CK(n5369), .RN(n5280), .Q(result_add_subt[7]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ (
.D(n2446), .CK(n5369), .RN(n5280), .Q(result_add_subt[40]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ (
.D(n2438), .CK(n5386), .RN(n5281), .Q(result_add_subt[38]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ (
.D(n2334), .CK(n5387), .RN(n5281), .Q(result_add_subt[12]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ (
.D(n2330), .CK(n5387), .RN(n5281), .Q(result_add_subt[11]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ (
.D(n2454), .CK(n5386), .RN(n5281), .Q(result_add_subt[42]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ (
.D(n2318), .CK(n3266), .RN(n5281), .Q(result_add_subt[8]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ (
.D(n2450), .CK(n5400), .RN(n5281), .Q(result_add_subt[41]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ (
.D(n2442), .CK(n5402), .RN(n5282), .Q(result_add_subt[39]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ (
.D(n2434), .CK(n3256), .RN(n5282), .Q(result_add_subt[37]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ (
.D(n2362), .CK(n5395), .RN(n5282), .Q(result_add_subt[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ (
.D(n2422), .CK(n5396), .RN(n5282), .Q(result_add_subt[34]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ (
.D(n2378), .CK(n5391), .RN(n5282), .Q(result_add_subt[23]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ (
.D(n2406), .CK(n3257), .RN(n5283), .Q(result_add_subt[30]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ (
.D(n2426), .CK(n5399), .RN(n5283), .Q(result_add_subt[35]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ (
.D(n2346), .CK(n5398), .RN(n5283), .Q(result_add_subt[15]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ (
.D(n2430), .CK(n5395), .RN(n5283), .Q(result_add_subt[36]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ (
.D(n2342), .CK(n5396), .RN(n5283), .Q(result_add_subt[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ (
.D(n2394), .CK(n5391), .RN(n5283), .Q(result_add_subt[27]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ (
.D(n2410), .CK(n5406), .RN(n5283), .Q(result_add_subt[31]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ (
.D(n2402), .CK(n5407), .RN(n5284), .Q(result_add_subt[29]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ (
.D(n2370), .CK(n5408), .RN(n5284), .Q(result_add_subt[21]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ (
.D(n2358), .CK(n5409), .RN(n5284), .Q(result_add_subt[18]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ (
.D(n2418), .CK(n5412), .RN(n5284), .Q(result_add_subt[33]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ (
.D(n2354), .CK(n5413), .RN(n5285), .Q(result_add_subt[17]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ (
.D(n2414), .CK(n3260), .RN(n5285), .Q(result_add_subt[32]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ (
.D(n2382), .CK(n5424), .RN(n5285), .Q(result_add_subt[24]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ (
.D(n2374), .CK(n5416), .RN(n5285), .Q(result_add_subt[22]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ (
.D(n2398), .CK(n5414), .RN(n5285), .Q(result_add_subt[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ (
.D(n2390), .CK(n5419), .RN(n5325), .Q(result_add_subt[26]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ (
.D(n2534), .CK(n5403), .RN(n5275), .Q(result_add_subt[62]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ (
.D(n2530), .CK(n5351), .RN(n5275), .Q(result_add_subt[61]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ (
.D(n2526), .CK(n5352), .RN(n5275), .Q(result_add_subt[60]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ (
.D(n2522), .CK(n5353), .RN(n5275), .Q(result_add_subt[59]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ (
.D(n2518), .CK(n5354), .RN(n5275), .Q(result_add_subt[58]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ (
.D(n2514), .CK(n5326), .RN(n5275), .Q(result_add_subt[57]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ (
.D(n2510), .CK(n5343), .RN(n5275), .Q(result_add_subt[56]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ (
.D(n2506), .CK(n5357), .RN(n5276), .Q(result_add_subt[55]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ (
.D(n2502), .CK(n5358), .RN(n5276), .Q(result_add_subt[54]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ (
.D(n2498), .CK(n5358), .RN(n5276), .Q(result_add_subt[53]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ (
.D(n2494), .CK(n5337), .RN(n5276), .Q(result_add_subt[52]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n2658), .CK(n3265), .RN(n5324), .Q(add_subt_module_exp_oper_result[5]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n2851), .CK(n5394), .RN(n5514), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n2653), .CK(n5355), .RN(n5323), .Q(add_subt_module_exp_oper_result[0]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n2920), .CK(n5349), .RN(n5528), .Q(
d_ff1_operation_out) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n2919), .CK(n5327), .RN(n5528), .Q(
d_ff1_shift_region_flag_out[0]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]),
.CK(n5378), .RN(n5279), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n2852), .CK(n5437), .RN(n5514), .Q(
sel_mux_2_reg[0]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(
n2623), .CK(n5344), .RN(n5305), .Q(add_subt_module_Add_Subt_result[27]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n2657), .CK(n5348), .RN(n5323), .Q(add_subt_module_exp_oper_result[4]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n2656), .CK(n5394), .RN(n5323), .Q(add_subt_module_exp_oper_result[3]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n2655), .CK(n5350), .RN(n5323), .Q(add_subt_module_exp_oper_result[2]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n2654), .CK(n5373), .RN(n5310), .Q(add_subt_module_exp_oper_result[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]),
.CK(n5380), .RN(n5277), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]),
.CK(n5427), .RN(n5276), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]),
.CK(n3271), .RN(n5277), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]),
.CK(n5382), .RN(n5280), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n2105), .CK(n5352), .RN(n5511),
.Q(d_ff2_Y[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n2107), .CK(n5353), .RN(n5509),
.Q(d_ff2_Y[59]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]),
.CK(n5367), .RN(n5278), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n2109), .CK(n5355), .RN(n5508),
.Q(d_ff2_Y[57]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n2790), .CK(n5354), .RN(n5509),
.Q(d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n2792), .CK(n5352), .RN(n5511),
.Q(d_ff2_X[61]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n2788), .CK(n5350), .RN(n5507),
.Q(d_ff2_X[57]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]),
.CK(n5438), .RN(n5276), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
n2536), .CK(n3263), .RN(n5311), .Q(
add_subt_module_Sgf_normalized_result[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
n2535), .CK(n5347), .RN(n5311), .Q(
add_subt_module_Sgf_normalized_result[0]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]),
.CK(n5380), .RN(n5278), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]),
.CK(n5399), .RN(n5281), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]),
.CK(n5395), .RN(n5281), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]),
.CK(n5367), .RN(n5279), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]),
.CK(n5422), .RN(n5285), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]),
.CK(n5387), .RN(n5280), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]),
.CK(n5395), .RN(n5282), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]),
.CK(n5407), .RN(n5284), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]),
.CK(n5407), .RN(n5284), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]),
.CK(n5414), .RN(n5285), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]),
.CK(n5400), .RN(n5283), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]),
.CK(n5360), .RN(n5282), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]),
.CK(n5427), .RN(n5282), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]),
.CK(n5424), .RN(n5284), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]),
.CK(n5415), .RN(n5285), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]),
.CK(n5398), .RN(n5283), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]),
.CK(n5417), .RN(n5285), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]),
.CK(n5407), .RN(n5284), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]),
.CK(n5416), .RN(n5285), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]),
.CK(n5419), .RN(n5287), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
n2597), .CK(n5355), .RN(n5310), .Q(add_subt_module_Add_Subt_result[1])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(
n2622), .CK(n5344), .RN(n5305), .Q(add_subt_module_Add_Subt_result[26]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
n2611), .CK(n5346), .RN(n5307), .Q(add_subt_module_Add_Subt_result[15]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
n2607), .CK(n5346), .RN(n5308), .Q(add_subt_module_Add_Subt_result[11]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
n2603), .CK(n5346), .RN(n5309), .Q(add_subt_module_Add_Subt_result[7])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(
n2624), .CK(n5344), .RN(n5305), .Q(add_subt_module_Add_Subt_result[28]) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n2110), .CK(n5355), .RN(n5507),
.Q(d_ff2_Y[56]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n2787), .CK(n5356), .RN(n5507),
.Q(d_ff2_X[56]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
n2596), .CK(n5374), .RN(n5310), .Q(add_subt_module_Add_Subt_result[0])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(
n2635), .CK(n5355), .RN(n5307), .Q(add_subt_module_Add_Subt_result[39]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(
n2630), .CK(n5344), .RN(n5306), .Q(add_subt_module_Add_Subt_result[34]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(
n2634), .CK(n5421), .RN(n5307), .Q(add_subt_module_Add_Subt_result[38]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
n2618), .CK(n5447), .RN(n5306), .Q(add_subt_module_Add_Subt_result[22]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
n2617), .CK(n5361), .RN(n5306), .Q(add_subt_module_Add_Subt_result[21]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_45_ ( .D(n1857), .CK(n5441), .RN(
n5294), .Q(add_subt_module_intDX[45]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_53_ ( .D(n1948), .CK(n3263), .RN(
n5288), .Q(add_subt_module_intDY[53]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_59_ ( .D(n1933), .CK(n5430), .RN(
n5288), .Q(add_subt_module_intDX[59]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_6_ ( .D(n1863), .CK(n5437), .RN(
n5293), .Q(add_subt_module_intDX[6]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_0_ ( .D(n1909), .CK(n5432), .RN(
n5289), .Q(add_subt_module_intDX[0]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_54_ ( .D(n1949), .CK(n5428), .RN(
n3032), .Q(add_subt_module_intDY[54]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_44_ ( .D(n1867), .CK(n5437), .RN(
n5293), .Q(add_subt_module_intDX[44]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_4_ ( .D(n1904), .CK(n5432), .RN(
n3028), .Q(add_subt_module_intDX[4]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_48_ ( .D(n1901), .CK(n5433), .RN(
n3030), .Q(add_subt_module_intDX[48]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_32_ ( .D(n1748), .CK(n5446), .RN(
n5303), .Q(add_subt_module_intDY[32]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_56_ ( .D(n1924), .CK(n5430), .RN(
n5289), .Q(add_subt_module_intDX[56]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_50_ ( .D(n1894), .CK(n5433), .RN(
n5291), .Q(add_subt_module_intDX[50]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_43_ ( .D(n1844), .CK(n5420), .RN(
n5295), .Q(add_subt_module_intDX[43]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_37_ ( .D(n1809), .CK(n5442), .RN(
n5298), .Q(add_subt_module_intDX[37]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_35_ ( .D(n1791), .CK(n5444), .RN(
n5300), .Q(add_subt_module_intDY[35]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_14_ ( .D(n1781), .CK(n5445), .RN(
n5301), .Q(add_subt_module_intDX[14]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_33_ ( .D(n1755), .CK(n5446), .RN(
n5303), .Q(add_subt_module_intDY[33]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_22_ ( .D(n1741), .CK(n5449), .RN(
n5304), .Q(add_subt_module_intDY[22]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_52_ ( .D(n1947), .CK(n5415), .RN(
n5288), .Q(add_subt_module_intDY[52]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_2_ ( .D(n1896), .CK(n5433), .RN(
n5291), .Q(add_subt_module_intDY[2]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_10_ ( .D(n1846), .CK(n3266), .RN(
n5295), .Q(add_subt_module_intDY[10]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_28_ ( .D(n1739), .CK(n5449), .RN(
n5304), .Q(add_subt_module_intDX[28]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_26_ ( .D(n1734), .CK(n5449), .RN(
n5305), .Q(add_subt_module_intDY[26]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_61_ ( .D(n1939), .CK(n5429), .RN(
n5288), .Q(add_subt_module_intDX[61]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_60_ ( .D(n1936), .CK(n5429), .RN(
n5288), .Q(add_subt_module_intDX[60]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_5_ ( .D(n1860), .CK(n5435), .RN(
n5294), .Q(add_subt_module_intDX[5]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_38_ ( .D(n1833), .CK(n5360), .RN(
n5296), .Q(add_subt_module_intDX[38]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_34_ ( .D(n1800), .CK(n5443), .RN(
n5299), .Q(add_subt_module_intDY[34]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
n2615), .CK(n5448), .RN(n5306), .Q(add_subt_module_Add_Subt_result[19]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(
n2648), .CK(n5440), .RN(n5310), .Q(add_subt_module_Add_Subt_result[52]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(
n2627), .CK(n5344), .RN(n5306), .Q(add_subt_module_Add_Subt_result[31]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
n2619), .CK(n3262), .RN(n5306), .Q(add_subt_module_Add_Subt_result[23]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
n2598), .CK(n5350), .RN(n5310), .Q(add_subt_module_Add_Subt_result[2])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(
n2632), .CK(n5350), .RN(n5307), .Q(add_subt_module_Add_Subt_result[36]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(
n2644), .CK(n5338), .RN(n5309), .Q(add_subt_module_Add_Subt_result[48]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(
n2640), .CK(n5373), .RN(n5308), .Q(add_subt_module_Add_Subt_result[44]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(
n2626), .CK(n5344), .RN(n5305), .Q(add_subt_module_Add_Subt_result[30]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
n2604), .CK(n5346), .RN(n5309), .Q(add_subt_module_Add_Subt_result[8])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
n2608), .CK(n5346), .RN(n5308), .Q(add_subt_module_Add_Subt_result[12]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(
n2625), .CK(n5344), .RN(n5305), .Q(add_subt_module_Add_Subt_result[29]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(
n2647), .CK(n5337), .RN(n5310), .Q(add_subt_module_Add_Subt_result[51]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_7_ ( .D(n1840), .CK(n5438), .RN(
n5296), .Q(add_subt_module_intDX[7]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_12_ ( .D(n1828), .CK(n5348), .RN(
n5297), .Q(add_subt_module_intDY[12]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_62_ ( .D(n1942), .CK(n5429), .RN(
n5288), .Q(add_subt_module_intDX[62]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_47_ ( .D(n1890), .CK(n5434), .RN(
n5291), .Q(add_subt_module_intDY[47]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_17_ ( .D(n1752), .CK(n5394), .RN(
n5303), .Q(add_subt_module_intDX[17]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_8_ ( .D(n1819), .CK(n5436), .RN(
n5297), .Q(add_subt_module_intDX[8]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_31_ ( .D(n1774), .CK(n5445), .RN(
n5301), .Q(add_subt_module_intDX[31]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_24_ ( .D(n1745), .CK(n5361), .RN(
n5304), .Q(add_subt_module_intDX[24]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_55_ ( .D(n1950), .CK(n5424), .RN(
n3033), .Q(add_subt_module_intDY[55]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_3_ ( .D(n1886), .CK(n5434), .RN(
n5291), .Q(add_subt_module_intDY[3]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(
n2641), .CK(n5343), .RN(n5308), .Q(add_subt_module_Add_Subt_result[45]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(
n2637), .CK(n5356), .RN(n5308), .Q(add_subt_module_Add_Subt_result[41]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
n2610), .CK(n5346), .RN(n5307), .Q(add_subt_module_Add_Subt_result[14]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
n2600), .CK(n5349), .RN(n5309), .Q(add_subt_module_Add_Subt_result[4])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(
n2631), .CK(n5344), .RN(n5306), .Q(add_subt_module_Add_Subt_result[35]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(
n2595), .CK(n5343), .RN(n5310), .Q(add_subt_module_Add_Subt_result[54]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(
n2645), .CK(n5339), .RN(n5309), .Q(add_subt_module_Add_Subt_result[49]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
n2606), .CK(n5346), .RN(n5308), .Q(add_subt_module_Add_Subt_result[10]) );
DFFRX2TS cont_iter_count_reg_0_ ( .D(n2923), .CK(n5326), .RN(n5529), .Q(
cont_iter_out[0]), .QN(n5057) );
CMPR32X2TS DP_OP_95J75_125_7728_U56 ( .A(add_subt_module_S_A_S_Oper_A[0]),
.B(n5273), .C(DP_OP_95J75_125_7728_n114), .CO(DP_OP_95J75_125_7728_n55), .S(add_subt_module_Add_Subt_Sgf_module_S_to_D[0]) );
CMPR32X2TS DP_OP_95J75_125_7728_U55 ( .A(DP_OP_95J75_125_7728_n113), .B(
add_subt_module_S_A_S_Oper_A[1]), .C(DP_OP_95J75_125_7728_n55), .CO(
DP_OP_95J75_125_7728_n54), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[1]) );
CMPR32X2TS DP_OP_95J75_125_7728_U54 ( .A(DP_OP_95J75_125_7728_n112), .B(
add_subt_module_S_A_S_Oper_A[2]), .C(DP_OP_95J75_125_7728_n54), .CO(
DP_OP_95J75_125_7728_n53), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[2]) );
CMPR32X2TS DP_OP_95J75_125_7728_U53 ( .A(DP_OP_95J75_125_7728_n111), .B(
add_subt_module_S_A_S_Oper_A[3]), .C(DP_OP_95J75_125_7728_n53), .CO(
DP_OP_95J75_125_7728_n52), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]) );
CMPR32X2TS DP_OP_95J75_125_7728_U52 ( .A(DP_OP_95J75_125_7728_n110), .B(
add_subt_module_S_A_S_Oper_A[4]), .C(DP_OP_95J75_125_7728_n52), .CO(
DP_OP_95J75_125_7728_n51), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]) );
CMPR32X2TS DP_OP_95J75_125_7728_U51 ( .A(DP_OP_95J75_125_7728_n109), .B(
add_subt_module_S_A_S_Oper_A[5]), .C(DP_OP_95J75_125_7728_n51), .CO(
DP_OP_95J75_125_7728_n50), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]) );
CMPR32X2TS DP_OP_95J75_125_7728_U50 ( .A(DP_OP_95J75_125_7728_n108), .B(
add_subt_module_S_A_S_Oper_A[6]), .C(DP_OP_95J75_125_7728_n50), .CO(
DP_OP_95J75_125_7728_n49), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]) );
CMPR32X2TS DP_OP_95J75_125_7728_U49 ( .A(DP_OP_95J75_125_7728_n107), .B(
add_subt_module_S_A_S_Oper_A[7]), .C(DP_OP_95J75_125_7728_n49), .CO(
DP_OP_95J75_125_7728_n48), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[7]) );
CMPR32X2TS DP_OP_95J75_125_7728_U48 ( .A(DP_OP_95J75_125_7728_n106), .B(
add_subt_module_S_A_S_Oper_A[8]), .C(DP_OP_95J75_125_7728_n48), .CO(
DP_OP_95J75_125_7728_n47), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[8]) );
CMPR32X2TS DP_OP_95J75_125_7728_U47 ( .A(DP_OP_95J75_125_7728_n105), .B(
add_subt_module_S_A_S_Oper_A[9]), .C(DP_OP_95J75_125_7728_n47), .CO(
DP_OP_95J75_125_7728_n46), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[9]) );
CMPR32X2TS DP_OP_95J75_125_7728_U46 ( .A(DP_OP_95J75_125_7728_n104), .B(
add_subt_module_S_A_S_Oper_A[10]), .C(DP_OP_95J75_125_7728_n46), .CO(
DP_OP_95J75_125_7728_n45), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[10]) );
CMPR32X2TS DP_OP_95J75_125_7728_U45 ( .A(DP_OP_95J75_125_7728_n103), .B(
add_subt_module_S_A_S_Oper_A[11]), .C(DP_OP_95J75_125_7728_n45), .CO(
DP_OP_95J75_125_7728_n44), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[11]) );
CMPR32X2TS DP_OP_95J75_125_7728_U44 ( .A(DP_OP_95J75_125_7728_n102), .B(
add_subt_module_S_A_S_Oper_A[12]), .C(DP_OP_95J75_125_7728_n44), .CO(
DP_OP_95J75_125_7728_n43), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[12]) );
CMPR32X2TS DP_OP_95J75_125_7728_U43 ( .A(DP_OP_95J75_125_7728_n101), .B(
add_subt_module_S_A_S_Oper_A[13]), .C(DP_OP_95J75_125_7728_n43), .CO(
DP_OP_95J75_125_7728_n42), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]) );
CMPR32X2TS DP_OP_95J75_125_7728_U42 ( .A(DP_OP_95J75_125_7728_n100), .B(
add_subt_module_S_A_S_Oper_A[14]), .C(DP_OP_95J75_125_7728_n42), .CO(
DP_OP_95J75_125_7728_n41), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]) );
CMPR32X2TS DP_OP_95J75_125_7728_U41 ( .A(DP_OP_95J75_125_7728_n99), .B(
add_subt_module_S_A_S_Oper_A[15]), .C(DP_OP_95J75_125_7728_n41), .CO(
DP_OP_95J75_125_7728_n40), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[15]) );
CMPR32X2TS DP_OP_95J75_125_7728_U40 ( .A(DP_OP_95J75_125_7728_n98), .B(
add_subt_module_S_A_S_Oper_A[16]), .C(DP_OP_95J75_125_7728_n40), .CO(
DP_OP_95J75_125_7728_n39), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]) );
CMPR32X2TS DP_OP_95J75_125_7728_U39 ( .A(DP_OP_95J75_125_7728_n97), .B(
add_subt_module_S_A_S_Oper_A[17]), .C(DP_OP_95J75_125_7728_n39), .CO(
DP_OP_95J75_125_7728_n38), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[17]) );
CMPR32X2TS DP_OP_95J75_125_7728_U38 ( .A(DP_OP_95J75_125_7728_n96), .B(
add_subt_module_S_A_S_Oper_A[18]), .C(DP_OP_95J75_125_7728_n38), .CO(
DP_OP_95J75_125_7728_n37), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]) );
CMPR32X2TS DP_OP_95J75_125_7728_U37 ( .A(DP_OP_95J75_125_7728_n95), .B(
add_subt_module_S_A_S_Oper_A[19]), .C(DP_OP_95J75_125_7728_n37), .CO(
DP_OP_95J75_125_7728_n36), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[19]) );
CMPR32X2TS DP_OP_95J75_125_7728_U36 ( .A(DP_OP_95J75_125_7728_n94), .B(
add_subt_module_S_A_S_Oper_A[20]), .C(DP_OP_95J75_125_7728_n36), .CO(
DP_OP_95J75_125_7728_n35), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]) );
CMPR32X2TS DP_OP_95J75_125_7728_U35 ( .A(DP_OP_95J75_125_7728_n93), .B(
add_subt_module_S_A_S_Oper_A[21]), .C(DP_OP_95J75_125_7728_n35), .CO(
DP_OP_95J75_125_7728_n34), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]) );
CMPR32X2TS DP_OP_95J75_125_7728_U34 ( .A(DP_OP_95J75_125_7728_n92), .B(
add_subt_module_S_A_S_Oper_A[22]), .C(DP_OP_95J75_125_7728_n34), .CO(
DP_OP_95J75_125_7728_n33), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]) );
CMPR32X2TS DP_OP_95J75_125_7728_U33 ( .A(DP_OP_95J75_125_7728_n91), .B(
add_subt_module_S_A_S_Oper_A[23]), .C(DP_OP_95J75_125_7728_n33), .CO(
DP_OP_95J75_125_7728_n32), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]) );
CMPR32X2TS DP_OP_95J75_125_7728_U32 ( .A(DP_OP_95J75_125_7728_n90), .B(
add_subt_module_S_A_S_Oper_A[24]), .C(DP_OP_95J75_125_7728_n32), .CO(
DP_OP_95J75_125_7728_n31), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]) );
CMPR32X2TS DP_OP_95J75_125_7728_U31 ( .A(DP_OP_95J75_125_7728_n89), .B(
add_subt_module_S_A_S_Oper_A[25]), .C(DP_OP_95J75_125_7728_n31), .CO(
DP_OP_95J75_125_7728_n30), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]) );
CMPR32X2TS DP_OP_95J75_125_7728_U30 ( .A(DP_OP_95J75_125_7728_n88), .B(
add_subt_module_S_A_S_Oper_A[26]), .C(DP_OP_95J75_125_7728_n30), .CO(
DP_OP_95J75_125_7728_n29), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[26]) );
CMPR32X2TS DP_OP_95J75_125_7728_U29 ( .A(DP_OP_95J75_125_7728_n87), .B(
add_subt_module_S_A_S_Oper_A[27]), .C(DP_OP_95J75_125_7728_n29), .CO(
DP_OP_95J75_125_7728_n28), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[27]) );
CMPR32X2TS DP_OP_95J75_125_7728_U28 ( .A(DP_OP_95J75_125_7728_n86), .B(
add_subt_module_S_A_S_Oper_A[28]), .C(DP_OP_95J75_125_7728_n28), .CO(
DP_OP_95J75_125_7728_n27), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[28]) );
CMPR32X2TS DP_OP_95J75_125_7728_U27 ( .A(DP_OP_95J75_125_7728_n85), .B(
add_subt_module_S_A_S_Oper_A[29]), .C(DP_OP_95J75_125_7728_n27), .CO(
DP_OP_95J75_125_7728_n26), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[29]) );
CMPR32X2TS DP_OP_95J75_125_7728_U26 ( .A(DP_OP_95J75_125_7728_n84), .B(
add_subt_module_S_A_S_Oper_A[30]), .C(DP_OP_95J75_125_7728_n26), .CO(
DP_OP_95J75_125_7728_n25), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[30]) );
CMPR32X2TS DP_OP_95J75_125_7728_U25 ( .A(DP_OP_95J75_125_7728_n83), .B(
add_subt_module_S_A_S_Oper_A[31]), .C(DP_OP_95J75_125_7728_n25), .CO(
DP_OP_95J75_125_7728_n24), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[31]) );
CMPR32X2TS DP_OP_95J75_125_7728_U24 ( .A(DP_OP_95J75_125_7728_n82), .B(
add_subt_module_S_A_S_Oper_A[32]), .C(DP_OP_95J75_125_7728_n24), .CO(
DP_OP_95J75_125_7728_n23), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[32]) );
CMPR32X2TS DP_OP_95J75_125_7728_U23 ( .A(DP_OP_95J75_125_7728_n81), .B(
add_subt_module_S_A_S_Oper_A[33]), .C(DP_OP_95J75_125_7728_n23), .CO(
DP_OP_95J75_125_7728_n22), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[33]) );
CMPR32X2TS DP_OP_95J75_125_7728_U22 ( .A(DP_OP_95J75_125_7728_n80), .B(
add_subt_module_S_A_S_Oper_A[34]), .C(DP_OP_95J75_125_7728_n22), .CO(
DP_OP_95J75_125_7728_n21), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[34]) );
CMPR32X2TS DP_OP_95J75_125_7728_U21 ( .A(DP_OP_95J75_125_7728_n79), .B(
add_subt_module_S_A_S_Oper_A[35]), .C(DP_OP_95J75_125_7728_n21), .CO(
DP_OP_95J75_125_7728_n20), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[35]) );
CMPR32X2TS DP_OP_95J75_125_7728_U20 ( .A(DP_OP_95J75_125_7728_n78), .B(
add_subt_module_S_A_S_Oper_A[36]), .C(DP_OP_95J75_125_7728_n20), .CO(
DP_OP_95J75_125_7728_n19), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[36]) );
CMPR32X2TS DP_OP_95J75_125_7728_U19 ( .A(DP_OP_95J75_125_7728_n77), .B(
add_subt_module_S_A_S_Oper_A[37]), .C(DP_OP_95J75_125_7728_n19), .CO(
DP_OP_95J75_125_7728_n18), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[37]) );
CMPR32X2TS DP_OP_95J75_125_7728_U18 ( .A(DP_OP_95J75_125_7728_n76), .B(
add_subt_module_S_A_S_Oper_A[38]), .C(DP_OP_95J75_125_7728_n18), .CO(
DP_OP_95J75_125_7728_n17), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[38]) );
CMPR32X2TS DP_OP_95J75_125_7728_U17 ( .A(DP_OP_95J75_125_7728_n75), .B(
add_subt_module_S_A_S_Oper_A[39]), .C(DP_OP_95J75_125_7728_n17), .CO(
DP_OP_95J75_125_7728_n16), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[39]) );
CMPR32X2TS DP_OP_95J75_125_7728_U16 ( .A(DP_OP_95J75_125_7728_n74), .B(
add_subt_module_S_A_S_Oper_A[40]), .C(DP_OP_95J75_125_7728_n16), .CO(
DP_OP_95J75_125_7728_n15), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[40]) );
CMPR32X2TS DP_OP_95J75_125_7728_U15 ( .A(DP_OP_95J75_125_7728_n73), .B(
add_subt_module_S_A_S_Oper_A[41]), .C(DP_OP_95J75_125_7728_n15), .CO(
DP_OP_95J75_125_7728_n14), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[41]) );
CMPR32X2TS DP_OP_95J75_125_7728_U14 ( .A(DP_OP_95J75_125_7728_n72), .B(
add_subt_module_S_A_S_Oper_A[42]), .C(DP_OP_95J75_125_7728_n14), .CO(
DP_OP_95J75_125_7728_n13), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[42]) );
CMPR32X2TS DP_OP_95J75_125_7728_U13 ( .A(DP_OP_95J75_125_7728_n71), .B(
add_subt_module_S_A_S_Oper_A[43]), .C(DP_OP_95J75_125_7728_n13), .CO(
DP_OP_95J75_125_7728_n12), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[43]) );
CMPR32X2TS DP_OP_95J75_125_7728_U12 ( .A(DP_OP_95J75_125_7728_n70), .B(
add_subt_module_S_A_S_Oper_A[44]), .C(DP_OP_95J75_125_7728_n12), .CO(
DP_OP_95J75_125_7728_n11), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[44]) );
CMPR32X2TS DP_OP_95J75_125_7728_U11 ( .A(DP_OP_95J75_125_7728_n69), .B(
add_subt_module_S_A_S_Oper_A[45]), .C(DP_OP_95J75_125_7728_n11), .CO(
DP_OP_95J75_125_7728_n10), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[45]) );
CMPR32X2TS DP_OP_95J75_125_7728_U10 ( .A(DP_OP_95J75_125_7728_n68), .B(
add_subt_module_S_A_S_Oper_A[46]), .C(DP_OP_95J75_125_7728_n10), .CO(
DP_OP_95J75_125_7728_n9), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[46]) );
CMPR32X2TS DP_OP_95J75_125_7728_U9 ( .A(DP_OP_95J75_125_7728_n67), .B(
add_subt_module_S_A_S_Oper_A[47]), .C(DP_OP_95J75_125_7728_n9), .CO(
DP_OP_95J75_125_7728_n8), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[47]) );
CMPR32X2TS DP_OP_95J75_125_7728_U8 ( .A(DP_OP_95J75_125_7728_n66), .B(
add_subt_module_S_A_S_Oper_A[48]), .C(DP_OP_95J75_125_7728_n8), .CO(
DP_OP_95J75_125_7728_n7), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[48]) );
CMPR32X2TS DP_OP_95J75_125_7728_U7 ( .A(DP_OP_95J75_125_7728_n65), .B(
add_subt_module_S_A_S_Oper_A[49]), .C(DP_OP_95J75_125_7728_n7), .CO(
DP_OP_95J75_125_7728_n6), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[49]) );
CMPR32X2TS DP_OP_95J75_125_7728_U6 ( .A(DP_OP_95J75_125_7728_n64), .B(
add_subt_module_S_A_S_Oper_A[50]), .C(DP_OP_95J75_125_7728_n6), .CO(
DP_OP_95J75_125_7728_n5), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[50]) );
CMPR32X2TS DP_OP_95J75_125_7728_U5 ( .A(DP_OP_95J75_125_7728_n63), .B(
add_subt_module_S_A_S_Oper_A[51]), .C(DP_OP_95J75_125_7728_n5), .CO(
DP_OP_95J75_125_7728_n4), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[51]) );
CMPR32X2TS DP_OP_95J75_125_7728_U4 ( .A(DP_OP_95J75_125_7728_n62), .B(
add_subt_module_S_A_S_Oper_A[52]), .C(DP_OP_95J75_125_7728_n4), .CO(
DP_OP_95J75_125_7728_n3), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[52]) );
CMPR32X2TS DP_OP_95J75_125_7728_U3 ( .A(DP_OP_95J75_125_7728_n61), .B(
add_subt_module_S_A_S_Oper_A[53]), .C(DP_OP_95J75_125_7728_n3), .CO(
DP_OP_95J75_125_7728_n2), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[53]) );
CMPR32X2TS DP_OP_95J75_125_7728_U2 ( .A(DP_OP_95J75_125_7728_n60), .B(
add_subt_module_S_A_S_Oper_A[54]), .C(DP_OP_95J75_125_7728_n2), .CO(
DP_OP_95J75_125_7728_n1), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[54]) );
CMPR32X2TS DP_OP_92J75_122_9081_U12 ( .A(add_subt_module_S_Oper_A_exp[0]),
.B(add_subt_module_FSM_exp_operation_A_S), .C(DP_OP_92J75_122_9081_n26), .CO(DP_OP_92J75_122_9081_n11), .S(
add_subt_module_Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_92J75_122_9081_U11 ( .A(DP_OP_92J75_122_9081_n25), .B(
add_subt_module_S_Oper_A_exp[1]), .C(DP_OP_92J75_122_9081_n11), .CO(
DP_OP_92J75_122_9081_n10), .S(
add_subt_module_Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_92J75_122_9081_U10 ( .A(DP_OP_92J75_122_9081_n24), .B(
add_subt_module_S_Oper_A_exp[2]), .C(DP_OP_92J75_122_9081_n10), .CO(
DP_OP_92J75_122_9081_n9), .S(
add_subt_module_Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_92J75_122_9081_U9 ( .A(DP_OP_92J75_122_9081_n23), .B(
add_subt_module_S_Oper_A_exp[3]), .C(DP_OP_92J75_122_9081_n9), .CO(
DP_OP_92J75_122_9081_n8), .S(
add_subt_module_Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_92J75_122_9081_U8 ( .A(DP_OP_92J75_122_9081_n22), .B(
add_subt_module_S_Oper_A_exp[4]), .C(DP_OP_92J75_122_9081_n8), .CO(
DP_OP_92J75_122_9081_n7), .S(
add_subt_module_Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_92J75_122_9081_U7 ( .A(DP_OP_92J75_122_9081_n21), .B(
add_subt_module_S_Oper_A_exp[5]), .C(DP_OP_92J75_122_9081_n7), .CO(
DP_OP_92J75_122_9081_n6), .S(
add_subt_module_Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_92J75_122_9081_U6 ( .A(DP_OP_92J75_122_9081_n20), .B(
add_subt_module_S_Oper_A_exp[6]), .C(DP_OP_92J75_122_9081_n6), .CO(
DP_OP_92J75_122_9081_n5), .S(
add_subt_module_Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_92J75_122_9081_U5 ( .A(DP_OP_92J75_122_9081_n19), .B(
add_subt_module_S_Oper_A_exp[7]), .C(DP_OP_92J75_122_9081_n5), .CO(
DP_OP_92J75_122_9081_n4), .S(
add_subt_module_Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_92J75_122_9081_U4 ( .A(DP_OP_92J75_122_9081_n18), .B(
add_subt_module_S_Oper_A_exp[8]), .C(DP_OP_92J75_122_9081_n4), .CO(
DP_OP_92J75_122_9081_n3), .S(
add_subt_module_Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS DP_OP_92J75_122_9081_U3 ( .A(DP_OP_92J75_122_9081_n17), .B(
add_subt_module_S_Oper_A_exp[9]), .C(DP_OP_92J75_122_9081_n3), .CO(
DP_OP_92J75_122_9081_n2), .S(
add_subt_module_Exp_Operation_Module_Data_S[9]) );
CMPR32X2TS DP_OP_92J75_122_9081_U2 ( .A(DP_OP_92J75_122_9081_n16), .B(
add_subt_module_S_Oper_A_exp[10]), .C(DP_OP_92J75_122_9081_n2), .CO(
DP_OP_92J75_122_9081_n1), .S(
add_subt_module_Exp_Operation_Module_Data_S[10]) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n2843), .CK(n5334), .RN(n5521), .Q(
d_ff3_LUT_out[48]) );
DFFRX1TS add_subt_module_YRegister_Q_reg_63_ ( .D(n1946), .CK(n5425), .RN(
n5288), .Q(add_subt_module_intDY[63]) );
DFFRX4TS cont_iter_count_reg_3_ ( .D(n2924), .CK(n3261), .RN(n5528), .Q(
cont_iter_out[3]), .QN(n5023) );
DFFRX4TS add_subt_module_FS_Module_state_reg_reg_1_ ( .D(n2928), .CK(n5421),
.RN(n5274), .Q(add_subt_module_FS_Module_state_reg[1]) );
DFFRX4TS cont_iter_count_reg_1_ ( .D(n2922), .CK(n5403), .RN(n5529), .Q(
cont_iter_out[1]), .QN(n5056) );
DFFRX1TS reg_shift_x_Q_reg_61_ ( .D(n2773), .CK(n5340), .RN(n5515), .Q(
d_ff3_sh_x_out[61]) );
DFFRX1TS reg_LUT_Q_reg_42_ ( .D(n2837), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[42]) );
DFFRX1TS reg_LUT_Q_reg_37_ ( .D(n2832), .CK(n5335), .RN(n5520), .Q(
d_ff3_LUT_out[37]) );
DFFRX1TS reg_LUT_Q_reg_47_ ( .D(n2842), .CK(n5360), .RN(n5521), .Q(
d_ff3_LUT_out[47]) );
DFFRX1TS reg_LUT_Q_reg_50_ ( .D(n2845), .CK(n3266), .RN(n5521), .Q(
d_ff3_LUT_out[50]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n2797), .CK(n5339), .RN(n5516), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_17_ ( .D(n2812), .CK(n5420), .RN(n5518), .Q(
d_ff3_LUT_out[17]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n2801), .CK(n5338), .RN(n5517), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n2810), .CK(n5339), .RN(n5518), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n2806), .CK(n5337), .RN(n5517), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_35_ ( .D(n2830), .CK(n5338), .RN(n5520), .Q(
d_ff3_LUT_out[35]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n2822), .CK(n5339), .RN(n5519), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_shift_x_Q_reg_57_ ( .D(n2777), .CK(n5441), .RN(n5514), .Q(
d_ff3_sh_x_out[57]) );
DFFRX1TS reg_shift_x_Q_reg_59_ ( .D(n2775), .CK(n5436), .RN(n5515), .Q(
d_ff3_sh_x_out[59]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]),
.CK(n5363), .RN(n5278), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .QN(
n5149) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]),
.CK(n5356), .RN(n5277), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .QN(
n5148) );
DFFRX1TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(
n5356), .RN(n5274), .Q(n2959), .QN(n2978) );
DFFRX2TS add_subt_module_Sel_D_Q_reg_0_ ( .D(n2663), .CK(n5418), .RN(n1959),
.Q(n5009), .QN(n5202) );
DFFRX2TS cont_iter_count_reg_2_ ( .D(n2921), .CK(n5421), .RN(n5529), .Q(
cont_iter_out[2]), .QN(n2958) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n2453), .CK(n5387), .RN(n5492), .Q(
d_ff_Zn[42]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n2133), .CK(n5396), .RN(n5531), .Q(
d_ff3_sh_y_out[42]) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_1_ ( .D(n2935), .CK(n3009), .RN(n1959),
.Q(add_subt_module_FSM_selector_B[1]), .QN(n5208) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(
n2561), .CK(n5423), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[26]), .QN(n5197) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(
n2548), .CK(n5393), .RN(n5313), .Q(
add_subt_module_Sgf_normalized_result[13]), .QN(n5182) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(
n2572), .CK(n3257), .RN(n5318), .Q(
add_subt_module_Sgf_normalized_result[37]), .QN(n5167) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(
n2587), .CK(n5377), .RN(n5321), .Q(
add_subt_module_Sgf_normalized_result[52]), .QN(n5152) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
n2537), .CK(n5425), .RN(n5311), .Q(
add_subt_module_Sgf_normalized_result[2]), .QN(n5135) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(n2516), .CK(n5354), .RN(n5509), .Q(
d_ff_Yn[58]), .QN(n5090) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1821), .CK(n5441), .RN(n5297), .Q(add_subt_module_DmP[42]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1718), .CK(n5452), .RN(n5313), .Q(add_subt_module_DMP[12]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1703),
.CK(n5451), .RN(n5311), .Q(add_subt_module_DMP[0]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1874), .CK(n5441), .RN(n5320), .Q(add_subt_module_DMP[46]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1757), .CK(n5345), .RN(n5316), .Q(add_subt_module_DMP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1855), .CK(n5436), .RN(n5294), .Q(add_subt_module_DmP[45]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n2798), .CK(n5337), .RN(n5516), .Q(
d_ff3_LUT_out[3]) );
AOI222X4TS U3131 ( .A0(n4800), .A1(n3007), .B0(n4808), .B1(n4793), .C0(n4792), .C1(n2995), .Y(n4812) );
BUFX4TS U3132 ( .A(clk), .Y(n3259) );
CMPR32X2TS U3133 ( .A(d_ff2_Y[55]), .B(n5023), .C(n4185), .CO(n4021), .S(
n4186) );
BUFX6TS U3134 ( .A(n3259), .Y(n5361) );
BUFX6TS U3135 ( .A(n3259), .Y(n5335) );
BUFX6TS U3136 ( .A(n3273), .Y(n5385) );
BUFX6TS U3137 ( .A(n3273), .Y(n5384) );
BUFX6TS U3138 ( .A(n3273), .Y(n5382) );
BUFX6TS U3139 ( .A(n3273), .Y(n5369) );
BUFX6TS U3140 ( .A(n3271), .Y(n3273) );
CLKBUFX3TS U3141 ( .A(n3889), .Y(n3869) );
NAND2X4TS U3142 ( .A(n4991), .B(n4987), .Y(n3729) );
AOI21X2TS U3143 ( .A0(n2989), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3099), .Y(n2970) );
AOI222X1TS U3144 ( .A0(n3843), .A1(d_ff2_Z[53]), .B0(n3636), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n3854), .Y(n3736) );
NOR2X2TS U3145 ( .A(n3100), .B(n3516), .Y(n3084) );
CLKBUFX2TS U3146 ( .A(n3993), .Y(n3002) );
AOI21X2TS U3147 ( .A0(n4849), .A1(n5108), .B0(n4836), .Y(n2963) );
AND2X2TS U3148 ( .A(n3007), .B(n4789), .Y(n3397) );
NOR2X4TS U3149 ( .A(n3081), .B(n3077), .Y(n3561) );
OAI21X2TS U3150 ( .A0(n5128), .A1(n4814), .B0(n3967), .Y(n2962) );
NOR2X4TS U3151 ( .A(sel_mux_1_reg), .B(n4248), .Y(n3636) );
OR3X2TS U3152 ( .A(n3015), .B(n3082), .C(n3100), .Y(n4666) );
OR2X2TS U3153 ( .A(n3781), .B(n4814), .Y(n3306) );
AND2X2TS U3154 ( .A(n3007), .B(n4791), .Y(n3289) );
ADDFX1TS U3155 ( .A(d_ff2_X[55]), .B(n5023), .CI(n4174), .CO(n4382), .S(
n4175) );
OR2X2TS U3156 ( .A(n3607), .B(n4873), .Y(n3320) );
AO22X2TS U3157 ( .A0(add_subt_module_LZA_output[5]), .A1(n2984), .B0(
add_subt_module_exp_oper_result[5]), .B1(n2992), .Y(n3100) );
ADDFX1TS U3158 ( .A(d_ff2_Y[54]), .B(n2958), .CI(n4183), .CO(n4185), .S(
n4184) );
ADDFX1TS U3159 ( .A(d_ff2_X[54]), .B(n2988), .CI(n4172), .CO(n4174), .S(
n4173) );
AOI31X4TS U3160 ( .A0(n3290), .A1(n5010), .A2(n5054), .B0(n4821), .Y(n3291)
);
OA21X2TS U3161 ( .A0(n3945), .A1(n4501), .B0(n3290), .Y(n4671) );
NAND3X2TS U3162 ( .A(n2982), .B(n3955), .C(n5011), .Y(n3936) );
NOR2X4TS U3163 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n4966), .Y(
n3390) );
CLKBUFX2TS U3164 ( .A(n5023), .Y(n2985) );
INVX2TS U3165 ( .A(n3015), .Y(n3081) );
AO22XLTS U3166 ( .A0(add_subt_module_LZA_output[3]), .A1(n2983), .B0(n2992),
.B1(add_subt_module_exp_oper_result[3]), .Y(n3080) );
CLKAND2X2TS U3167 ( .A(n3566), .B(n3699), .Y(n2966) );
AOI222X4TS U3168 ( .A0(n4797), .A1(n3007), .B0(n4792), .B1(n4808), .C0(n4787), .C1(n2994), .Y(n4805) );
CLKBUFX3TS U3169 ( .A(n3219), .Y(n4263) );
CLKINVX3TS U3170 ( .A(n4261), .Y(n4248) );
CLKBUFX3TS U3171 ( .A(n4698), .Y(n4702) );
AOI2BB1XLTS U3172 ( .A0N(n4814), .A1N(add_subt_module_Add_Subt_result[52]),
.B0(n3980), .Y(n3993) );
AO21XLTS U3173 ( .A0(n4849), .A1(n5107), .B0(n3965), .Y(n2965) );
AO21XLTS U3174 ( .A0(n4849), .A1(n5104), .B0(n3966), .Y(n2957) );
AO21XLTS U3175 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .B0(
n3499), .Y(n2972) );
AO21XLTS U3176 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(
n3504), .Y(n2971) );
AO21XLTS U3177 ( .A0(n3075), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(
n3106), .Y(n2973) );
AO21XLTS U3178 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(
n3517), .Y(n2974) );
AO21XLTS U3179 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(
n3101), .Y(n2975) );
INVX2TS U3180 ( .A(n3320), .Y(n3566) );
OAI32X1TS U3181 ( .A0(n4675), .A1(cordic_FSM_state_reg[3]), .A2(n4674), .B0(
n4673), .B1(n4675), .Y(cordic_FSM_state_next_1_) );
OAI32X1TS U3182 ( .A0(n4949), .A1(n2959), .A2(n4672), .B0(n5060), .B1(n4949),
.Y(n4673) );
NAND2BXLTS U3183 ( .AN(d_ff3_LUT_out[48]), .B(n3952), .Y(n2843) );
AOI222X1TS U3184 ( .A0(n3017), .A1(d_ff2_Z[27]), .B0(n3821), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n3846), .Y(n3638) );
AOI222X1TS U3185 ( .A0(n3004), .A1(d_ff2_Z[36]), .B0(n3764), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n4321), .Y(n3637) );
AOI222X1TS U3186 ( .A0(n4101), .A1(d_ff2_Z[23]), .B0(n3821), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n4310), .Y(n3762) );
AOI222X1TS U3187 ( .A0(n4101), .A1(d_ff2_Z[41]), .B0(n3833), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n4321), .Y(n3757) );
AOI222X1TS U3188 ( .A0(n4101), .A1(d_ff2_Z[11]), .B0(n3828), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n3836), .Y(n3755) );
AOI222X1TS U3189 ( .A0(n4101), .A1(d_ff2_Z[5]), .B0(n3839), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n3854), .Y(n3747) );
AOI222X1TS U3190 ( .A0(n4101), .A1(d_ff2_Z[2]), .B0(n3839), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n3846), .Y(n3838) );
CLKINVX3TS U3191 ( .A(rst), .Y(n3278) );
INVX2TS U3192 ( .A(n4919), .Y(n4301) );
AO22X2TS U3193 ( .A0(add_subt_module_LZA_output[1]), .A1(n2983), .B0(n2991),
.B1(add_subt_module_exp_oper_result[1]), .Y(n2960) );
INVX2TS U3194 ( .A(n3216), .Y(n4963) );
AOI21X2TS U3195 ( .A0(n4849), .A1(n5064), .B0(n3969), .Y(n2961) );
BUFX4TS U3196 ( .A(n3259), .Y(n5362) );
OR2X1TS U3197 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n4964), .Y(
n2964) );
OR2X1TS U3198 ( .A(n3007), .B(n4791), .Y(n2967) );
AND2X2TS U3199 ( .A(n4791), .B(n2960), .Y(n2968) );
NOR3X2TS U3200 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[0]), .C(
add_subt_module_FS_Module_state_reg[3]), .Y(n2969) );
AOI21X2TS U3201 ( .A0(n3075), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n3560), .Y(n2976) );
AOI21X2TS U3202 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .B0(
n3560), .Y(n2977) );
CLKBUFX3TS U3203 ( .A(n3292), .Y(n4820) );
CLKBUFX3TS U3204 ( .A(n4820), .Y(n4766) );
OR2X1TS U3205 ( .A(n3015), .B(n3077), .Y(n2979) );
OR2X1TS U3206 ( .A(add_subt_module_FSM_selector_B[1]), .B(n5075), .Y(n2980)
);
OR2X1TS U3207 ( .A(add_subt_module_FSM_selector_B[0]), .B(
add_subt_module_FSM_selector_B[1]), .Y(n2981) );
CLKBUFX2TS U3208 ( .A(n4963), .Y(n4298) );
INVX2TS U3209 ( .A(n2978), .Y(n2982) );
INVX2TS U3210 ( .A(n2980), .Y(n2983) );
INVX2TS U3211 ( .A(n2980), .Y(n2984) );
INVX2TS U3212 ( .A(n4301), .Y(n2986) );
INVX2TS U3213 ( .A(n2986), .Y(n2987) );
INVX2TS U3214 ( .A(cont_iter_out[2]), .Y(n2988) );
INVX2TS U3215 ( .A(n2979), .Y(n2989) );
INVX2TS U3216 ( .A(n2979), .Y(n2990) );
INVX2TS U3217 ( .A(n2981), .Y(n2991) );
INVX2TS U3218 ( .A(n2981), .Y(n2992) );
INVX2TS U3219 ( .A(n2967), .Y(n2993) );
INVX2TS U3220 ( .A(n2967), .Y(n2994) );
INVX2TS U3221 ( .A(n2967), .Y(n2995) );
BUFX6TS U3222 ( .A(n5374), .Y(n5415) );
BUFX6TS U3223 ( .A(n5329), .Y(n5428) );
BUFX6TS U3224 ( .A(n5362), .Y(n5437) );
BUFX6TS U3225 ( .A(n5362), .Y(n5435) );
BUFX6TS U3226 ( .A(n3263), .Y(n5429) );
BUFX6TS U3227 ( .A(n5345), .Y(n5444) );
BUFX6TS U3228 ( .A(n5423), .Y(n5416) );
BUFX6TS U3229 ( .A(n5404), .Y(n5407) );
BUFX6TS U3230 ( .A(n5362), .Y(n5434) );
BUFX6TS U3231 ( .A(n5362), .Y(n5436) );
BUFX6TS U3232 ( .A(n5362), .Y(n5441) );
BUFX6TS U3233 ( .A(n5403), .Y(n5351) );
BUFX6TS U3234 ( .A(n5355), .Y(n5344) );
BUFX6TS U3235 ( .A(n5391), .Y(n5409) );
BUFX6TS U3236 ( .A(n3260), .Y(n5412) );
BUFX6TS U3237 ( .A(n3256), .Y(n5388) );
BUFX6TS U3238 ( .A(n5439), .Y(n5443) );
BUFX6TS U3239 ( .A(n5342), .Y(n5346) );
BUFX6TS U3240 ( .A(n5421), .Y(n5357) );
BUFX6TS U3241 ( .A(n5422), .Y(n5430) );
BUFX6TS U3242 ( .A(n5425), .Y(n5431) );
BUFX6TS U3243 ( .A(n3257), .Y(n5408) );
BUFX3TS U3244 ( .A(n3273), .Y(n5383) );
CLKINVX6TS U3245 ( .A(n3008), .Y(n2996) );
BUFX6TS U3246 ( .A(n3270), .Y(n5358) );
BUFX6TS U3247 ( .A(n3274), .Y(n5328) );
BUFX6TS U3248 ( .A(n3272), .Y(n5333) );
BUFX4TS U3249 ( .A(n3264), .Y(n5332) );
BUFX6TS U3250 ( .A(n3267), .Y(n5331) );
BUFX4TS U3251 ( .A(n3255), .Y(n5403) );
BUFX6TS U3252 ( .A(n3255), .Y(n5373) );
BUFX4TS U3253 ( .A(n3268), .Y(n5421) );
BUFX6TS U3254 ( .A(n3268), .Y(n5374) );
BUFX6TS U3255 ( .A(n5371), .Y(n5370) );
BUFX6TS U3256 ( .A(n5371), .Y(n5379) );
BUFX6TS U3257 ( .A(n5371), .Y(n5368) );
BUFX6TS U3258 ( .A(n5371), .Y(n5375) );
BUFX6TS U3259 ( .A(n5371), .Y(n5377) );
BUFX6TS U3260 ( .A(n5329), .Y(n5426) );
BUFX4TS U3261 ( .A(n5329), .Y(n5411) );
BUFX4TS U3262 ( .A(n5329), .Y(n5410) );
BUFX4TS U3263 ( .A(n5452), .Y(n5451) );
BUFX4TS U3264 ( .A(n5452), .Y(n5450) );
OR4X4TS U3265 ( .A(cordic_FSM_state_reg[0]), .B(n2982), .C(n5024), .D(n5060),
.Y(n4166) );
CLKINVX3TS U3266 ( .A(n3952), .Y(n4949) );
INVX2TS U3267 ( .A(n3952), .Y(n4940) );
CLKBUFX3TS U3268 ( .A(n3031), .Y(n3277) );
CLKBUFX3TS U3269 ( .A(n5531), .Y(n3279) );
CLKBUFX3TS U3270 ( .A(n5532), .Y(n3031) );
NOR4X1TS U3271 ( .A(n2982), .B(n5024), .C(n5060), .D(n5011), .Y(ready_cordic) );
INVX2TS U3272 ( .A(n4501), .Y(n4498) );
NOR2X2TS U3273 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n5088), .Y(
n4501) );
AOI211X1TS U3274 ( .A0(n3478), .A1(n5010), .B0(
add_subt_module_FS_Module_state_reg[0]), .C0(n3946), .Y(n3479) );
NOR2X2TS U3275 ( .A(n4578), .B(n4199), .Y(n4933) );
CLKBUFX3TS U3276 ( .A(n4963), .Y(n4262) );
INVX1TS U3277 ( .A(n4931), .Y(n4024) );
OAI21X2TS U3278 ( .A0(n4928), .A1(n3931), .B0(n3930), .Y(n4257) );
CLKBUFX3TS U3279 ( .A(n4041), .Y(n4011) );
AOI222X1TS U3280 ( .A0(n4248), .A1(d_ff2_Z[54]), .B0(n3636), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n4312), .Y(n3735) );
AOI222X1TS U3281 ( .A0(n4248), .A1(d_ff2_Z[51]), .B0(n3842), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n4312), .Y(n3739) );
AOI222X1TS U3282 ( .A0(n4248), .A1(d_ff2_Z[57]), .B0(n3636), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n3851), .Y(n3845) );
NOR4X1TS U3283 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(
add_subt_module_add_overflow_flag), .C(n4499), .D(n4842), .Y(n3079) );
NOR2X2TS U3284 ( .A(d_ff2_Y[59]), .B(n4398), .Y(n4397) );
NOR2X2TS U3285 ( .A(d_ff2_X[59]), .B(n4493), .Y(n4451) );
OAI21X2TS U3286 ( .A0(cont_iter_out[1]), .A1(cont_iter_out[0]), .B0(n2958),
.Y(n4954) );
OAI21X2TS U3287 ( .A0(cont_iter_out[2]), .A1(n4192), .B0(n4476), .Y(n4955)
);
INVX2TS U3288 ( .A(n4247), .Y(n4476) );
OAI21X2TS U3289 ( .A0(cont_iter_out[3]), .A1(n4481), .B0(n4932), .Y(n4943)
);
CLKINVX3TS U3290 ( .A(n4702), .Y(n4847) );
CLKBUFX3TS U3291 ( .A(n4147), .Y(n4508) );
CLKBUFX3TS U3292 ( .A(n4147), .Y(n4365) );
NOR2X2TS U3293 ( .A(n4367), .B(n3247), .Y(n4435) );
AOI21X2TS U3294 ( .A0(n2989), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(
n3105), .Y(n3527) );
AOI21X2TS U3295 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .A1(
n2989), .B0(n3503), .Y(n3600) );
INVX2TS U3296 ( .A(n2975), .Y(n2997) );
INVX2TS U3297 ( .A(n2973), .Y(n2998) );
INVX2TS U3298 ( .A(n2974), .Y(n2999) );
INVX2TS U3299 ( .A(n2971), .Y(n3000) );
INVX2TS U3300 ( .A(n2972), .Y(n3001) );
NOR2X2TS U3301 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n5067), .Y(
n3290) );
NOR2X2TS U3302 ( .A(cordic_FSM_state_reg[0]), .B(n2982), .Y(n3932) );
OAI32X1TS U3303 ( .A0(n3865), .A1(n3952), .A2(n3663), .B0(d_ff3_LUT_out[53]),
.B1(n4940), .Y(n3664) );
OAI21X2TS U3304 ( .A0(n3865), .A1(n2958), .B0(n4945), .Y(n4946) );
NOR2X2TS U3305 ( .A(cont_iter_out[1]), .B(n3026), .Y(n3865) );
NOR4X2TS U3306 ( .A(n4366), .B(cont_iter_out[3]), .C(n4951), .D(n5057), .Y(
n4032) );
CLKINVX3TS U3307 ( .A(n4766), .Y(n4773) );
NOR2X2TS U3308 ( .A(n3254), .B(n3773), .Y(n4675) );
NOR2X2TS U3309 ( .A(n2982), .B(n5011), .Y(n3254) );
INVX2TS U3310 ( .A(n3306), .Y(n3780) );
CLKINVX3TS U3311 ( .A(n3306), .Y(n3569) );
INVX2TS U3312 ( .A(n3306), .Y(n3596) );
CLKINVX3TS U3313 ( .A(n3320), .Y(n3705) );
CLKINVX3TS U3314 ( .A(n4311), .Y(n3832) );
INVX2TS U3315 ( .A(n4311), .Y(n4321) );
CLKINVX3TS U3316 ( .A(n4311), .Y(n3763) );
CLKINVX3TS U3317 ( .A(n4311), .Y(n4310) );
OAI211X2TS U3318 ( .A0(n3213), .A1(n3212), .B0(n3211), .C0(n3210), .Y(n4987)
);
CLKINVX3TS U3319 ( .A(add_subt_module_FSM_selector_C), .Y(n4821) );
CLKINVX3TS U3320 ( .A(n4834), .Y(n4914) );
CLKINVX3TS U3321 ( .A(n4834), .Y(n4724) );
CLKINVX3TS U3322 ( .A(n4834), .Y(n4828) );
CLKINVX3TS U3323 ( .A(n4834), .Y(n4890) );
BUFX3TS U3324 ( .A(n4766), .Y(n4834) );
CLKBUFX3TS U3325 ( .A(n4968), .Y(n4967) );
CLKBUFX3TS U3326 ( .A(n4980), .Y(n4968) );
CLKINVX3TS U3327 ( .A(n3790), .Y(n3805) );
CLKINVX3TS U3328 ( .A(n3790), .Y(n5001) );
CLKINVX3TS U3329 ( .A(n3790), .Y(n3792) );
CLKINVX3TS U3330 ( .A(n3790), .Y(n4998) );
CLKINVX3TS U3331 ( .A(n3790), .Y(n3812) );
CLKINVX3TS U3332 ( .A(n3790), .Y(n3797) );
CLKINVX3TS U3333 ( .A(n4671), .Y(n3550) );
CLKINVX3TS U3334 ( .A(n4671), .Y(n3700) );
CLKINVX3TS U3335 ( .A(n4671), .Y(n4669) );
INVX2TS U3336 ( .A(n4831), .Y(n4769) );
CLKINVX3TS U3337 ( .A(n4831), .Y(n4861) );
CLKINVX3TS U3338 ( .A(n4831), .Y(n4888) );
CLKINVX3TS U3339 ( .A(n2968), .Y(n4776) );
CLKINVX3TS U3340 ( .A(n3100), .Y(n3521) );
CLKINVX3TS U3341 ( .A(n3100), .Y(n3565) );
BUFX4TS U3342 ( .A(n3258), .Y(n5438) );
BUFX4TS U3343 ( .A(n5453), .Y(n5439) );
BUFX4TS U3344 ( .A(n5453), .Y(n3265) );
CLKINVX3TS U3345 ( .A(n4551), .Y(n4564) );
INVX2TS U3346 ( .A(n4298), .Y(n3003) );
AOI222X1TS U3347 ( .A0(n4101), .A1(d_ff2_Z[19]), .B0(n3828), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n3763), .Y(n3760) );
AOI222X1TS U3348 ( .A0(n4101), .A1(d_ff2_Z[8]), .B0(n3839), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n3854), .Y(n3756) );
CLKBUFX3TS U3349 ( .A(n3936), .Y(n4108) );
CLKBUFX3TS U3350 ( .A(n3291), .Y(n4711) );
NAND2X2TS U3351 ( .A(n4932), .B(n4367), .Y(n4944) );
CLKINVX3TS U3352 ( .A(n4985), .Y(n3851) );
CLKBUFX3TS U3353 ( .A(n4299), .Y(n4985) );
CLKINVX3TS U3354 ( .A(n4262), .Y(n3840) );
CLKINVX3TS U3355 ( .A(n4262), .Y(n3848) );
CLKINVX3TS U3356 ( .A(n4298), .Y(n3852) );
INVX2TS U3357 ( .A(n4261), .Y(n3004) );
AOI222X1TS U3358 ( .A0(n3834), .A1(d_ff2_Z[46]), .B0(n3833), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n4310), .Y(n3835) );
AOI222X1TS U3359 ( .A0(n3834), .A1(d_ff2_Z[42]), .B0(n3833), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n3832), .Y(n3826) );
AOI222X1TS U3360 ( .A0(n3834), .A1(d_ff2_Z[37]), .B0(n3764), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n3763), .Y(n3759) );
AOI222X1TS U3361 ( .A0(n3834), .A1(d_ff2_Z[39]), .B0(n3764), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n4321), .Y(n3758) );
AOI222X1TS U3362 ( .A0(n3834), .A1(d_ff2_Z[40]), .B0(n3833), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n3832), .Y(n3752) );
AOI222X1TS U3363 ( .A0(n3834), .A1(d_ff2_Z[43]), .B0(n3833), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n3851), .Y(n3750) );
AOI222X1TS U3364 ( .A0(n3834), .A1(d_ff2_Z[45]), .B0(n3833), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n3851), .Y(n3748) );
AOI222X1TS U3365 ( .A0(n3834), .A1(d_ff2_Z[49]), .B0(n3833), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n3851), .Y(n3744) );
AOI222X1TS U3366 ( .A0(n3834), .A1(d_ff2_Z[48]), .B0(n3833), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n4310), .Y(n3740) );
CLKBUFX3TS U3367 ( .A(n4963), .Y(n4261) );
AOI211X2TS U3368 ( .A0(n4961), .A1(n4366), .B0(n4508), .C0(n4952), .Y(n4942)
);
OAI32X1TS U3369 ( .A0(cont_iter_out[2]), .A1(n4192), .A2(n4924), .B0(n4926),
.B1(n2988), .Y(n2921) );
NAND2X2TS U3370 ( .A(n3294), .B(n4039), .Y(n4924) );
CLKBUFX3TS U3371 ( .A(n4239), .Y(n4229) );
INVX2TS U3372 ( .A(n4551), .Y(n4562) );
CLKINVX3TS U3373 ( .A(n4551), .Y(n4306) );
CLKINVX3TS U3374 ( .A(n4551), .Y(n4588) );
CLKINVX3TS U3375 ( .A(n5202), .Y(n4592) );
CLKINVX3TS U3376 ( .A(n5202), .Y(n4549) );
CLKBUFX3TS U3377 ( .A(n4421), .Y(n4369) );
CLKBUFX3TS U3378 ( .A(n4054), .Y(n4193) );
CLKBUFX3TS U3379 ( .A(n4997), .Y(n3911) );
CLKBUFX3TS U3380 ( .A(n3881), .Y(n4997) );
CLKBUFX3TS U3381 ( .A(n4169), .Y(n4368) );
CLKBUFX3TS U3382 ( .A(n4169), .Y(n4330) );
CLKBUFX3TS U3383 ( .A(n4003), .Y(n4458) );
CLKBUFX3TS U3384 ( .A(n4003), .Y(n4054) );
OAI21X2TS U3385 ( .A0(n3480), .A1(n3122), .B0(
add_subt_module_add_overflow_flag), .Y(n3087) );
AOI211X4TS U3386 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .A1(
n3559), .B0(n3558), .C0(n3557), .Y(n3698) );
NOR2X4TS U3387 ( .A(n3082), .B(n3081), .Y(n3559) );
NOR3X4TS U3388 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(
add_subt_module_FS_Module_state_reg[3]), .C(n3946), .Y(n4991) );
NAND2X2TS U3389 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n5067), .Y(
n3946) );
CLKBUFX3TS U3390 ( .A(n3278), .Y(n3032) );
CLKBUFX3TS U3391 ( .A(n3278), .Y(n3030) );
CLKBUFX3TS U3392 ( .A(n3278), .Y(n3028) );
CLKBUFX3TS U3393 ( .A(n3240), .Y(n4403) );
CLKBUFX3TS U3394 ( .A(n4352), .Y(n4958) );
CLKBUFX3TS U3395 ( .A(n4569), .Y(n4020) );
CLKINVX3TS U3396 ( .A(n4808), .Y(n4746) );
CLKBUFX3TS U3397 ( .A(n2968), .Y(n4808) );
BUFX4TS U3398 ( .A(n3272), .Y(n5397) );
BUFX4TS U3399 ( .A(n3264), .Y(n5394) );
BUFX6TS U3400 ( .A(clk), .Y(n3258) );
NAND2X1TS U3401 ( .A(n3945), .B(n5067), .Y(n4964) );
INVX2TS U3402 ( .A(n3945), .Y(n3076) );
NOR2X2TS U3403 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(n5010), .Y(
n3945) );
CLKBUFX3TS U3404 ( .A(n4510), .Y(n4571) );
CLKBUFX3TS U3405 ( .A(n4485), .Y(n4581) );
CLKBUFX3TS U3406 ( .A(n4485), .Y(n4489) );
CLKBUFX3TS U3407 ( .A(n3390), .Y(n4485) );
CLKBUFX3TS U3408 ( .A(n3390), .Y(n4492) );
CLKBUFX3TS U3409 ( .A(n3390), .Y(n4510) );
NOR4X2TS U3410 ( .A(add_subt_module_Add_Subt_result[46]), .B(
add_subt_module_Add_Subt_result[44]), .C(
add_subt_module_Add_Subt_result[45]), .D(n4637), .Y(n4612) );
CLKBUFX3TS U3411 ( .A(n3276), .Y(n5530) );
NOR4X2TS U3412 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .C(n5088), .D(n5010), .Y(
n4143) );
OAI21X2TS U3413 ( .A0(n5083), .A1(n4814), .B0(n4768), .Y(n4787) );
AOI21X2TS U3414 ( .A0(n4873), .A1(n5103), .B0(n4806), .Y(n4830) );
INVX2TS U3415 ( .A(n2957), .Y(n3005) );
AOI222X4TS U3416 ( .A0(n4797), .A1(n2960), .B0(n4802), .B1(n4831), .C0(n4807), .C1(n4811), .Y(n4818) );
OAI21X2TS U3417 ( .A0(n5087), .A1(n4864), .B0(n4796), .Y(n4807) );
AOI21X2TS U3418 ( .A0(n4873), .A1(n5131), .B0(n4872), .Y(n4895) );
CLKBUFX3TS U3419 ( .A(n4698), .Y(n4873) );
INVX2TS U3420 ( .A(n2965), .Y(n3006) );
OAI21X2TS U3421 ( .A0(n5150), .A1(n4823), .B0(n3964), .Y(n3994) );
OAI21X2TS U3422 ( .A0(n5133), .A1(n4814), .B0(n4813), .Y(n4837) );
INVX2TS U3423 ( .A(n2960), .Y(n3007) );
OAI21X2TS U3424 ( .A0(n5136), .A1(n4879), .B0(n4822), .Y(n4843) );
BUFX6TS U3425 ( .A(n5362), .Y(n5341) );
BUFX6TS U3426 ( .A(n5448), .Y(n5442) );
BUFX4TS U3427 ( .A(n3272), .Y(n5448) );
BUFX6TS U3428 ( .A(n5332), .Y(n5449) );
BUFX4TS U3429 ( .A(n3264), .Y(n5447) );
BUFX6TS U3430 ( .A(n5390), .Y(n5389) );
BUFX4TS U3431 ( .A(n3274), .Y(n5390) );
BUFX6TS U3432 ( .A(n5330), .Y(n5381) );
BUFX6TS U3433 ( .A(n5329), .Y(n5378) );
BUFX6TS U3434 ( .A(n5332), .Y(n5419) );
BUFX4TS U3435 ( .A(n3264), .Y(n5420) );
BUFX6TS U3436 ( .A(n5414), .Y(n5417) );
BUFX4TS U3437 ( .A(n3274), .Y(n5414) );
BUFX6TS U3438 ( .A(n5350), .Y(n5352) );
BUFX4TS U3439 ( .A(n3270), .Y(n5350) );
BUFX6TS U3440 ( .A(n5330), .Y(n5353) );
BUFX4TS U3441 ( .A(n3255), .Y(n5349) );
BUFX6TS U3442 ( .A(n5399), .Y(n5406) );
BUFX4TS U3443 ( .A(n5332), .Y(n5399) );
BUFX6TS U3444 ( .A(n5380), .Y(n5376) );
BUFX4TS U3445 ( .A(n3270), .Y(n5380) );
BUFX6TS U3446 ( .A(n5418), .Y(n5413) );
BUFX4TS U3447 ( .A(n3267), .Y(n5418) );
BUFX6TS U3448 ( .A(n5400), .Y(n5392) );
BUFX4TS U3449 ( .A(n5397), .Y(n5400) );
INVX2TS U3450 ( .A(n3259), .Y(n3008) );
CLKINVX6TS U3451 ( .A(n3008), .Y(n3009) );
BUFX6TS U3452 ( .A(n3272), .Y(n5359) );
BUFX6TS U3453 ( .A(n3264), .Y(n5336) );
BUFX6TS U3454 ( .A(n3274), .Y(n5338) );
BUFX6TS U3455 ( .A(n3267), .Y(n5337) );
BUFX6TS U3456 ( .A(n3258), .Y(n5339) );
BUFX6TS U3457 ( .A(n5453), .Y(n5334) );
BUFX6TS U3458 ( .A(n3270), .Y(n5340) );
BUFX4TS U3459 ( .A(n5453), .Y(n5360) );
BUFX4TS U3460 ( .A(n3258), .Y(n5348) );
BUFX4TS U3461 ( .A(n3264), .Y(n5440) );
CLKINVX6TS U3462 ( .A(n3008), .Y(n3010) );
BUFX4TS U3463 ( .A(n3272), .Y(n3269) );
BUFX4TS U3464 ( .A(n3267), .Y(n3271) );
BUFX4TS U3465 ( .A(n3274), .Y(n5367) );
BUFX6TS U3466 ( .A(n5446), .Y(n5445) );
BUFX6TS U3467 ( .A(n3258), .Y(n5446) );
BUFX4TS U3468 ( .A(n3267), .Y(n5342) );
BUFX4TS U3469 ( .A(n3274), .Y(n5345) );
BUFX6TS U3470 ( .A(n5453), .Y(n3266) );
BUFX4TS U3471 ( .A(n5453), .Y(n3262) );
BUFX4TS U3472 ( .A(n3258), .Y(n3256) );
BUFX4TS U3473 ( .A(n3267), .Y(n5396) );
BUFX6TS U3474 ( .A(n5371), .Y(n5366) );
BUFX6TS U3475 ( .A(n5371), .Y(n5363) );
BUFX6TS U3476 ( .A(n5371), .Y(n5372) );
BUFX6TS U3477 ( .A(n5371), .Y(n5364) );
BUFX6TS U3478 ( .A(n5371), .Y(n5365) );
BUFX6TS U3479 ( .A(n5398), .Y(n5405) );
BUFX6TS U3480 ( .A(n5330), .Y(n5398) );
BUFX6TS U3481 ( .A(n5330), .Y(n5401) );
BUFX6TS U3482 ( .A(n5330), .Y(n3257) );
BUFX4TS U3483 ( .A(n5373), .Y(n5391) );
BUFX4TS U3484 ( .A(n5403), .Y(n5404) );
BUFX6TS U3485 ( .A(n5343), .Y(n5354) );
BUFX6TS U3486 ( .A(n3270), .Y(n5343) );
BUFX6TS U3487 ( .A(n3268), .Y(n5356) );
BUFX4TS U3488 ( .A(n3272), .Y(n5355) );
BUFX6TS U3489 ( .A(n3255), .Y(n3261) );
BUFX4TS U3490 ( .A(n3268), .Y(n5347) );
BUFX6TS U3491 ( .A(n5330), .Y(n5386) );
BUFX6TS U3492 ( .A(n5330), .Y(n5395) );
BUFX6TS U3493 ( .A(n5330), .Y(n5402) );
BUFX6TS U3494 ( .A(n5330), .Y(n5393) );
BUFX6TS U3495 ( .A(n5330), .Y(n5387) );
BUFX4TS U3496 ( .A(n5453), .Y(n5427) );
BUFX4TS U3497 ( .A(n3258), .Y(n3260) );
BUFX6TS U3498 ( .A(n5329), .Y(n5422) );
BUFX6TS U3499 ( .A(n5411), .Y(n5433) );
BUFX6TS U3500 ( .A(n5329), .Y(n5425) );
BUFX6TS U3501 ( .A(n5410), .Y(n5432) );
BUFX6TS U3502 ( .A(n5329), .Y(n5424) );
BUFX4TS U3503 ( .A(n5329), .Y(n5423) );
BUFX4TS U3504 ( .A(n5329), .Y(n3263) );
BUFX6TS U3505 ( .A(n3255), .Y(n5327) );
BUFX6TS U3506 ( .A(n3268), .Y(n5326) );
INVX2TS U3507 ( .A(n2966), .Y(n3011) );
INVX2TS U3508 ( .A(n2966), .Y(n3012) );
INVX2TS U3509 ( .A(n2966), .Y(n3013) );
INVX2TS U3510 ( .A(n2964), .Y(n3014) );
INVX2TS U3511 ( .A(n3080), .Y(n3015) );
NOR2X4TS U3512 ( .A(n5056), .B(n2958), .Y(n4366) );
CLKBUFX3TS U3513 ( .A(n4540), .Y(n4591) );
AOI222X1TS U3514 ( .A0(n4196), .A1(add_subt_module_intDY[63]), .B0(n4054),
.B1(d_ff3_sh_x_out[63]), .C0(n4343), .C1(d_ff3_sh_y_out[63]), .Y(n3610) );
NOR2X2TS U3515 ( .A(n4250), .B(n4249), .Y(n4255) );
NAND2X2TS U3516 ( .A(cordic_FSM_state_reg[2]), .B(n5024), .Y(n4250) );
CLKBUFX3TS U3517 ( .A(n3506), .Y(n3622) );
CLKBUFX2TS U3518 ( .A(n3388), .Y(n3016) );
CLKBUFX3TS U3519 ( .A(n3440), .Y(n3586) );
NOR2X2TS U3520 ( .A(sel_mux_3_reg), .B(n3895), .Y(n3440) );
AOI222X4TS U3521 ( .A0(n4248), .A1(d_ff2_Z[52]), .B0(n3855), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n3851), .Y(n3737) );
AOI222X4TS U3522 ( .A0(n3848), .A1(d_ff2_Z[63]), .B0(n3855), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n4312), .Y(n3778) );
AOI222X4TS U3523 ( .A0(n4248), .A1(d_ff2_Z[58]), .B0(n3855), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n3846), .Y(n3847) );
AOI222X1TS U3524 ( .A0(n3852), .A1(d_ff2_Z[60]), .B0(n3855), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n3836), .Y(n3850) );
AOI222X1TS U3525 ( .A0(n3848), .A1(d_ff2_Z[61]), .B0(n3855), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n3851), .Y(n3853) );
AOI222X1TS U3526 ( .A0(n3003), .A1(d_ff2_Z[62]), .B0(n3855), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n4312), .Y(n3856) );
AOI211X1TS U3527 ( .A0(n4280), .A1(add_subt_module_Add_Subt_result[33]),
.B0(n4279), .C0(n4278), .Y(n4285) );
NOR4X4TS U3528 ( .A(add_subt_module_Add_Subt_result[36]), .B(
add_subt_module_Add_Subt_result[34]), .C(
add_subt_module_Add_Subt_result[35]), .D(n4265), .Y(n4280) );
AOI21X2TS U3529 ( .A0(n3076), .A1(n4767), .B0(n3584), .Y(n3480) );
CLKINVX3TS U3530 ( .A(n4871), .Y(n4767) );
OAI21X2TS U3531 ( .A0(n4199), .A1(n4952), .B0(n4932), .Y(n4938) );
CLKINVX3TS U3532 ( .A(n4508), .Y(n4932) );
NOR2X2TS U3533 ( .A(n3391), .B(n3930), .Y(n4923) );
AOI21X2TS U3534 ( .A0(add_subt_module_intDX[23]), .A1(n5130), .B0(n3173),
.Y(n3193) );
CLKINVX3TS U3535 ( .A(n3320), .Y(n3549) );
AOI22X2TS U3536 ( .A0(add_subt_module_intDX[5]), .A1(n5033), .B0(
add_subt_module_intDX[6]), .B1(n5071), .Y(n3385) );
NOR2X2TS U3537 ( .A(n3206), .B(n3201), .Y(n3372) );
OAI211X2TS U3538 ( .A0(add_subt_module_intDY[12]), .A1(n5031), .B0(n3189),
.C0(n3176), .Y(n3347) );
NOR4BX4TS U3539 ( .AN(n4208), .B(add_subt_module_Add_Subt_result[8]), .C(
add_subt_module_Add_Subt_result[10]), .D(n4645), .Y(n4629) );
AOI21X2TS U3540 ( .A0(add_subt_module_intDX[11]), .A1(n5129), .B0(n3183),
.Y(n3340) );
CLKINVX3TS U3541 ( .A(n4671), .Y(n3607) );
CLKBUFX3TS U3542 ( .A(n4027), .Y(n4164) );
CLKBUFX3TS U3543 ( .A(n4293), .Y(n4318) );
CLKINVX3TS U3544 ( .A(n4850), .Y(n4761) );
OAI22X2TS U3545 ( .A0(add_subt_module_Add_Subt_result[0]), .A1(n4880), .B0(
add_subt_module_Add_Subt_result[54]), .B1(n4879), .Y(n3630) );
CLKINVX3TS U3546 ( .A(n4702), .Y(n4880) );
OAI22X2TS U3547 ( .A0(add_subt_module_intDX[48]), .A1(n5029), .B0(
add_subt_module_intDX[49]), .B1(n5112), .Y(n3363) );
CLKBUFX3TS U3548 ( .A(n3883), .Y(n3871) );
CLKBUFX3TS U3549 ( .A(n3883), .Y(n3910) );
CLKINVX3TS U3550 ( .A(n3790), .Y(n4992) );
CLKBUFX3TS U3551 ( .A(n3729), .Y(n3790) );
INVX2TS U3552 ( .A(n4983), .Y(n3017) );
AOI222X1TS U3553 ( .A0(n3843), .A1(d_ff2_Z[56]), .B0(n3842), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n3836), .Y(n3844) );
AOI222X1TS U3554 ( .A0(n3843), .A1(d_ff2_Z[25]), .B0(n3821), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n4310), .Y(n3819) );
AOI222X1TS U3555 ( .A0(n3843), .A1(d_ff2_Z[30]), .B0(n3764), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n3763), .Y(n3765) );
AOI222X1TS U3556 ( .A0(n3843), .A1(d_ff2_Z[34]), .B0(n3764), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n3763), .Y(n3761) );
AOI222X1TS U3557 ( .A0(n3843), .A1(d_ff2_Z[28]), .B0(n3821), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n4321), .Y(n3646) );
AOI222X1TS U3558 ( .A0(n3843), .A1(d_ff2_Z[24]), .B0(n3821), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n4312), .Y(n3644) );
AOI222X1TS U3559 ( .A0(n3843), .A1(d_ff2_Z[33]), .B0(n3764), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n4310), .Y(n3641) );
AOI222X1TS U3560 ( .A0(n3843), .A1(d_ff2_Z[31]), .B0(n3764), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n3763), .Y(n3639) );
CLKBUFX3TS U3561 ( .A(n4262), .Y(n4983) );
NOR3X2TS U3562 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(n4021), .Y(n4187) );
NOR3X2TS U3563 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(n4382), .Y(n4494) );
AOI211X2TS U3564 ( .A0(n4366), .A1(n4949), .B0(n4934), .C0(n4410), .Y(n4957)
);
CLKINVX3TS U3565 ( .A(n4551), .Y(n4535) );
CLKBUFX3TS U3566 ( .A(n5202), .Y(n4551) );
CLKBUFX3TS U3567 ( .A(n3900), .Y(n3784) );
NAND2X2TS U3568 ( .A(cordic_FSM_state_reg[0]), .B(n2982), .Y(n4154) );
CLKBUFX3TS U3569 ( .A(n4368), .Y(n4459) );
AOI31X4TS U3570 ( .A0(n4340), .A1(n4480), .A2(n4426), .B0(n4487), .Y(n4479)
);
NAND3X2TS U3571 ( .A(cont_iter_out[1]), .B(n4961), .C(n2958), .Y(n4340) );
CLKBUFX3TS U3572 ( .A(n4421), .Y(n4437) );
AOI21X2TS U3573 ( .A0(n4951), .A1(n5023), .B0(n4487), .Y(n4506) );
CLKBUFX3TS U3574 ( .A(n4009), .Y(n4008) );
NOR2BX2TS U3575 ( .AN(n4257), .B(n4256), .Y(n4009) );
CLKBUFX2TS U3576 ( .A(n4973), .Y(n3018) );
CLKBUFX3TS U3577 ( .A(n4191), .Y(n4251) );
CLKBUFX3TS U3578 ( .A(n4263), .Y(n4100) );
NOR4X2TS U3579 ( .A(add_subt_module_Add_Subt_result[48]), .B(
add_subt_module_Add_Subt_result[50]), .C(
add_subt_module_Add_Subt_result[49]), .D(n4648), .Y(n4218) );
CLKBUFX3TS U3580 ( .A(n3278), .Y(n5325) );
BUFX3TS U3581 ( .A(n5532), .Y(n5531) );
CLKBUFX3TS U3582 ( .A(n4239), .Y(n4235) );
CLKBUFX3TS U3583 ( .A(n4234), .Y(n4239) );
AOI21X2TS U3584 ( .A0(n4849), .A1(n5080), .B0(n4848), .Y(n4869) );
AOI21X2TS U3585 ( .A0(n4873), .A1(n5109), .B0(n3970), .Y(n4899) );
AOI222X4TS U3586 ( .A0(n4800), .A1(n2960), .B0(n4807), .B1(n4831), .C0(n4817), .C1(n4811), .Y(n4829) );
OAI21X2TS U3587 ( .A0(n5083), .A1(n4864), .B0(n4799), .Y(n4817) );
AOI211X1TS U3588 ( .A0(n4811), .A1(n4792), .B0(n4780), .C0(n4779), .Y(n4798)
);
OAI21X2TS U3589 ( .A0(n5087), .A1(n4814), .B0(n4775), .Y(n4792) );
AOI22X2TS U3590 ( .A0(add_subt_module_LZA_output[4]), .A1(n2983), .B0(n2991),
.B1(add_subt_module_exp_oper_result[4]), .Y(n3082) );
CLKAND2X2TS U3591 ( .A(n3699), .B(n3569), .Y(n3707) );
INVX2TS U3592 ( .A(n3707), .Y(n3019) );
INVX2TS U3593 ( .A(n3707), .Y(n3020) );
INVX2TS U3594 ( .A(n3707), .Y(n3021) );
AOI21X2TS U3595 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(
n3560), .Y(n3708) );
AOI21X2TS U3596 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(
n3560), .Y(n3619) );
AOI21X2TS U3597 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n3560), .Y(n3616) );
AOI21X2TS U3598 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3560), .Y(n3613) );
AOI21X2TS U3599 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n3560), .Y(n3609) );
AOI21X2TS U3600 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(
n3560), .Y(n3605) );
NOR2X4TS U3601 ( .A(n3505), .B(n3087), .Y(n3560) );
CLKAND2X2TS U3602 ( .A(n3566), .B(n3285), .Y(n3782) );
INVX2TS U3603 ( .A(n3782), .Y(n3022) );
INVX2TS U3604 ( .A(n3782), .Y(n3023) );
INVX2TS U3605 ( .A(n3782), .Y(n3024) );
NOR2X2TS U3606 ( .A(n3699), .B(n3087), .Y(n3285) );
AOI211X4TS U3607 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3558), .C0(n3078), .Y(n3625) );
AOI211X4TS U3608 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n3558), .C0(n3091), .Y(n3554) );
AOI211X4TS U3609 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(
n3558), .C0(n3483), .Y(n3573) );
AOI211X4TS U3610 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3558), .C0(n3487), .Y(n3576) );
AOI211X4TS U3611 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(
n3558), .C0(n3491), .Y(n3579) );
AOI211X2TS U3612 ( .A0(n3505), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(
n3558), .C0(n3495), .Y(n3582) );
NOR2X4TS U3613 ( .A(n3015), .B(n3515), .Y(n3558) );
NOR3XLTS U3614 ( .A(n4920), .B(n4919), .C(n4918), .Y(n4921) );
BUFX4TS U3615 ( .A(n3259), .Y(n5452) );
BUFX6TS U3616 ( .A(clk), .Y(n5453) );
CLKBUFX2TS U3617 ( .A(add_subt_module_FSM_exp_operation_A_S), .Y(n3025) );
OAI22X2TS U3618 ( .A0(n4500), .A1(n5010), .B0(n3124), .B1(n4821), .Y(n3122)
);
INVX2TS U3619 ( .A(n5057), .Y(n3026) );
OAI211X1TS U3620 ( .A0(n3026), .A1(n4426), .B0(n4940), .C0(n4954), .Y(n4960)
);
NOR3X2TS U3621 ( .A(cont_iter_out[2]), .B(cont_iter_out[0]), .C(n4931), .Y(
n4410) );
INVX2TS U3622 ( .A(n4438), .Y(n3027) );
NOR3X6TS U3623 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .C(n4498), .Y(n4198) );
CLKBUFX3TS U3624 ( .A(n4013), .Y(n4438) );
NOR2XLTS U3625 ( .A(add_subt_module_intDX[1]), .B(n5086), .Y(n3177) );
NOR2XLTS U3626 ( .A(add_subt_module_intDY[3]), .B(n5027), .Y(n3179) );
OAI211XLTS U3627 ( .A0(add_subt_module_intDY[13]), .A1(n5147), .B0(
add_subt_module_intDY[12]), .C0(n5031), .Y(n3192) );
OAI211XLTS U3628 ( .A0(n3197), .A1(n3196), .B0(n3389), .C0(n3342), .Y(n3198)
);
OAI21XLTS U3629 ( .A0(n3355), .A1(n3161), .B0(n3354), .Y(n3134) );
NOR2XLTS U3630 ( .A(add_subt_module_Add_Subt_result[46]), .B(
add_subt_module_Add_Subt_result[45]), .Y(n4607) );
OAI21XLTS U3631 ( .A0(add_subt_module_Add_Subt_result[13]), .A1(
add_subt_module_Add_Subt_result[11]), .B0(n4620), .Y(n4220) );
OAI211XLTS U3632 ( .A0(add_subt_module_intDY[32]), .A1(n5066), .B0(n3163),
.C0(n3162), .Y(n3164) );
NOR2XLTS U3633 ( .A(n4593), .B(n5185), .Y(n4574) );
NOR2XLTS U3634 ( .A(n4306), .B(n5155), .Y(n4521) );
NOR2XLTS U3635 ( .A(n4575), .B(n5200), .Y(n4534) );
NOR2XLTS U3636 ( .A(n4547), .B(n5197), .Y(n4538) );
NOR2XLTS U3637 ( .A(n4535), .B(n5162), .Y(n4559) );
OAI21XLTS U3638 ( .A0(add_subt_module_Add_Subt_result[42]), .A1(
add_subt_module_Add_Subt_result[40]), .B0(n4630), .Y(n4633) );
OAI21XLTS U3639 ( .A0(n4861), .A1(n4875), .B0(n4860), .Y(n4862) );
OAI21XLTS U3640 ( .A0(n4903), .A1(n3996), .B0(n3982), .Y(n3983) );
NOR2XLTS U3641 ( .A(n4681), .B(n4756), .Y(n3632) );
OAI21XLTS U3642 ( .A0(d_ff3_LUT_out[26]), .A1(n4476), .B0(n4931), .Y(n4341)
);
NOR2XLTS U3643 ( .A(n4940), .B(d_ff3_LUT_out[19]), .Y(n4941) );
OAI21XLTS U3644 ( .A0(n4479), .A1(n4359), .B0(n4358), .Y(n4360) );
OAI21XLTS U3645 ( .A0(n4397), .A1(n5046), .B0(n4393), .Y(n4028) );
NOR2XLTS U3646 ( .A(add_subt_module_sign_final_result), .B(underflow_flag),
.Y(n3071) );
OR2X1TS U3647 ( .A(d_ff2_X[56]), .B(n4382), .Y(n4441) );
AOI211XLTS U3648 ( .A0(n5057), .A1(n4924), .B0(n3905), .C0(n4925), .Y(n2923)
);
OAI21XLTS U3649 ( .A0(n2977), .A1(n3019), .B0(n3701), .Y(n2535) );
OAI21XLTS U3650 ( .A0(n3708), .A1(n3020), .B0(n3706), .Y(n2536) );
OAI21XLTS U3651 ( .A0(n5134), .A1(n3814), .B0(n3681), .Y(n1871) );
OAI21XLTS U3652 ( .A0(n5117), .A1(n3802), .B0(n3671), .Y(n1802) );
OAI21XLTS U3653 ( .A0(n5035), .A1(n3802), .B0(n3656), .Y(n1807) );
OAI21XLTS U3654 ( .A0(n5126), .A1(n3907), .B0(n3731), .Y(n1724) );
OAI21XLTS U3655 ( .A0(n5022), .A1(n3726), .B0(n3721), .Y(n1732) );
OAI21XLTS U3656 ( .A0(n5146), .A1(n3810), .B0(n3693), .Y(n1834) );
OAI21XLTS U3657 ( .A0(n5059), .A1(n3871), .B0(n3870), .Y(n1934) );
OAI21XLTS U3658 ( .A0(n5033), .A1(n3910), .B0(n3877), .Y(n1713) );
OAI21XLTS U3659 ( .A0(n5066), .A1(n3790), .B0(n3789), .Y(n1747) );
OAI21XLTS U3660 ( .A0(n5030), .A1(n3871), .B0(n3815), .Y(n1889) );
AOI31XLTS U3661 ( .A0(n4579), .A1(n4358), .A2(n4506), .B0(n3858), .Y(n2849)
);
OAI21XLTS U3662 ( .A0(n5262), .A1(n3467), .B0(n3887), .Y(n1987) );
OAI21XLTS U3663 ( .A0(n5223), .A1(n3420), .B0(n3407), .Y(n2067) );
OAI21XLTS U3664 ( .A0(n5243), .A1(n3445), .B0(n3426), .Y(n2025) );
OAI21XLTS U3665 ( .A0(n5256), .A1(n3457), .B0(n3450), .Y(n1999) );
OAI21XLTS U3666 ( .A0(n5268), .A1(n3465), .B0(n3470), .Y(n1967) );
OAI211XLTS U3667 ( .A0(n3027), .A1(n5036), .B0(n3037), .C0(n3089), .Y(n1954)
);
OAI211XLTS U3668 ( .A0(n3619), .A1(n3011), .B0(n3618), .C0(n3022), .Y(n2587)
);
OAI211XLTS U3669 ( .A0(n3000), .A1(n3011), .B0(n3590), .C0(n3023), .Y(n2575)
);
OAI21XLTS U3670 ( .A0(n3576), .A1(n3021), .B0(n3544), .Y(n2553) );
NOR2X2TS U3671 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[3]),
.Y(n3955) );
NAND2X1TS U3672 ( .A(n3955), .B(n3932), .Y(n3275) );
CLKBUFX3TS U3673 ( .A(n3275), .Y(n5532) );
CLKBUFX2TS U3674 ( .A(n5495), .Y(n3280) );
CLKBUFX2TS U3675 ( .A(n3280), .Y(n3224) );
BUFX3TS U3676 ( .A(n3224), .Y(n5523) );
BUFX3TS U3677 ( .A(n3224), .Y(n5527) );
CLKBUFX2TS U3678 ( .A(n5532), .Y(n3276) );
BUFX3TS U3679 ( .A(n5492), .Y(n5458) );
BUFX3TS U3680 ( .A(n3224), .Y(n5521) );
BUFX3TS U3681 ( .A(n3224), .Y(n5516) );
BUFX3TS U3682 ( .A(n3033), .Y(n5314) );
BUFX3TS U3683 ( .A(n3030), .Y(n5318) );
BUFX3TS U3684 ( .A(n3028), .Y(n5319) );
BUFX3TS U3685 ( .A(n5286), .Y(n5320) );
BUFX3TS U3686 ( .A(n3032), .Y(n5323) );
BUFX3TS U3687 ( .A(n3033), .Y(n5324) );
BUFX3TS U3688 ( .A(n3028), .Y(n5281) );
CLKBUFX3TS U3689 ( .A(n3278), .Y(n3033) );
BUFX3TS U3690 ( .A(n3033), .Y(n5280) );
BUFX3TS U3691 ( .A(n5290), .Y(n5279) );
BUFX3TS U3692 ( .A(n5290), .Y(n5278) );
CLKBUFX2TS U3693 ( .A(n5532), .Y(n3034) );
BUFX3TS U3694 ( .A(n5495), .Y(n5496) );
BUFX3TS U3695 ( .A(n5492), .Y(n5488) );
BUFX3TS U3696 ( .A(n3276), .Y(n5490) );
BUFX3TS U3697 ( .A(n3224), .Y(n5515) );
BUFX3TS U3698 ( .A(n3224), .Y(n5517) );
BUFX3TS U3699 ( .A(n5492), .Y(n5528) );
BUFX3TS U3700 ( .A(n3033), .Y(n5309) );
BUFX3TS U3701 ( .A(n3030), .Y(n5315) );
BUFX3TS U3702 ( .A(n3033), .Y(n5317) );
BUFX3TS U3703 ( .A(n5287), .Y(n5311) );
BUFX3TS U3704 ( .A(n5287), .Y(n5312) );
BUFX3TS U3705 ( .A(n5325), .Y(n5285) );
BUFX3TS U3706 ( .A(n3028), .Y(n5313) );
BUFX3TS U3707 ( .A(n3028), .Y(n5306) );
BUFX3TS U3708 ( .A(n3031), .Y(n5489) );
BUFX3TS U3709 ( .A(n5530), .Y(n5486) );
BUFX3TS U3710 ( .A(n5292), .Y(n5291) );
BUFX3TS U3711 ( .A(n5325), .Y(n5282) );
BUFX3TS U3712 ( .A(n3032), .Y(n5283) );
BUFX3TS U3713 ( .A(n5530), .Y(n5485) );
BUFX3TS U3714 ( .A(n3276), .Y(n5466) );
BUFX3TS U3715 ( .A(n3033), .Y(n5316) );
BUFX3TS U3716 ( .A(n5531), .Y(n5491) );
BUFX3TS U3717 ( .A(n3031), .Y(n5461) );
BUFX3TS U3718 ( .A(n5286), .Y(n5288) );
BUFX3TS U3719 ( .A(n5292), .Y(n5308) );
BUFX3TS U3720 ( .A(n5531), .Y(n5468) );
CLKBUFX2TS U3721 ( .A(n5492), .Y(n3282) );
CLKBUFX2TS U3722 ( .A(n3282), .Y(n3029) );
BUFX3TS U3723 ( .A(n3029), .Y(n5506) );
BUFX3TS U3724 ( .A(n5530), .Y(n5482) );
BUFX3TS U3725 ( .A(n5287), .Y(n5322) );
BUFX3TS U3726 ( .A(n5530), .Y(n5487) );
BUFX3TS U3727 ( .A(n3276), .Y(n5477) );
BUFX3TS U3728 ( .A(n3031), .Y(n5484) );
BUFX3TS U3729 ( .A(n3031), .Y(n5474) );
BUFX3TS U3730 ( .A(n3029), .Y(n5512) );
BUFX3TS U3731 ( .A(n5287), .Y(n5284) );
BUFX3TS U3732 ( .A(n3030), .Y(n5297) );
BUFX3TS U3733 ( .A(n5530), .Y(n5483) );
BUFX3TS U3734 ( .A(n5495), .Y(n5494) );
BUFX3TS U3735 ( .A(n5287), .Y(n5296) );
BUFX3TS U3736 ( .A(n5286), .Y(n5298) );
BUFX3TS U3737 ( .A(n3029), .Y(n5509) );
BUFX3TS U3738 ( .A(n5290), .Y(n5295) );
BUFX3TS U3739 ( .A(n3030), .Y(n5277) );
BUFX3TS U3740 ( .A(n3030), .Y(n5300) );
BUFX3TS U3741 ( .A(n3029), .Y(n5513) );
BUFX3TS U3742 ( .A(n5531), .Y(n5472) );
BUFX3TS U3743 ( .A(n5292), .Y(n5302) );
BUFX3TS U3744 ( .A(n3032), .Y(n5289) );
BUFX3TS U3745 ( .A(n5290), .Y(n5321) );
BUFX3TS U3746 ( .A(n3032), .Y(n5303) );
BUFX3TS U3747 ( .A(n5286), .Y(n5293) );
BUFX3TS U3748 ( .A(n5292), .Y(n5276) );
BUFX3TS U3749 ( .A(n3029), .Y(n5510) );
BUFX3TS U3750 ( .A(n5325), .Y(n5275) );
BUFX3TS U3751 ( .A(n5286), .Y(n5299) );
BUFX3TS U3752 ( .A(n3029), .Y(n5508) );
BUFX3TS U3753 ( .A(n5325), .Y(n5310) );
BUFX3TS U3754 ( .A(n5495), .Y(n5475) );
BUFX3TS U3755 ( .A(n3032), .Y(n5307) );
BUFX3TS U3756 ( .A(n3030), .Y(n5294) );
BUFX3TS U3757 ( .A(n5495), .Y(n5481) );
BUFX3TS U3758 ( .A(n5325), .Y(n5304) );
BUFX3TS U3759 ( .A(n3032), .Y(n5301) );
BUFX3TS U3760 ( .A(n5292), .Y(n5274) );
BUFX3TS U3761 ( .A(n5325), .Y(n5305) );
BUFX3TS U3762 ( .A(n5492), .Y(n5493) );
INVX2TS U3763 ( .A(n4198), .Y(n3240) );
CLKBUFX3TS U3764 ( .A(n3240), .Y(n4461) );
NOR3BXLTS U3765 ( .AN(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .C(n4461),
.Y(n3035) );
CLKBUFX2TS U3766 ( .A(n3035), .Y(n4003) );
CLKBUFX3TS U3767 ( .A(n4193), .Y(n4421) );
NOR3XLTS U3768 ( .A(sel_mux_2_reg[1]), .B(sel_mux_2_reg[0]), .C(n4461), .Y(
n3036) );
CLKBUFX2TS U3769 ( .A(n3036), .Y(n4169) );
AOI22X1TS U3770 ( .A0(d_ff3_sh_x_out[59]), .A1(n4437), .B0(
d_ff3_sh_y_out[59]), .B1(n4330), .Y(n3037) );
CLKBUFX2TS U3771 ( .A(n3240), .Y(n4196) );
NOR3BX1TS U3772 ( .AN(sel_mux_2_reg[1]), .B(sel_mux_2_reg[0]), .C(n4196),
.Y(n3040) );
CLKBUFX2TS U3773 ( .A(n3040), .Y(n3249) );
CLKBUFX3TS U3774 ( .A(n3249), .Y(n4466) );
NAND2X2TS U3775 ( .A(n4466), .B(d_ff3_LUT_out[48]), .Y(n3089) );
CLKBUFX3TS U3776 ( .A(n4369), .Y(n4465) );
CLKBUFX3TS U3777 ( .A(n4169), .Y(n4406) );
CLKBUFX3TS U3778 ( .A(n4406), .Y(n4453) );
AOI22X1TS U3779 ( .A0(n4465), .A1(d_ff2_Y[10]), .B0(n4453), .B1(d_ff2_X[10]),
.Y(n3039) );
CLKBUFX3TS U3780 ( .A(n4403), .Y(n4407) );
CLKBUFX3TS U3781 ( .A(n4407), .Y(n4455) );
CLKBUFX3TS U3782 ( .A(n3249), .Y(n4379) );
AOI22X1TS U3783 ( .A0(add_subt_module_intDX[10]), .A1(n4455), .B0(n4379),
.B1(d_ff2_Z[10]), .Y(n3038) );
NAND2X1TS U3784 ( .A(n3039), .B(n3038), .Y(n1847) );
CLKBUFX2TS U3785 ( .A(n3040), .Y(n3977) );
CLKBUFX3TS U3786 ( .A(n3977), .Y(n4412) );
CLKBUFX3TS U3787 ( .A(n4169), .Y(n4343) );
CLKBUFX3TS U3788 ( .A(n4459), .Y(n4464) );
AOI22X1TS U3789 ( .A0(n4412), .A1(d_ff2_Z[19]), .B0(n4464), .B1(d_ff2_X[19]),
.Y(n3042) );
CLKBUFX3TS U3790 ( .A(n4196), .Y(n4013) );
AOI22X1TS U3791 ( .A0(add_subt_module_intDX[19]), .A1(n3240), .B0(n4437),
.B1(d_ff2_Y[19]), .Y(n3041) );
NAND2X1TS U3792 ( .A(n3042), .B(n3041), .Y(n1804) );
AOI22X1TS U3793 ( .A0(add_subt_module_intDX[22]), .A1(n4438), .B0(n4459),
.B1(d_ff2_X[22]), .Y(n3044) );
CLKBUFX3TS U3794 ( .A(n3977), .Y(n4430) );
CLKBUFX3TS U3795 ( .A(n4369), .Y(n4431) );
AOI22X1TS U3796 ( .A0(n4430), .A1(d_ff2_Z[22]), .B0(n4431), .B1(d_ff2_Y[22]),
.Y(n3043) );
NAND2X1TS U3797 ( .A(n3044), .B(n3043), .Y(n1742) );
CLKBUFX2TS U3798 ( .A(n4166), .Y(n4181) );
CLKBUFX2TS U3799 ( .A(n4181), .Y(n4027) );
INVX2TS U3800 ( .A(n4164), .Y(n4010) );
NAND2X1TS U3801 ( .A(d_ff1_operation_out), .B(d_ff1_shift_region_flag_out[0]), .Y(n3774) );
OAI221XLTS U3802 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_shift_region_flag_out[0]), .B0(n5209), .B1(d_ff1_operation_out),
.C0(n3774), .Y(n3045) );
XNOR2X1TS U3803 ( .A(data_output2_63_), .B(n3045), .Y(n3046) );
AO22XLTS U3804 ( .A0(n4010), .A1(n3046), .B0(n4164), .B1(data_output[63]),
.Y(n1961) );
AOI22X1TS U3805 ( .A0(add_subt_module_intDX[26]), .A1(n4013), .B0(n4330),
.B1(d_ff2_X[26]), .Y(n3048) );
AOI22X1TS U3806 ( .A0(n4430), .A1(d_ff2_Z[26]), .B0(n4437), .B1(d_ff2_Y[26]),
.Y(n3047) );
NAND2X1TS U3807 ( .A(n3048), .B(n3047), .Y(n1735) );
NOR2X2TS U3808 ( .A(cordic_FSM_state_reg[2]), .B(n5024), .Y(n3933) );
NOR2X1TS U3809 ( .A(n4154), .B(n4250), .Y(n3392) );
NOR2X2TS U3810 ( .A(n2958), .B(n5023), .Y(n4427) );
NAND3X2TS U3811 ( .A(cont_iter_out[1]), .B(cont_iter_out[0]), .C(n4427), .Y(
n4928) );
INVX2TS U3812 ( .A(n4928), .Y(n3857) );
INVX2TS U3813 ( .A(n3254), .Y(n3225) );
OAI22X1TS U3814 ( .A0(n3933), .A1(n3392), .B0(n3857), .B1(n3225), .Y(n3049)
);
AOI211X1TS U3815 ( .A0(cordic_FSM_state_reg[0]), .A1(ack_cordic), .B0(n2959),
.C0(n5060), .Y(n4150) );
NAND2X1TS U3816 ( .A(cordic_FSM_state_reg[3]), .B(n4150), .Y(n3957) );
NAND2X1TS U3817 ( .A(n3049), .B(n3957), .Y(n2940) );
AOI22X1TS U3818 ( .A0(d_ff3_sh_x_out[61]), .A1(n4437), .B0(
d_ff3_sh_y_out[61]), .B1(n4343), .Y(n3050) );
OAI211XLTS U3819 ( .A0(n4198), .A1(n5025), .B0(n3050), .C0(n3089), .Y(n1956)
);
CLKBUFX2TS U3820 ( .A(n4013), .Y(n4000) );
AOI22X1TS U3821 ( .A0(add_subt_module_intDX[55]), .A1(n4000), .B0(n4343),
.B1(d_ff2_X[55]), .Y(n3052) );
CLKBUFX3TS U3822 ( .A(n3249), .Y(n4384) );
AOI22X1TS U3823 ( .A0(n4384), .A1(d_ff2_Z[55]), .B0(n4458), .B1(d_ff2_Y[55]),
.Y(n3051) );
NAND2X1TS U3824 ( .A(n3052), .B(n3051), .Y(n1921) );
AOI22X1TS U3825 ( .A0(n4421), .A1(d_ff3_sh_x_out[48]), .B0(n4330), .B1(
d_ff3_sh_y_out[48]), .Y(n3053) );
OAI211XLTS U3826 ( .A0(n4198), .A1(n5029), .B0(n3053), .C0(n3089), .Y(n1900)
);
AOI22X1TS U3827 ( .A0(add_subt_module_intDX[47]), .A1(n4000), .B0(n4368),
.B1(d_ff2_X[47]), .Y(n3055) );
AOI22X1TS U3828 ( .A0(n4384), .A1(d_ff2_Z[47]), .B0(n4003), .B1(d_ff2_Y[47]),
.Y(n3054) );
NAND2X1TS U3829 ( .A(n3055), .B(n3054), .Y(n1891) );
CLKBUFX3TS U3830 ( .A(n4407), .Y(n4375) );
CLKBUFX3TS U3831 ( .A(n4330), .Y(n4372) );
AOI22X1TS U3832 ( .A0(add_subt_module_intDX[12]), .A1(n4375), .B0(n4372),
.B1(d_ff2_X[12]), .Y(n3057) );
CLKBUFX3TS U3833 ( .A(n3977), .Y(n4373) );
CLKBUFX3TS U3834 ( .A(n4003), .Y(n4374) );
AOI22X1TS U3835 ( .A0(n4373), .A1(d_ff2_Z[12]), .B0(n4331), .B1(d_ff2_Y[12]),
.Y(n3056) );
NAND2X1TS U3836 ( .A(n3057), .B(n3056), .Y(n1829) );
AOI22X1TS U3837 ( .A0(n4465), .A1(d_ff3_sh_x_out[7]), .B0(n4453), .B1(
d_ff3_sh_y_out[7]), .Y(n3059) );
AOI22X1TS U3838 ( .A0(add_subt_module_intDY[7]), .A1(n4375), .B0(
d_ff3_LUT_out[7]), .B1(n4466), .Y(n3058) );
NAND2X1TS U3839 ( .A(n3059), .B(n3058), .Y(n1839) );
AOI22X1TS U3840 ( .A0(n4465), .A1(d_ff3_sh_x_out[39]), .B0(n4464), .B1(
d_ff3_sh_y_out[39]), .Y(n3061) );
AOI22X1TS U3841 ( .A0(add_subt_module_intDY[39]), .A1(n4013), .B0(
d_ff3_LUT_out[39]), .B1(n4466), .Y(n3060) );
NAND2X1TS U3842 ( .A(n3061), .B(n3060), .Y(n1811) );
CLKBUFX3TS U3843 ( .A(n4000), .Y(n4432) );
CLKBUFX2TS U3844 ( .A(n4406), .Y(n4420) );
CLKBUFX3TS U3845 ( .A(n4420), .Y(n4436) );
AOI22X1TS U3846 ( .A0(add_subt_module_intDY[25]), .A1(n4432), .B0(n4436),
.B1(d_ff3_sh_y_out[25]), .Y(n3063) );
AOI22X1TS U3847 ( .A0(d_ff3_LUT_out[25]), .A1(n4379), .B0(n4431), .B1(
d_ff3_sh_x_out[25]), .Y(n3062) );
NAND2X1TS U3848 ( .A(n3063), .B(n3062), .Y(n1759) );
CLKBUFX3TS U3849 ( .A(n4343), .Y(n4443) );
AOI22X1TS U3850 ( .A0(n4193), .A1(d_ff3_sh_x_out[57]), .B0(n4443), .B1(
d_ff3_sh_y_out[57]), .Y(n3064) );
OAI211XLTS U3851 ( .A0(n4198), .A1(n5081), .B0(n3064), .C0(n3089), .Y(n1952)
);
CLKBUFX3TS U3852 ( .A(n4437), .Y(n4400) );
AOI22X1TS U3853 ( .A0(n4400), .A1(d_ff3_sh_x_out[51]), .B0(n4406), .B1(
d_ff3_sh_y_out[51]), .Y(n3065) );
OAI211XLTS U3854 ( .A0(n4198), .A1(n5082), .B0(n3065), .C0(n3089), .Y(n1906)
);
CLKBUFX3TS U3855 ( .A(n4000), .Y(n4332) );
CLKBUFX3TS U3856 ( .A(n4330), .Y(n4388) );
AOI22X1TS U3857 ( .A0(add_subt_module_intDY[1]), .A1(n4332), .B0(n4388),
.B1(d_ff3_sh_y_out[1]), .Y(n3067) );
CLKBUFX3TS U3858 ( .A(n3977), .Y(n4389) );
CLKBUFX3TS U3859 ( .A(n4003), .Y(n4331) );
AOI22X1TS U3860 ( .A0(n4389), .A1(d_ff3_LUT_out[1]), .B0(n4458), .B1(
d_ff3_sh_x_out[1]), .Y(n3066) );
NAND2X1TS U3861 ( .A(n3067), .B(n3066), .Y(n1883) );
AOI22X1TS U3862 ( .A0(n4458), .A1(d_ff3_sh_x_out[58]), .B0(n4443), .B1(
d_ff3_sh_y_out[58]), .Y(n3068) );
OAI211XLTS U3863 ( .A0(n4198), .A1(n5102), .B0(n3068), .C0(n3089), .Y(n1953)
);
AOI22X1TS U3864 ( .A0(add_subt_module_intDY[46]), .A1(n4332), .B0(n4388),
.B1(d_ff3_sh_y_out[46]), .Y(n3070) );
CLKBUFX3TS U3865 ( .A(n3977), .Y(n4471) );
AOI22X1TS U3866 ( .A0(n4471), .A1(d_ff3_LUT_out[46]), .B0(n4458), .B1(
d_ff3_sh_x_out[46]), .Y(n3069) );
NAND2X1TS U3867 ( .A(n3070), .B(n3069), .Y(n1876) );
INVX2TS U3868 ( .A(n3290), .Y(n4499) );
NOR3X6TS U3869 ( .A(n5088), .B(n5010), .C(n4499), .Y(n4973) );
INVX2TS U3870 ( .A(n4973), .Y(n4975) );
CLKBUFX3TS U3871 ( .A(n4975), .Y(n4969) );
OAI32X1TS U3872 ( .A0(n4969), .A1(overflow_flag), .A2(n3071), .B0(n4973),
.B1(n5049), .Y(n2933) );
AOI22X1TS U3873 ( .A0(n4465), .A1(d_ff3_sh_x_out[41]), .B0(n4464), .B1(
d_ff3_sh_y_out[41]), .Y(n3073) );
CLKBUFX3TS U3874 ( .A(n3249), .Y(n4422) );
AOI22X1TS U3875 ( .A0(add_subt_module_intDY[41]), .A1(n4013), .B0(n4422),
.B1(d_ff3_LUT_out[41]), .Y(n3072) );
NAND2X1TS U3876 ( .A(n3073), .B(n3072), .Y(n1815) );
AOI22X1TS U3877 ( .A0(d_ff3_sh_x_out[62]), .A1(n4421), .B0(
d_ff3_sh_y_out[62]), .B1(n4330), .Y(n3074) );
OAI21XLTS U3878 ( .A0(n4198), .A1(n5058), .B0(n3074), .Y(n1957) );
INVX2TS U3879 ( .A(n3082), .Y(n3077) );
CLKBUFX2TS U3880 ( .A(n3561), .Y(n3075) );
CLKBUFX3TS U3881 ( .A(n3075), .Y(n3505) );
CLKBUFX2TS U3882 ( .A(add_subt_module_FSM_selector_C), .Y(n4871) );
INVX2TS U3883 ( .A(n4671), .Y(n3781) );
INVX2TS U3884 ( .A(n3946), .Y(n4502) );
NAND2X1TS U3885 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(n4502), .Y(
n4500) );
NAND2X1TS U3886 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(n2969), .Y(
n3124) );
INVX2TS U3887 ( .A(n3087), .Y(n3633) );
NAND2X2TS U3888 ( .A(n3633), .B(n3077), .Y(n3515) );
AO22XLTS U3889 ( .A0(n3559), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n2990), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(
n3078) );
INVX2TS U3890 ( .A(n4871), .Y(n4842) );
CLKBUFX2TS U3891 ( .A(n3079), .Y(n4698) );
INVX2TS U3892 ( .A(n3100), .Y(n3699) );
INVX2TS U3893 ( .A(n4671), .Y(n3584) );
INVX2TS U3894 ( .A(n4702), .Y(n4814) );
AND2X2TS U3895 ( .A(n3075), .B(n3699), .Y(n3506) );
CLKBUFX3TS U3896 ( .A(n3506), .Y(n3562) );
INVX2TS U3897 ( .A(n4666), .Y(n3694) );
AOI22X1TS U3898 ( .A0(n3562), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(
n3086) );
NOR3XLTS U3899 ( .A(n3082), .B(n3081), .C(n3100), .Y(n3083) );
CLKBUFX2TS U3900 ( .A(n3083), .Y(n3621) );
CLKBUFX3TS U3901 ( .A(n3621), .Y(n4663) );
INVX2TS U3902 ( .A(n2989), .Y(n3516) );
CLKBUFX3TS U3903 ( .A(n3084), .Y(n4662) );
AOI22X1TS U3904 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(
n3085) );
OAI211X1TS U3905 ( .A0(n3565), .A1(n3708), .B0(n3086), .C0(n3085), .Y(n3555)
);
AOI22X1TS U3906 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[33]),
.B0(n3596), .B1(n3555), .Y(n3088) );
OAI211XLTS U3907 ( .A0(n3625), .A1(n3011), .B0(n3088), .C0(n3024), .Y(n2568)
);
AOI22X1TS U3908 ( .A0(d_ff3_sh_x_out[60]), .A1(n4421), .B0(
d_ff3_sh_y_out[60]), .B1(n4406), .Y(n3090) );
OAI211XLTS U3909 ( .A0(n4198), .A1(n5059), .B0(n3090), .C0(n3089), .Y(n1955)
);
AO22XLTS U3910 ( .A0(n2989), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n3559), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .Y(
n3091) );
AOI22X1TS U3911 ( .A0(n3562), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(
n3093) );
CLKBUFX3TS U3912 ( .A(n3621), .Y(n3546) );
AOI22X1TS U3913 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(
n3092) );
OAI211X1TS U3914 ( .A0(n3565), .A1(n3619), .B0(n3093), .C0(n3092), .Y(n3552)
);
AOI22X1TS U3915 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[34]),
.B0(n3569), .B1(n3552), .Y(n3094) );
OAI211XLTS U3916 ( .A0(n3554), .A1(n3011), .B0(n3094), .C0(n3022), .Y(n2569)
);
AOI22X1TS U3917 ( .A0(n4421), .A1(d_ff3_sh_x_out[0]), .B0(n4459), .B1(
d_ff3_sh_y_out[0]), .Y(n3096) );
NAND2X1TS U3918 ( .A(d_ff3_LUT_out[0]), .B(n4466), .Y(n3095) );
OAI211XLTS U3919 ( .A0(n4198), .A1(n5061), .B0(n3096), .C0(n3095), .Y(n1958)
);
CLKBUFX3TS U3920 ( .A(n4407), .Y(n4467) );
AOI22X1TS U3921 ( .A0(add_subt_module_intDX[34]), .A1(n4467), .B0(n4464),
.B1(d_ff2_X[34]), .Y(n3098) );
AOI22X1TS U3922 ( .A0(n4412), .A1(d_ff2_Z[34]), .B0(n4369), .B1(d_ff2_Y[34]),
.Y(n3097) );
NAND2X1TS U3923 ( .A(n3098), .B(n3097), .Y(n1801) );
OAI2BB1X1TS U3924 ( .A0N(n3075), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n3515), .Y(n3099) );
OAI21XLTS U3925 ( .A0(n3516), .A1(n5148), .B0(n3515), .Y(n3101) );
INVX2TS U3926 ( .A(n4666), .Y(n3529) );
AOI22X1TS U3927 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(
n3103) );
CLKBUFX3TS U3928 ( .A(n3084), .Y(n3545) );
AOI22X1TS U3929 ( .A0(n3622), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(
n3102) );
OAI211X1TS U3930 ( .A0(n3521), .A1(n2997), .B0(n3103), .C0(n3102), .Y(n3523)
);
AOI22X1TS U3931 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[42]),
.B0(n3596), .B1(n3523), .Y(n3104) );
OAI211XLTS U3932 ( .A0(n2970), .A1(n3011), .B0(n3104), .C0(n3023), .Y(n2577)
);
OAI2BB1X1TS U3933 ( .A0N(n3075), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n3515), .Y(n3105) );
OAI2BB1X1TS U3934 ( .A0N(n2990), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n3515), .Y(n3106) );
CLKBUFX3TS U3935 ( .A(n3621), .Y(n3518) );
AOI22X1TS U3936 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(
n3108) );
AOI22X1TS U3937 ( .A0(n3506), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(
n3107) );
OAI211X1TS U3938 ( .A0(n3521), .A1(n2998), .B0(n3108), .C0(n3107), .Y(n3510)
);
AOI22X1TS U3939 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[45]),
.B0(n3780), .B1(n3510), .Y(n3109) );
OAI211XLTS U3940 ( .A0(n3527), .A1(n3011), .B0(n3109), .C0(n3024), .Y(n2580)
);
AOI22X1TS U3941 ( .A0(add_subt_module_intDY[4]), .A1(n3240), .B0(n4368),
.B1(d_ff3_sh_y_out[4]), .Y(n3111) );
CLKBUFX3TS U3942 ( .A(n3249), .Y(n4444) );
AOI22X1TS U3943 ( .A0(n4444), .A1(d_ff3_LUT_out[4]), .B0(n4331), .B1(
d_ff3_sh_x_out[4]), .Y(n3110) );
NAND2X1TS U3944 ( .A(n3111), .B(n3110), .Y(n1903) );
AOI22X1TS U3945 ( .A0(n4444), .A1(d_ff2_Z[54]), .B0(n4368), .B1(d_ff2_X[54]),
.Y(n3113) );
AOI22X1TS U3946 ( .A0(add_subt_module_intDX[54]), .A1(n4407), .B0(n4054),
.B1(d_ff2_Y[54]), .Y(n3112) );
NAND2X1TS U3947 ( .A(n3113), .B(n3112), .Y(n1918) );
CLKBUFX3TS U3948 ( .A(n4368), .Y(n4470) );
AOI22X1TS U3949 ( .A0(n4400), .A1(d_ff2_Y[13]), .B0(n4470), .B1(d_ff2_X[13]),
.Y(n3115) );
AOI22X1TS U3950 ( .A0(add_subt_module_intDX[13]), .A1(n4455), .B0(n4379),
.B1(d_ff2_Z[13]), .Y(n3114) );
NAND2X1TS U3951 ( .A(n3115), .B(n3114), .Y(n1850) );
AOI22X1TS U3952 ( .A0(add_subt_module_intDX[40]), .A1(n4375), .B0(n4453),
.B1(d_ff2_X[40]), .Y(n3117) );
AOI22X1TS U3953 ( .A0(n4373), .A1(d_ff2_Z[40]), .B0(n4331), .B1(d_ff2_Y[40]),
.Y(n3116) );
NAND2X1TS U3954 ( .A(n3117), .B(n3116), .Y(n1837) );
NAND2X2TS U3955 ( .A(add_subt_module_add_overflow_flag), .B(n3122), .Y(
add_subt_module_FSM_exp_operation_A_S) );
XOR2X1TS U3956 ( .A(DP_OP_92J75_122_9081_n1), .B(n3025), .Y(n3766) );
NOR4X1TS U3957 ( .A(add_subt_module_Exp_Operation_Module_Data_S[6]), .B(
add_subt_module_Exp_Operation_Module_Data_S[3]), .C(
add_subt_module_Exp_Operation_Module_Data_S[2]), .D(
add_subt_module_Exp_Operation_Module_Data_S[0]), .Y(n3120) );
OR4X2TS U3958 ( .A(add_subt_module_Exp_Operation_Module_Data_S[7]), .B(
add_subt_module_Exp_Operation_Module_Data_S[9]), .C(
add_subt_module_Exp_Operation_Module_Data_S[5]), .D(
add_subt_module_Exp_Operation_Module_Data_S[4]), .Y(n3118) );
NOR4X1TS U3959 ( .A(add_subt_module_Exp_Operation_Module_Data_S[1]), .B(
add_subt_module_Exp_Operation_Module_Data_S[10]), .C(
add_subt_module_Exp_Operation_Module_Data_S[8]), .D(n3118), .Y(n3119)
);
NAND4BXLTS U3960 ( .AN(n3766), .B(n3120), .C(n3119), .D(n3122), .Y(n3121) );
OAI21XLTS U3961 ( .A0(n3122), .A1(n5145), .B0(n3121), .Y(n2934) );
NAND3BXLTS U3962 ( .AN(overflow_flag), .B(n4973), .C(n5145), .Y(n3123) );
CLKBUFX3TS U3963 ( .A(n3123), .Y(n4976) );
CLKBUFX2TS U3964 ( .A(n4975), .Y(n4978) );
OAI2BB2XLTS U3965 ( .B0(n4976), .B1(n5196), .A0N(result_add_subt[26]), .A1N(
n4978), .Y(n2390) );
OAI2BB2XLTS U3966 ( .B0(n4976), .B1(n5194), .A0N(result_add_subt[28]), .A1N(
n4978), .Y(n2398) );
CLKBUFX2TS U3967 ( .A(n4978), .Y(n3220) );
OAI2BB2XLTS U3968 ( .B0(n4976), .B1(n5197), .A0N(result_add_subt[24]), .A1N(
n3220), .Y(n2382) );
CLKBUFX2TS U3969 ( .A(n3123), .Y(n4980) );
CLKBUFX3TS U3970 ( .A(n4968), .Y(n4972) );
OAI2BB2XLTS U3971 ( .B0(n5170), .B1(n4972), .A0N(result_add_subt[32]), .A1N(
n4978), .Y(n2414) );
OAI2BB2XLTS U3972 ( .B0(n5169), .B1(n4972), .A0N(result_add_subt[33]), .A1N(
n4975), .Y(n2418) );
OAI2BB2XLTS U3973 ( .B0(n4976), .B1(n5193), .A0N(result_add_subt[29]), .A1N(
n3220), .Y(n2402) );
OAI2BB2XLTS U3974 ( .B0(n5171), .B1(n4972), .A0N(result_add_subt[31]), .A1N(
n3220), .Y(n2410) );
OAI2BB2XLTS U3975 ( .B0(n4976), .B1(n5195), .A0N(result_add_subt[27]), .A1N(
n3220), .Y(n2394) );
CLKBUFX2TS U3976 ( .A(n4980), .Y(n4982) );
CLKBUFX3TS U3977 ( .A(n4982), .Y(n4979) );
OAI2BB2XLTS U3978 ( .B0(n5172), .B1(n4979), .A0N(result_add_subt[30]), .A1N(
n4978), .Y(n2406) );
OAI2BB2XLTS U3979 ( .B0(n4976), .B1(n5198), .A0N(result_add_subt[23]), .A1N(
n4978), .Y(n2378) );
NAND2X2TS U3980 ( .A(n3124), .B(n4500), .Y(n4919) );
CLKAND2X2TS U3981 ( .A(add_subt_module_Exp_Operation_Module_Data_S[10]), .B(
n4919), .Y(n3768) );
AO21XLTS U3982 ( .A0(n2987), .A1(add_subt_module_exp_oper_result[10]), .B0(
n3768), .Y(n2652) );
OAI22X1TS U3983 ( .A0(n5070), .A1(add_subt_module_intDX[44]), .B0(n5041),
.B1(add_subt_module_intDX[45]), .Y(n3357) );
INVX2TS U3984 ( .A(n3357), .Y(n3129) );
AOI22X1TS U3985 ( .A0(add_subt_module_intDX[44]), .A1(n5070), .B0(
add_subt_module_intDX[43]), .B1(n5034), .Y(n3126) );
OAI22X1TS U3986 ( .A0(add_subt_module_intDX[43]), .A1(n5034), .B0(
add_subt_module_intDX[42]), .B1(n5115), .Y(n3356) );
OAI22X1TS U3987 ( .A0(add_subt_module_intDY[42]), .A1(n5050), .B0(
add_subt_module_intDY[41]), .B1(n5116), .Y(n3125) );
NOR2BX1TS U3988 ( .AN(n3126), .B(n3125), .Y(n3138) );
OAI22X1TS U3989 ( .A0(add_subt_module_intDX[41]), .A1(n5051), .B0(
add_subt_module_intDX[40]), .B1(n5114), .Y(n3358) );
AOI22X1TS U3990 ( .A0(n3126), .A1(n3356), .B0(n3138), .B1(n3358), .Y(n3128)
);
AOI22X1TS U3991 ( .A0(add_subt_module_intDX[46]), .A1(n5092), .B0(
add_subt_module_intDX[45]), .B1(n5041), .Y(n3127) );
OAI21X1TS U3992 ( .A0(add_subt_module_intDY[47]), .A1(n5030), .B0(n3127),
.Y(n3136) );
AOI21X1TS U3993 ( .A0(n3129), .A1(n3128), .B0(n3136), .Y(n3142) );
NOR2XLTS U3994 ( .A(add_subt_module_intDY[47]), .B(n5030), .Y(n3140) );
AOI22X1TS U3995 ( .A0(add_subt_module_intDY[47]), .A1(n5030), .B0(
add_subt_module_intDY[46]), .B1(n5127), .Y(n3359) );
OAI22X1TS U3996 ( .A0(add_subt_module_intDX[39]), .A1(n5074), .B0(
add_subt_module_intDX[38]), .B1(n5015), .Y(n3352) );
NAND2X1TS U3997 ( .A(add_subt_module_intDX[39]), .B(n5074), .Y(n3135) );
AOI22X1TS U3998 ( .A0(add_subt_module_intDY[32]), .A1(n5066), .B0(
add_subt_module_intDY[33]), .B1(n5017), .Y(n3355) );
OAI22X1TS U3999 ( .A0(add_subt_module_intDY[33]), .A1(n5017), .B0(
add_subt_module_intDY[34]), .B1(n5062), .Y(n3161) );
AOI22X1TS U4000 ( .A0(add_subt_module_intDY[34]), .A1(n5062), .B0(
add_subt_module_intDY[35]), .B1(n5016), .Y(n3354) );
AOI22X1TS U4001 ( .A0(add_subt_module_intDX[38]), .A1(n5015), .B0(
add_subt_module_intDX[37]), .B1(n5035), .Y(n3130) );
OAI21X1TS U4002 ( .A0(add_subt_module_intDY[39]), .A1(n5143), .B0(n3130),
.Y(n3132) );
OAI22X1TS U4003 ( .A0(add_subt_module_intDY[35]), .A1(n5016), .B0(
add_subt_module_intDY[36]), .B1(n5120), .Y(n3131) );
NOR2X1TS U4004 ( .A(n3132), .B(n3131), .Y(n3166) );
OAI22X1TS U4005 ( .A0(add_subt_module_intDX[37]), .A1(n5035), .B0(
add_subt_module_intDX[36]), .B1(n5119), .Y(n3353) );
INVX2TS U4006 ( .A(n3132), .Y(n3133) );
AOI222X1TS U4007 ( .A0(n3352), .A1(n3135), .B0(n3134), .B1(n3166), .C0(n3353), .C1(n3133), .Y(n3139) );
INVX2TS U4008 ( .A(n3136), .Y(n3137) );
OAI211X1TS U4009 ( .A0(add_subt_module_intDY[40]), .A1(n5146), .B0(n3138),
.C0(n3137), .Y(n3165) );
OAI22X1TS U4010 ( .A0(n3140), .A1(n3359), .B0(n3139), .B1(n3165), .Y(n3141)
);
NAND2X1TS U4011 ( .A(add_subt_module_intDX[48]), .B(n5029), .Y(n3162) );
OAI32X1TS U4012 ( .A0(n3363), .A1(n3142), .A2(n3141), .B0(n3162), .B1(n3363),
.Y(n3213) );
OAI22X1TS U4013 ( .A0(n5069), .A1(add_subt_module_intDY[54]), .B0(n5040),
.B1(add_subt_module_intDY[53]), .Y(n3159) );
AOI22X1TS U4014 ( .A0(add_subt_module_intDX[61]), .A1(n5025), .B0(
add_subt_module_intDX[62]), .B1(n5058), .Y(n3153) );
AOI22X1TS U4015 ( .A0(add_subt_module_intDX[60]), .A1(n5059), .B0(
add_subt_module_intDX[59]), .B1(n5036), .Y(n3143) );
NAND2X1TS U4016 ( .A(n3153), .B(n3143), .Y(n3148) );
OAI22X1TS U4017 ( .A0(add_subt_module_intDY[57]), .A1(n5096), .B0(
add_subt_module_intDY[58]), .B1(n5047), .Y(n3149) );
AOI211X1TS U4018 ( .A0(add_subt_module_intDX[56]), .A1(n5038), .B0(n3148),
.C0(n3149), .Y(n3209) );
OAI22X1TS U4019 ( .A0(add_subt_module_intDY[49]), .A1(n5097), .B0(
add_subt_module_intDY[55]), .B1(n5028), .Y(n3144) );
OAI22X1TS U4020 ( .A0(add_subt_module_intDY[51]), .A1(n5101), .B0(
add_subt_module_intDY[52]), .B1(n5020), .Y(n3154) );
AOI211XLTS U4021 ( .A0(add_subt_module_intDX[50]), .A1(n5039), .B0(n3144),
.C0(n3154), .Y(n3145) );
NAND3BXLTS U4022 ( .AN(n3159), .B(n3209), .C(n3145), .Y(n3212) );
OAI22X1TS U4023 ( .A0(add_subt_module_intDX[61]), .A1(n5025), .B0(
add_subt_module_intDX[60]), .B1(n5059), .Y(n3360) );
NOR2XLTS U4024 ( .A(add_subt_module_intDX[62]), .B(n5058), .Y(n3152) );
OAI22X1TS U4025 ( .A0(n5036), .A1(add_subt_module_intDX[59]), .B0(n5102),
.B1(add_subt_module_intDX[58]), .Y(n3147) );
INVX2TS U4026 ( .A(n3147), .Y(n3150) );
OAI22X1TS U4027 ( .A0(add_subt_module_intDX[56]), .A1(n5038), .B0(
add_subt_module_intDX[57]), .B1(n5081), .Y(n3146) );
NOR2X1TS U4028 ( .A(n3147), .B(n3146), .Y(n3344) );
AOI211X1TS U4029 ( .A0(n3150), .A1(n3149), .B0(n3344), .C0(n3148), .Y(n3151)
);
AOI211X1TS U4030 ( .A0(n3153), .A1(n3360), .B0(n3152), .C0(n3151), .Y(n3211)
);
AOI22X1TS U4031 ( .A0(add_subt_module_intDY[54]), .A1(n5069), .B0(
add_subt_module_intDY[55]), .B1(n5028), .Y(n3160) );
INVX2TS U4032 ( .A(n3154), .Y(n3156) );
OAI22X1TS U4033 ( .A0(add_subt_module_intDX[50]), .A1(n5039), .B0(
add_subt_module_intDX[51]), .B1(n5082), .Y(n3362) );
AOI22X1TS U4034 ( .A0(add_subt_module_intDY[53]), .A1(n5040), .B0(
add_subt_module_intDY[52]), .B1(n5020), .Y(n3155) );
NAND2X1TS U4035 ( .A(n3160), .B(n3155), .Y(n3351) );
AOI21X1TS U4036 ( .A0(n3156), .A1(n3362), .B0(n3351), .Y(n3158) );
NOR2XLTS U4037 ( .A(add_subt_module_intDY[55]), .B(n5028), .Y(n3157) );
AOI211X1TS U4038 ( .A0(n3160), .A1(n3159), .B0(n3158), .C0(n3157), .Y(n3208)
);
INVX2TS U4039 ( .A(n3161), .Y(n3163) );
NOR4BX1TS U4040 ( .AN(n3166), .B(n3165), .C(n3212), .D(n3164), .Y(n3388) );
AOI22X1TS U4041 ( .A0(add_subt_module_intDY[27]), .A1(n5095), .B0(
add_subt_module_intDY[26]), .B1(n5022), .Y(n3367) );
OAI22X1TS U4042 ( .A0(add_subt_module_intDY[29]), .A1(n5052), .B0(
add_subt_module_intDY[30]), .B1(n5126), .Y(n3167) );
AOI21X1TS U4043 ( .A0(add_subt_module_intDX[31]), .A1(n5012), .B0(n3167),
.Y(n3170) );
AOI22X1TS U4044 ( .A0(add_subt_module_intDX[27]), .A1(n5094), .B0(
add_subt_module_intDX[28]), .B1(n5021), .Y(n3168) );
NAND2X1TS U4045 ( .A(n3170), .B(n3168), .Y(n3206) );
OAI22X1TS U4046 ( .A0(add_subt_module_intDX[29]), .A1(n5098), .B0(
add_subt_module_intDX[28]), .B1(n5021), .Y(n3364) );
NAND2X1TS U4047 ( .A(add_subt_module_intDX[31]), .B(n5012), .Y(n3169) );
OAI22X1TS U4048 ( .A0(add_subt_module_intDX[31]), .A1(n5012), .B0(
add_subt_module_intDX[30]), .B1(n5118), .Y(n3365) );
AOI22X1TS U4049 ( .A0(n3170), .A1(n3364), .B0(n3169), .B1(n3365), .Y(n3205)
);
NOR2XLTS U4050 ( .A(add_subt_module_intDY[23]), .B(n5078), .Y(n3200) );
AOI22X1TS U4051 ( .A0(add_subt_module_intDY[23]), .A1(n5078), .B0(
add_subt_module_intDY[22]), .B1(n5018), .Y(n3366) );
NAND2X1TS U4052 ( .A(add_subt_module_intDX[17]), .B(n5014), .Y(n3172) );
OAI22X1TS U4053 ( .A0(add_subt_module_intDX[17]), .A1(n5014), .B0(
add_subt_module_intDX[18]), .B1(n5122), .Y(n3171) );
AOI31X1TS U4054 ( .A0(add_subt_module_intDY[16]), .A1(n3172), .A2(n5137),
.B0(n3171), .Y(n3346) );
OAI22X1TS U4055 ( .A0(add_subt_module_intDY[19]), .A1(n5043), .B0(
add_subt_module_intDY[18]), .B1(n5124), .Y(n3195) );
OAI22X1TS U4056 ( .A0(n3346), .A1(n3195), .B0(add_subt_module_intDX[19]),
.B1(n5117), .Y(n3175) );
OAI22X1TS U4057 ( .A0(add_subt_module_intDY[22]), .A1(n5018), .B0(
add_subt_module_intDY[21]), .B1(n5125), .Y(n3173) );
NAND2X1TS U4058 ( .A(add_subt_module_intDX[20]), .B(n5042), .Y(n3174) );
OAI22X1TS U4059 ( .A0(add_subt_module_intDX[20]), .A1(n5042), .B0(
add_subt_module_intDX[21]), .B1(n5121), .Y(n3376) );
AOI32X1TS U4060 ( .A0(n3175), .A1(n3193), .A2(n3174), .B0(n3376), .B1(n3193),
.Y(n3199) );
AOI22X1TS U4061 ( .A0(add_subt_module_intDX[15]), .A1(n5093), .B0(
add_subt_module_intDX[14]), .B1(n5019), .Y(n3189) );
NAND2X1TS U4062 ( .A(add_subt_module_intDX[13]), .B(n5076), .Y(n3176) );
NOR2XLTS U4063 ( .A(add_subt_module_intDY[11]), .B(n5079), .Y(n3187) );
AOI22X1TS U4064 ( .A0(add_subt_module_intDY[11]), .A1(n5079), .B0(
add_subt_module_intDY[10]), .B1(n5037), .Y(n3380) );
OAI22X1TS U4065 ( .A0(n5071), .A1(add_subt_module_intDX[6]), .B0(n5032),
.B1(add_subt_module_intDX[7]), .Y(n3384) );
INVX2TS U4066 ( .A(n3384), .Y(n3182) );
AOI22X1TS U4067 ( .A0(add_subt_module_intDY[3]), .A1(n5027), .B0(
add_subt_module_intDY[2]), .B1(n5063), .Y(n3377) );
NAND2X1TS U4068 ( .A(add_subt_module_intDX[0]), .B(n5061), .Y(n3331) );
OAI22X1TS U4069 ( .A0(add_subt_module_intDY[1]), .A1(n5073), .B0(n3177),
.B1(n3331), .Y(n3178) );
OAI22X1TS U4070 ( .A0(add_subt_module_intDY[3]), .A1(n5027), .B0(
add_subt_module_intDY[2]), .B1(n5063), .Y(n3375) );
OAI22X1TS U4071 ( .A0(n3179), .A1(n3377), .B0(n3178), .B1(n3375), .Y(n3180)
);
NAND2X1TS U4072 ( .A(add_subt_module_intDX[4]), .B(n5065), .Y(n3334) );
OAI22X1TS U4073 ( .A0(add_subt_module_intDX[4]), .A1(n5065), .B0(
add_subt_module_intDX[5]), .B1(n5033), .Y(n3374) );
AOI32X1TS U4074 ( .A0(n3180), .A1(n3385), .A2(n3334), .B0(n3374), .B1(n3385),
.Y(n3181) );
AOI22X1TS U4075 ( .A0(add_subt_module_intDX[7]), .A1(n5032), .B0(n3182),
.B1(n3181), .Y(n3185) );
OAI22X1TS U4076 ( .A0(add_subt_module_intDY[9]), .A1(n5100), .B0(
add_subt_module_intDY[10]), .B1(n5037), .Y(n3183) );
NAND2X1TS U4077 ( .A(add_subt_module_intDX[8]), .B(n5026), .Y(n3184) );
OAI22X1TS U4078 ( .A0(add_subt_module_intDX[8]), .A1(n5026), .B0(
add_subt_module_intDX[9]), .B1(n5113), .Y(n3381) );
AOI32X1TS U4079 ( .A0(n3185), .A1(n3340), .A2(n3184), .B0(n3381), .B1(n3340),
.Y(n3186) );
OAI32X1TS U4080 ( .A0(n3347), .A1(n3187), .A2(n3380), .B0(n3186), .B1(n3347),
.Y(n3197) );
OAI22X1TS U4081 ( .A0(add_subt_module_intDX[14]), .A1(n5019), .B0(
add_subt_module_intDX[13]), .B1(n5076), .Y(n3188) );
AOI21X1TS U4082 ( .A0(add_subt_module_intDY[15]), .A1(n5077), .B0(n3188),
.Y(n3345) );
INVX2TS U4083 ( .A(n3189), .Y(n3191) );
NAND2X1TS U4084 ( .A(add_subt_module_intDY[15]), .B(n5077), .Y(n3190) );
AOI22X1TS U4085 ( .A0(n3345), .A1(n3192), .B0(n3191), .B1(n3190), .Y(n3196)
);
OAI21XLTS U4086 ( .A0(add_subt_module_intDY[20]), .A1(n5144), .B0(n3193),
.Y(n3194) );
AOI211X1TS U4087 ( .A0(add_subt_module_intDX[17]), .A1(n5014), .B0(n3195),
.C0(n3194), .Y(n3389) );
NAND2X1TS U4088 ( .A(add_subt_module_intDX[16]), .B(n5134), .Y(n3342) );
OAI211XLTS U4089 ( .A0(n3200), .A1(n3366), .B0(n3199), .C0(n3198), .Y(n3203)
);
OAI22X1TS U4090 ( .A0(add_subt_module_intDY[25]), .A1(n5099), .B0(
add_subt_module_intDY[26]), .B1(n5022), .Y(n3201) );
NAND2X1TS U4091 ( .A(add_subt_module_intDX[24]), .B(n5013), .Y(n3202) );
OAI22X1TS U4092 ( .A0(add_subt_module_intDX[24]), .A1(n5013), .B0(
add_subt_module_intDX[25]), .B1(n5123), .Y(n3361) );
AOI32X1TS U4093 ( .A0(n3203), .A1(n3372), .A2(n3202), .B0(n3361), .B1(n3372),
.Y(n3204) );
OAI211XLTS U4094 ( .A0(n3367), .A1(n3206), .B0(n3205), .C0(n3204), .Y(n3207)
);
AOI22X1TS U4095 ( .A0(n3209), .A1(n3208), .B0(n3016), .B1(n3207), .Y(n3210)
);
INVX2TS U4096 ( .A(n4991), .Y(n3881) );
CLKBUFX3TS U4097 ( .A(n4997), .Y(n3900) );
CLKBUFX2TS U4098 ( .A(n3900), .Y(n3732) );
NOR2XLTS U4099 ( .A(n4987), .B(n3732), .Y(n3214) );
CLKBUFX2TS U4100 ( .A(n3214), .Y(n3889) );
CLKBUFX2TS U4101 ( .A(n3869), .Y(n3872) );
CLKBUFX2TS U4102 ( .A(n3732), .Y(n3873) );
CLKBUFX3TS U4103 ( .A(n3873), .Y(n5000) );
AOI22X1TS U4104 ( .A0(add_subt_module_intDY[44]), .A1(n4992), .B0(
add_subt_module_DMP[44]), .B1(n5000), .Y(n3215) );
OAI2BB1X1TS U4105 ( .A0N(add_subt_module_intDX[44]), .A1N(n3872), .B0(n3215),
.Y(n1864) );
INVX2TS U4106 ( .A(n4250), .Y(n4151) );
NAND2X1TS U4107 ( .A(n4151), .B(n3932), .Y(n3216) );
NAND2X1TS U4108 ( .A(sel_mux_1_reg), .B(n4983), .Y(n3219) );
CLKBUFX2TS U4109 ( .A(n4263), .Y(n4311) );
CLKBUFX2TS U4110 ( .A(n4963), .Y(n3635) );
OA22X1TS U4111 ( .A0(d_ff_Xn[57]), .A1(n4100), .B0(d_ff2_X[57]), .B1(n3635),
.Y(n2788) );
CLKBUFX2TS U4112 ( .A(n4263), .Y(n4260) );
OA22X1TS U4113 ( .A0(d_ff_Xn[61]), .A1(n4260), .B0(d_ff2_X[61]), .B1(n3635),
.Y(n2792) );
OA22X1TS U4114 ( .A0(d_ff_Xn[59]), .A1(n4263), .B0(d_ff2_X[59]), .B1(n3635),
.Y(n2790) );
NOR2X2TS U4115 ( .A(cont_iter_out[1]), .B(cont_iter_out[2]), .Y(n4951) );
INVX2TS U4116 ( .A(n4951), .Y(n4367) );
NAND2X1TS U4117 ( .A(n5023), .B(n5057), .Y(n3247) );
INVX2TS U4118 ( .A(n3955), .Y(n3218) );
NAND2X1TS U4119 ( .A(n2959), .B(n5011), .Y(n4249) );
INVX2TS U4120 ( .A(n4249), .Y(n3773) );
OAI2BB1X1TS U4121 ( .A0N(n3955), .A1N(n4675), .B0(sel_mux_1_reg), .Y(n3217)
);
OAI31X1TS U4122 ( .A0(n4435), .A1(n4154), .A2(n3218), .B0(n3217), .Y(n2853)
);
OA22X1TS U4123 ( .A0(d_ff2_X[0]), .A1(n4298), .B0(d_ff_Xn[0]), .B1(n4100),
.Y(n2669) );
CLKBUFX3TS U4124 ( .A(n4298), .Y(n3221) );
OA22X1TS U4125 ( .A0(d_ff2_X[48]), .A1(n3221), .B0(d_ff_Xn[48]), .B1(n4299),
.Y(n2765) );
OA22X1TS U4126 ( .A0(d_ff2_X[3]), .A1(n4262), .B0(d_ff_Xn[3]), .B1(n4985),
.Y(n2675) );
OA22X1TS U4127 ( .A0(d_ff2_X[49]), .A1(n3221), .B0(d_ff_Xn[49]), .B1(n4260),
.Y(n2767) );
OA22X1TS U4128 ( .A0(d_ff2_X[46]), .A1(n3221), .B0(d_ff_Xn[46]), .B1(n4100),
.Y(n2761) );
OA22X1TS U4129 ( .A0(d_ff2_X[9]), .A1(n4963), .B0(d_ff_Xn[9]), .B1(n3219),
.Y(n2687) );
OA22X1TS U4130 ( .A0(d_ff2_X[6]), .A1(n4261), .B0(d_ff_Xn[6]), .B1(n4985),
.Y(n2681) );
OA22X1TS U4131 ( .A0(d_ff2_X[45]), .A1(n3221), .B0(d_ff_Xn[45]), .B1(n4299),
.Y(n2759) );
CLKBUFX3TS U4132 ( .A(n4260), .Y(n4962) );
OA22X1TS U4133 ( .A0(d_ff2_X[43]), .A1(n3221), .B0(d_ff_Xn[43]), .B1(n4962),
.Y(n2755) );
OA22X1TS U4134 ( .A0(d_ff2_X[7]), .A1(n4261), .B0(d_ff_Xn[7]), .B1(n3219),
.Y(n2683) );
OA22X1TS U4135 ( .A0(d_ff2_X[42]), .A1(n3221), .B0(d_ff_Xn[42]), .B1(n4962),
.Y(n2753) );
OA22X1TS U4136 ( .A0(d_ff2_X[41]), .A1(n3221), .B0(d_ff_Xn[41]), .B1(n4962),
.Y(n2751) );
OA22X1TS U4137 ( .A0(d_ff2_X[39]), .A1(n3221), .B0(d_ff_Xn[39]), .B1(n4962),
.Y(n2747) );
OA22X1TS U4138 ( .A0(d_ff2_X[19]), .A1(n4262), .B0(d_ff_Xn[19]), .B1(n4962),
.Y(n2707) );
OA22X1TS U4139 ( .A0(d_ff2_X[36]), .A1(n3221), .B0(d_ff_Xn[36]), .B1(n4962),
.Y(n2741) );
OA22X1TS U4140 ( .A0(d_ff2_X[29]), .A1(n4261), .B0(d_ff_Xn[29]), .B1(n3219),
.Y(n2727) );
OA22X1TS U4141 ( .A0(d_ff2_X[32]), .A1(n4261), .B0(d_ff_Xn[32]), .B1(n4962),
.Y(n2733) );
OA22X1TS U4142 ( .A0(d_ff2_X[24]), .A1(n4262), .B0(d_ff_Xn[24]), .B1(n4260),
.Y(n2717) );
OA22X1TS U4143 ( .A0(d_ff2_X[28]), .A1(n4298), .B0(d_ff_Xn[28]), .B1(n4299),
.Y(n2725) );
OAI2BB2XLTS U4144 ( .B0(n5192), .B1(n4979), .A0N(result_add_subt[1]), .A1N(
n3220), .Y(n2290) );
OAI2BB2XLTS U4145 ( .B0(n5191), .B1(n4976), .A0N(result_add_subt[2]), .A1N(
n3220), .Y(n2294) );
OAI2BB2XLTS U4146 ( .B0(n5135), .B1(n4972), .A0N(result_add_subt[0]), .A1N(
n3220), .Y(n2286) );
OA22X1TS U4147 ( .A0(d_ff2_X[53]), .A1(n3221), .B0(d_ff_Xn[53]), .B1(n4260),
.Y(n2784) );
OA22X1TS U4148 ( .A0(d_ff2_X[54]), .A1(n3635), .B0(d_ff_Xn[54]), .B1(n4100),
.Y(n2785) );
OA22X1TS U4149 ( .A0(d_ff2_X[55]), .A1(n3635), .B0(d_ff_Xn[55]), .B1(n4299),
.Y(n2786) );
AOI22X1TS U4150 ( .A0(add_subt_module_intDX[63]), .A1(n4461), .B0(n4443),
.B1(d_ff2_X[63]), .Y(n3223) );
AOI22X1TS U4151 ( .A0(n4384), .A1(d_ff2_Z[63]), .B0(n4458), .B1(d_ff2_Y[63]),
.Y(n3222) );
NAND2X1TS U4152 ( .A(n3223), .B(n3222), .Y(n1945) );
CLKBUFX2TS U4153 ( .A(n3224), .Y(n5529) );
OR2X2TS U4154 ( .A(n3225), .B(n4250), .Y(n3952) );
CLKBUFX2TS U4155 ( .A(n3952), .Y(n4147) );
CLKBUFX3TS U4156 ( .A(n4958), .Y(n4487) );
NOR2X2TS U4157 ( .A(n4487), .B(n2985), .Y(n4934) );
NAND2X1TS U4158 ( .A(cont_iter_out[1]), .B(n4934), .Y(n3328) );
NAND2X1TS U4159 ( .A(cont_iter_out[2]), .B(n5056), .Y(n4426) );
INVX2TS U4160 ( .A(n4426), .Y(n3226) );
INVX2TS U4161 ( .A(n4366), .Y(n4577) );
NOR2X1TS U4162 ( .A(n4577), .B(n3247), .Y(n4953) );
OAI32X1TS U4163 ( .A0(n4958), .A1(n3226), .A2(n4953), .B0(n4949), .B1(
d_ff3_LUT_out[14]), .Y(n3227) );
NAND2X1TS U4164 ( .A(n3328), .B(n3227), .Y(n2809) );
CLKBUFX2TS U4165 ( .A(n4263), .Y(n4299) );
OA22X1TS U4166 ( .A0(d_ff_Xn[56]), .A1(n4299), .B0(d_ff2_X[56]), .B1(n3635),
.Y(n2787) );
AOI22X1TS U4167 ( .A0(n4430), .A1(d_ff2_Z[24]), .B0(n4459), .B1(d_ff2_X[24]),
.Y(n3229) );
AOI22X1TS U4168 ( .A0(add_subt_module_intDX[24]), .A1(n4438), .B0(n4431),
.B1(d_ff2_Y[24]), .Y(n3228) );
NAND2X1TS U4169 ( .A(n3229), .B(n3228), .Y(n1745) );
AOI22X1TS U4170 ( .A0(n4384), .A1(d_ff3_LUT_out[47]), .B0(n4343), .B1(
d_ff3_sh_y_out[47]), .Y(n3231) );
AOI22X1TS U4171 ( .A0(add_subt_module_intDY[47]), .A1(n4407), .B0(n4458),
.B1(d_ff3_sh_x_out[47]), .Y(n3230) );
NAND2X1TS U4172 ( .A(n3231), .B(n3230), .Y(n1890) );
AOI22X1TS U4173 ( .A0(n4373), .A1(d_ff2_Z[7]), .B0(n4453), .B1(d_ff2_X[7]),
.Y(n3233) );
AOI22X1TS U4174 ( .A0(add_subt_module_intDX[7]), .A1(n4455), .B0(n4374),
.B1(d_ff2_Y[7]), .Y(n3232) );
NAND2X1TS U4175 ( .A(n3233), .B(n3232), .Y(n1840) );
AOI22X1TS U4176 ( .A0(n4384), .A1(d_ff2_Z[0]), .B0(n4169), .B1(d_ff2_X[0]),
.Y(n3235) );
AOI22X1TS U4177 ( .A0(add_subt_module_intDX[0]), .A1(n4407), .B0(n4374),
.B1(d_ff2_Y[0]), .Y(n3234) );
NAND2X1TS U4178 ( .A(n3235), .B(n3234), .Y(n1909) );
AOI22X1TS U4179 ( .A0(add_subt_module_intDX[48]), .A1(n4407), .B0(n4406),
.B1(d_ff2_X[48]), .Y(n3237) );
AOI22X1TS U4180 ( .A0(n4444), .A1(d_ff2_Z[48]), .B0(n4003), .B1(d_ff2_Y[48]),
.Y(n3236) );
NAND2X1TS U4181 ( .A(n3237), .B(n3236), .Y(n1901) );
AOI22X1TS U4182 ( .A0(n4471), .A1(d_ff2_Z[43]), .B0(n4453), .B1(d_ff2_X[43]),
.Y(n3239) );
AOI22X1TS U4183 ( .A0(add_subt_module_intDX[43]), .A1(n4455), .B0(n4374),
.B1(d_ff2_Y[43]), .Y(n3238) );
NAND2X1TS U4184 ( .A(n3239), .B(n3238), .Y(n1844) );
AOI22X1TS U4185 ( .A0(add_subt_module_intDY[2]), .A1(n3240), .B0(n4368),
.B1(d_ff3_sh_y_out[2]), .Y(n3242) );
AOI22X1TS U4186 ( .A0(n4384), .A1(d_ff3_LUT_out[2]), .B0(n4331), .B1(
d_ff3_sh_x_out[2]), .Y(n3241) );
NAND2X1TS U4187 ( .A(n3242), .B(n3241), .Y(n1896) );
AOI22X1TS U4188 ( .A0(n4465), .A1(d_ff3_sh_x_out[10]), .B0(n4453), .B1(
d_ff3_sh_y_out[10]), .Y(n3244) );
AOI22X1TS U4189 ( .A0(add_subt_module_intDY[10]), .A1(n4455), .B0(n4422),
.B1(d_ff3_LUT_out[10]), .Y(n3243) );
NAND2X1TS U4190 ( .A(n3244), .B(n3243), .Y(n1846) );
AOI22X1TS U4191 ( .A0(add_subt_module_intDX[28]), .A1(n4013), .B0(n4343),
.B1(d_ff2_X[28]), .Y(n3246) );
AOI22X1TS U4192 ( .A0(n4430), .A1(d_ff2_Z[28]), .B0(n4431), .B1(d_ff2_Y[28]),
.Y(n3245) );
NAND2X1TS U4193 ( .A(n3246), .B(n3245), .Y(n1739) );
OAI31X4TS U4194 ( .A0(cont_iter_out[3]), .A1(n3026), .A2(n4426), .B0(n4932),
.Y(n4578) );
INVX2TS U4195 ( .A(n3247), .Y(n4961) );
NAND3X2TS U4196 ( .A(n4366), .B(cont_iter_out[0]), .C(n5023), .Y(n4947) );
OAI211XLTS U4197 ( .A0(n4961), .A1(n4367), .B0(n4947), .C0(n4340), .Y(n3248)
);
INVX2TS U4198 ( .A(n4508), .Y(n4959) );
OA22X1TS U4199 ( .A0(n4578), .A1(n3248), .B0(n4959), .B1(d_ff3_LUT_out[15]),
.Y(n2810) );
AOI22X1TS U4200 ( .A0(add_subt_module_intDX[60]), .A1(n4407), .B0(
d_ff2_X[60]), .B1(n4343), .Y(n3251) );
CLKBUFX3TS U4201 ( .A(n3249), .Y(n4460) );
AOI22X1TS U4202 ( .A0(d_ff2_Y[60]), .A1(n4437), .B0(n4460), .B1(d_ff2_Z[60]),
.Y(n3250) );
NAND2X1TS U4203 ( .A(n3251), .B(n3250), .Y(n1936) );
AOI22X1TS U4204 ( .A0(n4373), .A1(d_ff2_Z[38]), .B0(n4372), .B1(d_ff2_X[38]),
.Y(n3253) );
AOI22X1TS U4205 ( .A0(add_subt_module_intDX[38]), .A1(n4375), .B0(n4331),
.B1(d_ff2_Y[38]), .Y(n3252) );
NAND2X1TS U4206 ( .A(n3253), .B(n3252), .Y(n1833) );
NAND2X1TS U4207 ( .A(cont_iter_out[1]), .B(cont_iter_out[0]), .Y(n4192) );
NAND2X1TS U4208 ( .A(n3933), .B(n3254), .Y(n3391) );
INVX2TS U4209 ( .A(n3391), .Y(n3294) );
NOR2X1TS U4210 ( .A(n5068), .B(n3857), .Y(n4258) );
NOR2BX1TS U4211 ( .AN(n4258), .B(cont_var_out[0]), .Y(n4039) );
NOR2X1TS U4212 ( .A(n5057), .B(n4924), .Y(n3905) );
INVX2TS U4213 ( .A(n3905), .Y(n4927) );
OAI21X1TS U4214 ( .A0(n5056), .A1(n4927), .B0(n4108), .Y(n4926) );
CLKBUFX2TS U4215 ( .A(clk), .Y(n3267) );
CLKBUFX2TS U4216 ( .A(clk), .Y(n3274) );
CLKBUFX2TS U4217 ( .A(clk), .Y(n3255) );
CLKBUFX2TS U4218 ( .A(clk), .Y(n3268) );
CLKBUFX2TS U4219 ( .A(clk), .Y(n3272) );
CLKBUFX2TS U4220 ( .A(clk), .Y(n3270) );
CLKBUFX2TS U4221 ( .A(clk), .Y(n3264) );
BUFX3TS U4222 ( .A(n3270), .Y(n5371) );
BUFX3TS U4223 ( .A(n3255), .Y(n5330) );
BUFX3TS U4224 ( .A(n3268), .Y(n5329) );
BUFX3TS U4225 ( .A(n3275), .Y(n5525) );
BUFX3TS U4226 ( .A(n3276), .Y(n5524) );
BUFX3TS U4227 ( .A(n3282), .Y(n5526) );
BUFX3TS U4228 ( .A(n3277), .Y(n5459) );
BUFX3TS U4229 ( .A(n3277), .Y(n5457) );
BUFX3TS U4230 ( .A(n3277), .Y(n5456) );
BUFX3TS U4231 ( .A(n3277), .Y(n5454) );
BUFX3TS U4232 ( .A(n3282), .Y(n5520) );
BUFX3TS U4233 ( .A(n3280), .Y(n5522) );
BUFX3TS U4234 ( .A(n3277), .Y(n5455) );
BUFX3TS U4235 ( .A(n3282), .Y(n5519) );
CLKBUFX2TS U4236 ( .A(n3275), .Y(n3281) );
BUFX3TS U4237 ( .A(n3281), .Y(n5499) );
BUFX3TS U4238 ( .A(n3282), .Y(n5498) );
CLKBUFX3TS U4239 ( .A(n5532), .Y(n5492) );
BUFX3TS U4240 ( .A(n3281), .Y(n5502) );
BUFX3TS U4241 ( .A(n3281), .Y(n5500) );
BUFX3TS U4242 ( .A(n5532), .Y(n5503) );
BUFX3TS U4243 ( .A(n3282), .Y(n5518) );
BUFX3TS U4244 ( .A(n5530), .Y(n5514) );
BUFX3TS U4245 ( .A(n3279), .Y(n5464) );
BUFX3TS U4246 ( .A(n3031), .Y(n5507) );
BUFX3TS U4247 ( .A(n3279), .Y(n5465) );
BUFX3TS U4248 ( .A(n3277), .Y(n5460) );
BUFX3TS U4249 ( .A(n3279), .Y(n5467) );
BUFX3TS U4250 ( .A(n3278), .Y(n5286) );
BUFX3TS U4251 ( .A(n3277), .Y(n5462) );
BUFX3TS U4252 ( .A(n3279), .Y(n5471) );
BUFX3TS U4253 ( .A(n5531), .Y(n5505) );
BUFX3TS U4254 ( .A(n3279), .Y(n5463) );
BUFX3TS U4255 ( .A(n5532), .Y(n5495) );
BUFX3TS U4256 ( .A(n3280), .Y(n5473) );
BUFX3TS U4257 ( .A(n3278), .Y(n5287) );
BUFX3TS U4258 ( .A(n5532), .Y(n5497) );
BUFX3TS U4259 ( .A(n3280), .Y(n5480) );
BUFX3TS U4260 ( .A(n3280), .Y(n5479) );
BUFX3TS U4261 ( .A(n3280), .Y(n5478) );
BUFX3TS U4262 ( .A(n5532), .Y(n5501) );
BUFX3TS U4263 ( .A(n3278), .Y(n5290) );
BUFX3TS U4264 ( .A(n3279), .Y(n5470) );
BUFX3TS U4265 ( .A(n3278), .Y(n5292) );
BUFX3TS U4266 ( .A(n3279), .Y(n5469) );
BUFX3TS U4267 ( .A(n3280), .Y(n5476) );
BUFX3TS U4268 ( .A(n5532), .Y(n5504) );
BUFX3TS U4269 ( .A(n3282), .Y(n5511) );
AOI22X1TS U4270 ( .A0(n3562), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(
n3283) );
OAI2BB1X1TS U4271 ( .A0N(n3621), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n3283), .Y(n3284) );
NOR3X1TS U4272 ( .A(n3285), .B(n3558), .C(n3284), .Y(n3324) );
AOI22X1TS U4273 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .Y(
n3287) );
AOI22X1TS U4274 ( .A0(n3562), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(
n3286) );
INVX2TS U4275 ( .A(n3285), .Y(n4664) );
NAND3XLTS U4276 ( .A(n3287), .B(n3286), .C(n4664), .Y(n3322) );
AOI22X1TS U4277 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[23]),
.B0(n3566), .B1(n3322), .Y(n3288) );
OAI21XLTS U4278 ( .A0(n3324), .A1(n3306), .B0(n3288), .Y(n2558) );
CLKAND2X2TS U4279 ( .A(n2983), .B(add_subt_module_LZA_output[0]), .Y(n4302)
);
OAI32X4TS U4280 ( .A0(n4302), .A1(add_subt_module_FSM_selector_B[1]), .A2(
add_subt_module_exp_oper_result[0]), .B0(n5075), .B1(n4302), .Y(n4791)
);
CLKBUFX3TS U4281 ( .A(n3289), .Y(n4900) );
INVX2TS U4282 ( .A(n3291), .Y(n4879) );
INVX2TS U4283 ( .A(n3630), .Y(n3399) );
CLKBUFX2TS U4284 ( .A(n3289), .Y(n4850) );
INVX2TS U4285 ( .A(n4850), .Y(n4756) );
AOI22X1TS U4286 ( .A0(n4900), .A1(n3399), .B0(n3633), .B1(n4756), .Y(n4680)
);
AOI22X1TS U4287 ( .A0(add_subt_module_LZA_output[2]), .A1(n2983), .B0(n2991),
.B1(add_subt_module_exp_oper_result[2]), .Y(n3292) );
INVX2TS U4288 ( .A(n4820), .Y(n4679) );
NAND2X1TS U4289 ( .A(n3633), .B(n4679), .Y(n3634) );
OAI21XLTS U4290 ( .A0(n4680), .A1(n4679), .B0(n3634), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]) );
NAND2X1TS U4291 ( .A(n4932), .B(n5023), .Y(n4931) );
NAND2X1TS U4292 ( .A(cont_iter_out[2]), .B(n4024), .Y(n4411) );
OAI21X1TS U4293 ( .A0(cont_iter_out[1]), .A1(n5057), .B0(n4577), .Y(n4481)
);
OAI211XLTS U4294 ( .A0(n4940), .A1(n5272), .B0(n4411), .C0(n4943), .Y(n2807)
);
INVX2TS U4295 ( .A(n3869), .Y(n3802) );
CLKBUFX3TS U4296 ( .A(n3911), .Y(n4994) );
CLKBUFX3TS U4297 ( .A(n4994), .Y(n3799) );
AOI22X1TS U4298 ( .A0(add_subt_module_intDX[15]), .A1(n5001), .B0(
add_subt_module_DmP[15]), .B1(n3799), .Y(n3293) );
OAI21XLTS U4299 ( .A0(n5093), .A1(n3802), .B0(n3293), .Y(n1786) );
NAND2X1TS U4300 ( .A(cont_var_out[0]), .B(n4928), .Y(n3930) );
AOI31XLTS U4301 ( .A0(n3294), .A1(n4928), .A2(n5068), .B0(cont_var_out[0]),
.Y(n3295) );
NOR3XLTS U4302 ( .A(n4940), .B(n4923), .C(n3295), .Y(n2926) );
CLKBUFX3TS U4303 ( .A(n3506), .Y(n4668) );
AOI22X1TS U4304 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(
n3296) );
OAI211XLTS U4305 ( .A0(n5211), .A1(n4666), .B0(n3296), .C0(n4664), .Y(n3297)
);
AOI21X1TS U4306 ( .A0(n4668), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n3297), .Y(n3321) );
INVX2TS U4307 ( .A(n4666), .Y(n3620) );
AOI22X1TS U4308 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B1(
n3529), .Y(n3299) );
AOI22X1TS U4309 ( .A0(n3562), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B1(
n3084), .Y(n3298) );
NAND3XLTS U4310 ( .A(n3299), .B(n3298), .C(n4664), .Y(n3318) );
AOI22X1TS U4311 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[24]),
.B0(n3566), .B1(n3318), .Y(n3300) );
OAI21XLTS U4312 ( .A0(n3321), .A1(n3306), .B0(n3300), .Y(n2559) );
AOI22X1TS U4313 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(
n3301) );
OAI211XLTS U4314 ( .A0(n4666), .A1(n5269), .B0(n3301), .C0(n4664), .Y(n3302)
);
AOI21X1TS U4315 ( .A0(n3622), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n3302), .Y(n3317) );
CLKBUFX3TS U4316 ( .A(n3084), .Y(n3695) );
AOI22X1TS U4317 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .Y(
n3304) );
AOI22X1TS U4318 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(
n3562), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(
n3303) );
NAND3XLTS U4319 ( .A(n3304), .B(n3303), .C(n4664), .Y(n3315) );
AOI22X1TS U4320 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[25]),
.B0(n3566), .B1(n3315), .Y(n3305) );
OAI21XLTS U4321 ( .A0(n3317), .A1(n3306), .B0(n3305), .Y(n2560) );
AOI22X1TS U4322 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(
n3307) );
OAI211XLTS U4323 ( .A0(n4666), .A1(n5148), .B0(n3307), .C0(n4664), .Y(n3308)
);
AOI21X1TS U4324 ( .A0(n3622), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n3308), .Y(n3314) );
AOI22X1TS U4325 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .Y(
n3310) );
AOI22X1TS U4326 ( .A0(n3622), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(
n3309) );
NAND3XLTS U4327 ( .A(n3310), .B(n3309), .C(n4664), .Y(n3312) );
AOI22X1TS U4328 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[26]),
.B0(n3566), .B1(n3312), .Y(n3311) );
OAI21XLTS U4329 ( .A0(n3314), .A1(n3306), .B0(n3311), .Y(n2561) );
AOI22X1TS U4330 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[28]),
.B0(n3596), .B1(n3312), .Y(n3313) );
OAI21XLTS U4331 ( .A0(n3314), .A1(n3320), .B0(n3313), .Y(n2563) );
AOI22X1TS U4332 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[29]),
.B0(n3569), .B1(n3315), .Y(n3316) );
OAI21XLTS U4333 ( .A0(n3317), .A1(n3320), .B0(n3316), .Y(n2564) );
AOI22X1TS U4334 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[30]),
.B0(n3596), .B1(n3318), .Y(n3319) );
OAI21XLTS U4335 ( .A0(n3321), .A1(n3320), .B0(n3319), .Y(n2565) );
AOI22X1TS U4336 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[31]),
.B0(n3569), .B1(n3322), .Y(n3323) );
OAI21XLTS U4337 ( .A0(n3324), .A1(n3320), .B0(n3323), .Y(n2566) );
INVX2TS U4338 ( .A(n4427), .Y(n4480) );
INVX2TS U4339 ( .A(n4479), .Y(n4477) );
OAI211XLTS U4340 ( .A0(n4940), .A1(n5271), .B0(n4943), .C0(n4477), .Y(n2819)
);
INVX2TS U4341 ( .A(n3933), .Y(n3325) );
NOR2X1TS U4342 ( .A(n3325), .B(n4154), .Y(n3326) );
NAND2X2TS U4343 ( .A(n3326), .B(sel_mux_3_reg), .Y(n3467) );
CLKBUFX2TS U4344 ( .A(n3467), .Y(n3588) );
CLKBUFX2TS U4345 ( .A(n3588), .Y(n3465) );
CLKBUFX3TS U4346 ( .A(n3465), .Y(n3898) );
INVX2TS U4347 ( .A(n3326), .Y(n3665) );
CLKBUFX2TS U4348 ( .A(n3665), .Y(n3449) );
CLKBUFX2TS U4349 ( .A(n3449), .Y(n3412) );
CLKBUFX2TS U4350 ( .A(n3449), .Y(n3895) );
CLKBUFX3TS U4351 ( .A(n3586), .Y(n3896) );
AOI22X1TS U4352 ( .A0(d_ff_Xn[1]), .A1(n3896), .B0(sign_inv_out[1]), .B1(
n3895), .Y(n3327) );
OAI21XLTS U4353 ( .A0(n5213), .A1(n3898), .B0(n3327), .Y(n2087) );
NOR2X1TS U4354 ( .A(n4427), .B(n4435), .Y(n4033) );
AOI21X1TS U4355 ( .A0(n2988), .A1(n5057), .B0(cont_iter_out[3]), .Y(n4945)
);
CLKBUFX3TS U4356 ( .A(n4349), .Y(n4507) );
AO21XLTS U4357 ( .A0(n4033), .A1(n4946), .B0(n4507), .Y(n3951) );
OAI211XLTS U4358 ( .A0(n4940), .A1(n5270), .B0(n3328), .C0(n3951), .Y(n2828)
);
CLKBUFX3TS U4359 ( .A(n3467), .Y(n3420) );
CLKBUFX3TS U4360 ( .A(n3440), .Y(n3418) );
CLKBUFX3TS U4361 ( .A(n3412), .Y(n3422) );
AOI22X1TS U4362 ( .A0(d_ff_Xn[16]), .A1(n3418), .B0(sign_inv_out[16]), .B1(
n3422), .Y(n3329) );
OAI21XLTS U4363 ( .A0(n5228), .A1(n3420), .B0(n3329), .Y(n2057) );
NAND2X2TS U4364 ( .A(n2969), .B(n5067), .Y(n1959) );
OAI22X1TS U4365 ( .A0(add_subt_module_Sgf_normalized_result[1]), .A1(
add_subt_module_Sgf_normalized_result[0]), .B0(r_mode[0]), .B1(
r_mode[1]), .Y(n3330) );
AOI221X1TS U4366 ( .A0(r_mode[1]), .A1(add_subt_module_sign_final_result),
.B0(r_mode[0]), .B1(n5105), .C0(n3330), .Y(n4142) );
INVX2TS U4367 ( .A(n4143), .Y(n3395) );
INVX2TS U4368 ( .A(n3331), .Y(n3337) );
NAND2X1TS U4369 ( .A(add_subt_module_intDX[1]), .B(n5086), .Y(n3335) );
NAND2X1TS U4370 ( .A(add_subt_module_intDX[7]), .B(n5032), .Y(n3333) );
NAND2X1TS U4371 ( .A(add_subt_module_intDY[12]), .B(n5031), .Y(n3332) );
NAND4XLTS U4372 ( .A(n3335), .B(n3334), .C(n3333), .D(n3332), .Y(n3336) );
AOI211X1TS U4373 ( .A0(add_subt_module_intDY[1]), .A1(n5073), .B0(n3337),
.C0(n3336), .Y(n3339) );
NAND2X1TS U4374 ( .A(add_subt_module_intDY[19]), .B(n5043), .Y(n3338) );
OAI211XLTS U4375 ( .A0(add_subt_module_intDX[62]), .A1(n5058), .B0(n3339),
.C0(n3338), .Y(n3350) );
INVX2TS U4376 ( .A(n3340), .Y(n3341) );
AOI21X1TS U4377 ( .A0(add_subt_module_intDX[8]), .A1(n5026), .B0(n3341), .Y(
n3343) );
OAI211XLTS U4378 ( .A0(add_subt_module_intDX[0]), .A1(n5061), .B0(n3343),
.C0(n3342), .Y(n3349) );
NAND4BXLTS U4379 ( .AN(n3347), .B(n3346), .C(n3345), .D(n3344), .Y(n3348) );
NOR4X1TS U4380 ( .A(n3351), .B(n3350), .C(n3349), .D(n3348), .Y(n3387) );
NOR4BBX1TS U4381 ( .AN(n3355), .BN(n3354), .C(n3353), .D(n3352), .Y(n3371)
);
NOR4BX1TS U4382 ( .AN(n3359), .B(n3358), .C(n3357), .D(n3356), .Y(n3370) );
NOR4X1TS U4383 ( .A(n3363), .B(n3362), .C(n3361), .D(n3360), .Y(n3369) );
NOR4BBX1TS U4384 ( .AN(n3367), .BN(n3366), .C(n3365), .D(n3364), .Y(n3368)
);
NAND4XLTS U4385 ( .A(n3371), .B(n3370), .C(n3369), .D(n3368), .Y(n3383) );
INVX2TS U4386 ( .A(n3372), .Y(n3373) );
AOI21X1TS U4387 ( .A0(add_subt_module_intDX[24]), .A1(n5013), .B0(n3373),
.Y(n3379) );
NOR4BX1TS U4388 ( .AN(n3377), .B(n3376), .C(n3375), .D(n3374), .Y(n3378) );
NAND4BXLTS U4389 ( .AN(n3381), .B(n3380), .C(n3379), .D(n3378), .Y(n3382) );
NOR4BX1TS U4390 ( .AN(n3385), .B(n3384), .C(n3383), .D(n3382), .Y(n3386) );
NAND4XLTS U4391 ( .A(n3389), .B(n3016), .C(n3387), .D(n3386), .Y(n4986) );
XOR2X1TS U4392 ( .A(add_subt_module_intAS), .B(add_subt_module_intDY[63]),
.Y(n4988) );
XNOR2X1TS U4393 ( .A(n4988), .B(add_subt_module_intDX[63]), .Y(n3918) );
NOR2X1TS U4394 ( .A(n4986), .B(n3918), .Y(n3478) );
CLKAND2X2TS U4395 ( .A(n3478), .B(n4991), .Y(n4920) );
NAND2X1TS U4396 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .Y(n4966) );
NOR4X1TS U4397 ( .A(n3480), .B(n4920), .C(n4973), .D(n4581), .Y(n3394) );
AND3X1TS U4398 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .C(n3945), .Y(n3956) );
NAND2X1TS U4399 ( .A(n3956), .B(n3391), .Y(n4497) );
OAI21X1TS U4400 ( .A0(n3392), .A1(n1959), .B0(n4497), .Y(n3481) );
OAI21XLTS U4401 ( .A0(n4502), .A1(n3481), .B0(
add_subt_module_FS_Module_state_reg[3]), .Y(n3393) );
OAI211XLTS U4402 ( .A0(n4142), .A1(n3395), .B0(n3394), .C0(n3393), .Y(n2930)
);
AOI22X1TS U4403 ( .A0(d_ff_Xn[9]), .A1(n3896), .B0(sign_inv_out[9]), .B1(
n3449), .Y(n3396) );
OAI21XLTS U4404 ( .A0(n5221), .A1(n3898), .B0(n3396), .Y(n2071) );
INVX2TS U4405 ( .A(n4791), .Y(n4789) );
CLKBUFX3TS U4406 ( .A(n3397), .Y(n4831) );
CLKBUFX3TS U4407 ( .A(n3291), .Y(n4849) );
AOI222X4TS U4408 ( .A0(n4767), .A1(add_subt_module_DmP[51]), .B0(
add_subt_module_Add_Subt_result[1]), .B1(n4873), .C0(
add_subt_module_Add_Subt_result[53]), .C1(n4849), .Y(n4676) );
INVX2TS U4409 ( .A(n4676), .Y(n3398) );
CLKBUFX2TS U4410 ( .A(n3289), .Y(n4811) );
AOI222X1TS U4411 ( .A0(n2960), .A1(n3633), .B0(n3399), .B1(n4831), .C0(n3398), .C1(n4811), .Y(n4684) );
OAI21XLTS U4412 ( .A0(n4684), .A1(n4679), .B0(n3634), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]) );
AOI22X1TS U4413 ( .A0(d_ff_Xn[6]), .A1(n3896), .B0(sign_inv_out[6]), .B1(
n3412), .Y(n3400) );
OAI21XLTS U4414 ( .A0(n5218), .A1(n3898), .B0(n3400), .Y(n2077) );
AOI22X1TS U4415 ( .A0(d_ff_Xn[5]), .A1(n3896), .B0(sign_inv_out[5]), .B1(
n3449), .Y(n3401) );
OAI21XLTS U4416 ( .A0(n5217), .A1(n3898), .B0(n3401), .Y(n2079) );
CLKBUFX3TS U4417 ( .A(n3467), .Y(n3434) );
CLKBUFX3TS U4418 ( .A(n3586), .Y(n3432) );
AOI22X1TS U4419 ( .A0(d_ff_Xn[20]), .A1(n3432), .B0(sign_inv_out[20]), .B1(
n3422), .Y(n3402) );
OAI21XLTS U4420 ( .A0(n5232), .A1(n3434), .B0(n3402), .Y(n2049) );
AOI22X1TS U4421 ( .A0(d_ff_Xn[13]), .A1(n3418), .B0(sign_inv_out[13]), .B1(
n3665), .Y(n3403) );
OAI21XLTS U4422 ( .A0(n5225), .A1(n3420), .B0(n3403), .Y(n2063) );
AOI22X1TS U4423 ( .A0(d_ff_Xn[10]), .A1(n3418), .B0(sign_inv_out[10]), .B1(
n3412), .Y(n3404) );
OAI21XLTS U4424 ( .A0(n5222), .A1(n3420), .B0(n3404), .Y(n2069) );
AOI22X1TS U4425 ( .A0(d_ff_Xn[7]), .A1(n3896), .B0(sign_inv_out[7]), .B1(
n3449), .Y(n3405) );
OAI21XLTS U4426 ( .A0(n5219), .A1(n3898), .B0(n3405), .Y(n2075) );
AOI22X1TS U4427 ( .A0(d_ff_Xn[12]), .A1(n3418), .B0(sign_inv_out[12]), .B1(
n3412), .Y(n3406) );
OAI21XLTS U4428 ( .A0(n5224), .A1(n3420), .B0(n3406), .Y(n2065) );
AOI22X1TS U4429 ( .A0(d_ff_Xn[11]), .A1(n3418), .B0(sign_inv_out[11]), .B1(
n3895), .Y(n3407) );
AOI22X1TS U4430 ( .A0(d_ff_Xn[8]), .A1(n3896), .B0(sign_inv_out[8]), .B1(
n3412), .Y(n3408) );
OAI21XLTS U4431 ( .A0(n5220), .A1(n3898), .B0(n3408), .Y(n2073) );
AOI22X1TS U4432 ( .A0(d_ff_Xn[19]), .A1(n3418), .B0(sign_inv_out[19]), .B1(
n3422), .Y(n3409) );
OAI21XLTS U4433 ( .A0(n5231), .A1(n3420), .B0(n3409), .Y(n2051) );
CLKBUFX3TS U4434 ( .A(n3588), .Y(n3445) );
CLKBUFX3TS U4435 ( .A(n3586), .Y(n3443) );
CLKBUFX3TS U4436 ( .A(n3449), .Y(n3447) );
AOI22X1TS U4437 ( .A0(d_ff_Xn[34]), .A1(n3443), .B0(sign_inv_out[34]), .B1(
n3447), .Y(n3410) );
OAI21XLTS U4438 ( .A0(n5245), .A1(n3445), .B0(n3410), .Y(n2021) );
AOI22X1TS U4439 ( .A0(d_ff_Xn[23]), .A1(n3432), .B0(sign_inv_out[23]), .B1(
n3422), .Y(n3411) );
OAI21XLTS U4440 ( .A0(n5235), .A1(n3434), .B0(n3411), .Y(n2043) );
CLKBUFX3TS U4441 ( .A(n3412), .Y(n3431) );
AOI22X1TS U4442 ( .A0(d_ff_Xn[30]), .A1(n3443), .B0(sign_inv_out[30]), .B1(
n3431), .Y(n3413) );
OAI21XLTS U4443 ( .A0(n5241), .A1(n3445), .B0(n3413), .Y(n2029) );
AOI22X1TS U4444 ( .A0(d_ff_Xn[15]), .A1(n3418), .B0(sign_inv_out[15]), .B1(
n3422), .Y(n3414) );
OAI21XLTS U4445 ( .A0(n5227), .A1(n3420), .B0(n3414), .Y(n2059) );
AOI22X1TS U4446 ( .A0(d_ff_Xn[14]), .A1(n3418), .B0(sign_inv_out[14]), .B1(
n3422), .Y(n3415) );
OAI21XLTS U4447 ( .A0(n5226), .A1(n3420), .B0(n3415), .Y(n2061) );
AOI22X1TS U4448 ( .A0(d_ff_Xn[21]), .A1(n3432), .B0(sign_inv_out[21]), .B1(
n3422), .Y(n3416) );
OAI21XLTS U4449 ( .A0(n5233), .A1(n3434), .B0(n3416), .Y(n2047) );
AOI22X1TS U4450 ( .A0(d_ff_Xn[18]), .A1(n3418), .B0(sign_inv_out[18]), .B1(
n3422), .Y(n3417) );
OAI21XLTS U4451 ( .A0(n5230), .A1(n3420), .B0(n3417), .Y(n2053) );
AOI22X1TS U4452 ( .A0(d_ff_Xn[17]), .A1(n3418), .B0(sign_inv_out[17]), .B1(
n3422), .Y(n3419) );
OAI21XLTS U4453 ( .A0(n5229), .A1(n3420), .B0(n3419), .Y(n2055) );
AOI22X1TS U4454 ( .A0(d_ff_Xn[24]), .A1(n3432), .B0(sign_inv_out[24]), .B1(
n3431), .Y(n3421) );
OAI21XLTS U4455 ( .A0(n5236), .A1(n3434), .B0(n3421), .Y(n2041) );
AOI22X1TS U4456 ( .A0(d_ff_Xn[22]), .A1(n3432), .B0(sign_inv_out[22]), .B1(
n3422), .Y(n3423) );
OAI21XLTS U4457 ( .A0(n5234), .A1(n3434), .B0(n3423), .Y(n2045) );
AOI22X1TS U4458 ( .A0(d_ff_Xn[26]), .A1(n3432), .B0(sign_inv_out[26]), .B1(
n3431), .Y(n3424) );
OAI21XLTS U4459 ( .A0(n5237), .A1(n3434), .B0(n3424), .Y(n2037) );
AOI22X1TS U4460 ( .A0(d_ff_Xn[28]), .A1(n3432), .B0(sign_inv_out[28]), .B1(
n3431), .Y(n3425) );
OAI21XLTS U4461 ( .A0(n5239), .A1(n3434), .B0(n3425), .Y(n2033) );
AOI22X1TS U4462 ( .A0(d_ff_Xn[32]), .A1(n3443), .B0(sign_inv_out[32]), .B1(
n3431), .Y(n3426) );
AOI22X1TS U4463 ( .A0(d_ff_Xn[33]), .A1(n3443), .B0(sign_inv_out[33]), .B1(
n3431), .Y(n3427) );
OAI21XLTS U4464 ( .A0(n5244), .A1(n3445), .B0(n3427), .Y(n2023) );
AOI22X1TS U4465 ( .A0(d_ff_Xn[25]), .A1(n3432), .B0(sign_inv_out[25]), .B1(
n3431), .Y(n3428) );
OAI21XLTS U4466 ( .A0(n5110), .A1(n3434), .B0(n3428), .Y(n2039) );
AOI22X1TS U4467 ( .A0(d_ff_Xn[29]), .A1(n3432), .B0(sign_inv_out[29]), .B1(
n3431), .Y(n3429) );
OAI21XLTS U4468 ( .A0(n5240), .A1(n3434), .B0(n3429), .Y(n2031) );
AOI22X1TS U4469 ( .A0(d_ff_Xn[31]), .A1(n3443), .B0(sign_inv_out[31]), .B1(
n3431), .Y(n3430) );
OAI21XLTS U4470 ( .A0(n5242), .A1(n3445), .B0(n3430), .Y(n2027) );
AOI22X1TS U4471 ( .A0(d_ff_Xn[27]), .A1(n3432), .B0(sign_inv_out[27]), .B1(
n3431), .Y(n3433) );
OAI21XLTS U4472 ( .A0(n5238), .A1(n3434), .B0(n3433), .Y(n2035) );
AOI22X1TS U4473 ( .A0(d_ff_Xn[36]), .A1(n3443), .B0(sign_inv_out[36]), .B1(
n3447), .Y(n3435) );
OAI21XLTS U4474 ( .A0(n5247), .A1(n3445), .B0(n3435), .Y(n2017) );
AOI22X1TS U4475 ( .A0(d_ff_Xn[35]), .A1(n3443), .B0(sign_inv_out[35]), .B1(
n3447), .Y(n3436) );
OAI21XLTS U4476 ( .A0(n5246), .A1(n3445), .B0(n3436), .Y(n2019) );
AOI22X1TS U4477 ( .A0(d_ff_Xn[39]), .A1(n3443), .B0(sign_inv_out[39]), .B1(
n3447), .Y(n3437) );
OAI21XLTS U4478 ( .A0(n5250), .A1(n3445), .B0(n3437), .Y(n2011) );
AOI22X1TS U4479 ( .A0(d_ff_Xn[37]), .A1(n3443), .B0(sign_inv_out[37]), .B1(
n3447), .Y(n3438) );
OAI21XLTS U4480 ( .A0(n5248), .A1(n3445), .B0(n3438), .Y(n2015) );
AOI22X1TS U4481 ( .A0(d_ff_Xn[3]), .A1(n3896), .B0(sign_inv_out[3]), .B1(
n3895), .Y(n3439) );
OAI21XLTS U4482 ( .A0(n5215), .A1(n3898), .B0(n3439), .Y(n2083) );
CLKBUFX3TS U4483 ( .A(n3588), .Y(n3457) );
CLKBUFX3TS U4484 ( .A(n3440), .Y(n3455) );
AOI22X1TS U4485 ( .A0(d_ff_Xn[41]), .A1(n3455), .B0(sign_inv_out[41]), .B1(
n3447), .Y(n3441) );
OAI21XLTS U4486 ( .A0(n5252), .A1(n3457), .B0(n3441), .Y(n2007) );
AOI22X1TS U4487 ( .A0(d_ff_Xn[42]), .A1(n3455), .B0(sign_inv_out[42]), .B1(
n3447), .Y(n3442) );
OAI21XLTS U4488 ( .A0(n5253), .A1(n3457), .B0(n3442), .Y(n2005) );
AOI22X1TS U4489 ( .A0(d_ff_Xn[38]), .A1(n3443), .B0(sign_inv_out[38]), .B1(
n3447), .Y(n3444) );
OAI21XLTS U4490 ( .A0(n5249), .A1(n3445), .B0(n3444), .Y(n2013) );
AOI22X1TS U4491 ( .A0(d_ff_Xn[40]), .A1(n3455), .B0(sign_inv_out[40]), .B1(
n3447), .Y(n3446) );
OAI21XLTS U4492 ( .A0(n5251), .A1(n3457), .B0(n3446), .Y(n2009) );
AOI22X1TS U4493 ( .A0(d_ff_Xn[43]), .A1(n3455), .B0(sign_inv_out[43]), .B1(
n3447), .Y(n3448) );
OAI21XLTS U4494 ( .A0(n5254), .A1(n3457), .B0(n3448), .Y(n2003) );
CLKBUFX3TS U4495 ( .A(n3449), .Y(n3886) );
AOI22X1TS U4496 ( .A0(d_ff_Xn[45]), .A1(n3455), .B0(sign_inv_out[45]), .B1(
n3886), .Y(n3450) );
AOI22X1TS U4497 ( .A0(d_ff_Xn[44]), .A1(n3455), .B0(sign_inv_out[44]), .B1(
n3886), .Y(n3451) );
OAI21XLTS U4498 ( .A0(n5255), .A1(n3457), .B0(n3451), .Y(n2001) );
AOI22X1TS U4499 ( .A0(d_ff_Xn[46]), .A1(n3455), .B0(sign_inv_out[46]), .B1(
n3886), .Y(n3452) );
OAI21XLTS U4500 ( .A0(n5257), .A1(n3457), .B0(n3452), .Y(n1997) );
AOI22X1TS U4501 ( .A0(d_ff_Xn[49]), .A1(n3455), .B0(sign_inv_out[49]), .B1(
n3886), .Y(n3453) );
OAI21XLTS U4502 ( .A0(n5260), .A1(n3457), .B0(n3453), .Y(n1991) );
AOI22X1TS U4503 ( .A0(d_ff_Xn[47]), .A1(n3455), .B0(sign_inv_out[47]), .B1(
n3886), .Y(n3454) );
OAI21XLTS U4504 ( .A0(n5258), .A1(n3457), .B0(n3454), .Y(n1995) );
AOI22X1TS U4505 ( .A0(d_ff_Xn[48]), .A1(n3455), .B0(sign_inv_out[48]), .B1(
n3886), .Y(n3456) );
OAI21XLTS U4506 ( .A0(n5259), .A1(n3457), .B0(n3456), .Y(n1993) );
CLKBUFX2TS U4507 ( .A(n3586), .Y(n3666) );
AOI22X1TS U4508 ( .A0(d_ff_Xn[52]), .A1(n3666), .B0(sign_inv_out[52]), .B1(
n3886), .Y(n3458) );
OAI21XLTS U4509 ( .A0(n5089), .A1(n3465), .B0(n3458), .Y(n1985) );
AOI22X1TS U4510 ( .A0(d_ff_Xn[53]), .A1(n3440), .B0(sign_inv_out[53]), .B1(
n3886), .Y(n3459) );
OAI21XLTS U4511 ( .A0(n5263), .A1(n3467), .B0(n3459), .Y(n1983) );
CLKBUFX2TS U4512 ( .A(n3665), .Y(n3469) );
AOI22X1TS U4513 ( .A0(d_ff_Xn[54]), .A1(n3586), .B0(sign_inv_out[54]), .B1(
n3469), .Y(n3460) );
OAI21XLTS U4514 ( .A0(n5264), .A1(n3588), .B0(n3460), .Y(n1981) );
AOI22X1TS U4515 ( .A0(d_ff_Xn[55]), .A1(n3586), .B0(sign_inv_out[55]), .B1(
n3469), .Y(n3461) );
OAI21XLTS U4516 ( .A0(n5265), .A1(n3465), .B0(n3461), .Y(n1979) );
AOI22X1TS U4517 ( .A0(d_ff_Xn[56]), .A1(n3440), .B0(sign_inv_out[56]), .B1(
n3665), .Y(n3462) );
OAI21XLTS U4518 ( .A0(n5140), .A1(n3467), .B0(n3462), .Y(n1977) );
AOI22X1TS U4519 ( .A0(d_ff_Xn[57]), .A1(n3586), .B0(sign_inv_out[57]), .B1(
n3469), .Y(n3463) );
OAI21XLTS U4520 ( .A0(n5266), .A1(n3465), .B0(n3463), .Y(n1975) );
AOI22X1TS U4521 ( .A0(d_ff_Xn[58]), .A1(n3666), .B0(sign_inv_out[58]), .B1(
n3469), .Y(n3464) );
OAI21XLTS U4522 ( .A0(n5090), .A1(n3465), .B0(n3464), .Y(n1973) );
AOI22X1TS U4523 ( .A0(d_ff_Xn[59]), .A1(n3586), .B0(sign_inv_out[59]), .B1(
n3469), .Y(n3466) );
OAI21XLTS U4524 ( .A0(n5267), .A1(n3467), .B0(n3466), .Y(n1971) );
AOI22X1TS U4525 ( .A0(d_ff_Xn[60]), .A1(n3666), .B0(sign_inv_out[60]), .B1(
n3469), .Y(n3468) );
OAI21XLTS U4526 ( .A0(n5091), .A1(n3588), .B0(n3468), .Y(n1969) );
AOI22X1TS U4527 ( .A0(d_ff_Xn[61]), .A1(n3666), .B0(sign_inv_out[61]), .B1(
n3469), .Y(n3470) );
AOI22X1TS U4528 ( .A0(d_ff_Xn[62]), .A1(n3666), .B0(sign_inv_out[62]), .B1(
n3665), .Y(n3471) );
OAI21XLTS U4529 ( .A0(n5141), .A1(n3465), .B0(n3471), .Y(n1965) );
CLKBUFX2TS U4530 ( .A(n3729), .Y(n3883) );
AOI22X1TS U4531 ( .A0(add_subt_module_intDY[55]), .A1(n3889), .B0(
add_subt_module_DmP[55]), .B1(n3881), .Y(n3472) );
OAI21XLTS U4532 ( .A0(n5028), .A1(n3910), .B0(n3472), .Y(n1920) );
CLKBUFX2TS U4533 ( .A(n3889), .Y(n4996) );
INVX2TS U4534 ( .A(n4996), .Y(n3904) );
AOI22X1TS U4535 ( .A0(add_subt_module_intDX[56]), .A1(n3805), .B0(
add_subt_module_DmP[56]), .B1(n3881), .Y(n3473) );
OAI21XLTS U4536 ( .A0(n5038), .A1(n3904), .B0(n3473), .Y(n1923) );
AOI22X1TS U4537 ( .A0(add_subt_module_intDX[57]), .A1(n5001), .B0(
add_subt_module_DmP[57]), .B1(n3881), .Y(n3474) );
OAI21XLTS U4538 ( .A0(n5081), .A1(n3904), .B0(n3474), .Y(n1926) );
AOI22X1TS U4539 ( .A0(n3506), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(
n3476) );
AOI22X1TS U4540 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .Y(
n3475) );
OAI211X1TS U4541 ( .A0(n3699), .A1(n3554), .B0(n3476), .C0(n3475), .Y(n3617)
);
AOI22X1TS U4542 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[2]),
.B0(n3705), .B1(n3617), .Y(n3477) );
OAI21XLTS U4543 ( .A0(n3619), .A1(n3019), .B0(n3477), .Y(n2537) );
NOR4X1TS U4544 ( .A(n3480), .B(n2969), .C(n4143), .D(n3479), .Y(n3482) );
NOR2XLTS U4545 ( .A(n3482), .B(n3481), .Y(n2929) );
AO22XLTS U4546 ( .A0(n3559), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n2990), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(
n3483) );
AOI22X1TS U4547 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(
n3485) );
AOI22X1TS U4548 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]), .Y(
n3484) );
OAI211X1TS U4549 ( .A0(n3521), .A1(n3573), .B0(n3485), .C0(n3484), .Y(n3614)
);
AOI22X1TS U4550 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[3]),
.B0(n3705), .B1(n3614), .Y(n3486) );
OAI21XLTS U4551 ( .A0(n3616), .A1(n3020), .B0(n3486), .Y(n2538) );
AO22XLTS U4552 ( .A0(n3559), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(
n2990), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(
n3487) );
AOI22X1TS U4553 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .Y(
n3489) );
AOI22X1TS U4554 ( .A0(n3506), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(
n3488) );
OAI211X1TS U4555 ( .A0(n3521), .A1(n3576), .B0(n3489), .C0(n3488), .Y(n3611)
);
AOI22X1TS U4556 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[4]),
.B0(n3705), .B1(n3611), .Y(n3490) );
OAI21XLTS U4557 ( .A0(n3613), .A1(n3021), .B0(n3490), .Y(n2539) );
AO22XLTS U4558 ( .A0(n2989), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n3559), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .Y(
n3491) );
AOI22X1TS U4559 ( .A0(n3622), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .Y(
n3493) );
AOI22X1TS U4560 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(
n3492) );
OAI211X1TS U4561 ( .A0(n3521), .A1(n3579), .B0(n3493), .C0(n3492), .Y(n3606)
);
AOI22X1TS U4562 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[5]),
.B0(n3705), .B1(n3606), .Y(n3494) );
OAI21XLTS U4563 ( .A0(n3609), .A1(n3019), .B0(n3494), .Y(n2540) );
AO22XLTS U4564 ( .A0(n2990), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .B1(
n3559), .Y(n3495) );
AOI22X1TS U4565 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(
n3497) );
AOI22X1TS U4566 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]), .Y(
n3496) );
OAI211X1TS U4567 ( .A0(n3521), .A1(n3582), .B0(n3497), .C0(n3496), .Y(n3603)
);
AOI22X1TS U4568 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[6]),
.B0(n3705), .B1(n3603), .Y(n3498) );
OAI21XLTS U4569 ( .A0(n3605), .A1(n3020), .B0(n3498), .Y(n2541) );
OAI2BB1X1TS U4570 ( .A0N(n2990), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n3515), .Y(n3499) );
AOI22X1TS U4571 ( .A0(n3506), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(
n3501) );
AOI22X1TS U4572 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .Y(
n3500) );
OAI211X1TS U4573 ( .A0(n3521), .A1(n3001), .B0(n3501), .C0(n3500), .Y(n3601)
);
AOI22X1TS U4574 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[7]),
.B0(n3705), .B1(n3601), .Y(n3502) );
OAI21XLTS U4575 ( .A0(n2976), .A1(n3021), .B0(n3502), .Y(n2542) );
OAI2BB1X1TS U4576 ( .A0N(n3075), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
n3515), .Y(n3503) );
OAI2BB1X1TS U4577 ( .A0N(n2990), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(
n3515), .Y(n3504) );
AOI22X1TS U4578 ( .A0(n3506), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B1(
n3694), .Y(n3508) );
AOI22X1TS U4579 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .B1(
n3084), .Y(n3507) );
OAI211X1TS U4580 ( .A0(n3521), .A1(n3000), .B0(n3508), .C0(n3507), .Y(n3598)
);
AOI22X1TS U4581 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[8]),
.B0(n3705), .B1(n3598), .Y(n3509) );
OAI21XLTS U4582 ( .A0(n3600), .A1(n3019), .B0(n3509), .Y(n2543) );
AOI22X1TS U4583 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[9]),
.B0(n3705), .B1(n3510), .Y(n3511) );
OAI21XLTS U4584 ( .A0(n3527), .A1(n3020), .B0(n3511), .Y(n2544) );
AOI22X1TS U4585 ( .A0(n3622), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(
n3513) );
AOI22X1TS U4586 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(
n3512) );
OAI211X1TS U4587 ( .A0(n3521), .A1(n2970), .B0(n3513), .C0(n3512), .Y(n3595)
);
AOI22X1TS U4588 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[10]),
.B0(n3549), .B1(n3595), .Y(n3514) );
OAI21XLTS U4589 ( .A0(n2997), .A1(n3021), .B0(n3514), .Y(n2545) );
OAI21XLTS U4590 ( .A0(n3516), .A1(n5149), .B0(n3515), .Y(n3517) );
AOI22X1TS U4591 ( .A0(n3518), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .Y(
n3520) );
AOI22X1TS U4592 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(
n3519) );
OAI211X1TS U4593 ( .A0(n3521), .A1(n2999), .B0(n3520), .C0(n3519), .Y(n3593)
);
AOI22X1TS U4594 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[11]),
.B0(n3549), .B1(n3593), .Y(n3522) );
OAI21XLTS U4595 ( .A0(n2999), .A1(n3019), .B0(n3522), .Y(n2546) );
AOI22X1TS U4596 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[12]),
.B0(n3549), .B1(n3523), .Y(n3524) );
OAI21XLTS U4597 ( .A0(n2970), .A1(n3020), .B0(n3524), .Y(n2547) );
AOI22X1TS U4598 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .Y(
n3526) );
AOI22X1TS U4599 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(
n3525) );
OAI211X1TS U4600 ( .A0(n3565), .A1(n3527), .B0(n3526), .C0(n3525), .Y(n3591)
);
AOI22X1TS U4601 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[13]),
.B0(n3549), .B1(n3591), .Y(n3528) );
OAI21XLTS U4602 ( .A0(n2998), .A1(n3021), .B0(n3528), .Y(n2548) );
AOI22X1TS U4603 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(
n3531) );
AOI22X1TS U4604 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .Y(
n3530) );
OAI211X1TS U4605 ( .A0(n3565), .A1(n3600), .B0(n3531), .C0(n3530), .Y(n3589)
);
AOI22X1TS U4606 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[14]),
.B0(n3549), .B1(n3589), .Y(n3532) );
OAI21XLTS U4607 ( .A0(n3000), .A1(n3019), .B0(n3532), .Y(n2549) );
AOI22X1TS U4608 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(
n3534) );
AOI22X1TS U4609 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .Y(
n3533) );
OAI211X1TS U4610 ( .A0(n3565), .A1(n2976), .B0(n3534), .C0(n3533), .Y(n3583)
);
AOI22X1TS U4611 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[15]),
.B0(n3549), .B1(n3583), .Y(n3535) );
OAI21XLTS U4612 ( .A0(n3001), .A1(n3020), .B0(n3535), .Y(n2550) );
AOI22X1TS U4613 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n3562), .B0(n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(
n3537) );
AOI22X1TS U4614 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B1(
n3620), .Y(n3536) );
OAI211X1TS U4615 ( .A0(n3565), .A1(n3605), .B0(n3537), .C0(n3536), .Y(n3580)
);
AOI22X1TS U4616 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[16]),
.B0(n3549), .B1(n3580), .Y(n3538) );
OAI21XLTS U4617 ( .A0(n3582), .A1(n3021), .B0(n3538), .Y(n2551) );
AOI22X1TS U4618 ( .A0(n3562), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(
n3540) );
AOI22X1TS U4619 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(
n3539) );
OAI211X1TS U4620 ( .A0(n3565), .A1(n3609), .B0(n3540), .C0(n3539), .Y(n3577)
);
AOI22X1TS U4621 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[17]),
.B0(n3549), .B1(n3577), .Y(n3541) );
OAI21XLTS U4622 ( .A0(n3579), .A1(n3019), .B0(n3541), .Y(n2552) );
AOI22X1TS U4623 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(
n3543) );
AOI22X1TS U4624 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(
n3542) );
OAI211X1TS U4625 ( .A0(n3565), .A1(n3613), .B0(n3543), .C0(n3542), .Y(n3574)
);
AOI22X1TS U4626 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[18]),
.B0(n3549), .B1(n3574), .Y(n3544) );
AOI22X1TS U4627 ( .A0(n3562), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n3529), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(
n3548) );
AOI22X1TS U4628 ( .A0(n3546), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(
n3545), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(
n3547) );
OAI211X1TS U4629 ( .A0(n3565), .A1(n3616), .B0(n3548), .C0(n3547), .Y(n3571)
);
AOI22X1TS U4630 ( .A0(n3550), .A1(add_subt_module_Sgf_normalized_result[19]),
.B0(n3549), .B1(n3571), .Y(n3551) );
OAI21XLTS U4631 ( .A0(n3573), .A1(n3020), .B0(n3551), .Y(n2554) );
AOI22X1TS U4632 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[20]),
.B0(n3566), .B1(n3552), .Y(n3553) );
OAI21XLTS U4633 ( .A0(n3554), .A1(n3021), .B0(n3553), .Y(n2555) );
AOI22X1TS U4634 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[21]),
.B0(n3566), .B1(n3555), .Y(n3556) );
OAI21XLTS U4635 ( .A0(n3625), .A1(n3019), .B0(n3556), .Y(n2556) );
AO22XLTS U4636 ( .A0(n3561), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
n2990), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(
n3557) );
AOI22X1TS U4637 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(
n3564) );
AOI22X1TS U4638 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(
n3562), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(
n3563) );
OAI211X1TS U4639 ( .A0(n3565), .A1(n2977), .B0(n3564), .C0(n3563), .Y(n3568)
);
AOI22X1TS U4640 ( .A0(n3700), .A1(add_subt_module_Sgf_normalized_result[22]),
.B0(n3566), .B1(n3568), .Y(n3567) );
OAI21XLTS U4641 ( .A0(n3698), .A1(n3020), .B0(n3567), .Y(n2557) );
AOI22X1TS U4642 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[32]),
.B0(n3596), .B1(n3568), .Y(n3570) );
OAI211XLTS U4643 ( .A0(n3698), .A1(n3011), .B0(n3570), .C0(n3022), .Y(n2567)
);
AOI22X1TS U4644 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[35]),
.B0(n3569), .B1(n3571), .Y(n3572) );
OAI211XLTS U4645 ( .A0(n3573), .A1(n3011), .B0(n3572), .C0(n3023), .Y(n2570)
);
AOI22X1TS U4646 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[36]),
.B0(n3596), .B1(n3574), .Y(n3575) );
OAI211XLTS U4647 ( .A0(n3576), .A1(n3012), .B0(n3575), .C0(n3024), .Y(n2571)
);
AOI22X1TS U4648 ( .A0(n3584), .A1(add_subt_module_Sgf_normalized_result[37]),
.B0(n3569), .B1(n3577), .Y(n3578) );
OAI211XLTS U4649 ( .A0(n3579), .A1(n3013), .B0(n3578), .C0(n3022), .Y(n2572)
);
AOI22X1TS U4650 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[38]),
.B0(n3596), .B1(n3580), .Y(n3581) );
OAI211XLTS U4651 ( .A0(n3582), .A1(n3012), .B0(n3581), .C0(n3023), .Y(n2573)
);
AOI22X1TS U4652 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[39]),
.B0(n3569), .B1(n3583), .Y(n3585) );
OAI211XLTS U4653 ( .A0(n3001), .A1(n3013), .B0(n3585), .C0(n3024), .Y(n2574)
);
AOI22X1TS U4654 ( .A0(d_ff_Xn[50]), .A1(n3586), .B0(sign_inv_out[50]), .B1(
n3886), .Y(n3587) );
OAI21XLTS U4655 ( .A0(n5261), .A1(n3588), .B0(n3587), .Y(n1989) );
AOI22X1TS U4656 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[40]),
.B0(n3596), .B1(n3589), .Y(n3590) );
AOI22X1TS U4657 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[41]),
.B0(n3569), .B1(n3591), .Y(n3592) );
OAI211XLTS U4658 ( .A0(n2998), .A1(n3012), .B0(n3592), .C0(n3022), .Y(n2576)
);
AOI22X1TS U4659 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[43]),
.B0(n3596), .B1(n3593), .Y(n3594) );
OAI211XLTS U4660 ( .A0(n2999), .A1(n3013), .B0(n3594), .C0(n3023), .Y(n2578)
);
AOI22X1TS U4661 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[44]),
.B0(n3569), .B1(n3595), .Y(n3597) );
OAI211XLTS U4662 ( .A0(n2997), .A1(n3012), .B0(n3597), .C0(n3024), .Y(n2579)
);
AOI22X1TS U4663 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[46]),
.B0(n3780), .B1(n3598), .Y(n3599) );
OAI211XLTS U4664 ( .A0(n3600), .A1(n3013), .B0(n3599), .C0(n3022), .Y(n2581)
);
AOI22X1TS U4665 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[47]),
.B0(n3780), .B1(n3601), .Y(n3602) );
OAI211XLTS U4666 ( .A0(n2976), .A1(n3012), .B0(n3602), .C0(n3023), .Y(n2582)
);
AOI22X1TS U4667 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[48]),
.B0(n3780), .B1(n3603), .Y(n3604) );
OAI211XLTS U4668 ( .A0(n3605), .A1(n3013), .B0(n3604), .C0(n3024), .Y(n2583)
);
AOI22X1TS U4669 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[49]),
.B0(n3780), .B1(n3606), .Y(n3608) );
OAI211XLTS U4670 ( .A0(n3609), .A1(n3012), .B0(n3608), .C0(n3022), .Y(n2584)
);
INVX2TS U4671 ( .A(n3610), .Y(n1946) );
AOI22X1TS U4672 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[50]),
.B0(n3780), .B1(n3611), .Y(n3612) );
OAI211XLTS U4673 ( .A0(n3613), .A1(n3013), .B0(n3612), .C0(n3023), .Y(n2585)
);
AOI22X1TS U4674 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[51]),
.B0(n3780), .B1(n3614), .Y(n3615) );
OAI211XLTS U4675 ( .A0(n3616), .A1(n3012), .B0(n3615), .C0(n3024), .Y(n2586)
);
AOI22X1TS U4676 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[52]),
.B0(n3780), .B1(n3617), .Y(n3618) );
AOI22X1TS U4677 ( .A0(n3621), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(
n3694), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(
n3624) );
AOI22X1TS U4678 ( .A0(n3622), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .Y(
n3623) );
OAI211X1TS U4679 ( .A0(n3699), .A1(n3625), .B0(n3624), .C0(n3623), .Y(n3704)
);
AOI22X1TS U4680 ( .A0(n3781), .A1(add_subt_module_Sgf_normalized_result[53]),
.B0(n3780), .B1(n3704), .Y(n3626) );
OAI211XLTS U4681 ( .A0(n3708), .A1(n3013), .B0(n3626), .C0(n3022), .Y(n2588)
);
INVX2TS U4682 ( .A(n3291), .Y(n4864) );
CLKBUFX3TS U4683 ( .A(add_subt_module_FSM_selector_C), .Y(n4865) );
OAI222X4TS U4684 ( .A0(n4864), .A1(add_subt_module_Add_Subt_result[51]),
.B0(n4880), .B1(add_subt_module_Add_Subt_result[3]), .C0(
add_subt_module_DmP[49]), .C1(n4865), .Y(n4685) );
OAI22X1TS U4685 ( .A0(n4676), .A1(n4776), .B0(n4883), .B1(n4685), .Y(n3629)
);
AOI222X4TS U4686 ( .A0(n4767), .A1(add_subt_module_DmP[50]), .B0(
add_subt_module_Add_Subt_result[2]), .B1(n4698), .C0(
add_subt_module_Add_Subt_result[52]), .C1(n4711), .Y(n4681) );
INVX2TS U4687 ( .A(n2993), .Y(n4826) );
CLKBUFX2TS U4688 ( .A(n4826), .Y(n3627) );
CLKBUFX3TS U4689 ( .A(n3627), .Y(n4777) );
OAI22X1TS U4690 ( .A0(n4681), .A1(n4861), .B0(n4777), .B1(n3630), .Y(n3628)
);
NOR2X1TS U4691 ( .A(n3629), .B(n3628), .Y(n4692) );
OAI21XLTS U4692 ( .A0(n4692), .A1(n4679), .B0(n3634), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]) );
OAI22X1TS U4693 ( .A0(n4676), .A1(n4888), .B0(n4776), .B1(n3630), .Y(n3631)
);
AOI211X1TS U4694 ( .A0(n3633), .A1(n2993), .B0(n3632), .C0(n3631), .Y(n4688)
);
OAI21XLTS U4695 ( .A0(n4688), .A1(n4679), .B0(n3634), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]) );
INVX2TS U4696 ( .A(n3635), .Y(n3834) );
CLKBUFX2TS U4697 ( .A(n3636), .Y(n3842) );
CLKBUFX3TS U4698 ( .A(n3842), .Y(n3764) );
INVX2TS U4699 ( .A(n3637), .Y(n2248) );
INVX2TS U4700 ( .A(n4298), .Y(n3843) );
CLKBUFX3TS U4701 ( .A(n3636), .Y(n3821) );
INVX2TS U4702 ( .A(n4311), .Y(n3836) );
INVX2TS U4703 ( .A(n3638), .Y(n2257) );
INVX2TS U4704 ( .A(n3639), .Y(n2253) );
AOI222X1TS U4705 ( .A0(n3848), .A1(d_ff2_Z[21]), .B0(n3821), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n3832), .Y(n3640) );
INVX2TS U4706 ( .A(n3640), .Y(n2263) );
INVX2TS U4707 ( .A(n3641), .Y(n2251) );
CLKBUFX3TS U4708 ( .A(n3842), .Y(n3828) );
AOI222X1TS U4709 ( .A0(n3852), .A1(d_ff2_Z[17]), .B0(n3828), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n3836), .Y(n3642) );
INVX2TS U4710 ( .A(n3642), .Y(n2267) );
AOI222X1TS U4711 ( .A0(n3840), .A1(d_ff2_Z[32]), .B0(n3764), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n3832), .Y(n3643) );
INVX2TS U4712 ( .A(n3643), .Y(n2252) );
INVX2TS U4713 ( .A(n3644), .Y(n2260) );
AOI222X1TS U4714 ( .A0(n3852), .A1(d_ff2_Z[22]), .B0(n3821), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n3854), .Y(n3645) );
INVX2TS U4715 ( .A(n3645), .Y(n2262) );
INVX2TS U4716 ( .A(n3646), .Y(n2256) );
AOI222X1TS U4717 ( .A0(n3848), .A1(d_ff2_Z[26]), .B0(n3821), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n3846), .Y(n3647) );
INVX2TS U4718 ( .A(n3647), .Y(n2258) );
CLKBUFX3TS U4719 ( .A(n3889), .Y(n3893) );
CLKBUFX3TS U4720 ( .A(n3873), .Y(n3808) );
AOI22X1TS U4721 ( .A0(add_subt_module_intDY[12]), .A1(n3893), .B0(
add_subt_module_DmP[12]), .B1(n3808), .Y(n3648) );
OAI21XLTS U4722 ( .A0(n5031), .A1(n3871), .B0(n3648), .Y(n1827) );
INVX2TS U4723 ( .A(n3869), .Y(n3810) );
CLKBUFX3TS U4724 ( .A(n4994), .Y(n3803) );
AOI22X1TS U4725 ( .A0(add_subt_module_intDX[11]), .A1(n3812), .B0(
add_subt_module_DmP[11]), .B1(n3803), .Y(n3649) );
OAI21XLTS U4726 ( .A0(n5129), .A1(n3810), .B0(n3649), .Y(n1824) );
INVX2TS U4727 ( .A(n4996), .Y(n3913) );
AOI22X1TS U4728 ( .A0(add_subt_module_intDX[49]), .A1(n3812), .B0(
add_subt_module_DmP[49]), .B1(n3911), .Y(n3650) );
OAI21XLTS U4729 ( .A0(n5112), .A1(n3913), .B0(n3650), .Y(n1879) );
INVX2TS U4730 ( .A(n4996), .Y(n3814) );
AOI22X1TS U4731 ( .A0(add_subt_module_intDX[9]), .A1(n3797), .B0(
add_subt_module_DmP[9]), .B1(n5000), .Y(n3651) );
OAI21XLTS U4732 ( .A0(n5113), .A1(n3814), .B0(n3651), .Y(n1868) );
AOI22X1TS U4733 ( .A0(add_subt_module_intDX[5]), .A1(n3792), .B0(
add_subt_module_DmP[5]), .B1(n5000), .Y(n3652) );
OAI21XLTS U4734 ( .A0(n5033), .A1(n3814), .B0(n3652), .Y(n1858) );
AOI22X1TS U4735 ( .A0(add_subt_module_intDX[45]), .A1(n4998), .B0(
add_subt_module_DmP[45]), .B1(n5000), .Y(n3653) );
OAI21XLTS U4736 ( .A0(n5041), .A1(n3814), .B0(n3653), .Y(n1855) );
AOI22X1TS U4737 ( .A0(add_subt_module_intDX[13]), .A1(n4992), .B0(
add_subt_module_DmP[13]), .B1(n3808), .Y(n3654) );
OAI21XLTS U4738 ( .A0(n5076), .A1(n3810), .B0(n3654), .Y(n1848) );
AOI22X1TS U4739 ( .A0(add_subt_module_intDX[41]), .A1(n3797), .B0(
add_subt_module_DmP[41]), .B1(n3803), .Y(n3655) );
OAI21XLTS U4740 ( .A0(n5051), .A1(n3802), .B0(n3655), .Y(n1814) );
AOI22X1TS U4741 ( .A0(add_subt_module_intDX[37]), .A1(n3805), .B0(
add_subt_module_DmP[37]), .B1(n3803), .Y(n3656) );
INVX2TS U4742 ( .A(n3869), .Y(n3795) );
CLKBUFX3TS U4743 ( .A(n3732), .Y(n3791) );
AOI22X1TS U4744 ( .A0(add_subt_module_intDX[29]), .A1(n3797), .B0(
add_subt_module_DmP[29]), .B1(n3791), .Y(n3657) );
OAI21XLTS U4745 ( .A0(n5098), .A1(n3795), .B0(n3657), .Y(n1768) );
AOI22X1TS U4746 ( .A0(add_subt_module_intDX[21]), .A1(n3805), .B0(
add_subt_module_DmP[21]), .B1(n3791), .Y(n3658) );
OAI21XLTS U4747 ( .A0(n5121), .A1(n3795), .B0(n3658), .Y(n1764) );
CLKBUFX3TS U4748 ( .A(n3732), .Y(n3788) );
AOI22X1TS U4749 ( .A0(add_subt_module_intDY[33]), .A1(n3893), .B0(
add_subt_module_DmP[33]), .B1(n3788), .Y(n3659) );
OAI21XLTS U4750 ( .A0(n5017), .A1(n3729), .B0(n3659), .Y(n1754) );
INVX2TS U4751 ( .A(n3872), .Y(n3726) );
AOI22X1TS U4752 ( .A0(add_subt_module_intDX[17]), .A1(n5001), .B0(
add_subt_module_DmP[17]), .B1(n3788), .Y(n3660) );
OAI21XLTS U4753 ( .A0(n5014), .A1(n3726), .B0(n3660), .Y(n1750) );
INVX2TS U4754 ( .A(n3729), .Y(n3786) );
AOI22X1TS U4755 ( .A0(add_subt_module_intDX[24]), .A1(n3915), .B0(
add_subt_module_DmP[24]), .B1(n3788), .Y(n3661) );
OAI21XLTS U4756 ( .A0(n5013), .A1(n3726), .B0(n3661), .Y(n1743) );
CLKBUFX3TS U4757 ( .A(n4996), .Y(n3908) );
AOI22X1TS U4758 ( .A0(add_subt_module_intDY[26]), .A1(n3908), .B0(
add_subt_module_DmP[26]), .B1(n3788), .Y(n3662) );
OAI21XLTS U4759 ( .A0(n5022), .A1(n3729), .B0(n3662), .Y(n1733) );
INVX2TS U4760 ( .A(n4192), .Y(n3663) );
INVX2TS U4761 ( .A(n3664), .Y(n2847) );
AOI22X1TS U4762 ( .A0(d_ff_Xn[63]), .A1(n3666), .B0(data_output2_63_), .B1(
n3665), .Y(n3667) );
OAI21XLTS U4763 ( .A0(n5111), .A1(n3588), .B0(n3667), .Y(n1963) );
INVX2TS U4764 ( .A(n4311), .Y(n3854) );
AOI222X1TS U4765 ( .A0(n3840), .A1(d_ff2_Z[35]), .B0(n3764), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n3854), .Y(n3668) );
INVX2TS U4766 ( .A(n3668), .Y(n2249) );
AOI22X1TS U4767 ( .A0(add_subt_module_intDY[2]), .A1(n3869), .B0(
add_subt_module_DmP[2]), .B1(n3911), .Y(n3669) );
OAI21XLTS U4768 ( .A0(n5063), .A1(n3883), .B0(n3669), .Y(n1895) );
AOI22X1TS U4769 ( .A0(add_subt_module_intDX[1]), .A1(n3805), .B0(
add_subt_module_DmP[1]), .B1(n4994), .Y(n3670) );
OAI21XLTS U4770 ( .A0(n5086), .A1(n3913), .B0(n3670), .Y(n1882) );
AOI22X1TS U4771 ( .A0(add_subt_module_intDX[19]), .A1(n3792), .B0(
add_subt_module_DmP[19]), .B1(n3799), .Y(n3671) );
AOI22X1TS U4772 ( .A0(add_subt_module_intDX[23]), .A1(n4998), .B0(
add_subt_module_DmP[23]), .B1(n3799), .Y(n3672) );
OAI21XLTS U4773 ( .A0(n5130), .A1(n3802), .B0(n3672), .Y(n1796) );
AOI22X1TS U4774 ( .A0(add_subt_module_intDX[27]), .A1(n4992), .B0(
add_subt_module_DmP[27]), .B1(n3791), .Y(n3673) );
OAI21XLTS U4775 ( .A0(n5094), .A1(n3795), .B0(n3673), .Y(n1776) );
AOI22X1TS U4776 ( .A0(add_subt_module_intDX[18]), .A1(n3792), .B0(
add_subt_module_DmP[18]), .B1(n3791), .Y(n3674) );
OAI21XLTS U4777 ( .A0(n5122), .A1(n3795), .B0(n3674), .Y(n1761) );
AOI22X1TS U4778 ( .A0(add_subt_module_intDX[25]), .A1(n4998), .B0(
add_subt_module_DmP[25]), .B1(n3791), .Y(n3675) );
OAI21XLTS U4779 ( .A0(n5123), .A1(n3726), .B0(n3675), .Y(n1758) );
AOI22X1TS U4780 ( .A0(add_subt_module_intDY[22]), .A1(n3908), .B0(
add_subt_module_DmP[22]), .B1(n3788), .Y(n3676) );
OAI21XLTS U4781 ( .A0(n5018), .A1(n3910), .B0(n3676), .Y(n1740) );
AOI22X1TS U4782 ( .A0(add_subt_module_intDX[28]), .A1(n5005), .B0(
add_subt_module_DmP[28]), .B1(n3788), .Y(n3677) );
OAI21XLTS U4783 ( .A0(n5021), .A1(n3726), .B0(n3677), .Y(n1737) );
AOI22X1TS U4784 ( .A0(add_subt_module_intDX[0]), .A1(n4998), .B0(
add_subt_module_DmP[0]), .B1(n4994), .Y(n3678) );
OAI21XLTS U4785 ( .A0(n5061), .A1(n3913), .B0(n3678), .Y(n1908) );
AOI22X1TS U4786 ( .A0(add_subt_module_intDX[4]), .A1(n4992), .B0(
add_subt_module_DmP[4]), .B1(n4997), .Y(n3679) );
OAI21XLTS U4787 ( .A0(n5065), .A1(n3913), .B0(n3679), .Y(n1902) );
AOI22X1TS U4788 ( .A0(add_subt_module_intDY[3]), .A1(n3889), .B0(
add_subt_module_DmP[3]), .B1(n3881), .Y(n3680) );
OAI21XLTS U4789 ( .A0(n5027), .A1(n3910), .B0(n3680), .Y(n1885) );
AOI22X1TS U4790 ( .A0(add_subt_module_intDX[16]), .A1(n5001), .B0(
add_subt_module_DmP[16]), .B1(n5000), .Y(n3681) );
AOI22X1TS U4791 ( .A0(add_subt_module_intDX[6]), .A1(n3812), .B0(
add_subt_module_DmP[6]), .B1(n5000), .Y(n3682) );
OAI21XLTS U4792 ( .A0(n5071), .A1(n3814), .B0(n3682), .Y(n1861) );
AOI22X1TS U4793 ( .A0(add_subt_module_intDX[20]), .A1(n3797), .B0(
add_subt_module_DmP[20]), .B1(n5000), .Y(n3683) );
OAI21XLTS U4794 ( .A0(n5042), .A1(n3814), .B0(n3683), .Y(n1851) );
AOI22X1TS U4795 ( .A0(add_subt_module_intDY[10]), .A1(n3869), .B0(
add_subt_module_DmP[10]), .B1(n3808), .Y(n3684) );
OAI21XLTS U4796 ( .A0(n5037), .A1(n3871), .B0(n3684), .Y(n1845) );
AOI22X1TS U4797 ( .A0(add_subt_module_intDX[7]), .A1(n3805), .B0(
add_subt_module_DmP[7]), .B1(n3808), .Y(n3685) );
OAI21XLTS U4798 ( .A0(n5032), .A1(n3810), .B0(n3685), .Y(n1838) );
AOI22X1TS U4799 ( .A0(add_subt_module_intDX[8]), .A1(n5001), .B0(
add_subt_module_DmP[8]), .B1(n3803), .Y(n3686) );
OAI21XLTS U4800 ( .A0(n5026), .A1(n3810), .B0(n3686), .Y(n1817) );
AOI22X1TS U4801 ( .A0(add_subt_module_intDX[14]), .A1(n3812), .B0(
add_subt_module_DmP[14]), .B1(n3799), .Y(n3687) );
OAI21XLTS U4802 ( .A0(n5019), .A1(n3795), .B0(n3687), .Y(n1779) );
AOI22X1TS U4803 ( .A0(add_subt_module_intDX[48]), .A1(n3872), .B0(
add_subt_module_DMP[48]), .B1(n3911), .Y(n3688) );
OAI21XLTS U4804 ( .A0(n5029), .A1(n3729), .B0(n3688), .Y(n1898) );
AOI22X1TS U4805 ( .A0(add_subt_module_intDY[47]), .A1(n3792), .B0(
add_subt_module_DMP[47]), .B1(n3911), .Y(n3689) );
OAI21XLTS U4806 ( .A0(n5030), .A1(n3913), .B0(n3689), .Y(n1888) );
AOI22X1TS U4807 ( .A0(add_subt_module_intDY[49]), .A1(n4998), .B0(
add_subt_module_DMP[49]), .B1(n3732), .Y(n3690) );
OAI21XLTS U4808 ( .A0(n5097), .A1(n3814), .B0(n3690), .Y(n1878) );
AOI22X1TS U4809 ( .A0(add_subt_module_intDY[46]), .A1(n4992), .B0(
add_subt_module_DMP[46]), .B1(n5000), .Y(n3691) );
OAI21XLTS U4810 ( .A0(n5127), .A1(n3814), .B0(n3691), .Y(n1874) );
AOI22X1TS U4811 ( .A0(add_subt_module_intDX[43]), .A1(n3893), .B0(
add_subt_module_DMP[43]), .B1(n3808), .Y(n3692) );
OAI21XLTS U4812 ( .A0(n5034), .A1(n3729), .B0(n3692), .Y(n1841) );
AOI22X1TS U4813 ( .A0(add_subt_module_intDY[40]), .A1(n5001), .B0(
add_subt_module_DMP[40]), .B1(n3808), .Y(n3693) );
AOI22X1TS U4814 ( .A0(n3695), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(
n3620), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(
n3697) );
AOI22X1TS U4815 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .B0(
n4668), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]), .Y(
n3696) );
OAI211X1TS U4816 ( .A0(n3699), .A1(n3698), .B0(n3697), .C0(n3696), .Y(n3779)
);
AOI22X1TS U4817 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[0]),
.B0(n3705), .B1(n3779), .Y(n3701) );
AOI22X1TS U4818 ( .A0(add_subt_module_intDX[38]), .A1(n3893), .B0(
add_subt_module_DMP[38]), .B1(n3808), .Y(n3702) );
OAI21XLTS U4819 ( .A0(n5015), .A1(n3883), .B0(n3702), .Y(n1830) );
AOI22X1TS U4820 ( .A0(add_subt_module_intDY[42]), .A1(n3792), .B0(
add_subt_module_DMP[42]), .B1(n3803), .Y(n3703) );
OAI21XLTS U4821 ( .A0(n5050), .A1(n3810), .B0(n3703), .Y(n1820) );
AOI22X1TS U4822 ( .A0(n4669), .A1(add_subt_module_Sgf_normalized_result[1]),
.B0(n3705), .B1(n3704), .Y(n3706) );
AOI22X1TS U4823 ( .A0(add_subt_module_intDY[41]), .A1(n4998), .B0(
add_subt_module_DMP[41]), .B1(n3803), .Y(n3709) );
OAI21XLTS U4824 ( .A0(n5116), .A1(n3802), .B0(n3709), .Y(n1813) );
AOI22X1TS U4825 ( .A0(add_subt_module_intDX[37]), .A1(n3893), .B0(
add_subt_module_DMP[37]), .B1(n3803), .Y(n3710) );
OAI21XLTS U4826 ( .A0(n5035), .A1(n3871), .B0(n3710), .Y(n1806) );
AOI22X1TS U4827 ( .A0(add_subt_module_intDY[39]), .A1(n4992), .B0(
add_subt_module_DMP[39]), .B1(n3803), .Y(n3711) );
OAI21XLTS U4828 ( .A0(n5143), .A1(n3802), .B0(n3711), .Y(n1805) );
AOI22X1TS U4829 ( .A0(add_subt_module_intDY[35]), .A1(n3797), .B0(
add_subt_module_DMP[35]), .B1(n3799), .Y(n3712) );
OAI21XLTS U4830 ( .A0(n5016), .A1(n3802), .B0(n3712), .Y(n1789) );
AOI22X1TS U4831 ( .A0(add_subt_module_intDY[36]), .A1(n3805), .B0(
add_subt_module_DMP[36]), .B1(n3799), .Y(n3713) );
OAI21XLTS U4832 ( .A0(n5120), .A1(n3795), .B0(n3713), .Y(n1782) );
AOI22X1TS U4833 ( .A0(add_subt_module_intDY[27]), .A1(n5001), .B0(
add_subt_module_DMP[27]), .B1(n3791), .Y(n3714) );
OAI21XLTS U4834 ( .A0(n5095), .A1(n3795), .B0(n3714), .Y(n1775) );
AOI22X1TS U4835 ( .A0(add_subt_module_intDX[31]), .A1(n3893), .B0(
add_subt_module_DMP[31]), .B1(n3791), .Y(n3715) );
OAI21XLTS U4836 ( .A0(n5012), .A1(n3883), .B0(n3715), .Y(n1771) );
AOI22X1TS U4837 ( .A0(add_subt_module_intDY[29]), .A1(n4992), .B0(
add_subt_module_DMP[29]), .B1(n3791), .Y(n3716) );
OAI21XLTS U4838 ( .A0(n5052), .A1(n3795), .B0(n3716), .Y(n1767) );
AOI22X1TS U4839 ( .A0(add_subt_module_intDY[25]), .A1(n3812), .B0(
add_subt_module_DMP[25]), .B1(n3791), .Y(n3717) );
OAI21XLTS U4840 ( .A0(n5099), .A1(n3726), .B0(n3717), .Y(n1757) );
AOI22X1TS U4841 ( .A0(add_subt_module_intDY[33]), .A1(n3797), .B0(
add_subt_module_DMP[33]), .B1(n3788), .Y(n3718) );
OAI21XLTS U4842 ( .A0(n5017), .A1(n3726), .B0(n3718), .Y(n1753) );
AOI22X1TS U4843 ( .A0(add_subt_module_intDY[32]), .A1(n3805), .B0(
add_subt_module_DMP[32]), .B1(n3788), .Y(n3719) );
OAI21XLTS U4844 ( .A0(n5066), .A1(n3726), .B0(n3719), .Y(n1746) );
AOI22X1TS U4845 ( .A0(add_subt_module_intDX[28]), .A1(n3908), .B0(
add_subt_module_DMP[28]), .B1(n3788), .Y(n3720) );
OAI21XLTS U4846 ( .A0(n5021), .A1(n3871), .B0(n3720), .Y(n1736) );
AOI22X1TS U4847 ( .A0(add_subt_module_intDY[26]), .A1(n3786), .B0(
add_subt_module_DMP[26]), .B1(n3784), .Y(n3721) );
AOI22X1TS U4848 ( .A0(add_subt_module_intDY[22]), .A1(n3915), .B0(
add_subt_module_DMP[22]), .B1(n3784), .Y(n3722) );
OAI21XLTS U4849 ( .A0(n5018), .A1(n3726), .B0(n3722), .Y(n1731) );
AOI22X1TS U4850 ( .A0(add_subt_module_intDX[24]), .A1(n3908), .B0(
add_subt_module_DMP[24]), .B1(n3784), .Y(n3723) );
OAI21XLTS U4851 ( .A0(n5013), .A1(n3871), .B0(n3723), .Y(n1730) );
AOI22X1TS U4852 ( .A0(add_subt_module_intDX[17]), .A1(n3908), .B0(
add_subt_module_DMP[17]), .B1(n3784), .Y(n3724) );
OAI21XLTS U4853 ( .A0(n5014), .A1(n3871), .B0(n3724), .Y(n1729) );
AOI22X1TS U4854 ( .A0(add_subt_module_intDY[18]), .A1(n5005), .B0(
add_subt_module_DMP[18]), .B1(n3784), .Y(n3725) );
OAI21XLTS U4855 ( .A0(n5124), .A1(n3726), .B0(n3725), .Y(n1728) );
INVX2TS U4856 ( .A(n3872), .Y(n3907) );
AOI22X1TS U4857 ( .A0(add_subt_module_intDY[21]), .A1(n3786), .B0(
add_subt_module_DMP[21]), .B1(n3900), .Y(n3727) );
OAI21XLTS U4858 ( .A0(n5125), .A1(n3907), .B0(n3727), .Y(n1727) );
AOI22X1TS U4859 ( .A0(add_subt_module_intDX[14]), .A1(n3908), .B0(
add_subt_module_DMP[14]), .B1(n3784), .Y(n3728) );
OAI21XLTS U4860 ( .A0(n5019), .A1(n3729), .B0(n3728), .Y(n1726) );
AOI22X1TS U4861 ( .A0(add_subt_module_intDY[15]), .A1(n3915), .B0(
add_subt_module_DMP[15]), .B1(n3900), .Y(n3730) );
OAI21XLTS U4862 ( .A0(n5077), .A1(n3907), .B0(n3730), .Y(n1725) );
AOI22X1TS U4863 ( .A0(add_subt_module_intDY[30]), .A1(n5005), .B0(
add_subt_module_DMP[30]), .B1(n3784), .Y(n3731) );
AOI22X1TS U4864 ( .A0(add_subt_module_intDY[52]), .A1(n3812), .B0(
add_subt_module_DMP[52]), .B1(n3732), .Y(n3733) );
OAI21XLTS U4865 ( .A0(n5020), .A1(n3913), .B0(n3733), .Y(n1910) );
AOI222X1TS U4866 ( .A0(n4248), .A1(d_ff2_Z[55]), .B0(n3842), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n3846), .Y(n3734) );
INVX2TS U4867 ( .A(n3734), .Y(n2229) );
INVX2TS U4868 ( .A(n3735), .Y(n2230) );
INVX2TS U4869 ( .A(n3736), .Y(n2231) );
CLKBUFX2TS U4870 ( .A(n3842), .Y(n3855) );
INVX2TS U4871 ( .A(n3737), .Y(n2232) );
CLKBUFX3TS U4872 ( .A(n3855), .Y(n3839) );
AOI222X1TS U4873 ( .A0(n3852), .A1(d_ff2_Z[0]), .B0(n3839), .B1(d_ff1_Z[0]),
.C0(d_ff_Zn[0]), .C1(n3851), .Y(n3738) );
INVX2TS U4874 ( .A(n3738), .Y(n2284) );
INVX2TS U4875 ( .A(n3739), .Y(n2233) );
CLKBUFX3TS U4876 ( .A(n3842), .Y(n3833) );
INVX2TS U4877 ( .A(n3740), .Y(n2236) );
AOI222X1TS U4878 ( .A0(n3848), .A1(d_ff2_Z[47]), .B0(n3833), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n3851), .Y(n3741) );
INVX2TS U4879 ( .A(n3741), .Y(n2237) );
AOI222X1TS U4880 ( .A0(n3848), .A1(d_ff2_Z[3]), .B0(n3839), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n3832), .Y(n3742) );
INVX2TS U4881 ( .A(n3742), .Y(n2281) );
AOI222X1TS U4882 ( .A0(n3852), .A1(d_ff2_Z[1]), .B0(n3839), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n3836), .Y(n3743) );
INVX2TS U4883 ( .A(n3743), .Y(n2283) );
INVX2TS U4884 ( .A(n3744), .Y(n2235) );
INVX2TS U4885 ( .A(n4100), .Y(n3846) );
AOI222X1TS U4886 ( .A0(n3852), .A1(d_ff2_Z[16]), .B0(n3828), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n3836), .Y(n3745) );
INVX2TS U4887 ( .A(n3745), .Y(n2268) );
AOI222X1TS U4888 ( .A0(n3848), .A1(d_ff2_Z[44]), .B0(n3833), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n3832), .Y(n3746) );
INVX2TS U4889 ( .A(n3746), .Y(n2240) );
INVX2TS U4890 ( .A(n4983), .Y(n4101) );
INVX2TS U4891 ( .A(n3747), .Y(n2279) );
INVX2TS U4892 ( .A(n3748), .Y(n2239) );
AOI222X1TS U4893 ( .A0(n3848), .A1(d_ff2_Z[20]), .B0(n3821), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n3832), .Y(n3749) );
INVX2TS U4894 ( .A(n3749), .Y(n2264) );
INVX2TS U4895 ( .A(n3750), .Y(n2241) );
AOI222X1TS U4896 ( .A0(n3840), .A1(d_ff2_Z[7]), .B0(n3839), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n3832), .Y(n3751) );
INVX2TS U4897 ( .A(n3751), .Y(n2277) );
INVX2TS U4898 ( .A(n3752), .Y(n2244) );
AOI222X1TS U4899 ( .A0(n3852), .A1(d_ff2_Z[38]), .B0(n3764), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n3854), .Y(n3753) );
INVX2TS U4900 ( .A(n3753), .Y(n2246) );
AOI222X1TS U4901 ( .A0(n3840), .A1(d_ff2_Z[12]), .B0(n3828), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n3832), .Y(n3754) );
INVX2TS U4902 ( .A(n3754), .Y(n2272) );
INVX2TS U4903 ( .A(n3755), .Y(n2273) );
INVX2TS U4904 ( .A(n3756), .Y(n2276) );
INVX2TS U4905 ( .A(n3757), .Y(n2243) );
INVX2TS U4906 ( .A(n3758), .Y(n2245) );
INVX2TS U4907 ( .A(n3759), .Y(n2247) );
INVX2TS U4908 ( .A(n3760), .Y(n2265) );
INVX2TS U4909 ( .A(n3761), .Y(n2250) );
INVX2TS U4910 ( .A(n3762), .Y(n2261) );
INVX2TS U4911 ( .A(n3765), .Y(n2254) );
INVX2TS U4912 ( .A(n3766), .Y(n3772) );
NAND4XLTS U4913 ( .A(add_subt_module_Exp_Operation_Module_Data_S[3]), .B(
add_subt_module_Exp_Operation_Module_Data_S[2]), .C(
add_subt_module_Exp_Operation_Module_Data_S[0]), .D(
add_subt_module_Exp_Operation_Module_Data_S[1]), .Y(n3771) );
AND4X1TS U4914 ( .A(add_subt_module_Exp_Operation_Module_Data_S[9]), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .C(
add_subt_module_Exp_Operation_Module_Data_S[4]), .D(
add_subt_module_Exp_Operation_Module_Data_S[6]), .Y(n3767) );
NAND4XLTS U4915 ( .A(n3768), .B(
add_subt_module_Exp_Operation_Module_Data_S[8]), .C(
add_subt_module_Exp_Operation_Module_Data_S[7]), .D(n3767), .Y(n3770)
);
NAND2X1TS U4916 ( .A(n4301), .B(overflow_flag), .Y(n3769) );
OAI31X1TS U4917 ( .A0(n3772), .A1(n3771), .A2(n3770), .B0(n3769), .Y(n2651)
);
NAND2X1TS U4918 ( .A(n3933), .B(n3773), .Y(n3777) );
OAI21XLTS U4919 ( .A0(d_ff1_operation_out), .A1(
d_ff1_shift_region_flag_out[0]), .B0(n3774), .Y(n3775) );
XOR2X1TS U4920 ( .A(d_ff1_shift_region_flag_out[1]), .B(n3775), .Y(n3931) );
NAND3XLTS U4921 ( .A(sel_mux_3_reg), .B(n5529), .C(n3777), .Y(n3776) );
OAI21XLTS U4922 ( .A0(n3777), .A1(n3931), .B0(n3776), .Y(n2667) );
INVX2TS U4923 ( .A(n3778), .Y(n2221) );
AOI22X1TS U4924 ( .A0(n3607), .A1(add_subt_module_Sgf_normalized_result[54]),
.B0(n3569), .B1(n3779), .Y(n3783) );
OAI211XLTS U4925 ( .A0(n2977), .A1(n3012), .B0(n3783), .C0(n3023), .Y(n2937)
);
CLKBUFX3TS U4926 ( .A(n3784), .Y(n5003) );
AOI22X1TS U4927 ( .A0(add_subt_module_intDY[34]), .A1(n3786), .B0(
add_subt_module_DMP[34]), .B1(n5003), .Y(n3785) );
OAI21XLTS U4928 ( .A0(n5062), .A1(n3907), .B0(n3785), .Y(n1722) );
AOI22X1TS U4929 ( .A0(add_subt_module_intDY[23]), .A1(n3915), .B0(
add_subt_module_DMP[23]), .B1(n3900), .Y(n3787) );
OAI21XLTS U4930 ( .A0(n5078), .A1(n3907), .B0(n3787), .Y(n1723) );
AOI22X1TS U4931 ( .A0(add_subt_module_intDY[32]), .A1(n3893), .B0(
add_subt_module_DmP[32]), .B1(n3788), .Y(n3789) );
AOI22X1TS U4932 ( .A0(add_subt_module_intDX[31]), .A1(n5001), .B0(
add_subt_module_DmP[31]), .B1(n3791), .Y(n3793) );
OAI21XLTS U4933 ( .A0(n5012), .A1(n3795), .B0(n3793), .Y(n1772) );
AOI22X1TS U4934 ( .A0(add_subt_module_intDX[36]), .A1(n3792), .B0(
add_subt_module_DmP[36]), .B1(n3799), .Y(n3794) );
OAI21XLTS U4935 ( .A0(n5119), .A1(n3795), .B0(n3794), .Y(n1783) );
AOI22X1TS U4936 ( .A0(add_subt_module_intDY[35]), .A1(n3893), .B0(
add_subt_module_DmP[35]), .B1(n3799), .Y(n3796) );
OAI21XLTS U4937 ( .A0(n5016), .A1(n3729), .B0(n3796), .Y(n1790) );
AOI22X1TS U4938 ( .A0(add_subt_module_intDX[30]), .A1(n4998), .B0(
add_subt_module_DmP[30]), .B1(n3799), .Y(n3798) );
OAI21XLTS U4939 ( .A0(n5118), .A1(n3802), .B0(n3798), .Y(n1793) );
AOI22X1TS U4940 ( .A0(add_subt_module_intDY[34]), .A1(n3893), .B0(
add_subt_module_DmP[34]), .B1(n3799), .Y(n3800) );
OAI21XLTS U4941 ( .A0(n5062), .A1(n3883), .B0(n3800), .Y(n1799) );
AOI22X1TS U4942 ( .A0(add_subt_module_intDX[39]), .A1(n3812), .B0(
add_subt_module_DmP[39]), .B1(n3803), .Y(n3801) );
OAI21XLTS U4943 ( .A0(n5074), .A1(n3802), .B0(n3801), .Y(n1810) );
AOI22X1TS U4944 ( .A0(add_subt_module_intDX[42]), .A1(n3797), .B0(
add_subt_module_DmP[42]), .B1(n3803), .Y(n3804) );
OAI21XLTS U4945 ( .A0(n5115), .A1(n3810), .B0(n3804), .Y(n1821) );
AOI22X1TS U4946 ( .A0(add_subt_module_intDX[38]), .A1(n3805), .B0(
add_subt_module_DmP[38]), .B1(n3808), .Y(n3806) );
OAI21XLTS U4947 ( .A0(n5015), .A1(n3810), .B0(n3806), .Y(n1831) );
AOI22X1TS U4948 ( .A0(add_subt_module_intDX[40]), .A1(n3792), .B0(
add_subt_module_DmP[40]), .B1(n3808), .Y(n3807) );
OAI21XLTS U4949 ( .A0(n5114), .A1(n3810), .B0(n3807), .Y(n1835) );
AOI22X1TS U4950 ( .A0(add_subt_module_intDX[43]), .A1(n4998), .B0(
add_subt_module_DmP[43]), .B1(n3808), .Y(n3809) );
OAI21XLTS U4951 ( .A0(n5034), .A1(n3810), .B0(n3809), .Y(n1842) );
AOI22X1TS U4952 ( .A0(add_subt_module_intDX[44]), .A1(n3812), .B0(
add_subt_module_DmP[44]), .B1(n5000), .Y(n3811) );
OAI21XLTS U4953 ( .A0(n5070), .A1(n3814), .B0(n3811), .Y(n1865) );
AOI22X1TS U4954 ( .A0(add_subt_module_intDX[46]), .A1(n3797), .B0(
add_subt_module_DmP[46]), .B1(n4994), .Y(n3813) );
OAI21XLTS U4955 ( .A0(n5092), .A1(n3814), .B0(n3813), .Y(n1875) );
AOI22X1TS U4956 ( .A0(add_subt_module_intDY[47]), .A1(n4996), .B0(
add_subt_module_DmP[47]), .B1(n4994), .Y(n3815) );
AOI22X1TS U4957 ( .A0(add_subt_module_intDX[50]), .A1(n3797), .B0(
add_subt_module_DmP[50]), .B1(n4997), .Y(n3816) );
OAI21XLTS U4958 ( .A0(n5039), .A1(n3913), .B0(n3816), .Y(n1892) );
AOI22X1TS U4959 ( .A0(add_subt_module_intDX[48]), .A1(n3805), .B0(
add_subt_module_DmP[48]), .B1(n4994), .Y(n3817) );
OAI21XLTS U4960 ( .A0(n5029), .A1(n3913), .B0(n3817), .Y(n1899) );
AOI22X1TS U4961 ( .A0(add_subt_module_intDX[51]), .A1(n5001), .B0(
add_subt_module_DmP[51]), .B1(n3911), .Y(n3818) );
OAI21XLTS U4962 ( .A0(n5082), .A1(n3913), .B0(n3818), .Y(n1905) );
INVX2TS U4963 ( .A(n3819), .Y(n2259) );
AOI222X1TS U4964 ( .A0(n3848), .A1(d_ff2_Z[18]), .B0(n3828), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n3846), .Y(n3820) );
INVX2TS U4965 ( .A(n3820), .Y(n2266) );
AOI222X1TS U4966 ( .A0(n3840), .A1(d_ff2_Z[29]), .B0(n3821), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n3832), .Y(n3822) );
INVX2TS U4967 ( .A(n3822), .Y(n2255) );
AOI222X1TS U4968 ( .A0(n3852), .A1(d_ff2_Z[14]), .B0(n3828), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n3851), .Y(n3823) );
INVX2TS U4969 ( .A(n3823), .Y(n2270) );
AOI222X1TS U4970 ( .A0(n3852), .A1(d_ff2_Z[15]), .B0(n3828), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n3836), .Y(n3824) );
INVX2TS U4971 ( .A(n3824), .Y(n2269) );
INVX2TS U4972 ( .A(n3871), .Y(n5005) );
AOI22X1TS U4973 ( .A0(add_subt_module_intDY[19]), .A1(n5005), .B0(
add_subt_module_DMP[19]), .B1(n5003), .Y(n3825) );
OAI21XLTS U4974 ( .A0(n5043), .A1(n3907), .B0(n3825), .Y(n1721) );
INVX2TS U4975 ( .A(n3826), .Y(n2242) );
AOI222X1TS U4976 ( .A0(n3840), .A1(d_ff2_Z[10]), .B0(n3828), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n3854), .Y(n3827) );
INVX2TS U4977 ( .A(n3827), .Y(n2274) );
AOI222X1TS U4978 ( .A0(n3840), .A1(d_ff2_Z[13]), .B0(n3828), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n4312), .Y(n3829) );
INVX2TS U4979 ( .A(n3829), .Y(n2271) );
AOI222X1TS U4980 ( .A0(n3840), .A1(d_ff2_Z[6]), .B0(n3839), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n3846), .Y(n3830) );
INVX2TS U4981 ( .A(n3830), .Y(n2278) );
AOI222X1TS U4982 ( .A0(n3840), .A1(d_ff2_Z[9]), .B0(n3839), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n3836), .Y(n3831) );
INVX2TS U4983 ( .A(n3831), .Y(n2275) );
INVX2TS U4984 ( .A(n3835), .Y(n2238) );
AOI222X1TS U4985 ( .A0(n3848), .A1(d_ff2_Z[50]), .B0(n3636), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n4312), .Y(n3837) );
INVX2TS U4986 ( .A(n3837), .Y(n2234) );
INVX2TS U4987 ( .A(n3838), .Y(n2282) );
AOI222X1TS U4988 ( .A0(n3840), .A1(d_ff2_Z[4]), .B0(n3839), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n3854), .Y(n3841) );
INVX2TS U4989 ( .A(n3841), .Y(n2280) );
INVX2TS U4990 ( .A(n3844), .Y(n2228) );
INVX2TS U4991 ( .A(n3845), .Y(n2227) );
INVX2TS U4992 ( .A(n3847), .Y(n2226) );
AOI222X1TS U4993 ( .A0(n3852), .A1(d_ff2_Z[59]), .B0(n3636), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n3851), .Y(n3849) );
INVX2TS U4994 ( .A(n3849), .Y(n2225) );
INVX2TS U4995 ( .A(n3850), .Y(n2224) );
INVX2TS U4996 ( .A(n3853), .Y(n2223) );
INVX2TS U4997 ( .A(n3856), .Y(n2222) );
AOI211X2TS U4998 ( .A0(n4366), .A1(n4961), .B0(n4032), .C0(n3857), .Y(n4579)
);
NAND2X1TS U4999 ( .A(n4367), .B(n4961), .Y(n4358) );
NOR2XLTS U5000 ( .A(n4940), .B(d_ff3_LUT_out[55]), .Y(n3858) );
AOI22X1TS U5001 ( .A0(add_subt_module_intDY[58]), .A1(n3869), .B0(
add_subt_module_DmP[58]), .B1(n3881), .Y(n3859) );
OAI21XLTS U5002 ( .A0(n5047), .A1(n3729), .B0(n3859), .Y(n1929) );
AOI22X1TS U5003 ( .A0(add_subt_module_intDX[59]), .A1(n3792), .B0(
add_subt_module_DmP[59]), .B1(n3732), .Y(n3860) );
OAI21XLTS U5004 ( .A0(n5036), .A1(n3904), .B0(n3860), .Y(n1932) );
AOI22X1TS U5005 ( .A0(add_subt_module_intDY[52]), .A1(n3869), .B0(
add_subt_module_DmP[52]), .B1(n4994), .Y(n3861) );
OAI21XLTS U5006 ( .A0(n5020), .A1(n3871), .B0(n3861), .Y(n1911) );
AOI22X1TS U5007 ( .A0(add_subt_module_intDX[60]), .A1(n4992), .B0(
add_subt_module_DmP[60]), .B1(n4997), .Y(n3862) );
OAI21XLTS U5008 ( .A0(n5059), .A1(n3904), .B0(n3862), .Y(n1935) );
AOI22X1TS U5009 ( .A0(add_subt_module_intDX[61]), .A1(n4998), .B0(
add_subt_module_DmP[61]), .B1(n3873), .Y(n3863) );
OAI21XLTS U5010 ( .A0(n5025), .A1(n3904), .B0(n3863), .Y(n1938) );
AOI22X1TS U5011 ( .A0(add_subt_module_intDX[62]), .A1(n3812), .B0(
add_subt_module_DmP[62]), .B1(n3873), .Y(n3864) );
OAI21XLTS U5012 ( .A0(n5058), .A1(n3904), .B0(n3864), .Y(n1941) );
NAND3XLTS U5013 ( .A(cont_iter_out[3]), .B(n3865), .C(n2988), .Y(n4200) );
NAND2X1TS U5014 ( .A(n4200), .B(n4947), .Y(n4952) );
NAND3XLTS U5015 ( .A(n3026), .B(n4427), .C(n5056), .Y(n4339) );
NOR2XLTS U5016 ( .A(n4940), .B(d_ff3_LUT_out[1]), .Y(n3866) );
AOI31XLTS U5017 ( .A0(n4942), .A1(n4339), .A2(n4946), .B0(n3866), .Y(n2796)
);
INVX2TS U5018 ( .A(n3872), .Y(n3917) );
AOI22X1TS U5019 ( .A0(add_subt_module_intDY[16]), .A1(n3786), .B0(
add_subt_module_DMP[16]), .B1(n4997), .Y(n3867) );
OAI21XLTS U5020 ( .A0(n5137), .A1(n3917), .B0(n3867), .Y(n1710) );
AOI22X1TS U5021 ( .A0(add_subt_module_intDY[9]), .A1(n3915), .B0(
add_subt_module_DMP[9]), .B1(n3784), .Y(n3868) );
OAI21XLTS U5022 ( .A0(n5100), .A1(n3917), .B0(n3868), .Y(n1711) );
AOI22X1TS U5023 ( .A0(add_subt_module_intDX[60]), .A1(n3869), .B0(
add_subt_module_DMP[60]), .B1(n3873), .Y(n3870) );
CLKBUFX2TS U5024 ( .A(n3872), .Y(n5007) );
AOI22X1TS U5025 ( .A0(add_subt_module_intDX[61]), .A1(n5007), .B0(
add_subt_module_DMP[61]), .B1(n3873), .Y(n3874) );
OAI21XLTS U5026 ( .A0(n5025), .A1(n3910), .B0(n3874), .Y(n1937) );
INVX2TS U5027 ( .A(n3910), .Y(n3915) );
AOI22X1TS U5028 ( .A0(add_subt_module_intDY[1]), .A1(n3786), .B0(
add_subt_module_DMP[1]), .B1(n3900), .Y(n3875) );
OAI21XLTS U5029 ( .A0(n5073), .A1(n3917), .B0(n3875), .Y(n1709) );
AOI22X1TS U5030 ( .A0(d_ff_Xn[0]), .A1(n3896), .B0(sign_inv_out[0]), .B1(
n3895), .Y(n3876) );
OAI21XLTS U5031 ( .A0(n5212), .A1(n3898), .B0(n3876), .Y(n2089) );
AOI22X1TS U5032 ( .A0(add_subt_module_intDX[5]), .A1(n3908), .B0(
add_subt_module_DMP[5]), .B1(n5003), .Y(n3877) );
AOI22X1TS U5033 ( .A0(add_subt_module_intDY[58]), .A1(n3797), .B0(
add_subt_module_DMP[58]), .B1(n4997), .Y(n3878) );
OAI21XLTS U5034 ( .A0(n5047), .A1(n3904), .B0(n3878), .Y(n1928) );
AOI22X1TS U5035 ( .A0(add_subt_module_intDY[20]), .A1(n5005), .B0(
add_subt_module_DMP[20]), .B1(n5003), .Y(n3879) );
OAI21XLTS U5036 ( .A0(n5144), .A1(n3917), .B0(n3879), .Y(n1714) );
AOI22X1TS U5037 ( .A0(add_subt_module_intDY[3]), .A1(n3915), .B0(
add_subt_module_DMP[3]), .B1(n3911), .Y(n3880) );
OAI21XLTS U5038 ( .A0(n5027), .A1(n3917), .B0(n3880), .Y(n1708) );
AOI22X1TS U5039 ( .A0(add_subt_module_intDX[62]), .A1(n5007), .B0(
add_subt_module_DMP[62]), .B1(n3881), .Y(n3882) );
OAI21XLTS U5040 ( .A0(n5058), .A1(n3883), .B0(n3882), .Y(n1940) );
AOI22X1TS U5041 ( .A0(add_subt_module_intDY[57]), .A1(n3805), .B0(
add_subt_module_DMP[57]), .B1(n3881), .Y(n3884) );
OAI21XLTS U5042 ( .A0(n5096), .A1(n3904), .B0(n3884), .Y(n1925) );
AOI22X1TS U5043 ( .A0(add_subt_module_intDY[13]), .A1(n3786), .B0(
add_subt_module_DMP[13]), .B1(n5003), .Y(n3885) );
OAI21XLTS U5044 ( .A0(n5147), .A1(n3907), .B0(n3885), .Y(n1715) );
AOI22X1TS U5045 ( .A0(d_ff_Xn[51]), .A1(n3586), .B0(sign_inv_out[51]), .B1(
n3886), .Y(n3887) );
AOI22X1TS U5046 ( .A0(add_subt_module_intDY[10]), .A1(n3915), .B0(
add_subt_module_DMP[10]), .B1(n5003), .Y(n3888) );
OAI21XLTS U5047 ( .A0(n5037), .A1(n3907), .B0(n3888), .Y(n1716) );
AOI22X1TS U5048 ( .A0(add_subt_module_intDX[56]), .A1(n3889), .B0(
add_subt_module_DMP[56]), .B1(n3881), .Y(n3890) );
OAI21XLTS U5049 ( .A0(n5038), .A1(n3790), .B0(n3890), .Y(n1922) );
AOI22X1TS U5050 ( .A0(add_subt_module_intDX[50]), .A1(n3908), .B0(
add_subt_module_DMP[50]), .B1(n3900), .Y(n3891) );
OAI21XLTS U5051 ( .A0(n5039), .A1(n3910), .B0(n3891), .Y(n1707) );
AOI22X1TS U5052 ( .A0(d_ff_Xn[4]), .A1(n3896), .B0(sign_inv_out[4]), .B1(
n3665), .Y(n3892) );
OAI21XLTS U5053 ( .A0(n5216), .A1(n3898), .B0(n3892), .Y(n2081) );
AOI22X1TS U5054 ( .A0(add_subt_module_intDX[0]), .A1(n3893), .B0(
add_subt_module_DMP[0]), .B1(n4997), .Y(n3894) );
OAI21XLTS U5055 ( .A0(n5061), .A1(n3910), .B0(n3894), .Y(n1703) );
AOI22X1TS U5056 ( .A0(d_ff_Xn[2]), .A1(n3896), .B0(sign_inv_out[2]), .B1(
n3895), .Y(n3897) );
OAI21XLTS U5057 ( .A0(n5214), .A1(n3898), .B0(n3897), .Y(n2085) );
AOI22X1TS U5058 ( .A0(add_subt_module_intDY[11]), .A1(n5005), .B0(
add_subt_module_DMP[11]), .B1(n5003), .Y(n3899) );
OAI21XLTS U5059 ( .A0(n5079), .A1(n3907), .B0(n3899), .Y(n1719) );
AOI22X1TS U5060 ( .A0(add_subt_module_intDX[4]), .A1(n3908), .B0(
add_subt_module_DMP[4]), .B1(n3900), .Y(n3901) );
OAI21XLTS U5061 ( .A0(n5065), .A1(n3910), .B0(n3901), .Y(n1705) );
AOI22X1TS U5062 ( .A0(add_subt_module_intDY[54]), .A1(n3792), .B0(
add_subt_module_DMP[54]), .B1(n3911), .Y(n3902) );
OAI21XLTS U5063 ( .A0(n5069), .A1(n3904), .B0(n3902), .Y(n1916) );
AOI22X1TS U5064 ( .A0(add_subt_module_intDY[55]), .A1(n5001), .B0(
add_subt_module_DMP[55]), .B1(n3900), .Y(n3903) );
OAI21XLTS U5065 ( .A0(n5028), .A1(n3904), .B0(n3903), .Y(n1919) );
INVX2TS U5066 ( .A(n4108), .Y(n4925) );
AOI22X1TS U5067 ( .A0(add_subt_module_intDY[12]), .A1(n3786), .B0(
add_subt_module_DMP[12]), .B1(n5003), .Y(n3906) );
OAI21XLTS U5068 ( .A0(n5031), .A1(n3907), .B0(n3906), .Y(n1718) );
AOI22X1TS U5069 ( .A0(add_subt_module_intDX[8]), .A1(n3908), .B0(
add_subt_module_DMP[8]), .B1(n5003), .Y(n3909) );
OAI21XLTS U5070 ( .A0(n5026), .A1(n3910), .B0(n3909), .Y(n1720) );
AOI22X1TS U5071 ( .A0(add_subt_module_intDY[53]), .A1(n4998), .B0(
add_subt_module_DMP[53]), .B1(n3911), .Y(n3912) );
OAI21XLTS U5072 ( .A0(n5040), .A1(n3913), .B0(n3912), .Y(n1913) );
AOI22X1TS U5073 ( .A0(add_subt_module_intDY[2]), .A1(n5005), .B0(
add_subt_module_DMP[2]), .B1(n3900), .Y(n3914) );
OAI21XLTS U5074 ( .A0(n5063), .A1(n3917), .B0(n3914), .Y(n1706) );
AOI22X1TS U5075 ( .A0(add_subt_module_intDY[51]), .A1(n3786), .B0(
add_subt_module_DMP[51]), .B1(n3784), .Y(n3916) );
OAI21XLTS U5076 ( .A0(n5101), .A1(n3917), .B0(n3916), .Y(n1704) );
INVX2TS U5077 ( .A(n4551), .Y(n4593) );
NOR2XLTS U5078 ( .A(n4593), .B(n3918), .Y(n3919) );
CLKBUFX2TS U5079 ( .A(n3919), .Y(n4540) );
CLKBUFX3TS U5080 ( .A(n4540), .Y(n5273) );
CLKAND2X2TS U5081 ( .A(n2991), .B(add_subt_module_DmP[59]), .Y(n3920) );
XOR2X1TS U5082 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3920), .Y(
DP_OP_92J75_122_9081_n19) );
CLKAND2X2TS U5083 ( .A(n2991), .B(add_subt_module_DmP[60]), .Y(n3921) );
XOR2X1TS U5084 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3921), .Y(
DP_OP_92J75_122_9081_n18) );
CLKAND2X2TS U5085 ( .A(n2991), .B(add_subt_module_DmP[61]), .Y(n3922) );
XOR2X1TS U5086 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3922), .Y(
DP_OP_92J75_122_9081_n17) );
CLKAND2X2TS U5087 ( .A(n2991), .B(add_subt_module_DmP[62]), .Y(n3923) );
XOR2X1TS U5088 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3923), .Y(
DP_OP_92J75_122_9081_n16) );
AO22XLTS U5089 ( .A0(add_subt_module_LZA_output[1]), .A1(n2984), .B0(n2992),
.B1(add_subt_module_DmP[53]), .Y(n3924) );
XOR2X1TS U5090 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3924), .Y(
DP_OP_92J75_122_9081_n25) );
AO22XLTS U5091 ( .A0(add_subt_module_LZA_output[2]), .A1(n2984), .B0(n2992),
.B1(add_subt_module_DmP[54]), .Y(n3925) );
XOR2X1TS U5092 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3925), .Y(
DP_OP_92J75_122_9081_n24) );
AO22XLTS U5093 ( .A0(add_subt_module_LZA_output[3]), .A1(n2984), .B0(n2992),
.B1(add_subt_module_DmP[55]), .Y(n3926) );
XOR2X1TS U5094 ( .A(n3025), .B(n3926), .Y(DP_OP_92J75_122_9081_n23) );
AO22XLTS U5095 ( .A0(add_subt_module_LZA_output[4]), .A1(n2984), .B0(n2992),
.B1(add_subt_module_DmP[56]), .Y(n3927) );
XOR2X1TS U5096 ( .A(n3025), .B(n3927), .Y(DP_OP_92J75_122_9081_n22) );
AO22XLTS U5097 ( .A0(add_subt_module_LZA_output[5]), .A1(n2984), .B0(n2992),
.B1(add_subt_module_DmP[57]), .Y(n3928) );
XOR2X1TS U5098 ( .A(n3025), .B(n3928), .Y(DP_OP_92J75_122_9081_n21) );
CLKAND2X2TS U5099 ( .A(n2992), .B(add_subt_module_DmP[58]), .Y(n3929) );
XOR2X1TS U5100 ( .A(n3025), .B(n3929), .Y(DP_OP_92J75_122_9081_n20) );
NAND3X1TS U5101 ( .A(n3956), .B(n3933), .C(n3932), .Y(n4256) );
CLKBUFX2TS U5102 ( .A(n4008), .Y(n4041) );
INVX2TS U5103 ( .A(n4011), .Y(n4025) );
AO22XLTS U5104 ( .A0(n4025), .A1(d_ff_Yn[6]), .B0(n4011), .B1(
result_add_subt[6]), .Y(n2308) );
AOI22X1TS U5105 ( .A0(n4054), .A1(d_ff3_sh_x_out[56]), .B0(n4443), .B1(
d_ff3_sh_y_out[56]), .Y(n3935) );
AOI22X1TS U5106 ( .A0(add_subt_module_intDY[56]), .A1(n4461), .B0(n4466),
.B1(d_ff3_LUT_out[56]), .Y(n3934) );
NAND2X1TS U5107 ( .A(n3935), .B(n3934), .Y(n1951) );
CLKBUFX2TS U5108 ( .A(n4958), .Y(n4158) );
INVX2TS U5109 ( .A(n4158), .Y(n4159) );
CLKBUFX3TS U5110 ( .A(n4958), .Y(n4335) );
AO22XLTS U5111 ( .A0(n4159), .A1(d_ff2_Y[28]), .B0(n4335), .B1(
d_ff3_sh_y_out[28]), .Y(n2161) );
INVX2TS U5112 ( .A(n4011), .Y(n4111) );
CLKBUFX3TS U5113 ( .A(n4008), .Y(n4038) );
AO22XLTS U5114 ( .A0(n4111), .A1(d_ff_Yn[10]), .B0(n4038), .B1(
result_add_subt[10]), .Y(n2324) );
CLKBUFX2TS U5115 ( .A(n4147), .Y(n4141) );
INVX2TS U5116 ( .A(n4508), .Y(n4353) );
CLKBUFX3TS U5117 ( .A(n4569), .Y(n4354) );
AO22XLTS U5118 ( .A0(n4353), .A1(d_ff2_X[26]), .B0(n4160), .B1(
d_ff3_sh_x_out[26]), .Y(n2720) );
INVX2TS U5119 ( .A(n4508), .Y(n4355) );
CLKBUFX3TS U5120 ( .A(n4147), .Y(n4349) );
AO22XLTS U5121 ( .A0(n4355), .A1(d_ff2_X[17]), .B0(n4569), .B1(
d_ff3_sh_x_out[17]), .Y(n2702) );
INVX2TS U5122 ( .A(n4158), .Y(n4135) );
CLKBUFX3TS U5123 ( .A(n3952), .Y(n4134) );
AO22XLTS U5124 ( .A0(n4135), .A1(d_ff2_Y[32]), .B0(n4134), .B1(
d_ff3_sh_y_out[32]), .Y(n2153) );
CLKBUFX2TS U5125 ( .A(n3936), .Y(n4191) );
CLKBUFX2TS U5126 ( .A(n4191), .Y(n4252) );
INVX2TS U5127 ( .A(n4252), .Y(n4230) );
CLKBUFX3TS U5128 ( .A(n4191), .Y(n4131) );
AO22XLTS U5129 ( .A0(n4230), .A1(data_in[20]), .B0(n4131), .B1(d_ff1_Z[20]),
.Y(n2875) );
AO22XLTS U5130 ( .A0(n4111), .A1(d_ff_Yn[9]), .B0(n4038), .B1(
result_add_subt[9]), .Y(n2320) );
CLKBUFX3TS U5131 ( .A(n4147), .Y(n4352) );
AO22XLTS U5132 ( .A0(n4353), .A1(d_ff2_X[33]), .B0(n4569), .B1(
d_ff3_sh_x_out[33]), .Y(n2734) );
AO22XLTS U5133 ( .A0(n4111), .A1(d_ff_Yn[8]), .B0(n4038), .B1(
result_add_subt[8]), .Y(n2316) );
AO22XLTS U5134 ( .A0(n4025), .A1(d_ff_Yn[4]), .B0(n4008), .B1(
result_add_subt[4]), .Y(n2300) );
AO22XLTS U5135 ( .A0(n4025), .A1(d_ff_Yn[7]), .B0(n4038), .B1(
result_add_subt[7]), .Y(n2312) );
INVX2TS U5136 ( .A(n4166), .Y(n4034) );
AO22XLTS U5137 ( .A0(n4034), .A1(sign_inv_out[41]), .B0(n4027), .B1(
data_output[41]), .Y(n2006) );
AO22XLTS U5138 ( .A0(n4025), .A1(d_ff_Yn[5]), .B0(n4011), .B1(
result_add_subt[5]), .Y(n2304) );
CLKBUFX2TS U5139 ( .A(n4027), .Y(n4155) );
INVX2TS U5140 ( .A(n4155), .Y(n4137) );
CLKBUFX3TS U5141 ( .A(n4027), .Y(n4136) );
AO22XLTS U5142 ( .A0(n4137), .A1(sign_inv_out[36]), .B0(n4136), .B1(
data_output[36]), .Y(n2016) );
AO22XLTS U5143 ( .A0(n4137), .A1(sign_inv_out[39]), .B0(n4155), .B1(
data_output[39]), .Y(n2010) );
AO22XLTS U5144 ( .A0(n4111), .A1(d_ff_Yn[11]), .B0(n4038), .B1(
result_add_subt[11]), .Y(n2328) );
INVX2TS U5145 ( .A(n4158), .Y(n4146) );
AO22XLTS U5146 ( .A0(n4146), .A1(d_ff2_Y[17]), .B0(n4508), .B1(
d_ff3_sh_y_out[17]), .Y(n2183) );
AO22XLTS U5147 ( .A0(n4353), .A1(d_ff2_X[28]), .B0(n4354), .B1(
d_ff3_sh_x_out[28]), .Y(n2724) );
AO22XLTS U5148 ( .A0(n4135), .A1(d_ff2_Y[33]), .B0(n4134), .B1(
d_ff3_sh_y_out[33]), .Y(n2151) );
INVX2TS U5149 ( .A(n4508), .Y(n4509) );
AO22XLTS U5150 ( .A0(n4509), .A1(d_ff2_Y[0]), .B0(n4487), .B1(
d_ff3_sh_y_out[0]), .Y(n2217) );
INVX2TS U5151 ( .A(n4011), .Y(n4042) );
AO22XLTS U5152 ( .A0(n4042), .A1(d_ff_Yn[3]), .B0(n4008), .B1(
result_add_subt[3]), .Y(n2296) );
AO22XLTS U5153 ( .A0(n4353), .A1(d_ff2_X[24]), .B0(n4507), .B1(
d_ff3_sh_x_out[24]), .Y(n2716) );
AOI22X1TS U5154 ( .A0(add_subt_module_intDY[37]), .A1(n4013), .B0(n4464),
.B1(d_ff3_sh_y_out[37]), .Y(n3938) );
AOI22X1TS U5155 ( .A0(n4412), .A1(d_ff3_LUT_out[37]), .B0(n4437), .B1(
d_ff3_sh_x_out[37]), .Y(n3937) );
NAND2X1TS U5156 ( .A(n3938), .B(n3937), .Y(n1808) );
AO22XLTS U5157 ( .A0(n4159), .A1(d_ff2_Y[26]), .B0(n4335), .B1(
d_ff3_sh_y_out[26]), .Y(n2165) );
AO22XLTS U5158 ( .A0(n4137), .A1(sign_inv_out[35]), .B0(n4136), .B1(
data_output[35]), .Y(n2018) );
AO22XLTS U5159 ( .A0(n4353), .A1(d_ff2_X[25]), .B0(n4020), .B1(
d_ff3_sh_x_out[25]), .Y(n2718) );
AO22XLTS U5160 ( .A0(n4159), .A1(d_ff2_Y[22]), .B0(n4335), .B1(
d_ff3_sh_y_out[22]), .Y(n2173) );
AO22XLTS U5161 ( .A0(n4159), .A1(d_ff2_Y[24]), .B0(n4335), .B1(
d_ff3_sh_y_out[24]), .Y(n2169) );
AO22XLTS U5162 ( .A0(n4137), .A1(sign_inv_out[37]), .B0(n4136), .B1(
data_output[37]), .Y(n2014) );
AO22XLTS U5163 ( .A0(n4034), .A1(sign_inv_out[42]), .B0(n4181), .B1(
data_output[42]), .Y(n2004) );
AOI22X1TS U5164 ( .A0(add_subt_module_intDY[50]), .A1(n4403), .B0(n4330),
.B1(d_ff3_sh_y_out[50]), .Y(n3940) );
AOI22X1TS U5165 ( .A0(n4384), .A1(d_ff3_LUT_out[50]), .B0(n4193), .B1(
d_ff3_sh_x_out[50]), .Y(n3939) );
NAND2X1TS U5166 ( .A(n3940), .B(n3939), .Y(n1893) );
AO22XLTS U5167 ( .A0(n4042), .A1(d_ff_Yn[2]), .B0(n4011), .B1(
result_add_subt[2]), .Y(n2292) );
AO22XLTS U5168 ( .A0(n4159), .A1(d_ff2_Y[25]), .B0(n4335), .B1(
d_ff3_sh_y_out[25]), .Y(n2167) );
INVX2TS U5169 ( .A(n4155), .Y(n4145) );
CLKBUFX3TS U5170 ( .A(n4166), .Y(n4144) );
AO22XLTS U5171 ( .A0(n4145), .A1(sign_inv_out[27]), .B0(n4144), .B1(
data_output[27]), .Y(n2034) );
AO22XLTS U5172 ( .A0(n4146), .A1(d_ff2_Y[18]), .B0(n4569), .B1(
d_ff3_sh_y_out[18]), .Y(n2181) );
AO22XLTS U5173 ( .A0(n4042), .A1(d_ff_Yn[1]), .B0(n4011), .B1(
result_add_subt[1]), .Y(n2288) );
AO22XLTS U5174 ( .A0(n4146), .A1(d_ff2_Y[21]), .B0(n4147), .B1(
d_ff3_sh_y_out[21]), .Y(n2175) );
AO22XLTS U5175 ( .A0(n4137), .A1(sign_inv_out[31]), .B0(n4136), .B1(
data_output[31]), .Y(n2026) );
INVX2TS U5176 ( .A(n4008), .Y(n4018) );
CLKBUFX3TS U5177 ( .A(n4041), .Y(n4019) );
AO22XLTS U5178 ( .A0(n4018), .A1(d_ff_Yn[0]), .B0(n4019), .B1(
result_add_subt[0]), .Y(n2219) );
AO22XLTS U5179 ( .A0(n4353), .A1(d_ff2_X[29]), .B0(n4352), .B1(
d_ff3_sh_x_out[29]), .Y(n2726) );
AOI22X1TS U5180 ( .A0(n4389), .A1(d_ff2_Z[53]), .B0(n4368), .B1(d_ff2_X[53]),
.Y(n3942) );
AOI22X1TS U5181 ( .A0(add_subt_module_intDX[53]), .A1(n4403), .B0(n4193),
.B1(d_ff2_Y[53]), .Y(n3941) );
NAND2X1TS U5182 ( .A(n3942), .B(n3941), .Y(n1915) );
AO22XLTS U5183 ( .A0(n4159), .A1(d_ff2_Y[29]), .B0(n4335), .B1(
d_ff3_sh_y_out[29]), .Y(n2159) );
AO22XLTS U5184 ( .A0(n4145), .A1(sign_inv_out[29]), .B0(n4136), .B1(
data_output[29]), .Y(n2030) );
AO22XLTS U5185 ( .A0(n4135), .A1(d_ff2_Y[31]), .B0(n4134), .B1(
d_ff3_sh_y_out[31]), .Y(n2155) );
AOI32X1TS U5186 ( .A0(n4579), .A1(n4949), .A2(n4947), .B0(n4487), .B1(n5210),
.Y(n2818) );
AO22XLTS U5187 ( .A0(n4353), .A1(d_ff2_X[27]), .B0(n4568), .B1(
d_ff3_sh_x_out[27]), .Y(n2722) );
AOI22X1TS U5188 ( .A0(n4471), .A1(d_ff3_LUT_out[45]), .B0(n4470), .B1(
d_ff3_sh_y_out[45]), .Y(n3944) );
CLKBUFX3TS U5189 ( .A(n4000), .Y(n4473) );
CLKBUFX3TS U5190 ( .A(n4374), .Y(n4472) );
AOI22X1TS U5191 ( .A0(add_subt_module_intDY[45]), .A1(n4473), .B0(n4472),
.B1(d_ff3_sh_x_out[45]), .Y(n3943) );
NAND2X1TS U5192 ( .A(n3944), .B(n3943), .Y(n1856) );
AO22XLTS U5193 ( .A0(n4145), .A1(sign_inv_out[25]), .B0(n4144), .B1(
data_output[25]), .Y(n2038) );
AO22XLTS U5194 ( .A0(n4159), .A1(d_ff2_Y[27]), .B0(n4335), .B1(
d_ff3_sh_y_out[27]), .Y(n2163) );
CLKBUFX2TS U5195 ( .A(n3936), .Y(n4086) );
INVX2TS U5196 ( .A(n4086), .Y(n4106) );
AO22XLTS U5197 ( .A0(n4086), .A1(d_ff1_shift_region_flag_out[1]), .B0(n4106),
.B1(shift_region_flag[1]), .Y(n2918) );
AO22XLTS U5198 ( .A0(n4355), .A1(d_ff2_X[14]), .B0(n4352), .B1(
d_ff3_sh_x_out[14]), .Y(n2696) );
INVX2TS U5199 ( .A(n4964), .Y(n4965) );
AOI32X1TS U5200 ( .A0(n3946), .A1(n4965), .A2(n5054), .B0(n4964), .B1(n5208),
.Y(n2935) );
AO22XLTS U5201 ( .A0(n4146), .A1(d_ff2_Y[14]), .B0(n4569), .B1(
d_ff3_sh_y_out[14]), .Y(n2189) );
AO22XLTS U5202 ( .A0(n4137), .A1(sign_inv_out[33]), .B0(n4136), .B1(
data_output[33]), .Y(n2022) );
INVX2TS U5203 ( .A(n4365), .Y(n4342) );
AO22XLTS U5204 ( .A0(n4342), .A1(d_ff2_X[36]), .B0(n4349), .B1(
d_ff3_sh_x_out[36]), .Y(n2740) );
NAND2X1TS U5205 ( .A(cont_iter_out[0]), .B(n5044), .Y(n4179) );
OR2X1TS U5206 ( .A(n4021), .B(d_ff2_Y[56]), .Y(n4022) );
NAND2X1TS U5207 ( .A(d_ff2_Y[56]), .B(n4021), .Y(n3947) );
AOI32X1TS U5208 ( .A0(n4022), .A1(n4949), .A2(n3947), .B0(n5207), .B1(n4958),
.Y(n2099) );
AOI22X1TS U5209 ( .A0(add_subt_module_intDY[20]), .A1(n4455), .B0(n4470),
.B1(d_ff3_sh_y_out[20]), .Y(n3949) );
AOI22X1TS U5210 ( .A0(n4471), .A1(d_ff3_LUT_out[20]), .B0(n4472), .B1(
d_ff3_sh_x_out[20]), .Y(n3948) );
NAND2X1TS U5211 ( .A(n3949), .B(n3948), .Y(n1852) );
AO22XLTS U5212 ( .A0(n4135), .A1(d_ff2_Y[36]), .B0(n4134), .B1(
d_ff3_sh_y_out[36]), .Y(n2145) );
NAND2X1TS U5213 ( .A(cont_iter_out[0]), .B(n5139), .Y(n4167) );
NAND2X1TS U5214 ( .A(d_ff2_X[56]), .B(n4382), .Y(n3950) );
AOI32X1TS U5215 ( .A0(n4441), .A1(n4949), .A2(n3950), .B0(n5206), .B1(n3952),
.Y(n2778) );
AO22XLTS U5216 ( .A0(n4355), .A1(d_ff2_X[15]), .B0(n4349), .B1(
d_ff3_sh_x_out[15]), .Y(n2698) );
AO22XLTS U5217 ( .A0(n4137), .A1(sign_inv_out[32]), .B0(n4136), .B1(
data_output[32]), .Y(n2024) );
AO22XLTS U5218 ( .A0(n4146), .A1(d_ff2_Y[15]), .B0(n4365), .B1(
d_ff3_sh_y_out[15]), .Y(n2187) );
AOI22X1TS U5219 ( .A0(n5205), .A1(n3952), .B0(n3951), .B1(n4024), .Y(n2803)
);
AO22XLTS U5220 ( .A0(n4342), .A1(d_ff2_X[35]), .B0(n4141), .B1(
d_ff3_sh_x_out[35]), .Y(n2738) );
AO22XLTS U5221 ( .A0(n4145), .A1(sign_inv_out[28]), .B0(n4144), .B1(
data_output[28]), .Y(n2032) );
AO22XLTS U5222 ( .A0(n4135), .A1(d_ff2_Y[35]), .B0(n4134), .B1(
d_ff3_sh_y_out[35]), .Y(n2147) );
AO22XLTS U5223 ( .A0(n4353), .A1(d_ff2_X[30]), .B0(n4365), .B1(
d_ff3_sh_x_out[30]), .Y(n2728) );
INVX2TS U5224 ( .A(n4581), .Y(n4522) );
AO22XLTS U5225 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[40]), .B0(
n3390), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[40]), .Y(n2636)
);
AO22XLTS U5226 ( .A0(n4145), .A1(sign_inv_out[26]), .B0(n4144), .B1(
data_output[26]), .Y(n2036) );
AO22XLTS U5227 ( .A0(n4159), .A1(d_ff2_Y[30]), .B0(n4335), .B1(
d_ff3_sh_y_out[30]), .Y(n2157) );
AO22XLTS U5228 ( .A0(n4355), .A1(d_ff2_X[23]), .B0(n4160), .B1(
d_ff3_sh_x_out[23]), .Y(n2714) );
AO22XLTS U5229 ( .A0(n4145), .A1(sign_inv_out[22]), .B0(n4144), .B1(
data_output[22]), .Y(n2044) );
AO22XLTS U5230 ( .A0(n4159), .A1(d_ff2_Y[23]), .B0(n4335), .B1(
d_ff3_sh_y_out[23]), .Y(n2171) );
AO22XLTS U5231 ( .A0(n4135), .A1(d_ff2_Y[34]), .B0(n4134), .B1(
d_ff3_sh_y_out[34]), .Y(n2149) );
AO22XLTS U5232 ( .A0(n4355), .A1(d_ff2_X[19]), .B0(n4354), .B1(
d_ff3_sh_x_out[19]), .Y(n2706) );
AO22XLTS U5233 ( .A0(n4145), .A1(sign_inv_out[24]), .B0(n4144), .B1(
data_output[24]), .Y(n2040) );
AO22XLTS U5234 ( .A0(n4146), .A1(d_ff2_Y[19]), .B0(n4158), .B1(
d_ff3_sh_y_out[19]), .Y(n2179) );
AO22XLTS U5235 ( .A0(n4342), .A1(d_ff2_X[37]), .B0(n4569), .B1(
d_ff3_sh_x_out[37]), .Y(n2742) );
INVX2TS U5236 ( .A(n4155), .Y(n4149) );
CLKBUFX3TS U5237 ( .A(n4166), .Y(n4148) );
AO22XLTS U5238 ( .A0(n4149), .A1(sign_inv_out[17]), .B0(n4148), .B1(
data_output[17]), .Y(n2054) );
AO22XLTS U5239 ( .A0(n4135), .A1(d_ff2_Y[37]), .B0(n4134), .B1(
d_ff3_sh_y_out[37]), .Y(n2143) );
AO22XLTS U5240 ( .A0(n4135), .A1(d_ff2_Y[39]), .B0(n4134), .B1(
d_ff3_sh_y_out[39]), .Y(n2139) );
AO22XLTS U5241 ( .A0(n4149), .A1(sign_inv_out[18]), .B0(n4148), .B1(
data_output[18]), .Y(n2052) );
INVX2TS U5242 ( .A(n4020), .Y(n4161) );
CLKBUFX3TS U5243 ( .A(n4352), .Y(n4160) );
AO22XLTS U5244 ( .A0(n4161), .A1(d_ff2_Y[41]), .B0(n4568), .B1(
d_ff3_sh_y_out[41]), .Y(n2135) );
INVX2TS U5245 ( .A(n4365), .Y(n4336) );
CLKBUFX3TS U5246 ( .A(n3952), .Y(n4188) );
AO22XLTS U5247 ( .A0(n4336), .A1(d_ff2_X[8]), .B0(n4188), .B1(
d_ff3_sh_x_out[8]), .Y(n2684) );
AOI22X1TS U5248 ( .A0(add_subt_module_intDX[58]), .A1(n4196), .B0(
d_ff2_X[58]), .B1(n4330), .Y(n3954) );
AOI22X1TS U5249 ( .A0(d_ff2_Y[58]), .A1(n4437), .B0(n4460), .B1(d_ff2_Z[58]),
.Y(n3953) );
NAND2X1TS U5250 ( .A(n3954), .B(n3953), .Y(n1930) );
AO22XLTS U5251 ( .A0(n4145), .A1(sign_inv_out[21]), .B0(n4144), .B1(
data_output[21]), .Y(n2046) );
INVX2TS U5252 ( .A(n4508), .Y(n4163) );
CLKBUFX3TS U5253 ( .A(n4958), .Y(n4162) );
AO22XLTS U5254 ( .A0(n4163), .A1(d_ff2_Y[8]), .B0(n4162), .B1(
d_ff3_sh_y_out[8]), .Y(n2201) );
CLKBUFX3TS U5255 ( .A(n4349), .Y(n4568) );
AO22XLTS U5256 ( .A0(n4342), .A1(d_ff2_X[42]), .B0(n4958), .B1(
d_ff3_sh_x_out[42]), .Y(n2752) );
AO22XLTS U5257 ( .A0(n4161), .A1(d_ff2_Y[42]), .B0(n4160), .B1(
d_ff3_sh_y_out[42]), .Y(n2133) );
AO22XLTS U5258 ( .A0(n4149), .A1(sign_inv_out[14]), .B0(n4148), .B1(
data_output[14]), .Y(n2060) );
AO22XLTS U5259 ( .A0(n4336), .A1(d_ff2_X[11]), .B0(n4141), .B1(
d_ff3_sh_x_out[11]), .Y(n2690) );
AO22XLTS U5260 ( .A0(n4163), .A1(d_ff2_Y[11]), .B0(n4162), .B1(
d_ff3_sh_y_out[11]), .Y(n2195) );
NOR2X1TS U5261 ( .A(n2959), .B(beg_fsm_cordic), .Y(n4674) );
AOI22X1TS U5262 ( .A0(n4674), .A1(n3955), .B0(n5024), .B1(n5011), .Y(n3959)
);
OAI211XLTS U5263 ( .A0(n3956), .A1(n2982), .B0(n5011), .C0(n5060), .Y(n3958)
);
NAND4XLTS U5264 ( .A(n3959), .B(n4924), .C(n3958), .D(n3957), .Y(n2938) );
AOI22X1TS U5265 ( .A0(n4430), .A1(d_ff3_LUT_out[24]), .B0(n4459), .B1(
d_ff3_sh_y_out[24]), .Y(n3961) );
AOI22X1TS U5266 ( .A0(add_subt_module_intDY[24]), .A1(n4438), .B0(n4431),
.B1(d_ff3_sh_x_out[24]), .Y(n3960) );
NAND2X1TS U5267 ( .A(n3961), .B(n3960), .Y(n1744) );
AOI22X1TS U5268 ( .A0(n4430), .A1(d_ff3_LUT_out[17]), .B0(n4436), .B1(
d_ff3_sh_y_out[17]), .Y(n3963) );
AOI22X1TS U5269 ( .A0(add_subt_module_intDY[17]), .A1(n4438), .B0(n4431),
.B1(d_ff3_sh_x_out[17]), .Y(n3962) );
NAND2X1TS U5270 ( .A(n3963), .B(n3962), .Y(n1751) );
INVX2TS U5271 ( .A(n4009), .Y(n4974) );
CLKBUFX2TS U5272 ( .A(n4041), .Y(n4118) );
AO22XLTS U5273 ( .A0(n4974), .A1(d_ff_Yn[61]), .B0(n4118), .B1(
result_add_subt[61]), .Y(n2528) );
AO22XLTS U5274 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[17]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[17]), .Y(n2613)
);
AO22XLTS U5275 ( .A0(n4974), .A1(d_ff_Yn[59]), .B0(n4118), .B1(
result_add_subt[59]), .Y(n2520) );
INVX2TS U5276 ( .A(n3291), .Y(n4823) );
AOI22X1TS U5277 ( .A0(add_subt_module_Add_Subt_result[51]), .A1(n4873), .B0(
add_subt_module_DmP[1]), .B1(n4821), .Y(n3964) );
OAI22X1TS U5278 ( .A0(add_subt_module_DmP[4]), .A1(
add_subt_module_FSM_selector_C), .B0(
add_subt_module_Add_Subt_result[48]), .B1(n4847), .Y(n3965) );
AOI22X1TS U5279 ( .A0(n3289), .A1(n3994), .B0(n2993), .B1(n3006), .Y(n3974)
);
CLKBUFX2TS U5280 ( .A(n4820), .Y(n4913) );
OAI22X1TS U5281 ( .A0(add_subt_module_DmP[3]), .A1(n4871), .B0(
add_subt_module_Add_Subt_result[49]), .B1(n4814), .Y(n3966) );
AOI22X1TS U5282 ( .A0(add_subt_module_Add_Subt_result[4]), .A1(n4849), .B0(
add_subt_module_DmP[2]), .B1(n4821), .Y(n3967) );
AOI22X1TS U5283 ( .A0(n2968), .A1(n3005), .B0(n3397), .B1(n2962), .Y(n3973)
);
CLKBUFX3TS U5284 ( .A(add_subt_module_FSM_selector_C), .Y(n4878) );
OAI22X1TS U5285 ( .A0(add_subt_module_DmP[8]), .A1(n4878), .B0(
add_subt_module_Add_Subt_result[44]), .B1(n4847), .Y(n3968) );
AOI2BB1X2TS U5286 ( .A0N(n4879), .A1N(add_subt_module_Add_Subt_result[10]),
.B0(n3968), .Y(n4897) );
INVX2TS U5287 ( .A(n4850), .Y(n4883) );
OAI222X4TS U5288 ( .A0(n4880), .A1(add_subt_module_Add_Subt_result[47]),
.B0(n4823), .B1(add_subt_module_Add_Subt_result[7]), .C0(
add_subt_module_DmP[5]), .C1(n4865), .Y(n3996) );
OAI22X1TS U5289 ( .A0(add_subt_module_DmP[7]), .A1(n4878), .B0(
add_subt_module_Add_Subt_result[45]), .B1(n4814), .Y(n3969) );
CLKBUFX3TS U5290 ( .A(n3397), .Y(n4905) );
OAI22X1TS U5291 ( .A0(add_subt_module_DmP[6]), .A1(
add_subt_module_FSM_selector_C), .B0(
add_subt_module_Add_Subt_result[8]), .B1(n4864), .Y(n3970) );
AOI22X1TS U5292 ( .A0(n2968), .A1(n2961), .B0(n4905), .B1(n4899), .Y(n3971)
);
OAI21XLTS U5293 ( .A0(n4761), .A1(n3996), .B0(n3971), .Y(n3972) );
AOI21X1TS U5294 ( .A0(n2994), .A1(n4897), .B0(n3972), .Y(n4908) );
AOI32X1TS U5295 ( .A0(n3974), .A1(n4913), .A2(n3973), .B0(n4908), .B1(n4914),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AO22XLTS U5296 ( .A0(n4042), .A1(d_ff_Yn[57]), .B0(n4118), .B1(
result_add_subt[57]), .Y(n2512) );
AOI22X1TS U5297 ( .A0(add_subt_module_intDY[38]), .A1(n4375), .B0(n4372),
.B1(d_ff3_sh_y_out[38]), .Y(n3976) );
AOI22X1TS U5298 ( .A0(n4373), .A1(d_ff3_LUT_out[38]), .B0(n4054), .B1(
d_ff3_sh_x_out[38]), .Y(n3975) );
NAND2X1TS U5299 ( .A(n3976), .B(n3975), .Y(n1832) );
CLKBUFX3TS U5300 ( .A(n4041), .Y(n4109) );
AO22XLTS U5301 ( .A0(n4042), .A1(d_ff_Yn[55]), .B0(n4109), .B1(
result_add_subt[55]), .Y(n2504) );
AO22XLTS U5302 ( .A0(n4042), .A1(d_ff_Yn[54]), .B0(n4109), .B1(
result_add_subt[54]), .Y(n2500) );
CLKBUFX3TS U5303 ( .A(n3977), .Y(n4344) );
CLKBUFX3TS U5304 ( .A(n4330), .Y(n4416) );
AOI22X1TS U5305 ( .A0(n4344), .A1(d_ff2_Z[35]), .B0(n4416), .B1(d_ff2_X[35]),
.Y(n3979) );
AOI22X1TS U5306 ( .A0(add_subt_module_intDX[35]), .A1(n4467), .B0(n4369),
.B1(d_ff2_Y[35]), .Y(n3978) );
NAND2X1TS U5307 ( .A(n3979), .B(n3978), .Y(n1792) );
OAI22X1TS U5308 ( .A0(add_subt_module_DmP[0]), .A1(n4871), .B0(
add_subt_module_Add_Subt_result[2]), .B1(n4823), .Y(n3980) );
AOI22X1TS U5309 ( .A0(n2968), .A1(n3002), .B0(n2993), .B1(n3994), .Y(n3985)
);
CLKBUFX2TS U5310 ( .A(n4913), .Y(n4917) );
AO22XLTS U5311 ( .A0(add_subt_module_Add_Subt_result[54]), .A1(n4702), .B0(
add_subt_module_Add_Subt_result[0]), .B1(n4711), .Y(n3981) );
OAI2BB2X1TS U5312 ( .B0(n5132), .B1(n4814), .A0N(
add_subt_module_Add_Subt_result[1]), .A1N(n3291), .Y(n3986) );
AOI22X1TS U5313 ( .A0(n4900), .A1(n3981), .B0(n4905), .B1(n3986), .Y(n3984)
);
CLKBUFX2TS U5314 ( .A(n4826), .Y(n4903) );
AOI22X1TS U5315 ( .A0(n4808), .A1(n3006), .B0(n4831), .B1(n3005), .Y(n3982)
);
AOI21X1TS U5316 ( .A0(n4811), .A1(n2962), .B0(n3983), .Y(n4916) );
AOI32X1TS U5317 ( .A0(n3985), .A1(n4917), .A2(n3984), .B0(n4916), .B1(n4914),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
AO22XLTS U5318 ( .A0(n4042), .A1(d_ff_Yn[53]), .B0(n4109), .B1(
result_add_subt[53]), .Y(n2496) );
AO22XLTS U5319 ( .A0(n4042), .A1(d_ff_Yn[51]), .B0(n4109), .B1(
result_add_subt[51]), .Y(n2488) );
AOI22X1TS U5320 ( .A0(n3397), .A1(n3002), .B0(n2993), .B1(n2962), .Y(n3990)
);
AOI22X1TS U5321 ( .A0(n4900), .A1(n3986), .B0(n4808), .B1(n3994), .Y(n3989)
);
INVX2TS U5322 ( .A(n4808), .Y(n4893) );
AOI22X1TS U5323 ( .A0(n3397), .A1(n3006), .B0(n2993), .B1(n4899), .Y(n3987)
);
OAI21XLTS U5324 ( .A0(n4893), .A1(n3996), .B0(n3987), .Y(n3988) );
AOI21X1TS U5325 ( .A0(n4811), .A1(n3005), .B0(n3988), .Y(n4912) );
AOI32X1TS U5326 ( .A0(n3990), .A1(n4913), .A2(n3989), .B0(n4912), .B1(n4914),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U5327 ( .A0(n4430), .A1(d_ff2_Z[33]), .B0(n4436), .B1(d_ff2_X[33]),
.Y(n3992) );
CLKBUFX3TS U5328 ( .A(n4193), .Y(n4417) );
AOI22X1TS U5329 ( .A0(add_subt_module_intDX[33]), .A1(n4432), .B0(n4417),
.B1(d_ff2_Y[33]), .Y(n3991) );
NAND2X1TS U5330 ( .A(n3992), .B(n3991), .Y(n1756) );
AO22XLTS U5331 ( .A0(n4974), .A1(d_ff_Yn[50]), .B0(n4109), .B1(
result_add_subt[50]), .Y(n2484) );
AO22XLTS U5332 ( .A0(n4974), .A1(d_ff_Yn[49]), .B0(n4109), .B1(
result_add_subt[49]), .Y(n2480) );
AO22XLTS U5333 ( .A0(n4974), .A1(d_ff_Yn[48]), .B0(n4109), .B1(
result_add_subt[48]), .Y(n2476) );
CLKBUFX3TS U5334 ( .A(n2968), .Y(n4898) );
AOI22X1TS U5335 ( .A0(n4900), .A1(n3002), .B0(n4898), .B1(n2962), .Y(n3999)
);
AOI22X1TS U5336 ( .A0(n4831), .A1(n3994), .B0(n2993), .B1(n3005), .Y(n3998)
);
AOI22X1TS U5337 ( .A0(n4808), .A1(n4899), .B0(n2995), .B1(n2961), .Y(n3995)
);
OAI21XLTS U5338 ( .A0(n4888), .A1(n3996), .B0(n3995), .Y(n3997) );
AOI21X1TS U5339 ( .A0(n4900), .A1(n3006), .B0(n3997), .Y(n4910) );
AOI32X1TS U5340 ( .A0(n3999), .A1(n4913), .A2(n3998), .B0(n4910), .B1(n4914),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AO22XLTS U5341 ( .A0(n4018), .A1(d_ff_Yn[47]), .B0(n4109), .B1(
result_add_subt[47]), .Y(n2472) );
AO22XLTS U5342 ( .A0(n4018), .A1(d_ff_Yn[46]), .B0(n4008), .B1(
result_add_subt[46]), .Y(n2468) );
CLKBUFX3TS U5343 ( .A(n4000), .Y(n4423) );
AOI22X1TS U5344 ( .A0(add_subt_module_intDY[14]), .A1(n4423), .B0(n4420),
.B1(d_ff3_sh_y_out[14]), .Y(n4002) );
AOI22X1TS U5345 ( .A0(n4344), .A1(d_ff3_LUT_out[14]), .B0(n4417), .B1(
d_ff3_sh_x_out[14]), .Y(n4001) );
NAND2X1TS U5346 ( .A(n4002), .B(n4001), .Y(n1780) );
AO22XLTS U5347 ( .A0(n4018), .A1(d_ff_Yn[45]), .B0(n4008), .B1(
result_add_subt[45]), .Y(n2464) );
AO22XLTS U5348 ( .A0(n4018), .A1(d_ff_Yn[44]), .B0(n4009), .B1(
result_add_subt[44]), .Y(n2460) );
AOI22X1TS U5349 ( .A0(n4444), .A1(d_ff2_Z[52]), .B0(n4330), .B1(d_ff2_X[52]),
.Y(n4005) );
AOI22X1TS U5350 ( .A0(add_subt_module_intDX[52]), .A1(n4196), .B0(n4003),
.B1(d_ff2_Y[52]), .Y(n4004) );
NAND2X1TS U5351 ( .A(n4005), .B(n4004), .Y(n1912) );
AO22XLTS U5352 ( .A0(n4018), .A1(d_ff_Yn[43]), .B0(n4011), .B1(
result_add_subt[43]), .Y(n2456) );
INVX2TS U5353 ( .A(n4008), .Y(n4037) );
AO22XLTS U5354 ( .A0(n4037), .A1(d_ff_Yn[42]), .B0(n4118), .B1(
result_add_subt[42]), .Y(n2452) );
AO22XLTS U5355 ( .A0(n4010), .A1(sign_inv_out[62]), .B0(n4164), .B1(
data_output[62]), .Y(n1964) );
AOI22X1TS U5356 ( .A0(add_subt_module_intDY[28]), .A1(n4438), .B0(n4459),
.B1(d_ff3_sh_y_out[28]), .Y(n4007) );
AOI22X1TS U5357 ( .A0(d_ff3_LUT_out[28]), .A1(n4379), .B0(n4417), .B1(
d_ff3_sh_x_out[28]), .Y(n4006) );
NAND2X1TS U5358 ( .A(n4007), .B(n4006), .Y(n1738) );
AO22XLTS U5359 ( .A0(n4037), .A1(d_ff_Yn[41]), .B0(n4008), .B1(
result_add_subt[41]), .Y(n2448) );
AO22XLTS U5360 ( .A0(n4010), .A1(sign_inv_out[61]), .B0(n4164), .B1(
data_output[61]), .Y(n1966) );
AO22XLTS U5361 ( .A0(n4037), .A1(d_ff_Yn[40]), .B0(n4009), .B1(
result_add_subt[40]), .Y(n2444) );
AO22XLTS U5362 ( .A0(n4037), .A1(d_ff_Yn[39]), .B0(n4011), .B1(
result_add_subt[39]), .Y(n2440) );
AO22XLTS U5363 ( .A0(n4010), .A1(sign_inv_out[60]), .B0(n4164), .B1(
data_output[60]), .Y(n1968) );
AO22XLTS U5364 ( .A0(n4037), .A1(d_ff_Yn[38]), .B0(n4041), .B1(
result_add_subt[38]), .Y(n2436) );
INVX2TS U5365 ( .A(n4181), .Y(n4177) );
AO22XLTS U5366 ( .A0(n4177), .A1(sign_inv_out[59]), .B0(n4164), .B1(
data_output[59]), .Y(n1970) );
AO22XLTS U5367 ( .A0(n4974), .A1(d_ff_Yn[37]), .B0(n4118), .B1(
result_add_subt[37]), .Y(n2432) );
INVX2TS U5368 ( .A(n4011), .Y(n4012) );
AO22XLTS U5369 ( .A0(n4012), .A1(d_ff_Yn[36]), .B0(n4019), .B1(
result_add_subt[36]), .Y(n2428) );
CLKBUFX3TS U5370 ( .A(n4027), .Y(n4176) );
AO22XLTS U5371 ( .A0(n4177), .A1(sign_inv_out[58]), .B0(n4176), .B1(
data_output[58]), .Y(n1972) );
AO22XLTS U5372 ( .A0(n4012), .A1(d_ff_Yn[35]), .B0(n4019), .B1(
result_add_subt[35]), .Y(n2424) );
AO22XLTS U5373 ( .A0(n4177), .A1(sign_inv_out[57]), .B0(n4176), .B1(
data_output[57]), .Y(n1974) );
AO22XLTS U5374 ( .A0(n4012), .A1(d_ff_Yn[34]), .B0(n4019), .B1(
result_add_subt[34]), .Y(n2420) );
AO22XLTS U5375 ( .A0(n4012), .A1(d_ff_Yn[33]), .B0(n4019), .B1(
result_add_subt[33]), .Y(n2416) );
AO22XLTS U5376 ( .A0(n4177), .A1(sign_inv_out[56]), .B0(n4176), .B1(
data_output[56]), .Y(n1976) );
AOI22X1TS U5377 ( .A0(n4412), .A1(d_ff3_LUT_out[8]), .B0(n4372), .B1(
d_ff3_sh_y_out[8]), .Y(n4015) );
CLKBUFX3TS U5378 ( .A(n4331), .Y(n4454) );
AOI22X1TS U5379 ( .A0(add_subt_module_intDY[8]), .A1(n4013), .B0(n4454),
.B1(d_ff3_sh_x_out[8]), .Y(n4014) );
NAND2X1TS U5380 ( .A(n4015), .B(n4014), .Y(n1818) );
AO22XLTS U5381 ( .A0(n4018), .A1(d_ff_Yn[32]), .B0(n4019), .B1(
result_add_subt[32]), .Y(n2412) );
AO22XLTS U5382 ( .A0(n4177), .A1(sign_inv_out[55]), .B0(n4176), .B1(
data_output[55]), .Y(n1978) );
AO22XLTS U5383 ( .A0(n4018), .A1(d_ff_Yn[31]), .B0(n4019), .B1(
result_add_subt[31]), .Y(n2408) );
AOI22X1TS U5384 ( .A0(n4389), .A1(d_ff2_Z[3]), .B0(n4169), .B1(d_ff2_X[3]),
.Y(n4017) );
AOI22X1TS U5385 ( .A0(add_subt_module_intDX[3]), .A1(n4332), .B0(n4054),
.B1(d_ff2_Y[3]), .Y(n4016) );
NAND2X1TS U5386 ( .A(n4017), .B(n4016), .Y(n1887) );
AO22XLTS U5387 ( .A0(n4018), .A1(d_ff_Yn[30]), .B0(n4019), .B1(
result_add_subt[30]), .Y(n2404) );
AO22XLTS U5388 ( .A0(n4177), .A1(sign_inv_out[54]), .B0(n4176), .B1(
data_output[54]), .Y(n1980) );
AO22XLTS U5389 ( .A0(n4018), .A1(d_ff_Yn[29]), .B0(n4019), .B1(
result_add_subt[29]), .Y(n2400) );
AO22XLTS U5390 ( .A0(n4177), .A1(sign_inv_out[53]), .B0(n4176), .B1(
data_output[53]), .Y(n1982) );
AO22XLTS U5391 ( .A0(n4111), .A1(d_ff_Yn[28]), .B0(n4019), .B1(
result_add_subt[28]), .Y(n2396) );
CLKBUFX3TS U5392 ( .A(n4041), .Y(n4026) );
AO22XLTS U5393 ( .A0(n4111), .A1(d_ff_Yn[27]), .B0(n4026), .B1(
result_add_subt[27]), .Y(n2392) );
AO22XLTS U5394 ( .A0(n4177), .A1(sign_inv_out[52]), .B0(n4176), .B1(
data_output[52]), .Y(n1984) );
AO22XLTS U5395 ( .A0(n4111), .A1(d_ff_Yn[26]), .B0(n4026), .B1(
result_add_subt[26]), .Y(n2388) );
AO22XLTS U5396 ( .A0(n4034), .A1(sign_inv_out[48]), .B0(n4181), .B1(
data_output[48]), .Y(n1992) );
AO22XLTS U5397 ( .A0(n4111), .A1(d_ff_Yn[24]), .B0(n4026), .B1(
result_add_subt[24]), .Y(n2380) );
AO22XLTS U5398 ( .A0(n4025), .A1(d_ff_Yn[23]), .B0(n4026), .B1(
result_add_subt[23]), .Y(n2376) );
AO22XLTS U5399 ( .A0(n4034), .A1(sign_inv_out[47]), .B0(n4181), .B1(
data_output[47]), .Y(n1994) );
AO22XLTS U5400 ( .A0(n4025), .A1(d_ff_Yn[22]), .B0(n4026), .B1(
result_add_subt[22]), .Y(n2372) );
AO22XLTS U5401 ( .A0(n4034), .A1(sign_inv_out[49]), .B0(n4176), .B1(
data_output[49]), .Y(n1990) );
AO22XLTS U5402 ( .A0(n4025), .A1(d_ff_Yn[21]), .B0(n4026), .B1(
result_add_subt[21]), .Y(n2368) );
CLKBUFX2TS U5403 ( .A(n4958), .Y(n4247) );
AOI21X1TS U5404 ( .A0(d_ff2_Y[57]), .A1(n4022), .B0(n4187), .Y(n4023) );
INVX2TS U5405 ( .A(n4247), .Y(n4496) );
AOI2BB2XLTS U5406 ( .B0(n4476), .B1(n4023), .A0N(d_ff3_sh_y_out[57]), .A1N(
n4496), .Y(n2098) );
AO22XLTS U5407 ( .A0(n4025), .A1(d_ff_Yn[20]), .B0(n4026), .B1(
result_add_subt[20]), .Y(n2364) );
AND3X1TS U5408 ( .A(n4340), .B(n4577), .C(n4024), .Y(n4359) );
AOI2BB1XLTS U5409 ( .A0N(n4509), .A1N(d_ff3_LUT_out[41]), .B0(n4359), .Y(
n2836) );
AO22XLTS U5410 ( .A0(n4034), .A1(sign_inv_out[46]), .B0(n4027), .B1(
data_output[46]), .Y(n1996) );
AO22XLTS U5411 ( .A0(n4025), .A1(d_ff_Yn[19]), .B0(n4026), .B1(
result_add_subt[19]), .Y(n2360) );
AO22XLTS U5412 ( .A0(n4034), .A1(sign_inv_out[44]), .B0(n4155), .B1(
data_output[44]), .Y(n2000) );
AO22XLTS U5413 ( .A0(n4025), .A1(d_ff_Yn[18]), .B0(n4026), .B1(
result_add_subt[18]), .Y(n2356) );
AO22XLTS U5414 ( .A0(n4037), .A1(d_ff_Yn[17]), .B0(n4026), .B1(
result_add_subt[17]), .Y(n2352) );
AO22XLTS U5415 ( .A0(n4034), .A1(sign_inv_out[45]), .B0(n4027), .B1(
data_output[45]), .Y(n1998) );
AO22XLTS U5416 ( .A0(n4037), .A1(d_ff_Yn[16]), .B0(n4038), .B1(
result_add_subt[16]), .Y(n2348) );
INVX2TS U5417 ( .A(n4958), .Y(n4190) );
NAND2X1TS U5418 ( .A(n4187), .B(n5045), .Y(n4398) );
NAND2X1TS U5419 ( .A(n4397), .B(n5046), .Y(n4393) );
AO22XLTS U5420 ( .A0(n4190), .A1(n4028), .B0(n4188), .B1(d_ff3_sh_y_out[60]),
.Y(n2095) );
AOI22X1TS U5421 ( .A0(n4471), .A1(d_ff3_LUT_out[5]), .B0(n4470), .B1(
d_ff3_sh_y_out[5]), .Y(n4030) );
AOI22X1TS U5422 ( .A0(add_subt_module_intDY[5]), .A1(n4473), .B0(n4472),
.B1(d_ff3_sh_x_out[5]), .Y(n4029) );
NAND2X1TS U5423 ( .A(n4030), .B(n4029), .Y(n1859) );
AO22XLTS U5424 ( .A0(n4034), .A1(sign_inv_out[43]), .B0(n4164), .B1(
data_output[43]), .Y(n2002) );
NOR2X1TS U5425 ( .A(d_ff2_Y[61]), .B(n4393), .Y(n4392) );
XOR2XLTS U5426 ( .A(d_ff2_Y[62]), .B(n4392), .Y(n4031) );
AO22XLTS U5427 ( .A0(n4190), .A1(n4031), .B0(n4188), .B1(d_ff3_sh_y_out[62]),
.Y(n2093) );
AO22XLTS U5428 ( .A0(n4037), .A1(d_ff_Yn[15]), .B0(n4038), .B1(
result_add_subt[15]), .Y(n2344) );
AOI21X1TS U5429 ( .A0(cont_iter_out[3]), .A1(n2988), .B0(n4032), .Y(n4491)
);
OAI21X1TS U5430 ( .A0(n4491), .A1(n4954), .B0(n4033), .Y(n4199) );
AOI2BB2XLTS U5431 ( .B0(n4933), .B1(n4340), .A0N(n4932), .A1N(
d_ff3_LUT_out[18]), .Y(n2813) );
AO22XLTS U5432 ( .A0(n4037), .A1(d_ff_Yn[14]), .B0(n4038), .B1(
result_add_subt[14]), .Y(n2340) );
AO22XLTS U5433 ( .A0(n4034), .A1(sign_inv_out[40]), .B0(n4155), .B1(
data_output[40]), .Y(n2008) );
AOI22X1TS U5434 ( .A0(d_ff3_LUT_out[43]), .A1(n4444), .B0(n4453), .B1(
d_ff3_sh_y_out[43]), .Y(n4036) );
AOI22X1TS U5435 ( .A0(add_subt_module_intDY[43]), .A1(n4455), .B0(n4374),
.B1(d_ff3_sh_x_out[43]), .Y(n4035) );
NAND2X1TS U5436 ( .A(n4036), .B(n4035), .Y(n1843) );
AO22XLTS U5437 ( .A0(n4037), .A1(d_ff_Yn[13]), .B0(n4038), .B1(
result_add_subt[13]), .Y(n2336) );
AO22XLTS U5438 ( .A0(n4137), .A1(sign_inv_out[38]), .B0(n4136), .B1(
data_output[38]), .Y(n2012) );
AO22XLTS U5439 ( .A0(n4111), .A1(d_ff_Yn[12]), .B0(n4038), .B1(
result_add_subt[12]), .Y(n2332) );
AO22XLTS U5440 ( .A0(n4149), .A1(sign_inv_out[15]), .B0(n4148), .B1(
data_output[15]), .Y(n2058) );
NOR2BX1TS U5441 ( .AN(n4039), .B(n4256), .Y(n4040) );
INVX2TS U5442 ( .A(n4040), .Y(n4231) );
CLKBUFX2TS U5443 ( .A(n4231), .Y(n4234) );
INVX2TS U5444 ( .A(n4229), .Y(n4240) );
AO22XLTS U5445 ( .A0(n4240), .A1(result_add_subt[27]), .B0(n4239), .B1(
d_ff_Zn[27]), .Y(n2393) );
INVX2TS U5446 ( .A(n4252), .Y(n4238) );
CLKBUFX3TS U5447 ( .A(n4191), .Y(n4237) );
AO22XLTS U5448 ( .A0(n4238), .A1(data_in[53]), .B0(n4237), .B1(d_ff1_Z[53]),
.Y(n2908) );
CLKBUFX2TS U5449 ( .A(n4231), .Y(n4104) );
INVX2TS U5450 ( .A(n4234), .Y(n4236) );
CLKBUFX3TS U5451 ( .A(n4231), .Y(n4070) );
AO22XLTS U5452 ( .A0(n4236), .A1(result_add_subt[14]), .B0(n4070), .B1(
d_ff_Zn[14]), .Y(n2341) );
INVX2TS U5453 ( .A(n4485), .Y(n4517) );
AO22XLTS U5454 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[47]), .B0(
n4581), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[47]), .Y(n2643)
);
INVX2TS U5455 ( .A(n4229), .Y(n4053) );
CLKBUFX3TS U5456 ( .A(n4231), .Y(n4067) );
AO22XLTS U5457 ( .A0(n4053), .A1(result_add_subt[36]), .B0(n4067), .B1(
d_ff_Zn[36]), .Y(n2429) );
AO22XLTS U5458 ( .A0(n4238), .A1(data_in[52]), .B0(n4237), .B1(d_ff1_Z[52]),
.Y(n2907) );
AO22XLTS U5459 ( .A0(n4042), .A1(d_ff_Yn[62]), .B0(n4041), .B1(
result_add_subt[62]), .Y(n2532) );
AO22XLTS U5460 ( .A0(n4236), .A1(result_add_subt[15]), .B0(n4239), .B1(
d_ff_Zn[15]), .Y(n2345) );
AO22XLTS U5461 ( .A0(n4053), .A1(result_add_subt[35]), .B0(n4070), .B1(
d_ff_Zn[35]), .Y(n2425) );
AO22XLTS U5462 ( .A0(n4042), .A1(d_ff_Yn[56]), .B0(n4109), .B1(
result_add_subt[56]), .Y(n2508) );
AO22XLTS U5463 ( .A0(n4238), .A1(data_in[51]), .B0(n4237), .B1(d_ff1_Z[51]),
.Y(n2906) );
AO22XLTS U5464 ( .A0(n4240), .A1(result_add_subt[30]), .B0(n4231), .B1(
d_ff_Zn[30]), .Y(n2405) );
AOI22X1TS U5465 ( .A0(n4389), .A1(d_ff2_Z[1]), .B0(n4343), .B1(d_ff2_X[1]),
.Y(n4044) );
AOI22X1TS U5466 ( .A0(add_subt_module_intDX[1]), .A1(n4332), .B0(n4054),
.B1(d_ff2_Y[1]), .Y(n4043) );
NAND2X1TS U5467 ( .A(n4044), .B(n4043), .Y(n1884) );
INVX2TS U5468 ( .A(n4262), .Y(n4984) );
INVX2TS U5469 ( .A(n4100), .Y(n4307) );
AO22XLTS U5470 ( .A0(d_ff2_X[52]), .A1(n4984), .B0(d_ff_Xn[52]), .B1(n4307),
.Y(n2783) );
AO22XLTS U5471 ( .A0(n4236), .A1(result_add_subt[23]), .B0(n4234), .B1(
d_ff_Zn[23]), .Y(n2377) );
AO22XLTS U5472 ( .A0(n4238), .A1(data_in[50]), .B0(n4237), .B1(d_ff1_Z[50]),
.Y(n2905) );
AO22XLTS U5473 ( .A0(n4053), .A1(result_add_subt[34]), .B0(n4231), .B1(
d_ff_Zn[34]), .Y(n2421) );
INVX2TS U5474 ( .A(n4485), .Y(n4582) );
AO22XLTS U5475 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[43]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[43]), .Y(n2639)
);
AO22XLTS U5476 ( .A0(n4236), .A1(result_add_subt[19]), .B0(n4231), .B1(
d_ff_Zn[19]), .Y(n2361) );
AOI22X1TS U5477 ( .A0(n4389), .A1(d_ff2_Z[16]), .B0(n4388), .B1(d_ff2_X[16]),
.Y(n4046) );
AOI22X1TS U5478 ( .A0(add_subt_module_intDX[16]), .A1(n4332), .B0(n4374),
.B1(d_ff2_Y[16]), .Y(n4045) );
NAND2X1TS U5479 ( .A(n4046), .B(n4045), .Y(n1873) );
AO22XLTS U5480 ( .A0(n4053), .A1(result_add_subt[37]), .B0(n4104), .B1(
d_ff_Zn[37]), .Y(n2433) );
AO22XLTS U5481 ( .A0(n4238), .A1(data_in[49]), .B0(n4237), .B1(d_ff1_Z[49]),
.Y(n2904) );
AO22XLTS U5482 ( .A0(n4053), .A1(result_add_subt[39]), .B0(n4070), .B1(
d_ff_Zn[39]), .Y(n2441) );
INVX2TS U5483 ( .A(n4581), .Y(n4486) );
AO22XLTS U5484 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[20]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[20]), .Y(n2616)
);
AO22XLTS U5485 ( .A0(n4053), .A1(result_add_subt[41]), .B0(n4104), .B1(
d_ff_Zn[41]), .Y(n2449) );
AO22XLTS U5486 ( .A0(n4238), .A1(data_in[48]), .B0(n4237), .B1(d_ff1_Z[48]),
.Y(n2903) );
INVX2TS U5487 ( .A(n4234), .Y(n4083) );
AO22XLTS U5488 ( .A0(n4083), .A1(result_add_subt[8]), .B0(n4104), .B1(
d_ff_Zn[8]), .Y(n2317) );
AO22XLTS U5489 ( .A0(n4053), .A1(result_add_subt[42]), .B0(n4067), .B1(
d_ff_Zn[42]), .Y(n2453) );
AOI22X1TS U5490 ( .A0(n4389), .A1(d_ff3_LUT_out[16]), .B0(n4388), .B1(
d_ff3_sh_y_out[16]), .Y(n4048) );
AOI22X1TS U5491 ( .A0(add_subt_module_intDY[16]), .A1(n4332), .B0(n4331),
.B1(d_ff3_sh_x_out[16]), .Y(n4047) );
NAND2X1TS U5492 ( .A(n4048), .B(n4047), .Y(n1872) );
AO22XLTS U5493 ( .A0(n4238), .A1(data_in[47]), .B0(n4237), .B1(d_ff1_Z[47]),
.Y(n2902) );
AO22XLTS U5494 ( .A0(n4083), .A1(result_add_subt[11]), .B0(n4070), .B1(
d_ff_Zn[11]), .Y(n2329) );
AO22XLTS U5495 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[33]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[33]), .Y(n2629)
);
AO22XLTS U5496 ( .A0(n4083), .A1(result_add_subt[12]), .B0(n4104), .B1(
d_ff_Zn[12]), .Y(n2333) );
AOI22X1TS U5497 ( .A0(n4471), .A1(d_ff3_LUT_out[13]), .B0(n4453), .B1(
d_ff3_sh_y_out[13]), .Y(n4050) );
AOI22X1TS U5498 ( .A0(add_subt_module_intDY[13]), .A1(n4455), .B0(n4331),
.B1(d_ff3_sh_x_out[13]), .Y(n4049) );
NAND2X1TS U5499 ( .A(n4050), .B(n4049), .Y(n1849) );
AO22XLTS U5500 ( .A0(n4925), .A1(data_in[46]), .B0(n4237), .B1(d_ff1_Z[46]),
.Y(n2901) );
AO22XLTS U5501 ( .A0(n4053), .A1(result_add_subt[38]), .B0(n4067), .B1(
d_ff_Zn[38]), .Y(n2437) );
INVX2TS U5502 ( .A(n4485), .Y(n4511) );
AO22XLTS U5503 ( .A0(n4511), .A1(add_subt_module_Add_Subt_result[53]), .B0(
n3390), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[53]), .Y(n2649)
);
AO22XLTS U5504 ( .A0(n4053), .A1(result_add_subt[40]), .B0(n4070), .B1(
d_ff_Zn[40]), .Y(n2445) );
AO22XLTS U5505 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[42]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[42]), .Y(n2638)
);
AO22XLTS U5506 ( .A0(n4083), .A1(result_add_subt[7]), .B0(n4067), .B1(
d_ff_Zn[7]), .Y(n2313) );
INVX2TS U5507 ( .A(n4086), .Y(n4107) );
AO22XLTS U5508 ( .A0(n4107), .A1(data_in[45]), .B0(n4237), .B1(d_ff1_Z[45]),
.Y(n2900) );
AOI22X1TS U5509 ( .A0(n4465), .A1(d_ff2_Y[15]), .B0(n4416), .B1(d_ff2_X[15]),
.Y(n4052) );
AOI22X1TS U5510 ( .A0(add_subt_module_intDX[15]), .A1(n4467), .B0(n4422),
.B1(d_ff2_Z[15]), .Y(n4051) );
NAND2X1TS U5511 ( .A(n4052), .B(n4051), .Y(n1788) );
AO22XLTS U5512 ( .A0(n4053), .A1(result_add_subt[43]), .B0(n4104), .B1(
d_ff_Zn[43]), .Y(n2457) );
AOI22X1TS U5513 ( .A0(n4412), .A1(d_ff3_LUT_out[23]), .B0(n4416), .B1(
d_ff3_sh_y_out[23]), .Y(n4056) );
AOI22X1TS U5514 ( .A0(add_subt_module_intDY[23]), .A1(n4467), .B0(n4054),
.B1(d_ff3_sh_x_out[23]), .Y(n4055) );
NAND2X1TS U5515 ( .A(n4056), .B(n4055), .Y(n1797) );
AO22XLTS U5516 ( .A0(n4083), .A1(result_add_subt[10]), .B0(n4070), .B1(
d_ff_Zn[10]), .Y(n2325) );
AO22XLTS U5517 ( .A0(n4107), .A1(data_in[44]), .B0(n3936), .B1(d_ff1_Z[44]),
.Y(n2899) );
AOI22X1TS U5518 ( .A0(add_subt_module_intDY[11]), .A1(n4375), .B0(n4372),
.B1(d_ff3_sh_y_out[11]), .Y(n4058) );
AOI22X1TS U5519 ( .A0(n4373), .A1(d_ff3_LUT_out[11]), .B0(n4454), .B1(
d_ff3_sh_x_out[11]), .Y(n4057) );
NAND2X1TS U5520 ( .A(n4058), .B(n4057), .Y(n1825) );
AO22XLTS U5521 ( .A0(n4083), .A1(result_add_subt[13]), .B0(n4104), .B1(
d_ff_Zn[13]), .Y(n2337) );
AOI22X1TS U5522 ( .A0(n4412), .A1(d_ff2_Z[23]), .B0(n4416), .B1(d_ff2_X[23]),
.Y(n4060) );
AOI22X1TS U5523 ( .A0(add_subt_module_intDX[23]), .A1(n4467), .B0(n4193),
.B1(d_ff2_Y[23]), .Y(n4059) );
NAND2X1TS U5524 ( .A(n4060), .B(n4059), .Y(n1798) );
AO22XLTS U5525 ( .A0(n4236), .A1(result_add_subt[20]), .B0(n4229), .B1(
d_ff_Zn[20]), .Y(n2365) );
AO22XLTS U5526 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[50]), .B0(
n4581), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[50]), .Y(n2646)
);
AO22XLTS U5527 ( .A0(n4107), .A1(data_in[43]), .B0(n3936), .B1(d_ff1_Z[43]),
.Y(n2898) );
INVX2TS U5528 ( .A(n4229), .Y(n4092) );
CLKBUFX3TS U5529 ( .A(n4239), .Y(n4095) );
AO22XLTS U5530 ( .A0(n4092), .A1(result_add_subt[45]), .B0(n4095), .B1(
d_ff_Zn[45]), .Y(n2465) );
AOI22X1TS U5531 ( .A0(n4400), .A1(d_ff2_Y[46]), .B0(n4388), .B1(d_ff2_X[46]),
.Y(n4062) );
AOI22X1TS U5532 ( .A0(add_subt_module_intDX[46]), .A1(n4332), .B0(n4422),
.B1(d_ff2_Z[46]), .Y(n4061) );
NAND2X1TS U5533 ( .A(n4062), .B(n4061), .Y(n1877) );
AO22XLTS U5534 ( .A0(n4083), .A1(result_add_subt[5]), .B0(n4067), .B1(
d_ff_Zn[5]), .Y(n2305) );
AO22XLTS U5535 ( .A0(n4107), .A1(data_in[42]), .B0(n4252), .B1(d_ff1_Z[42]),
.Y(n2897) );
AO22XLTS U5536 ( .A0(n4083), .A1(result_add_subt[6]), .B0(n4070), .B1(
d_ff_Zn[6]), .Y(n2309) );
AOI22X1TS U5537 ( .A0(n4344), .A1(d_ff2_Z[30]), .B0(n4416), .B1(d_ff2_X[30]),
.Y(n4064) );
AOI22X1TS U5538 ( .A0(add_subt_module_intDX[30]), .A1(n4467), .B0(n4193),
.B1(d_ff2_Y[30]), .Y(n4063) );
NAND2X1TS U5539 ( .A(n4064), .B(n4063), .Y(n1795) );
AOI22X1TS U5540 ( .A0(n4373), .A1(d_ff2_Z[11]), .B0(n4372), .B1(d_ff2_X[11]),
.Y(n4066) );
AOI22X1TS U5541 ( .A0(add_subt_module_intDX[11]), .A1(n4375), .B0(n4454),
.B1(d_ff2_Y[11]), .Y(n4065) );
NAND2X1TS U5542 ( .A(n4066), .B(n4065), .Y(n1826) );
AO22XLTS U5543 ( .A0(n4092), .A1(result_add_subt[44]), .B0(n4067), .B1(
d_ff_Zn[44]), .Y(n2461) );
AOI22X1TS U5544 ( .A0(n4344), .A1(d_ff2_Z[21]), .B0(n4406), .B1(d_ff2_X[21]),
.Y(n4069) );
AOI22X1TS U5545 ( .A0(add_subt_module_intDX[21]), .A1(n4432), .B0(n4431),
.B1(d_ff2_Y[21]), .Y(n4068) );
NAND2X1TS U5546 ( .A(n4069), .B(n4068), .Y(n1766) );
AO22XLTS U5547 ( .A0(n4083), .A1(result_add_subt[9]), .B0(n4104), .B1(
d_ff_Zn[9]), .Y(n2321) );
AO22XLTS U5548 ( .A0(n4107), .A1(data_in[41]), .B0(n4086), .B1(d_ff1_Z[41]),
.Y(n2896) );
AO22XLTS U5549 ( .A0(n4236), .A1(result_add_subt[16]), .B0(n4234), .B1(
d_ff_Zn[16]), .Y(n2349) );
AOI22X1TS U5550 ( .A0(n4465), .A1(d_ff2_Y[18]), .B0(n4436), .B1(d_ff2_X[18]),
.Y(n4072) );
AOI22X1TS U5551 ( .A0(add_subt_module_intDX[18]), .A1(n4432), .B0(n4460),
.B1(d_ff2_Z[18]), .Y(n4071) );
NAND2X1TS U5552 ( .A(n4072), .B(n4071), .Y(n1763) );
AO22XLTS U5553 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[16]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[16]), .Y(n2612)
);
AO22XLTS U5554 ( .A0(n4092), .A1(result_add_subt[46]), .B0(n4095), .B1(
d_ff_Zn[46]), .Y(n2469) );
AO22XLTS U5555 ( .A0(n4107), .A1(data_in[40]), .B0(n3936), .B1(d_ff1_Z[40]),
.Y(n2895) );
AO22XLTS U5556 ( .A0(n4092), .A1(result_add_subt[49]), .B0(n4095), .B1(
d_ff_Zn[49]), .Y(n2481) );
INVX2TS U5557 ( .A(n4234), .Y(n4089) );
AO22XLTS U5558 ( .A0(n4089), .A1(result_add_subt[1]), .B0(n4067), .B1(
d_ff_Zn[1]), .Y(n2289) );
AOI22X1TS U5559 ( .A0(n4465), .A1(d_ff3_sh_x_out[18]), .B0(n4436), .B1(
d_ff3_sh_y_out[18]), .Y(n4074) );
AOI22X1TS U5560 ( .A0(add_subt_module_intDY[18]), .A1(n4432), .B0(
d_ff3_LUT_out[18]), .B1(n4466), .Y(n4073) );
NAND2X1TS U5561 ( .A(n4074), .B(n4073), .Y(n1762) );
AO22XLTS U5562 ( .A0(n4107), .A1(data_in[39]), .B0(n4252), .B1(d_ff1_Z[39]),
.Y(n2894) );
AO22XLTS U5563 ( .A0(n4089), .A1(result_add_subt[3]), .B0(n4229), .B1(
d_ff_Zn[3]), .Y(n2297) );
AOI22X1TS U5564 ( .A0(n4400), .A1(d_ff3_sh_x_out[21]), .B0(n4420), .B1(
d_ff3_sh_y_out[21]), .Y(n4076) );
AOI22X1TS U5565 ( .A0(add_subt_module_intDY[21]), .A1(n4432), .B0(
d_ff3_LUT_out[21]), .B1(n4466), .Y(n4075) );
NAND2X1TS U5566 ( .A(n4076), .B(n4075), .Y(n1765) );
AO22XLTS U5567 ( .A0(n4092), .A1(result_add_subt[47]), .B0(n4095), .B1(
d_ff_Zn[47]), .Y(n2473) );
AO22XLTS U5568 ( .A0(n4107), .A1(data_in[38]), .B0(n4086), .B1(d_ff1_Z[38]),
.Y(n2893) );
AO22XLTS U5569 ( .A0(n4092), .A1(result_add_subt[50]), .B0(n4095), .B1(
d_ff_Zn[50]), .Y(n2485) );
AOI22X1TS U5570 ( .A0(add_subt_module_intDX[36]), .A1(n4423), .B0(n4416),
.B1(d_ff2_X[36]), .Y(n4078) );
AOI22X1TS U5571 ( .A0(n4344), .A1(d_ff2_Z[36]), .B0(n4417), .B1(d_ff2_Y[36]),
.Y(n4077) );
NAND2X1TS U5572 ( .A(n4078), .B(n4077), .Y(n1785) );
AO22XLTS U5573 ( .A0(n4089), .A1(result_add_subt[2]), .B0(n4239), .B1(
d_ff_Zn[2]), .Y(n2293) );
AOI22X1TS U5574 ( .A0(d_ff3_LUT_out[36]), .A1(n4379), .B0(n4416), .B1(
d_ff3_sh_y_out[36]), .Y(n4080) );
AOI22X1TS U5575 ( .A0(add_subt_module_intDY[36]), .A1(n4423), .B0(n4417),
.B1(d_ff3_sh_x_out[36]), .Y(n4079) );
NAND2X1TS U5576 ( .A(n4080), .B(n4079), .Y(n1784) );
AO22XLTS U5577 ( .A0(n4092), .A1(result_add_subt[48]), .B0(n4095), .B1(
d_ff_Zn[48]), .Y(n2477) );
AO22XLTS U5578 ( .A0(n4107), .A1(data_in[37]), .B0(n4191), .B1(d_ff1_Z[37]),
.Y(n2892) );
AOI22X1TS U5579 ( .A0(n4412), .A1(d_ff2_Z[39]), .B0(n4464), .B1(d_ff2_X[39]),
.Y(n4082) );
AOI22X1TS U5580 ( .A0(add_subt_module_intDX[39]), .A1(n3240), .B0(n4454),
.B1(d_ff2_Y[39]), .Y(n4081) );
NAND2X1TS U5581 ( .A(n4082), .B(n4081), .Y(n1812) );
AO22XLTS U5582 ( .A0(n4083), .A1(result_add_subt[4]), .B0(n4070), .B1(
d_ff_Zn[4]), .Y(n2301) );
AOI22X1TS U5583 ( .A0(n4344), .A1(d_ff3_LUT_out[30]), .B0(n4416), .B1(
d_ff3_sh_y_out[30]), .Y(n4085) );
AOI22X1TS U5584 ( .A0(add_subt_module_intDY[30]), .A1(n4467), .B0(n4437),
.B1(d_ff3_sh_x_out[30]), .Y(n4084) );
NAND2X1TS U5585 ( .A(n4085), .B(n4084), .Y(n1794) );
AO22XLTS U5586 ( .A0(n4092), .A1(result_add_subt[51]), .B0(n4095), .B1(
d_ff_Zn[51]), .Y(n2489) );
INVX2TS U5587 ( .A(n4086), .Y(n4124) );
AO22XLTS U5588 ( .A0(n4124), .A1(data_in[36]), .B0(n3936), .B1(d_ff1_Z[36]),
.Y(n2891) );
AOI22X1TS U5589 ( .A0(n4412), .A1(d_ff3_LUT_out[19]), .B0(n4464), .B1(
d_ff3_sh_y_out[19]), .Y(n4088) );
AOI22X1TS U5590 ( .A0(add_subt_module_intDY[19]), .A1(n4467), .B0(n4369),
.B1(d_ff3_sh_x_out[19]), .Y(n4087) );
NAND2X1TS U5591 ( .A(n4088), .B(n4087), .Y(n1803) );
AO22XLTS U5592 ( .A0(n4089), .A1(result_add_subt[0]), .B0(n4067), .B1(
d_ff_Zn[0]), .Y(n2285) );
INVX2TS U5593 ( .A(n4581), .Y(n4505) );
AO22XLTS U5594 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[24]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[24]), .Y(n2620)
);
AO22XLTS U5595 ( .A0(n4092), .A1(result_add_subt[52]), .B0(n4095), .B1(
d_ff_Zn[52]), .Y(n2493) );
AOI22X1TS U5596 ( .A0(n4412), .A1(d_ff2_Z[41]), .B0(n4464), .B1(d_ff2_X[41]),
.Y(n4091) );
AOI22X1TS U5597 ( .A0(add_subt_module_intDX[41]), .A1(n3240), .B0(n4454),
.B1(d_ff2_Y[41]), .Y(n4090) );
NAND2X1TS U5598 ( .A(n4091), .B(n4090), .Y(n1816) );
AO22XLTS U5599 ( .A0(n4925), .A1(data_in[35]), .B0(n4252), .B1(d_ff1_Z[35]),
.Y(n2890) );
AO22XLTS U5600 ( .A0(n4092), .A1(result_add_subt[53]), .B0(n4095), .B1(
d_ff_Zn[53]), .Y(n2497) );
AOI22X1TS U5601 ( .A0(n4373), .A1(d_ff3_LUT_out[42]), .B0(n4372), .B1(
d_ff3_sh_y_out[42]), .Y(n4094) );
AOI22X1TS U5602 ( .A0(add_subt_module_intDY[42]), .A1(n3240), .B0(n4454),
.B1(d_ff3_sh_x_out[42]), .Y(n4093) );
NAND2X1TS U5603 ( .A(n4094), .B(n4093), .Y(n1822) );
INVX2TS U5604 ( .A(n4235), .Y(n4105) );
AO22XLTS U5605 ( .A0(n4105), .A1(result_add_subt[54]), .B0(n4095), .B1(
d_ff_Zn[54]), .Y(n2501) );
AOI2BB2XLTS U5606 ( .B0(n5084), .B1(n4101), .A0N(d_ff_Xn[58]), .A1N(n4260),
.Y(n2789) );
CLKBUFX3TS U5607 ( .A(n4191), .Y(n4110) );
AO22XLTS U5608 ( .A0(n4106), .A1(data_in[34]), .B0(n4110), .B1(d_ff1_Z[34]),
.Y(n2889) );
AO22XLTS U5609 ( .A0(n4105), .A1(result_add_subt[55]), .B0(n4235), .B1(
d_ff_Zn[55]), .Y(n2505) );
AOI22X1TS U5610 ( .A0(d_ff3_LUT_out[40]), .A1(n4444), .B0(n4453), .B1(
d_ff3_sh_y_out[40]), .Y(n4097) );
AOI22X1TS U5611 ( .A0(add_subt_module_intDY[40]), .A1(n4375), .B0(n4054),
.B1(d_ff3_sh_x_out[40]), .Y(n4096) );
NAND2X1TS U5612 ( .A(n4097), .B(n4096), .Y(n1836) );
AO22XLTS U5613 ( .A0(n4105), .A1(result_add_subt[56]), .B0(n4235), .B1(
d_ff_Zn[56]), .Y(n2509) );
AOI22X1TS U5614 ( .A0(add_subt_module_intDY[9]), .A1(n4473), .B0(n4388),
.B1(d_ff3_sh_y_out[9]), .Y(n4099) );
AOI22X1TS U5615 ( .A0(n4389), .A1(d_ff3_LUT_out[9]), .B0(n4472), .B1(
d_ff3_sh_x_out[9]), .Y(n4098) );
NAND2X1TS U5616 ( .A(n4099), .B(n4098), .Y(n1869) );
AO22XLTS U5617 ( .A0(n4105), .A1(result_add_subt[57]), .B0(n4235), .B1(
d_ff_Zn[57]), .Y(n2513) );
AO22XLTS U5618 ( .A0(n4106), .A1(data_in[33]), .B0(n4110), .B1(d_ff1_Z[33]),
.Y(n2888) );
AOI2BB2XLTS U5619 ( .B0(n5085), .B1(n4101), .A0N(d_ff_Xn[60]), .A1N(n4100),
.Y(n2791) );
AO22XLTS U5620 ( .A0(n4105), .A1(result_add_subt[58]), .B0(n4235), .B1(
d_ff_Zn[58]), .Y(n2517) );
AOI22X1TS U5621 ( .A0(n4389), .A1(d_ff3_LUT_out[49]), .B0(n4388), .B1(
d_ff3_sh_y_out[49]), .Y(n4103) );
AOI22X1TS U5622 ( .A0(add_subt_module_intDY[49]), .A1(n4332), .B0(n4331),
.B1(d_ff3_sh_x_out[49]), .Y(n4102) );
NAND2X1TS U5623 ( .A(n4103), .B(n4102), .Y(n1880) );
AO22XLTS U5624 ( .A0(n4105), .A1(result_add_subt[59]), .B0(n4235), .B1(
d_ff_Zn[59]), .Y(n2521) );
AO22XLTS U5625 ( .A0(n4106), .A1(data_in[32]), .B0(n4110), .B1(d_ff1_Z[32]),
.Y(n2887) );
AO22XLTS U5626 ( .A0(n4105), .A1(result_add_subt[60]), .B0(n4235), .B1(
d_ff_Zn[60]), .Y(n2525) );
AO22XLTS U5627 ( .A0(n4105), .A1(result_add_subt[61]), .B0(n4235), .B1(
d_ff_Zn[61]), .Y(n2529) );
AO22XLTS U5628 ( .A0(n4106), .A1(data_in[31]), .B0(n4110), .B1(d_ff1_Z[31]),
.Y(n2886) );
AO22XLTS U5629 ( .A0(n4105), .A1(result_add_subt[62]), .B0(n4229), .B1(
d_ff_Zn[62]), .Y(n2533) );
AO22XLTS U5630 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[46]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[46]), .Y(n2642)
);
AO22XLTS U5631 ( .A0(n4105), .A1(result_add_subt[63]), .B0(n4067), .B1(
d_ff_Zn[63]), .Y(n2665) );
AO22XLTS U5632 ( .A0(n4106), .A1(data_in[30]), .B0(n4110), .B1(d_ff1_Z[30]),
.Y(n2885) );
AO22XLTS U5633 ( .A0(n4496), .A1(d_ff2_X[63]), .B0(n4160), .B1(
d_ff3_sh_x_out[63]), .Y(n2794) );
AO22XLTS U5634 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[18]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[18]), .Y(n2614)
);
AO22XLTS U5635 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[25]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[25]), .Y(n2621)
);
AO22XLTS U5636 ( .A0(n4106), .A1(data_in[63]), .B0(n4110), .B1(d_ff1_Z[63]),
.Y(n2854) );
AO22XLTS U5637 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[6]), .B0(
n4581), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[6]), .Y(n2602)
);
INVX2TS U5638 ( .A(n4252), .Y(n4253) );
AO22XLTS U5639 ( .A0(n4253), .A1(data_in[0]), .B0(n4108), .B1(d_ff1_Z[0]),
.Y(n2855) );
AO22XLTS U5640 ( .A0(n4106), .A1(data_in[29]), .B0(n4110), .B1(d_ff1_Z[29]),
.Y(n2884) );
AO22XLTS U5641 ( .A0(n4253), .A1(data_in[1]), .B0(n4108), .B1(d_ff1_Z[1]),
.Y(n2856) );
AO22XLTS U5642 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[13]), .B0(
n3390), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[13]), .Y(n2609)
);
AO22XLTS U5643 ( .A0(n4253), .A1(data_in[2]), .B0(n4108), .B1(d_ff1_Z[2]),
.Y(n2857) );
AO22XLTS U5644 ( .A0(n4106), .A1(data_in[28]), .B0(n4110), .B1(d_ff1_Z[28]),
.Y(n2883) );
AO22XLTS U5645 ( .A0(n4253), .A1(data_in[3]), .B0(n4108), .B1(d_ff1_Z[3]),
.Y(n2858) );
AO22XLTS U5646 ( .A0(n4253), .A1(data_in[4]), .B0(n4108), .B1(d_ff1_Z[4]),
.Y(n2859) );
AO22XLTS U5647 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[5]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[5]), .Y(n2601)
);
AO22XLTS U5648 ( .A0(n4107), .A1(data_in[27]), .B0(n4110), .B1(d_ff1_Z[27]),
.Y(n2882) );
AO22XLTS U5649 ( .A0(n4253), .A1(data_in[5]), .B0(n4108), .B1(d_ff1_Z[5]),
.Y(n2860) );
AO22XLTS U5650 ( .A0(n4974), .A1(d_ff_Yn[52]), .B0(n4109), .B1(
result_add_subt[52]), .Y(n2492) );
AO22XLTS U5651 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[32]), .B0(
n4485), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[32]), .Y(n2628)
);
CLKBUFX3TS U5652 ( .A(n3936), .Y(n4123) );
AO22XLTS U5653 ( .A0(n4253), .A1(data_in[6]), .B0(n4123), .B1(d_ff1_Z[6]),
.Y(n2861) );
AO22XLTS U5654 ( .A0(n4230), .A1(data_in[26]), .B0(n4110), .B1(d_ff1_Z[26]),
.Y(n2881) );
AO22XLTS U5655 ( .A0(n4230), .A1(data_in[7]), .B0(n4123), .B1(d_ff1_Z[7]),
.Y(n2862) );
AO22XLTS U5656 ( .A0(n4124), .A1(data_in[8]), .B0(n4123), .B1(d_ff1_Z[8]),
.Y(n2863) );
AO22XLTS U5657 ( .A0(n4111), .A1(d_ff_Yn[58]), .B0(n4118), .B1(
result_add_subt[58]), .Y(n2516) );
AOI22X1TS U5658 ( .A0(n4444), .A1(d_ff2_Z[51]), .B0(n4368), .B1(d_ff2_X[51]),
.Y(n4113) );
AOI22X1TS U5659 ( .A0(add_subt_module_intDX[51]), .A1(n4403), .B0(n4193),
.B1(d_ff2_Y[51]), .Y(n4112) );
NAND2X1TS U5660 ( .A(n4113), .B(n4112), .Y(n1907) );
AO22XLTS U5661 ( .A0(n4124), .A1(data_in[9]), .B0(n4123), .B1(d_ff1_Z[9]),
.Y(n2864) );
AO22XLTS U5662 ( .A0(n4230), .A1(data_in[25]), .B0(n4131), .B1(d_ff1_Z[25]),
.Y(n2880) );
AO22XLTS U5663 ( .A0(n4124), .A1(data_in[10]), .B0(n4123), .B1(d_ff1_Z[10]),
.Y(n2865) );
AOI22X1TS U5664 ( .A0(n4400), .A1(d_ff2_Y[9]), .B0(n4388), .B1(d_ff2_X[9]),
.Y(n4115) );
AOI22X1TS U5665 ( .A0(add_subt_module_intDX[9]), .A1(n4473), .B0(n4379),
.B1(d_ff2_Z[9]), .Y(n4114) );
NAND2X1TS U5666 ( .A(n4115), .B(n4114), .Y(n1870) );
AO22XLTS U5667 ( .A0(n4124), .A1(data_in[11]), .B0(n4123), .B1(d_ff1_Z[11]),
.Y(n2866) );
AO22XLTS U5668 ( .A0(n4230), .A1(data_in[24]), .B0(n4131), .B1(d_ff1_Z[24]),
.Y(n2879) );
AOI22X1TS U5669 ( .A0(n4400), .A1(d_ff2_Y[25]), .B0(n4436), .B1(d_ff2_X[25]),
.Y(n4117) );
AOI22X1TS U5670 ( .A0(add_subt_module_intDX[25]), .A1(n4432), .B0(n4460),
.B1(d_ff2_Z[25]), .Y(n4116) );
NAND2X1TS U5671 ( .A(n4117), .B(n4116), .Y(n1760) );
AO22XLTS U5672 ( .A0(n4124), .A1(data_in[12]), .B0(n4123), .B1(d_ff1_Z[12]),
.Y(n2867) );
AO22XLTS U5673 ( .A0(n4974), .A1(d_ff_Yn[60]), .B0(n4118), .B1(
result_add_subt[60]), .Y(n2524) );
AO22XLTS U5674 ( .A0(n4124), .A1(data_in[13]), .B0(n4123), .B1(d_ff1_Z[13]),
.Y(n2868) );
AOI22X1TS U5675 ( .A0(add_subt_module_intDY[29]), .A1(n4432), .B0(n4420),
.B1(d_ff3_sh_y_out[29]), .Y(n4120) );
AOI22X1TS U5676 ( .A0(n4344), .A1(d_ff3_LUT_out[29]), .B0(n4417), .B1(
d_ff3_sh_x_out[29]), .Y(n4119) );
NAND2X1TS U5677 ( .A(n4120), .B(n4119), .Y(n1769) );
AO22XLTS U5678 ( .A0(n4230), .A1(data_in[23]), .B0(n4131), .B1(d_ff1_Z[23]),
.Y(n2878) );
AO22XLTS U5679 ( .A0(n4124), .A1(data_in[14]), .B0(n4123), .B1(d_ff1_Z[14]),
.Y(n2869) );
AOI22X1TS U5680 ( .A0(n4384), .A1(d_ff2_Z[49]), .B0(n4388), .B1(d_ff2_X[49]),
.Y(n4122) );
AOI22X1TS U5681 ( .A0(add_subt_module_intDX[49]), .A1(n4332), .B0(n4374),
.B1(d_ff2_Y[49]), .Y(n4121) );
NAND2X1TS U5682 ( .A(n4122), .B(n4121), .Y(n1881) );
AO22XLTS U5683 ( .A0(n4124), .A1(data_in[15]), .B0(n4123), .B1(d_ff1_Z[15]),
.Y(n2870) );
AO22XLTS U5684 ( .A0(n4230), .A1(data_in[22]), .B0(n4131), .B1(d_ff1_Z[22]),
.Y(n2877) );
AO22XLTS U5685 ( .A0(n4124), .A1(data_in[16]), .B0(n4131), .B1(d_ff1_Z[16]),
.Y(n2871) );
AOI22X1TS U5686 ( .A0(d_ff2_X[57]), .A1(n4459), .B0(n4422), .B1(d_ff2_Z[57]),
.Y(n4126) );
AOI22X1TS U5687 ( .A0(add_subt_module_intDX[57]), .A1(n4407), .B0(
d_ff2_Y[57]), .B1(n4374), .Y(n4125) );
NAND2X1TS U5688 ( .A(n4126), .B(n4125), .Y(n1927) );
AO22XLTS U5689 ( .A0(n4253), .A1(data_in[17]), .B0(n4131), .B1(d_ff1_Z[17]),
.Y(n2872) );
AOI22X1TS U5690 ( .A0(n4344), .A1(d_ff2_Z[27]), .B0(n4343), .B1(d_ff2_X[27]),
.Y(n4128) );
AOI22X1TS U5691 ( .A0(add_subt_module_intDX[27]), .A1(n4423), .B0(n4431),
.B1(d_ff2_Y[27]), .Y(n4127) );
NAND2X1TS U5692 ( .A(n4128), .B(n4127), .Y(n1778) );
AO22XLTS U5693 ( .A0(n4253), .A1(data_in[18]), .B0(n4131), .B1(d_ff1_Z[18]),
.Y(n2873) );
AO22XLTS U5694 ( .A0(n4230), .A1(data_in[21]), .B0(n4131), .B1(d_ff1_Z[21]),
.Y(n2876) );
AOI22X1TS U5695 ( .A0(add_subt_module_intDY[15]), .A1(n4423), .B0(n4416),
.B1(d_ff3_sh_y_out[15]), .Y(n4130) );
AOI22X1TS U5696 ( .A0(n4344), .A1(d_ff3_LUT_out[15]), .B0(n4417), .B1(
d_ff3_sh_x_out[15]), .Y(n4129) );
NAND2X1TS U5697 ( .A(n4130), .B(n4129), .Y(n1787) );
AO22XLTS U5698 ( .A0(n4230), .A1(data_in[19]), .B0(n4131), .B1(d_ff1_Z[19]),
.Y(n2874) );
AO22XLTS U5699 ( .A0(n4240), .A1(result_add_subt[31]), .B0(n4229), .B1(
d_ff_Zn[31]), .Y(n2409) );
AO22XLTS U5700 ( .A0(n4336), .A1(d_ff2_X[12]), .B0(n4365), .B1(
d_ff3_sh_x_out[12]), .Y(n2692) );
AO22XLTS U5701 ( .A0(n4146), .A1(d_ff2_Y[12]), .B0(n4352), .B1(
d_ff3_sh_y_out[12]), .Y(n2193) );
AO22XLTS U5702 ( .A0(n4137), .A1(sign_inv_out[30]), .B0(n4136), .B1(
data_output[30]), .Y(n2028) );
AO22XLTS U5703 ( .A0(n4342), .A1(d_ff2_X[38]), .B0(n4352), .B1(
d_ff3_sh_x_out[38]), .Y(n2744) );
AO22XLTS U5704 ( .A0(n4135), .A1(d_ff2_Y[38]), .B0(n4134), .B1(
d_ff3_sh_y_out[38]), .Y(n2141) );
AO22XLTS U5705 ( .A0(n4145), .A1(sign_inv_out[23]), .B0(n4144), .B1(
data_output[23]), .Y(n2042) );
AO22XLTS U5706 ( .A0(n4342), .A1(d_ff2_X[40]), .B0(n4020), .B1(
d_ff3_sh_x_out[40]), .Y(n2748) );
AOI22X1TS U5707 ( .A0(n4369), .A1(d_ff2_Y[42]), .B0(n4372), .B1(d_ff2_X[42]),
.Y(n4133) );
AOI22X1TS U5708 ( .A0(add_subt_module_intDX[42]), .A1(n4375), .B0(n4422),
.B1(d_ff2_Z[42]), .Y(n4132) );
NAND2X1TS U5709 ( .A(n4133), .B(n4132), .Y(n1823) );
AO22XLTS U5710 ( .A0(n4135), .A1(d_ff2_Y[40]), .B0(n4134), .B1(
d_ff3_sh_y_out[40]), .Y(n2137) );
AO22XLTS U5711 ( .A0(n4163), .A1(d_ff2_Y[7]), .B0(n4162), .B1(
d_ff3_sh_y_out[7]), .Y(n2203) );
AO22XLTS U5712 ( .A0(n4137), .A1(sign_inv_out[34]), .B0(n4136), .B1(
data_output[34]), .Y(n2020) );
AO22XLTS U5713 ( .A0(n4342), .A1(d_ff2_X[43]), .B0(n4568), .B1(
d_ff3_sh_x_out[43]), .Y(n2754) );
AO22XLTS U5714 ( .A0(n4161), .A1(d_ff2_Y[43]), .B0(n4354), .B1(
d_ff3_sh_y_out[43]), .Y(n2131) );
AO22XLTS U5715 ( .A0(n4149), .A1(sign_inv_out[19]), .B0(n4144), .B1(
data_output[19]), .Y(n2050) );
AO22XLTS U5716 ( .A0(n4163), .A1(d_ff2_Y[10]), .B0(n4162), .B1(
d_ff3_sh_y_out[10]), .Y(n2197) );
AO22XLTS U5717 ( .A0(n4336), .A1(d_ff2_X[13]), .B0(n4569), .B1(
d_ff3_sh_x_out[13]), .Y(n2694) );
INVX2TS U5718 ( .A(n4166), .Y(n4182) );
AO22XLTS U5719 ( .A0(n4182), .A1(sign_inv_out[8]), .B0(n4166), .B1(
data_output[8]), .Y(n2072) );
AO22XLTS U5720 ( .A0(n4146), .A1(d_ff2_Y[13]), .B0(n4158), .B1(
d_ff3_sh_y_out[13]), .Y(n2191) );
AOI22X1TS U5721 ( .A0(n4465), .A1(d_ff2_Y[29]), .B0(n4406), .B1(d_ff2_X[29]),
.Y(n4139) );
AOI22X1TS U5722 ( .A0(add_subt_module_intDX[29]), .A1(n4423), .B0(n4460),
.B1(d_ff2_Z[29]), .Y(n4138) );
NAND2X1TS U5723 ( .A(n4139), .B(n4138), .Y(n1770) );
AO22XLTS U5724 ( .A0(n4355), .A1(d_ff2_X[20]), .B0(n4507), .B1(
d_ff3_sh_x_out[20]), .Y(n2708) );
AO22XLTS U5725 ( .A0(n4149), .A1(sign_inv_out[11]), .B0(n4148), .B1(
data_output[11]), .Y(n2066) );
AO22XLTS U5726 ( .A0(n4146), .A1(d_ff2_Y[20]), .B0(n4352), .B1(
d_ff3_sh_y_out[20]), .Y(n2177) );
INVX2TS U5727 ( .A(n4247), .Y(n4570) );
AO22XLTS U5728 ( .A0(n4570), .A1(d_ff2_X[45]), .B0(n4160), .B1(
d_ff3_sh_x_out[45]), .Y(n2758) );
XOR2XLTS U5729 ( .A(DP_OP_95J75_125_7728_n1), .B(n4591), .Y(n4140) );
AO22XLTS U5730 ( .A0(add_subt_module_add_overflow_flag), .A1(n4511), .B0(
n4485), .B1(n4140), .Y(n2936) );
AO22XLTS U5731 ( .A0(n4161), .A1(d_ff2_Y[45]), .B0(n4507), .B1(
d_ff3_sh_y_out[45]), .Y(n2127) );
AO22XLTS U5732 ( .A0(n4149), .A1(sign_inv_out[12]), .B0(n4148), .B1(
data_output[12]), .Y(n2064) );
AO22XLTS U5733 ( .A0(n4336), .A1(d_ff2_X[5]), .B0(n4349), .B1(
d_ff3_sh_x_out[5]), .Y(n2678) );
AO22XLTS U5734 ( .A0(n4163), .A1(d_ff2_Y[5]), .B0(n4162), .B1(
d_ff3_sh_y_out[5]), .Y(n2207) );
AO22XLTS U5735 ( .A0(n4182), .A1(sign_inv_out[7]), .B0(n4181), .B1(
data_output[7]), .Y(n2074) );
AO22XLTS U5736 ( .A0(n4336), .A1(d_ff2_X[6]), .B0(n4141), .B1(
d_ff3_sh_x_out[6]), .Y(n2680) );
AO22XLTS U5737 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[37]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[37]), .Y(n2633)
);
AO22XLTS U5738 ( .A0(n4163), .A1(d_ff2_Y[6]), .B0(n4162), .B1(
d_ff3_sh_y_out[6]), .Y(n2205) );
AO22XLTS U5739 ( .A0(n4149), .A1(sign_inv_out[10]), .B0(n4148), .B1(
data_output[10]), .Y(n2068) );
AO22XLTS U5740 ( .A0(n4570), .A1(d_ff2_X[44]), .B0(n4354), .B1(
d_ff3_sh_x_out[44]), .Y(n2756) );
AO22XLTS U5741 ( .A0(n4161), .A1(d_ff2_Y[44]), .B0(n4568), .B1(
d_ff3_sh_y_out[44]), .Y(n2129) );
NAND2X1TS U5742 ( .A(n4143), .B(n4142), .Y(n4504) );
NAND2X1TS U5743 ( .A(n4504), .B(n5202), .Y(n2663) );
AO22XLTS U5744 ( .A0(n4149), .A1(sign_inv_out[13]), .B0(n4148), .B1(
data_output[13]), .Y(n2062) );
AO22XLTS U5745 ( .A0(n4336), .A1(d_ff2_X[9]), .B0(n4352), .B1(
d_ff3_sh_x_out[9]), .Y(n2686) );
AO22XLTS U5746 ( .A0(n4163), .A1(d_ff2_Y[9]), .B0(n4162), .B1(
d_ff3_sh_y_out[9]), .Y(n2199) );
AO22XLTS U5747 ( .A0(n4355), .A1(d_ff2_X[16]), .B0(n4349), .B1(
d_ff3_sh_x_out[16]), .Y(n2700) );
AO22XLTS U5748 ( .A0(n4145), .A1(sign_inv_out[20]), .B0(n4144), .B1(
data_output[20]), .Y(n2048) );
AO22XLTS U5749 ( .A0(n4146), .A1(d_ff2_Y[16]), .B0(n4247), .B1(
d_ff3_sh_y_out[16]), .Y(n2185) );
AO22XLTS U5750 ( .A0(n4570), .A1(d_ff2_X[46]), .B0(n4507), .B1(
d_ff3_sh_x_out[46]), .Y(n2760) );
AO22XLTS U5751 ( .A0(n4182), .A1(sign_inv_out[5]), .B0(n4166), .B1(
data_output[5]), .Y(n2078) );
AO22XLTS U5752 ( .A0(n4161), .A1(d_ff2_Y[46]), .B0(n4160), .B1(
d_ff3_sh_y_out[46]), .Y(n2125) );
CLKBUFX3TS U5753 ( .A(n4147), .Y(n4569) );
AO22XLTS U5754 ( .A0(n4570), .A1(d_ff2_X[49]), .B0(n4569), .B1(
d_ff3_sh_x_out[49]), .Y(n2766) );
AO22XLTS U5755 ( .A0(n4182), .A1(sign_inv_out[6]), .B0(n4166), .B1(
data_output[6]), .Y(n2076) );
AO22XLTS U5756 ( .A0(n4161), .A1(d_ff2_Y[49]), .B0(n4354), .B1(
d_ff3_sh_y_out[49]), .Y(n2119) );
AO22XLTS U5757 ( .A0(n4509), .A1(d_ff2_X[1]), .B0(n4162), .B1(
d_ff3_sh_x_out[1]), .Y(n2670) );
AO22XLTS U5758 ( .A0(n4182), .A1(sign_inv_out[9]), .B0(n4148), .B1(
data_output[9]), .Y(n2070) );
AO22XLTS U5759 ( .A0(n4163), .A1(d_ff2_Y[1]), .B0(n4162), .B1(
d_ff3_sh_y_out[1]), .Y(n2215) );
AO22XLTS U5760 ( .A0(n4190), .A1(d_ff2_X[3]), .B0(n4487), .B1(
d_ff3_sh_x_out[3]), .Y(n2674) );
AO22XLTS U5761 ( .A0(n4163), .A1(d_ff2_Y[3]), .B0(n4487), .B1(
d_ff3_sh_y_out[3]), .Y(n2211) );
AO22XLTS U5762 ( .A0(n4149), .A1(sign_inv_out[16]), .B0(n4148), .B1(
data_output[16]), .Y(n2056) );
AO22XLTS U5763 ( .A0(n4570), .A1(d_ff2_X[47]), .B0(n4568), .B1(
d_ff3_sh_x_out[47]), .Y(n2762) );
AOI21X1TS U5764 ( .A0(n4151), .A1(n4154), .B0(n4150), .Y(n4153) );
NOR2X1TS U5765 ( .A(n5024), .B(n5011), .Y(n4672) );
OAI211XLTS U5766 ( .A0(cont_var_out[0]), .A1(n5068), .B0(n4672), .C0(n4928),
.Y(n4152) );
AOI32X1TS U5767 ( .A0(n4154), .A1(n4153), .A2(n4152), .B0(
cordic_FSM_state_reg[2]), .B1(n4153), .Y(n2939) );
AO22XLTS U5768 ( .A0(n4161), .A1(d_ff2_Y[47]), .B0(n4507), .B1(
d_ff3_sh_y_out[47]), .Y(n2123) );
AO22XLTS U5769 ( .A0(n4182), .A1(sign_inv_out[1]), .B0(n4155), .B1(
data_output[1]), .Y(n2086) );
AO22XLTS U5770 ( .A0(n4570), .A1(d_ff2_X[50]), .B0(n4352), .B1(
d_ff3_sh_x_out[50]), .Y(n2768) );
AOI22X1TS U5771 ( .A0(n4400), .A1(d_ff3_sh_x_out[31]), .B0(n4420), .B1(
d_ff3_sh_y_out[31]), .Y(n4157) );
AOI22X1TS U5772 ( .A0(add_subt_module_intDY[31]), .A1(n4423), .B0(n4460),
.B1(d_ff3_LUT_out[31]), .Y(n4156) );
NAND2X1TS U5773 ( .A(n4157), .B(n4156), .Y(n1773) );
AO22XLTS U5774 ( .A0(n4161), .A1(d_ff2_Y[50]), .B0(n4020), .B1(
d_ff3_sh_y_out[50]), .Y(n2117) );
AO22XLTS U5775 ( .A0(n4182), .A1(sign_inv_out[3]), .B0(n4166), .B1(
data_output[3]), .Y(n2082) );
AO22XLTS U5776 ( .A0(n4159), .A1(d_ff2_X[2]), .B0(n4158), .B1(
d_ff3_sh_x_out[2]), .Y(n2672) );
AO22XLTS U5777 ( .A0(n4509), .A1(d_ff2_Y[2]), .B0(n4487), .B1(
d_ff3_sh_y_out[2]), .Y(n2213) );
AO22XLTS U5778 ( .A0(n4177), .A1(sign_inv_out[50]), .B0(n4176), .B1(
data_output[50]), .Y(n1988) );
AO22XLTS U5779 ( .A0(n4161), .A1(d_ff2_Y[48]), .B0(n4568), .B1(
d_ff3_sh_y_out[48]), .Y(n2121) );
AO22XLTS U5780 ( .A0(n4336), .A1(d_ff2_X[4]), .B0(n4020), .B1(
d_ff3_sh_x_out[4]), .Y(n2676) );
AO22XLTS U5781 ( .A0(n4163), .A1(d_ff2_Y[4]), .B0(n4162), .B1(
d_ff3_sh_y_out[4]), .Y(n2209) );
AO22XLTS U5782 ( .A0(n4182), .A1(sign_inv_out[2]), .B0(n4164), .B1(
data_output[2]), .Y(n2084) );
AO22XLTS U5783 ( .A0(n4190), .A1(d_ff2_Y[51]), .B0(n4188), .B1(
d_ff3_sh_y_out[51]), .Y(n2115) );
OAI21XLTS U5784 ( .A0(n3026), .A1(n5139), .B0(n4167), .Y(n4165) );
AO22XLTS U5785 ( .A0(n4496), .A1(n4165), .B0(n4349), .B1(d_ff3_sh_x_out[52]),
.Y(n2782) );
AO22XLTS U5786 ( .A0(n4182), .A1(sign_inv_out[4]), .B0(n4166), .B1(
data_output[4]), .Y(n2080) );
CMPR32X2TS U5787 ( .A(d_ff2_X[53]), .B(n5056), .C(n4167), .CO(n4172), .S(
n4168) );
AO22XLTS U5788 ( .A0(n4496), .A1(n4168), .B0(n4141), .B1(d_ff3_sh_x_out[53]),
.Y(n2781) );
AOI22X1TS U5789 ( .A0(n4400), .A1(d_ff2_Y[2]), .B0(n4169), .B1(d_ff2_X[2]),
.Y(n4171) );
AOI22X1TS U5790 ( .A0(add_subt_module_intDX[2]), .A1(n4403), .B0(n4422),
.B1(d_ff2_Z[2]), .Y(n4170) );
NAND2X1TS U5791 ( .A(n4171), .B(n4170), .Y(n1897) );
AO22XLTS U5792 ( .A0(n4570), .A1(n4173), .B0(n4365), .B1(d_ff3_sh_x_out[54]),
.Y(n2780) );
AO22XLTS U5793 ( .A0(n4496), .A1(n4175), .B0(n4569), .B1(d_ff3_sh_x_out[55]),
.Y(n2779) );
AO22XLTS U5794 ( .A0(n4177), .A1(sign_inv_out[51]), .B0(n4176), .B1(
data_output[51]), .Y(n1986) );
OAI21XLTS U5795 ( .A0(n3026), .A1(n5044), .B0(n4179), .Y(n4178) );
AO22XLTS U5796 ( .A0(n4190), .A1(n4178), .B0(n4188), .B1(d_ff3_sh_y_out[52]),
.Y(n2103) );
AO22XLTS U5797 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[9]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[9]), .Y(n2605)
);
CMPR32X2TS U5798 ( .A(d_ff2_Y[53]), .B(n5056), .C(n4179), .CO(n4183), .S(
n4180) );
AO22XLTS U5799 ( .A0(n4190), .A1(n4180), .B0(n4188), .B1(d_ff3_sh_y_out[53]),
.Y(n2102) );
AO22XLTS U5800 ( .A0(n4182), .A1(sign_inv_out[0]), .B0(n4181), .B1(
data_output[0]), .Y(n2088) );
AO22XLTS U5801 ( .A0(n4190), .A1(n4184), .B0(n4188), .B1(d_ff3_sh_y_out[54]),
.Y(n2101) );
AO22XLTS U5802 ( .A0(n4190), .A1(n4186), .B0(n4188), .B1(d_ff3_sh_y_out[55]),
.Y(n2100) );
AO22XLTS U5803 ( .A0(n4190), .A1(d_ff2_Y[63]), .B0(n4188), .B1(
d_ff3_sh_y_out[63]), .Y(n2091) );
OAI21XLTS U5804 ( .A0(n4187), .A1(n5045), .B0(n4398), .Y(n4189) );
AO22XLTS U5805 ( .A0(n4190), .A1(n4189), .B0(n4188), .B1(d_ff3_sh_y_out[58]),
.Y(n2097) );
AO22XLTS U5806 ( .A0(n4509), .A1(n4928), .B0(n4487), .B1(d_ff3_LUT_out[56]),
.Y(n2850) );
AO22XLTS U5807 ( .A0(n4925), .A1(data_in[62]), .B0(n4251), .B1(d_ff1_Z[62]),
.Y(n2917) );
INVX2TS U5808 ( .A(n4934), .Y(n4428) );
NAND2X1TS U5809 ( .A(n4428), .B(n4955), .Y(n4484) );
AO21XLTS U5810 ( .A0(d_ff3_LUT_out[32]), .A1(n4354), .B0(n4484), .Y(n2827)
);
AOI22X1TS U5811 ( .A0(n4430), .A1(d_ff2_Z[32]), .B0(n4436), .B1(d_ff2_X[32]),
.Y(n4195) );
AOI22X1TS U5812 ( .A0(add_subt_module_intDX[32]), .A1(n4438), .B0(n4193),
.B1(d_ff2_Y[32]), .Y(n4194) );
NAND2X1TS U5813 ( .A(n4195), .B(n4194), .Y(n1749) );
AO22XLTS U5814 ( .A0(n4925), .A1(data_in[61]), .B0(n4251), .B1(d_ff1_Z[61]),
.Y(n2916) );
AOI2BB2XLTS U5815 ( .B0(d_ff3_sign_out), .B1(n5201), .A0N(n5201), .A1N(
d_ff3_sign_out), .Y(n4197) );
AO22XLTS U5816 ( .A0(n4198), .A1(n4197), .B0(n4196), .B1(
add_subt_module_intAS), .Y(n1944) );
AO22XLTS U5817 ( .A0(n4925), .A1(data_in[60]), .B0(n4251), .B1(d_ff1_Z[60]),
.Y(n2915) );
OAI211X1TS U5818 ( .A0(cont_iter_out[2]), .A1(n5056), .B0(n4949), .C0(n4961),
.Y(n4415) );
AOI21X1TS U5819 ( .A0(n4938), .A1(n4415), .B0(n4366), .Y(n4201) );
INVX2TS U5820 ( .A(n4247), .Y(n4449) );
AOI2BB2XLTS U5821 ( .B0(n4201), .B1(n4200), .A0N(d_ff3_LUT_out[0]), .A1N(
n4449), .Y(n2795) );
AO22XLTS U5822 ( .A0(n4238), .A1(data_in[59]), .B0(n4251), .B1(d_ff1_Z[59]),
.Y(n2914) );
OR4X2TS U5823 ( .A(add_subt_module_Add_Subt_result[53]), .B(
add_subt_module_Add_Subt_result[54]), .C(
add_subt_module_Add_Subt_result[51]), .D(
add_subt_module_Add_Subt_result[52]), .Y(n4648) );
NAND2X1TS U5824 ( .A(n4218), .B(n5142), .Y(n4637) );
CLKAND2X2TS U5825 ( .A(n4612), .B(n5138), .Y(n4630) );
NAND2X1TS U5826 ( .A(n5131), .B(n4630), .Y(n4211) );
NOR2X1TS U5827 ( .A(add_subt_module_Add_Subt_result[40]), .B(
add_subt_module_Add_Subt_result[39]), .Y(n4610) );
NAND2BX1TS U5828 ( .AN(n4211), .B(n4610), .Y(n4276) );
NOR2XLTS U5829 ( .A(add_subt_module_Add_Subt_result[41]), .B(n4276), .Y(
n4202) );
NOR2X1TS U5830 ( .A(add_subt_module_Add_Subt_result[37]), .B(
add_subt_module_Add_Subt_result[38]), .Y(n4277) );
NAND2X1TS U5831 ( .A(n4202), .B(n4277), .Y(n4265) );
NAND2X1TS U5832 ( .A(n4280), .B(n5133), .Y(n4647) );
NOR3X2TS U5833 ( .A(add_subt_module_Add_Subt_result[32]), .B(
add_subt_module_Add_Subt_result[31]), .C(n4647), .Y(n4639) );
OR3X1TS U5834 ( .A(add_subt_module_Add_Subt_result[28]), .B(
add_subt_module_Add_Subt_result[30]), .C(
add_subt_module_Add_Subt_result[29]), .Y(n4283) );
NOR2X1TS U5835 ( .A(add_subt_module_Add_Subt_result[27]), .B(n4283), .Y(
n4282) );
NAND3BXLTS U5836 ( .AN(add_subt_module_Add_Subt_result[26]), .B(n4639), .C(
n4282), .Y(n4203) );
NOR2X1TS U5837 ( .A(n5087), .B(n4203), .Y(n4279) );
NOR2X1TS U5838 ( .A(add_subt_module_Add_Subt_result[9]), .B(
add_subt_module_Add_Subt_result[7]), .Y(n4208) );
AOI21X1TS U5839 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n5064), .B0(
add_subt_module_Add_Subt_result[10]), .Y(n4644) );
INVX2TS U5840 ( .A(n4644), .Y(n4205) );
NOR2X1TS U5841 ( .A(add_subt_module_Add_Subt_result[25]), .B(n4203), .Y(
n4268) );
NAND2X1TS U5842 ( .A(n4268), .B(n5083), .Y(n4204) );
NOR3X1TS U5843 ( .A(add_subt_module_Add_Subt_result[23]), .B(
add_subt_module_Add_Subt_result[22]), .C(n4204), .Y(n4207) );
NAND2BX1TS U5844 ( .AN(add_subt_module_Add_Subt_result[21]), .B(n4207), .Y(
n4270) );
NOR3X1TS U5845 ( .A(add_subt_module_Add_Subt_result[20]), .B(
add_subt_module_Add_Subt_result[19]), .C(n4270), .Y(n4621) );
NAND2X1TS U5846 ( .A(n4621), .B(n5108), .Y(n4605) );
NOR3X1TS U5847 ( .A(add_subt_module_Add_Subt_result[16]), .B(
add_subt_module_Add_Subt_result[17]), .C(n4605), .Y(n4223) );
NAND2BX1TS U5848 ( .AN(add_subt_module_Add_Subt_result[15]), .B(n4223), .Y(
n4658) );
NOR3X1TS U5849 ( .A(add_subt_module_Add_Subt_result[14]), .B(
add_subt_module_Add_Subt_result[13]), .C(n4658), .Y(n4604) );
NOR2X1TS U5850 ( .A(add_subt_module_Add_Subt_result[12]), .B(
add_subt_module_Add_Subt_result[11]), .Y(n4596) );
NAND2X2TS U5851 ( .A(n4604), .B(n4596), .Y(n4645) );
INVX2TS U5852 ( .A(n4204), .Y(n4281) );
NAND2X1TS U5853 ( .A(n4281), .B(add_subt_module_Add_Subt_result[23]), .Y(
n4269) );
OAI31X1TS U5854 ( .A0(n4208), .A1(n4205), .A2(n4645), .B0(n4269), .Y(n4206)
);
AOI211X1TS U5855 ( .A0(n4612), .A1(add_subt_module_Add_Subt_result[43]),
.B0(n4279), .C0(n4206), .Y(n4643) );
INVX2TS U5856 ( .A(n4270), .Y(n4631) );
AOI21X1TS U5857 ( .A0(add_subt_module_Add_Subt_result[39]), .A1(n5203), .B0(
add_subt_module_Add_Subt_result[41]), .Y(n4212) );
AOI21X1TS U5858 ( .A0(add_subt_module_Add_Subt_result[21]), .A1(n4207), .B0(
n2964), .Y(n4290) );
NOR2XLTS U5859 ( .A(add_subt_module_Add_Subt_result[4]), .B(n5150), .Y(n4209) );
OAI211XLTS U5860 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n4209), .B0(
n4629), .C0(n5107), .Y(n4210) );
OAI211XLTS U5861 ( .A0(n4212), .A1(n4211), .B0(n4290), .C0(n4210), .Y(n4213)
);
AOI31X1TS U5862 ( .A0(add_subt_module_Add_Subt_result[19]), .A1(n4631), .A2(
n5136), .B0(n4213), .Y(n4635) );
NOR2X1TS U5863 ( .A(add_subt_module_Add_Subt_result[36]), .B(n4265), .Y(
n4275) );
AOI21X1TS U5864 ( .A0(add_subt_module_Add_Subt_result[49]), .A1(n5128), .B0(
add_subt_module_Add_Subt_result[51]), .Y(n4214) );
OAI32X1TS U5865 ( .A0(add_subt_module_Add_Subt_result[54]), .A1(
add_subt_module_Add_Subt_result[52]), .A2(n4214), .B0(n5132), .B1(
add_subt_module_Add_Subt_result[54]), .Y(n4215) );
AOI31XLTS U5866 ( .A0(n4218), .A1(add_subt_module_Add_Subt_result[45]), .A2(
n5109), .B0(n4215), .Y(n4216) );
OAI31X1TS U5867 ( .A0(add_subt_module_Add_Subt_result[38]), .A1(n4276), .A2(
n5055), .B0(n4216), .Y(n4225) );
INVX2TS U5868 ( .A(n4639), .Y(n4217) );
NOR2X1TS U5869 ( .A(add_subt_module_Add_Subt_result[30]), .B(n4217), .Y(
n4606) );
NOR3BX1TS U5870 ( .AN(add_subt_module_Add_Subt_result[27]), .B(n4217), .C(
n4283), .Y(n4274) );
INVX2TS U5871 ( .A(n4218), .Y(n4221) );
AOI211X1TS U5872 ( .A0(add_subt_module_Add_Subt_result[12]), .A1(n5106),
.B0(add_subt_module_Add_Subt_result[14]), .C0(n4658), .Y(n4620) );
AOI32X1TS U5873 ( .A0(add_subt_module_Add_Subt_result[31]), .A1(n4280), .A2(
n5103), .B0(add_subt_module_Add_Subt_result[33]), .B1(n4280), .Y(n4219) );
OAI211XLTS U5874 ( .A0(n4221), .A1(n5142), .B0(n4220), .C0(n4219), .Y(n4222)
);
AOI211X1TS U5875 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4606),
.B0(n4274), .C0(n4222), .Y(n4657) );
NAND2X1TS U5876 ( .A(add_subt_module_Add_Subt_result[15]), .B(n4223), .Y(
n4599) );
OAI211XLTS U5877 ( .A0(n4605), .A1(n5008), .B0(n4657), .C0(n4599), .Y(n4224)
);
AOI211X1TS U5878 ( .A0(add_subt_module_Add_Subt_result[35]), .A1(n4275),
.B0(n4225), .C0(n4224), .Y(n4227) );
NOR3X1TS U5879 ( .A(add_subt_module_Add_Subt_result[6]), .B(
add_subt_module_Add_Subt_result[5]), .C(
add_subt_module_Add_Subt_result[2]), .Y(n4619) );
NOR2XLTS U5880 ( .A(add_subt_module_Add_Subt_result[6]), .B(
add_subt_module_Add_Subt_result[5]), .Y(n4226) );
NAND2X1TS U5881 ( .A(n4629), .B(n4226), .Y(n4600) );
NOR3X1TS U5882 ( .A(add_subt_module_Add_Subt_result[4]), .B(
add_subt_module_Add_Subt_result[3]), .C(n4600), .Y(n4286) );
NAND3XLTS U5883 ( .A(add_subt_module_Add_Subt_result[1]), .B(n4619), .C(
n4286), .Y(n4625) );
NAND4XLTS U5884 ( .A(n4643), .B(n4635), .C(n4227), .D(n4625), .Y(n4228) );
OA21XLTS U5885 ( .A0(n3014), .A1(add_subt_module_LZA_output[0]), .B0(n4228),
.Y(n2592) );
AO22XLTS U5886 ( .A0(n4240), .A1(result_add_subt[26]), .B0(n4229), .B1(
d_ff_Zn[26]), .Y(n2389) );
AO22XLTS U5887 ( .A0(n4925), .A1(data_in[58]), .B0(n4251), .B1(d_ff1_Z[58]),
.Y(n2913) );
AO22XLTS U5888 ( .A0(n4240), .A1(result_add_subt[28]), .B0(n4070), .B1(
d_ff_Zn[28]), .Y(n2397) );
AO22XLTS U5889 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[3]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[3]), .Y(n2599)
);
AO22XLTS U5890 ( .A0(n4236), .A1(result_add_subt[22]), .B0(n4239), .B1(
d_ff_Zn[22]), .Y(n2373) );
AO22XLTS U5891 ( .A0(n4240), .A1(result_add_subt[24]), .B0(n4231), .B1(
d_ff_Zn[24]), .Y(n2381) );
AO22XLTS U5892 ( .A0(n4925), .A1(data_in[57]), .B0(n4251), .B1(d_ff1_Z[57]),
.Y(n2912) );
AO22XLTS U5893 ( .A0(n4240), .A1(result_add_subt[32]), .B0(n4231), .B1(
d_ff_Zn[32]), .Y(n2413) );
AO22XLTS U5894 ( .A0(n4236), .A1(result_add_subt[17]), .B0(n4239), .B1(
d_ff_Zn[17]), .Y(n2353) );
AO22XLTS U5895 ( .A0(n4230), .A1(data_in[56]), .B0(n4251), .B1(d_ff1_Z[56]),
.Y(n2911) );
AO22XLTS U5896 ( .A0(n4240), .A1(result_add_subt[33]), .B0(n4231), .B1(
d_ff_Zn[33]), .Y(n2417) );
AOI22X1TS U5897 ( .A0(n4389), .A1(d_ff3_LUT_out[44]), .B0(n4470), .B1(
d_ff3_sh_y_out[44]), .Y(n4233) );
AOI22X1TS U5898 ( .A0(add_subt_module_intDY[44]), .A1(n4473), .B0(n4472),
.B1(d_ff3_sh_x_out[44]), .Y(n4232) );
NAND2X1TS U5899 ( .A(n4233), .B(n4232), .Y(n1866) );
AO22XLTS U5900 ( .A0(n4240), .A1(result_add_subt[25]), .B0(n4067), .B1(
d_ff_Zn[25]), .Y(n2385) );
AO22XLTS U5901 ( .A0(n4238), .A1(data_in[55]), .B0(n4251), .B1(d_ff1_Z[55]),
.Y(n2910) );
AO22XLTS U5902 ( .A0(n4236), .A1(result_add_subt[18]), .B0(n4070), .B1(
d_ff_Zn[18]), .Y(n2357) );
AO22XLTS U5903 ( .A0(n4236), .A1(result_add_subt[21]), .B0(n4235), .B1(
d_ff_Zn[21]), .Y(n2369) );
AO22XLTS U5904 ( .A0(n4238), .A1(data_in[54]), .B0(n4237), .B1(d_ff1_Z[54]),
.Y(n2909) );
AO22XLTS U5905 ( .A0(n4240), .A1(result_add_subt[29]), .B0(n4239), .B1(
d_ff_Zn[29]), .Y(n2401) );
AOI22X1TS U5906 ( .A0(n4471), .A1(d_ff2_Z[20]), .B0(n4470), .B1(d_ff2_X[20]),
.Y(n4242) );
AOI22X1TS U5907 ( .A0(add_subt_module_intDX[20]), .A1(n4455), .B0(n4472),
.B1(d_ff2_Y[20]), .Y(n4241) );
NAND2X1TS U5908 ( .A(n4242), .B(n4241), .Y(n1853) );
AOI22X1TS U5909 ( .A0(d_ff3_LUT_out[6]), .A1(n4379), .B0(n4470), .B1(
d_ff3_sh_y_out[6]), .Y(n4244) );
AOI22X1TS U5910 ( .A0(add_subt_module_intDY[6]), .A1(n4473), .B0(n4472),
.B1(d_ff3_sh_x_out[6]), .Y(n4243) );
NAND2X1TS U5911 ( .A(n4244), .B(n4243), .Y(n1862) );
AOI22X1TS U5912 ( .A0(d_ff3_LUT_out[27]), .A1(n4379), .B0(n4420), .B1(
d_ff3_sh_y_out[27]), .Y(n4246) );
AOI22X1TS U5913 ( .A0(add_subt_module_intDY[27]), .A1(n4423), .B0(n4454),
.B1(d_ff3_sh_x_out[27]), .Y(n4245) );
NAND2X1TS U5914 ( .A(n4246), .B(n4245), .Y(n1777) );
INVX2TS U5915 ( .A(n4100), .Y(n4316) );
INVX2TS U5916 ( .A(n4262), .Y(n4324) );
AO22XLTS U5917 ( .A0(d_ff_Yn[32]), .A1(n4316), .B0(d_ff2_Y[32]), .B1(n4324),
.Y(n2154) );
AO22XLTS U5918 ( .A0(n4247), .A1(d_ff3_sign_out), .B0(n4496), .B1(
d_ff2_Z[63]), .Y(n2220) );
AO22XLTS U5919 ( .A0(n4919), .A1(
add_subt_module_Exp_Operation_Module_Data_S[9]), .B0(n4301), .B1(
add_subt_module_exp_oper_result[9]), .Y(n2662) );
AO22XLTS U5920 ( .A0(n4919), .A1(
add_subt_module_Exp_Operation_Module_Data_S[8]), .B0(n4301), .B1(
add_subt_module_exp_oper_result[8]), .Y(n2661) );
AO22XLTS U5921 ( .A0(d_ff_Yn[57]), .A1(n4307), .B0(n4248), .B1(d_ff2_Y[57]),
.Y(n2109) );
AO22XLTS U5922 ( .A0(d_ff_Yn[59]), .A1(n4307), .B0(n4248), .B1(d_ff2_Y[59]),
.Y(n2107) );
AO22XLTS U5923 ( .A0(d_ff_Yn[61]), .A1(n4307), .B0(n4248), .B1(d_ff2_Y[61]),
.Y(n2105) );
AO22XLTS U5924 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[1]), .A1(
n2986), .B0(n4301), .B1(add_subt_module_exp_oper_result[1]), .Y(n2654)
);
AO22XLTS U5925 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[2]), .A1(
n2986), .B0(n4301), .B1(add_subt_module_exp_oper_result[2]), .Y(n2655)
);
AO22XLTS U5926 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[3]), .A1(
n2986), .B0(n2987), .B1(add_subt_module_exp_oper_result[3]), .Y(n2656)
);
AO22XLTS U5927 ( .A0(n4919), .A1(
add_subt_module_Exp_Operation_Module_Data_S[4]), .B0(n2987), .B1(
add_subt_module_exp_oper_result[4]), .Y(n2657) );
AO22XLTS U5928 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[27]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[27]), .Y(n2623)
);
NOR2BX1TS U5929 ( .AN(n5529), .B(n4255), .Y(n4254) );
AO22XLTS U5930 ( .A0(n4254), .A1(sel_mux_2_reg[0]), .B0(n4255), .B1(n4257),
.Y(n2852) );
AO22XLTS U5931 ( .A0(n4925), .A1(shift_region_flag[0]), .B0(n4251), .B1(
d_ff1_shift_region_flag_out[0]), .Y(n2919) );
AO22XLTS U5932 ( .A0(n4253), .A1(operation), .B0(n4252), .B1(
d_ff1_operation_out), .Y(n2920) );
AO22XLTS U5933 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[0]), .A1(
n2986), .B0(n2987), .B1(add_subt_module_exp_oper_result[0]), .Y(n2653)
);
AO22XLTS U5934 ( .A0(n4255), .A1(n4258), .B0(sel_mux_2_reg[1]), .B1(n4254),
.Y(n2851) );
AO22XLTS U5935 ( .A0(n4919), .A1(
add_subt_module_Exp_Operation_Module_Data_S[5]), .B0(n2987), .B1(
add_subt_module_exp_oper_result[5]), .Y(n2658) );
AO22XLTS U5936 ( .A0(n2986), .A1(
add_subt_module_Exp_Operation_Module_Data_S[7]), .B0(n2987), .B1(
add_subt_module_exp_oper_result[7]), .Y(n2660) );
OR3X1TS U5937 ( .A(n4258), .B(n4257), .C(n4256), .Y(n4259) );
CLKBUFX2TS U5938 ( .A(n4259), .Y(n4293) );
CLKBUFX2TS U5939 ( .A(n4293), .Y(n4264) );
CLKBUFX2TS U5940 ( .A(n4264), .Y(n4297) );
INVX2TS U5941 ( .A(n4297), .Y(n4323) );
CLKBUFX3TS U5942 ( .A(n4264), .Y(n4322) );
AO22XLTS U5943 ( .A0(n4323), .A1(result_add_subt[32]), .B0(n4322), .B1(
d_ff_Xn[32]), .Y(n2411) );
AO22XLTS U5944 ( .A0(d_ff_Xn[22]), .A1(n3763), .B0(d_ff2_X[22]), .B1(n3004),
.Y(n2713) );
INVX2TS U5945 ( .A(n4299), .Y(n4313) );
AO22XLTS U5946 ( .A0(d_ff_Yn[28]), .A1(n4313), .B0(d_ff2_Y[28]), .B1(n4984),
.Y(n2162) );
AO22XLTS U5947 ( .A0(n4323), .A1(result_add_subt[29]), .B0(n4322), .B1(
d_ff_Xn[29]), .Y(n2399) );
AO22XLTS U5948 ( .A0(d_ff_Yn[26]), .A1(n4313), .B0(d_ff2_Y[26]), .B1(n4984),
.Y(n2166) );
AO22XLTS U5949 ( .A0(n4323), .A1(result_add_subt[31]), .B0(n4322), .B1(
d_ff_Xn[31]), .Y(n2407) );
INVX2TS U5950 ( .A(n4318), .Y(n4319) );
AO22XLTS U5951 ( .A0(n4319), .A1(result_add_subt[62]), .B0(n4297), .B1(
d_ff_Xn[62]), .Y(n2531) );
INVX2TS U5952 ( .A(n4259), .Y(n4327) );
CLKBUFX3TS U5953 ( .A(n4264), .Y(n4328) );
AO22XLTS U5954 ( .A0(n4327), .A1(result_add_subt[14]), .B0(n4328), .B1(
d_ff_Xn[14]), .Y(n2339) );
INVX2TS U5955 ( .A(n4297), .Y(n4294) );
CLKBUFX3TS U5956 ( .A(n4259), .Y(n4291) );
AO22XLTS U5957 ( .A0(n4294), .A1(result_add_subt[52]), .B0(n4291), .B1(
d_ff_Xn[52]), .Y(n2491) );
INVX2TS U5958 ( .A(n4297), .Y(n4296) );
CLKBUFX3TS U5959 ( .A(n4259), .Y(n4295) );
AO22XLTS U5960 ( .A0(n4296), .A1(result_add_subt[36]), .B0(n4295), .B1(
d_ff_Xn[36]), .Y(n2427) );
AO22XLTS U5961 ( .A0(n4319), .A1(result_add_subt[60]), .B0(n4318), .B1(
d_ff_Xn[60]), .Y(n2523) );
AO22XLTS U5962 ( .A0(n4319), .A1(result_add_subt[58]), .B0(n4318), .B1(
d_ff_Xn[58]), .Y(n2515) );
AO22XLTS U5963 ( .A0(n4296), .A1(result_add_subt[35]), .B0(n4295), .B1(
d_ff_Xn[35]), .Y(n2423) );
INVX2TS U5964 ( .A(n4261), .Y(n4308) );
AO22XLTS U5965 ( .A0(d_ff_Yn[4]), .A1(n4307), .B0(d_ff2_Y[4]), .B1(n4308),
.Y(n2210) );
AO22XLTS U5966 ( .A0(n4296), .A1(result_add_subt[34]), .B0(n4322), .B1(
d_ff_Xn[34]), .Y(n2419) );
INVX2TS U5967 ( .A(n4260), .Y(n4315) );
AO22XLTS U5968 ( .A0(d_ff_Yn[2]), .A1(n4315), .B0(d_ff2_Y[2]), .B1(n4308),
.Y(n2214) );
INVX2TS U5969 ( .A(n4261), .Y(n4300) );
AO22XLTS U5970 ( .A0(d_ff_Yn[50]), .A1(n4321), .B0(d_ff2_Y[50]), .B1(n4300),
.Y(n2118) );
AO22XLTS U5971 ( .A0(n4327), .A1(result_add_subt[19]), .B0(n4297), .B1(
d_ff_Xn[19]), .Y(n2359) );
AO22XLTS U5972 ( .A0(d_ff_Yn[46]), .A1(n3763), .B0(d_ff2_Y[46]), .B1(n4300),
.Y(n2126) );
AO22XLTS U5973 ( .A0(n4296), .A1(result_add_subt[39]), .B0(n4295), .B1(
d_ff_Xn[39]), .Y(n2439) );
INVX2TS U5974 ( .A(n4263), .Y(n4309) );
AO22XLTS U5975 ( .A0(d_ff_Yn[9]), .A1(n4309), .B0(d_ff2_Y[9]), .B1(n4308),
.Y(n2200) );
AO22XLTS U5976 ( .A0(d_ff_Yn[6]), .A1(n4309), .B0(d_ff2_Y[6]), .B1(n4308),
.Y(n2206) );
AO22XLTS U5977 ( .A0(n4296), .A1(result_add_subt[41]), .B0(n4295), .B1(
d_ff_Xn[41]), .Y(n2447) );
INVX2TS U5978 ( .A(n4261), .Y(n4320) );
AO22XLTS U5979 ( .A0(d_ff_Yn[13]), .A1(n4309), .B0(d_ff2_Y[13]), .B1(n4320),
.Y(n2192) );
INVX2TS U5980 ( .A(n4293), .Y(n4329) );
AO22XLTS U5981 ( .A0(n4329), .A1(result_add_subt[8]), .B0(n4328), .B1(
d_ff_Xn[8]), .Y(n2315) );
AO22XLTS U5982 ( .A0(d_ff_Yn[10]), .A1(n4309), .B0(d_ff2_Y[10]), .B1(n4308),
.Y(n2198) );
INVX2TS U5983 ( .A(n4262), .Y(n4314) );
AO22XLTS U5984 ( .A0(d_ff_Yn[42]), .A1(n4310), .B0(d_ff2_Y[42]), .B1(n4314),
.Y(n2134) );
AO22XLTS U5985 ( .A0(n4296), .A1(result_add_subt[42]), .B0(n4295), .B1(
d_ff_Xn[42]), .Y(n2451) );
AO22XLTS U5986 ( .A0(d_ff_Yn[15]), .A1(n4316), .B0(d_ff2_Y[15]), .B1(n4320),
.Y(n2188) );
AO22XLTS U5987 ( .A0(n4329), .A1(result_add_subt[11]), .B0(n4328), .B1(
d_ff_Xn[11]), .Y(n2327) );
AO22XLTS U5988 ( .A0(d_ff_Yn[14]), .A1(n4310), .B0(d_ff2_Y[14]), .B1(n4320),
.Y(n2190) );
INVX2TS U5989 ( .A(n4263), .Y(n4325) );
AO22XLTS U5990 ( .A0(d_ff_Yn[29]), .A1(n4325), .B0(d_ff2_Y[29]), .B1(n4324),
.Y(n2160) );
AO22XLTS U5991 ( .A0(n4329), .A1(result_add_subt[7]), .B0(n4328), .B1(
d_ff_Xn[7]), .Y(n2311) );
AO22XLTS U5992 ( .A0(d_ff_Yn[18]), .A1(n4313), .B0(d_ff2_Y[18]), .B1(n4314),
.Y(n2182) );
AO22XLTS U5993 ( .A0(n4296), .A1(result_add_subt[43]), .B0(n4295), .B1(
d_ff_Xn[43]), .Y(n2455) );
AO22XLTS U5994 ( .A0(d_ff_Yn[25]), .A1(n4325), .B0(d_ff2_Y[25]), .B1(n4984),
.Y(n2168) );
AO22XLTS U5995 ( .A0(n4329), .A1(result_add_subt[13]), .B0(n4328), .B1(
d_ff_Xn[13]), .Y(n2335) );
AO22XLTS U5996 ( .A0(n4294), .A1(result_add_subt[45]), .B0(n4291), .B1(
d_ff_Xn[45]), .Y(n2463) );
AO22XLTS U5997 ( .A0(n4329), .A1(result_add_subt[6]), .B0(n4328), .B1(
d_ff_Xn[6]), .Y(n2307) );
AO22XLTS U5998 ( .A0(n4329), .A1(result_add_subt[9]), .B0(n4328), .B1(
d_ff_Xn[9]), .Y(n2319) );
AO22XLTS U5999 ( .A0(n4294), .A1(result_add_subt[46]), .B0(n4291), .B1(
d_ff_Xn[46]), .Y(n2467) );
AO22XLTS U6000 ( .A0(n4294), .A1(result_add_subt[49]), .B0(n4291), .B1(
d_ff_Xn[49]), .Y(n2479) );
AO22XLTS U6001 ( .A0(d_ff_Yn[22]), .A1(n4325), .B0(d_ff2_Y[22]), .B1(n4984),
.Y(n2174) );
CLKBUFX2TS U6002 ( .A(n4264), .Y(n4326) );
INVX2TS U6003 ( .A(n4326), .Y(n4292) );
AO22XLTS U6004 ( .A0(n4292), .A1(result_add_subt[3]), .B0(n4326), .B1(
d_ff_Xn[3]), .Y(n2295) );
AO22XLTS U6005 ( .A0(n4294), .A1(result_add_subt[48]), .B0(n4291), .B1(
d_ff_Xn[48]), .Y(n2475) );
AO22XLTS U6006 ( .A0(n4294), .A1(result_add_subt[53]), .B0(n4291), .B1(
d_ff_Xn[53]), .Y(n2495) );
AO22XLTS U6007 ( .A0(n4319), .A1(result_add_subt[54]), .B0(n4291), .B1(
d_ff_Xn[54]), .Y(n2499) );
AO22XLTS U6008 ( .A0(n4319), .A1(result_add_subt[55]), .B0(n4318), .B1(
d_ff_Xn[55]), .Y(n2503) );
AO22XLTS U6009 ( .A0(n4292), .A1(result_add_subt[0]), .B0(n4326), .B1(
d_ff_Xn[0]), .Y(n2090) );
AO22XLTS U6010 ( .A0(n4327), .A1(result_add_subt[22]), .B0(n4264), .B1(
d_ff_Xn[22]), .Y(n2371) );
AO22XLTS U6011 ( .A0(n4327), .A1(result_add_subt[17]), .B0(n4264), .B1(
d_ff_Xn[17]), .Y(n2351) );
AO22XLTS U6012 ( .A0(n4323), .A1(result_add_subt[33]), .B0(n4322), .B1(
d_ff_Xn[33]), .Y(n2415) );
AO22XLTS U6013 ( .A0(n4323), .A1(result_add_subt[25]), .B0(n4322), .B1(
d_ff_Xn[25]), .Y(n2383) );
AO22XLTS U6014 ( .A0(n4327), .A1(result_add_subt[18]), .B0(n4264), .B1(
d_ff_Xn[18]), .Y(n2355) );
AO22XLTS U6015 ( .A0(n4327), .A1(result_add_subt[21]), .B0(n4293), .B1(
d_ff_Xn[21]), .Y(n2367) );
NOR2XLTS U6016 ( .A(add_subt_module_Add_Subt_result[32]), .B(
add_subt_module_Add_Subt_result[31]), .Y(n4267) );
NOR2XLTS U6017 ( .A(add_subt_module_Add_Subt_result[36]), .B(
add_subt_module_Add_Subt_result[35]), .Y(n4266) );
OAI22X1TS U6018 ( .A0(n4267), .A1(n4647), .B0(n4266), .B1(n4265), .Y(n4273)
);
NOR2XLTS U6019 ( .A(add_subt_module_Add_Subt_result[20]), .B(
add_subt_module_Add_Subt_result[19]), .Y(n4271) );
NAND2X1TS U6020 ( .A(add_subt_module_Add_Subt_result[24]), .B(n4268), .Y(
n4636) );
OAI211XLTS U6021 ( .A0(n4271), .A1(n4270), .B0(n4636), .C0(n4269), .Y(n4272)
);
NOR3X1TS U6022 ( .A(n4274), .B(n4273), .C(n4272), .Y(n4616) );
NAND2X1TS U6023 ( .A(add_subt_module_Add_Subt_result[34]), .B(n4275), .Y(
n4650) );
OAI31X1TS U6024 ( .A0(add_subt_module_Add_Subt_result[41]), .A1(n4277), .A2(
n4276), .B0(n4650), .Y(n4278) );
NAND2X1TS U6025 ( .A(n4281), .B(add_subt_module_Add_Subt_result[22]), .Y(
n4652) );
CLKAND2X2TS U6026 ( .A(add_subt_module_Add_Subt_result[26]), .B(n4282), .Y(
n4640) );
OAI21XLTS U6027 ( .A0(n4640), .A1(n4283), .B0(n4639), .Y(n4284) );
NAND4XLTS U6028 ( .A(n4616), .B(n4285), .C(n4652), .D(n4284), .Y(n4288) );
NOR2X1TS U6029 ( .A(add_subt_module_Add_Subt_result[2]), .B(
add_subt_module_Add_Subt_result[1]), .Y(n4598) );
INVX2TS U6030 ( .A(n4598), .Y(n4287) );
OAI32X1TS U6031 ( .A0(n4288), .A1(add_subt_module_Add_Subt_result[0]), .A2(
n4287), .B0(n4286), .B1(n4288), .Y(n4289) );
AOI2BB2XLTS U6032 ( .B0(n4290), .B1(n4289), .A0N(n3014), .A1N(
add_subt_module_LZA_output[4]), .Y(n2590) );
AO22XLTS U6033 ( .A0(n4323), .A1(result_add_subt[27]), .B0(n4322), .B1(
d_ff_Xn[27]), .Y(n2391) );
AO22XLTS U6034 ( .A0(n4319), .A1(result_add_subt[63]), .B0(n4293), .B1(
d_ff_Xn[63]), .Y(n2932) );
AO22XLTS U6035 ( .A0(n4327), .A1(result_add_subt[15]), .B0(n4293), .B1(
d_ff_Xn[15]), .Y(n2343) );
AO22XLTS U6036 ( .A0(n4294), .A1(result_add_subt[51]), .B0(n4291), .B1(
d_ff_Xn[51]), .Y(n2487) );
AO22XLTS U6037 ( .A0(n4329), .A1(result_add_subt[4]), .B0(n4326), .B1(
d_ff_Xn[4]), .Y(n2299) );
AO22XLTS U6038 ( .A0(n4323), .A1(result_add_subt[30]), .B0(n4322), .B1(
d_ff_Xn[30]), .Y(n2403) );
AO22XLTS U6039 ( .A0(n4292), .A1(result_add_subt[2]), .B0(n4326), .B1(
d_ff_Xn[2]), .Y(n2291) );
AO22XLTS U6040 ( .A0(n4327), .A1(result_add_subt[23]), .B0(n4297), .B1(
d_ff_Xn[23]), .Y(n2375) );
AO22XLTS U6041 ( .A0(n4294), .A1(result_add_subt[50]), .B0(n4291), .B1(
d_ff_Xn[50]), .Y(n2483) );
AO22XLTS U6042 ( .A0(n4294), .A1(result_add_subt[47]), .B0(n4291), .B1(
d_ff_Xn[47]), .Y(n2471) );
AO22XLTS U6043 ( .A0(n4296), .A1(result_add_subt[37]), .B0(n4295), .B1(
d_ff_Xn[37]), .Y(n2431) );
AO22XLTS U6044 ( .A0(n4292), .A1(result_add_subt[1]), .B0(n4326), .B1(
d_ff_Xn[1]), .Y(n2287) );
AO22XLTS U6045 ( .A0(n4329), .A1(result_add_subt[12]), .B0(n4328), .B1(
d_ff_Xn[12]), .Y(n2331) );
AO22XLTS U6046 ( .A0(n4327), .A1(result_add_subt[16]), .B0(n4293), .B1(
d_ff_Xn[16]), .Y(n2347) );
AO22XLTS U6047 ( .A0(n4294), .A1(result_add_subt[44]), .B0(n4295), .B1(
d_ff_Xn[44]), .Y(n2459) );
AO22XLTS U6048 ( .A0(n4296), .A1(result_add_subt[38]), .B0(n4295), .B1(
d_ff_Xn[38]), .Y(n2435) );
AO22XLTS U6049 ( .A0(n4329), .A1(result_add_subt[5]), .B0(n4328), .B1(
d_ff_Xn[5]), .Y(n2303) );
AO22XLTS U6050 ( .A0(n4296), .A1(result_add_subt[40]), .B0(n4295), .B1(
d_ff_Xn[40]), .Y(n2443) );
AO22XLTS U6051 ( .A0(n4323), .A1(result_add_subt[24]), .B0(n4297), .B1(
d_ff_Xn[24]), .Y(n2379) );
AO22XLTS U6052 ( .A0(d_ff_Xn[63]), .A1(n4313), .B0(d_ff2_X[63]), .B1(n4324),
.Y(n2931) );
AO22XLTS U6053 ( .A0(d_ff_Yn[63]), .A1(n4307), .B0(d_ff2_Y[63]), .B1(n4320),
.Y(n2092) );
AO22XLTS U6054 ( .A0(d_ff_Yn[0]), .A1(n4315), .B0(d_ff2_Y[0]), .B1(n3004),
.Y(n2218) );
AO22XLTS U6055 ( .A0(d_ff_Yn[51]), .A1(n4307), .B0(d_ff2_Y[51]), .B1(n4300),
.Y(n2116) );
AO22XLTS U6056 ( .A0(d_ff_Xn[51]), .A1(n4313), .B0(d_ff2_X[51]), .B1(n3003),
.Y(n2771) );
AO22XLTS U6057 ( .A0(d_ff_Xn[4]), .A1(n4315), .B0(d_ff2_X[4]), .B1(n3216),
.Y(n2677) );
AO22XLTS U6058 ( .A0(d_ff_Yn[48]), .A1(n4321), .B0(d_ff2_Y[48]), .B1(n4300),
.Y(n2122) );
INVX2TS U6059 ( .A(n4100), .Y(n4317) );
AO22XLTS U6060 ( .A0(d_ff_Xn[2]), .A1(n4317), .B0(d_ff2_X[2]), .B1(n3003),
.Y(n2673) );
AO22XLTS U6061 ( .A0(d_ff_Xn[50]), .A1(n4313), .B0(d_ff2_X[50]), .B1(n3017),
.Y(n2769) );
AO22XLTS U6062 ( .A0(d_ff_Yn[47]), .A1(n3763), .B0(d_ff2_Y[47]), .B1(n4300),
.Y(n2124) );
AO22XLTS U6063 ( .A0(d_ff_Xn[47]), .A1(n4317), .B0(d_ff2_X[47]), .B1(n3004),
.Y(n2763) );
AO22XLTS U6064 ( .A0(d_ff_Yn[3]), .A1(n4315), .B0(d_ff2_Y[3]), .B1(n4308),
.Y(n2212) );
AO22XLTS U6065 ( .A0(d_ff_Yn[1]), .A1(n4315), .B0(d_ff2_Y[1]), .B1(n4308),
.Y(n2216) );
AO22XLTS U6066 ( .A0(d_ff_Xn[1]), .A1(n4315), .B0(d_ff2_X[1]), .B1(n3017),
.Y(n2671) );
AO22XLTS U6067 ( .A0(d_ff_Yn[49]), .A1(n4310), .B0(d_ff2_Y[49]), .B1(n4300),
.Y(n2120) );
AO22XLTS U6068 ( .A0(d_ff_Yn[16]), .A1(n4325), .B0(d_ff2_Y[16]), .B1(n4320),
.Y(n2186) );
MX2X1TS U6069 ( .A(add_subt_module_DMP[59]), .B(
add_subt_module_exp_oper_result[7]), .S0(n4588), .Y(
add_subt_module_S_Oper_A_exp[7]) );
MX2X1TS U6070 ( .A(add_subt_module_DMP[60]), .B(
add_subt_module_exp_oper_result[8]), .S0(n4306), .Y(
add_subt_module_S_Oper_A_exp[8]) );
MX2X1TS U6071 ( .A(add_subt_module_DMP[61]), .B(
add_subt_module_exp_oper_result[9]), .S0(n4588), .Y(
add_subt_module_S_Oper_A_exp[9]) );
MX2X1TS U6072 ( .A(add_subt_module_DMP[62]), .B(
add_subt_module_exp_oper_result[10]), .S0(n4592), .Y(
add_subt_module_S_Oper_A_exp[10]) );
AO22XLTS U6073 ( .A0(d_ff_Xn[16]), .A1(n4321), .B0(d_ff2_X[16]), .B1(n3004),
.Y(n2701) );
AO22XLTS U6074 ( .A0(d_ff_Yn[44]), .A1(n4321), .B0(d_ff2_Y[44]), .B1(n4300),
.Y(n2130) );
AO22XLTS U6075 ( .A0(d_ff_Xn[44]), .A1(n4313), .B0(d_ff2_X[44]), .B1(n3216),
.Y(n2757) );
AO22XLTS U6076 ( .A0(d_ff_Yn[5]), .A1(n4309), .B0(d_ff2_Y[5]), .B1(n4308),
.Y(n2208) );
AO22XLTS U6077 ( .A0(d_ff_Xn[5]), .A1(n4317), .B0(d_ff2_X[5]), .B1(n3003),
.Y(n2679) );
AO22XLTS U6078 ( .A0(d_ff_Yn[45]), .A1(n4310), .B0(d_ff2_Y[45]), .B1(n4300),
.Y(n2128) );
AO22XLTS U6079 ( .A0(d_ff_Yn[20]), .A1(n4313), .B0(d_ff2_Y[20]), .B1(n4984),
.Y(n2178) );
AO22XLTS U6080 ( .A0(d_ff_Xn[20]), .A1(n3763), .B0(d_ff2_X[20]), .B1(n3003),
.Y(n2709) );
AO22XLTS U6081 ( .A0(d_ff_Xn[10]), .A1(n4317), .B0(d_ff2_X[10]), .B1(n3017),
.Y(n2689) );
AO22XLTS U6082 ( .A0(d_ff_Yn[43]), .A1(n3763), .B0(d_ff2_Y[43]), .B1(n4300),
.Y(n2132) );
AO22XLTS U6083 ( .A0(d_ff_Yn[7]), .A1(n4309), .B0(d_ff2_Y[7]), .B1(n4308),
.Y(n2204) );
AO22XLTS U6084 ( .A0(d_ff_Yn[40]), .A1(n4309), .B0(d_ff2_Y[40]), .B1(n4314),
.Y(n2138) );
AO22XLTS U6085 ( .A0(d_ff_Yn[53]), .A1(n4307), .B0(d_ff2_Y[53]), .B1(n4300),
.Y(n2113) );
AO22XLTS U6086 ( .A0(d_ff_Xn[40]), .A1(n4317), .B0(d_ff2_X[40]), .B1(n3003),
.Y(n2749) );
AO22XLTS U6087 ( .A0(d_ff_Yn[38]), .A1(n4316), .B0(d_ff2_Y[38]), .B1(n4314),
.Y(n2142) );
AO22XLTS U6088 ( .A0(d_ff_Yn[54]), .A1(n4307), .B0(d_ff2_Y[54]), .B1(n4320),
.Y(n2112) );
AO22XLTS U6089 ( .A0(n2986), .A1(
add_subt_module_Exp_Operation_Module_Data_S[6]), .B0(n2987), .B1(
add_subt_module_exp_oper_result[6]), .Y(n2659) );
NOR2XLTS U6090 ( .A(add_subt_module_FSM_selector_B[1]), .B(
add_subt_module_DmP[52]), .Y(n4304) );
INVX2TS U6091 ( .A(n4302), .Y(n4303) );
OAI21XLTS U6092 ( .A0(add_subt_module_FSM_selector_B[0]), .A1(n4304), .B0(
n4303), .Y(n4305) );
XOR2X1TS U6093 ( .A(n3025), .B(n4305), .Y(DP_OP_92J75_122_9081_n26) );
MX2X1TS U6094 ( .A(add_subt_module_DMP[52]), .B(
add_subt_module_exp_oper_result[0]), .S0(n4588), .Y(
add_subt_module_S_Oper_A_exp[0]) );
MX2X1TS U6095 ( .A(add_subt_module_DMP[53]), .B(
add_subt_module_exp_oper_result[1]), .S0(n4535), .Y(
add_subt_module_S_Oper_A_exp[1]) );
MX2X1TS U6096 ( .A(add_subt_module_DMP[54]), .B(
add_subt_module_exp_oper_result[2]), .S0(n4565), .Y(
add_subt_module_S_Oper_A_exp[2]) );
MX2X1TS U6097 ( .A(add_subt_module_DMP[55]), .B(
add_subt_module_exp_oper_result[3]), .S0(n4564), .Y(
add_subt_module_S_Oper_A_exp[3]) );
MX2X1TS U6098 ( .A(add_subt_module_DMP[56]), .B(
add_subt_module_exp_oper_result[4]), .S0(n4588), .Y(
add_subt_module_S_Oper_A_exp[4]) );
MX2X1TS U6099 ( .A(add_subt_module_DMP[57]), .B(
add_subt_module_exp_oper_result[5]), .S0(n4306), .Y(
add_subt_module_S_Oper_A_exp[5]) );
MX2X1TS U6100 ( .A(add_subt_module_DMP[58]), .B(
add_subt_module_exp_oper_result[6]), .S0(n4535), .Y(
add_subt_module_S_Oper_A_exp[6]) );
AO22XLTS U6101 ( .A0(d_ff_Xn[38]), .A1(n4317), .B0(d_ff2_X[38]), .B1(n3017),
.Y(n2745) );
AO22XLTS U6102 ( .A0(d_ff_Yn[55]), .A1(n4307), .B0(d_ff2_Y[55]), .B1(n4320),
.Y(n2111) );
AO22XLTS U6103 ( .A0(d_ff_Yn[12]), .A1(n4309), .B0(d_ff2_Y[12]), .B1(n4320),
.Y(n2194) );
AO22XLTS U6104 ( .A0(d_ff_Xn[12]), .A1(n4317), .B0(d_ff2_X[12]), .B1(n3004),
.Y(n2693) );
AO22XLTS U6105 ( .A0(d_ff_Yn[11]), .A1(n4309), .B0(d_ff2_Y[11]), .B1(n4320),
.Y(n2196) );
AO22XLTS U6106 ( .A0(d_ff_Yn[8]), .A1(n4309), .B0(d_ff2_Y[8]), .B1(n4308),
.Y(n2202) );
AO22XLTS U6107 ( .A0(d_ff_Yn[41]), .A1(n4321), .B0(d_ff2_Y[41]), .B1(n4314),
.Y(n2136) );
AO22XLTS U6108 ( .A0(d_ff_Yn[39]), .A1(n4316), .B0(d_ff2_Y[39]), .B1(n4314),
.Y(n2140) );
AO22XLTS U6109 ( .A0(d_ff_Yn[37]), .A1(n4316), .B0(d_ff2_Y[37]), .B1(n4314),
.Y(n2144) );
AO22XLTS U6110 ( .A0(d_ff_Xn[37]), .A1(n4317), .B0(d_ff2_X[37]), .B1(n3017),
.Y(n2743) );
AO22XLTS U6111 ( .A0(d_ff_Yn[19]), .A1(n4313), .B0(d_ff2_Y[19]), .B1(n4314),
.Y(n2180) );
AO22XLTS U6112 ( .A0(d_ff_Yn[34]), .A1(n4316), .B0(d_ff2_Y[34]), .B1(n4324),
.Y(n2150) );
AO22XLTS U6113 ( .A0(d_ff_Yn[23]), .A1(n4325), .B0(d_ff2_Y[23]), .B1(n4984),
.Y(n2172) );
INVX2TS U6114 ( .A(n4100), .Y(n4312) );
AO22XLTS U6115 ( .A0(d_ff2_X[62]), .A1(n4984), .B0(d_ff_Xn[62]), .B1(n3846),
.Y(n2793) );
AO22XLTS U6116 ( .A0(d_ff_Xn[23]), .A1(n4315), .B0(d_ff2_X[23]), .B1(n3004),
.Y(n2715) );
AO22XLTS U6117 ( .A0(d_ff_Yn[30]), .A1(n4313), .B0(d_ff2_Y[30]), .B1(n4324),
.Y(n2158) );
AO22XLTS U6118 ( .A0(d_ff_Xn[30]), .A1(n4317), .B0(d_ff2_X[30]), .B1(n3004),
.Y(n2729) );
AO22XLTS U6119 ( .A0(d_ff_Yn[35]), .A1(n4316), .B0(d_ff2_Y[35]), .B1(n4314),
.Y(n2148) );
AO22XLTS U6120 ( .A0(d_ff_Xn[15]), .A1(n4325), .B0(d_ff2_X[15]), .B1(n3003),
.Y(n2699) );
AO22XLTS U6121 ( .A0(d_ff_Yn[36]), .A1(n4316), .B0(d_ff2_Y[36]), .B1(n4314),
.Y(n2146) );
AO22XLTS U6122 ( .A0(d_ff_Yn[27]), .A1(n4325), .B0(d_ff2_Y[27]), .B1(n4324),
.Y(n2164) );
AO22XLTS U6123 ( .A0(d_ff_Xn[27]), .A1(n4315), .B0(d_ff2_X[27]), .B1(n3003),
.Y(n2723) );
AO22XLTS U6124 ( .A0(d_ff_Yn[31]), .A1(n4316), .B0(d_ff2_Y[31]), .B1(n4324),
.Y(n2156) );
AO22XLTS U6125 ( .A0(d_ff_Yn[21]), .A1(n4325), .B0(d_ff2_Y[21]), .B1(n4324),
.Y(n2176) );
AO22XLTS U6126 ( .A0(n4319), .A1(result_add_subt[56]), .B0(n4318), .B1(
d_ff_Xn[56]), .Y(n2507) );
AO22XLTS U6127 ( .A0(d_ff_Xn[21]), .A1(n4315), .B0(d_ff2_X[21]), .B1(n3017),
.Y(n2711) );
AO22XLTS U6128 ( .A0(d_ff_Xn[18]), .A1(n4310), .B0(d_ff2_X[18]), .B1(n3003),
.Y(n2705) );
AO22XLTS U6129 ( .A0(n4319), .A1(result_add_subt[57]), .B0(n4318), .B1(
d_ff_Xn[57]), .Y(n2511) );
AO22XLTS U6130 ( .A0(d_ff_Xn[25]), .A1(n4315), .B0(d_ff2_X[25]), .B1(n3017),
.Y(n2719) );
AO22XLTS U6131 ( .A0(n4319), .A1(result_add_subt[59]), .B0(n4318), .B1(
d_ff_Xn[59]), .Y(n2519) );
AO22XLTS U6132 ( .A0(d_ff_Yn[33]), .A1(n4316), .B0(d_ff2_Y[33]), .B1(n4324),
.Y(n2152) );
AO22XLTS U6133 ( .A0(d_ff_Xn[33]), .A1(n4317), .B0(d_ff2_X[33]), .B1(n3004),
.Y(n2735) );
AO22XLTS U6134 ( .A0(n4319), .A1(result_add_subt[61]), .B0(n4318), .B1(
d_ff_Xn[61]), .Y(n2527) );
AO22XLTS U6135 ( .A0(d_ff_Yn[17]), .A1(n4325), .B0(d_ff2_Y[17]), .B1(n4320),
.Y(n2184) );
AO22XLTS U6136 ( .A0(n4323), .A1(result_add_subt[26]), .B0(n4322), .B1(
d_ff_Xn[26]), .Y(n2387) );
AO22XLTS U6137 ( .A0(d_ff_Xn[17]), .A1(n4321), .B0(d_ff2_X[17]), .B1(n3017),
.Y(n2703) );
AO22XLTS U6138 ( .A0(n4323), .A1(result_add_subt[28]), .B0(n4322), .B1(
d_ff_Xn[28]), .Y(n2395) );
AO22XLTS U6139 ( .A0(d_ff_Yn[24]), .A1(n4325), .B0(d_ff2_Y[24]), .B1(n4324),
.Y(n2170) );
AO22XLTS U6140 ( .A0(n4327), .A1(result_add_subt[20]), .B0(n4326), .B1(
d_ff_Xn[20]), .Y(n2363) );
AO22XLTS U6141 ( .A0(n4329), .A1(result_add_subt[10]), .B0(n4328), .B1(
d_ff_Xn[10]), .Y(n2323) );
AO22XLTS U6142 ( .A0(n4336), .A1(d_ff2_X[10]), .B0(n4141), .B1(
d_ff3_sh_x_out[10]), .Y(n2688) );
AOI22X1TS U6143 ( .A0(n4384), .A1(d_ff3_LUT_out[3]), .B0(n4368), .B1(
d_ff3_sh_y_out[3]), .Y(n4334) );
AOI22X1TS U6144 ( .A0(add_subt_module_intDY[3]), .A1(n4332), .B0(n4374),
.B1(d_ff3_sh_x_out[3]), .Y(n4333) );
NAND2X1TS U6145 ( .A(n4334), .B(n4333), .Y(n1886) );
AO22XLTS U6146 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[28]), .B0(
n3390), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[28]), .Y(n2624)
);
AO22XLTS U6147 ( .A0(n4336), .A1(d_ff2_X[7]), .B0(n4335), .B1(
d_ff3_sh_x_out[7]), .Y(n2682) );
AOI22X1TS U6148 ( .A0(add_subt_module_intDY[55]), .A1(n4461), .B0(n4443),
.B1(d_ff3_sh_y_out[55]), .Y(n4338) );
AOI22X1TS U6149 ( .A0(d_ff3_LUT_out[55]), .A1(n4379), .B0(n4417), .B1(
d_ff3_sh_x_out[55]), .Y(n4337) );
NAND2X1TS U6150 ( .A(n4338), .B(n4337), .Y(n1950) );
AO22XLTS U6151 ( .A0(n4342), .A1(d_ff2_X[41]), .B0(n4160), .B1(
d_ff3_sh_x_out[41]), .Y(n2750) );
NAND4XLTS U6152 ( .A(n4949), .B(n4579), .C(n4340), .D(n4339), .Y(n4936) );
NAND2X1TS U6153 ( .A(n4341), .B(n4936), .Y(n2821) );
AO22XLTS U6154 ( .A0(n4342), .A1(d_ff2_X[39]), .B0(n4354), .B1(
d_ff3_sh_x_out[39]), .Y(n2746) );
AO22XLTS U6155 ( .A0(n4511), .A1(add_subt_module_Add_Subt_result[0]), .B0(
n3390), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[0]), .Y(n2596)
);
AO22XLTS U6156 ( .A0(n4342), .A1(d_ff2_X[34]), .B0(n4349), .B1(
d_ff3_sh_x_out[34]), .Y(n2736) );
AO22XLTS U6157 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[39]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[39]), .Y(n2635)
);
AOI22X1TS U6158 ( .A0(n4344), .A1(d_ff2_Z[31]), .B0(n4343), .B1(d_ff2_X[31]),
.Y(n4346) );
AOI22X1TS U6159 ( .A0(add_subt_module_intDX[31]), .A1(n4423), .B0(n4431),
.B1(d_ff2_Y[31]), .Y(n4345) );
NAND2X1TS U6160 ( .A(n4346), .B(n4345), .Y(n1774) );
AO22XLTS U6161 ( .A0(n4353), .A1(d_ff2_X[31]), .B0(n4141), .B1(
d_ff3_sh_x_out[31]), .Y(n2730) );
AO22XLTS U6162 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[34]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[34]), .Y(n2630)
);
AO22XLTS U6163 ( .A0(n4355), .A1(d_ff2_X[21]), .B0(n4020), .B1(
d_ff3_sh_x_out[21]), .Y(n2710) );
AOI22X1TS U6164 ( .A0(add_subt_module_intDX[8]), .A1(n4013), .B0(n4372),
.B1(d_ff2_X[8]), .Y(n4348) );
AOI22X1TS U6165 ( .A0(n4373), .A1(d_ff2_Z[8]), .B0(n4454), .B1(d_ff2_Y[8]),
.Y(n4347) );
NAND2X1TS U6166 ( .A(n4348), .B(n4347), .Y(n1819) );
AO22XLTS U6167 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[38]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[38]), .Y(n2634)
);
AO22XLTS U6168 ( .A0(n4355), .A1(d_ff2_X[18]), .B0(n4365), .B1(
d_ff3_sh_x_out[18]), .Y(n2704) );
AOI22X1TS U6169 ( .A0(n4430), .A1(d_ff2_Z[17]), .B0(n4436), .B1(d_ff2_X[17]),
.Y(n4351) );
AOI22X1TS U6170 ( .A0(add_subt_module_intDX[17]), .A1(n4432), .B0(n4417),
.B1(d_ff2_Y[17]), .Y(n4350) );
NAND2X1TS U6171 ( .A(n4351), .B(n4350), .Y(n1752) );
AO22XLTS U6172 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[22]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[22]), .Y(n2618)
);
AO22XLTS U6173 ( .A0(n4353), .A1(d_ff2_X[32]), .B0(n4365), .B1(
d_ff3_sh_x_out[32]), .Y(n2732) );
AO22XLTS U6174 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[21]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[21]), .Y(n2617)
);
AO22XLTS U6175 ( .A0(n4355), .A1(d_ff2_X[22]), .B0(n4568), .B1(
d_ff3_sh_x_out[22]), .Y(n2712) );
AOI22X1TS U6176 ( .A0(n4471), .A1(d_ff2_Z[45]), .B0(n4470), .B1(d_ff2_X[45]),
.Y(n4357) );
AOI22X1TS U6177 ( .A0(add_subt_module_intDX[45]), .A1(n4473), .B0(n4472),
.B1(d_ff2_Y[45]), .Y(n4356) );
NAND2X1TS U6178 ( .A(n4357), .B(n4356), .Y(n1857) );
OA21XLTS U6179 ( .A0(n4449), .A1(d_ff3_LUT_out[7]), .B0(n4360), .Y(n2802) );
AOI22X1TS U6180 ( .A0(add_subt_module_intDX[62]), .A1(n4461), .B0(
d_ff2_X[62]), .B1(n4443), .Y(n4362) );
AOI22X1TS U6181 ( .A0(d_ff2_Y[62]), .A1(n4421), .B0(n4466), .B1(d_ff2_Z[62]),
.Y(n4361) );
NAND2X1TS U6182 ( .A(n4362), .B(n4361), .Y(n1942) );
AOI22X1TS U6183 ( .A0(n4444), .A1(d_ff3_LUT_out[53]), .B0(n4443), .B1(
d_ff3_sh_y_out[53]), .Y(n4364) );
AOI22X1TS U6184 ( .A0(add_subt_module_intDY[53]), .A1(n4461), .B0(n4458),
.B1(d_ff3_sh_x_out[53]), .Y(n4363) );
NAND2X1TS U6185 ( .A(n4364), .B(n4363), .Y(n1948) );
NAND2X1TS U6186 ( .A(n4957), .B(n4944), .Y(n4378) );
AO21XLTS U6187 ( .A0(d_ff3_LUT_out[40]), .A1(n4020), .B0(n4378), .Y(n2835)
);
AO21XLTS U6188 ( .A0(d_ff3_LUT_out[36]), .A1(n4507), .B0(n4378), .Y(n2831)
);
AOI22X1TS U6189 ( .A0(add_subt_module_intDX[59]), .A1(n4403), .B0(
d_ff2_X[59]), .B1(n4406), .Y(n4371) );
AOI22X1TS U6190 ( .A0(d_ff2_Y[59]), .A1(n4369), .B0(n4460), .B1(d_ff2_Z[59]),
.Y(n4370) );
NAND2X1TS U6191 ( .A(n4371), .B(n4370), .Y(n1933) );
AOI22X1TS U6192 ( .A0(n4373), .A1(d_ff3_LUT_out[12]), .B0(n4372), .B1(
d_ff3_sh_y_out[12]), .Y(n4377) );
AOI22X1TS U6193 ( .A0(add_subt_module_intDY[12]), .A1(n4375), .B0(n4374),
.B1(d_ff3_sh_x_out[12]), .Y(n4376) );
NAND2X1TS U6194 ( .A(n4377), .B(n4376), .Y(n1828) );
AO21XLTS U6195 ( .A0(d_ff3_LUT_out[28]), .A1(n4020), .B0(n4378), .Y(n2823)
);
AOI22X1TS U6196 ( .A0(n4400), .A1(d_ff2_Y[6]), .B0(n4470), .B1(d_ff2_X[6]),
.Y(n4381) );
AOI22X1TS U6197 ( .A0(add_subt_module_intDX[6]), .A1(n4473), .B0(n4379),
.B1(d_ff2_Z[6]), .Y(n4380) );
NAND2X1TS U6198 ( .A(n4381), .B(n4380), .Y(n1863) );
NAND2X1TS U6199 ( .A(n4494), .B(n5084), .Y(n4493) );
NAND2X1TS U6200 ( .A(n4451), .B(n5085), .Y(n4448) );
NOR2X1TS U6201 ( .A(d_ff2_X[61]), .B(n4448), .Y(n4447) );
XOR2XLTS U6202 ( .A(d_ff2_X[62]), .B(n4447), .Y(n4383) );
AO22XLTS U6203 ( .A0(n4570), .A1(n4383), .B0(n4352), .B1(d_ff3_sh_x_out[62]),
.Y(n2772) );
AOI22X1TS U6204 ( .A0(n4384), .A1(d_ff3_LUT_out[54]), .B0(n4443), .B1(
d_ff3_sh_y_out[54]), .Y(n4386) );
AOI22X1TS U6205 ( .A0(add_subt_module_intDY[54]), .A1(n4461), .B0(n4458),
.B1(d_ff3_sh_x_out[54]), .Y(n4385) );
NAND2X1TS U6206 ( .A(n4386), .B(n4385), .Y(n1949) );
OAI21XLTS U6207 ( .A0(n4451), .A1(n5085), .B0(n4448), .Y(n4387) );
AO22XLTS U6208 ( .A0(n4496), .A1(n4387), .B0(n4349), .B1(d_ff3_sh_x_out[60]),
.Y(n2774) );
AO22XLTS U6209 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[51]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[51]), .Y(n2647)
);
AOI22X1TS U6210 ( .A0(n4389), .A1(d_ff2_Z[44]), .B0(n4388), .B1(d_ff2_X[44]),
.Y(n4391) );
AOI22X1TS U6211 ( .A0(add_subt_module_intDX[44]), .A1(n4473), .B0(n4472),
.B1(d_ff2_Y[44]), .Y(n4390) );
NAND2X1TS U6212 ( .A(n4391), .B(n4390), .Y(n1867) );
AOI21X1TS U6213 ( .A0(d_ff2_Y[61]), .A1(n4393), .B0(n4392), .Y(n4394) );
AOI2BB2XLTS U6214 ( .B0(n4476), .B1(n4394), .A0N(d_ff3_sh_y_out[61]), .A1N(
n4449), .Y(n2094) );
AO22XLTS U6215 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[29]), .B0(
n3390), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[29]), .Y(n2625)
);
AOI22X1TS U6216 ( .A0(n4369), .A1(d_ff2_Y[4]), .B0(n4406), .B1(d_ff2_X[4]),
.Y(n4396) );
AOI22X1TS U6217 ( .A0(add_subt_module_intDX[4]), .A1(n4403), .B0(n4422),
.B1(d_ff2_Z[4]), .Y(n4395) );
NAND2X1TS U6218 ( .A(n4396), .B(n4395), .Y(n1904) );
AOI21X1TS U6219 ( .A0(d_ff2_Y[59]), .A1(n4398), .B0(n4397), .Y(n4399) );
AOI2BB2XLTS U6220 ( .B0(n4476), .B1(n4399), .A0N(d_ff3_sh_y_out[59]), .A1N(
n4449), .Y(n2096) );
AO22XLTS U6221 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[12]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[12]), .Y(n2608)
);
AOI22X1TS U6222 ( .A0(n4400), .A1(d_ff3_sh_x_out[32]), .B0(n4459), .B1(
d_ff3_sh_y_out[32]), .Y(n4402) );
AOI22X1TS U6223 ( .A0(add_subt_module_intDY[32]), .A1(n4438), .B0(n4460),
.B1(d_ff3_LUT_out[32]), .Y(n4401) );
NAND2X1TS U6224 ( .A(n4402), .B(n4401), .Y(n1748) );
AO22XLTS U6225 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[8]), .B0(
n4581), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[8]), .Y(n2604)
);
AOI22X1TS U6226 ( .A0(add_subt_module_intDX[56]), .A1(n4403), .B0(
d_ff2_X[56]), .B1(n4443), .Y(n4405) );
AOI22X1TS U6227 ( .A0(d_ff2_Y[56]), .A1(n4421), .B0(n4422), .B1(d_ff2_Z[56]),
.Y(n4404) );
NAND2X1TS U6228 ( .A(n4405), .B(n4404), .Y(n1924) );
AOI2BB1XLTS U6229 ( .A0N(n4509), .A1N(d_ff3_LUT_out[47]), .B0(n4410), .Y(
n2842) );
AOI22X1TS U6230 ( .A0(n4369), .A1(d_ff2_Y[50]), .B0(n4406), .B1(d_ff2_X[50]),
.Y(n4409) );
AOI22X1TS U6231 ( .A0(add_subt_module_intDX[50]), .A1(n4407), .B0(n4460),
.B1(d_ff2_Z[50]), .Y(n4408) );
NAND2X1TS U6232 ( .A(n4409), .B(n4408), .Y(n1894) );
AOI2BB1XLTS U6233 ( .A0N(n4509), .A1N(d_ff3_LUT_out[42]), .B0(n4410), .Y(
n2837) );
AO22XLTS U6234 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[30]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[30]), .Y(n2626)
);
AOI2BB1XLTS U6235 ( .A0N(n4509), .A1N(d_ff3_LUT_out[17]), .B0(n4942), .Y(
n2812) );
AO22XLTS U6236 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[44]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[44]), .Y(n2640)
);
OA21XLTS U6237 ( .A0(n4449), .A1(d_ff3_LUT_out[37]), .B0(n4411), .Y(n2832)
);
AOI22X1TS U6238 ( .A0(add_subt_module_intDX[37]), .A1(n4013), .B0(n4464),
.B1(d_ff2_X[37]), .Y(n4414) );
AOI22X1TS U6239 ( .A0(n4412), .A1(d_ff2_Z[37]), .B0(n4454), .B1(d_ff2_Y[37]),
.Y(n4413) );
NAND2X1TS U6240 ( .A(n4414), .B(n4413), .Y(n1809) );
OA21XLTS U6241 ( .A0(n4449), .A1(d_ff3_LUT_out[2]), .B0(n4415), .Y(n2797) );
AOI22X1TS U6242 ( .A0(d_ff3_LUT_out[35]), .A1(n4444), .B0(n4416), .B1(
d_ff3_sh_y_out[35]), .Y(n4419) );
AOI22X1TS U6243 ( .A0(add_subt_module_intDY[35]), .A1(n4467), .B0(n4417),
.B1(d_ff3_sh_x_out[35]), .Y(n4418) );
NAND2X1TS U6244 ( .A(n4419), .B(n4418), .Y(n1791) );
AO22XLTS U6245 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[48]), .B0(
n4581), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[48]), .Y(n2644)
);
AOI2BB1XLTS U6246 ( .A0N(n4509), .A1N(d_ff3_LUT_out[35]), .B0(n4933), .Y(
n2830) );
AOI22X1TS U6247 ( .A0(n4421), .A1(d_ff2_Y[14]), .B0(n4420), .B1(d_ff2_X[14]),
.Y(n4425) );
AOI22X1TS U6248 ( .A0(add_subt_module_intDX[14]), .A1(n4423), .B0(n4422),
.B1(d_ff2_Z[14]), .Y(n4424) );
NAND2X1TS U6249 ( .A(n4425), .B(n4424), .Y(n1781) );
AO22XLTS U6250 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[36]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[36]), .Y(n2632)
);
AOI21X1TS U6251 ( .A0(n4428), .A1(n4960), .B0(n4427), .Y(n4429) );
AOI2BB1XLTS U6252 ( .A0N(n4959), .A1N(d_ff3_LUT_out[6]), .B0(n4429), .Y(
n2801) );
AOI22X1TS U6253 ( .A0(n4430), .A1(d_ff3_LUT_out[33]), .B0(n4436), .B1(
d_ff3_sh_y_out[33]), .Y(n4434) );
AOI22X1TS U6254 ( .A0(add_subt_module_intDY[33]), .A1(n4432), .B0(n4431),
.B1(d_ff3_sh_x_out[33]), .Y(n4433) );
NAND2X1TS U6255 ( .A(n4434), .B(n4433), .Y(n1755) );
AOI2BB2XLTS U6256 ( .B0(n4476), .B1(n4435), .A0N(d_ff3_LUT_out[50]), .A1N(
n4449), .Y(n2845) );
AO22XLTS U6257 ( .A0(n4511), .A1(add_subt_module_Add_Subt_result[2]), .B0(
n4485), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[2]), .Y(n2598)
);
AOI22X1TS U6258 ( .A0(n4437), .A1(d_ff3_sh_x_out[22]), .B0(n4436), .B1(
d_ff3_sh_y_out[22]), .Y(n4440) );
AOI22X1TS U6259 ( .A0(add_subt_module_intDY[22]), .A1(n4438), .B0(n4466),
.B1(d_ff3_LUT_out[22]), .Y(n4439) );
NAND2X1TS U6260 ( .A(n4440), .B(n4439), .Y(n1741) );
AOI21X1TS U6261 ( .A0(d_ff2_X[57]), .A1(n4441), .B0(n4494), .Y(n4442) );
AOI2BB2XLTS U6262 ( .B0(n4476), .B1(n4442), .A0N(d_ff3_sh_x_out[57]), .A1N(
n4449), .Y(n2777) );
AOI22X1TS U6263 ( .A0(add_subt_module_intDY[52]), .A1(n4461), .B0(n4443),
.B1(d_ff3_sh_y_out[52]), .Y(n4446) );
AOI22X1TS U6264 ( .A0(n4444), .A1(d_ff3_LUT_out[52]), .B0(n4458), .B1(
d_ff3_sh_x_out[52]), .Y(n4445) );
NAND2X1TS U6265 ( .A(n4446), .B(n4445), .Y(n1947) );
AO22XLTS U6266 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[23]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[23]), .Y(n2619)
);
AOI21X1TS U6267 ( .A0(d_ff2_X[61]), .A1(n4448), .B0(n4447), .Y(n4450) );
AOI2BB2XLTS U6268 ( .B0(n4476), .B1(n4450), .A0N(d_ff3_sh_x_out[61]), .A1N(
n4449), .Y(n2773) );
AOI21X1TS U6269 ( .A0(d_ff2_X[59]), .A1(n4493), .B0(n4451), .Y(n4452) );
AOI2BB2XLTS U6270 ( .B0(n4476), .B1(n4452), .A0N(d_ff3_sh_x_out[59]), .A1N(
n4496), .Y(n2775) );
AO22XLTS U6271 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[31]), .B0(
n4485), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[31]), .Y(n2627)
);
AO22XLTS U6272 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[52]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[52]), .Y(n2648)
);
AOI22X1TS U6273 ( .A0(n4471), .A1(d_ff3_LUT_out[26]), .B0(n4453), .B1(
d_ff3_sh_y_out[26]), .Y(n4457) );
AOI22X1TS U6274 ( .A0(add_subt_module_intDY[26]), .A1(n4455), .B0(n4454),
.B1(d_ff3_sh_x_out[26]), .Y(n4456) );
NAND2X1TS U6275 ( .A(n4457), .B(n4456), .Y(n1734) );
AO22XLTS U6276 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[19]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[19]), .Y(n2615)
);
AOI22X1TS U6277 ( .A0(d_ff2_X[61]), .A1(n4459), .B0(d_ff2_Y[61]), .B1(n4331),
.Y(n4463) );
AOI22X1TS U6278 ( .A0(add_subt_module_intDX[61]), .A1(n4461), .B0(n4460),
.B1(d_ff2_Z[61]), .Y(n4462) );
NAND2X1TS U6279 ( .A(n4463), .B(n4462), .Y(n1939) );
AOI22X1TS U6280 ( .A0(n4465), .A1(d_ff3_sh_x_out[34]), .B0(n4464), .B1(
d_ff3_sh_y_out[34]), .Y(n4469) );
AOI22X1TS U6281 ( .A0(add_subt_module_intDY[34]), .A1(n4467), .B0(
d_ff3_LUT_out[34]), .B1(n4466), .Y(n4468) );
NAND2X1TS U6282 ( .A(n4469), .B(n4468), .Y(n1800) );
AOI22X1TS U6283 ( .A0(n4471), .A1(d_ff2_Z[5]), .B0(n4470), .B1(d_ff2_X[5]),
.Y(n4475) );
AOI22X1TS U6284 ( .A0(add_subt_module_intDX[5]), .A1(n4473), .B0(n4472),
.B1(d_ff2_Y[5]), .Y(n4474) );
NAND2X1TS U6285 ( .A(n4475), .B(n4474), .Y(n1860) );
OAI21XLTS U6286 ( .A0(d_ff3_LUT_out[31]), .A1(n4476), .B0(n4955), .Y(n4478)
);
NAND2X1TS U6287 ( .A(n4478), .B(n4477), .Y(n2826) );
AO22XLTS U6288 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[4]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[4]), .Y(n2600)
);
AO21XLTS U6289 ( .A0(d_ff3_LUT_out[29]), .A1(n4568), .B0(n4479), .Y(n2824)
);
AO21XLTS U6290 ( .A0(d_ff3_LUT_out[38]), .A1(n4160), .B0(n4484), .Y(n2833)
);
NOR2XLTS U6291 ( .A(n3026), .B(n2985), .Y(n4482) );
OAI21XLTS U6292 ( .A0(n4482), .A1(n4481), .B0(n4480), .Y(n4483) );
AOI2BB2XLTS U6293 ( .B0(n4484), .B1(n4483), .A0N(n4932), .A1N(
d_ff3_LUT_out[9]), .Y(n2804) );
AO22XLTS U6294 ( .A0(n4486), .A1(add_subt_module_Add_Subt_result[35]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[35]), .Y(n2631)
);
AOI21X1TS U6295 ( .A0(n4577), .A1(n5023), .B0(n4487), .Y(n4488) );
AO21XLTS U6296 ( .A0(d_ff3_LUT_out[20]), .A1(n4354), .B0(n4488), .Y(n2815)
);
AO22XLTS U6297 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[14]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[14]), .Y(n2610)
);
AO21XLTS U6298 ( .A0(d_ff3_LUT_out[44]), .A1(n4568), .B0(n4506), .Y(n2839)
);
AO22XLTS U6299 ( .A0(n4496), .A1(n3026), .B0(n4354), .B1(d_ff3_LUT_out[52]),
.Y(n2846) );
AO22XLTS U6300 ( .A0(n4511), .A1(add_subt_module_Add_Subt_result[1]), .B0(
n3390), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[1]), .Y(n2597)
);
AO22XLTS U6301 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[10]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[10]), .Y(n2606)
);
INVX2TS U6302 ( .A(n4578), .Y(n4490) );
AOI2BB2XLTS U6303 ( .B0(n4491), .B1(n4490), .A0N(n4932), .A1N(
d_ff3_LUT_out[5]), .Y(n2800) );
AO22XLTS U6304 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[41]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[41]), .Y(n2637)
);
OAI21XLTS U6305 ( .A0(n4494), .A1(n5084), .B0(n4493), .Y(n4495) );
AO22XLTS U6306 ( .A0(n4496), .A1(n4495), .B0(n4141), .B1(d_ff3_sh_x_out[58]),
.Y(n2776) );
OAI31X1TS U6307 ( .A0(add_subt_module_FSM_selector_C), .A1(n4499), .A2(n4498), .B0(n4497), .Y(n4918) );
OAI211XLTS U6308 ( .A0(n4502), .A1(n4501), .B0(n4500), .C0(n4499), .Y(n4503)
);
NAND4BXLTS U6309 ( .AN(n4918), .B(n4969), .C(n4504), .D(n4503), .Y(n2928) );
AO22XLTS U6310 ( .A0(n4505), .A1(add_subt_module_Add_Subt_result[26]), .B0(
n4485), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[26]), .Y(n2622)
);
AO21XLTS U6311 ( .A0(d_ff3_LUT_out[49]), .A1(n4160), .B0(n4506), .Y(n2844)
);
AO21XLTS U6312 ( .A0(d_ff3_LUT_out[46]), .A1(n4507), .B0(n4506), .Y(n2841)
);
AO22XLTS U6313 ( .A0(n4509), .A1(d_ff2_X[0]), .B0(n4349), .B1(
d_ff3_sh_x_out[0]), .Y(n2668) );
AO22XLTS U6314 ( .A0(n4511), .A1(add_subt_module_Add_Subt_result[54]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[54]), .Y(n2595)
);
MX2X1TS U6315 ( .A(add_subt_module_DMP[48]), .B(
add_subt_module_Sgf_normalized_result[50]), .S0(n4306), .Y(
add_subt_module_S_A_S_Oper_A[50]) );
NOR2XLTS U6316 ( .A(n4306), .B(n5154), .Y(n4512) );
XOR2X1TS U6317 ( .A(n5273), .B(n4512), .Y(DP_OP_95J75_125_7728_n64) );
MX2X1TS U6318 ( .A(add_subt_module_DMP[49]), .B(
add_subt_module_Sgf_normalized_result[51]), .S0(n4535), .Y(
add_subt_module_S_A_S_Oper_A[51]) );
INVX2TS U6319 ( .A(n4551), .Y(n4565) );
NOR2XLTS U6320 ( .A(n4565), .B(n5153), .Y(n4513) );
XOR2X1TS U6321 ( .A(n5273), .B(n4513), .Y(DP_OP_95J75_125_7728_n63) );
MX2X1TS U6322 ( .A(add_subt_module_DMP[50]), .B(
add_subt_module_Sgf_normalized_result[52]), .S0(n4565), .Y(
add_subt_module_S_A_S_Oper_A[52]) );
NOR2XLTS U6323 ( .A(n4535), .B(n5152), .Y(n4514) );
XOR2X1TS U6324 ( .A(n5273), .B(n4514), .Y(DP_OP_95J75_125_7728_n62) );
MX2X1TS U6325 ( .A(add_subt_module_DMP[51]), .B(
add_subt_module_Sgf_normalized_result[53]), .S0(n4564), .Y(
add_subt_module_S_A_S_Oper_A[53]) );
NOR2XLTS U6326 ( .A(n4564), .B(n5151), .Y(n4515) );
XOR2X1TS U6327 ( .A(n5273), .B(n4515), .Y(DP_OP_95J75_125_7728_n61) );
NAND2BXLTS U6328 ( .AN(add_subt_module_Sgf_normalized_result[54]), .B(n4564),
.Y(add_subt_module_S_A_S_Oper_A[54]) );
CLKAND2X2TS U6329 ( .A(add_subt_module_Sgf_normalized_result[54]), .B(n5202),
.Y(n4516) );
XOR2X1TS U6330 ( .A(n5273), .B(n4516), .Y(DP_OP_95J75_125_7728_n60) );
AO22XLTS U6331 ( .A0(n4517), .A1(add_subt_module_Add_Subt_result[49]), .B0(
n4492), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[49]), .Y(n2645)
);
MX2X1TS U6332 ( .A(add_subt_module_DMP[44]), .B(
add_subt_module_Sgf_normalized_result[46]), .S0(n4588), .Y(
add_subt_module_S_A_S_Oper_A[46]) );
CLKBUFX3TS U6333 ( .A(n4540), .Y(n4567) );
NOR2XLTS U6334 ( .A(n4588), .B(n5158), .Y(n4518) );
XOR2X1TS U6335 ( .A(n4567), .B(n4518), .Y(DP_OP_95J75_125_7728_n68) );
MX2X1TS U6336 ( .A(add_subt_module_DMP[45]), .B(
add_subt_module_Sgf_normalized_result[47]), .S0(n4306), .Y(
add_subt_module_S_A_S_Oper_A[47]) );
NOR2XLTS U6337 ( .A(n4306), .B(n5157), .Y(n4519) );
XOR2X1TS U6338 ( .A(n5273), .B(n4519), .Y(DP_OP_95J75_125_7728_n67) );
MX2X1TS U6339 ( .A(add_subt_module_DMP[46]), .B(
add_subt_module_Sgf_normalized_result[48]), .S0(n4535), .Y(
add_subt_module_S_A_S_Oper_A[48]) );
NOR2XLTS U6340 ( .A(n4535), .B(n5156), .Y(n4520) );
XOR2X1TS U6341 ( .A(n5273), .B(n4520), .Y(DP_OP_95J75_125_7728_n66) );
MX2X1TS U6342 ( .A(add_subt_module_DMP[47]), .B(
add_subt_module_Sgf_normalized_result[49]), .S0(n4565), .Y(
add_subt_module_S_A_S_Oper_A[49]) );
XOR2X1TS U6343 ( .A(n5273), .B(n4521), .Y(DP_OP_95J75_125_7728_n65) );
AO22XLTS U6344 ( .A0(n4522), .A1(add_subt_module_Add_Subt_result[15]), .B0(
n4489), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[15]), .Y(n2611)
);
AO22XLTS U6345 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[45]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[45]), .Y(n2641)
);
MX2X1TS U6346 ( .A(add_subt_module_DMP[10]), .B(
add_subt_module_Sgf_normalized_result[12]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[12]) );
CLKBUFX3TS U6347 ( .A(n4540), .Y(n4595) );
INVX2TS U6348 ( .A(n4551), .Y(n4575) );
NOR2XLTS U6349 ( .A(n4575), .B(n5183), .Y(n4523) );
XOR2X1TS U6350 ( .A(n4595), .B(n4523), .Y(DP_OP_95J75_125_7728_n102) );
MX2X1TS U6351 ( .A(add_subt_module_DMP[11]), .B(
add_subt_module_Sgf_normalized_result[13]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[13]) );
NOR2XLTS U6352 ( .A(n4593), .B(n5182), .Y(n4524) );
XOR2X1TS U6353 ( .A(n4595), .B(n4524), .Y(DP_OP_95J75_125_7728_n101) );
MX2X1TS U6354 ( .A(add_subt_module_DMP[12]), .B(
add_subt_module_Sgf_normalized_result[14]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[14]) );
NOR2XLTS U6355 ( .A(n4575), .B(n5181), .Y(n4525) );
XOR2X1TS U6356 ( .A(n4595), .B(n4525), .Y(DP_OP_95J75_125_7728_n100) );
MX2X1TS U6357 ( .A(add_subt_module_DMP[13]), .B(
add_subt_module_Sgf_normalized_result[15]), .S0(n4565), .Y(
add_subt_module_S_A_S_Oper_A[15]) );
NOR2XLTS U6358 ( .A(n4575), .B(n5180), .Y(n4526) );
XOR2X1TS U6359 ( .A(n4595), .B(n4526), .Y(DP_OP_95J75_125_7728_n99) );
MX2X1TS U6360 ( .A(add_subt_module_DMP[14]), .B(
add_subt_module_Sgf_normalized_result[16]), .S0(n4564), .Y(
add_subt_module_S_A_S_Oper_A[16]) );
NOR2XLTS U6361 ( .A(n4575), .B(n5179), .Y(n4527) );
XOR2X1TS U6362 ( .A(n4595), .B(n4527), .Y(DP_OP_95J75_125_7728_n98) );
MX2X1TS U6363 ( .A(add_subt_module_DMP[15]), .B(
add_subt_module_Sgf_normalized_result[17]), .S0(n4588), .Y(
add_subt_module_S_A_S_Oper_A[17]) );
CLKBUFX3TS U6364 ( .A(n4540), .Y(n4539) );
NOR2XLTS U6365 ( .A(n4575), .B(n5178), .Y(n4528) );
XOR2X1TS U6366 ( .A(n4539), .B(n4528), .Y(DP_OP_95J75_125_7728_n97) );
MX2X1TS U6367 ( .A(add_subt_module_DMP[16]), .B(
add_subt_module_Sgf_normalized_result[18]), .S0(n4306), .Y(
add_subt_module_S_A_S_Oper_A[18]) );
NOR2XLTS U6368 ( .A(n4575), .B(n5177), .Y(n4529) );
XOR2X1TS U6369 ( .A(n4539), .B(n4529), .Y(DP_OP_95J75_125_7728_n96) );
MX2X1TS U6370 ( .A(add_subt_module_DMP[17]), .B(
add_subt_module_Sgf_normalized_result[19]), .S0(n4535), .Y(
add_subt_module_S_A_S_Oper_A[19]) );
NOR2XLTS U6371 ( .A(n4575), .B(n5176), .Y(n4530) );
XOR2X1TS U6372 ( .A(n4539), .B(n4530), .Y(DP_OP_95J75_125_7728_n95) );
MX2X1TS U6373 ( .A(add_subt_module_DMP[18]), .B(
add_subt_module_Sgf_normalized_result[20]), .S0(n4565), .Y(
add_subt_module_S_A_S_Oper_A[20]) );
INVX2TS U6374 ( .A(n5202), .Y(n4547) );
NOR2XLTS U6375 ( .A(n4547), .B(n5175), .Y(n4531) );
XOR2X1TS U6376 ( .A(n4539), .B(n4531), .Y(DP_OP_95J75_125_7728_n94) );
MX2X1TS U6377 ( .A(add_subt_module_DMP[19]), .B(
add_subt_module_Sgf_normalized_result[21]), .S0(n4564), .Y(
add_subt_module_S_A_S_Oper_A[21]) );
NOR2XLTS U6378 ( .A(n4575), .B(n5174), .Y(n4532) );
XOR2X1TS U6379 ( .A(n4539), .B(n4532), .Y(DP_OP_95J75_125_7728_n93) );
MX2X1TS U6380 ( .A(add_subt_module_DMP[20]), .B(
add_subt_module_Sgf_normalized_result[22]), .S0(n4588), .Y(
add_subt_module_S_A_S_Oper_A[22]) );
NOR2XLTS U6381 ( .A(n4547), .B(n5173), .Y(n4533) );
XOR2X1TS U6382 ( .A(n4539), .B(n4533), .Y(DP_OP_95J75_125_7728_n92) );
MX2X1TS U6383 ( .A(add_subt_module_DMP[21]), .B(
add_subt_module_Sgf_normalized_result[23]), .S0(n4306), .Y(
add_subt_module_S_A_S_Oper_A[23]) );
XOR2X1TS U6384 ( .A(n4539), .B(n4534), .Y(DP_OP_95J75_125_7728_n91) );
MX2X1TS U6385 ( .A(add_subt_module_DMP[22]), .B(
add_subt_module_Sgf_normalized_result[24]), .S0(n4535), .Y(
add_subt_module_S_A_S_Oper_A[24]) );
NOR2XLTS U6386 ( .A(n4547), .B(n5199), .Y(n4536) );
XOR2X1TS U6387 ( .A(n4539), .B(n4536), .Y(DP_OP_95J75_125_7728_n90) );
MX2X1TS U6388 ( .A(add_subt_module_DMP[23]), .B(
add_subt_module_Sgf_normalized_result[25]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[25]) );
NOR2XLTS U6389 ( .A(n4547), .B(n5198), .Y(n4537) );
XOR2X1TS U6390 ( .A(n4539), .B(n4537), .Y(DP_OP_95J75_125_7728_n89) );
MX2X1TS U6391 ( .A(add_subt_module_DMP[24]), .B(
add_subt_module_Sgf_normalized_result[26]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[26]) );
XOR2X1TS U6392 ( .A(n4539), .B(n4538), .Y(DP_OP_95J75_125_7728_n88) );
MX2X1TS U6393 ( .A(add_subt_module_DMP[25]), .B(
add_subt_module_Sgf_normalized_result[27]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[27]) );
CLKBUFX3TS U6394 ( .A(n4540), .Y(n4560) );
NOR2XLTS U6395 ( .A(n4547), .B(n5072), .Y(n4541) );
XOR2X1TS U6396 ( .A(n4560), .B(n4541), .Y(DP_OP_95J75_125_7728_n87) );
MX2X1TS U6397 ( .A(add_subt_module_DMP[26]), .B(
add_subt_module_Sgf_normalized_result[28]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[28]) );
NOR2XLTS U6398 ( .A(n4547), .B(n5196), .Y(n4542) );
XOR2X1TS U6399 ( .A(n4560), .B(n4542), .Y(DP_OP_95J75_125_7728_n86) );
MX2X1TS U6400 ( .A(add_subt_module_DMP[27]), .B(
add_subt_module_Sgf_normalized_result[29]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[29]) );
NOR2XLTS U6401 ( .A(n4547), .B(n5195), .Y(n4543) );
XOR2X1TS U6402 ( .A(n4560), .B(n4543), .Y(DP_OP_95J75_125_7728_n85) );
MX2X1TS U6403 ( .A(add_subt_module_DMP[28]), .B(
add_subt_module_Sgf_normalized_result[30]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[30]) );
NOR2XLTS U6404 ( .A(n5009), .B(n5194), .Y(n4544) );
XOR2X1TS U6405 ( .A(n4560), .B(n4544), .Y(DP_OP_95J75_125_7728_n84) );
MX2X1TS U6406 ( .A(add_subt_module_DMP[29]), .B(
add_subt_module_Sgf_normalized_result[31]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[31]) );
NOR2XLTS U6407 ( .A(n4547), .B(n5193), .Y(n4545) );
XOR2X1TS U6408 ( .A(n4560), .B(n4545), .Y(DP_OP_95J75_125_7728_n83) );
MX2X1TS U6409 ( .A(add_subt_module_DMP[30]), .B(
add_subt_module_Sgf_normalized_result[32]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[32]) );
NOR2XLTS U6410 ( .A(n5009), .B(n5172), .Y(n4546) );
XOR2X1TS U6411 ( .A(n4560), .B(n4546), .Y(DP_OP_95J75_125_7728_n82) );
MX2X1TS U6412 ( .A(add_subt_module_DMP[31]), .B(
add_subt_module_Sgf_normalized_result[33]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[33]) );
NOR2XLTS U6413 ( .A(n4547), .B(n5171), .Y(n4548) );
XOR2X1TS U6414 ( .A(n4560), .B(n4548), .Y(DP_OP_95J75_125_7728_n81) );
MX2X1TS U6415 ( .A(add_subt_module_DMP[32]), .B(
add_subt_module_Sgf_normalized_result[34]), .S0(n4549), .Y(
add_subt_module_S_A_S_Oper_A[34]) );
NOR2XLTS U6416 ( .A(n5009), .B(n5170), .Y(n4550) );
XOR2X1TS U6417 ( .A(n4560), .B(n4550), .Y(DP_OP_95J75_125_7728_n80) );
MX2X1TS U6418 ( .A(add_subt_module_DMP[33]), .B(
add_subt_module_Sgf_normalized_result[35]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[35]) );
NOR2XLTS U6419 ( .A(n5009), .B(n5169), .Y(n4552) );
XOR2X1TS U6420 ( .A(n4560), .B(n4552), .Y(DP_OP_95J75_125_7728_n79) );
MX2X1TS U6421 ( .A(add_subt_module_DMP[34]), .B(
add_subt_module_Sgf_normalized_result[36]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[36]) );
NOR2XLTS U6422 ( .A(n5009), .B(n5168), .Y(n4553) );
XOR2X1TS U6423 ( .A(n4567), .B(n4553), .Y(DP_OP_95J75_125_7728_n78) );
MX2X1TS U6424 ( .A(add_subt_module_DMP[35]), .B(
add_subt_module_Sgf_normalized_result[37]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[37]) );
NOR2XLTS U6425 ( .A(n5009), .B(n5167), .Y(n4554) );
XOR2X1TS U6426 ( .A(n4567), .B(n4554), .Y(DP_OP_95J75_125_7728_n77) );
MX2X1TS U6427 ( .A(add_subt_module_DMP[36]), .B(
add_subt_module_Sgf_normalized_result[38]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[38]) );
NOR2XLTS U6428 ( .A(n5009), .B(n5166), .Y(n4555) );
XOR2X1TS U6429 ( .A(n4567), .B(n4555), .Y(DP_OP_95J75_125_7728_n76) );
MX2X1TS U6430 ( .A(add_subt_module_DMP[37]), .B(
add_subt_module_Sgf_normalized_result[39]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[39]) );
NOR2XLTS U6431 ( .A(n5009), .B(n5165), .Y(n4556) );
XOR2X1TS U6432 ( .A(n4567), .B(n4556), .Y(DP_OP_95J75_125_7728_n75) );
MX2X1TS U6433 ( .A(add_subt_module_DMP[38]), .B(
add_subt_module_Sgf_normalized_result[40]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[40]) );
NOR2XLTS U6434 ( .A(n4565), .B(n5164), .Y(n4557) );
XOR2X1TS U6435 ( .A(n4567), .B(n4557), .Y(DP_OP_95J75_125_7728_n74) );
MX2X1TS U6436 ( .A(add_subt_module_DMP[39]), .B(
add_subt_module_Sgf_normalized_result[41]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[41]) );
NOR2XLTS U6437 ( .A(n5009), .B(n5163), .Y(n4558) );
XOR2X1TS U6438 ( .A(n4567), .B(n4558), .Y(DP_OP_95J75_125_7728_n73) );
MX2X1TS U6439 ( .A(add_subt_module_DMP[40]), .B(
add_subt_module_Sgf_normalized_result[42]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[42]) );
XOR2X1TS U6440 ( .A(n4560), .B(n4559), .Y(DP_OP_95J75_125_7728_n72) );
MX2X1TS U6441 ( .A(add_subt_module_DMP[41]), .B(
add_subt_module_Sgf_normalized_result[43]), .S0(n4562), .Y(
add_subt_module_S_A_S_Oper_A[43]) );
NOR2XLTS U6442 ( .A(n5009), .B(n5161), .Y(n4561) );
XOR2X1TS U6443 ( .A(n4567), .B(n4561), .Y(DP_OP_95J75_125_7728_n71) );
MX2X1TS U6444 ( .A(add_subt_module_DMP[42]), .B(
add_subt_module_Sgf_normalized_result[44]), .S0(n4564), .Y(
add_subt_module_S_A_S_Oper_A[44]) );
NOR2XLTS U6445 ( .A(n4588), .B(n5160), .Y(n4563) );
XOR2X1TS U6446 ( .A(n4567), .B(n4563), .Y(DP_OP_95J75_125_7728_n70) );
MX2X1TS U6447 ( .A(add_subt_module_DMP[43]), .B(
add_subt_module_Sgf_normalized_result[45]), .S0(n4564), .Y(
add_subt_module_S_A_S_Oper_A[45]) );
NOR2XLTS U6448 ( .A(n4564), .B(n5159), .Y(n4566) );
XOR2X1TS U6449 ( .A(n4567), .B(n4566), .Y(DP_OP_95J75_125_7728_n69) );
AO22XLTS U6450 ( .A0(n4570), .A1(d_ff2_X[48]), .B0(n4507), .B1(
d_ff3_sh_x_out[48]), .Y(n2764) );
AO22XLTS U6451 ( .A0(n4570), .A1(d_ff2_X[51]), .B0(n4365), .B1(
d_ff3_sh_x_out[51]), .Y(n2770) );
AO22XLTS U6452 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[11]), .B0(
n4571), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[11]), .Y(n2607)
);
MX2X1TS U6453 ( .A(add_subt_module_DMP[6]), .B(
add_subt_module_Sgf_normalized_result[8]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[8]) );
NOR2XLTS U6454 ( .A(n4593), .B(n5187), .Y(n4572) );
XOR2X1TS U6455 ( .A(n4595), .B(n4572), .Y(DP_OP_95J75_125_7728_n106) );
MX2X1TS U6456 ( .A(add_subt_module_DMP[7]), .B(
add_subt_module_Sgf_normalized_result[9]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[9]) );
NOR2XLTS U6457 ( .A(n4593), .B(n5186), .Y(n4573) );
XOR2X1TS U6458 ( .A(n4595), .B(n4573), .Y(DP_OP_95J75_125_7728_n105) );
MX2X1TS U6459 ( .A(add_subt_module_DMP[8]), .B(
add_subt_module_Sgf_normalized_result[10]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[10]) );
XOR2X1TS U6460 ( .A(n4595), .B(n4574), .Y(DP_OP_95J75_125_7728_n104) );
MX2X1TS U6461 ( .A(add_subt_module_DMP[9]), .B(
add_subt_module_Sgf_normalized_result[11]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[11]) );
NOR2XLTS U6462 ( .A(n4575), .B(n5184), .Y(n4576) );
XOR2X1TS U6463 ( .A(n4595), .B(n4576), .Y(DP_OP_95J75_125_7728_n103) );
NOR3X1TS U6464 ( .A(cont_iter_out[0]), .B(n2985), .C(n4577), .Y(n4937) );
NOR2XLTS U6465 ( .A(n4578), .B(n4937), .Y(n4580) );
AOI2BB2XLTS U6466 ( .B0(n4580), .B1(n4579), .A0N(n4932), .A1N(
d_ff3_LUT_out[25]), .Y(n2820) );
AO22XLTS U6467 ( .A0(n4582), .A1(add_subt_module_Add_Subt_result[7]), .B0(
n4510), .B1(add_subt_module_Add_Subt_Sgf_module_S_to_D[7]), .Y(n2603)
);
CLKAND2X2TS U6468 ( .A(add_subt_module_Sgf_normalized_result[0]), .B(n5202),
.Y(n4583) );
XOR2X1TS U6469 ( .A(n5273), .B(n4583), .Y(DP_OP_95J75_125_7728_n114) );
CLKAND2X2TS U6470 ( .A(n4588), .B(add_subt_module_Sgf_normalized_result[0]),
.Y(add_subt_module_S_A_S_Oper_A[0]) );
CLKAND2X2TS U6471 ( .A(add_subt_module_Sgf_normalized_result[1]), .B(n4565),
.Y(add_subt_module_S_A_S_Oper_A[1]) );
CLKAND2X2TS U6472 ( .A(add_subt_module_Sgf_normalized_result[1]), .B(n5202),
.Y(n4584) );
XOR2X1TS U6473 ( .A(n4591), .B(n4584), .Y(DP_OP_95J75_125_7728_n113) );
MX2X1TS U6474 ( .A(add_subt_module_DMP[0]), .B(
add_subt_module_Sgf_normalized_result[2]), .S0(n4306), .Y(
add_subt_module_S_A_S_Oper_A[2]) );
NAND2X1TS U6475 ( .A(n5202), .B(n5135), .Y(n4585) );
XOR2X1TS U6476 ( .A(n4591), .B(n4585), .Y(DP_OP_95J75_125_7728_n112) );
MX2X1TS U6477 ( .A(add_subt_module_DMP[1]), .B(
add_subt_module_Sgf_normalized_result[3]), .S0(n4535), .Y(
add_subt_module_S_A_S_Oper_A[3]) );
NOR2XLTS U6478 ( .A(n4593), .B(n5192), .Y(n4586) );
XOR2X1TS U6479 ( .A(n4591), .B(n4586), .Y(DP_OP_95J75_125_7728_n111) );
MX2X1TS U6480 ( .A(add_subt_module_DMP[2]), .B(
add_subt_module_Sgf_normalized_result[4]), .S0(n4565), .Y(
add_subt_module_S_A_S_Oper_A[4]) );
NOR2XLTS U6481 ( .A(n4593), .B(n5191), .Y(n4587) );
XOR2X1TS U6482 ( .A(n4591), .B(n4587), .Y(DP_OP_95J75_125_7728_n110) );
MX2X1TS U6483 ( .A(add_subt_module_DMP[3]), .B(
add_subt_module_Sgf_normalized_result[5]), .S0(n4564), .Y(
add_subt_module_S_A_S_Oper_A[5]) );
NOR2XLTS U6484 ( .A(n4593), .B(n5190), .Y(n4589) );
XOR2X1TS U6485 ( .A(n4591), .B(n4589), .Y(DP_OP_95J75_125_7728_n109) );
MX2X1TS U6486 ( .A(add_subt_module_DMP[4]), .B(
add_subt_module_Sgf_normalized_result[6]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[6]) );
NOR2XLTS U6487 ( .A(n4593), .B(n5189), .Y(n4590) );
XOR2X1TS U6488 ( .A(n4591), .B(n4590), .Y(DP_OP_95J75_125_7728_n108) );
MX2X1TS U6489 ( .A(add_subt_module_DMP[5]), .B(
add_subt_module_Sgf_normalized_result[7]), .S0(n4592), .Y(
add_subt_module_S_A_S_Oper_A[7]) );
NOR2XLTS U6490 ( .A(n4593), .B(n5188), .Y(n4594) );
XOR2X1TS U6491 ( .A(n4595), .B(n4594), .Y(DP_OP_95J75_125_7728_n107) );
OAI21XLTS U6492 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(
add_subt_module_Add_Subt_result[7]), .B0(n5064), .Y(n4597) );
OAI21XLTS U6493 ( .A0(add_subt_module_Add_Subt_result[10]), .A1(n4597), .B0(
n4596), .Y(n4603) );
AOI211XLTS U6494 ( .A0(n4598), .A1(add_subt_module_Add_Subt_result[0]), .B0(
add_subt_module_Add_Subt_result[4]), .C0(
add_subt_module_Add_Subt_result[3]), .Y(n4601) );
OAI211XLTS U6495 ( .A0(n4601), .A1(n4600), .B0(n3014), .C0(n4599), .Y(n4602)
);
AOI21X1TS U6496 ( .A0(n4604), .A1(n4603), .B0(n4602), .Y(n4626) );
OAI31X1TS U6497 ( .A0(add_subt_module_Add_Subt_result[17]), .A1(n5080), .A2(
n4605), .B0(n4626), .Y(n4618) );
NAND2X1TS U6498 ( .A(add_subt_module_Add_Subt_result[28]), .B(n4606), .Y(
n4651) );
NOR2XLTS U6499 ( .A(add_subt_module_Add_Subt_result[53]), .B(
add_subt_module_Add_Subt_result[54]), .Y(n4614) );
AOI211X1TS U6500 ( .A0(add_subt_module_Add_Subt_result[44]), .A1(n4607),
.B0(add_subt_module_Add_Subt_result[47]), .C0(
add_subt_module_Add_Subt_result[48]), .Y(n4609) );
NOR2XLTS U6501 ( .A(add_subt_module_Add_Subt_result[51]), .B(
add_subt_module_Add_Subt_result[52]), .Y(n4608) );
OAI31X1TS U6502 ( .A0(add_subt_module_Add_Subt_result[50]), .A1(
add_subt_module_Add_Subt_result[49]), .A2(n4609), .B0(n4608), .Y(n4613) );
OAI31X1TS U6503 ( .A0(add_subt_module_Add_Subt_result[42]), .A1(
add_subt_module_Add_Subt_result[41]), .A2(n4610), .B0(n5138), .Y(n4611) );
AOI22X1TS U6504 ( .A0(n4614), .A1(n4613), .B0(n4612), .B1(n4611), .Y(n4615)
);
OAI211XLTS U6505 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4651),
.B0(n4616), .C0(n4615), .Y(n4617) );
OA22X1TS U6506 ( .A0(n4618), .A1(n4617), .B0(add_subt_module_LZA_output[1]),
.B1(n3014), .Y(n2591) );
AOI21X1TS U6507 ( .A0(n4619), .A1(n5064), .B0(n4645), .Y(n4628) );
OAI21XLTS U6508 ( .A0(add_subt_module_Add_Subt_result[13]), .A1(
add_subt_module_Add_Subt_result[10]), .B0(n4620), .Y(n4624) );
NAND2X1TS U6509 ( .A(n5080), .B(n5008), .Y(n4622) );
OAI31X1TS U6510 ( .A0(add_subt_module_Add_Subt_result[18]), .A1(
add_subt_module_Add_Subt_result[14]), .A2(n4622), .B0(n4621), .Y(n4623) );
NAND4XLTS U6511 ( .A(n4626), .B(n4625), .C(n4624), .D(n4623), .Y(n4627) );
OA22X1TS U6512 ( .A0(n3014), .A1(add_subt_module_LZA_output[5]), .B0(n4628),
.B1(n4627), .Y(n2589) );
AOI32X1TS U6513 ( .A0(add_subt_module_Add_Subt_result[4]), .A1(n4629), .A2(
n5104), .B0(add_subt_module_Add_Subt_result[6]), .B1(n4629), .Y(n4634)
);
NAND2X1TS U6514 ( .A(add_subt_module_Add_Subt_result[20]), .B(n4631), .Y(
n4632) );
NAND4XLTS U6515 ( .A(n4635), .B(n4634), .C(n4633), .D(n4632), .Y(n4661) );
NOR3X1TS U6516 ( .A(add_subt_module_Add_Subt_result[44]), .B(
add_subt_module_Add_Subt_result[46]), .C(
add_subt_module_Add_Subt_result[45]), .Y(n4638) );
OAI211X1TS U6517 ( .A0(n4638), .A1(n4637), .B0(n4652), .C0(n4636), .Y(n4641)
);
OAI32X1TS U6518 ( .A0(n4641), .A1(add_subt_module_Add_Subt_result[30]), .A2(
n4640), .B0(n4639), .B1(n4641), .Y(n4642) );
OAI211XLTS U6519 ( .A0(n4645), .A1(n4644), .B0(n4643), .C0(n4642), .Y(n4646)
);
OA22X1TS U6520 ( .A0(n3014), .A1(add_subt_module_LZA_output[3]), .B0(n4661),
.B1(n4646), .Y(n2593) );
AOI21X1TS U6521 ( .A0(add_subt_module_Add_Subt_result[12]), .A1(n5106), .B0(
add_subt_module_Add_Subt_result[14]), .Y(n4659) );
INVX2TS U6522 ( .A(n4647), .Y(n4655) );
NOR3X1TS U6523 ( .A(add_subt_module_Add_Subt_result[48]), .B(
add_subt_module_Add_Subt_result[50]), .C(
add_subt_module_Add_Subt_result[49]), .Y(n4649) );
OAI22X1TS U6524 ( .A0(add_subt_module_Add_Subt_result[35]), .A1(n4650), .B0(
n4649), .B1(n4648), .Y(n4654) );
OAI21XLTS U6525 ( .A0(add_subt_module_Add_Subt_result[23]), .A1(n4652), .B0(
n4651), .Y(n4653) );
AOI211XLTS U6526 ( .A0(add_subt_module_Add_Subt_result[32]), .A1(n4655),
.B0(n4654), .C0(n4653), .Y(n4656) );
OAI211XLTS U6527 ( .A0(n4659), .A1(n4658), .B0(n4657), .C0(n4656), .Y(n4660)
);
OA22X1TS U6528 ( .A0(n3014), .A1(add_subt_module_LZA_output[2]), .B0(n4661),
.B1(n4660), .Y(n2594) );
AOI22X1TS U6529 ( .A0(n4663), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(
n4662), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(
n4665) );
OAI211XLTS U6530 ( .A0(n4666), .A1(n5149), .B0(n4665), .C0(n4664), .Y(n4667)
);
AOI21X1TS U6531 ( .A0(n4668), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n4667), .Y(n4670) );
AOI22X1TS U6532 ( .A0(n4671), .A1(n4670), .B0(n3700), .B1(n5072), .Y(n2562)
);
CLKBUFX3TS U6533 ( .A(n4820), .Y(n4720) );
AOI222X4TS U6534 ( .A0(n4767), .A1(add_subt_module_DmP[48]), .B0(
add_subt_module_Add_Subt_result[4]), .B1(n4702), .C0(
add_subt_module_Add_Subt_result[50]), .C1(n4711), .Y(n4689) );
OAI22X1TS U6535 ( .A0(n4681), .A1(n4746), .B0(n4689), .B1(n4756), .Y(n4678)
);
OAI22X1TS U6536 ( .A0(n4676), .A1(n4777), .B0(n4769), .B1(n4685), .Y(n4677)
);
NOR2X1TS U6537 ( .A(n4678), .B(n4677), .Y(n4696) );
AOI22X1TS U6538 ( .A0(n4720), .A1(n4696), .B0(n4680), .B1(n4679), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]) );
CLKBUFX3TS U6539 ( .A(n4698), .Y(n4755) );
AOI222X4TS U6540 ( .A0(n4767), .A1(add_subt_module_DmP[47]), .B0(
add_subt_module_Add_Subt_result[5]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[49]), .C1(n4711), .Y(n4693) );
OAI22X1TS U6541 ( .A0(n4681), .A1(n3627), .B0(n4693), .B1(n4761), .Y(n4683)
);
OAI22X1TS U6542 ( .A0(n4689), .A1(n4861), .B0(n4776), .B1(n4685), .Y(n4682)
);
NOR2X1TS U6543 ( .A(n4683), .B(n4682), .Y(n4701) );
AOI22X1TS U6544 ( .A0(n4720), .A1(n4701), .B0(n4684), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]) );
OAI22X1TS U6545 ( .A0(n4689), .A1(n4893), .B0(n4777), .B1(n4685), .Y(n4687)
);
AOI222X4TS U6546 ( .A0(n4767), .A1(add_subt_module_DmP[46]), .B0(
add_subt_module_Add_Subt_result[6]), .B1(n4698), .C0(
add_subt_module_Add_Subt_result[48]), .C1(n4711), .Y(n4697) );
OAI22X1TS U6547 ( .A0(n4697), .A1(n4761), .B0(n4693), .B1(n4861), .Y(n4686)
);
NOR2X1TS U6548 ( .A(n4687), .B(n4686), .Y(n4706) );
AOI22X1TS U6549 ( .A0(n4720), .A1(n4706), .B0(n4688), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]) );
OAI22X1TS U6550 ( .A0(n4697), .A1(n4888), .B0(n4693), .B1(n4893), .Y(n4691)
);
OAI222X4TS U6551 ( .A0(n4823), .A1(add_subt_module_Add_Subt_result[47]),
.B0(n4847), .B1(add_subt_module_Add_Subt_result[7]), .C0(
add_subt_module_DmP[45]), .C1(n4865), .Y(n4703) );
OAI22X1TS U6552 ( .A0(n4689), .A1(n3627), .B0(n4883), .B1(n4703), .Y(n4690)
);
NOR2X1TS U6553 ( .A(n4691), .B(n4690), .Y(n4710) );
AOI22X1TS U6554 ( .A0(n4720), .A1(n4710), .B0(n4692), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]) );
OAI22X1TS U6555 ( .A0(n4697), .A1(n4746), .B0(n4769), .B1(n4703), .Y(n4695)
);
CLKBUFX3TS U6556 ( .A(n3291), .Y(n4841) );
AOI222X4TS U6557 ( .A0(n5053), .A1(add_subt_module_DmP[44]), .B0(
add_subt_module_Add_Subt_result[8]), .B1(n4702), .C0(
add_subt_module_Add_Subt_result[46]), .C1(n4841), .Y(n4707) );
OAI22X1TS U6558 ( .A0(n4693), .A1(n3627), .B0(n4707), .B1(n4756), .Y(n4694)
);
NOR2X1TS U6559 ( .A(n4695), .B(n4694), .Y(n4715) );
AOI22X1TS U6560 ( .A0(n4720), .A1(n4715), .B0(n4696), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]) );
OAI22X1TS U6561 ( .A0(n4697), .A1(n3627), .B0(n4776), .B1(n4703), .Y(n4700)
);
AOI222X4TS U6562 ( .A0(n4767), .A1(add_subt_module_DmP[43]), .B0(
add_subt_module_Add_Subt_result[9]), .B1(n4698), .C0(
add_subt_module_Add_Subt_result[45]), .C1(n4711), .Y(n4712) );
OAI22X1TS U6563 ( .A0(n4707), .A1(n4861), .B0(n4712), .B1(n4761), .Y(n4699)
);
NOR2X1TS U6564 ( .A(n4700), .B(n4699), .Y(n4719) );
AOI22X1TS U6565 ( .A0(n4720), .A1(n4719), .B0(n4701), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]) );
OAI22X1TS U6566 ( .A0(n4707), .A1(n4746), .B0(n4712), .B1(n4888), .Y(n4705)
);
AOI222X4TS U6567 ( .A0(n4767), .A1(add_subt_module_DmP[42]), .B0(
add_subt_module_Add_Subt_result[10]), .B1(n4702), .C0(
add_subt_module_Add_Subt_result[44]), .C1(n4711), .Y(n4716) );
OAI22X1TS U6568 ( .A0(n4716), .A1(n4761), .B0(n4777), .B1(n4703), .Y(n4704)
);
NOR2X1TS U6569 ( .A(n4705), .B(n4704), .Y(n4725) );
AOI22X1TS U6570 ( .A0(n4720), .A1(n4725), .B0(n4706), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]) );
OAI22X1TS U6571 ( .A0(n4707), .A1(n4826), .B0(n4716), .B1(n4861), .Y(n4709)
);
OAI222X4TS U6572 ( .A0(n4879), .A1(add_subt_module_Add_Subt_result[43]),
.B0(n4847), .B1(add_subt_module_Add_Subt_result[11]), .C0(
add_subt_module_DmP[41]), .C1(n4865), .Y(n4721) );
OAI22X1TS U6573 ( .A0(n4712), .A1(n4746), .B0(n4883), .B1(n4721), .Y(n4708)
);
NOR2X1TS U6574 ( .A(n4709), .B(n4708), .Y(n4729) );
AOI22X1TS U6575 ( .A0(n4720), .A1(n4729), .B0(n4710), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
AOI222X4TS U6576 ( .A0(n4767), .A1(add_subt_module_DmP[40]), .B0(
add_subt_module_Add_Subt_result[12]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[42]), .C1(n4711), .Y(n4726) );
OAI22X1TS U6577 ( .A0(n4712), .A1(n3627), .B0(n4726), .B1(n4756), .Y(n4714)
);
OAI22X1TS U6578 ( .A0(n4716), .A1(n4746), .B0(n4769), .B1(n4721), .Y(n4713)
);
NOR2X1TS U6579 ( .A(n4714), .B(n4713), .Y(n4733) );
AOI22X1TS U6580 ( .A0(n4720), .A1(n4733), .B0(n4715), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
AOI222X4TS U6581 ( .A0(n5053), .A1(add_subt_module_DmP[39]), .B0(
add_subt_module_Add_Subt_result[13]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[41]), .C1(n4841), .Y(n4730) );
OAI22X1TS U6582 ( .A0(n4726), .A1(n4888), .B0(n4730), .B1(n4756), .Y(n4718)
);
OAI22X1TS U6583 ( .A0(n4716), .A1(n4826), .B0(n4776), .B1(n4721), .Y(n4717)
);
NOR2X1TS U6584 ( .A(n4718), .B(n4717), .Y(n4737) );
AOI22X1TS U6585 ( .A0(n4720), .A1(n4737), .B0(n4719), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI222X4TS U6586 ( .A0(n5053), .A1(add_subt_module_DmP[38]), .B0(
add_subt_module_Add_Subt_result[14]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[40]), .C1(n4841), .Y(n4734) );
OAI22X1TS U6587 ( .A0(n4730), .A1(n4769), .B0(n4734), .B1(n4761), .Y(n4723)
);
OAI22X1TS U6588 ( .A0(n4726), .A1(n4746), .B0(n4777), .B1(n4721), .Y(n4722)
);
NOR2X1TS U6589 ( .A(n4723), .B(n4722), .Y(n4741) );
AOI22X1TS U6590 ( .A0(n4820), .A1(n4741), .B0(n4725), .B1(n4724), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
OAI222X4TS U6591 ( .A0(n4864), .A1(add_subt_module_Add_Subt_result[39]),
.B0(n4847), .B1(add_subt_module_Add_Subt_result[15]), .C0(
add_subt_module_DmP[37]), .C1(n4865), .Y(n4738) );
OAI22X1TS U6592 ( .A0(n4726), .A1(n4903), .B0(n4883), .B1(n4738), .Y(n4728)
);
OAI22X1TS U6593 ( .A0(n4730), .A1(n4746), .B0(n4734), .B1(n4888), .Y(n4727)
);
NOR2X1TS U6594 ( .A(n4728), .B(n4727), .Y(n4745) );
AOI22X1TS U6595 ( .A0(n4766), .A1(n4745), .B0(n4729), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
OAI22X1TS U6596 ( .A0(n4730), .A1(n4777), .B0(n4734), .B1(n4893), .Y(n4732)
);
AOI222X4TS U6597 ( .A0(n5053), .A1(add_subt_module_DmP[36]), .B0(
add_subt_module_Add_Subt_result[16]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[38]), .C1(n4841), .Y(n4742) );
OAI22X1TS U6598 ( .A0(n4742), .A1(n4883), .B0(n4769), .B1(n4738), .Y(n4731)
);
NOR2X1TS U6599 ( .A(n4732), .B(n4731), .Y(n4750) );
AOI22X1TS U6600 ( .A0(n4834), .A1(n4750), .B0(n4733), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
AOI222X4TS U6601 ( .A0(n5053), .A1(add_subt_module_DmP[35]), .B0(
add_subt_module_Add_Subt_result[17]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[37]), .C1(n4841), .Y(n4747) );
OAI22X1TS U6602 ( .A0(n4747), .A1(n4883), .B0(n4776), .B1(n4738), .Y(n4736)
);
OAI22X1TS U6603 ( .A0(n4734), .A1(n4826), .B0(n4742), .B1(n4861), .Y(n4735)
);
NOR2X1TS U6604 ( .A(n4736), .B(n4735), .Y(n4754) );
AOI22X1TS U6605 ( .A0(n4820), .A1(n4754), .B0(n4737), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
OAI22X1TS U6606 ( .A0(n4742), .A1(n4746), .B0(n4747), .B1(n4888), .Y(n4740)
);
AOI222X4TS U6607 ( .A0(n4842), .A1(add_subt_module_DmP[34]), .B0(
add_subt_module_Add_Subt_result[18]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[36]), .C1(n4841), .Y(n4751) );
OAI22X1TS U6608 ( .A0(n4751), .A1(n4756), .B0(n4777), .B1(n4738), .Y(n4739)
);
NOR2X1TS U6609 ( .A(n4740), .B(n4739), .Y(n4760) );
AOI22X1TS U6610 ( .A0(n4766), .A1(n4760), .B0(n4741), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
OAI222X4TS U6611 ( .A0(n4823), .A1(add_subt_module_Add_Subt_result[35]),
.B0(n4847), .B1(add_subt_module_Add_Subt_result[19]), .C0(
add_subt_module_DmP[33]), .C1(n4865), .Y(n4757) );
OAI22X1TS U6612 ( .A0(n4747), .A1(n4746), .B0(n4883), .B1(n4757), .Y(n4744)
);
OAI22X1TS U6613 ( .A0(n4742), .A1(n4826), .B0(n4751), .B1(n4861), .Y(n4743)
);
NOR2X1TS U6614 ( .A(n4744), .B(n4743), .Y(n4765) );
AOI22X1TS U6615 ( .A0(n4834), .A1(n4765), .B0(n4745), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]) );
OAI22X1TS U6616 ( .A0(n4751), .A1(n4746), .B0(n4769), .B1(n4757), .Y(n4749)
);
AOI222X4TS U6617 ( .A0(n5053), .A1(add_subt_module_DmP[32]), .B0(
add_subt_module_Add_Subt_result[20]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[34]), .C1(n4841), .Y(n4762) );
OAI22X1TS U6618 ( .A0(n4762), .A1(n4883), .B0(n4747), .B1(n4903), .Y(n4748)
);
NOR2X1TS U6619 ( .A(n4749), .B(n4748), .Y(n4774) );
AOI22X1TS U6620 ( .A0(n4820), .A1(n4774), .B0(n4750), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]) );
OAI22X1TS U6621 ( .A0(n4762), .A1(n4769), .B0(n4776), .B1(n4757), .Y(n4753)
);
AOI222X4TS U6622 ( .A0(n5053), .A1(add_subt_module_DmP[31]), .B0(
add_subt_module_Add_Subt_result[21]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[33]), .C1(n4841), .Y(n4770) );
OAI22X1TS U6623 ( .A0(n4770), .A1(n4761), .B0(n4751), .B1(n4826), .Y(n4752)
);
NOR2X1TS U6624 ( .A(n4753), .B(n4752), .Y(n4781) );
AOI22X1TS U6625 ( .A0(n4766), .A1(n4781), .B0(n4754), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
AOI222X4TS U6626 ( .A0(n5053), .A1(add_subt_module_DmP[30]), .B0(
add_subt_module_Add_Subt_result[22]), .B1(n4755), .C0(
add_subt_module_Add_Subt_result[32]), .C1(n4841), .Y(n4778) );
OAI22X1TS U6627 ( .A0(n4762), .A1(n4776), .B0(n4778), .B1(n4761), .Y(n4759)
);
OAI22X1TS U6628 ( .A0(n4770), .A1(n4769), .B0(n4777), .B1(n4757), .Y(n4758)
);
NOR2X1TS U6629 ( .A(n4759), .B(n4758), .Y(n4785) );
AOI22X1TS U6630 ( .A0(n4834), .A1(n4785), .B0(n4760), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
OAI222X4TS U6631 ( .A0(n4879), .A1(add_subt_module_Add_Subt_result[31]),
.B0(n4847), .B1(add_subt_module_Add_Subt_result[23]), .C0(
add_subt_module_DmP[29]), .C1(n4865), .Y(n4783) );
OAI22X1TS U6632 ( .A0(n4778), .A1(n4888), .B0(n4883), .B1(n4783), .Y(n4764)
);
OAI22X1TS U6633 ( .A0(n4770), .A1(n4776), .B0(n4762), .B1(n4903), .Y(n4763)
);
NOR2X1TS U6634 ( .A(n4764), .B(n4763), .Y(n4788) );
AOI22X1TS U6635 ( .A0(n4766), .A1(n4788), .B0(n4765), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
CLKBUFX3TS U6636 ( .A(n4766), .Y(n4819) );
AOI22X1TS U6637 ( .A0(add_subt_module_Add_Subt_result[30]), .A1(n4849), .B0(
add_subt_module_DmP[28]), .B1(n4767), .Y(n4768) );
NOR2XLTS U6638 ( .A(n4778), .B(n4893), .Y(n4772) );
OAI22X1TS U6639 ( .A0(n4770), .A1(n4777), .B0(n4769), .B1(n4783), .Y(n4771)
);
AOI211X1TS U6640 ( .A0(n3289), .A1(n4787), .B0(n4772), .C0(n4771), .Y(n4794)
);
AOI22X1TS U6641 ( .A0(n4819), .A1(n4794), .B0(n4774), .B1(n4773), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U6642 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4849), .B0(
add_subt_module_DmP[27]), .B1(n4821), .Y(n4775) );
NOR2BX1TS U6643 ( .AN(n4787), .B(n4888), .Y(n4780) );
OAI22X1TS U6644 ( .A0(n4778), .A1(n4777), .B0(n4776), .B1(n4783), .Y(n4779)
);
AOI22X1TS U6645 ( .A0(n4819), .A1(n4798), .B0(n4781), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
OAI222X1TS U6646 ( .A0(n4823), .A1(add_subt_module_Add_Subt_result[28]),
.B0(n4847), .B1(add_subt_module_Add_Subt_result[26]), .C0(
add_subt_module_DmP[26]), .C1(n4865), .Y(n4786) );
INVX2TS U6647 ( .A(n4786), .Y(n4793) );
AOI22X1TS U6648 ( .A0(n4850), .A1(n4793), .B0(n3397), .B1(n4792), .Y(n4782)
);
OAI21XLTS U6649 ( .A0(n4826), .A1(n4783), .B0(n4782), .Y(n4784) );
AOI21X1TS U6650 ( .A0(n4898), .A1(n4787), .B0(n4784), .Y(n4801) );
AOI22X1TS U6651 ( .A0(n4819), .A1(n4801), .B0(n4785), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
AOI22X1TS U6652 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_Add_Subt_result[27]), .B0(add_subt_module_DmP[25]),
.B1(n4821), .Y(n4790) );
AOI22X1TS U6653 ( .A0(n4791), .A1(n4790), .B0(n4786), .B1(n4789), .Y(n4797)
);
AOI22X1TS U6654 ( .A0(n4819), .A1(n4805), .B0(n4788), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
OAI222X1TS U6655 ( .A0(n4880), .A1(add_subt_module_Add_Subt_result[28]),
.B0(n4823), .B1(add_subt_module_Add_Subt_result[26]), .C0(
add_subt_module_DmP[24]), .C1(n4878), .Y(n4795) );
AOI22X1TS U6656 ( .A0(n4791), .A1(n4795), .B0(n4790), .B1(n4789), .Y(n4800)
);
AOI22X1TS U6657 ( .A0(n4819), .A1(n4812), .B0(n4794), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
INVX2TS U6658 ( .A(n4795), .Y(n4802) );
AOI22X1TS U6659 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4873), .B0(
add_subt_module_DmP[23]), .B1(n4821), .Y(n4796) );
AOI22X1TS U6660 ( .A0(n4819), .A1(n4818), .B0(n4798), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI22X1TS U6661 ( .A0(add_subt_module_Add_Subt_result[30]), .A1(n4873), .B0(
add_subt_module_DmP[22]), .B1(n4821), .Y(n4799) );
AOI22X1TS U6662 ( .A0(n4819), .A1(n4829), .B0(n4801), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI222X4TS U6663 ( .A0(n4880), .A1(add_subt_module_Add_Subt_result[31]),
.B0(n4879), .B1(add_subt_module_Add_Subt_result[23]), .C0(
add_subt_module_DmP[21]), .C1(n4878), .Y(n4825) );
AOI22X1TS U6664 ( .A0(n3397), .A1(n4817), .B0(n2994), .B1(n4802), .Y(n4803)
);
OAI21XLTS U6665 ( .A0(n4756), .A1(n4825), .B0(n4803), .Y(n4804) );
AOI21X1TS U6666 ( .A0(n4898), .A1(n4807), .B0(n4804), .Y(n4835) );
AOI22X1TS U6667 ( .A0(n4819), .A1(n4835), .B0(n4805), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
OAI22X1TS U6668 ( .A0(add_subt_module_DmP[20]), .A1(n4878), .B0(
add_subt_module_Add_Subt_result[22]), .B1(n4879), .Y(n4806) );
AOI22X1TS U6669 ( .A0(n4808), .A1(n4817), .B0(n2995), .B1(n4807), .Y(n4809)
);
OAI21XLTS U6670 ( .A0(n4861), .A1(n4825), .B0(n4809), .Y(n4810) );
AOI21X1TS U6671 ( .A0(n4811), .A1(n4830), .B0(n4810), .Y(n4840) );
AOI22X1TS U6672 ( .A0(n4819), .A1(n4840), .B0(n4812), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U6673 ( .A0(add_subt_module_Add_Subt_result[21]), .A1(n4849), .B0(
add_subt_module_DmP[19]), .B1(n4821), .Y(n4813) );
AOI22X1TS U6674 ( .A0(n3289), .A1(n4837), .B0(n3397), .B1(n4830), .Y(n4815)
);
OAI21XLTS U6675 ( .A0(n4893), .A1(n4825), .B0(n4815), .Y(n4816) );
AOI21X1TS U6676 ( .A0(n2995), .A1(n4817), .B0(n4816), .Y(n4846) );
AOI22X1TS U6677 ( .A0(n4819), .A1(n4846), .B0(n4818), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X1TS U6678 ( .A0(add_subt_module_Add_Subt_result[34]), .A1(n4873), .B0(
add_subt_module_DmP[18]), .B1(n4821), .Y(n4822) );
AOI22X1TS U6679 ( .A0(n3289), .A1(n4843), .B0(n4898), .B1(n4830), .Y(n4824)
);
OAI21XLTS U6680 ( .A0(n4826), .A1(n4825), .B0(n4824), .Y(n4827) );
AOI21X1TS U6681 ( .A0(n4905), .A1(n4837), .B0(n4827), .Y(n4854) );
AOI22X1TS U6682 ( .A0(n4766), .A1(n4854), .B0(n4829), .B1(n4828), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI222X4TS U6683 ( .A0(n4880), .A1(add_subt_module_Add_Subt_result[35]),
.B0(n4864), .B1(add_subt_module_Add_Subt_result[19]), .C0(
add_subt_module_DmP[17]), .C1(n4878), .Y(n4852) );
AOI22X1TS U6684 ( .A0(n4831), .A1(n4843), .B0(n2994), .B1(n4830), .Y(n4832)
);
OAI21XLTS U6685 ( .A0(n4761), .A1(n4852), .B0(n4832), .Y(n4833) );
AOI21X1TS U6686 ( .A0(n4898), .A1(n4837), .B0(n4833), .Y(n4857) );
AOI22X1TS U6687 ( .A0(n4820), .A1(n4857), .B0(n4835), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI22X1TS U6688 ( .A0(add_subt_module_DmP[16]), .A1(n4878), .B0(
add_subt_module_Add_Subt_result[36]), .B1(n4847), .Y(n4836) );
AOI22X1TS U6689 ( .A0(n2968), .A1(n4843), .B0(n2995), .B1(n4837), .Y(n4838)
);
OAI21XLTS U6690 ( .A0(n4888), .A1(n4852), .B0(n4838), .Y(n4839) );
AOI21X1TS U6691 ( .A0(n4900), .A1(n2963), .B0(n4839), .Y(n4863) );
AOI22X1TS U6692 ( .A0(n4834), .A1(n4863), .B0(n4840), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI222X4TS U6693 ( .A0(n5204), .A1(n4842), .B0(n5055), .B1(n4873), .C0(n5008), .C1(n4841), .Y(n4859) );
AOI22X1TS U6694 ( .A0(n4850), .A1(n4859), .B0(n2994), .B1(n4843), .Y(n4844)
);
OAI21XLTS U6695 ( .A0(n4893), .A1(n4852), .B0(n4844), .Y(n4845) );
AOI21X1TS U6696 ( .A0(n4905), .A1(n2963), .B0(n4845), .Y(n4870) );
AOI22X1TS U6697 ( .A0(n4766), .A1(n4870), .B0(n4846), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
OAI22X1TS U6698 ( .A0(add_subt_module_DmP[14]), .A1(n4878), .B0(
add_subt_module_Add_Subt_result[38]), .B1(n4847), .Y(n4848) );
AOI22X1TS U6699 ( .A0(n4850), .A1(n4869), .B0(n4898), .B1(n2963), .Y(n4851)
);
OAI21XLTS U6700 ( .A0(n4903), .A1(n4852), .B0(n4851), .Y(n4853) );
AOI21X1TS U6701 ( .A0(n4905), .A1(n4859), .B0(n4853), .Y(n4877) );
AOI22X1TS U6702 ( .A0(n4820), .A1(n4877), .B0(n4854), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI222X4TS U6703 ( .A0(n4880), .A1(add_subt_module_Add_Subt_result[39]),
.B0(n4823), .B1(add_subt_module_Add_Subt_result[15]), .C0(
add_subt_module_DmP[13]), .C1(n4878), .Y(n4875) );
AOI22X1TS U6704 ( .A0(n2968), .A1(n4859), .B0(n2994), .B1(n2963), .Y(n4855)
);
OAI21XLTS U6705 ( .A0(n4756), .A1(n4875), .B0(n4855), .Y(n4856) );
AOI21X1TS U6706 ( .A0(n4905), .A1(n4869), .B0(n4856), .Y(n4885) );
AOI22X1TS U6707 ( .A0(n4834), .A1(n4885), .B0(n4857), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI222X1TS U6708 ( .A0(add_subt_module_DmP[12]), .A1(n4865), .B0(
add_subt_module_Add_Subt_result[40]), .B1(n4880), .C0(
add_subt_module_Add_Subt_result[14]), .C1(n4879), .Y(n4858) );
INVX2TS U6709 ( .A(n4858), .Y(n4881) );
AOI22X1TS U6710 ( .A0(n2968), .A1(n4869), .B0(n2995), .B1(n4859), .Y(n4860)
);
AOI21X1TS U6711 ( .A0(n4900), .A1(n4881), .B0(n4862), .Y(n4891) );
AOI22X1TS U6712 ( .A0(n4766), .A1(n4891), .B0(n4863), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
OAI222X1TS U6713 ( .A0(add_subt_module_DmP[11]), .A1(n4865), .B0(
add_subt_module_Add_Subt_result[41]), .B1(n4880), .C0(
add_subt_module_Add_Subt_result[13]), .C1(n4864), .Y(n4866) );
INVX2TS U6714 ( .A(n4866), .Y(n4886) );
AOI22X1TS U6715 ( .A0(n3289), .A1(n4886), .B0(n4905), .B1(n4881), .Y(n4867)
);
OAI21XLTS U6716 ( .A0(n4893), .A1(n4875), .B0(n4867), .Y(n4868) );
AOI21X1TS U6717 ( .A0(n2994), .A1(n4869), .B0(n4868), .Y(n4896) );
AOI22X1TS U6718 ( .A0(n4820), .A1(n4896), .B0(n4870), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
OAI22X1TS U6719 ( .A0(add_subt_module_DmP[10]), .A1(n4871), .B0(
add_subt_module_Add_Subt_result[12]), .B1(n4864), .Y(n4872) );
AOI22X1TS U6720 ( .A0(n3289), .A1(n4895), .B0(n4898), .B1(n4881), .Y(n4874)
);
OAI21XLTS U6721 ( .A0(n4903), .A1(n4875), .B0(n4874), .Y(n4876) );
AOI21X1TS U6722 ( .A0(n4905), .A1(n4886), .B0(n4876), .Y(n4906) );
AOI22X1TS U6723 ( .A0(n4834), .A1(n4906), .B0(n4877), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
OAI222X4TS U6724 ( .A0(n4880), .A1(add_subt_module_Add_Subt_result[43]),
.B0(n4879), .B1(add_subt_module_Add_Subt_result[11]), .C0(
add_subt_module_DmP[9]), .C1(n4878), .Y(n4902) );
AOI22X1TS U6725 ( .A0(n3397), .A1(n4895), .B0(n2994), .B1(n4881), .Y(n4882)
);
OAI21XLTS U6726 ( .A0(n4761), .A1(n4902), .B0(n4882), .Y(n4884) );
AOI21X1TS U6727 ( .A0(n4898), .A1(n4886), .B0(n4884), .Y(n4907) );
AOI22X1TS U6728 ( .A0(n3292), .A1(n4907), .B0(n4885), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U6729 ( .A0(n4900), .A1(n4897), .B0(n2995), .B1(n4886), .Y(n4887)
);
OAI21XLTS U6730 ( .A0(n4861), .A1(n4902), .B0(n4887), .Y(n4889) );
AOI21X1TS U6731 ( .A0(n4898), .A1(n4895), .B0(n4889), .Y(n4909) );
AOI22X1TS U6732 ( .A0(n4917), .A1(n4909), .B0(n4891), .B1(n4890), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U6733 ( .A0(n4900), .A1(n2961), .B0(n4905), .B1(n4897), .Y(n4892)
);
OAI21XLTS U6734 ( .A0(n4893), .A1(n4902), .B0(n4892), .Y(n4894) );
AOI21X1TS U6735 ( .A0(n2995), .A1(n4895), .B0(n4894), .Y(n4911) );
AOI22X1TS U6736 ( .A0(n4917), .A1(n4911), .B0(n4896), .B1(n4914), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U6737 ( .A0(n4900), .A1(n4899), .B0(n4898), .B1(n4897), .Y(n4901)
);
OAI21XLTS U6738 ( .A0(n4903), .A1(n4902), .B0(n4901), .Y(n4904) );
AOI21X1TS U6739 ( .A0(n4905), .A1(n2961), .B0(n4904), .Y(n4915) );
AOI22X1TS U6740 ( .A0(n4913), .A1(n4915), .B0(n4906), .B1(n4914), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U6741 ( .A0(n4917), .A1(n4908), .B0(n4907), .B1(n4914), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U6742 ( .A0(n4917), .A1(n4910), .B0(n4909), .B1(n4914), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U6743 ( .A0(n4913), .A1(n4912), .B0(n4911), .B1(n4914), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI22X1TS U6744 ( .A0(n4917), .A1(n4916), .B0(n4915), .B1(n4914), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
OAI21XLTS U6745 ( .A0(add_subt_module_FS_Module_state_reg[1]), .A1(n5010),
.B0(n4921), .Y(n2927) );
INVX2TS U6746 ( .A(n4923), .Y(n4922) );
AOI221XLTS U6747 ( .A0(cont_var_out[1]), .A1(n4923), .B0(n5068), .B1(n4922),
.C0(n4940), .Y(n2925) );
OAI22X1TS U6748 ( .A0(n4925), .A1(n5023), .B0(n4947), .B1(n4924), .Y(n2924)
);
AOI21X1TS U6749 ( .A0(n5056), .A1(n4927), .B0(n4926), .Y(n2922) );
NAND2X1TS U6750 ( .A(cont_iter_out[1]), .B(n2988), .Y(n4930) );
OAI211XLTS U6751 ( .A0(n3026), .A1(n4930), .B0(n4928), .C0(n4947), .Y(n4929)
);
OA22X1TS U6752 ( .A0(n4959), .A1(d_ff3_LUT_out[54]), .B0(n4929), .B1(n4944),
.Y(n2848) );
OA22X1TS U6753 ( .A0(n4932), .A1(d_ff3_LUT_out[45]), .B0(n4931), .B1(n4930),
.Y(n2840) );
NOR2X1TS U6754 ( .A(n4934), .B(n4933), .Y(n4935) );
OAI2BB1X1TS U6755 ( .A0N(d_ff3_LUT_out[43]), .A1N(n4020), .B0(n4935), .Y(
n2838) );
OAI2BB1X1TS U6756 ( .A0N(d_ff3_LUT_out[39]), .A1N(n4020), .B0(n4938), .Y(
n2834) );
OAI2BB1X1TS U6757 ( .A0N(d_ff3_LUT_out[34]), .A1N(n4568), .B0(n4935), .Y(
n2829) );
OAI2BB1X1TS U6758 ( .A0N(d_ff3_LUT_out[30]), .A1N(n4160), .B0(n4957), .Y(
n2825) );
OA22X1TS U6759 ( .A0(n4937), .A1(n4936), .B0(n4959), .B1(d_ff3_LUT_out[27]),
.Y(n2822) );
OA22X1TS U6760 ( .A0(cont_iter_out[3]), .A1(n4944), .B0(n4959), .B1(
d_ff3_LUT_out[22]), .Y(n2817) );
NOR2XLTS U6761 ( .A(cont_iter_out[3]), .B(n5057), .Y(n4939) );
OA22X1TS U6762 ( .A0(n4939), .A1(n4938), .B0(n4959), .B1(d_ff3_LUT_out[21]),
.Y(n2816) );
OAI22X1TS U6763 ( .A0(n4942), .A1(n4941), .B0(cont_iter_out[3]), .B1(n4944),
.Y(n2814) );
OAI2BB1X1TS U6764 ( .A0N(d_ff3_LUT_out[16]), .A1N(n4354), .B0(n4943), .Y(
n2811) );
OA22X1TS U6765 ( .A0(n4959), .A1(d_ff3_LUT_out[13]), .B0(n4945), .B1(n4944),
.Y(n2808) );
NAND4XLTS U6766 ( .A(cont_iter_out[1]), .B(cont_iter_out[3]), .C(n2988), .D(
n5057), .Y(n4948) );
NAND4XLTS U6767 ( .A(n4949), .B(n4948), .C(n4947), .D(n4946), .Y(n4950) );
OA22X1TS U6768 ( .A0(n4951), .A1(n4950), .B0(n4959), .B1(d_ff3_LUT_out[11]),
.Y(n2806) );
NOR3BXLTS U6769 ( .AN(n4954), .B(n4953), .C(n4952), .Y(n4956) );
OA22X1TS U6770 ( .A0(n4959), .A1(d_ff3_LUT_out[10]), .B0(n4956), .B1(n4955),
.Y(n2805) );
OAI2BB1X1TS U6771 ( .A0N(d_ff3_LUT_out[4]), .A1N(n4507), .B0(n4957), .Y(
n2799) );
OA22X1TS U6772 ( .A0(n4961), .A1(n4960), .B0(n4959), .B1(d_ff3_LUT_out[3]),
.Y(n2798) );
OA22X1TS U6773 ( .A0(d_ff2_X[35]), .A1(n4963), .B0(d_ff_Xn[35]), .B1(n4962),
.Y(n2739) );
OA22X1TS U6774 ( .A0(d_ff2_X[34]), .A1(n4963), .B0(d_ff_Xn[34]), .B1(n4962),
.Y(n2737) );
OA22X1TS U6775 ( .A0(d_ff2_X[31]), .A1(n4963), .B0(d_ff_Xn[31]), .B1(n4962),
.Y(n2731) );
OA22X1TS U6776 ( .A0(d_ff2_X[26]), .A1(n4963), .B0(d_ff_Xn[26]), .B1(n4263),
.Y(n2721) );
OA22X1TS U6777 ( .A0(d_ff2_X[14]), .A1(n4983), .B0(d_ff_Xn[14]), .B1(n4263),
.Y(n2697) );
OA22X1TS U6778 ( .A0(d_ff2_X[13]), .A1(n4983), .B0(d_ff_Xn[13]), .B1(n4985),
.Y(n2695) );
OA22X1TS U6779 ( .A0(d_ff2_X[11]), .A1(n4983), .B0(d_ff_Xn[11]), .B1(n4263),
.Y(n2691) );
OA22X1TS U6780 ( .A0(d_ff2_X[8]), .A1(n4963), .B0(d_ff_Xn[8]), .B1(n4985),
.Y(n2685) );
OAI22X1TS U6781 ( .A0(n4974), .A1(n5049), .B0(n4009), .B1(n5111), .Y(n2666)
);
AOI22X1TS U6782 ( .A0(n4965), .A1(add_subt_module_add_overflow_flag), .B0(
n5075), .B1(n4964), .Y(n2664) );
OAI31X1TS U6783 ( .A0(add_subt_module_FS_Module_state_reg[0]), .A1(
add_subt_module_FS_Module_state_reg[3]), .A2(n4966), .B0(n5053), .Y(
n2650) );
OA22X1TS U6784 ( .A0(add_subt_module_exp_oper_result[10]), .A1(n4968), .B0(
n3018), .B1(result_add_subt[62]), .Y(n2534) );
OA22X1TS U6785 ( .A0(add_subt_module_exp_oper_result[9]), .A1(n4967), .B0(
n3018), .B1(result_add_subt[61]), .Y(n2530) );
OA22X1TS U6786 ( .A0(add_subt_module_exp_oper_result[8]), .A1(n4967), .B0(
n3018), .B1(result_add_subt[60]), .Y(n2526) );
OA22X1TS U6787 ( .A0(add_subt_module_exp_oper_result[7]), .A1(n4968), .B0(
n3018), .B1(result_add_subt[59]), .Y(n2522) );
OA22X1TS U6788 ( .A0(add_subt_module_exp_oper_result[6]), .A1(n4968), .B0(
n3018), .B1(result_add_subt[58]), .Y(n2518) );
OA22X1TS U6789 ( .A0(n4973), .A1(result_add_subt[57]), .B0(
add_subt_module_exp_oper_result[5]), .B1(n4967), .Y(n2514) );
OA22X1TS U6790 ( .A0(n4973), .A1(result_add_subt[56]), .B0(
add_subt_module_exp_oper_result[4]), .B1(n4968), .Y(n2510) );
OA22X1TS U6791 ( .A0(n4973), .A1(result_add_subt[55]), .B0(
add_subt_module_exp_oper_result[3]), .B1(n4967), .Y(n2506) );
OA22X1TS U6792 ( .A0(n4973), .A1(result_add_subt[54]), .B0(
add_subt_module_exp_oper_result[2]), .B1(n4967), .Y(n2502) );
OA22X1TS U6793 ( .A0(n3018), .A1(result_add_subt[53]), .B0(
add_subt_module_exp_oper_result[1]), .B1(n4967), .Y(n2498) );
OA22X1TS U6794 ( .A0(n3018), .A1(result_add_subt[52]), .B0(
add_subt_module_exp_oper_result[0]), .B1(n4968), .Y(n2494) );
OAI2BB2XLTS U6795 ( .B0(n5151), .B1(n4967), .A0N(result_add_subt[51]), .A1N(
n4969), .Y(n2490) );
OAI2BB2XLTS U6796 ( .B0(n5152), .B1(n4967), .A0N(result_add_subt[50]), .A1N(
n4969), .Y(n2486) );
CLKBUFX3TS U6797 ( .A(n4968), .Y(n4970) );
OAI2BB2XLTS U6798 ( .B0(n5153), .B1(n4970), .A0N(result_add_subt[49]), .A1N(
n4969), .Y(n2482) );
OAI2BB2XLTS U6799 ( .B0(n5154), .B1(n4970), .A0N(result_add_subt[48]), .A1N(
n4969), .Y(n2478) );
OAI2BB2XLTS U6800 ( .B0(n5155), .B1(n4970), .A0N(result_add_subt[47]), .A1N(
n4969), .Y(n2474) );
OAI2BB2XLTS U6801 ( .B0(n5156), .B1(n4970), .A0N(result_add_subt[46]), .A1N(
n4969), .Y(n2470) );
OAI2BB2XLTS U6802 ( .B0(n5157), .B1(n4970), .A0N(result_add_subt[45]), .A1N(
n4969), .Y(n2466) );
OAI2BB2XLTS U6803 ( .B0(n5158), .B1(n4970), .A0N(result_add_subt[44]), .A1N(
n4969), .Y(n2462) );
CLKBUFX3TS U6804 ( .A(n4975), .Y(n4971) );
OAI2BB2XLTS U6805 ( .B0(n5159), .B1(n4970), .A0N(result_add_subt[43]), .A1N(
n4971), .Y(n2458) );
OAI2BB2XLTS U6806 ( .B0(n5160), .B1(n4970), .A0N(result_add_subt[42]), .A1N(
n4971), .Y(n2454) );
OAI2BB2XLTS U6807 ( .B0(n5161), .B1(n4970), .A0N(result_add_subt[41]), .A1N(
n4971), .Y(n2450) );
OAI2BB2XLTS U6808 ( .B0(n5162), .B1(n4970), .A0N(result_add_subt[40]), .A1N(
n4971), .Y(n2446) );
OAI2BB2XLTS U6809 ( .B0(n5163), .B1(n4972), .A0N(result_add_subt[39]), .A1N(
n4971), .Y(n2442) );
OAI2BB2XLTS U6810 ( .B0(n5164), .B1(n4972), .A0N(result_add_subt[38]), .A1N(
n4971), .Y(n2438) );
OAI2BB2XLTS U6811 ( .B0(n5165), .B1(n4972), .A0N(result_add_subt[37]), .A1N(
n4971), .Y(n2434) );
OAI2BB2XLTS U6812 ( .B0(n5166), .B1(n4972), .A0N(result_add_subt[36]), .A1N(
n4971), .Y(n2430) );
OAI2BB2XLTS U6813 ( .B0(n5167), .B1(n4972), .A0N(result_add_subt[35]), .A1N(
n4971), .Y(n2426) );
OAI2BB2XLTS U6814 ( .B0(n5168), .B1(n4972), .A0N(result_add_subt[34]), .A1N(
n4971), .Y(n2422) );
OAI22X1TS U6815 ( .A0(n4973), .A1(n5048), .B0(n4976), .B1(n5072), .Y(n2386)
);
OAI22X1TS U6816 ( .A0(n4974), .A1(n5048), .B0(n4008), .B1(n5110), .Y(n2384)
);
CLKBUFX3TS U6817 ( .A(n4975), .Y(n4977) );
OAI2BB2XLTS U6818 ( .B0(n4976), .B1(n5199), .A0N(result_add_subt[22]), .A1N(
n4977), .Y(n2374) );
OAI2BB2XLTS U6819 ( .B0(n4976), .B1(n5200), .A0N(result_add_subt[21]), .A1N(
n4977), .Y(n2370) );
OAI2BB2XLTS U6820 ( .B0(n5173), .B1(n4979), .A0N(result_add_subt[20]), .A1N(
n4977), .Y(n2366) );
OAI2BB2XLTS U6821 ( .B0(n5174), .B1(n4979), .A0N(result_add_subt[19]), .A1N(
n4977), .Y(n2362) );
OAI2BB2XLTS U6822 ( .B0(n5175), .B1(n4979), .A0N(result_add_subt[18]), .A1N(
n4977), .Y(n2358) );
OAI2BB2XLTS U6823 ( .B0(n5176), .B1(n4979), .A0N(result_add_subt[17]), .A1N(
n4977), .Y(n2354) );
OAI2BB2XLTS U6824 ( .B0(n5177), .B1(n4979), .A0N(result_add_subt[16]), .A1N(
n4977), .Y(n2350) );
OAI2BB2XLTS U6825 ( .B0(n5178), .B1(n4979), .A0N(result_add_subt[15]), .A1N(
n4977), .Y(n2346) );
OAI2BB2XLTS U6826 ( .B0(n5179), .B1(n4980), .A0N(result_add_subt[14]), .A1N(
n4977), .Y(n2342) );
OAI2BB2XLTS U6827 ( .B0(n5180), .B1(n4979), .A0N(result_add_subt[13]), .A1N(
n4977), .Y(n2338) );
CLKBUFX3TS U6828 ( .A(n4978), .Y(n4981) );
OAI2BB2XLTS U6829 ( .B0(n5181), .B1(n4980), .A0N(result_add_subt[12]), .A1N(
n4981), .Y(n2334) );
OAI2BB2XLTS U6830 ( .B0(n5182), .B1(n4979), .A0N(result_add_subt[11]), .A1N(
n4981), .Y(n2330) );
OAI2BB2XLTS U6831 ( .B0(n5183), .B1(n4980), .A0N(result_add_subt[10]), .A1N(
n4981), .Y(n2326) );
OAI2BB2XLTS U6832 ( .B0(n5184), .B1(n4982), .A0N(result_add_subt[9]), .A1N(
n4981), .Y(n2322) );
OAI2BB2XLTS U6833 ( .B0(n5185), .B1(n4982), .A0N(result_add_subt[8]), .A1N(
n4981), .Y(n2318) );
OAI2BB2XLTS U6834 ( .B0(n5186), .B1(n4982), .A0N(result_add_subt[7]), .A1N(
n4981), .Y(n2314) );
OAI2BB2XLTS U6835 ( .B0(n5187), .B1(n4980), .A0N(result_add_subt[6]), .A1N(
n4981), .Y(n2310) );
OAI2BB2XLTS U6836 ( .B0(n5188), .B1(n4982), .A0N(result_add_subt[5]), .A1N(
n4981), .Y(n2306) );
OAI2BB2XLTS U6837 ( .B0(n5189), .B1(n4980), .A0N(result_add_subt[4]), .A1N(
n4981), .Y(n2302) );
OAI2BB2XLTS U6838 ( .B0(n5190), .B1(n4982), .A0N(result_add_subt[3]), .A1N(
n4981), .Y(n2298) );
OAI22X1TS U6839 ( .A0(n4983), .A1(n5044), .B0(n5089), .B1(n4985), .Y(n2114)
);
OAI2BB2XLTS U6840 ( .B0(n5140), .B1(n4985), .A0N(n4984), .A1N(d_ff2_Y[56]),
.Y(n2110) );
OAI22X1TS U6841 ( .A0(n4983), .A1(n5045), .B0(n5090), .B1(n4985), .Y(n2108)
);
OAI22X1TS U6842 ( .A0(n4983), .A1(n5046), .B0(n5091), .B1(n4985), .Y(n2106)
);
OAI2BB2XLTS U6843 ( .B0(n5141), .B1(n4985), .A0N(n4984), .A1N(d_ff2_Y[62]),
.Y(n2104) );
AOI21X1TS U6844 ( .A0(n4987), .A1(n4986), .B0(add_subt_module_intDX[63]),
.Y(n4990) );
AOI21X1TS U6845 ( .A0(n4991), .A1(n4988), .B0(n5007), .Y(n4989) );
OAI22X1TS U6846 ( .A0(n4991), .A1(n5105), .B0(n4990), .B1(n4989), .Y(n1943)
);
AOI22X1TS U6847 ( .A0(add_subt_module_intDY[59]), .A1(n3792), .B0(
add_subt_module_DMP[59]), .B1(n4994), .Y(n4993) );
OAI2BB1X1TS U6848 ( .A0N(add_subt_module_intDX[59]), .A1N(n5007), .B0(n4993),
.Y(n1931) );
AOI22X1TS U6849 ( .A0(add_subt_module_intDX[54]), .A1(n4992), .B0(
add_subt_module_DmP[54]), .B1(n4994), .Y(n4995) );
OAI2BB1X1TS U6850 ( .A0N(add_subt_module_intDY[54]), .A1N(n4996), .B0(n4995),
.Y(n1917) );
AOI22X1TS U6851 ( .A0(add_subt_module_intDX[53]), .A1(n3812), .B0(
add_subt_module_DmP[53]), .B1(n4997), .Y(n4999) );
OAI2BB1X1TS U6852 ( .A0N(add_subt_module_intDY[53]), .A1N(n3869), .B0(n4999),
.Y(n1914) );
AOI22X1TS U6853 ( .A0(add_subt_module_intDY[45]), .A1(n4992), .B0(
add_subt_module_DMP[45]), .B1(n5000), .Y(n5002) );
OAI2BB1X1TS U6854 ( .A0N(add_subt_module_intDX[45]), .A1N(n5007), .B0(n5002),
.Y(n1854) );
AOI22X1TS U6855 ( .A0(add_subt_module_intDY[7]), .A1(n3915), .B0(
add_subt_module_DMP[7]), .B1(n5003), .Y(n5004) );
OAI2BB1X1TS U6856 ( .A0N(add_subt_module_intDX[7]), .A1N(n5007), .B0(n5004),
.Y(n1717) );
AOI22X1TS U6857 ( .A0(add_subt_module_intDY[6]), .A1(n5005), .B0(
add_subt_module_DMP[6]), .B1(n3911), .Y(n5006) );
OAI2BB1X1TS U6858 ( .A0N(add_subt_module_intDX[6]), .A1N(n5007), .B0(n5006),
.Y(n1712) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_noclk.tcl_syn.sdf");
endmodule
|
(*** An approach to representing Models with inductive types ***)
Require Import List.
Import ListNotations.
(* Require Export Coq.Logic.Eqdep. *)
Add LoadPath "." as Specware.
Require Import Specware.Util.
Section Spec.
(* The type of spec fields *)
Variable F : Set.
Variable F_dec : forall (f1 f2 : F), {f1=f2} + {f1<>f2}.
(**
** Models and specs
**)
(* A Model is an element of the record type denoted by a Sig *)
Inductive Model : Type :=
| Model_Nil : Model
| Model_Cons (fld:F) A (a : A) (M:Model) : Model
.
(* A Spec is a partial Model of a Sig; README: Specs are indexed with
their fields so that the fields they contain are known: i.e., even
an inconsistent Spec has a fixed list of fields *)
Inductive Spec : forall {flds : list F}, Type :=
| Spec_Nil : Spec (flds:=nil)
| Spec_ConsNone f A {flds} :
~ In f flds ->
(forall (a:A), Spec (flds:=flds)) -> Spec (flds:= f :: flds)
| Spec_ConsSome f A (a : A) {flds} :
~ In f flds ->
Spec (flds:=flds) ->
Spec (flds:= f :: flds)
.
(* helper function for printing purposes *)
(* Definition get_fields {flds} (spec : @Spec flds) := flds. *)
(**
** Notions of elements of structures
**)
(* Get the fields of a Model *)
Fixpoint modelFields (M : Model) : list F :=
match M with
| Model_Nil => []
| Model_Cons fld _ _ M' => fld :: modelFields M'
end.
(* Proof that field f is associated with element a of type A in model *)
Inductive ModelElem (fld : F) A (a:A) : Model -> Prop :=
| ModelElem_Base (model : Model) :
ModelElem fld A a (Model_Cons fld A a model)
| ModelElem_Cons fld' A' a' (model : Model) :
ModelElem fld A a model ->
ModelElem fld A a (Model_Cons fld' A' a' model)
.
(* Model_Nil has no ModelElems *)
Lemma not_ModelElem_nil (fld : F) A (a:A) :
ModelElem fld A a Model_Nil -> False.
assert (forall model,
ModelElem fld A a model -> model = Model_Nil -> False).
intros model melem e; induction melem; discriminate.
intro melem; apply (H _ melem); reflexivity.
Qed.
(* Projecting an element out of a Model *)
(* FIXME: update or remove
Fixpoint modelProj (model : Model) :
forall f, In f (modelFields model) -> { A : Type & A } :=
match model in Model (flds:=flds)
return forall f, In f flds -> { A : Type & A }
with
| Model_Nil => fun f in_nil => False_rect _ in_nil
| Model_Cons f' A a _ model =>
fun f in_pf =>
match F_dec f' f with
| left _ => existT id A a
| right neq =>
modelProj model f (or_proj_r _ _ neq in_pf)
end
end.
(* Correctness of modelProj: always returns a ModelElem *)
Lemma modelProj_correct flds (model : Model (flds:=flds)) f in_pf :
ModelElem f (projT1 (modelProj model f in_pf))
(projT2 (modelProj model f in_pf))
model.
revert f in_pf; induction model; intros.
elimtype False; apply in_pf.
unfold modelProj; fold (modelProj (flds:=flds)).
destruct (F_dec f f0).
rewrite <- e; apply ModelElem_Base.
apply ModelElem_Cons.
apply IHmodel.
Qed.
*)
(**
** Defining the notion of models of specs
**)
Fixpoint IsModel (model : Model) {flds} (spec : Spec (flds:=flds)) {struct spec} : Prop :=
match spec in Spec (flds:=flds) with
| Spec_Nil => True
| Spec_ConsNone f A _ _ specF =>
exists a, ModelElem f A a model /\ IsModel model (specF a)
| Spec_ConsSome f A a _ _ spec' =>
ModelElem f A a model /\ IsModel model spec'
end.
Definition IsModel_Nil model : IsModel model Spec_Nil := I.
Definition IsModel_ConsNone model f A a {flds} not_in
(spec : A -> Spec (flds:=flds))
(melem : ModelElem f A a model) (ism : IsModel model (spec a)) :
IsModel model (Spec_ConsNone f A not_in spec).
exists a; split; assumption.
Qed.
Definition IsModel_ConsSome model f A a {flds} not_in
(spec : Spec (flds:=flds))
(melem : ModelElem f A a model) (ism : IsModel model spec) :
IsModel model (Spec_ConsSome f A a not_in spec).
split; assumption.
Qed.
(* A model of a Spec contains an element for each field in the spec *)
(* README: old, inductive version
Inductive IsModel (model : Model) :
forall {flds}, Spec (flds:=flds) -> Prop :=
| IsModel_Nil : IsModel model Spec_Nil
| IsModel_ConsNone f A a flds (spec : A -> Spec (flds:=flds)) :
ModelElem f A a model ->
IsModel model (spec a) ->
IsModel model (Spec_ConsNone f A spec)
| IsModel_ConsSome f A a flds (spec : Spec (flds:=flds)) :
ModelElem f A a model ->
IsModel model spec ->
IsModel model (Spec_ConsSome f A a spec)
.
*)
Lemma IsModel_nil_spec {flds} (spec : Spec (flds:=flds)) :
IsModel Model_Nil spec -> eq_dep _ (@Spec) _ spec _ Spec_Nil.
induction spec; intro ism.
reflexivity.
destruct ism as [ a sig ]; destruct sig as [ melem ism ];
elimtype False; apply (not_ModelElem_nil _ _ _ melem).
destruct ism as [ melem ism ];
elimtype False; apply (not_ModelElem_nil _ _ _ melem).
Qed.
(*
Lemma IsModel_ConsNone_inversion model {flds} f A
(spec : A -> Spec (flds:=flds)) :
IsModel model (Spec_ConsNone f A spec) ->
exists a, ModelElem f A a model /\ IsModel model (spec a).
intro ism; inversion ism.
exists a; split; [ assumption | ].
assert (spec1 = spec).
apply (inj_pair2_flds (inj_pair2_flds H3)).
*)
(* FIXME: write prove_ismodel tactic *)
(*
Lemma ModelElem_to_SpecElem {flds_m} (model : Model (flds:=flds_m))
{flds_s} (spec : Spec (flds:=flds_s)) f A a :
ModelElem f A a
*)
FIXME HERE: need a notion of when a FieldMap applies to a spec
(**
** Field maps: finite functions on Fs
**)
(* A FieldMap is represented as a list of pairs *)
Definition FieldMap := list (F * F).
(* The identity FieldMap *)
Definition idFM : FieldMap := [].
(* Apply a FieldMap to a F *)
Fixpoint applyFM (m : FieldMap) (str : F) : F :=
match m with
| [] => str
| (str_from, str_to) :: m' =>
if F_dec str str_from then str_to else
applyFM m' str
end.
(* Applying idFM is the identity *)
Lemma idFM_is_id (str : F) : applyFM idFM str = str.
reflexivity.
Qed.
(* compose two FieldMaps, applying m1 and then m2 *)
Fixpoint composeFM (m1 m2 : FieldMap) : FieldMap :=
match m1 with
| [] => m2
| (str_from, str_to) :: m1' =>
(str_from, applyFM m2 str_to) :: composeFM m1' m2
end.
(* composition works as expected *)
Lemma FieldMap_compose m1 m2 str :
applyFM (composeFM m1 m2) str = applyFM m2 (applyFM m1 str).
induction m1.
reflexivity.
destruct a as [ str_from str_to ]; unfold composeFM; fold composeFM.
unfold applyFM; fold applyFM.
destruct (F_dec str str_from).
reflexivity.
apply IHm1.
Qed.
(* Return the list of Fs that map to an output F *)
Fixpoint semiInvertFM (m : FieldMap) str : list F :=
match m with
| [] => [str]
| (str_from, str_to) :: m' =>
if F_dec str str_to then str_from :: semiInvertFM m' str
else remove F_dec str_from (semiInvertFM m' str)
end.
(* semiInvertFM returns only Fs that map back to str *)
Lemma semiInvertFM_sound m str str' :
In str' (semiInvertFM m str) -> applyFM m str' = str.
induction m.
intro in_pf; destruct in_pf;
[ rewrite H; reflexivity | destruct H ].
destruct a as [ str_from str_to ]; unfold applyFM; fold applyFM.
unfold semiInvertFM; fold semiInvertFM.
destruct (F_dec str str_to); intro in_pf;
destruct (F_dec str' str_from).
rewrite e; reflexivity.
apply IHm; destruct in_pf;
[ elimtype False; apply n; rewrite H; reflexivity | assumption ].
rewrite e in in_pf; elimtype False; apply (remove_In _ _ _ in_pf).
apply IHm; apply (In_remove _ _ _ _ in_pf).
Qed.
(* semiInvertFM returns all Fs that map back to str *)
Lemma semiInvertFM_complete m str str' :
applyFM m str' = str -> In str' (semiInvertFM m str).
induction m; unfold applyFM; fold applyFM.
intro e; left; symmetry; assumption.
destruct a as [ str_from str_to ]; unfold semiInvertFM; fold semiInvertFM.
destruct (F_dec str' str_from); intro eApp.
rewrite eApp; rewrite F_dec_true; left; symmetry; assumption.
destruct (F_dec str str_to).
right; apply IHm; assumption.
apply remove_not_eq; [ assumption | apply IHm; assumption ].
Qed.
(* str is always in semiInvertFM m (applyFM m str) *)
Lemma in_semiInvert_apply m str : In str (semiInvertFM m (applyFM m str)).
apply semiInvertFM_complete; reflexivity.
Qed.
(**
** Mapping functions over structures
**)
Fixpoint model_map (m : FieldMap) (model : Model) : Model :=
match model with
| Model_Nil => Model_Nil
| Model_Cons f A a model =>
Model_Cons (applyFM m f) A a (model_map m model)
end.
Fixpoint spec_map (m : FieldMap) {flds} (spec : Spec (flds:=flds)) :
Spec (flds:=map (applyFM m) flds) :=
match spec in Spec (flds:=flds) return Spec (flds:=map (applyFM m) flds) with
| Spec_Nil => Spec_Nil
| Spec_ConsNone f A flds spec =>
Spec_ConsNone (applyFM m f) A (fun a => spec_map m (spec a))
| Spec_ConsSome f A a flds spec =>
Spec_ConsSome (applyFM m f) A a (spec_map m spec)
end.
(* mapping id over a model is the identity itself *)
Lemma model_map_id model : model_map idFM model = model.
induction model.
reflexivity.
unfold model_map; fold model_map. f_equal. assumption.
Qed.
(* mapping id over a spec is the identity itself *)
Lemma spec_map_id {flds} (spec : Spec (flds:=flds)) :
eq_dep _ (@Spec) _ (spec_map idFM spec) _ spec.
induction spec.
apply eq_dep_intro.
apply (eq_dep_ctx _ (fun fs => A -> @Spec fs)
(map id flds) flds (fun a => spec_map idFM (s a)) s
_ (fun fs => f :: fs)
_ (fun _ spec => Spec_ConsNone f A spec)).
apply eq_dep_flds_fun; [ apply map_id | assumption ].
apply (eq_dep_ctx _ (@Spec)
_ _ _ _ _ (fun fs => f :: fs) _ (fun _ => Spec_ConsSome f A a)
IHspec).
Qed.
(* if the result of spec_map is Spec_Nil, then the input is as well *)
Lemma spec_map_to_Nil m {flds} (spec : Spec (flds:=flds)) :
eq_dep _ (@Spec) _ (spec_map m spec) _ Spec_Nil ->
eq_dep _ (@Spec) _ spec _ Spec_Nil.
induction spec; unfold spec_map; fold spec_map; intro e;
[ reflexivity | | ];
(assert (map (applyFM m) (f :: flds) = []);
[ apply (eq_dep_fst e) | discriminate ]).
Qed.
(* if the result of spec_map is a Spec_ConsNone, then the input is as well *)
(* FIXME: prove or remove
Lemma spec_map_to_ConsNone m {flds} (spec : Spec (flds:=flds))
f' A {flds'} (spec' : A -> Spec (flds:=flds')) :
eq_dep _ (@Spec) _ (spec_map m spec) _ (Spec_ConsNone f' A spec') ->
{ f'':_ & { flds'':_ & { spec'' : A -> Spec (flds:=flds'') |
eq_dep _ (@Spec) _ spec
_ (Spec_ConsNone f'' A spec'') }}}.
induction spec; unfold spec_map; fold spec_map; intro e.
assert ([] = f' :: flds'); [ apply (eq_dep_fst e) | discriminate ].
assert (map (applyFM m) (f :: flds) = f' :: flds') as H;
[ apply (eq_dep_fst e) | ].
injection H; intros e_flds' e_f'.
revert s spec' X e; rewrite <- e_f'; rewrite <- e_flds'; intros.
assert (Spec_ConsNone (applyFM m f) A0 (fun a : A0 => spec_map m (s a))
= Spec_ConsNone (applyFM m f) A spec');
apply (eq_dep_eq_flds _ e).
assert (A0 = A) as H;
[
| revert s X e; rewrite H; intros;
exists f; exists flds; exists s; reflexivity ].
[ reflexivity | | ];
(assert (map (applyFM m) (f :: flds) = []);
[ apply (eq_dep_fst e) | discriminate ]).
Qed.
*)
(* composing two spec_maps together *)
Lemma spec_map_comp {flds} (spec : Spec (flds:=flds)) m1 m2 :
eq_dep _ (@Spec) _ (spec_map m2 (spec_map m1 spec)) _
(spec_map (composeFM m1 m2) spec).
induction spec.
apply eq_dep_intro.
unfold map; fold (map (applyFM m1)); fold (map (applyFM m2));
fold (map (applyFM (composeFM m1 m2))).
unfold spec_map; fold spec_map; rewrite FieldMap_compose.
apply (eq_dep_ctx _ (fun fs => A -> @Spec fs)
(map (applyFM m2) (map (applyFM m1) flds))
(map (applyFM (composeFM m1 m2)) flds)
(fun a => spec_map m2 (spec_map m1 (s a)))
(fun a => spec_map (composeFM m1 m2) (s a))
_ (fun fs => applyFM m2 (applyFM m1 f) :: fs)
_ (fun _ spec => Spec_ConsNone (applyFM m2 (applyFM m1 f)) A spec)
).
apply eq_dep_flds_fun;
[ rewrite map_map; apply map_ext;
intro fld; symmetry; apply FieldMap_compose
| assumption ].
unfold map; fold (map (applyFM m1)); fold (map (applyFM m2));
fold (map (applyFM (composeFM m1 m2))).
unfold spec_map; fold spec_map; rewrite FieldMap_compose.
apply (eq_dep_ctx _ (@Spec)
_ _ _ _ _
(fun fs => _ :: fs) _ (fun _ => Spec_ConsSome _ A a)
IHspec).
Qed.
(* FIXME: generalize spec_map_id and spec_map_comp into a Lemma and/or
tactic for proving things about specs *)
(* ModelElem commutes with mapping *)
Lemma ModelElem_map model m f A a :
ModelElem f A a model -> ModelElem (applyFM m f) A a (model_map m model).
intro melem; induction melem.
apply ModelElem_Base.
apply ModelElem_Cons; apply IHmelem.
Qed.
(* SpecElem commutes with mapping *)
(*
Lemma SpecElem_map {flds} (spec : Spec (flds:=flds)) m f A a :
SpecElem f A a spec ->
SpecElem (m f) A a (spec_map m spec).
intro selem; induction selem.
apply SpecElem_BaseNone.
apply SpecElem_BaseSome.
unfold spec_map; fold spec_map; apply SpecElem_ConsNone; assumption.
unfold spec_map; fold spec_map; apply SpecElem_ConsSome; assumption.
Qed.
*)
(* IsModel commutes with mapping *)
(* FIXME: prove or remove *)
(*
Lemma IsModel_map_commutes (g : F -> F)
{flds_s} (spec : Spec (flds:=flds_s))
{flds_m} (model : Model (flds:=flds_m)) :
IsModel model spec ->
IsModel (model_map g model) (spec_map g spec).
intro ism; induction ism.
apply IsModel_Nil.
apply IsModel_ConsNone; apply IHism.
apply IsModel_ConsSome; apply IHism.
Qed.
*)
(* FIXME: this no longer holds!
Lemma SuperModel_map_trans {flds1} (model1 : Model (flds:=flds1))
{flds2} (model2 : Model (flds:=flds2))
{flds3} (model3 : Model (flds:=flds3))
m1 m2 :
SuperModel model3 (model_map m2 model2) ->
SuperModel model2 (model_map m1 model1) ->
SuperModel model3 (model_map (fun x : F => m2 (m1 x)) model1).
induction model1.
intros super32 super21 f A a melem; inversion melem.
unfold model_map; fold model_map;
intros super32 super21 f' A' a' melem1.
apply (super32 f' A' a'). apply ModelElem_map.
apply (super21 f' A' a').
destruct super21 as [ melem2 super21 ].
split.
apply (SuperModel_elem (model_map m2 model2)); [ apply ModelElem_map | ]; assumption.
apply IHmodel1; assumption.
Qed.
*)
(**
** Model "un-mapping", which is a weak right inverse of model
** mapping; i.e., model_map m (model_unmap m model) has at least all
** of the same model elements of model
**)
(* Apply Model_Cons once for each field name in a list *)
Fixpoint multi_Model_Cons (flds : list F) A (a : A) model :=
match flds with
| [] => model
| fld :: flds' => Model_Cons fld A a (multi_Model_Cons flds' A a model)
end.
Lemma In_multi_Model_Cons (flds : list F) A (a : A) model f :
In f flds -> ModelElem f A a (multi_Model_Cons flds A a model).
induction flds; intro in_pf.
inversion in_pf.
destruct in_pf.
rewrite H; apply ModelElem_Base.
apply ModelElem_Cons; apply IHflds; assumption.
Qed.
Lemma multi_Model_Cons_ModelElem (flds : list F) A (a : A) model f A' a' :
ModelElem f A' a' model ->
ModelElem f A' a' (multi_Model_Cons flds A a model).
induction flds; intro melem.
apply melem.
apply ModelElem_Cons; apply IHflds; assumption.
Qed.
Lemma multi_Model_Cons_un_ModelElem (flds : list F) A (a : A) model f A' a' :
ModelElem f A' a' (multi_Model_Cons flds A a model) ->
(In f flds /\ eq_dep _ id A a A' a') \/ ModelElem f A' a' model.
revert A a model f A' a'; induction flds; intros.
right; assumption.
inversion H.
left; split; [ left; reflexivity | reflexivity ].
destruct (IHflds _ _ _ _ _ _ H1).
destruct H5; left; split; [ right | ]; assumption.
right; assumption.
Qed.
(* Un-map a model *)
Fixpoint model_unmap (m : FieldMap) (model : Model) {struct model} : Model :=
match model with
| Model_Nil => Model_Nil
| Model_Cons fld A a model =>
multi_Model_Cons (semiInvertFM m fld) A a (model_unmap m model)
end.
(* Un-mapping the identity function is an identity *)
Lemma model_unmap_id model : model_unmap idFM model = model.
induction model.
reflexivity.
unfold model_unmap; fold model_unmap.
unfold idFM; unfold semiInvertFM;
unfold idFM in IHmodel; rewrite IHmodel; reflexivity.
Qed.
(* applyFM and model_unmap form an adjunction w.r.t. ModelElem *)
Lemma ModelElem_spec_map_model_unmap f A a model m :
ModelElem (applyFM m f) A a model <-> ModelElem f A a (model_unmap m model).
split; intro melem.
induction melem; unfold model_unmap; fold model_unmap.
apply In_multi_Model_Cons; apply in_semiInvert_apply.
apply multi_Model_Cons_ModelElem; assumption.
induction model.
inversion melem.
unfold model_unmap in melem; fold model_unmap in melem.
destruct (multi_Model_Cons_un_ModelElem _ _ _ _ _ _ _ melem).
destruct H.
rewrite H0. rewrite (semiInvertFM_sound _ _ _ H).
apply ModelElem_Base.
apply ModelElem_Cons; apply IHmodel; assumption.
Qed.
(* spec_map and model_unmap form an adjunction w.r.t. IsModel *)
Lemma IsModel_spec_map_model_unmap model {flds} (spec : Spec (flds:=flds)) m :
IsModel model (spec_map m spec) <-> IsModel (model_unmap m model) spec.
split.
induction spec; unfold spec_map; fold spec_map; intro ism.
apply IsModel_Nil.
destruct ism as [ a sig ]; destruct sig as [ melem ism ].
exists a; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply H; assumption ].
destruct ism as [ melem ism ]; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply IHspec; assumption ].
induction spec; intro ism; unfold spec_map; fold spec_map.
apply IsModel_Nil.
destruct ism as [ a sig ]; destruct sig as [ melem ism ].
exists a; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply H; assumption ].
destruct ism as [ melem ism ]; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply IHspec; assumption ].
Qed.
(**
** Morphisms
**)
(* A morphism maps the elements of one spec to those of another *)
(*
2Definition IsMorphism_spec {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
(m : F -> F) : Prop :=
forall f A a,
SpecElem f A a spec1 ->
SpecElem (m f) A a spec2.
*)
(* Another def of morphisms, as being a subset mapping for models *)
Definition IsMorphism {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
(m : FieldMap) : Prop :=
forall model,
IsModel model spec2 ->
IsModel model (spec_map m spec1).
(* proof that the two definitions are equivalent *)
(*
Lemma IsMorphism_equiv {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
(m : F -> F) :
IsMorphism spec1 spec2 m <-> IsMorphism_models spec1 spec2 m.
split.
*)
Inductive Morphism {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2)) :=
| mkMorphism m : IsMorphism spec1 spec2 m -> Morphism spec1 spec2.
Definition projMorph {flds1 spec1 flds2 spec2}
(morph : @Morphism flds1 spec1 flds2 spec2) : FieldMap :=
match morph with
| mkMorphism m _ => m
end.
Definition projMorph_pf {flds1 spec1 flds2 spec2}
(morph : @Morphism flds1 spec1 flds2 spec2) :
IsMorphism spec1 spec2 (projMorph morph) :=
match morph with
| mkMorphism _ pf => pf
end.
(**
** Morphisms as a category
**)
Lemma IsMorphism_id {flds} (spec : Spec (flds:=flds)) :
IsMorphism spec spec idFM.
intros model ism.
rewrite spec_map_id; assumption.
Qed.
Definition mid {flds} spec :
Morphism (flds1:=flds) spec (flds2:=flds) spec :=
mkMorphism spec spec idFM (IsMorphism_id _).
(*
Lemma IsMorphism_map {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2)) m1 m2 :
IsMorphism spec1 spec2 m1 ->
forall model,
IsModel model (spec_map m' spec2) ->
IsModel model (spec_map (fun f => m' (m f)) spec1).
induction spec1.
intros; apply IsModel_Nil.
intros.
FIXME HERE: how to prove this?!?
IDEA: "un-map" a model along an m, given a set of input fields:
- un-mapping should depend only on m and flds
- NOTE: might duplicate some fields, since model might have duplicate fields,
so we define unmap_flds : flds -> m -> model -> list F and
unmap : forall flds m model, Model (flds:=unmap_flds flds m model)
- need IsModel model (spec_map m spec) <-> IsModel (unmap flds m model) spec
- can then unmap, pass to the original IsMorphism, and then undo the unmapping
IsMorphism (spec_map m' spec1) (spec_map m' spec2)
*)
Lemma IsMorphism_trans {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
{flds3} (spec3 : Spec (flds:=flds3))
m1 m2 :
IsMorphism spec1 spec2 m1 ->
IsMorphism spec2 spec3 m2 ->
IsMorphism spec1 spec3 (composeFM m1 m2).
intros ismorph1 ismorph2 model ism3.
rewrite <- spec_map_comp.
apply IsModel_spec_map_model_unmap.
apply ismorph1.
apply IsModel_spec_map_model_unmap.
apply ismorph2.
assumption.
Qed.
Definition mcompose {flds1} {spec1 : Spec (flds:=flds1)}
{flds2} {spec2 : Spec (flds:=flds2)}
{flds3} {spec3 : Spec (flds:=flds3)}
(morph1 : Morphism spec1 spec2)
(morph2 : Morphism spec2 spec3) : Morphism spec1 spec3 :=
mkMorphism spec1 spec3 (composeFM (projMorph morph1) (projMorph morph2))
(IsMorphism_trans _ _ _ _ _ (projMorph_pf morph1) (projMorph_pf morph2)).
(**
** Syntax for specs and morphism
**)
(*
FIXME HERE: figure out notations
*)
(* one approach that works... *)
(*
Notation "{| |}" := Spec_Nil (at level 80).
Notation "{| spec |}" := spec.
Notation "end-spec" := Spec_Nil (at level 80).
Notation "f : A := a ; spec" := (Spec_ConsSome f A a spec) (at level 80, spec at level 80).
Notation "f : A ; x => spec" := (Spec_ConsNone f A (fun x => spec)) (at level 80, x ident, spec at level 80).
*)
(* another approach, which always prints one {| |} pair for each level of the spec *)
(*
Notation "{| f : A := a ; spec |}" := (Spec_ConsSome f A a spec) (at level 80, f at level 99, spec at level 80).
Notation "{| f : A ; x => spec |}" := (Spec_ConsNone f A (fun x => spec)) (at level 80, x ident, f at level 99, spec at level 80).
*)
Delimit Scope spec_scope with spec_scope.
(* Bind Scope spec_scope with Spec. *)
Global Notation "end-spec" := Spec_Nil (at level 80).
Global Notation "{# spec #}" := (spec%spec_scope : Spec) (at level 100).
Global Notation "f ::: A := a ; spec" := (Spec_ConsSome f A a spec) (at level 80, spec at level 80) : spec_scope.
Global Notation "f ::: A ; x => spec" := (Spec_ConsNone f A (fun x => spec)) (at level 80, x ident, spec at level 80) : spec_scope.
(*
Notation "{{ f : A := a ; spec }}" := (Spec_ConsSome f A a (spec%spec_scope)) (at level 80, f at level 99, spec at level 80).
Notation "{{ f : A ; x => spec }}" := (Spec_ConsNone f A (fun x => (spec%spec_scope))) (at level 80, x ident, f at level 99, spec at level 80).
*)
Global Arguments Spec_ConsSome (f%string) _ _ _ (spec%spec_scope).
Global Arguments Spec_ConsNone (f%string) _ _ (spec%spec_scope).
(*
Eval compute in (Spec_ConsNone "f1" nat (fun f1 => Spec_ConsSome "f2" nat 0 Spec_Nil)).
Eval compute in ({# "f2" ::: nat := 0; end-spec #}).
Eval compute in ({# "f1" ::: nat ; f1 => "f2" ::: nat := 0; end-spec #}).
*)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_2_V
`define SKY130_FD_SC_HDLL__NOR4B_2_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: efc_tck.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: Efuse Cluster
// Unit Name: efc_tck (tck logic)
//
//-----------------------------------------------------------------------------
`include "sys.h"
`include "iop.h"
module efc_tck (/*AUTOARG*/
// Outputs
tck_shft_data_ff, efc_ctu_data_out,
// Inputs
read_data_ff, ctu_efc_data_in, ctu_efc_shiftdr, ctu_efc_capturedr,
tck
);
//-----------------------------------------------------------------------------
// I/O declarations
//-----------------------------------------------------------------------------
// CTU/JTAG Shift Interface
output [31:0] tck_shft_data_ff; // shift register data
input [31:0] read_data_ff; // read reg val
input ctu_efc_data_in; // Serial(scan) in from ctu
output efc_ctu_data_out; // Serial(scan) out to ctu
input ctu_efc_shiftdr; // shift data register
input ctu_efc_capturedr; // shift data reg captures read reg val
input tck; // Shift dr data in/out from ctu
//-----------------------------------------------------------------------------
// Wire/reg declarations
//-----------------------------------------------------------------------------
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
wire [31:0] tck_shft_data_nxt;
wire [31:0] tck_shft_data_ff;
//-----------------------------------------------------------------------------
// Module Body
//-----------------------------------------------------------------------------
assign tck_shft_data_nxt
= ctu_efc_capturedr ? read_data_ff
: ctu_efc_shiftdr ? {tck_shft_data_ff[30:0], ctu_efc_data_in}
: tck_shft_data_ff;
dff_ns #(32) tck_shft_data_reg (.din(tck_shft_data_nxt ),
.q(tck_shft_data_ff ), .clk(tck));
assign efc_ctu_data_out = tck_shft_data_ff[31];
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
module tri_light_svetofor ( //Этот модуль описывает блок имитации трехцветного светофора.
//A usual tricolor traffic light. Inverter logic, 1 is off.
input wire time_signal,
input wire reset,
output wire red,
output wire yellow,
output wire green
);
//Блок параметров - аналог констант в Verilog. Описываются временные интервалы
//каждого из режимов работы светофора, для проверок в блоке always.
//Значения умножаются на два так как даются в секундах, а отсчет времени идет полусекундными интервалами.
parameter green_time = 8'd26 * 8'd2, //Multiplier is 2, because time interval is a half-second.
red_time = 8'd84 * 8'd2,
yellow_time = 8'd3 * 8'd2,
blnk_time = 8'd4 * 8'd2,
tril_time = green_time + blnk_time + red_time + yellow_time * 8'd2;
reg [7:0] timer; //Счетчик сигналов времени.
//A time keeper for this module.
reg [2:0] sel_color; //Регистр выбора цвета светофора. 0 бит - красный, 1 бит - желтый, 2 бит - зеленый.
//Активный сигнал для светодиодов - ноль.
//An output selector: 0 bit - red, 1 bit - yellow, 2 bit - green. A zero level is active.
//Соединение выходных проводов модуля с соотвествующими битами регистра выбора цвета.
//Операция assign должна выполняться всегда и поэтому не может размещаться в поведенческом блоке always.
assign red = sel_color[0];
assign yellow = sel_color[1];
assign green = sel_color[2];
//Поведенческий блок always, выполняется по сигналам (по умолчанию - фронт) перечисленным в скобках.
//Только здесь возможно использование ветвлений и циклов verilog.
always @(posedge time_signal or negedge reset)
begin
//Здесь в операциях с регистрами используется неблокирующее присваивание "<=".
//Эти операции не выполняются в месте использования, а откладываются до конца блока always.
//Зато в конце блока они выполняются все разом, одновременно. Абсолютно ПАРАЛЛЕЛЬНО.
if (!reset) //Если нажата кнопка сброса (активный сигнал - ноль), то...
begin //A zero level is active.
timer <= 8'd0;
sel_color <= 3'b110; //Произвести установку регистров в начальное состояние.
//Работа светофора начинается с красного сигнала. Активный сигнал - ноль.
end
else //Иначе, вход сброса не в нулевом состоянии (там единица, z или вообще неопределенное состояние).
begin //Ниже идет логика работы светофора.
if (timer < tril_time) //Если значение счетчика не добралось до конца одного цикла работы светофора...
//Keep time counting.
timer <= timer + 8'd1; //Увеличить его еще на единицу.
else
timer <= 8'd0; //Иначе начать отсчет заново.
//Reset timer.
if (timer <= red_time) //Если значение таймера лежит в интервале работы красного света.
//A red color time.
sel_color <= 3'b110; //Включить красный (активный - ноль), а желтый и зеленый отключить.
//A yellow color time.
if (timer > red_time && timer <= red_time + yellow_time) //Желтый свет - переход от красного к зеленому.
sel_color <= 3'b100; //Горят два светодиода.
//A green color time.
if (timer > red_time + yellow_time && timer <= red_time + yellow_time + green_time) //Зеленый свет.
sel_color <= 3'b011; //Горит один светодиод, красный и желтый выключены.
//Окончание работы зеленого света.
//На протяжении этого интервала зеленый сигнал мигает с частотой сигнала времени.
//A green blinking.
if (timer > red_time + yellow_time + green_time && timer <= red_time + yellow_time + green_time + blnk_time)
if (sel_color == 3'b011)
sel_color <= 3'b111; //Выключить зеленый.
else
sel_color <= 3'b011; //Включить зеленый.
//A yellow color time.
//End of sequence. Next - timer reset.
//Переход от зеленого сигнала к красному. Конец цикла работы светофора.
//Дальше будет сброс таймера и все заново.
if (timer > red_time + yellow_time + green_time + blnk_time)
sel_color <= 3'b101; //Горит один светодиод - желтый.
end
end
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
reg port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_1_V
`define SKY130_FD_SC_LP__DFRTN_1_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_2_V
`define SKY130_FD_SC_HS__O32AI_2_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32ai_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:23:45 11/28/2017
// Design Name:
// Module Name: bram_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bram_controller(clk, reset, btn, wea, addra);
input wire clk, reset, btn;
output reg wea;
output reg [3:0] addra;
localparam [1:0]
idle = 2'b00,
leer = 2'b01,
fin = 2'b10;
reg [1:0] state_reg;
reg [3:0] counter;
always@(posedge clk, posedge reset)
if(reset)
begin
addra<=0;
counter<=0;
state_reg<=idle;
wea<=0;
end
else begin
case(state_reg)
idle:
if(btn==1'b1)begin
state_reg<=leer;
end
leer:
begin
wea<=0;
counter<=counter+1'b1;
state_reg<=fin;
end
fin:begin
addra<=addra+1'b1;
if(counter==4'b1111)begin
counter<=0;
end
state_reg<=idle;
end
endcase
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [4:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 12,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 25,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 4800,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20833,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.010000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.01000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4800"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__AND3B_BEHAVIORAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_BEHAVIORAL_PP_V |
`timescale 1 ns / 1 ps
module axis_averager #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 16,
parameter AXIS_TDATA_SIGNED = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] pre_data,
input wire [CNTR_WIDTH-1:0] tot_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
// FIFO_WRITE port
input wire fifo_write_full,
output wire [AXIS_TDATA_WIDTH-1:0] fifo_write_data,
output wire fifo_write_wren,
// FIFO_READ port
input wire fifo_read_empty,
input wire [AXIS_TDATA_WIDTH-1:0] fifo_read_data,
output wire fifo_read_rden
);
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_rden_reg, int_rden_next;
reg int_tvalid_reg, int_tvalid_next;
wire [AXIS_TDATA_WIDTH-1:0] int_data_wire, sum_data_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_rden_reg <= 1'b0;
int_tvalid_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_rden_reg <= int_rden_next;
int_tvalid_reg <= int_tvalid_next;
end
end
always @*
begin
int_cntr_next = int_cntr_reg;
int_rden_next = int_rden_reg;
int_tvalid_next = int_tvalid_reg;
if(s_axis_tvalid)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
if(s_axis_tvalid)
begin
int_cntr_next = int_cntr_reg + 1'b1;
if(int_cntr_reg == pre_data)
begin
int_rden_next = 1'b1;
int_tvalid_next = 1'b0;
end
if(int_cntr_reg == tot_data)
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_tvalid_next = 1'b1;
end
end
end
assign int_data_wire = ~int_tvalid_reg ? fifo_read_data : {(AXIS_TDATA_WIDTH){1'b0}};
generate
if(AXIS_TDATA_SIGNED == "TRUE")
begin : SIGNED
assign sum_data_wire = $signed(int_data_wire) + $signed(s_axis_tdata);
end
else
begin : UNSIGNED
assign sum_data_wire = int_data_wire + s_axis_tdata;
end
endgenerate
assign s_axis_tready = 1'b1;
assign m_axis_tdata = fifo_read_data;
assign m_axis_tvalid = int_tvalid_reg & s_axis_tvalid;
assign fifo_read_rden = int_rden_reg & s_axis_tvalid;
assign fifo_write_data = sum_data_wire;
assign fifo_write_wren = s_axis_tvalid;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O21BA_PP_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_M_V
`define SKY130_FD_SC_LP__EINVP_M_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_m (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_m (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_M_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_lp__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_lp__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_PP_SYMBOL_V
`define SKY130_FD_SC_HS__INV_PP_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_PP_SYMBOL_V
|
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