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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_1_V
`define SKY130_FD_SC_HS__EINVN_1_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvn_1 (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__einvn base (
.A(A),
.TE_B(TE_B),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvn_1 (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__einvn base (
.A(A),
.TE_B(TE_B),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_1_V
|
// file: clk_wiz_v3_6_0.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___125.000______0.000______50.0______125.247_____98.575
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_v3_6_0
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
//assign clkin1 = CLK_IN1;
BUFG clkin1_buf (
.I (CLK_IN1),
.O (clkin1)
);
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* $Date: 2014-08-23 15:24:59 -0400 (Sat, 23 Aug 2014) $ *)
(* #################################### *)
(** * Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
Y ::= ANum 0;;
WHILE BNot (BEq (AId X) (ANum 0)) DO
Y ::= APlus (AId X) (AId Y) ;;
X ::= AMinus (AId X) (ANum 1)
END.
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
Definition foo : com :=
Z ::= (AId X) ;;
WHILE (BLe (ANum 2) (AId Z)) DO
Z ::= AMinus (AId Z) (ANum 2)
END
.
Example foo_1 :
test_ceval (update empty_state X 5) foo
= Some (5, 0, 1).
Proof. reflexivity. Qed.
Example foo_2 :
test_ceval (update empty_state X 6) foo
= Some (6, 0, 0).
Proof. reflexivity. Qed.
(** [] *)
(* ################################################################ *)
(** * Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* TODO: Informal proof ... hehe ... *)
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
exists 1. reflexivity.
exists 1. simpl. rewrite H. reflexivity.
Case "E_Seq".
inversion IHHce1 as [x1 H1].
inversion IHHce2 as [x2 H2].
exists (x1 + x2).
induction x1 as [|x1']. inversion H1.
induction x2 as [|x2']. inversion H2.
simpl.
assert (HH: ceval_step st c1 (S x1' + x2') = Some st').
apply ceval_step_more with (S x1'). omega. apply H1.
destruct (ceval_step st c1 (x1' + S x2')) eqn:HE.
rewrite <-plus_n_Sm in HE. rewrite <-plus_Sn_m in HE.
rewrite HH in HE. inversion HE. subst.
rewrite plus_comm.
apply ceval_step_more with (S x2'). omega.
assumption.
rewrite <-plus_n_Sm in HE. rewrite <-plus_Sn_m in HE.
rewrite HH in HE. inversion HE.
Case "E_IfTrue".
inversion IHHce. exists (S x).
simpl. rewrite H. assumption.
Case "E_IfFalse".
inversion IHHce. exists (S x).
simpl. rewrite H. assumption.
Case "E_WhileEnd".
exists 1. simpl. rewrite H. reflexivity.
Case "E_WhileLoop".
inversion IHHce1 as [x1 H1].
inversion IHHce2 as [x2 H2].
exists (x1 + x2).
induction x1 as [|x1']. inversion H1.
induction x2 as [|x2']. inversion H2.
simpl.
assert (HH: ceval_step st c (S x1' + x2') = Some st').
apply ceval_step_more with (S x1'). omega. apply H1.
destruct (ceval_step st c (x1' + S x2')) eqn:HE.
rewrite <-plus_n_Sm in HE. rewrite <-plus_Sn_m in HE.
rewrite HH in HE. inversion HE. subst.
rewrite plus_comm.
rewrite H.
apply ceval_step_more with (S x2'). omega.
assumption.
rewrite H.
rewrite <-plus_n_Sm in HE. rewrite <-plus_Sn_m in HE.
rewrite HH in HE. inversion HE.
Qed.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** * Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_SYMBOL_V
`define SKY130_FD_SC_LP__MAJ3_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__maj3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_SYMBOL_V
|
// ?????
//------------------------------------------------------------------------------------------------------------
module clk_gen (clk,reset,clk1,clk2,clk4,fetch,alu_clk);
input clk,reset;
output clk1,clk2,clk4,fetch,alu_clk;
wire clk,reset;
reg clk2,clk4,fetch,alu_clk;
reg[7:0] state;
parameter S1 = 8'b00000001,
S2 = 8'b00000010,
S3 = 8'b00000100,
S4 = 8'b00001000,
S5 = 8'b00010000,
S6 = 8'b00100000,
S7 = 8'b01000000,
S8 = 8'b10000000,
idle = 8'b00000000;
assign clk1 = ~clk;
always @(negedge clk)
if(reset)
begin
clk2 <= 0;
clk4 <= 1;
fetch <= 0;
alu_clk <= 0;
state <= idle;
end
else
begin
case(state)
S1:
begin
clk2 <= ~clk2;
alu_clk <= ~alu_clk;
state <= S2;
end
S2:
begin
clk2 <= ~clk2;
clk4 <= ~clk4;
alu_clk <= ~alu_clk;
state <= S3;
end
S3:
begin
clk2 <= ~clk2;
state <= S4;
end
S4:
begin
clk2 <= ~clk2;
clk4 <= ~clk4;
fetch <= ~fetch;
state <= S5;
end
S5:
begin
clk2 <= ~clk2;
state <= S6;
end
S6:
begin
clk2 <= ~clk2;
clk4 <= ~clk4;
state <= S7;
end
S7:
begin
clk2 <= ~clk2;
state <= S8;
end
S8:
begin
clk2 <= ~clk2;
clk4 <= ~clk4;
fetch <= ~fetch;
state <= S1;
end
idle: state <= S1;
default: state <= idle;
endcase
end
endmodule
//--------------------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_PP_BLACKBOX_V
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
`define low_pos(w,b) ((w)*64 + (b)*8)
`define low_pos2(w,b) `low_pos(w,7-b)
`define high_pos(w,b) (`low_pos(w,b) + 7)
`define high_pos2(w,b) (`low_pos2(w,b) + 7)
module keccak(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready);
input clk, reset;
input [31:0] in;
input in_ready, is_last;
input [1:0] byte_num;
output buffer_full; /* to "user" module */
output [511:0] out;
output reg out_ready;
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
wire [575:0] padder_out,
padder_out_1; /* before reorder byte */
wire padder_out_ready;
wire f_ack;
wire [1599:0] f_out;
wire f_out_ready;
wire [511:0] out1; /* before reorder byte */
reg [22:0] i; /* gen "out_ready" */
genvar w, b;
assign out1 = f_out[1599:1599-511];
always @ (posedge clk)
if (reset)
i <= 0;
else
i <= {i[21:0], state & f_ack};
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
/* reorder byte ~ ~ */
generate
for(w=0; w<8; w=w+1)
begin : L0
for(b=0; b<8; b=b+1)
begin : L1
assign out[`high_pos(w,b):`low_pos(w,b)] = out1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
/* reorder byte ~ ~ */
generate
for(w=0; w<9; w=w+1)
begin : L2
for(b=0; b<8; b=b+1)
begin : L3
assign padder_out[`high_pos(w,b):`low_pos(w,b)] = padder_out_1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (i[22])
out_ready <= 1;
padder
padder_ (clk, reset, in, in_ready, is_last, byte_num, buffer_full, padder_out_1, padder_out_ready, f_ack);
f_permutation
f_permutation_ (clk, reset, padder_out, padder_out_ready, f_ack, f_out, f_out_ready);
endmodule
`undef low_pos
`undef low_pos2
`undef high_pos
`undef high_pos2
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_register_file.v
//
// *Module Description:
// openMSP430 Register files
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_register_file (
// OUTPUTs
cpuoff, // Turns off the CPU
gie, // General interrupt enable
oscoff, // Turns off LFXT1 clock input
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
reg_dest, // Selected register destination content
reg_src, // Selected register source content
scg1, // System clock generator 1. Turns off the SMCLK
status, // R2 Status {V,N,Z,C}
// INPUTs
alu_stat, // ALU Status {V,N,Z,C}
alu_stat_wr, // ALU Status write {V,N,Z,C}
inst_bw, // Decoded Inst: byte width
inst_dest, // Register destination selection
inst_src, // Register source selection
mclk, // Main system clock
pc, // Program counter
puc, // Main system reset
reg_dest_val, // Selected register destination value
reg_dest_wr, // Write selected register destination
reg_pc_call, // Trigger PC update for a CALL instruction
reg_sp_val, // Stack Pointer next value
reg_sp_wr, // Stack Pointer write
reg_sr_wr, // Status register update for RETI instruction
reg_sr_clr, // Status register clear for interrupts
reg_incr // Increment source register
);
// OUTPUTs
//=========
output cpuoff; // Turns off the CPU
output gie; // General interrupt enable
output oscoff; // Turns off LFXT1 clock input
output [15:0] pc_sw; // Program counter software value
output pc_sw_wr; // Program counter software write
output [15:0] reg_dest; // Selected register destination content
output [15:0] reg_src; // Selected register source content
output scg1; // System clock generator 1. Turns off the SMCLK
output [3:0] status; // R2 Status {V,N,Z,C}
// INPUTs
//=========
input [3:0] alu_stat; // ALU Status {V,N,Z,C}
input [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
input inst_bw; // Decoded Inst: byte width
input [15:0] inst_dest; // Register destination selection
input [15:0] inst_src; // Register source selection
input mclk; // Main system clock
input [15:0] pc; // Program counter
input puc; // Main system reset
input [15:0] reg_dest_val; // Selected register destination value
input reg_dest_wr; // Write selected register destination
input reg_pc_call; // Trigger PC update for a CALL instruction
input [15:0] reg_sp_val; // Stack Pointer next value
input reg_sp_wr; // Stack Pointer write
input reg_sr_wr; // Status register update for RETI instruction
input reg_sr_clr; // Status register clear for interrupts
input reg_incr; // Increment source register
//=============================================================================
// 1) AUTOINCREMENT UNIT
//=============================================================================
wire [15:0] incr_op = inst_bw ? 16'h0001 : 16'h0002;
wire [15:0] reg_incr_val = reg_src+incr_op;
wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val;
//=============================================================================
// 2) SPECIAL REGISTERS (R1/R2/R3)
//=============================================================================
// Source input selection mask (for interrupt support)
//-----------------------------------------------------
wire [15:0] inst_src_in = reg_sr_clr ? 16'h0004 : inst_src;
// R0: Program counter
//---------------------
wire [15:0] r0 = pc;
wire [15:0] pc_sw = reg_dest_val_in;
wire pc_sw_wr = (inst_dest[0] & reg_dest_wr) | reg_pc_call;
// R1: Stack pointer
//-------------------
reg [15:0] r1;
wire r1_wr = inst_dest[1] & reg_dest_wr;
wire r1_inc = inst_src_in[1] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r1 <= 16'h0000;
else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe;
else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe;
else if (r1_inc) r1 <= reg_incr_val & 16'hfffe;
// R2: Status register
//---------------------
reg [15:0] r2;
wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr;
wire r2_c = alu_stat_wr[0] ? alu_stat[0] :
r2_wr ? reg_dest_val_in[0] : r2[0]; // C
wire r2_z = alu_stat_wr[1] ? alu_stat[1] :
r2_wr ? reg_dest_val_in[1] : r2[1]; // Z
wire r2_n = alu_stat_wr[2] ? alu_stat[2] :
r2_wr ? reg_dest_val_in[2] : r2[2]; // N
wire [7:3] r2_nxt = r2_wr ? reg_dest_val_in[7:3] : r2[7:3];
wire r2_v = alu_stat_wr[3] ? alu_stat[3] :
r2_wr ? reg_dest_val_in[8] : r2[8]; // V
always @(posedge mclk or posedge puc)
if (puc) r2 <= 16'h0000;
else if (reg_sr_clr) r2 <= 16'h0000;
else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c};
assign status = {r2[8], r2[2:0]};
assign gie = r2[3];
assign cpuoff = r2[4] | (r2_nxt[4] & r2_wr);
assign oscoff = r2[5];
assign scg1 = r2[7];
// R3: Constant generator
//------------------------
reg [15:0] r3;
wire r3_wr = inst_dest[3] & reg_dest_wr;
wire r3_inc = inst_src_in[3] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r3 <= 16'h0000;
else if (r3_wr) r3 <= reg_dest_val_in;
else if (r3_inc) r3 <= reg_incr_val;
//=============================================================================
// 4) GENERAL PURPOSE REGISTERS (R4...R15)
//=============================================================================
// R4
reg [15:0] r4;
wire r4_wr = inst_dest[4] & reg_dest_wr;
wire r4_inc = inst_src_in[4] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r4 <= 16'h0000;
else if (r4_wr) r4 <= reg_dest_val_in;
else if (r4_inc) r4 <= reg_incr_val;
// R5
reg [15:0] r5;
wire r5_wr = inst_dest[5] & reg_dest_wr;
wire r5_inc = inst_src_in[5] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r5 <= 16'h0000;
else if (r5_wr) r5 <= reg_dest_val_in;
else if (r5_inc) r5 <= reg_incr_val;
// R6
reg [15:0] r6;
wire r6_wr = inst_dest[6] & reg_dest_wr;
wire r6_inc = inst_src_in[6] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r6 <= 16'h0000;
else if (r6_wr) r6 <= reg_dest_val_in;
else if (r6_inc) r6 <= reg_incr_val;
// R7
reg [15:0] r7;
wire r7_wr = inst_dest[7] & reg_dest_wr;
wire r7_inc = inst_src_in[7] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r7 <= 16'h0000;
else if (r7_wr) r7 <= reg_dest_val_in;
else if (r7_inc) r7 <= reg_incr_val;
// R8
reg [15:0] r8;
wire r8_wr = inst_dest[8] & reg_dest_wr;
wire r8_inc = inst_src_in[8] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r8 <= 16'h0000;
else if (r8_wr) r8 <= reg_dest_val_in;
else if (r8_inc) r8 <= reg_incr_val;
// R9
reg [15:0] r9;
wire r9_wr = inst_dest[9] & reg_dest_wr;
wire r9_inc = inst_src_in[9] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r9 <= 16'h0000;
else if (r9_wr) r9 <= reg_dest_val_in;
else if (r9_inc) r9 <= reg_incr_val;
// R10
reg [15:0] r10;
wire r10_wr = inst_dest[10] & reg_dest_wr;
wire r10_inc = inst_src_in[10] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r10 <= 16'h0000;
else if (r10_wr) r10 <= reg_dest_val_in;
else if (r10_inc) r10 <= reg_incr_val;
// R11
reg [15:0] r11;
wire r11_wr = inst_dest[11] & reg_dest_wr;
wire r11_inc = inst_src_in[11] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r11 <= 16'h0000;
else if (r11_wr) r11 <= reg_dest_val_in;
else if (r11_inc) r11 <= reg_incr_val;
// R12
reg [15:0] r12;
wire r12_wr = inst_dest[12] & reg_dest_wr;
wire r12_inc = inst_src_in[12] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r12 <= 16'h0000;
else if (r12_wr) r12 <= reg_dest_val_in;
else if (r12_inc) r12 <= reg_incr_val;
// R13
reg [15:0] r13;
wire r13_wr = inst_dest[13] & reg_dest_wr;
wire r13_inc = inst_src_in[13] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r13 <= 16'h0000;
else if (r13_wr) r13 <= reg_dest_val_in;
else if (r13_inc) r13 <= reg_incr_val;
// R14
reg [15:0] r14;
wire r14_wr = inst_dest[14] & reg_dest_wr;
wire r14_inc = inst_src_in[14] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r14 <= 16'h0000;
else if (r14_wr) r14 <= reg_dest_val_in;
else if (r14_inc) r14 <= reg_incr_val;
// R15
reg [15:0] r15;
wire r15_wr = inst_dest[15] & reg_dest_wr;
wire r15_inc = inst_src_in[15] & reg_incr;
always @(posedge mclk or posedge puc)
if (puc) r15 <= 16'h0000;
else if (r15_wr) r15 <= reg_dest_val_in;
else if (r15_inc) r15 <= reg_incr_val;
//=============================================================================
// 5) READ MUX
//=============================================================================
assign reg_src = (r0 & {16{inst_src_in[0]}}) |
(r1 & {16{inst_src_in[1]}}) |
(r2 & {16{inst_src_in[2]}}) |
(r3 & {16{inst_src_in[3]}}) |
(r4 & {16{inst_src_in[4]}}) |
(r5 & {16{inst_src_in[5]}}) |
(r6 & {16{inst_src_in[6]}}) |
(r7 & {16{inst_src_in[7]}}) |
(r8 & {16{inst_src_in[8]}}) |
(r9 & {16{inst_src_in[9]}}) |
(r10 & {16{inst_src_in[10]}}) |
(r11 & {16{inst_src_in[11]}}) |
(r12 & {16{inst_src_in[12]}}) |
(r13 & {16{inst_src_in[13]}}) |
(r14 & {16{inst_src_in[14]}}) |
(r15 & {16{inst_src_in[15]}});
assign reg_dest = (r0 & {16{inst_dest[0]}}) |
(r1 & {16{inst_dest[1]}}) |
(r2 & {16{inst_dest[2]}}) |
(r3 & {16{inst_dest[3]}}) |
(r4 & {16{inst_dest[4]}}) |
(r5 & {16{inst_dest[5]}}) |
(r6 & {16{inst_dest[6]}}) |
(r7 & {16{inst_dest[7]}}) |
(r8 & {16{inst_dest[8]}}) |
(r9 & {16{inst_dest[9]}}) |
(r10 & {16{inst_dest[10]}}) |
(r11 & {16{inst_dest[11]}}) |
(r12 & {16{inst_dest[12]}}) |
(r13 & {16{inst_dest[13]}}) |
(r14 & {16{inst_dest[14]}}) |
(r15 & {16{inst_dest[15]}});
endmodule // omsp_register_file
`include "openMSP430_undefines.v"
|
Require Import Arith.
Require Import Omega.
Require FunctionalExtensionality.
Require Import List.
Import List.ListNotations.
Require Import mathcomp.ssreflect.ssreflect.
Require Import mathcomp.ssreflect.ssrbool.
Set Bullet Behavior "Strict Subproofs".
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import InfSeqExt.infseq.
Require Import Chord.Chord.
Require Import Chord.HandlerLemmas.
Definition live_node_bool (gst : global_state) (h : addr) : bool :=
if sigma gst h is Some st then
joined st && in_dec addr_eq_dec h (nodes gst) && ~~ in_dec addr_eq_dec h (failed_nodes gst)
else false.
Ltac break_live_node_name var :=
match goal with
| H : live_node _ _ |- _ =>
unfold live_node in H; repeat break_and; break_exists_name var; repeat break_and
end.
Ltac break_live_node_exists_exists :=
match goal with
| H : live_node _ _ |- _ =>
unfold live_node in H; repeat break_and; break_exists_exists; repeat break_and
end.
Ltac break_dead_node :=
match goal with
| H : dead_node _ _ |- _ =>
unfold dead_node in H; repeat break_and; break_exists; repeat break_and
end.
Ltac break_dead_node_name var :=
match goal with
| H : dead_node _ _ |- _ =>
unfold dead_node in H; repeat break_and; break_exists_name var; repeat break_and
end.
Ltac break_dead_node_exists_exists :=
match goal with
| H : dead_node _ _ |- _ =>
unfold dead_node in H; repeat break_and; break_exists_exists; repeat break_and
end.
Ltac break_live_node :=
match goal with
| H : live_node _ _ |- _ =>
unfold live_node in H; repeat break_and; break_exists; repeat break_and
end.
Theorem live_node_characterization :
forall gst h st,
sigma gst h = Some st ->
joined st = true ->
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
live_node gst h.
Proof using.
unfold live_node.
intuition.
match goal with
| x : data |- exists _ : data, _ => exists x
end.
intuition.
Qed.
Definition live_node_dec :
forall gst h,
{live_node gst h} + {~ live_node gst h}.
Proof.
intros.
destruct (In_dec addr_eq_dec h (nodes gst));
destruct (In_dec addr_eq_dec h (failed_nodes gst));
destruct (sigma gst h) as [st|] eqn:?;
try destruct (joined st) eqn:?;
try solve [left; eapply live_node_characterization; eassumption
|right; intro; inv_prop live_node; expand_def; congruence].
Defined.
Definition live_addrs (gst : global_state) : list addr :=
filter (live_node_bool gst) (nodes gst).
Definition live_ptrs (gst : global_state) : list pointer :=
map make_pointer (live_addrs gst).
Definition live_ptrs_with_states (gst : global_state) : list (pointer * data) :=
FilterMap.filterMap (fun p =>
match sigma gst (addr_of p) with
| Some st => Some (p, st)
| None => None
end)
(live_ptrs gst).
Theorem live_node_equiv_live_node_bool :
forall gst h,
live_node gst h <-> live_node_bool gst h = true.
Proof using.
unfold live_node_bool.
intuition.
- repeat break_match; break_live_node; last by congruence.
find_rewrite.
find_injection.
apply/andP; split; first by apply/andP; split => //; case in_dec.
by case in_dec.
- repeat break_match; last by congruence.
move/andP: H => [H H_f]; move/andP: H => [H H_n].
apply: live_node_characterization; eauto.
* by move: H_n; case in_dec.
* by move: H_f; case in_dec.
Qed.
Lemma live_addr_In_live_addrs :
forall gst h,
live_node gst h ->
In h (live_addrs gst).
Proof.
unfold live_addrs.
intros.
apply filter_In; split.
- unfold live_node in *; break_and; auto.
- apply live_node_equiv_live_node_bool; auto.
Qed.
Lemma In_live_addrs_live :
forall gst h,
In h (live_addrs gst) ->
live_node gst h.
Proof.
unfold live_addrs.
intros.
find_apply_lem_hyp filter_In; break_and.
apply live_node_equiv_live_node_bool; auto.
Qed.
Lemma In_live_ptrs_live :
forall gst h,
In h (live_ptrs gst) ->
live_node gst (addr_of h).
Proof.
unfold live_ptrs.
intros.
apply In_live_addrs_live.
now find_apply_lem_hyp in_map_iff; expand_def.
Qed.
Lemma when_apply_handler_result_preserves_live_node :
forall h h0 st st' gst gst' e ms cts nts,
live_node gst h ->
sigma gst h = Some st ->
sigma gst' h = Some st' ->
joined st' = true ->
gst' = apply_handler_result h0 (st', ms, cts, nts) e gst ->
live_node gst' h.
Proof using.
intuition.
eapply live_node_characterization.
- eauto.
- break_live_node.
repeat find_rewrite.
find_inversion; eauto.
- find_apply_lem_hyp apply_handler_result_preserves_nodes.
find_inversion.
break_live_node; auto.
- find_apply_lem_hyp apply_handler_result_preserves_failed_nodes.
find_inversion.
break_live_node; auto.
Qed.
Theorem live_node_preserved_by_recv_step :
forall gst h src st msg gst' e st' ms nts cts,
live_node gst h ->
Some st = sigma gst h ->
recv_handler src h st msg = (st', ms, nts, cts) ->
gst' = apply_handler_result h (st', ms, nts, cts) e gst ->
live_node gst' h.
Proof using.
intuition.
eapply when_apply_handler_result_preserves_live_node; eauto.
- eauto using apply_handler_result_updates_sigma.
- eapply joined_preserved_by_recv_handler.
* eauto.
* break_live_node.
find_rewrite.
find_injection.
auto.
Qed.
Theorem live_node_preserved_by_timeout_step :
forall gst h st st' t ms nts cts e gst',
live_node gst h ->
sigma gst h = Some st ->
timeout_handler h st t = (st', ms, nts, cts) ->
gst' = apply_handler_result h (st', ms, nts, t :: cts) e gst ->
live_node gst' h.
Proof using.
intuition.
eapply when_apply_handler_result_preserves_live_node; eauto.
- eauto using apply_handler_result_updates_sigma.
- break_live_node.
unfold timeout_handler, fst in *; break_let.
repeat find_rewrite.
find_apply_lem_hyp joined_preserved_by_timeout_handler_eff.
repeat find_rewrite.
find_injection.
eauto.
Qed.
Definition best_succ_of (gst : global_state) (h : addr) : option addr :=
match (sigma gst) h with
| Some st => head (filter (live_node_bool gst) (map addr_of (succ_list st)))
| None => None
end.
Lemma live_node_specificity :
forall gst gst',
nodes gst = nodes gst' ->
failed_nodes gst = failed_nodes gst' ->
sigma gst = sigma gst' ->
live_node gst = live_node gst'.
Proof using.
intuition.
unfold live_node.
repeat find_rewrite.
auto.
Qed.
Lemma live_node_joined :
forall gst h,
live_node gst h ->
exists st,
sigma gst h = Some st /\
joined st = true.
Proof using.
intuition.
by break_live_node_exists_exists.
Qed.
Lemma live_node_in_nodes :
forall gst h,
live_node gst h ->
In h (nodes gst).
Proof using.
intuition.
by break_live_node.
Qed.
Hint Resolve live_node_in_nodes.
Lemma live_node_not_in_failed_nodes :
forall gst h,
live_node gst h ->
~ In h (failed_nodes gst).
Proof using.
intuition.
by break_live_node.
Qed.
Hint Resolve live_node_not_in_failed_nodes.
Lemma live_node_equivalence :
forall gst gst' h st st',
live_node gst h ->
nodes gst = nodes gst' ->
failed_nodes gst = failed_nodes gst' ->
sigma gst h = Some st ->
sigma gst' h = Some st' ->
joined st = joined st' ->
live_node gst' h.
Proof using.
intuition.
break_live_node.
eapply live_node_characterization.
* eauto.
* repeat find_rewrite.
find_injection.
eauto.
* repeat find_rewrite; auto.
* repeat find_rewrite; auto.
Qed.
Lemma live_node_means_state_exists :
forall gst h,
live_node gst h ->
exists st, sigma gst h = Some st.
Proof using.
intuition.
find_apply_lem_hyp live_node_joined.
break_exists_exists.
by break_and.
Qed.
Hint Resolve live_node_means_state_exists.
Lemma coarse_live_node_characterization :
forall gst gst' h,
live_node gst h ->
nodes gst = nodes gst' ->
failed_nodes gst = failed_nodes gst' ->
sigma gst = sigma gst' ->
live_node gst' h.
Proof using.
intuition.
find_copy_apply_lem_hyp live_node_means_state_exists.
break_exists.
eapply live_node_equivalence.
* repeat find_rewrite; eauto.
* repeat find_rewrite; eauto.
* repeat find_rewrite; eauto.
* repeat find_rewrite; eauto.
* repeat find_rewrite; eauto.
* repeat find_rewrite; eauto.
Qed.
Lemma adding_nodes_does_not_affect_live_node :
forall gst gst' h n st,
~ In n (nodes gst) ->
sigma gst' = update addr_eq_dec (sigma gst) n (Some st) ->
nodes gst' = n :: nodes gst ->
failed_nodes gst' = failed_nodes gst ->
live_node gst h ->
live_node gst' h.
Proof using.
intuition.
break_live_node_name d.
repeat split.
* repeat find_rewrite.
now apply in_cons.
* by find_rewrite.
* exists d.
split => //.
repeat find_reverse_rewrite.
find_rewrite.
find_rewrite.
apply update_diff.
congruence.
Qed.
(* reverse of the above, with additional hypothesis that h <> n. *)
Lemma adding_nodes_did_not_affect_live_node :
forall gst gst' h n st,
~ In n (nodes gst) ->
sigma gst' = update addr_eq_dec (sigma gst) n st ->
nodes gst' = n :: nodes gst ->
failed_nodes gst' = failed_nodes gst ->
live_node gst' h ->
h <> n ->
live_node gst h.
Proof using.
intuition.
unfold live_node.
break_live_node_name d.
repeat split.
* repeat find_rewrite.
find_apply_lem_hyp in_inv.
break_or_hyp; congruence.
* repeat find_rewrite.
auto.
* exists d.
split => //.
repeat find_reverse_rewrite.
find_rewrite.
find_rewrite.
find_rewrite.
find_rewrite.
symmetry.
apply update_diff; auto.
Qed.
Lemma adding_nodes_does_not_affect_dead_node :
forall gst gst' h n st,
~ In n (nodes gst) ->
sigma gst' = update addr_eq_dec (sigma gst) n st ->
nodes gst' = n :: nodes gst ->
failed_nodes gst' = failed_nodes gst ->
dead_node gst h ->
dead_node gst' h.
Proof using.
intuition.
break_dead_node_name d.
repeat split.
- find_rewrite.
eauto using in_cons.
- find_rewrite; auto.
- exists d.
repeat find_reverse_rewrite.
find_rewrite.
find_rewrite.
eapply update_diff.
congruence.
Qed.
(* use lemma from Update.v instead *)
Lemma update_determined_by_f :
forall A (f : addr -> A) x d d' y,
y <> x ->
update addr_eq_dec f x d y = d' ->
f y = d'.
Proof using.
intuition.
symmetry.
repeat find_reverse_rewrite.
apply update_diff.
now apply not_eq_sym.
Qed.
Lemma adding_nodes_did_not_affect_dead_node :
forall gst gst' h n st,
~ In n (nodes gst) ->
In h (nodes gst) ->
sigma gst' = update addr_eq_dec (sigma gst) n st ->
nodes gst' = n :: nodes gst ->
failed_nodes gst' = failed_nodes gst ->
dead_node gst' h ->
dead_node gst h.
Proof using.
intuition.
break_dead_node_name d.
unfold dead_node.
repeat split.
- find_rewrite.
eauto using in_cons.
- now repeat find_rewrite.
- eexists.
eapply update_determined_by_f.
* instantiate (1 := n).
eauto using In_notIn_implies_neq.
* repeat find_rewrite; eauto.
Qed.
Lemma coarse_dead_node_characterization :
forall gst gst' h,
dead_node gst h ->
sigma gst' = sigma gst ->
nodes gst' = nodes gst ->
failed_nodes gst' = failed_nodes gst ->
dead_node gst' h.
Proof using.
intuition.
break_dead_node_name d.
repeat split; try (find_rewrite; auto).
now exists d.
Qed.
Lemma coarse_best_succ_characterization :
forall gst gst' h s,
best_succ gst h s ->
sigma gst' = sigma gst ->
nodes gst' = nodes gst ->
failed_nodes gst' = failed_nodes gst ->
best_succ gst' h s.
Proof using.
unfold best_succ in *.
intuition.
break_exists_exists.
break_and.
repeat break_and_goal.
- eapply live_node_equivalence; eauto.
now repeat find_rewrite.
- now repeat find_rewrite.
- easy.
- move => o H_in.
find_apply_hyp_hyp.
eapply coarse_dead_node_characterization; eauto.
- eapply coarse_live_node_characterization; eauto.
Qed.
Lemma adding_nodes_does_not_affect_best_succ :
forall gst gst' h s n st,
best_succ gst h s ->
~ In n (nodes gst) ->
sigma gst' = update addr_eq_dec (sigma gst) n (Some st) ->
nodes gst' = n :: nodes gst ->
failed_nodes gst' = failed_nodes gst ->
best_succ gst' h s.
Proof using.
unfold best_succ.
intuition.
break_exists_exists.
break_and.
repeat break_and_goal;
eauto using adding_nodes_does_not_affect_live_node.
- repeat break_live_node.
repeat find_rewrite.
match goal with
| H: sigma gst h = Some _ |- _ = Some _ => rewrite <- H
end.
eapply update_diff.
congruence.
- intuition.
find_copy_apply_hyp_hyp.
break_dead_node.
eauto using adding_nodes_does_not_affect_dead_node.
Qed.
Lemma global_state_eq_ext :
forall gst gst',
nodes gst = nodes gst' ->
failed_nodes gst = failed_nodes gst' ->
timeouts gst = timeouts gst' ->
sigma gst = sigma gst' ->
msgs gst = msgs gst' ->
trace gst = trace gst' ->
gst = gst'.
Proof using.
intros.
destruct gst, gst'.
simpl in *.
subst_max.
tauto.
Qed.
Definition channel (gst : global_state) (src dst : addr) : list payload :=
filterMap
(fun m =>
if (addr_eq_dec (fst m) src) && (addr_eq_dec (fst (snd m)) dst)
then Some (snd (snd m))
else None)
(msgs gst).
Lemma in_msgs_in_channel :
forall gst src dst p,
In (src, (dst, p)) (msgs gst) ->
In p (channel gst src dst).
Proof.
unfold channel.
intros.
eapply filterMap_In; eauto.
by case addr_eq_dec, addr_eq_dec.
Qed.
Hint Resolve in_msgs_in_channel.
Lemma in_channel_in_msgs :
forall gst src dst p,
In p (channel gst src dst) ->
In (src, (dst, p)) (msgs gst).
Proof.
unfold channel.
intros.
find_eapply_lem_hyp In_filterMap; eauto.
break_exists.
break_and.
assert (x = (src, (dst, p))).
{ break_if; try discriminate.
find_apply_lem_hyp Bool.andb_true_iff; break_and.
repeat find_apply_lem_hyp addr_eqb_true.
find_injection.
move: H1 H2.
case addr_eq_dec, addr_eq_dec => H_a H_a' //=.
by destruct x, p; subst. }
now find_reverse_rewrite.
Qed.
Hint Resolve in_channel_in_msgs.
Lemma channel_contents :
forall gst src dst p,
In (src, (dst, p)) (msgs gst) <-> In p (channel gst src dst).
Proof using.
intuition.
Qed.
Lemma sigma_apply_handler_result_same :
forall h res es gst,
sigma (apply_handler_result h res es gst) h =
Some (fst (fst (fst res))).
Proof.
intros. unfold apply_handler_result.
repeat break_match. subst. simpl.
now rewrite_update.
Qed.
Lemma sigma_apply_handler_result_diff :
forall h h' res es gst,
h <> h' ->
sigma (apply_handler_result h res es gst) h' =
sigma gst h'.
Proof.
intros. unfold apply_handler_result.
repeat break_match. subst. simpl.
now rewrite_update.
Qed.
Lemma sigma_initial_st_start_handler :
forall gst h st,
initial_st gst ->
sigma gst h = Some st ->
st = fst (fst (start_handler h (nodes gst))).
Proof.
intros.
inv_prop initial_st.
break_and.
destruct (start_handler _ _) as [[d ?] ?] eqn:?.
simpl.
destruct (In_dec addr_eq_dec h (nodes gst)).
- apply_prop_hyp sigma start_handler;
intuition congruence.
- find_higher_order_rewrite; congruence.
Qed.
Lemma timeouts_apply_handler_result_diff :
forall h h' res es gst,
h <> h' ->
timeouts (apply_handler_result h res es gst) h' =
timeouts gst h'.
Proof.
intros. unfold apply_handler_result.
repeat break_match. subst. simpl.
now rewrite_update.
Qed.
Definition active_nodes (gst : global_state) :=
RemoveAll.remove_all addr_eq_dec (failed_nodes gst) (nodes gst).
Lemma labeled_step_dynamic_preserves_active_nodes :
forall gst l gst',
labeled_step_dynamic gst l gst' ->
active_nodes gst = active_nodes gst'.
Proof.
intros; unfold active_nodes.
erewrite labeled_step_dynamic_preserves_failed_nodes; eauto.
erewrite labeled_step_dynamic_preserves_nodes; eauto.
Qed.
Lemma active_nodes_always_identical :
forall l ex,
lb_execution ex ->
active_nodes (occ_gst (hd ex)) = l ->
always (fun ex' => l = active_nodes (occ_gst (hd ex'))) ex.
Proof.
cofix c. intros.
constructor; destruct ex.
- easy.
- apply c; eauto using lb_execution_invar.
inv_prop lb_execution.
find_apply_lem_hyp labeled_step_dynamic_preserves_active_nodes.
cbn; congruence.
Qed.
Definition has_succs (gst : global_state) (h : addr) (succs : list pointer) :=
exists st,
sigma gst h = Some st /\
succ_list st = succs.
Lemma has_succs_intro :
forall gst h succs st,
sigma gst h = Some st ->
succ_list st = succs ->
has_succs gst h succs.
Proof.
eexists; eauto.
Qed.
Lemma initial_nodes_large :
forall gst,
initial_st gst ->
3 <= length (nodes gst).
Proof.
unfold initial_st.
intros.
break_and.
assert (2 <= Chord.SUCC_LIST_LEN)
by apply Chord.succ_list_len_lower_bound.
omega.
Qed.
Lemma Tick_in_initial_st :
forall gst h,
initial_st gst ->
In h (nodes gst) ->
timeouts gst h = [Tick].
Proof.
intros.
find_copy_eapply_lem_hyp initial_nodes_large.
unfold initial_st in *.
break_and.
destruct (start_handler h (nodes gst)) as [[? ?] nts] eqn:?.
assert ([Tick] = nts).
{
pose proof (sort_by_between_permutes h (map make_pointer (nodes gst)) _ eq_refl).
find_copy_apply_lem_hyp Permutation.Permutation_length.
find_rewrite_lem map_length.
destruct (sort_by_between h (map make_pointer (nodes gst))) as [| ? [|? ?]] eqn:? in *;
change ChordIDParams.name with addr in *;
simpl in *; try omega.
unfold start_handler in *.
change ChordIDParams.name with addr in *;
repeat find_rewrite.
now find_inversion.
}
find_rewrite.
eapply_prop_hyp start_handler start_handler; auto.
tauto.
Qed.
Lemma in_nodes_sigma_some :
forall gst h,
initial_st gst ->
In h (nodes gst) ->
exists st,
sigma gst h = Some st.
Proof.
intros. unfold initial_st in *. intuition.
match goal with
| H : context [start_handler] |- _ =>
remember H as Hsh; clear HeqHsh; clear H
end.
specialize (Hsh h). concludes.
destruct (start_handler h (nodes gst)) as [[st ms] nts].
specialize (Hsh st ms nts). intuition.
eauto.
Qed.
Lemma exists_node_in_initial_st :
forall gst,
initial_st gst ->
exists h,
In h (nodes gst) /\ ~ In h (failed_nodes gst).
Proof.
intros. unfold initial_st in *. intuition.
destruct (nodes gst); simpl in *; [omega|].
repeat find_rewrite.
eexists; intuition; eauto.
Qed.
Lemma start_handler_init_state_preset :
forall h knowns,
length knowns > 1 ->
start_handler h knowns =
(init_state_preset h
(find_pred h (sort_by_between h (map make_pointer knowns)))
(chop_succs (List.tl (sort_by_between h (map make_pointer knowns)))),
nil,
Tick :: nil).
Proof.
intros.
unfold start_handler.
repeat break_match;
match goal with H : _ = _ |- _ => symmetry in H end;
find_copy_apply_lem_hyp sort_by_between_permutes;
[| | reflexivity];
find_apply_lem_hyp Permutation.Permutation_length;
rewrite map_length in H0; simpl in *; repeat find_reverse_rewrite;
exfalso; eapply gt_irrefl; eauto.
Qed.
Lemma live_node_in_initial_st :
forall gst,
initial_st gst ->
exists h,
live_node gst h.
Proof.
intros.
find_copy_apply_lem_hyp exists_node_in_initial_st.
break_exists_name h; exists h. intuition.
find_copy_eapply_lem_hyp in_nodes_sigma_some; eauto.
break_exists_name st. unfold live_node. intuition.
exists st. intuition.
find_apply_lem_hyp sigma_initial_st_start_handler; auto. subst.
pose proof succ_list_len_lower_bound.
rewrite start_handler_init_state_preset;
[|unfold initial_st in *; intuition].
reflexivity.
Qed.
Lemma sorted_knowns_same_length :
forall h ks,
length (sort_by_between h (map make_pointer ks)) = length ks.
Proof.
intros.
pose proof (sort_by_between_permutes h (map make_pointer ks) ltac:(eauto) ltac:(eauto)).
find_apply_lem_hyp Permutation.Permutation_length.
find_reverse_rewrite.
apply map_length.
Qed.
Hint Rewrite sorted_knowns_same_length.
Lemma initial_start_handler_st_joined :
forall h ks st ms nts,
start_handler h ks = (st, ms, nts) ->
length ks > 1 ->
joined st = true.
Proof.
intros.
unfold start_handler, empty_start_res, init_state_join, init_state_preset in *.
repeat break_match; try find_injection.
- rewrite <- (sorted_knowns_same_length h) in *.
find_rewrite.
simpl in *; omega.
- rewrite <- (sorted_knowns_same_length h) in *.
find_rewrite.
simpl in *; omega.
- reflexivity.
Qed.
Lemma initial_nodes_live :
forall gst h,
initial_st gst ->
In h (nodes gst) ->
live_node gst h.
Proof.
intros.
destruct (start_handler h (nodes gst)) as [[?st ?ms] ?nts] eqn:?.
inv_prop initial_st; break_and.
eapply live_node_characterization.
- apply_prop_hyp sigma start_handler; break_and; eauto.
- find_copy_apply_lem_hyp initial_nodes_large.
eapply initial_start_handler_st_joined; eauto; omega.
- auto.
- repeat find_rewrite; in_crush.
Qed.
Hint Resolve initial_nodes_live.
Theorem initial_succ_list :
forall h gst st,
initial_st gst ->
In h (nodes gst) ->
sigma gst h = Some st ->
succ_list st = chop_succs (List.tl (sort_by_between h (map make_pointer (nodes gst)))).
Proof.
intros.
inv_prop initial_st; break_and.
find_copy_apply_lem_hyp initial_nodes_large.
destruct (start_handler h (nodes gst)) as [[?st ?ms] ?nts] eqn:?.
copy_eapply_prop_hyp start_handler start_handler; auto; break_and.
rewrite start_handler_init_state_preset in Heqp; eauto with arith.
repeat find_rewrite; repeat find_injection.
simpl in *; eauto.
Qed.
Hint Rewrite initial_succ_list.
Lemma NoDup_map_make_pointer :
forall l, NoDup l ->
NoDup (map make_pointer l).
Proof.
elim => //=.
move => a l IH H_nd.
inversion H_nd; subst.
find_apply_lem_hyp IH.
apply NoDup_cons => //.
move {H2 H_nd IH}.
elim: l H1 => //=.
move => a' l IH H_in H_in'.
have H_neq: a' <> a by auto.
have H_nin: ~ In a l by auto.
break_or_hyp.
- unfold make_pointer in H.
by find_injection.
- by apply IH.
Qed.
Lemma initial_successor_lists_full :
forall h gst,
initial_st gst ->
length (chop_succs (List.tl (sort_by_between h (map make_pointer (nodes gst))))) = SUCC_LIST_LEN.
Proof.
intros.
pose proof (sorted_knowns_same_length h (nodes gst)).
inv_prop initial_st; break_and.
rewrite -H0 in H1.
move: H1 H0.
set mm := map _ _.
move => H_le H_eq.
have H_pm := sort_by_between_permutes h mm (sort_by_between h mm) (eq_refl _).
have H_nd := NoDup_map_make_pointer _ H2.
rewrite -/mm in H_nd.
apply NoDup_Permutation_NoDup in H_pm => //.
move: H_pm H_le.
destruct (sort_by_between _ _) eqn:?.
- subst; move => H_nd' H_le.
simpl in *; omega.
- intros.
simpl in *.
rewrite /chop_succs.
rewrite firstn_length /=.
rewrite min_l; omega.
Qed.
Lemma best_succ_preserved :
forall gst gst' h h0 s st st',
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some st ->
sigma gst' = update (addr_eq_dec) (sigma gst) h (Some st') ->
(joined st = true -> joined st' = true) ->
succ_list st = succ_list st' \/ h <> h0 ->
nodes gst' = nodes gst ->
failed_nodes gst = failed_nodes gst' ->
best_succ gst h0 s ->
best_succ gst' h0 s.
Proof.
unfold best_succ.
intros.
destruct (addr_eq_dec h h0).
{
symmetry in e; subst.
expand_def.
repeat find_rewrite; rewrite_update.
find_inversion.
do 3 eexists.
repeat break_and_goal.
- repeat break_live_node.
eapply live_node_characterization; try congruence.
+ repeat find_rewrite; rewrite_update; eauto.
+ find_eapply_prop joined; congruence.
- reflexivity.
- find_rewrite; eauto.
- intros.
assert (dead_node gst o) by auto.
inv_prop dead_node; expand_def; unfold dead_node; repeat find_rewrite.
rewrite_update; eauto.
- inv_prop live_node; expand_def.
destruct (addr_eq_dec h s); subst.
+ eapply live_node_characterization;
repeat find_rewrite; rewrite_update; eauto.
find_injection; auto.
+ eapply live_node_equivalence; eauto.
repeat find_rewrite; rewrite_update; auto.
}
break_exists_exists.
repeat break_and_goal; break_and;
repeat find_rewrite; rewrite_update.
- repeat break_live_node.
eapply live_node_characterization; try congruence.
+ repeat find_rewrite; rewrite_update; eauto.
+ congruence.
- auto.
- auto.
- intros.
assert (dead_node gst o) by auto.
inv_prop dead_node; expand_def; unfold dead_node; repeat find_rewrite;
rewrite_update; eauto.
- repeat break_live_node.
destruct (addr_eq_dec s h);
eapply live_node_characterization; try congruence;
try solve [repeat find_rewrite; rewrite_update; eauto
|congruence
|find_eapply_prop joined; congruence].
Qed.
Hint Resolve best_succ_preserved.
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:04:01 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_processing_system7_0_0 -prefix
// system_processing_system7_0_0_ system_processing_system7_0_0_sim_netlist.v
// Design : system_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *) (* C_GP1_EN_MODIFIABLE_TXN = "0" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module system_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_processing_system7_0_0
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *)
(* C_GP1_EN_MODIFIABLE_TXN = "0" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
system_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4_PP_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_PP_BLACKBOX_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_memory_async (reset, enable, start_addr, end_addr, ren, raddr, rdata, wen, waddr,
wdata, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter data_width = 1;
parameter addr_width = 1;
parameter mem_size = 2;
parameter addr_check = 1;
parameter init_check = 1;
parameter one_read_check = 0;
parameter one_write_check = 0;
parameter value_check = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter wen_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter ren_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input reset, enable;
input ren, wen;
input [addr_width-1 : 0] start_addr;
input [addr_width-1 : 0] end_addr;
input [addr_width-1 : 0] raddr;
input [data_width-1 : 0] rdata;
input [addr_width-1 : 0] waddr;
input [data_width-1 : 0] wdata;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_MEMORY_ASYNC";
`ifdef OVL_EVERYTHING_OFF
// No logic if ASSERT & COVER both OFF
`else
// latch based gated clock
wire ren_gclk, wen_gclk;
reg ren_clken, wen_clken;
always @ (ren or enable) begin
if (ren == 1'b0)
ren_clken <= enable;
end
always @ (wen or enable) begin
if (wen == 1'b0)
wen_clken <= enable;
end
assign ren_gclk = (gating_type == `OVL_GATE_CLOCK) ? ren & ren_clken : ren;
assign wen_gclk = (gating_type == `OVL_GATE_CLOCK) ? wen & wen_clken : wen;
// clk (programmable edge)
wire ren_clk, wen_clk;
assign ren_clk = (ren_edge == `OVL_POSEDGE) ? ren_gclk : ~ren_gclk;
assign wen_clk = (wen_edge == `OVL_POSEDGE) ? wen_gclk : ~wen_gclk;
// reset_n (programmable polarity & optional gating)
wire reset_n;
assign reset_n = (gating_type == `OVL_GATE_RESET) ? ((reset_polarity == `OVL_ACTIVE_LOW) ? reset & enable : ~reset & enable)
: ((reset_polarity == `OVL_ACTIVE_LOW) ? reset : ~reset);
`endif
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_memory_async_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_memory_async
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_V |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: MAIN_synthesis.v
// /___/ /\ Timestamp: Wed Apr 06 10:35:47 2016
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim MAIN.ngc MAIN_synthesis.v
// Device : xc6slx16-3-csg324
// Input file : MAIN.ngc
// Output file : \\mac\github\TEOCOA\EXPR3_DIGITAL\netgen\synthesis\MAIN_synthesis.v
// # of Modules : 1
// Design Name : MAIN
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module MAIN (
F_LED_SW, clock, RST, ALU_OP, AB_SW, LED, dig, AN
);
input F_LED_SW;
input clock;
input RST;
input [2 : 0] ALU_OP;
input [2 : 0] AB_SW;
output [1 : 0] LED;
output [7 : 0] dig;
output [3 : 0] AN;
wire ALU_OP_2_IBUF_0;
wire ALU_OP_1_IBUF_1;
wire ALU_OP_0_IBUF_2;
wire AB_SW_2_IBUF_3;
wire AB_SW_1_IBUF_4;
wire AB_SW_0_IBUF_5;
wire F_LED_SW_IBUF_6;
wire clock_BUFGP_7;
wire RST_IBUF_8;
wire LED_0_OBUF_41;
wire LED_1_OBUF_42;
wire dig_7_OBUF_43;
wire dig_6_OBUF_44;
wire dig_5_OBUF_45;
wire dig_4_OBUF_46;
wire dig_3_OBUF_47;
wire dig_2_OBUF_48;
wire dig_1_OBUF_49;
wire AN_3_OBUF_50;
wire AN_2_OBUF_51;
wire AN_1_OBUF_52;
wire AN_0_OBUF_53;
wire Mram__n0040;
wire Mram__n004010;
wire Mram__n004011;
wire Mram__n004031;
wire Mram__n004033;
wire RST_inv;
wire \Result<0>1 ;
wire \CL/Mcount_count_eqn_0 ;
wire \Result<1>1 ;
wire \CL/Mcount_count_eqn_1 ;
wire \CL/Mcount_count_eqn_2 ;
wire \CL/Mcount_count_eqn_3 ;
wire \CL/Mcount_count_eqn_4 ;
wire \CL/Mcount_count_eqn_5 ;
wire \CL/Mcount_count_eqn_6 ;
wire \CL/Mcount_count_eqn_7 ;
wire \CL/Mcount_count_eqn_8 ;
wire \CL/Mcount_count_eqn_9 ;
wire \CL/Mcount_count_eqn_10 ;
wire \CL/Mcount_count_eqn_11 ;
wire \CL/Mcount_count_eqn_12 ;
wire \CL/Mcount_count_eqn_13 ;
wire \CL/Mcount_count_eqn_14 ;
wire \CL/Mcount_count_eqn_15 ;
wire \CL/Mcount_count_eqn_16 ;
wire \CL/Mcount_count_eqn_17 ;
wire Mmux_dig811_134;
wire Mmux_dig711;
wire Mmux_dig812;
wire Mmux_dig821;
wire Mmux_dig831;
wire Mmux_dig8111;
wire Mmux_dig8211_140;
wire Mmux_dig611_141;
wire Mmux_dig621;
wire Mmux_dig8112_143;
wire Mmux_dig8212;
wire Mmux_dig612;
wire Mmux_dig622;
wire Mmux_dig511_147;
wire Mmux_dig521;
wire Mmux_dig512;
wire Mmux_dig522;
wire Mmux_dig8115_151;
wire Mmux_dig8215_152;
wire Mmux_dig8116;
wire Mmux_dig8216;
wire Mmux_dig721;
wire Mmux_dig81171;
wire Mmux_dig82171;
wire Mmux_dig7121;
wire Mmux_dig311;
wire \ALU/Mmux_F27211 ;
wire \ALU/Sh561 ;
wire \ALU/Mmux_F102 ;
wire \ALU/Mmux_F110 ;
wire \ALU/Sh46 ;
wire \ALU/Sh45 ;
wire \ALU/Sh44 ;
wire \ALU/Sh42 ;
wire \ALU/Sh40 ;
wire \ALU/Sh12 ;
wire \CL/count[17]_PWR_5_o_equal_1_o<17> ;
wire \CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ;
wire \CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ;
wire Mmux_dig73;
wire Mmux_dig76;
wire Mmux_dig710;
wire Mmux_dig715;
wire Mmux_dig717;
wire Mmux_dig32;
wire Mmux_dig35;
wire Mmux_dig36_373;
wire Mmux_dig37_374;
wire Mmux_dig38_375;
wire Mmux_dig39_376;
wire Mmux_dig310_377;
wire Mmux_dig312_378;
wire Mmux_dig2;
wire Mmux_dig21_380;
wire Mmux_dig22_381;
wire Mmux_dig23_382;
wire Mmux_dig24_383;
wire Mmux_dig25_384;
wire Mmux_dig26_385;
wire Mmux_dig27_386;
wire Mmux_dig29;
wire Mmux_dig211;
wire Mmux_dig43;
wire Mmux_dig44_390;
wire Mmux_dig47;
wire Mmux_dig48_392;
wire Mmux_dig411;
wire Mmux_dig414;
wire Mmux_dig51;
wire Mmux_dig53;
wire Mmux_dig54_397;
wire Mmux_dig55_398;
wire Mmux_dig56_399;
wire Mmux_dig57_400;
wire Mmux_dig58_401;
wire Mmux_dig59_402;
wire Mmux_dig61;
wire Mmux_dig63;
wire Mmux_dig64_405;
wire Mmux_dig65_406;
wire Mmux_dig66_407;
wire Mmux_dig67_408;
wire Mmux_dig68_409;
wire Mmux_dig69_410;
wire Mmux_dig8114;
wire Mmux_dig8117;
wire Mmux_dig8213;
wire Mmux_dig8218;
wire Mmux_dig8;
wire Mmux_dig81_416;
wire Mmux_dig82_417;
wire Mmux_dig83_418;
wire Mmux_dig84_419;
wire Mmux_dig85_420;
wire Mmux_dig86_421;
wire Mmux_dig87_422;
wire Mmux_dig88_423;
wire Mmux_dig89_424;
wire Mmux_dig7213_425;
wire \ALU/Mmux_F261_426 ;
wire \ALU/Mmux_F112 ;
wire \ALU/Mmux_F231 ;
wire \ALU/Mmux_F101 ;
wire \ALU/Mmux_F121_430 ;
wire \ALU/Mmux_F122_431 ;
wire \ALU/Mmux_F133 ;
wire \ALU/Mmux_F253 ;
wire \ALU/Mmux_F7 ;
wire \ALU/Mmux_F6 ;
wire \ALU/Mmux_F5 ;
wire \ALU/Mmux_F4 ;
wire \ALU/Mmux_F32_438 ;
wire \ALU/Mmux_F31_439 ;
wire \ALU/Mmux_F3 ;
wire \ALU/Mmux_F2 ;
wire \ALU/Mmux_F301 ;
wire \ALU/Mmux_F291 ;
wire \ALU/Mmux_F281 ;
wire \ALU/Mmux_F271 ;
wire \ALU/Mmux_F191 ;
wire \ALU/Mmux_F172 ;
wire \ALU/ZF<31>1_449 ;
wire \ALU/ZF<31>2_450 ;
wire \ALU/ZF<31>3_451 ;
wire \ALU/ZF<31>4_452 ;
wire \ALU/ZF<31>5_453 ;
wire \ALU/ZF<31>6_454 ;
wire \CL/Mcount_count_cy<1>_rt_478 ;
wire \CL/Mcount_count_cy<2>_rt_479 ;
wire \CL/Mcount_count_cy<3>_rt_480 ;
wire \CL/Mcount_count_cy<4>_rt_481 ;
wire \CL/Mcount_count_cy<5>_rt_482 ;
wire \CL/Mcount_count_cy<6>_rt_483 ;
wire \CL/Mcount_count_cy<7>_rt_484 ;
wire \CL/Mcount_count_cy<8>_rt_485 ;
wire \CL/Mcount_count_cy<9>_rt_486 ;
wire \CL/Mcount_count_cy<10>_rt_487 ;
wire \CL/Mcount_count_cy<11>_rt_488 ;
wire \CL/Mcount_count_cy<12>_rt_489 ;
wire \CL/Mcount_count_cy<13>_rt_490 ;
wire \CL/Mcount_count_cy<14>_rt_491 ;
wire \CL/Mcount_count_cy<15>_rt_492 ;
wire \CL/Mcount_count_cy<16>_rt_493 ;
wire \CL/Mcount_count_xor<17>_rt_494 ;
wire \CL/Bit_Sel_0_dpot_495 ;
wire \CL/Bit_Sel_1_dpot_496 ;
wire N0;
wire N2;
wire N8;
wire N10;
wire N12;
wire N14;
wire N16;
wire N18;
wire N20;
wire N22;
wire \CL/count[17]_PWR_5_o_equal_1_o<17>21 ;
wire N24;
wire N25;
wire N26;
wire N27;
wire N28;
wire N29;
wire N30;
wire N31;
wire N32;
wire N33;
wire N34;
wire N35;
wire N36;
wire N37;
wire N38;
wire N39;
wire N40;
wire N41;
wire N42;
wire N43;
wire [31 : 0] F;
wire [1 : 0] \CL/Bit_Sel ;
wire [17 : 0] \CL/count ;
wire [17 : 2] Result;
wire [0 : 0] \CL/Mcount_count_lut ;
wire [16 : 0] \CL/Mcount_count_cy ;
wire [31 : 0] \ALU/Madd_n0030_cy ;
wire [31 : 0] \ALU/Madd_n0030_lut ;
wire [31 : 0] \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy ;
wire [31 : 0] \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut ;
wire [31 : 0] \ALU/n0030 ;
wire [32 : 0] \ALU/GND_2_o_GND_2_o_sub_7_OUT ;
wire [31 : 31] \ALU/ZF ;
VCC XST_VCC (
.P(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31])
);
GND XST_GND (
.G(\ALU/Madd_n0030_lut [31])
);
FDC \CL/count_0 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_0 ),
.Q(\CL/count [0])
);
FDC \CL/count_1 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_1 ),
.Q(\CL/count [1])
);
FDC \CL/count_2 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_2 ),
.Q(\CL/count [2])
);
FDC \CL/count_3 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_3 ),
.Q(\CL/count [3])
);
FDC \CL/count_4 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_4 ),
.Q(\CL/count [4])
);
FDC \CL/count_5 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_5 ),
.Q(\CL/count [5])
);
FDC \CL/count_6 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_6 ),
.Q(\CL/count [6])
);
FDC \CL/count_7 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_7 ),
.Q(\CL/count [7])
);
FDC \CL/count_8 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_8 ),
.Q(\CL/count [8])
);
FDC \CL/count_9 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_9 ),
.Q(\CL/count [9])
);
FDC \CL/count_10 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_10 ),
.Q(\CL/count [10])
);
FDC \CL/count_11 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_11 ),
.Q(\CL/count [11])
);
FDC \CL/count_12 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_12 ),
.Q(\CL/count [12])
);
FDC \CL/count_13 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_13 ),
.Q(\CL/count [13])
);
FDC \CL/count_14 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_14 ),
.Q(\CL/count [14])
);
FDC \CL/count_15 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_15 ),
.Q(\CL/count [15])
);
FDC \CL/count_16 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_16 ),
.Q(\CL/count [16])
);
FDC \CL/count_17 (
.C(clock_BUFGP_7),
.CLR(RST_inv),
.D(\CL/Mcount_count_eqn_17 ),
.Q(\CL/count [17])
);
FDCE \CL/Bit_Sel_0 (
.C(clock_BUFGP_7),
.CE(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.CLR(RST_inv),
.D(\CL/Bit_Sel_0_dpot_495 ),
.Q(\CL/Bit_Sel [0])
);
FDCE \CL/Bit_Sel_1 (
.C(clock_BUFGP_7),
.CE(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.CLR(RST_inv),
.D(\CL/Bit_Sel_1_dpot_496 ),
.Q(\CL/Bit_Sel [1])
);
MUXCY \CL/Mcount_count_cy<0> (
.CI(\ALU/Madd_n0030_lut [31]),
.DI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31]),
.S(\CL/Mcount_count_lut [0]),
.O(\CL/Mcount_count_cy [0])
);
XORCY \CL/Mcount_count_xor<0> (
.CI(\ALU/Madd_n0030_lut [31]),
.LI(\CL/Mcount_count_lut [0]),
.O(\Result<0>1 )
);
MUXCY \CL/Mcount_count_cy<1> (
.CI(\CL/Mcount_count_cy [0]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<1>_rt_478 ),
.O(\CL/Mcount_count_cy [1])
);
XORCY \CL/Mcount_count_xor<1> (
.CI(\CL/Mcount_count_cy [0]),
.LI(\CL/Mcount_count_cy<1>_rt_478 ),
.O(\Result<1>1 )
);
MUXCY \CL/Mcount_count_cy<2> (
.CI(\CL/Mcount_count_cy [1]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<2>_rt_479 ),
.O(\CL/Mcount_count_cy [2])
);
XORCY \CL/Mcount_count_xor<2> (
.CI(\CL/Mcount_count_cy [1]),
.LI(\CL/Mcount_count_cy<2>_rt_479 ),
.O(Result[2])
);
MUXCY \CL/Mcount_count_cy<3> (
.CI(\CL/Mcount_count_cy [2]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<3>_rt_480 ),
.O(\CL/Mcount_count_cy [3])
);
XORCY \CL/Mcount_count_xor<3> (
.CI(\CL/Mcount_count_cy [2]),
.LI(\CL/Mcount_count_cy<3>_rt_480 ),
.O(Result[3])
);
MUXCY \CL/Mcount_count_cy<4> (
.CI(\CL/Mcount_count_cy [3]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<4>_rt_481 ),
.O(\CL/Mcount_count_cy [4])
);
XORCY \CL/Mcount_count_xor<4> (
.CI(\CL/Mcount_count_cy [3]),
.LI(\CL/Mcount_count_cy<4>_rt_481 ),
.O(Result[4])
);
MUXCY \CL/Mcount_count_cy<5> (
.CI(\CL/Mcount_count_cy [4]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<5>_rt_482 ),
.O(\CL/Mcount_count_cy [5])
);
XORCY \CL/Mcount_count_xor<5> (
.CI(\CL/Mcount_count_cy [4]),
.LI(\CL/Mcount_count_cy<5>_rt_482 ),
.O(Result[5])
);
MUXCY \CL/Mcount_count_cy<6> (
.CI(\CL/Mcount_count_cy [5]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<6>_rt_483 ),
.O(\CL/Mcount_count_cy [6])
);
XORCY \CL/Mcount_count_xor<6> (
.CI(\CL/Mcount_count_cy [5]),
.LI(\CL/Mcount_count_cy<6>_rt_483 ),
.O(Result[6])
);
MUXCY \CL/Mcount_count_cy<7> (
.CI(\CL/Mcount_count_cy [6]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<7>_rt_484 ),
.O(\CL/Mcount_count_cy [7])
);
XORCY \CL/Mcount_count_xor<7> (
.CI(\CL/Mcount_count_cy [6]),
.LI(\CL/Mcount_count_cy<7>_rt_484 ),
.O(Result[7])
);
MUXCY \CL/Mcount_count_cy<8> (
.CI(\CL/Mcount_count_cy [7]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<8>_rt_485 ),
.O(\CL/Mcount_count_cy [8])
);
XORCY \CL/Mcount_count_xor<8> (
.CI(\CL/Mcount_count_cy [7]),
.LI(\CL/Mcount_count_cy<8>_rt_485 ),
.O(Result[8])
);
MUXCY \CL/Mcount_count_cy<9> (
.CI(\CL/Mcount_count_cy [8]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<9>_rt_486 ),
.O(\CL/Mcount_count_cy [9])
);
XORCY \CL/Mcount_count_xor<9> (
.CI(\CL/Mcount_count_cy [8]),
.LI(\CL/Mcount_count_cy<9>_rt_486 ),
.O(Result[9])
);
MUXCY \CL/Mcount_count_cy<10> (
.CI(\CL/Mcount_count_cy [9]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<10>_rt_487 ),
.O(\CL/Mcount_count_cy [10])
);
XORCY \CL/Mcount_count_xor<10> (
.CI(\CL/Mcount_count_cy [9]),
.LI(\CL/Mcount_count_cy<10>_rt_487 ),
.O(Result[10])
);
MUXCY \CL/Mcount_count_cy<11> (
.CI(\CL/Mcount_count_cy [10]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<11>_rt_488 ),
.O(\CL/Mcount_count_cy [11])
);
XORCY \CL/Mcount_count_xor<11> (
.CI(\CL/Mcount_count_cy [10]),
.LI(\CL/Mcount_count_cy<11>_rt_488 ),
.O(Result[11])
);
MUXCY \CL/Mcount_count_cy<12> (
.CI(\CL/Mcount_count_cy [11]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<12>_rt_489 ),
.O(\CL/Mcount_count_cy [12])
);
XORCY \CL/Mcount_count_xor<12> (
.CI(\CL/Mcount_count_cy [11]),
.LI(\CL/Mcount_count_cy<12>_rt_489 ),
.O(Result[12])
);
MUXCY \CL/Mcount_count_cy<13> (
.CI(\CL/Mcount_count_cy [12]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<13>_rt_490 ),
.O(\CL/Mcount_count_cy [13])
);
XORCY \CL/Mcount_count_xor<13> (
.CI(\CL/Mcount_count_cy [12]),
.LI(\CL/Mcount_count_cy<13>_rt_490 ),
.O(Result[13])
);
MUXCY \CL/Mcount_count_cy<14> (
.CI(\CL/Mcount_count_cy [13]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<14>_rt_491 ),
.O(\CL/Mcount_count_cy [14])
);
XORCY \CL/Mcount_count_xor<14> (
.CI(\CL/Mcount_count_cy [13]),
.LI(\CL/Mcount_count_cy<14>_rt_491 ),
.O(Result[14])
);
MUXCY \CL/Mcount_count_cy<15> (
.CI(\CL/Mcount_count_cy [14]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<15>_rt_492 ),
.O(\CL/Mcount_count_cy [15])
);
XORCY \CL/Mcount_count_xor<15> (
.CI(\CL/Mcount_count_cy [14]),
.LI(\CL/Mcount_count_cy<15>_rt_492 ),
.O(Result[15])
);
MUXCY \CL/Mcount_count_cy<16> (
.CI(\CL/Mcount_count_cy [15]),
.DI(\ALU/Madd_n0030_lut [31]),
.S(\CL/Mcount_count_cy<16>_rt_493 ),
.O(\CL/Mcount_count_cy [16])
);
XORCY \CL/Mcount_count_xor<16> (
.CI(\CL/Mcount_count_cy [15]),
.LI(\CL/Mcount_count_cy<16>_rt_493 ),
.O(Result[16])
);
XORCY \CL/Mcount_count_xor<17> (
.CI(\CL/Mcount_count_cy [16]),
.LI(\CL/Mcount_count_xor<17>_rt_494 ),
.O(Result[17])
);
XORCY \ALU/Madd_n0030_xor<31> (
.CI(\ALU/Madd_n0030_cy [30]),
.LI(\ALU/Madd_n0030_lut [31]),
.O(\ALU/n0030 [31])
);
MUXCY \ALU/Madd_n0030_cy<31> (
.CI(\ALU/Madd_n0030_cy [30]),
.DI(Mram__n004031),
.S(\ALU/Madd_n0030_lut [31]),
.O(\ALU/Madd_n0030_cy [31])
);
XORCY \ALU/Madd_n0030_xor<30> (
.CI(\ALU/Madd_n0030_cy [29]),
.LI(\ALU/Madd_n0030_lut [30]),
.O(\ALU/n0030 [30])
);
MUXCY \ALU/Madd_n0030_cy<30> (
.CI(\ALU/Madd_n0030_cy [29]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [30]),
.O(\ALU/Madd_n0030_cy [30])
);
XORCY \ALU/Madd_n0030_xor<29> (
.CI(\ALU/Madd_n0030_cy [28]),
.LI(\ALU/Madd_n0030_lut [29]),
.O(\ALU/n0030 [29])
);
MUXCY \ALU/Madd_n0030_cy<29> (
.CI(\ALU/Madd_n0030_cy [28]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [29]),
.O(\ALU/Madd_n0030_cy [29])
);
XORCY \ALU/Madd_n0030_xor<28> (
.CI(\ALU/Madd_n0030_cy [27]),
.LI(\ALU/Madd_n0030_lut [28]),
.O(\ALU/n0030 [28])
);
MUXCY \ALU/Madd_n0030_cy<28> (
.CI(\ALU/Madd_n0030_cy [27]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [28]),
.O(\ALU/Madd_n0030_cy [28])
);
XORCY \ALU/Madd_n0030_xor<27> (
.CI(\ALU/Madd_n0030_cy [26]),
.LI(\ALU/Madd_n0030_lut [27]),
.O(\ALU/n0030 [27])
);
MUXCY \ALU/Madd_n0030_cy<27> (
.CI(\ALU/Madd_n0030_cy [26]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [27]),
.O(\ALU/Madd_n0030_cy [27])
);
XORCY \ALU/Madd_n0030_xor<26> (
.CI(\ALU/Madd_n0030_cy [25]),
.LI(\ALU/Madd_n0030_lut [26]),
.O(\ALU/n0030 [26])
);
MUXCY \ALU/Madd_n0030_cy<26> (
.CI(\ALU/Madd_n0030_cy [25]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [26]),
.O(\ALU/Madd_n0030_cy [26])
);
XORCY \ALU/Madd_n0030_xor<25> (
.CI(\ALU/Madd_n0030_cy [24]),
.LI(\ALU/Madd_n0030_lut [25]),
.O(\ALU/n0030 [25])
);
MUXCY \ALU/Madd_n0030_cy<25> (
.CI(\ALU/Madd_n0030_cy [24]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [25]),
.O(\ALU/Madd_n0030_cy [25])
);
XORCY \ALU/Madd_n0030_xor<24> (
.CI(\ALU/Madd_n0030_cy [23]),
.LI(\ALU/Madd_n0030_lut [24]),
.O(\ALU/n0030 [24])
);
MUXCY \ALU/Madd_n0030_cy<24> (
.CI(\ALU/Madd_n0030_cy [23]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [24]),
.O(\ALU/Madd_n0030_cy [24])
);
XORCY \ALU/Madd_n0030_xor<23> (
.CI(\ALU/Madd_n0030_cy [22]),
.LI(\ALU/Madd_n0030_lut [23]),
.O(\ALU/n0030 [23])
);
MUXCY \ALU/Madd_n0030_cy<23> (
.CI(\ALU/Madd_n0030_cy [22]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [23]),
.O(\ALU/Madd_n0030_cy [23])
);
XORCY \ALU/Madd_n0030_xor<22> (
.CI(\ALU/Madd_n0030_cy [21]),
.LI(\ALU/Madd_n0030_lut [22]),
.O(\ALU/n0030 [22])
);
MUXCY \ALU/Madd_n0030_cy<22> (
.CI(\ALU/Madd_n0030_cy [21]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [22]),
.O(\ALU/Madd_n0030_cy [22])
);
XORCY \ALU/Madd_n0030_xor<21> (
.CI(\ALU/Madd_n0030_cy [20]),
.LI(\ALU/Madd_n0030_lut [21]),
.O(\ALU/n0030 [21])
);
MUXCY \ALU/Madd_n0030_cy<21> (
.CI(\ALU/Madd_n0030_cy [20]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [21]),
.O(\ALU/Madd_n0030_cy [21])
);
XORCY \ALU/Madd_n0030_xor<20> (
.CI(\ALU/Madd_n0030_cy [19]),
.LI(\ALU/Madd_n0030_lut [20]),
.O(\ALU/n0030 [20])
);
MUXCY \ALU/Madd_n0030_cy<20> (
.CI(\ALU/Madd_n0030_cy [19]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [20]),
.O(\ALU/Madd_n0030_cy [20])
);
XORCY \ALU/Madd_n0030_xor<19> (
.CI(\ALU/Madd_n0030_cy [18]),
.LI(\ALU/Madd_n0030_lut [19]),
.O(\ALU/n0030 [19])
);
MUXCY \ALU/Madd_n0030_cy<19> (
.CI(\ALU/Madd_n0030_cy [18]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [19]),
.O(\ALU/Madd_n0030_cy [19])
);
XORCY \ALU/Madd_n0030_xor<18> (
.CI(\ALU/Madd_n0030_cy [17]),
.LI(\ALU/Madd_n0030_lut [18]),
.O(\ALU/n0030 [18])
);
MUXCY \ALU/Madd_n0030_cy<18> (
.CI(\ALU/Madd_n0030_cy [17]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [18]),
.O(\ALU/Madd_n0030_cy [18])
);
XORCY \ALU/Madd_n0030_xor<17> (
.CI(\ALU/Madd_n0030_cy [16]),
.LI(\ALU/Madd_n0030_lut [17]),
.O(\ALU/n0030 [17])
);
MUXCY \ALU/Madd_n0030_cy<17> (
.CI(\ALU/Madd_n0030_cy [16]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [17]),
.O(\ALU/Madd_n0030_cy [17])
);
XORCY \ALU/Madd_n0030_xor<16> (
.CI(\ALU/Madd_n0030_cy [15]),
.LI(\ALU/Madd_n0030_lut [16]),
.O(\ALU/n0030 [16])
);
MUXCY \ALU/Madd_n0030_cy<16> (
.CI(\ALU/Madd_n0030_cy [15]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [16]),
.O(\ALU/Madd_n0030_cy [16])
);
XORCY \ALU/Madd_n0030_xor<15> (
.CI(\ALU/Madd_n0030_cy [14]),
.LI(\ALU/Madd_n0030_lut [15]),
.O(\ALU/n0030 [15])
);
MUXCY \ALU/Madd_n0030_cy<15> (
.CI(\ALU/Madd_n0030_cy [14]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [15]),
.O(\ALU/Madd_n0030_cy [15])
);
XORCY \ALU/Madd_n0030_xor<14> (
.CI(\ALU/Madd_n0030_cy [13]),
.LI(\ALU/Madd_n0030_lut [14]),
.O(\ALU/n0030 [14])
);
MUXCY \ALU/Madd_n0030_cy<14> (
.CI(\ALU/Madd_n0030_cy [13]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [14]),
.O(\ALU/Madd_n0030_cy [14])
);
XORCY \ALU/Madd_n0030_xor<13> (
.CI(\ALU/Madd_n0030_cy [12]),
.LI(\ALU/Madd_n0030_lut [13]),
.O(\ALU/n0030 [13])
);
MUXCY \ALU/Madd_n0030_cy<13> (
.CI(\ALU/Madd_n0030_cy [12]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [13]),
.O(\ALU/Madd_n0030_cy [13])
);
XORCY \ALU/Madd_n0030_xor<12> (
.CI(\ALU/Madd_n0030_cy [11]),
.LI(\ALU/Madd_n0030_lut [12]),
.O(\ALU/n0030 [12])
);
MUXCY \ALU/Madd_n0030_cy<12> (
.CI(\ALU/Madd_n0030_cy [11]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [12]),
.O(\ALU/Madd_n0030_cy [12])
);
XORCY \ALU/Madd_n0030_xor<11> (
.CI(\ALU/Madd_n0030_cy [10]),
.LI(\ALU/Madd_n0030_lut [11]),
.O(\ALU/n0030 [11])
);
MUXCY \ALU/Madd_n0030_cy<11> (
.CI(\ALU/Madd_n0030_cy [10]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [11]),
.O(\ALU/Madd_n0030_cy [11])
);
XORCY \ALU/Madd_n0030_xor<10> (
.CI(\ALU/Madd_n0030_cy [9]),
.LI(\ALU/Madd_n0030_lut [10]),
.O(\ALU/n0030 [10])
);
MUXCY \ALU/Madd_n0030_cy<10> (
.CI(\ALU/Madd_n0030_cy [9]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [10]),
.O(\ALU/Madd_n0030_cy [10])
);
XORCY \ALU/Madd_n0030_xor<9> (
.CI(\ALU/Madd_n0030_cy [8]),
.LI(\ALU/Madd_n0030_lut [9]),
.O(\ALU/n0030 [9])
);
MUXCY \ALU/Madd_n0030_cy<9> (
.CI(\ALU/Madd_n0030_cy [8]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [9]),
.O(\ALU/Madd_n0030_cy [9])
);
XORCY \ALU/Madd_n0030_xor<8> (
.CI(\ALU/Madd_n0030_cy [7]),
.LI(\ALU/Madd_n0030_lut [8]),
.O(\ALU/n0030 [8])
);
MUXCY \ALU/Madd_n0030_cy<8> (
.CI(\ALU/Madd_n0030_cy [7]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [8]),
.O(\ALU/Madd_n0030_cy [8])
);
XORCY \ALU/Madd_n0030_xor<7> (
.CI(\ALU/Madd_n0030_cy [6]),
.LI(\ALU/Madd_n0030_lut [7]),
.O(\ALU/n0030 [7])
);
MUXCY \ALU/Madd_n0030_cy<7> (
.CI(\ALU/Madd_n0030_cy [6]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [7]),
.O(\ALU/Madd_n0030_cy [7])
);
XORCY \ALU/Madd_n0030_xor<6> (
.CI(\ALU/Madd_n0030_cy [5]),
.LI(\ALU/Madd_n0030_lut [6]),
.O(\ALU/n0030 [6])
);
MUXCY \ALU/Madd_n0030_cy<6> (
.CI(\ALU/Madd_n0030_cy [5]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [6]),
.O(\ALU/Madd_n0030_cy [6])
);
XORCY \ALU/Madd_n0030_xor<5> (
.CI(\ALU/Madd_n0030_cy [4]),
.LI(\ALU/Madd_n0030_lut [5]),
.O(\ALU/n0030 [5])
);
MUXCY \ALU/Madd_n0030_cy<5> (
.CI(\ALU/Madd_n0030_cy [4]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [5]),
.O(\ALU/Madd_n0030_cy [5])
);
XORCY \ALU/Madd_n0030_xor<4> (
.CI(\ALU/Madd_n0030_cy [3]),
.LI(\ALU/Madd_n0030_lut [4]),
.O(\ALU/n0030 [4])
);
MUXCY \ALU/Madd_n0030_cy<4> (
.CI(\ALU/Madd_n0030_cy [3]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [4]),
.O(\ALU/Madd_n0030_cy [4])
);
XORCY \ALU/Madd_n0030_xor<3> (
.CI(\ALU/Madd_n0030_cy [2]),
.LI(\ALU/Madd_n0030_lut [3]),
.O(\ALU/n0030 [3])
);
MUXCY \ALU/Madd_n0030_cy<3> (
.CI(\ALU/Madd_n0030_cy [2]),
.DI(Mram__n004010),
.S(\ALU/Madd_n0030_lut [3]),
.O(\ALU/Madd_n0030_cy [3])
);
XORCY \ALU/Madd_n0030_xor<2> (
.CI(\ALU/Madd_n0030_cy [1]),
.LI(\ALU/Madd_n0030_lut [2]),
.O(\ALU/n0030 [2])
);
MUXCY \ALU/Madd_n0030_cy<2> (
.CI(\ALU/Madd_n0030_cy [1]),
.DI(Mram__n004011),
.S(\ALU/Madd_n0030_lut [2]),
.O(\ALU/Madd_n0030_cy [2])
);
XORCY \ALU/Madd_n0030_xor<1> (
.CI(\ALU/Madd_n0030_cy [0]),
.LI(\ALU/Madd_n0030_lut [1]),
.O(\ALU/n0030 [1])
);
MUXCY \ALU/Madd_n0030_cy<1> (
.CI(\ALU/Madd_n0030_cy [0]),
.DI(Mram__n0040),
.S(\ALU/Madd_n0030_lut [1]),
.O(\ALU/Madd_n0030_cy [1])
);
XORCY \ALU/Madd_n0030_xor<0> (
.CI(\ALU/Madd_n0030_lut [31]),
.LI(\ALU/Madd_n0030_lut [0]),
.O(\ALU/n0030 [0])
);
MUXCY \ALU/Madd_n0030_cy<0> (
.CI(\ALU/Madd_n0030_lut [31]),
.DI(Mram__n0040),
.S(\ALU/Madd_n0030_lut [0]),
.O(\ALU/Madd_n0030_cy [0])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<32> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [31]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [32])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<31> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [30]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [31])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<31> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [30]),
.DI(Mram__n004031),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [31])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<30> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [29]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [30]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [30])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<30> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [29]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [30]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [30])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<29> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [28]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [29]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [29])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<29> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [28]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [29]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [29])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<28> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [27]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [28]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [28])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<28> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [27]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [28]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [28])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<27> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [26]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [27]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [27])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<27> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [26]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [27]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [27])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<26> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [25]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [26]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [26])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<26> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [25]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [26]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [26])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<25> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [24]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [25]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [25])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<25> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [24]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [25]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [25])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<24> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [23]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [24]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [24])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<24> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [23]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [24]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [24])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<23> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [22]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [23]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [23])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<23> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [22]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [23]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [23])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<22> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [21]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [22]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [22])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<22> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [21]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [22]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [22])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<21> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [20]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [21]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [21])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<21> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [20]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [21]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [21])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<20> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [19]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [20]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [20])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<20> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [19]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [20]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [20])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<19> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [18]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [19]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [19])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<19> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [18]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [19]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [19])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<18> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [17]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [18]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [18])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<18> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [17]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [18]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [18])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<17> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [16]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [17]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [17])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<17> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [16]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [17]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [17])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<16> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [15]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [16]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [16])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<16> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [15]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [16]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [16])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<15> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [14]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [15]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [15])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<15> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [14]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [15]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [15])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<14> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [13]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [14]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [14])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<14> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [13]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [14]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [14])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<13> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [12]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [13]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [13])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<13> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [12]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [13]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [13])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<12> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [11]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [12]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [12])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<12> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [11]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [12]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [12])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<11> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [10]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [11]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [11])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<11> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [10]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [11]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [11])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<10> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [9]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [10]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [10])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<10> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [9]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [10]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [10])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<9> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [8]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [9]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [9])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<9> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [8]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [9]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [9])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<8> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [7]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [8]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [8])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<8> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [7]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [8]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [8])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<7> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [6]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [7]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [7])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<7> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [6]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [7]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [7])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<6> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [5]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [6]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [6])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<6> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [5]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [6]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [6])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<5> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [4]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [5]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [5])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<5> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [4]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [5]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [5])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<4> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [3]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [4]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [4])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<4> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [3]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [4]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [4])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<3> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [2]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [3]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [3])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<3> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [2]),
.DI(Mram__n004010),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [3]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [3])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<2> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [1]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [2]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [2])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<2> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [1]),
.DI(Mram__n004011),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [2]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [2])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<1> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [0]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [1]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [1])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<1> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [0]),
.DI(Mram__n0040),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [1]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [1])
);
XORCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_xor<0> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31]),
.LI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [0]),
.O(\ALU/GND_2_o_GND_2_o_sub_7_OUT [0])
);
MUXCY \ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy<0> (
.CI(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31]),
.DI(Mram__n0040),
.S(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [0]),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_cy [0])
);
LUT2 #(
.INIT ( 4'h6 ))
Mram__n00401 (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_2_IBUF_3),
.O(Mram__n0040)
);
LUT3 #(
.INIT ( 8'hD8 ))
Mram__n0040101 (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(Mram__n004010)
);
LUT3 #(
.INIT ( 8'h72 ))
Mram__n0040311 (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(Mram__n004031)
);
LUT3 #(
.INIT ( 8'h72 ))
Mram__n0040321 (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Sh12 )
);
LUT3 #(
.INIT ( 8'hBA ))
Mram__n0040331 (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(Mram__n004033)
);
LUT3 #(
.INIT ( 8'hD8 ))
Mram__n0040371 (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Sh561 )
);
LUT2 #(
.INIT ( 4'h7 ))
\CL/Mram_AN12 (
.I0(\CL/Bit_Sel [0]),
.I1(\CL/Bit_Sel [1]),
.O(AN_0_OBUF_53)
);
LUT2 #(
.INIT ( 4'hD ))
\CL/Mram_AN111 (
.I0(\CL/Bit_Sel [1]),
.I1(\CL/Bit_Sel [0]),
.O(AN_1_OBUF_52)
);
LUT2 #(
.INIT ( 4'hD ))
\CL/Mram_AN21 (
.I0(\CL/Bit_Sel [0]),
.I1(\CL/Bit_Sel [1]),
.O(AN_2_OBUF_51)
);
LUT2 #(
.INIT ( 4'hE ))
\CL/Mram_AN31 (
.I0(\CL/Bit_Sel [1]),
.I1(\CL/Bit_Sel [0]),
.O(AN_3_OBUF_50)
);
LUT3 #(
.INIT ( 8'h08 ))
Mmux_dig81111 (
.I0(F_LED_SW_IBUF_6),
.I1(F[18]),
.I2(F[17]),
.O(Mmux_dig8111)
);
LUT3 #(
.INIT ( 8'h08 ))
Mmux_dig82111 (
.I0(F_LED_SW_IBUF_6),
.I1(F[22]),
.I2(F[21]),
.O(Mmux_dig8211_140)
);
LUT4 #(
.INIT ( 16'h2000 ))
Mmux_dig6111 (
.I0(F_LED_SW_IBUF_6),
.I1(\CL/Bit_Sel [1]),
.I2(F[27]),
.I3(F[26]),
.O(Mmux_dig611_141)
);
LUT4 #(
.INIT ( 16'h2000 ))
Mmux_dig6211 (
.I0(F_LED_SW_IBUF_6),
.I1(\CL/Bit_Sel [1]),
.I2(F[31]),
.I3(F[30]),
.O(Mmux_dig621)
);
LUT3 #(
.INIT ( 8'h10 ))
Mmux_dig81121 (
.I0(F_LED_SW_IBUF_6),
.I1(F[1]),
.I2(F[2]),
.O(Mmux_dig8112_143)
);
LUT3 #(
.INIT ( 8'h10 ))
Mmux_dig82121 (
.I0(F_LED_SW_IBUF_6),
.I1(F[5]),
.I2(F[6]),
.O(Mmux_dig8212)
);
LUT4 #(
.INIT ( 16'h1000 ))
Mmux_dig6121 (
.I0(\CL/Bit_Sel [1]),
.I1(F_LED_SW_IBUF_6),
.I2(F[10]),
.I3(F[11]),
.O(Mmux_dig612)
);
LUT6 #(
.INIT ( 64'h2020FF2020202020 ))
Mmux_dig8121 (
.I0(F[24]),
.I1(F[25]),
.I2(Mmux_dig611_141),
.I3(F[8]),
.I4(F[9]),
.I5(Mmux_dig612),
.O(Mmux_dig812)
);
LUT4 #(
.INIT ( 16'h1000 ))
Mmux_dig6221 (
.I0(\CL/Bit_Sel [1]),
.I1(F_LED_SW_IBUF_6),
.I2(F[15]),
.I3(F[14]),
.O(Mmux_dig622)
);
LUT6 #(
.INIT ( 64'h2020FF2020202020 ))
Mmux_dig8311 (
.I0(F[28]),
.I1(F[29]),
.I2(Mmux_dig621),
.I3(F[12]),
.I4(F[13]),
.I5(Mmux_dig622),
.O(Mmux_dig831)
);
LUT3 #(
.INIT ( 8'h08 ))
Mmux_dig5111 (
.I0(F[1]),
.I1(F[0]),
.I2(F_LED_SW_IBUF_6),
.O(Mmux_dig511_147)
);
LUT3 #(
.INIT ( 8'h08 ))
Mmux_dig5211 (
.I0(F[5]),
.I1(F[4]),
.I2(F_LED_SW_IBUF_6),
.O(Mmux_dig521)
);
LUT3 #(
.INIT ( 8'h80 ))
Mmux_dig5121 (
.I0(F[16]),
.I1(F_LED_SW_IBUF_6),
.I2(F[17]),
.O(Mmux_dig512)
);
LUT3 #(
.INIT ( 8'h80 ))
Mmux_dig5221 (
.I0(F_LED_SW_IBUF_6),
.I1(F[20]),
.I2(F[21]),
.O(Mmux_dig522)
);
LUT3 #(
.INIT ( 8'h01 ))
Mmux_dig81151 (
.I0(F_LED_SW_IBUF_6),
.I1(F[3]),
.I2(F[2]),
.O(Mmux_dig8115_151)
);
LUT3 #(
.INIT ( 8'h01 ))
Mmux_dig82151 (
.I0(F_LED_SW_IBUF_6),
.I1(F[7]),
.I2(F[6]),
.O(Mmux_dig8215_152)
);
LUT3 #(
.INIT ( 8'h10 ))
Mmux_dig81161 (
.I0(F[18]),
.I1(F[19]),
.I2(F_LED_SW_IBUF_6),
.O(Mmux_dig8116)
);
LUT3 #(
.INIT ( 8'h10 ))
Mmux_dig82161 (
.I0(F[22]),
.I1(F[23]),
.I2(F_LED_SW_IBUF_6),
.O(Mmux_dig8216)
);
LUT3 #(
.INIT ( 8'h10 ))
Mmux_dig811711 (
.I0(F[25]),
.I1(F[27]),
.I2(F_LED_SW_IBUF_6),
.O(Mmux_dig81171)
);
LUT3 #(
.INIT ( 8'h10 ))
Mmux_dig821711 (
.I0(F[29]),
.I1(F[31]),
.I2(F_LED_SW_IBUF_6),
.O(Mmux_dig82171)
);
LUT3 #(
.INIT ( 8'h10 ))
Mmux_dig71211 (
.I0(F_LED_SW_IBUF_6),
.I1(F[0]),
.I2(F[2]),
.O(Mmux_dig7121)
);
LUT3 #(
.INIT ( 8'h64 ))
Mram__n0040111 (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_2_IBUF_3),
.I2(AB_SW_1_IBUF_4),
.O(Mram__n004011)
);
LUT3 #(
.INIT ( 8'h64 ))
Mram__n0040351 (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_2_IBUF_3),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Mmux_F191 )
);
LUT3 #(
.INIT ( 8'h10 ))
\ALU/Mmux_F1331 (
.I0(ALU_OP_0_IBUF_2),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_2_IBUF_0),
.O(\ALU/Mmux_F102 )
);
LUT3 #(
.INIT ( 8'h08 ))
\ALU/Mmux_F1101 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_0_IBUF_2),
.I2(ALU_OP_1_IBUF_1),
.O(\ALU/Mmux_F110 )
);
LUT6 #(
.INIT ( 64'h60FFFF6060606060 ))
\ALU/Mmux_OF11 (
.I0(\ALU/GND_2_o_GND_2_o_sub_7_OUT [32]),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [31]),
.I2(\ALU/Mmux_F110 ),
.I3(\ALU/Madd_n0030_cy [31]),
.I4(\ALU/n0030 [31]),
.I5(\ALU/Mmux_F102 ),
.O(LED_1_OBUF_42)
);
LUT6 #(
.INIT ( 64'h1000000000000000 ))
\CL/count[17]_PWR_5_o_equal_1_o<17>1 (
.I0(\CL/count [0]),
.I1(\CL/count [1]),
.I2(\CL/count [9]),
.I3(\CL/count [8]),
.I4(\CL/count [7]),
.I5(\CL/count [5]),
.O(\CL/count[17]_PWR_5_o_equal_1_o<17> )
);
LUT6 #(
.INIT ( 64'h0000000100000000 ))
\CL/count[17]_PWR_5_o_equal_1_o<17>2 (
.I0(\CL/count [11]),
.I1(\CL/count [6]),
.I2(\CL/count [4]),
.I3(\CL/count [2]),
.I4(\CL/count [3]),
.I5(\CL/count[17]_PWR_5_o_equal_1_o<17> ),
.O(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 )
);
LUT5 #(
.INIT ( 32'h80000000 ))
\CL/count[17]_PWR_5_o_equal_1_o<17>3 (
.I0(\CL/count [14]),
.I1(\CL/count [13]),
.I2(\CL/count [17]),
.I3(\CL/count [16]),
.I4(\CL/count [15]),
.O(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 )
);
LUT5 #(
.INIT ( 32'hFFFDAAA8 ))
Mmux_dig719 (
.I0(\CL/Bit_Sel [0]),
.I1(Mmux_dig711),
.I2(Mmux_dig76),
.I3(Mmux_dig73),
.I4(Mmux_dig717),
.O(dig_6_OBUF_44)
);
LUT3 #(
.INIT ( 8'hD8 ))
Mmux_dig37 (
.I0(\CL/Bit_Sel [0]),
.I1(Mmux_dig812),
.I2(Mmux_dig831),
.O(Mmux_dig36_373)
);
LUT5 #(
.INIT ( 32'h10110010 ))
Mmux_dig312 (
.I0(F_LED_SW_IBUF_6),
.I1(F[11]),
.I2(F[9]),
.I3(F[10]),
.I4(F[8]),
.O(Mmux_dig310_377)
);
LUT6 #(
.INIT ( 64'h5551555155514440 ))
Mmux_dig313 (
.I0(\CL/Bit_Sel [1]),
.I1(\CL/Bit_Sel [0]),
.I2(Mmux_dig310_377),
.I3(Mmux_dig39_376),
.I4(Mmux_dig38_375),
.I5(Mmux_dig37_374),
.O(Mmux_dig312_378)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFAAA8 ))
Mmux_dig314 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig311),
.I2(Mmux_dig35),
.I3(Mmux_dig32),
.I4(Mmux_dig36_373),
.I5(Mmux_dig312_378),
.O(dig_2_OBUF_48)
);
LUT5 #(
.INIT ( 32'h08020082 ))
Mmux_dig21 (
.I0(F_LED_SW_IBUF_6),
.I1(F[26]),
.I2(F[27]),
.I3(F[25]),
.I4(F[24]),
.O(Mmux_dig2)
);
LUT5 #(
.INIT ( 32'h04010041 ))
Mmux_dig22 (
.I0(F_LED_SW_IBUF_6),
.I1(F[10]),
.I2(F[11]),
.I3(F[9]),
.I4(F[8]),
.O(Mmux_dig21_380)
);
LUT5 #(
.INIT ( 32'h08020082 ))
Mmux_dig23 (
.I0(F_LED_SW_IBUF_6),
.I1(F[30]),
.I2(F[31]),
.I3(F[29]),
.I4(F[28]),
.O(Mmux_dig22_381)
);
LUT5 #(
.INIT ( 32'h04010041 ))
Mmux_dig24 (
.I0(F_LED_SW_IBUF_6),
.I1(F[14]),
.I2(F[15]),
.I3(F[13]),
.I4(F[12]),
.O(Mmux_dig23_382)
);
LUT6 #(
.INIT ( 64'h5551555155514440 ))
Mmux_dig25 (
.I0(\CL/Bit_Sel [1]),
.I1(\CL/Bit_Sel [0]),
.I2(Mmux_dig21_380),
.I3(Mmux_dig2),
.I4(Mmux_dig23_382),
.I5(Mmux_dig22_381),
.O(Mmux_dig24_383)
);
LUT6 #(
.INIT ( 64'hAEAEAEAEFFAEAEAE ))
Mmux_dig27 (
.I0(Mmux_dig25_384),
.I1(Mmux_dig8116),
.I2(F[17]),
.I3(Mmux_dig8112_143),
.I4(F[3]),
.I5(F[0]),
.O(Mmux_dig26_385)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFAAA28880 ))
Mmux_dig213 (
.I0(\CL/Bit_Sel [1]),
.I1(\CL/Bit_Sel [0]),
.I2(Mmux_dig26_385),
.I3(Mmux_dig27_386),
.I4(Mmux_dig211),
.I5(Mmux_dig24_383),
.O(dig_1_OBUF_49)
);
LUT6 #(
.INIT ( 64'hFDA8FDA8FDFDFDA8 ))
Mmux_dig416 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig43),
.I2(Mmux_dig47),
.I3(Mmux_dig411),
.I4(Mmux_dig414),
.I5(\CL/Bit_Sel [0]),
.O(dig_3_OBUF_47)
);
LUT5 #(
.INIT ( 32'h20022000 ))
Mmux_dig52 (
.I0(F[13]),
.I1(F_LED_SW_IBUF_6),
.I2(F[12]),
.I3(F[14]),
.I4(F[15]),
.O(Mmux_dig51)
);
LUT5 #(
.INIT ( 32'h20022000 ))
Mmux_dig54 (
.I0(F[5]),
.I1(F_LED_SW_IBUF_6),
.I2(F[4]),
.I3(F[6]),
.I4(F[7]),
.O(Mmux_dig53)
);
LUT5 #(
.INIT ( 32'h80088000 ))
Mmux_dig56 (
.I0(F_LED_SW_IBUF_6),
.I1(F[25]),
.I2(F[24]),
.I3(F[26]),
.I4(F[27]),
.O(Mmux_dig55_398)
);
LUT5 #(
.INIT ( 32'h20022000 ))
Mmux_dig57 (
.I0(F[9]),
.I1(F_LED_SW_IBUF_6),
.I2(F[10]),
.I3(F[8]),
.I4(F[11]),
.O(Mmux_dig56_399)
);
LUT5 #(
.INIT ( 32'h80088000 ))
Mmux_dig58 (
.I0(F_LED_SW_IBUF_6),
.I1(F[17]),
.I2(F[16]),
.I3(F[18]),
.I4(F[19]),
.O(Mmux_dig57_400)
);
LUT5 #(
.INIT ( 32'h20022000 ))
Mmux_dig59 (
.I0(F[1]),
.I1(F_LED_SW_IBUF_6),
.I2(F[0]),
.I3(F[2]),
.I4(F[3]),
.O(Mmux_dig58_401)
);
LUT5 #(
.INIT ( 32'hFDFDFDA8 ))
Mmux_dig510 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig57_400),
.I2(Mmux_dig58_401),
.I3(Mmux_dig55_398),
.I4(Mmux_dig56_399),
.O(Mmux_dig59_402)
);
LUT5 #(
.INIT ( 32'hFDFDFDA8 ))
Mmux_dig511 (
.I0(\CL/Bit_Sel [0]),
.I1(Mmux_dig811_134),
.I2(Mmux_dig59_402),
.I3(Mmux_dig821),
.I4(Mmux_dig54_397),
.O(dig_4_OBUF_46)
);
LUT5 #(
.INIT ( 32'h20002002 ))
Mmux_dig62 (
.I0(F[9]),
.I1(F_LED_SW_IBUF_6),
.I2(F[11]),
.I3(F[10]),
.I4(F[8]),
.O(Mmux_dig61)
);
LUT5 #(
.INIT ( 32'h20002002 ))
Mmux_dig64 (
.I0(F[1]),
.I1(F_LED_SW_IBUF_6),
.I2(F[3]),
.I3(F[2]),
.I4(F[0]),
.O(Mmux_dig63)
);
LUT5 #(
.INIT ( 32'h80008008 ))
Mmux_dig66 (
.I0(F_LED_SW_IBUF_6),
.I1(F[29]),
.I2(F[30]),
.I3(F[31]),
.I4(F[28]),
.O(Mmux_dig65_406)
);
LUT5 #(
.INIT ( 32'h20002002 ))
Mmux_dig67 (
.I0(F[13]),
.I1(F_LED_SW_IBUF_6),
.I2(F[15]),
.I3(F[14]),
.I4(F[12]),
.O(Mmux_dig66_407)
);
LUT5 #(
.INIT ( 32'h80008008 ))
Mmux_dig68 (
.I0(F_LED_SW_IBUF_6),
.I1(F[21]),
.I2(F[22]),
.I3(F[23]),
.I4(F[20]),
.O(Mmux_dig67_408)
);
LUT5 #(
.INIT ( 32'h20002002 ))
Mmux_dig69 (
.I0(F[5]),
.I1(F_LED_SW_IBUF_6),
.I2(F[7]),
.I3(F[6]),
.I4(F[4]),
.O(Mmux_dig68_409)
);
LUT5 #(
.INIT ( 32'hFDFDFDA8 ))
Mmux_dig610 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig67_408),
.I2(Mmux_dig68_409),
.I3(Mmux_dig65_406),
.I4(Mmux_dig66_407),
.O(Mmux_dig69_410)
);
LUT5 #(
.INIT ( 32'hFDFDFDA8 ))
Mmux_dig611 (
.I0(\CL/Bit_Sel [0]),
.I1(Mmux_dig711),
.I2(Mmux_dig64_405),
.I3(Mmux_dig721),
.I4(Mmux_dig69_410),
.O(dig_5_OBUF_45)
);
LUT5 #(
.INIT ( 32'h00010100 ))
Mmux_dig8112 (
.I0(F[1]),
.I1(F_LED_SW_IBUF_6),
.I2(F[3]),
.I3(F[2]),
.I4(F[0]),
.O(Mmux_dig8114)
);
LUT5 #(
.INIT ( 32'h00010100 ))
Mmux_dig8214 (
.I0(F[5]),
.I1(F_LED_SW_IBUF_6),
.I2(F[7]),
.I3(F[6]),
.I4(F[4]),
.O(Mmux_dig8218)
);
LUT5 #(
.INIT ( 32'h08000000 ))
Mmux_dig81 (
.I0(F[20]),
.I1(F[21]),
.I2(F[22]),
.I3(F_LED_SW_IBUF_6),
.I4(F[23]),
.O(Mmux_dig8)
);
LUT5 #(
.INIT ( 32'h00000800 ))
Mmux_dig82 (
.I0(F[4]),
.I1(F[5]),
.I2(F_LED_SW_IBUF_6),
.I3(F[7]),
.I4(F[6]),
.O(Mmux_dig81_416)
);
LUT5 #(
.INIT ( 32'h08000000 ))
Mmux_dig83 (
.I0(F[28]),
.I1(F[29]),
.I2(F[30]),
.I3(F_LED_SW_IBUF_6),
.I4(F[31]),
.O(Mmux_dig82_417)
);
LUT5 #(
.INIT ( 32'h00000800 ))
Mmux_dig84 (
.I0(F[12]),
.I1(F[13]),
.I2(F_LED_SW_IBUF_6),
.I3(F[15]),
.I4(F[14]),
.O(Mmux_dig83_418)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFDFDFDA8 ))
Mmux_dig85 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig8),
.I2(Mmux_dig81_416),
.I3(Mmux_dig82_417),
.I4(Mmux_dig83_418),
.I5(Mmux_dig831),
.O(Mmux_dig84_419)
);
LUT5 #(
.INIT ( 32'h08000000 ))
Mmux_dig86 (
.I0(F[24]),
.I1(F[25]),
.I2(F[26]),
.I3(F_LED_SW_IBUF_6),
.I4(F[27]),
.O(Mmux_dig85_420)
);
LUT5 #(
.INIT ( 32'h00000800 ))
Mmux_dig87 (
.I0(F[8]),
.I1(F[9]),
.I2(F_LED_SW_IBUF_6),
.I3(F[11]),
.I4(F[10]),
.O(Mmux_dig86_421)
);
LUT5 #(
.INIT ( 32'h08000000 ))
Mmux_dig88 (
.I0(F[16]),
.I1(F[17]),
.I2(F[18]),
.I3(F_LED_SW_IBUF_6),
.I4(F[19]),
.O(Mmux_dig87_422)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF00004000 ))
Mmux_dig89 (
.I0(F_LED_SW_IBUF_6),
.I1(F[1]),
.I2(F[0]),
.I3(F[3]),
.I4(F[2]),
.I5(Mmux_dig87_422),
.O(Mmux_dig88_423)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFE54 ))
Mmux_dig810 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig86_421),
.I2(Mmux_dig85_420),
.I3(Mmux_dig88_423),
.I4(Mmux_dig811_134),
.I5(Mmux_dig812),
.O(Mmux_dig89_424)
);
LUT6 #(
.INIT ( 64'hFFFEFEFEFF545454 ))
Mmux_dig811 (
.I0(\CL/Bit_Sel [0]),
.I1(Mmux_dig821),
.I2(Mmux_dig84_419),
.I3(Mmux_dig311),
.I4(\CL/Bit_Sel [1]),
.I5(Mmux_dig89_424),
.O(dig_7_OBUF_43)
);
LUT4 #(
.INIT ( 16'h1000 ))
Mmux_dig7213 (
.I0(F_LED_SW_IBUF_6),
.I1(F[4]),
.I2(F[7]),
.I3(F[6]),
.O(Mmux_dig7213_425)
);
LUT5 #(
.INIT ( 32'h11141440 ))
\ALU/Mmux_F81 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(\ALU/Sh561 ),
.I3(Mram__n004011),
.I4(ALU_OP_0_IBUF_2),
.O(\ALU/Mmux_F172 )
);
LUT5 #(
.INIT ( 32'hFFEAEAEA ))
\ALU/Mmux_F84 (
.I0(\ALU/Mmux_F172 ),
.I1(\ALU/Mmux_F102 ),
.I2(\ALU/n0030 [16]),
.I3(\ALU/GND_2_o_GND_2_o_sub_7_OUT [16]),
.I4(\ALU/Mmux_F110 ),
.O(F[16])
);
LUT5 #(
.INIT ( 32'h11141440 ))
\ALU/Mmux_F261 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(\ALU/Mmux_F191 ),
.I3(Mram__n004010),
.I4(ALU_OP_0_IBUF_2),
.O(\ALU/Mmux_F101 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFF88A80020 ))
\ALU/Mmux_F263 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [3]),
.I3(ALU_OP_1_IBUF_1),
.I4(\ALU/Mmux_F261_426 ),
.I5(\ALU/Mmux_F101 ),
.O(F[3])
);
LUT5 #(
.INIT ( 32'h11141440 ))
\ALU/Mmux_F116 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(\ALU/Mmux_F191 ),
.I3(Mram__n004011),
.I4(ALU_OP_0_IBUF_2),
.O(\ALU/Mmux_F112 )
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F117 (
.I0(\ALU/Mmux_F102 ),
.I1(\ALU/n0030 [19]),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F112 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [19]),
.I5(\ALU/Mmux_F110 ),
.O(F[19])
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F233 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Sh12 ),
.I4(Mram__n004011),
.I5(\ALU/Mmux_F231 ),
.O(F[2])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F103 (
.I0(\ALU/Mmux_F102 ),
.I1(\ALU/n0030 [18]),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F101 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [18]),
.I5(\ALU/Mmux_F110 ),
.O(F[18])
);
LUT6 #(
.INIT ( 64'hAF0D0D0DAA080808 ))
\ALU/Mmux_F122 (
.I0(ALU_OP_0_IBUF_2),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [1]),
.I2(ALU_OP_1_IBUF_1),
.I3(\ALU/Mmux_F121_430 ),
.I4(\ALU/Mmux_F27211 ),
.I5(\ALU/n0030 [1]),
.O(\ALU/Mmux_F122_431 )
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F123 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(Mram__n004033),
.I4(Mram__n0040),
.I5(\ALU/Mmux_F122_431 ),
.O(F[1])
);
LUT5 #(
.INIT ( 32'hFFEAEAEA ))
\ALU/Mmux_F94 (
.I0(\ALU/Mmux_F172 ),
.I1(\ALU/Mmux_F102 ),
.I2(\ALU/n0030 [17]),
.I3(\ALU/GND_2_o_GND_2_o_sub_7_OUT [17]),
.I4(\ALU/Mmux_F110 ),
.O(F[17])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F164 (
.I0(\ALU/n0030 [23]),
.I1(\ALU/Mmux_F102 ),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F112 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [23]),
.I5(\ALU/Mmux_F110 ),
.O(F[23])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F153 (
.I0(\ALU/n0030 [22]),
.I1(\ALU/Mmux_F102 ),
.I2(\ALU/Mmux_F112 ),
.I3(\ALU/Madd_n0030_lut [31]),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [22]),
.I5(\ALU/Mmux_F110 ),
.O(F[22])
);
LUT5 #(
.INIT ( 32'h11141440 ))
\ALU/Mmux_F143 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(\ALU/Sh561 ),
.I3(Mram__n004010),
.I4(ALU_OP_0_IBUF_2),
.O(\ALU/Mmux_F133 )
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F144 (
.I0(\ALU/n0030 [21]),
.I1(\ALU/Mmux_F102 ),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F133 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [21]),
.I5(\ALU/Mmux_F110 ),
.O(F[21])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F134 (
.I0(\ALU/n0030 [20]),
.I1(\ALU/Mmux_F102 ),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F133 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [20]),
.I5(\ALU/Mmux_F110 ),
.O(F[20])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F255 (
.I0(\ALU/GND_2_o_GND_2_o_sub_7_OUT [31]),
.I1(\ALU/Mmux_F110 ),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F253 ),
.I4(\ALU/Mmux_F102 ),
.I5(\ALU/n0030 [31]),
.O(F[31])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F245 (
.I0(\ALU/GND_2_o_GND_2_o_sub_7_OUT [30]),
.I1(\ALU/Mmux_F110 ),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F112 ),
.I4(\ALU/Mmux_F102 ),
.I5(\ALU/n0030 [30]),
.O(F[30])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F225 (
.I0(\ALU/GND_2_o_GND_2_o_sub_7_OUT [29]),
.I1(\ALU/Mmux_F110 ),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F172 ),
.I4(\ALU/Mmux_F102 ),
.I5(\ALU/n0030 [29]),
.O(F[29])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F215 (
.I0(\ALU/GND_2_o_GND_2_o_sub_7_OUT [28]),
.I1(\ALU/Mmux_F110 ),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F133 ),
.I4(\ALU/Mmux_F102 ),
.I5(\ALU/n0030 [28]),
.O(F[28])
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F72 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Mmux_F191 ),
.I4(Mram__n004011),
.I5(\ALU/Mmux_F7 ),
.O(F[15])
);
LUT6 #(
.INIT ( 64'hAF0D0D0DAA080808 ))
\ALU/Mmux_F61 (
.I0(ALU_OP_0_IBUF_2),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [14]),
.I2(ALU_OP_1_IBUF_1),
.I3(\ALU/Mmux_F27211 ),
.I4(\ALU/Sh46 ),
.I5(\ALU/n0030 [14]),
.O(\ALU/Mmux_F6 )
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F62 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Mmux_F191 ),
.I4(Mram__n004010),
.I5(\ALU/Mmux_F6 ),
.O(F[14])
);
LUT6 #(
.INIT ( 64'hAF0D0D0DAA080808 ))
\ALU/Mmux_F51 (
.I0(ALU_OP_0_IBUF_2),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [13]),
.I2(ALU_OP_1_IBUF_1),
.I3(\ALU/Mmux_F27211 ),
.I4(\ALU/Sh45 ),
.I5(\ALU/n0030 [13]),
.O(\ALU/Mmux_F5 )
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F52 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Sh561 ),
.I4(Mram__n004011),
.I5(\ALU/Mmux_F5 ),
.O(F[13])
);
LUT6 #(
.INIT ( 64'hAF0D0D0DAA080808 ))
\ALU/Mmux_F41 (
.I0(ALU_OP_0_IBUF_2),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [12]),
.I2(ALU_OP_1_IBUF_1),
.I3(\ALU/Mmux_F27211 ),
.I4(\ALU/Sh44 ),
.I5(\ALU/n0030 [12]),
.O(\ALU/Mmux_F4 )
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F42 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Mmux_F191 ),
.I4(Mram__n004010),
.I5(\ALU/Mmux_F4 ),
.O(F[12])
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F322 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(Mram__n004033),
.I4(Mram__n004010),
.I5(\ALU/Mmux_F32_438 ),
.O(F[9])
);
LUT6 #(
.INIT ( 64'hAF0D0D0DAA080808 ))
\ALU/Mmux_F311 (
.I0(ALU_OP_0_IBUF_2),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [8]),
.I2(ALU_OP_1_IBUF_1),
.I3(\ALU/Mmux_F27211 ),
.I4(\ALU/Sh40 ),
.I5(\ALU/n0030 [8]),
.O(\ALU/Mmux_F31_439 )
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F312 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Mmux_F191 ),
.I4(Mram__n004011),
.I5(\ALU/Mmux_F31_439 ),
.O(F[8])
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F32 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Mmux_F191 ),
.I4(Mram__n004011),
.I5(\ALU/Mmux_F3 ),
.O(F[11])
);
LUT6 #(
.INIT ( 64'hAF0D0D0DAA080808 ))
\ALU/Mmux_F21 (
.I0(ALU_OP_0_IBUF_2),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [10]),
.I2(ALU_OP_1_IBUF_1),
.I3(\ALU/Mmux_F27211 ),
.I4(\ALU/Sh42 ),
.I5(\ALU/n0030 [10]),
.O(\ALU/Mmux_F2 )
);
LUT6 #(
.INIT ( 64'hBBBEBEEA11141440 ))
\ALU/Mmux_F22 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(\ALU/Sh12 ),
.I4(Mram__n004010),
.I5(\ALU/Mmux_F2 ),
.O(F[10])
);
LUT6 #(
.INIT ( 64'hFFFFFFFF88A80020 ))
\ALU/Mmux_F303 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [7]),
.I3(ALU_OP_1_IBUF_1),
.I4(\ALU/Mmux_F301 ),
.I5(\ALU/Mmux_F112 ),
.O(F[7])
);
LUT6 #(
.INIT ( 64'hFFFFFFFF88A80020 ))
\ALU/Mmux_F293 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [6]),
.I3(ALU_OP_1_IBUF_1),
.I4(\ALU/Mmux_F291 ),
.I5(\ALU/Mmux_F101 ),
.O(F[6])
);
LUT6 #(
.INIT ( 64'hFFFFFFFF88A80020 ))
\ALU/Mmux_F283 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [5]),
.I3(ALU_OP_1_IBUF_1),
.I4(\ALU/Mmux_F281 ),
.I5(\ALU/Mmux_F133 ),
.O(F[5])
);
LUT6 #(
.INIT ( 64'hFFFFFFFF88A80020 ))
\ALU/Mmux_F273 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [4]),
.I3(ALU_OP_1_IBUF_1),
.I4(\ALU/Mmux_F271 ),
.I5(\ALU/Mmux_F101 ),
.O(F[4])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F204 (
.I0(\ALU/Mmux_F102 ),
.I1(\ALU/n0030 [27]),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F112 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [27]),
.I5(\ALU/Mmux_F110 ),
.O(F[27])
);
LUT5 #(
.INIT ( 32'hFFEAEAEA ))
\ALU/Mmux_F194 (
.I0(\ALU/Mmux_F112 ),
.I1(\ALU/Mmux_F102 ),
.I2(\ALU/n0030 [26]),
.I3(\ALU/GND_2_o_GND_2_o_sub_7_OUT [26]),
.I4(\ALU/Mmux_F110 ),
.O(F[26])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F184 (
.I0(\ALU/Mmux_F102 ),
.I1(\ALU/n0030 [25]),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F133 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [25]),
.I5(\ALU/Mmux_F110 ),
.O(F[25])
);
LUT6 #(
.INIT ( 64'hFFFFFFF8FFF8FFF8 ))
\ALU/Mmux_F174 (
.I0(\ALU/Mmux_F102 ),
.I1(\ALU/n0030 [24]),
.I2(\ALU/Madd_n0030_lut [31]),
.I3(\ALU/Mmux_F172 ),
.I4(\ALU/GND_2_o_GND_2_o_sub_7_OUT [24]),
.I5(\ALU/Mmux_F110 ),
.O(F[24])
);
LUT5 #(
.INIT ( 32'h00000001 ))
\ALU/ZF<31>1 (
.I0(F[16]),
.I1(F[0]),
.I2(F[17]),
.I3(F[18]),
.I4(F[19]),
.O(\ALU/ZF [31])
);
LUT6 #(
.INIT ( 64'h0000000000000002 ))
\ALU/ZF<31>2 (
.I0(\ALU/ZF [31]),
.I1(F[8]),
.I2(F[6]),
.I3(F[29]),
.I4(F[30]),
.I5(F[7]),
.O(\ALU/ZF<31>1_449 )
);
LUT2 #(
.INIT ( 4'h1 ))
\ALU/ZF<31>3 (
.I0(F[9]),
.I1(F[20]),
.O(\ALU/ZF<31>2_450 )
);
LUT6 #(
.INIT ( 64'h0000000000000002 ))
\ALU/ZF<31>4 (
.I0(\ALU/ZF<31>2_450 ),
.I1(F[21]),
.I2(F[10]),
.I3(F[22]),
.I4(F[11]),
.I5(F[1]),
.O(\ALU/ZF<31>3_451 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\ALU/ZF<31>5 (
.I0(F[15]),
.I1(F[26]),
.I2(F[27]),
.I3(F[4]),
.I4(F[28]),
.I5(F[5]),
.O(\ALU/ZF<31>4_452 )
);
LUT2 #(
.INIT ( 4'h1 ))
\ALU/ZF<31>6 (
.I0(F[31]),
.I1(F[3]),
.O(\ALU/ZF<31>5_453 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\ALU/ZF<31>7 (
.I0(F[12]),
.I1(F[23]),
.I2(F[24]),
.I3(F[13]),
.I4(F[25]),
.I5(F[14]),
.O(\ALU/ZF<31>6_454 )
);
LUT6 #(
.INIT ( 64'h0000000080000000 ))
\ALU/ZF<31>8 (
.I0(\ALU/ZF<31>1_449 ),
.I1(\ALU/ZF<31>3_451 ),
.I2(\ALU/ZF<31>4_452 ),
.I3(\ALU/ZF<31>5_453 ),
.I4(\ALU/ZF<31>6_454 ),
.I5(F[2]),
.O(LED_0_OBUF_41)
);
IBUF ALU_OP_2_IBUF (
.I(ALU_OP[2]),
.O(ALU_OP_2_IBUF_0)
);
IBUF ALU_OP_1_IBUF (
.I(ALU_OP[1]),
.O(ALU_OP_1_IBUF_1)
);
IBUF ALU_OP_0_IBUF (
.I(ALU_OP[0]),
.O(ALU_OP_0_IBUF_2)
);
IBUF AB_SW_2_IBUF (
.I(AB_SW[2]),
.O(AB_SW_2_IBUF_3)
);
IBUF AB_SW_1_IBUF (
.I(AB_SW[1]),
.O(AB_SW_1_IBUF_4)
);
IBUF AB_SW_0_IBUF (
.I(AB_SW[0]),
.O(AB_SW_0_IBUF_5)
);
IBUF F_LED_SW_IBUF (
.I(F_LED_SW),
.O(F_LED_SW_IBUF_6)
);
IBUF RST_IBUF (
.I(RST),
.O(RST_IBUF_8)
);
OBUF LED_1_OBUF (
.I(LED_1_OBUF_42),
.O(LED[1])
);
OBUF LED_0_OBUF (
.I(LED_0_OBUF_41),
.O(LED[0])
);
OBUF dig_7_OBUF (
.I(dig_7_OBUF_43),
.O(dig[7])
);
OBUF dig_6_OBUF (
.I(dig_6_OBUF_44),
.O(dig[6])
);
OBUF dig_5_OBUF (
.I(dig_5_OBUF_45),
.O(dig[5])
);
OBUF dig_4_OBUF (
.I(dig_4_OBUF_46),
.O(dig[4])
);
OBUF dig_3_OBUF (
.I(dig_3_OBUF_47),
.O(dig[3])
);
OBUF dig_2_OBUF (
.I(dig_2_OBUF_48),
.O(dig[2])
);
OBUF dig_1_OBUF (
.I(dig_1_OBUF_49),
.O(dig[1])
);
OBUF dig_0_OBUF (
.I(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [31]),
.O(dig[0])
);
OBUF AN_3_OBUF (
.I(AN_3_OBUF_50),
.O(AN[3])
);
OBUF AN_2_OBUF (
.I(AN_2_OBUF_51),
.O(AN[2])
);
OBUF AN_1_OBUF (
.I(AN_1_OBUF_52),
.O(AN[1])
);
OBUF AN_0_OBUF (
.I(AN_0_OBUF_53),
.O(AN[0])
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<1>_rt (
.I0(\CL/count [1]),
.O(\CL/Mcount_count_cy<1>_rt_478 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<2>_rt (
.I0(\CL/count [2]),
.O(\CL/Mcount_count_cy<2>_rt_479 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<3>_rt (
.I0(\CL/count [3]),
.O(\CL/Mcount_count_cy<3>_rt_480 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<4>_rt (
.I0(\CL/count [4]),
.O(\CL/Mcount_count_cy<4>_rt_481 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<5>_rt (
.I0(\CL/count [5]),
.O(\CL/Mcount_count_cy<5>_rt_482 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<6>_rt (
.I0(\CL/count [6]),
.O(\CL/Mcount_count_cy<6>_rt_483 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<7>_rt (
.I0(\CL/count [7]),
.O(\CL/Mcount_count_cy<7>_rt_484 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<8>_rt (
.I0(\CL/count [8]),
.O(\CL/Mcount_count_cy<8>_rt_485 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<9>_rt (
.I0(\CL/count [9]),
.O(\CL/Mcount_count_cy<9>_rt_486 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<10>_rt (
.I0(\CL/count [10]),
.O(\CL/Mcount_count_cy<10>_rt_487 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<11>_rt (
.I0(\CL/count [11]),
.O(\CL/Mcount_count_cy<11>_rt_488 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<12>_rt (
.I0(\CL/count [12]),
.O(\CL/Mcount_count_cy<12>_rt_489 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<13>_rt (
.I0(\CL/count [13]),
.O(\CL/Mcount_count_cy<13>_rt_490 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<14>_rt (
.I0(\CL/count [14]),
.O(\CL/Mcount_count_cy<14>_rt_491 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<15>_rt (
.I0(\CL/count [15]),
.O(\CL/Mcount_count_cy<15>_rt_492 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_cy<16>_rt (
.I0(\CL/count [16]),
.O(\CL/Mcount_count_cy<16>_rt_493 )
);
LUT1 #(
.INIT ( 2'h2 ))
\CL/Mcount_count_xor<17>_rt (
.I0(\CL/count [17]),
.O(\CL/Mcount_count_xor<17>_rt_494 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_01 (
.I0(\Result<0>1 ),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_0 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_18 (
.I0(\Result<1>1 ),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_1 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_21 (
.I0(Result[2]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_2 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_31 (
.I0(Result[3]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_3 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_41 (
.I0(Result[4]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_4 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_51 (
.I0(Result[5]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_5 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_61 (
.I0(Result[6]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_6 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_71 (
.I0(Result[7]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_7 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_81 (
.I0(Result[8]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_8 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_91 (
.I0(Result[9]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_9 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_101 (
.I0(Result[10]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_10 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_111 (
.I0(Result[11]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_11 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_121 (
.I0(Result[12]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_12 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_131 (
.I0(Result[13]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_13 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_141 (
.I0(Result[14]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_14 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_151 (
.I0(Result[15]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_15 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_161 (
.I0(Result[16]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_16 )
);
LUT5 #(
.INIT ( 32'h2AAAAAAA ))
\CL/Mcount_count_eqn_171 (
.I0(Result[17]),
.I1(\CL/count [12]),
.I2(\CL/count [10]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>2_365 ),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Mcount_count_eqn_17 )
);
LUT4 #(
.INIT ( 16'h78F0 ))
\CL/Bit_Sel_0_dpot (
.I0(\CL/count [10]),
.I1(\CL/count [12]),
.I2(\CL/Bit_Sel [0]),
.I3(\CL/count[17]_PWR_5_o_equal_1_o<17>1_364 ),
.O(\CL/Bit_Sel_0_dpot_495 )
);
LUT5 #(
.INIT ( 32'h7F80FF00 ))
\CL/Bit_Sel_1_dpot (
.I0(\CL/count [10]),
.I1(\CL/count [12]),
.I2(\CL/Bit_Sel [0]),
.I3(\CL/Bit_Sel [1]),
.I4(\CL/count[17]_PWR_5_o_equal_1_o<17>21 ),
.O(\CL/Bit_Sel_1_dpot_496 )
);
LUT4 #(
.INIT ( 16'hF2B3 ))
Mmux_dig415_SW0 (
.I0(F[29]),
.I1(F[28]),
.I2(F[31]),
.I3(F[30]),
.O(N0)
);
LUT6 #(
.INIT ( 64'h00105150AABAFBFA ))
Mmux_dig415 (
.I0(F_LED_SW_IBUF_6),
.I1(F[13]),
.I2(F[12]),
.I3(F[14]),
.I4(F[15]),
.I5(N0),
.O(Mmux_dig414)
);
LUT3 #(
.INIT ( 8'h08 ))
Mmux_dig716_SW0 (
.I0(F[6]),
.I1(F[5]),
.I2(F[4]),
.O(N2)
);
LUT6 #(
.INIT ( 64'hF57DD555A0288000 ))
Mmux_dig716 (
.I0(F_LED_SW_IBUF_6),
.I1(F[20]),
.I2(F[21]),
.I3(F[23]),
.I4(F[22]),
.I5(N2),
.O(Mmux_dig715)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF88800800 ))
Mmux_dig712 (
.I0(F[29]),
.I1(F_LED_SW_IBUF_6),
.I2(F[28]),
.I3(F[30]),
.I4(F[31]),
.I5(N8),
.O(Mmux_dig710)
);
LUT5 #(
.INIT ( 32'hFFFF4F44 ))
Mmux_dig212_SW0 (
.I0(F[5]),
.I1(Mmux_dig8215_152),
.I2(F[21]),
.I3(Mmux_dig8216),
.I4(Mmux_dig29),
.O(N10)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF75202020 ))
Mmux_dig212 (
.I0(F[7]),
.I1(F[4]),
.I2(Mmux_dig8212),
.I3(F[6]),
.I4(Mmux_dig521),
.I5(N10),
.O(Mmux_dig211)
);
LUT6 #(
.INIT ( 64'hFFA8FFA8FFA8A8A8 ))
Mmux_dig33_SW0 (
.I0(Mmux_dig8115_151),
.I1(F[0]),
.I2(F[1]),
.I3(Mmux_dig8116),
.I4(F[16]),
.I5(F[17]),
.O(N12)
);
LUT6 #(
.INIT ( 64'hAAAAAAAA20AA2020 ))
Mmux_dig33 (
.I0(\CL/Bit_Sel [0]),
.I1(F[3]),
.I2(Mmux_dig511_147),
.I3(F[19]),
.I4(Mmux_dig512),
.I5(N12),
.O(Mmux_dig32)
);
LUT6 #(
.INIT ( 64'hFFA8FFA8FFA8A8A8 ))
Mmux_dig36_SW0 (
.I0(Mmux_dig8216),
.I1(F[20]),
.I2(F[21]),
.I3(Mmux_dig8215_152),
.I4(F[4]),
.I5(F[5]),
.O(N14)
);
LUT6 #(
.INIT ( 64'h5555555510551010 ))
Mmux_dig36 (
.I0(\CL/Bit_Sel [0]),
.I1(F[7]),
.I2(Mmux_dig521),
.I3(F[23]),
.I4(Mmux_dig522),
.I5(N14),
.O(Mmux_dig35)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF00101000 ))
Mmux_dig8115_SW0 (
.I0(F[17]),
.I1(F[19]),
.I2(F_LED_SW_IBUF_6),
.I3(F[16]),
.I4(F[18]),
.I5(Mmux_dig8114),
.O(N16)
);
LUT6 #(
.INIT ( 64'hFFFFAEEA55550440 ))
Mmux_dig8115 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig81171),
.I2(F[24]),
.I3(F[26]),
.I4(Mmux_dig8117),
.I5(N16),
.O(Mmux_dig811_134)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF00101000 ))
Mmux_dig8215_SW0 (
.I0(F[21]),
.I1(F[23]),
.I2(F_LED_SW_IBUF_6),
.I3(F[20]),
.I4(F[22]),
.I5(Mmux_dig8218),
.O(N18)
);
LUT6 #(
.INIT ( 64'hFFFFAEEA55550440 ))
Mmux_dig8215 (
.I0(\CL/Bit_Sel [1]),
.I1(Mmux_dig82171),
.I2(F[28]),
.I3(F[30]),
.I4(Mmux_dig8213),
.I5(N18),
.O(Mmux_dig821)
);
LUT6 #(
.INIT ( 64'hFFFF400040004000 ))
Mmux_dig7113_SW0 (
.I0(F[16]),
.I1(F[18]),
.I2(F[19]),
.I3(F_LED_SW_IBUF_6),
.I4(Mmux_dig7121),
.I5(F[3]),
.O(N20)
);
LUT6 #(
.INIT ( 64'hFFFF4F444F444F44 ))
Mmux_dig7113 (
.I0(F[8]),
.I1(Mmux_dig612),
.I2(F[24]),
.I3(Mmux_dig611_141),
.I4(\CL/Bit_Sel [1]),
.I5(N20),
.O(Mmux_dig711)
);
LUT5 #(
.INIT ( 32'hFFFF4000 ))
Mmux_dig7214_SW0 (
.I0(F[20]),
.I1(F[22]),
.I2(F[23]),
.I3(F_LED_SW_IBUF_6),
.I4(Mmux_dig7213_425),
.O(N22)
);
LUT6 #(
.INIT ( 64'hFFFF4F444F444F44 ))
Mmux_dig7214 (
.I0(F[28]),
.I1(Mmux_dig621),
.I2(F[12]),
.I3(Mmux_dig622),
.I4(\CL/Bit_Sel [1]),
.I5(N22),
.O(Mmux_dig721)
);
LUT5 #(
.INIT ( 32'h40004440 ))
Mmux_dig38 (
.I0(F[31]),
.I1(F_LED_SW_IBUF_6),
.I2(F[29]),
.I3(F[28]),
.I4(F[30]),
.O(Mmux_dig37_374)
);
LUT5 #(
.INIT ( 32'h10110010 ))
Mmux_dig39 (
.I0(F[15]),
.I1(F_LED_SW_IBUF_6),
.I2(F[12]),
.I3(F[14]),
.I4(F[13]),
.O(Mmux_dig38_375)
);
LUT5 #(
.INIT ( 32'h40004440 ))
Mmux_dig310 (
.I0(F[27]),
.I1(F_LED_SW_IBUF_6),
.I2(F[25]),
.I3(F[24]),
.I4(F[26]),
.O(Mmux_dig39_376)
);
LUT4 #(
.INIT ( 16'h1000 ))
Mmux_dig45 (
.I0(F[23]),
.I1(F[21]),
.I2(F[22]),
.I3(F_LED_SW_IBUF_6),
.O(Mmux_dig44_390)
);
LUT4 #(
.INIT ( 16'h0100 ))
Mmux_dig49 (
.I0(F_LED_SW_IBUF_6),
.I1(F[11]),
.I2(F[9]),
.I3(F[10]),
.O(Mmux_dig48_392)
);
LUT5 #(
.INIT ( 32'h00010100 ))
Mmux_dig8113 (
.I0(F_LED_SW_IBUF_6),
.I1(F[11]),
.I2(F[9]),
.I3(F[10]),
.I4(F[8]),
.O(Mmux_dig8117)
);
LUT5 #(
.INIT ( 32'h00010100 ))
Mmux_dig8211 (
.I0(F_LED_SW_IBUF_6),
.I1(F[13]),
.I2(F[15]),
.I3(F[12]),
.I4(F[14]),
.O(Mmux_dig8213)
);
LUT6 #(
.INIT ( 64'h4011404011111140 ))
\ALU/Mmux_F254 (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(ALU_OP_0_IBUF_2),
.I3(AB_SW_1_IBUF_4),
.I4(AB_SW_2_IBUF_3),
.I5(AB_SW_0_IBUF_5),
.O(\ALU/Mmux_F253 )
);
LUT5 #(
.INIT ( 32'h41444000 ))
Mmux_dig712_SW0 (
.I0(F_LED_SW_IBUF_6),
.I1(F[13]),
.I2(F[15]),
.I3(F[12]),
.I4(F[14]),
.O(N8)
);
LUT6 #(
.INIT ( 64'h4444444444444E44 ))
\ALU/Mmux_F302 (
.I0(ALU_OP_1_IBUF_1),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [7]),
.I2(Mram__n004011),
.I3(\ALU/Mmux_F191 ),
.I4(Mram__n004010),
.I5(Mram__n004031),
.O(\ALU/Mmux_F301 )
);
LUT5 #(
.INIT ( 32'h08000080 ))
Mmux_dig26 (
.I0(F[18]),
.I1(F_LED_SW_IBUF_6),
.I2(F[19]),
.I3(F[16]),
.I4(F[17]),
.O(Mmux_dig25_384)
);
LUT5 #(
.INIT ( 32'h08000080 ))
Mmux_dig210 (
.I0(F_LED_SW_IBUF_6),
.I1(F[22]),
.I2(F[23]),
.I3(F[20]),
.I4(F[21]),
.O(Mmux_dig29)
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<30> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [30])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<29> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [29])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<28> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [28])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<27> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [27])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<26> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [26])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<25> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [25])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<24> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [24])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<23> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [23])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<22> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [22])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<21> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [21])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<20> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [20])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<19> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [19])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<18> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [18])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<17> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [17])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<16> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [16])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<15> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [15])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<14> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [14])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<13> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [13])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<12> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [12])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<11> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [11])
);
LUT3 #(
.INIT ( 8'hD8 ))
\ALU/Madd_n0030_lut<10> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_2_IBUF_3),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [10])
);
LUT3 #(
.INIT ( 8'h64 ))
\ALU/Madd_n0030_lut<9> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Madd_n0030_lut [9])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<8> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [8])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<7> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [7])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<6> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [6])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<5> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [5])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<4> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [4])
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<3> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_0_IBUF_5),
.O(\ALU/Madd_n0030_lut [3])
);
LUT3 #(
.INIT ( 8'h64 ))
\ALU/Madd_n0030_lut<2> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Madd_n0030_lut [2])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<30> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [30])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<29> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [29])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<28> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [28])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<27> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [27])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<26> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [26])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<25> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [25])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<24> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [24])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<23> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [23])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<22> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [22])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<21> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [21])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<20> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [20])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<19> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [19])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<18> (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [18])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<17> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [17])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<16> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [16])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<15> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [15])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<14> (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [14])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<13> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [13])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<12> (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [12])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<11> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [11])
);
LUT3 #(
.INIT ( 8'h1D ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<10> (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [10])
);
LUT3 #(
.INIT ( 8'h9B ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<9> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [9])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<8> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [8])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<7> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [7])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<6> (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [6])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<5> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [5])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<4> (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [4])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<3> (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [3])
);
LUT3 #(
.INIT ( 8'h9B ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<2> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [2])
);
LUT5 #(
.INIT ( 32'h10010001 ))
Mmux_dig28 (
.I0(F[3]),
.I1(F_LED_SW_IBUF_6),
.I2(F[2]),
.I3(F[1]),
.I4(F[0]),
.O(Mmux_dig27_386)
);
LUT6 #(
.INIT ( 64'h4444444444444E44 ))
\ALU/Mmux_F262 (
.I0(ALU_OP_1_IBUF_1),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [3]),
.I2(Mram__n004011),
.I3(\ALU/Sh12 ),
.I4(Mram__n004010),
.I5(Mram__n004031),
.O(\ALU/Mmux_F261_426 )
);
LUT3 #(
.INIT ( 8'hA8 ))
\ALU/Madd_n0030_lut<1> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [1])
);
LUT3 #(
.INIT ( 8'h28 ))
\ALU/Madd_n0030_lut<0> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Madd_n0030_lut [0])
);
LUT3 #(
.INIT ( 8'h1F ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<1> (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [1])
);
LUT3 #(
.INIT ( 8'hD7 ))
\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut<0> (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_0_IBUF_5),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Msub_GND_2_o_GND_2_o_sub_7_OUT_lut [0])
);
LUT6 #(
.INIT ( 64'h4444444444444E44 ))
\ALU/Mmux_F292 (
.I0(ALU_OP_1_IBUF_1),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [6]),
.I2(Mram__n004011),
.I3(\ALU/Mmux_F121_430 ),
.I4(Mram__n004010),
.I5(Mram__n004031),
.O(\ALU/Mmux_F291 )
);
LUT6 #(
.INIT ( 64'h4444444444444E44 ))
\ALU/Mmux_F282 (
.I0(ALU_OP_1_IBUF_1),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [5]),
.I2(Mram__n004011),
.I3(\ALU/Sh45 ),
.I4(Mram__n004010),
.I5(Mram__n004031),
.O(\ALU/Mmux_F281 )
);
LUT6 #(
.INIT ( 64'h4444444444444E44 ))
\ALU/Mmux_F272 (
.I0(ALU_OP_1_IBUF_1),
.I1(\ALU/GND_2_o_GND_2_o_sub_7_OUT [4]),
.I2(Mram__n004011),
.I3(\ALU/Sh44 ),
.I4(Mram__n004010),
.I5(Mram__n004031),
.O(\ALU/Mmux_F271 )
);
LUT3 #(
.INIT ( 8'h08 ))
\ALU/Mmux_F121 (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_2_IBUF_3),
.I2(AB_SW_1_IBUF_4),
.O(\ALU/Mmux_F121_430 )
);
LUT2 #(
.INIT ( 4'h4 ))
\ALU/Sh4411 (
.I0(AB_SW_1_IBUF_4),
.I1(AB_SW_0_IBUF_5),
.O(\ALU/Sh44 )
);
LUT3 #(
.INIT ( 8'hA2 ))
\ALU/Sh4511 (
.I0(AB_SW_0_IBUF_5),
.I1(AB_SW_1_IBUF_4),
.I2(AB_SW_2_IBUF_3),
.O(\ALU/Sh45 )
);
LUT3 #(
.INIT ( 8'h10 ))
\ALU/Mmux_F272111 (
.I0(AB_SW_2_IBUF_3),
.I1(AB_SW_1_IBUF_4),
.I2(ALU_OP_1_IBUF_1),
.O(\ALU/Mmux_F27211 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\ALU/Mmux_F232 (
.I0(ALU_OP_1_IBUF_1),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [2]),
.I3(\ALU/GND_2_o_GND_2_o_sub_7_OUT [2]),
.O(\ALU/Mmux_F231 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\ALU/Mmux_F71 (
.I0(ALU_OP_1_IBUF_1),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [15]),
.I3(\ALU/GND_2_o_GND_2_o_sub_7_OUT [15]),
.O(\ALU/Mmux_F7 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\ALU/Mmux_F31 (
.I0(ALU_OP_1_IBUF_1),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [11]),
.I3(\ALU/GND_2_o_GND_2_o_sub_7_OUT [11]),
.O(\ALU/Mmux_F3 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\ALU/Mmux_F321 (
.I0(ALU_OP_1_IBUF_1),
.I1(ALU_OP_0_IBUF_2),
.I2(\ALU/n0030 [9]),
.I3(\ALU/GND_2_o_GND_2_o_sub_7_OUT [9]),
.O(\ALU/Mmux_F32_438 )
);
LUT3 #(
.INIT ( 8'hD8 ))
\ALU/Sh4621 (
.I0(Mram__n004010),
.I1(\ALU/Mmux_F121_430 ),
.I2(\ALU/Mmux_F191 ),
.O(\ALU/Sh46 )
);
LUT5 #(
.INIT ( 32'h44444E44 ))
\ALU/Sh4211 (
.I0(Mram__n004010),
.I1(\ALU/Mmux_F191 ),
.I2(Mram__n004011),
.I3(\ALU/Sh12 ),
.I4(Mram__n0040),
.O(\ALU/Sh42 )
);
LUT5 #(
.INIT ( 32'h51407160 ))
\ALU/Sh4011 (
.I0(Mram__n004010),
.I1(Mram__n004011),
.I2(\ALU/Sh12 ),
.I3(\ALU/Mmux_F191 ),
.I4(Mram__n0040),
.O(\ALU/Sh40 )
);
LUT6 #(
.INIT ( 64'h0000000100000000 ))
\CL/count[17]_PWR_5_o_equal_1_o<17>2_1 (
.I0(\CL/count [11]),
.I1(\CL/count [6]),
.I2(\CL/count [4]),
.I3(\CL/count [2]),
.I4(\CL/count [3]),
.I5(\CL/count[17]_PWR_5_o_equal_1_o<17> ),
.O(\CL/count[17]_PWR_5_o_equal_1_o<17>21 )
);
MUXF7 Mmux_dig48 (
.I0(N24),
.I1(N25),
.S(F_LED_SW_IBUF_6),
.O(Mmux_dig47)
);
LUT6 #(
.INIT ( 64'h5555555500044544 ))
Mmux_dig48_F (
.I0(\CL/Bit_Sel [0]),
.I1(F[4]),
.I2(F[5]),
.I3(F[6]),
.I4(F[7]),
.I5(Mmux_dig44_390),
.O(N24)
);
LUT6 #(
.INIT ( 64'h5555555504040444 ))
Mmux_dig48_G (
.I0(\CL/Bit_Sel [0]),
.I1(F[20]),
.I2(F[23]),
.I3(F[22]),
.I4(F[21]),
.I5(Mmux_dig44_390),
.O(N25)
);
MUXF7 Mmux_dig412 (
.I0(N26),
.I1(N27),
.S(F_LED_SW_IBUF_6),
.O(Mmux_dig411)
);
LUT6 #(
.INIT ( 64'hAAAAAAAA00088888 ))
Mmux_dig412_F (
.I0(\CL/Bit_Sel [0]),
.I1(F[8]),
.I2(F[9]),
.I3(F[10]),
.I4(F[11]),
.I5(Mmux_dig48_392),
.O(N26)
);
LUT6 #(
.INIT ( 64'hAAAAAAAA000888A8 ))
Mmux_dig412_G (
.I0(\CL/Bit_Sel [0]),
.I1(F[24]),
.I2(F[26]),
.I3(F[25]),
.I4(F[27]),
.I5(Mmux_dig48_392),
.O(N27)
);
MUXF7 Mmux_dig3113 (
.I0(N28),
.I1(N29),
.S(\CL/Bit_Sel [0]),
.O(Mmux_dig311)
);
LUT6 #(
.INIT ( 64'hFF80808080808080 ))
Mmux_dig3113_F (
.I0(Mmux_dig8211_140),
.I1(F[23]),
.I2(F[20]),
.I3(Mmux_dig8212),
.I4(F[7]),
.I5(F[4]),
.O(N28)
);
LUT6 #(
.INIT ( 64'hFF80808080808080 ))
Mmux_dig3113_G (
.I0(Mmux_dig8111),
.I1(F[19]),
.I2(F[16]),
.I3(Mmux_dig8112_143),
.I4(F[3]),
.I5(F[0]),
.O(N29)
);
MUXF7 Mmux_dig55 (
.I0(N30),
.I1(N31),
.S(\CL/Bit_Sel [1]),
.O(Mmux_dig54_397)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF80088000 ))
Mmux_dig55_F (
.I0(F_LED_SW_IBUF_6),
.I1(F[29]),
.I2(F[28]),
.I3(F[30]),
.I4(F[31]),
.I5(Mmux_dig51),
.O(N30)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF80088000 ))
Mmux_dig55_G (
.I0(F_LED_SW_IBUF_6),
.I1(F[21]),
.I2(F[20]),
.I3(F[22]),
.I4(F[23]),
.I5(Mmux_dig53),
.O(N31)
);
MUXF7 Mmux_dig65 (
.I0(N32),
.I1(N33),
.S(\CL/Bit_Sel [1]),
.O(Mmux_dig64_405)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF80008008 ))
Mmux_dig65_F (
.I0(F_LED_SW_IBUF_6),
.I1(F[25]),
.I2(F[26]),
.I3(F[27]),
.I4(F[24]),
.I5(Mmux_dig61),
.O(N32)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF80008008 ))
Mmux_dig65_G (
.I0(F_LED_SW_IBUF_6),
.I1(F[17]),
.I2(F[18]),
.I3(F[19]),
.I4(F[16]),
.I5(Mmux_dig63),
.O(N33)
);
MUXF7 Mmux_dig718 (
.I0(N34),
.I1(N35),
.S(\CL/Bit_Sel [1]),
.O(Mmux_dig717)
);
LUT5 #(
.INIT ( 32'hFFFFEAAA ))
Mmux_dig718_F (
.I0(Mmux_dig710),
.I1(Mmux_dig82171),
.I2(F[30]),
.I3(F[28]),
.I4(Mmux_dig721),
.O(N34)
);
LUT6 #(
.INIT ( 64'hFFFFFFEAFFFFFF40 ))
Mmux_dig718_G (
.I0(F[7]),
.I1(Mmux_dig8212),
.I2(F[4]),
.I3(Mmux_dig721),
.I4(Mmux_dig715),
.I5(Mmux_dig521),
.O(N35)
);
MUXF7 Mmux_dig77 (
.I0(N36),
.I1(N37),
.S(F_LED_SW_IBUF_6),
.O(Mmux_dig76)
);
LUT5 #(
.INIT ( 32'h41444000 ))
Mmux_dig77_F (
.I0(\CL/Bit_Sel [1]),
.I1(F[9]),
.I2(F[11]),
.I3(F[8]),
.I4(F[10]),
.O(N36)
);
LUT5 #(
.INIT ( 32'h41444000 ))
Mmux_dig77_G (
.I0(\CL/Bit_Sel [1]),
.I1(F[25]),
.I2(F[27]),
.I3(F[24]),
.I4(F[26]),
.O(N37)
);
MUXF7 Mmux_dig44 (
.I0(N38),
.I1(N39),
.S(F_LED_SW_IBUF_6),
.O(Mmux_dig43)
);
LUT5 #(
.INIT ( 32'h202022A0 ))
Mmux_dig44_F (
.I0(\CL/Bit_Sel [0]),
.I1(F[3]),
.I2(F[0]),
.I3(F[2]),
.I4(F[1]),
.O(N38)
);
LUT5 #(
.INIT ( 32'h202022A0 ))
Mmux_dig44_G (
.I0(\CL/Bit_Sel [0]),
.I1(F[19]),
.I2(F[16]),
.I3(F[18]),
.I4(F[17]),
.O(N39)
);
MUXF7 Mmux_dig74 (
.I0(N40),
.I1(N41),
.S(F_LED_SW_IBUF_6),
.O(Mmux_dig73)
);
LUT5 #(
.INIT ( 32'hA0288000 ))
Mmux_dig74_F (
.I0(\CL/Bit_Sel [1]),
.I1(F[0]),
.I2(F[1]),
.I3(F[3]),
.I4(F[2]),
.O(N40)
);
LUT5 #(
.INIT ( 32'hA0288000 ))
Mmux_dig74_G (
.I0(\CL/Bit_Sel [1]),
.I1(F[16]),
.I2(F[17]),
.I3(F[19]),
.I4(F[18]),
.O(N41)
);
MUXF7 \ALU/Mmux_F114 (
.I0(N42),
.I1(N43),
.S(ALU_OP_0_IBUF_2),
.O(F[0])
);
LUT6 #(
.INIT ( 64'hFFFF1894AAAA1894 ))
\ALU/Mmux_F114_F (
.I0(ALU_OP_1_IBUF_1),
.I1(AB_SW_2_IBUF_3),
.I2(AB_SW_0_IBUF_5),
.I3(AB_SW_1_IBUF_4),
.I4(ALU_OP_2_IBUF_0),
.I5(\ALU/n0030 [0]),
.O(N42)
);
LUT6 #(
.INIT ( 64'h6336333641141114 ))
\ALU/Mmux_F114_G (
.I0(ALU_OP_2_IBUF_0),
.I1(ALU_OP_1_IBUF_1),
.I2(AB_SW_0_IBUF_5),
.I3(AB_SW_2_IBUF_3),
.I4(AB_SW_1_IBUF_4),
.I5(\ALU/GND_2_o_GND_2_o_sub_7_OUT [0]),
.O(N43)
);
BUFGP clock_BUFGP (
.I(clock),
.O(clock_BUFGP_7)
);
INV \CL/Mcount_count_lut<0>_INV_0 (
.I(\CL/count [0]),
.O(\CL/Mcount_count_lut [0])
);
INV RST_inv1_INV_0 (
.I(RST_IBUF_8),
.O(RST_inv)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A22O_FUNCTIONAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a22o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_FUNCTIONAL_PP_V |
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)ff_primitives.v
***
****************************************************************************
****************************************************************************/
module fj_dff_e(q, d, clk);
output q;
input d, clk;
reg q;
always @(posedge (clk)) begin
q <= #1 d;
end
endmodule
module fj_dff_ec(q, d, clk, c);
output q;
input d, clk, c;
reg q;
always @(posedge clk or posedge c) begin
if (c)
q <= #1 1'b0;
else
q <= #1 d;
end
endmodule
module fj_dff_es(q, d, clk, s);
output q;
input d, clk, s;
reg q;
always @(posedge clk or posedge s) begin
if (s)
q <= #1 1'b1;
else
q <= #1 d;
end
endmodule
module fj_dff_ecs(q, d, clk, c, s);
output q;
input d, clk, c, s;
reg q;
always @(posedge clk or posedge s or posedge c) begin
if (c)
q <= #1 1'b0;
else if (s)
q <= #1 1'b1;
else
q <= #1 d;
end
endmodule
module fj_dff_e_muxscan(q, d, si, sm, clk);
output q;
input d, si, sm, clk;
reg q;
always @(posedge clk) begin
if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_dff_ec_muxscan(q, d, si, sm, clk, c);
output q;
input d, si, sm, clk, c;
reg q;
always @(posedge clk or posedge c) begin
if (c)
q <= #1 1'b0;
else if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_dff_es_muxscan(q, d, si, sm, clk, s);
output q;
input d, si, sm, clk, s;
reg q;
always @(posedge clk or posedge s) begin
if (s)
q <= #1 1'b1;
else if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_dff_ecs_muxscan(q, d, si, sm, clk, c, s);
output q;
input d, si, sm, clk, c, s;
reg q;
always @(posedge clk or posedge c or posedge s) begin
if (s)
q <= #1 1'b1;
else if (c)
q <= #1 1'b0;
else if (sm==1'b0)
q <= #1 d;
else if (sm==1'b1)
q <= #1 si;
else q <= #1 1'bx;
end
endmodule
module fj_latch_e(Q, G, D);
output Q;
input G, D;
reg Q;
always @ (G or D) begin
if (G==1) Q <= #1 D;
end
endmodule
module fj_xctrl(oe, en,en_);
output oe;
input en, en_;
assign oe = (en && (~en_));
endmodule
module UDP_MUX21(O_, A,B, S);
output O_;
input A, B, S;
assign O_ = ((~A && ~S) || (~B && S));
endmodule
module UDP_LATCH(Q, G_,D);
output Q;
input G_, D;
reg Q;
always @ (G_ or D) begin
if (G_==0) Q <= #1 D;
end
endmodule
module UDP_LATCH1(Q_, G1,G2, D1,D2);
output Q_;
input G1, G2, D1, D2;
reg Q_;
always @ (G1 or G2 or D1 or D2) begin
if ((G1==1) & (G2==0)) Q_ <= #1 D1;
else if ((G1==0) & (G2==1)) Q_ <= #1 D2;
end
endmodule
module UDP_LATCH2(Q_, G1A,G1B, D);
output Q_;
input G1A, G1B, D;
reg Q_;
always @ (G1A or G1B or D) begin
if ((G1A==1) & (G1B==1)) Q_ <= #1 ~D;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_aon(
input clock,
input reset,
input erst,
input test_mode,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [28:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [28:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [28:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
output io_moff_hfclkrst,
output io_moff_corerst,
output io_wdog_rst,
output io_lfclk,
output io_pmu_vddpaden,
output io_pmu_padrst,
input io_pmu_dwakeup,
input io_lfextclk,
input io_resetCauses_wdogrst,
input io_resetCauses_erst,
input io_resetCauses_porrst
);
wire rtc_clock;
wire rtc_reset;
wire rtc_io_regs_cfg_write_valid;
wire [31:0] rtc_io_regs_cfg_write_bits;
wire [31:0] rtc_io_regs_cfg_read;
wire rtc_io_regs_countLo_write_valid;
wire [31:0] rtc_io_regs_countLo_write_bits;
wire [31:0] rtc_io_regs_countLo_read;
wire rtc_io_regs_countHi_write_valid;
wire [31:0] rtc_io_regs_countHi_write_bits;
wire [31:0] rtc_io_regs_countHi_read;
wire rtc_io_regs_s_write_valid;
wire [31:0] rtc_io_regs_s_write_bits;
wire [31:0] rtc_io_regs_s_read;
wire rtc_io_regs_cmp_0_write_valid;
wire [31:0] rtc_io_regs_cmp_0_write_bits;
wire [31:0] rtc_io_regs_cmp_0_read;
wire rtc_io_regs_feed_write_valid;
wire [31:0] rtc_io_regs_feed_write_bits;
wire [31:0] rtc_io_regs_feed_read;
wire rtc_io_regs_key_write_valid;
wire [31:0] rtc_io_regs_key_write_bits;
wire [31:0] rtc_io_regs_key_read;
wire rtc_io_ip_0;
wire pmu_clock;
wire pmu_reset;
wire pmu_io_wakeup_awakeup;
wire pmu_io_wakeup_dwakeup;
wire pmu_io_wakeup_rtc;
wire pmu_io_wakeup_reset;
wire pmu_io_control_hfclkrst;
wire pmu_io_control_corerst;
wire pmu_io_control_reserved1;
wire pmu_io_control_vddpaden;
wire pmu_io_control_reserved0;
wire pmu_io_regs_ie_write_valid;
wire [3:0] pmu_io_regs_ie_write_bits;
wire [3:0] pmu_io_regs_ie_read;
wire pmu_io_regs_cause_write_valid;
wire [31:0] pmu_io_regs_cause_write_bits;
wire [31:0] pmu_io_regs_cause_read;
wire pmu_io_regs_sleep_write_valid;
wire [31:0] pmu_io_regs_sleep_write_bits;
wire [31:0] pmu_io_regs_sleep_read;
wire pmu_io_regs_key_write_valid;
wire [31:0] pmu_io_regs_key_write_bits;
wire [31:0] pmu_io_regs_key_read;
wire pmu_io_regs_wakeupProgram_0_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_0_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_0_read;
wire pmu_io_regs_wakeupProgram_1_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_1_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_1_read;
wire pmu_io_regs_wakeupProgram_2_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_2_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_2_read;
wire pmu_io_regs_wakeupProgram_3_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_3_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_3_read;
wire pmu_io_regs_wakeupProgram_4_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_4_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_4_read;
wire pmu_io_regs_wakeupProgram_5_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_5_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_5_read;
wire pmu_io_regs_wakeupProgram_6_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_6_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_6_read;
wire pmu_io_regs_wakeupProgram_7_write_valid;
wire [31:0] pmu_io_regs_wakeupProgram_7_write_bits;
wire [31:0] pmu_io_regs_wakeupProgram_7_read;
wire pmu_io_regs_sleepProgram_0_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_0_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_0_read;
wire pmu_io_regs_sleepProgram_1_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_1_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_1_read;
wire pmu_io_regs_sleepProgram_2_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_2_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_2_read;
wire pmu_io_regs_sleepProgram_3_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_3_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_3_read;
wire pmu_io_regs_sleepProgram_4_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_4_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_4_read;
wire pmu_io_regs_sleepProgram_5_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_5_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_5_read;
wire pmu_io_regs_sleepProgram_6_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_6_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_6_read;
wire pmu_io_regs_sleepProgram_7_write_valid;
wire [31:0] pmu_io_regs_sleepProgram_7_write_bits;
wire [31:0] pmu_io_regs_sleepProgram_7_read;
wire pmu_io_resetCauses_wdogrst;
wire pmu_io_resetCauses_erst;
wire pmu_io_resetCauses_porrst;
wire wdog_clock;
wire wdog_reset;
wire wdog_io_regs_cfg_write_valid;
wire [31:0] wdog_io_regs_cfg_write_bits;
wire [31:0] wdog_io_regs_cfg_read;
wire wdog_io_regs_countLo_write_valid;
wire [31:0] wdog_io_regs_countLo_write_bits;
wire [31:0] wdog_io_regs_countLo_read;
wire wdog_io_regs_countHi_write_valid;
wire [31:0] wdog_io_regs_countHi_write_bits;
wire [31:0] wdog_io_regs_countHi_read;
wire wdog_io_regs_s_write_valid;
wire [15:0] wdog_io_regs_s_write_bits;
wire [15:0] wdog_io_regs_s_read;
wire wdog_io_regs_cmp_0_write_valid;
wire [15:0] wdog_io_regs_cmp_0_write_bits;
wire [15:0] wdog_io_regs_cmp_0_read;
wire wdog_io_regs_feed_write_valid;
wire [31:0] wdog_io_regs_feed_write_bits;
wire [31:0] wdog_io_regs_feed_read;
wire wdog_io_regs_key_write_valid;
wire [31:0] wdog_io_regs_key_write_bits;
wire [31:0] wdog_io_regs_key_read;
wire wdog_io_ip_0;
wire wdog_io_corerst;
wire wdog_io_rst;
reg [31:0] backupRegs_0;
reg [31:0] GEN_792;
reg [31:0] backupRegs_1;
reg [31:0] GEN_793;
reg [31:0] backupRegs_2;
reg [31:0] GEN_794;
reg [31:0] backupRegs_3;
reg [31:0] GEN_795;
reg [31:0] backupRegs_4;
reg [31:0] GEN_796;
reg [31:0] backupRegs_5;
reg [31:0] GEN_797;
reg [31:0] backupRegs_6;
reg [31:0] GEN_798;
reg [31:0] backupRegs_7;
reg [31:0] GEN_799;
reg [31:0] backupRegs_8;
reg [31:0] GEN_800;
reg [31:0] backupRegs_9;
reg [31:0] GEN_801;
reg [31:0] backupRegs_10;
reg [31:0] GEN_802;
reg [31:0] backupRegs_11;
reg [31:0] GEN_803;
reg [31:0] backupRegs_12;
reg [31:0] GEN_804;
reg [31:0] backupRegs_13;
reg [31:0] GEN_805;
reg [31:0] backupRegs_14;
reg [31:0] GEN_806;
reg [31:0] backupRegs_15;
reg [31:0] GEN_807;
wire T_953_ready;
wire T_953_valid;
wire T_953_bits_read;
wire [9:0] T_953_bits_index;
wire [31:0] T_953_bits_data;
wire [3:0] T_953_bits_mask;
wire [9:0] T_953_bits_extra;
wire T_970;
wire [26:0] T_971;
wire [1:0] T_972;
wire [6:0] T_973;
wire [9:0] T_974;
wire T_992_ready;
wire T_992_valid;
wire T_992_bits_read;
wire [31:0] T_992_bits_data;
wire [9:0] T_992_bits_extra;
wire T_1028_ready;
wire T_1028_valid;
wire T_1028_bits_read;
wire [9:0] T_1028_bits_index;
wire [31:0] T_1028_bits_data;
wire [3:0] T_1028_bits_mask;
wire [9:0] T_1028_bits_extra;
wire Queue_1_clock;
wire Queue_1_reset;
wire Queue_1_io_enq_ready;
wire Queue_1_io_enq_valid;
wire Queue_1_io_enq_bits_read;
wire [9:0] Queue_1_io_enq_bits_index;
wire [31:0] Queue_1_io_enq_bits_data;
wire [3:0] Queue_1_io_enq_bits_mask;
wire [9:0] Queue_1_io_enq_bits_extra;
wire Queue_1_io_deq_ready;
wire Queue_1_io_deq_valid;
wire Queue_1_io_deq_bits_read;
wire [9:0] Queue_1_io_deq_bits_index;
wire [31:0] Queue_1_io_deq_bits_data;
wire [3:0] Queue_1_io_deq_bits_mask;
wire [9:0] Queue_1_io_deq_bits_extra;
wire Queue_1_io_count;
wire [9:0] T_1310;
wire [9:0] T_1311;
wire T_1313;
wire [9:0] T_1314;
wire [9:0] T_1315;
wire T_1317;
wire [9:0] T_1320;
wire T_1322;
wire [9:0] T_1323;
wire [9:0] T_1324;
wire T_1326;
wire [9:0] T_1328;
wire [9:0] T_1329;
wire T_1331;
wire [9:0] T_1332;
wire [9:0] T_1333;
wire T_1335;
wire [9:0] T_1337;
wire [9:0] T_1338;
wire T_1340;
wire [9:0] T_1341;
wire [9:0] T_1342;
wire T_1344;
wire [9:0] T_1346;
wire [9:0] T_1347;
wire T_1349;
wire [9:0] T_1350;
wire [9:0] T_1351;
wire T_1353;
wire [9:0] T_1355;
wire [9:0] T_1356;
wire T_1358;
wire [9:0] T_1359;
wire [9:0] T_1360;
wire T_1362;
wire [9:0] T_1364;
wire [9:0] T_1365;
wire T_1367;
wire [9:0] T_1368;
wire [9:0] T_1369;
wire T_1371;
wire [9:0] T_1373;
wire [9:0] T_1374;
wire T_1376;
wire [9:0] T_1377;
wire [9:0] T_1378;
wire T_1380;
wire [9:0] T_1382;
wire [9:0] T_1383;
wire T_1385;
wire [9:0] T_1386;
wire [9:0] T_1387;
wire T_1389;
wire [9:0] T_1391;
wire [9:0] T_1392;
wire T_1394;
wire [9:0] T_1395;
wire [9:0] T_1396;
wire T_1398;
wire [9:0] T_1400;
wire [9:0] T_1401;
wire T_1403;
wire [9:0] T_1404;
wire [9:0] T_1405;
wire T_1407;
wire [9:0] T_1409;
wire [9:0] T_1410;
wire T_1412;
wire [9:0] T_1413;
wire [9:0] T_1414;
wire T_1416;
wire [9:0] T_1418;
wire [9:0] T_1419;
wire T_1421;
wire [9:0] T_1422;
wire [9:0] T_1423;
wire T_1425;
wire [9:0] T_1427;
wire [9:0] T_1428;
wire T_1430;
wire [9:0] T_1431;
wire [9:0] T_1432;
wire T_1434;
wire [9:0] T_1436;
wire [9:0] T_1437;
wire T_1439;
wire [9:0] T_1440;
wire [9:0] T_1441;
wire T_1443;
wire [9:0] T_1445;
wire [9:0] T_1446;
wire T_1448;
wire [9:0] T_1449;
wire [9:0] T_1450;
wire T_1452;
wire [9:0] T_1454;
wire [9:0] T_1455;
wire T_1457;
wire [9:0] T_1458;
wire [9:0] T_1459;
wire T_1461;
wire [9:0] T_1463;
wire [9:0] T_1464;
wire T_1466;
wire [9:0] T_1467;
wire [9:0] T_1468;
wire T_1470;
wire [9:0] T_1472;
wire [9:0] T_1473;
wire T_1475;
wire [9:0] T_1476;
wire [9:0] T_1477;
wire T_1479;
wire [9:0] T_1481;
wire [9:0] T_1482;
wire T_1484;
wire [9:0] T_1485;
wire [9:0] T_1486;
wire T_1488;
wire [9:0] T_1490;
wire [9:0] T_1491;
wire T_1493;
wire [9:0] T_1494;
wire [9:0] T_1495;
wire T_1497;
wire [9:0] T_1499;
wire [9:0] T_1500;
wire T_1502;
wire [9:0] T_1503;
wire [9:0] T_1504;
wire T_1506;
wire [9:0] T_1508;
wire [9:0] T_1509;
wire T_1511;
wire [9:0] T_1512;
wire [9:0] T_1513;
wire T_1515;
wire [9:0] T_1517;
wire [9:0] T_1518;
wire T_1520;
wire [9:0] T_1521;
wire [9:0] T_1522;
wire T_1524;
wire [9:0] T_1526;
wire [9:0] T_1527;
wire T_1529;
wire [9:0] T_1530;
wire [9:0] T_1531;
wire T_1533;
wire [9:0] T_1535;
wire [9:0] T_1536;
wire T_1538;
wire [9:0] T_1539;
wire [9:0] T_1540;
wire T_1542;
wire [9:0] T_1544;
wire [9:0] T_1545;
wire T_1547;
wire [9:0] T_1548;
wire [9:0] T_1549;
wire T_1551;
wire [9:0] T_1553;
wire [9:0] T_1554;
wire T_1556;
wire [9:0] T_1557;
wire [9:0] T_1558;
wire T_1560;
wire [9:0] T_1562;
wire [9:0] T_1563;
wire T_1565;
wire [9:0] T_1566;
wire [9:0] T_1567;
wire T_1569;
wire [9:0] T_1571;
wire [9:0] T_1572;
wire T_1574;
wire [9:0] T_1575;
wire [9:0] T_1576;
wire T_1578;
wire [9:0] T_1580;
wire [9:0] T_1581;
wire T_1583;
wire [9:0] T_1584;
wire [9:0] T_1585;
wire T_1587;
wire [9:0] T_1589;
wire [9:0] T_1590;
wire T_1592;
wire [9:0] T_1593;
wire [9:0] T_1594;
wire T_1596;
wire [9:0] T_1598;
wire [9:0] T_1599;
wire T_1601;
wire [9:0] T_1602;
wire [9:0] T_1603;
wire T_1605;
wire [9:0] T_1607;
wire [9:0] T_1608;
wire T_1610;
wire [9:0] T_1611;
wire [9:0] T_1612;
wire T_1614;
wire [9:0] T_1616;
wire [9:0] T_1617;
wire T_1619;
wire [9:0] T_1620;
wire [9:0] T_1621;
wire T_1623;
wire [9:0] T_1625;
wire [9:0] T_1626;
wire T_1628;
wire [9:0] T_1629;
wire [9:0] T_1630;
wire T_1632;
wire [9:0] T_1634;
wire [9:0] T_1635;
wire T_1637;
wire [9:0] T_1638;
wire [9:0] T_1639;
wire T_1641;
wire [9:0] T_1643;
wire [9:0] T_1644;
wire T_1646;
wire [9:0] T_1647;
wire [9:0] T_1648;
wire T_1650;
wire [9:0] T_1652;
wire [9:0] T_1653;
wire T_1655;
wire [9:0] T_1656;
wire [9:0] T_1657;
wire T_1659;
wire [9:0] T_1661;
wire [9:0] T_1662;
wire T_1664;
wire [9:0] T_1665;
wire [9:0] T_1666;
wire T_1668;
wire [9:0] T_1670;
wire [9:0] T_1671;
wire T_1673;
wire [9:0] T_1674;
wire [9:0] T_1675;
wire T_1677;
wire [9:0] T_1679;
wire [9:0] T_1680;
wire T_1682;
wire [9:0] T_1683;
wire [9:0] T_1684;
wire T_1686;
wire [9:0] T_1688;
wire [9:0] T_1689;
wire T_1691;
wire [9:0] T_1692;
wire [9:0] T_1693;
wire T_1695;
wire [9:0] T_1697;
wire [9:0] T_1698;
wire T_1700;
wire [9:0] T_1701;
wire [9:0] T_1702;
wire T_1704;
wire [9:0] T_1706;
wire [9:0] T_1707;
wire T_1709;
wire [9:0] T_1710;
wire [9:0] T_1711;
wire T_1713;
wire [9:0] T_1715;
wire [9:0] T_1716;
wire T_1718;
wire [9:0] T_1719;
wire [9:0] T_1720;
wire T_1722;
wire [9:0] T_1724;
wire [9:0] T_1725;
wire T_1727;
wire [9:0] T_1728;
wire [9:0] T_1729;
wire T_1731;
wire [9:0] T_1733;
wire [9:0] T_1734;
wire T_1736;
wire [9:0] T_1737;
wire [9:0] T_1738;
wire T_1740;
wire [9:0] T_1742;
wire [9:0] T_1743;
wire T_1745;
wire [9:0] T_1746;
wire [9:0] T_1747;
wire T_1749;
wire [9:0] T_1751;
wire [9:0] T_1752;
wire T_1754;
wire [9:0] T_1755;
wire [9:0] T_1756;
wire T_1758;
wire T_1762_0;
wire T_1762_1;
wire T_1762_2;
wire T_1762_3;
wire T_1762_4;
wire T_1762_5;
wire T_1762_6;
wire T_1762_7;
wire T_1762_8;
wire T_1762_9;
wire T_1762_10;
wire T_1762_11;
wire T_1762_12;
wire T_1762_13;
wire T_1762_14;
wire T_1762_15;
wire T_1762_16;
wire T_1762_17;
wire T_1762_18;
wire T_1762_19;
wire T_1762_20;
wire T_1762_21;
wire T_1762_22;
wire T_1762_23;
wire T_1762_24;
wire T_1762_25;
wire T_1762_26;
wire T_1762_27;
wire T_1762_28;
wire T_1762_29;
wire T_1762_30;
wire T_1762_31;
wire T_1762_32;
wire T_1762_33;
wire T_1762_34;
wire T_1762_35;
wire T_1762_36;
wire T_1762_37;
wire T_1762_38;
wire T_1762_39;
wire T_1762_40;
wire T_1762_41;
wire T_1762_42;
wire T_1762_43;
wire T_1762_44;
wire T_1762_45;
wire T_1762_46;
wire T_1762_47;
wire T_1762_48;
wire T_1762_49;
wire T_1767_0;
wire T_1767_1;
wire T_1767_2;
wire T_1767_3;
wire T_1767_4;
wire T_1767_5;
wire T_1767_6;
wire T_1767_7;
wire T_1767_8;
wire T_1767_9;
wire T_1767_10;
wire T_1767_11;
wire T_1767_12;
wire T_1767_13;
wire T_1767_14;
wire T_1767_15;
wire T_1767_16;
wire T_1767_17;
wire T_1767_18;
wire T_1767_19;
wire T_1767_20;
wire T_1767_21;
wire T_1767_22;
wire T_1767_23;
wire T_1767_24;
wire T_1767_25;
wire T_1767_26;
wire T_1767_27;
wire T_1767_28;
wire T_1767_29;
wire T_1767_30;
wire T_1767_31;
wire T_1767_32;
wire T_1767_33;
wire T_1767_34;
wire T_1767_35;
wire T_1767_36;
wire T_1767_37;
wire T_1767_38;
wire T_1767_39;
wire T_1767_40;
wire T_1767_41;
wire T_1767_42;
wire T_1767_43;
wire T_1767_44;
wire T_1767_45;
wire T_1767_46;
wire T_1767_47;
wire T_1767_48;
wire T_1767_49;
wire T_1772_0;
wire T_1772_1;
wire T_1772_2;
wire T_1772_3;
wire T_1772_4;
wire T_1772_5;
wire T_1772_6;
wire T_1772_7;
wire T_1772_8;
wire T_1772_9;
wire T_1772_10;
wire T_1772_11;
wire T_1772_12;
wire T_1772_13;
wire T_1772_14;
wire T_1772_15;
wire T_1772_16;
wire T_1772_17;
wire T_1772_18;
wire T_1772_19;
wire T_1772_20;
wire T_1772_21;
wire T_1772_22;
wire T_1772_23;
wire T_1772_24;
wire T_1772_25;
wire T_1772_26;
wire T_1772_27;
wire T_1772_28;
wire T_1772_29;
wire T_1772_30;
wire T_1772_31;
wire T_1772_32;
wire T_1772_33;
wire T_1772_34;
wire T_1772_35;
wire T_1772_36;
wire T_1772_37;
wire T_1772_38;
wire T_1772_39;
wire T_1772_40;
wire T_1772_41;
wire T_1772_42;
wire T_1772_43;
wire T_1772_44;
wire T_1772_45;
wire T_1772_46;
wire T_1772_47;
wire T_1772_48;
wire T_1772_49;
wire T_1777_0;
wire T_1777_1;
wire T_1777_2;
wire T_1777_3;
wire T_1777_4;
wire T_1777_5;
wire T_1777_6;
wire T_1777_7;
wire T_1777_8;
wire T_1777_9;
wire T_1777_10;
wire T_1777_11;
wire T_1777_12;
wire T_1777_13;
wire T_1777_14;
wire T_1777_15;
wire T_1777_16;
wire T_1777_17;
wire T_1777_18;
wire T_1777_19;
wire T_1777_20;
wire T_1777_21;
wire T_1777_22;
wire T_1777_23;
wire T_1777_24;
wire T_1777_25;
wire T_1777_26;
wire T_1777_27;
wire T_1777_28;
wire T_1777_29;
wire T_1777_30;
wire T_1777_31;
wire T_1777_32;
wire T_1777_33;
wire T_1777_34;
wire T_1777_35;
wire T_1777_36;
wire T_1777_37;
wire T_1777_38;
wire T_1777_39;
wire T_1777_40;
wire T_1777_41;
wire T_1777_42;
wire T_1777_43;
wire T_1777_44;
wire T_1777_45;
wire T_1777_46;
wire T_1777_47;
wire T_1777_48;
wire T_1777_49;
wire T_1782_0;
wire T_1782_1;
wire T_1782_2;
wire T_1782_3;
wire T_1782_4;
wire T_1782_5;
wire T_1782_6;
wire T_1782_7;
wire T_1782_8;
wire T_1782_9;
wire T_1782_10;
wire T_1782_11;
wire T_1782_12;
wire T_1782_13;
wire T_1782_14;
wire T_1782_15;
wire T_1782_16;
wire T_1782_17;
wire T_1782_18;
wire T_1782_19;
wire T_1782_20;
wire T_1782_21;
wire T_1782_22;
wire T_1782_23;
wire T_1782_24;
wire T_1782_25;
wire T_1782_26;
wire T_1782_27;
wire T_1782_28;
wire T_1782_29;
wire T_1782_30;
wire T_1782_31;
wire T_1782_32;
wire T_1782_33;
wire T_1782_34;
wire T_1782_35;
wire T_1782_36;
wire T_1782_37;
wire T_1782_38;
wire T_1782_39;
wire T_1782_40;
wire T_1782_41;
wire T_1782_42;
wire T_1782_43;
wire T_1782_44;
wire T_1782_45;
wire T_1782_46;
wire T_1782_47;
wire T_1782_48;
wire T_1782_49;
wire T_1787_0;
wire T_1787_1;
wire T_1787_2;
wire T_1787_3;
wire T_1787_4;
wire T_1787_5;
wire T_1787_6;
wire T_1787_7;
wire T_1787_8;
wire T_1787_9;
wire T_1787_10;
wire T_1787_11;
wire T_1787_12;
wire T_1787_13;
wire T_1787_14;
wire T_1787_15;
wire T_1787_16;
wire T_1787_17;
wire T_1787_18;
wire T_1787_19;
wire T_1787_20;
wire T_1787_21;
wire T_1787_22;
wire T_1787_23;
wire T_1787_24;
wire T_1787_25;
wire T_1787_26;
wire T_1787_27;
wire T_1787_28;
wire T_1787_29;
wire T_1787_30;
wire T_1787_31;
wire T_1787_32;
wire T_1787_33;
wire T_1787_34;
wire T_1787_35;
wire T_1787_36;
wire T_1787_37;
wire T_1787_38;
wire T_1787_39;
wire T_1787_40;
wire T_1787_41;
wire T_1787_42;
wire T_1787_43;
wire T_1787_44;
wire T_1787_45;
wire T_1787_46;
wire T_1787_47;
wire T_1787_48;
wire T_1787_49;
wire T_1792_0;
wire T_1792_1;
wire T_1792_2;
wire T_1792_3;
wire T_1792_4;
wire T_1792_5;
wire T_1792_6;
wire T_1792_7;
wire T_1792_8;
wire T_1792_9;
wire T_1792_10;
wire T_1792_11;
wire T_1792_12;
wire T_1792_13;
wire T_1792_14;
wire T_1792_15;
wire T_1792_16;
wire T_1792_17;
wire T_1792_18;
wire T_1792_19;
wire T_1792_20;
wire T_1792_21;
wire T_1792_22;
wire T_1792_23;
wire T_1792_24;
wire T_1792_25;
wire T_1792_26;
wire T_1792_27;
wire T_1792_28;
wire T_1792_29;
wire T_1792_30;
wire T_1792_31;
wire T_1792_32;
wire T_1792_33;
wire T_1792_34;
wire T_1792_35;
wire T_1792_36;
wire T_1792_37;
wire T_1792_38;
wire T_1792_39;
wire T_1792_40;
wire T_1792_41;
wire T_1792_42;
wire T_1792_43;
wire T_1792_44;
wire T_1792_45;
wire T_1792_46;
wire T_1792_47;
wire T_1792_48;
wire T_1792_49;
wire T_1797_0;
wire T_1797_1;
wire T_1797_2;
wire T_1797_3;
wire T_1797_4;
wire T_1797_5;
wire T_1797_6;
wire T_1797_7;
wire T_1797_8;
wire T_1797_9;
wire T_1797_10;
wire T_1797_11;
wire T_1797_12;
wire T_1797_13;
wire T_1797_14;
wire T_1797_15;
wire T_1797_16;
wire T_1797_17;
wire T_1797_18;
wire T_1797_19;
wire T_1797_20;
wire T_1797_21;
wire T_1797_22;
wire T_1797_23;
wire T_1797_24;
wire T_1797_25;
wire T_1797_26;
wire T_1797_27;
wire T_1797_28;
wire T_1797_29;
wire T_1797_30;
wire T_1797_31;
wire T_1797_32;
wire T_1797_33;
wire T_1797_34;
wire T_1797_35;
wire T_1797_36;
wire T_1797_37;
wire T_1797_38;
wire T_1797_39;
wire T_1797_40;
wire T_1797_41;
wire T_1797_42;
wire T_1797_43;
wire T_1797_44;
wire T_1797_45;
wire T_1797_46;
wire T_1797_47;
wire T_1797_48;
wire T_1797_49;
wire T_2462;
wire T_2463;
wire T_2464;
wire T_2465;
wire [7:0] T_2469;
wire [7:0] T_2473;
wire [7:0] T_2477;
wire [7:0] T_2481;
wire [15:0] T_2482;
wire [15:0] T_2483;
wire [31:0] T_2484;
wire [31:0] T_2496;
wire T_2498;
wire T_2504;
wire [31:0] T_2505;
wire [31:0] T_2520;
wire T_2544;
wire [31:0] T_2560;
wire T_2584;
wire [31:0] GEN_6;
wire T_2624;
wire [31:0] T_2640;
wire T_2664;
wire [31:0] GEN_7;
wire T_2704;
wire [31:0] T_2720;
wire T_2744;
wire [31:0] GEN_8;
wire T_2784;
wire [31:0] T_2800;
wire T_2824;
wire [31:0] T_2840;
wire T_2864;
wire [31:0] T_2880;
wire T_2904;
wire [31:0] GEN_9;
wire T_2944;
wire [31:0] T_2960;
wire T_2984;
wire [31:0] GEN_10;
wire T_3024;
wire [31:0] T_3040;
wire T_3064;
wire [31:0] T_3080;
wire T_3104;
wire [31:0] GEN_11;
wire T_3144;
wire [31:0] T_3160;
wire T_3184;
wire [31:0] T_3200;
wire T_3224;
wire [31:0] GEN_12;
wire T_3264;
wire [31:0] GEN_13;
wire T_3304;
wire [31:0] GEN_14;
wire T_3344;
wire [31:0] T_3360;
wire T_3384;
wire [31:0] T_3400;
wire T_3424;
wire [31:0] GEN_15;
wire T_3464;
wire [31:0] T_3480;
wire T_3504;
wire [31:0] T_3520;
wire T_3544;
wire [31:0] T_3560;
wire T_3584;
wire [31:0] T_3600;
wire T_3624;
wire [31:0] GEN_16;
wire T_3664;
wire [31:0] T_3680;
wire T_3704;
wire [31:0] T_3720;
wire [3:0] T_3732;
wire [3:0] T_3736;
wire T_3738;
wire T_3744;
wire [3:0] T_3745;
wire [3:0] T_3760;
wire T_3784;
wire [31:0] GEN_17;
wire T_3824;
wire [31:0] T_3840;
wire T_3864;
wire [31:0] T_3880;
wire T_3904;
wire [31:0] T_3920;
wire T_3944;
wire [31:0] T_3960;
wire T_3984;
wire [31:0] GEN_18;
wire T_4024;
wire [31:0] GEN_19;
wire T_4064;
wire [31:0] T_4080;
wire [15:0] T_4092;
wire [15:0] T_4096;
wire T_4098;
wire T_4104;
wire [15:0] T_4105;
wire [15:0] T_4120;
wire T_4144;
wire [31:0] T_4160;
wire T_4184;
wire [31:0] T_4200;
wire T_4224;
wire [31:0] GEN_20;
wire T_4264;
wire [31:0] T_4280;
wire T_4304;
wire [15:0] T_4320;
wire T_4344;
wire [31:0] T_4360;
wire T_4384;
wire [31:0] GEN_21;
wire T_4424;
wire [31:0] T_4440;
wire T_4464;
wire [31:0] T_4480;
wire T_4486;
wire T_4488;
wire T_4493;
wire T_4495;
wire T_4497;
wire T_4499;
wire T_4501;
wire T_4503;
wire T_4508;
wire T_4510;
wire T_4512;
wire T_4514;
wire T_4516;
wire T_4518;
wire T_4541;
wire T_4543;
wire T_4548;
wire T_4550;
wire T_4552;
wire T_4554;
wire T_4556;
wire T_4558;
wire T_4563;
wire T_4565;
wire T_4567;
wire T_4569;
wire T_4571;
wire T_4573;
wire T_4596;
wire T_4598;
wire T_4600;
wire T_4602;
wire T_4604;
wire T_4606;
wire T_4608;
wire T_4610;
wire T_4612;
wire T_4614;
wire T_4616;
wire T_4618;
wire T_4620;
wire T_4622;
wire T_4624;
wire T_4626;
wire T_4628;
wire T_4630;
wire T_4632;
wire T_4634;
wire T_4636;
wire T_4638;
wire T_4640;
wire T_4642;
wire T_4644;
wire T_4646;
wire T_4648;
wire T_4650;
wire T_4652;
wire T_4654;
wire T_4656;
wire T_4658;
wire T_4708;
wire T_4710;
wire T_4712;
wire T_4714;
wire T_4716;
wire T_4718;
wire T_4720;
wire T_4722;
wire T_4724;
wire T_4726;
wire T_4728;
wire T_4730;
wire T_4732;
wire T_4734;
wire T_4736;
wire T_4738;
wire T_4740;
wire T_4742;
wire T_4744;
wire T_4746;
wire T_4748;
wire T_4750;
wire T_4752;
wire T_4754;
wire T_4756;
wire T_4758;
wire T_4760;
wire T_4762;
wire T_4764;
wire T_4766;
wire T_4768;
wire T_4770;
wire T_4772;
wire T_4774;
wire T_4776;
wire T_4778;
wire T_4780;
wire T_4782;
wire T_4784;
wire T_4786;
wire T_5050_0;
wire T_5050_1;
wire T_5050_2;
wire T_5050_3;
wire T_5050_4;
wire T_5050_5;
wire T_5050_6;
wire T_5050_7;
wire T_5050_8;
wire T_5050_9;
wire T_5050_10;
wire T_5050_11;
wire T_5050_12;
wire T_5050_13;
wire T_5050_14;
wire T_5050_15;
wire T_5050_16;
wire T_5050_17;
wire T_5050_18;
wire T_5050_19;
wire T_5050_20;
wire T_5050_21;
wire T_5050_22;
wire T_5050_23;
wire T_5050_24;
wire T_5050_25;
wire T_5050_26;
wire T_5050_27;
wire T_5050_28;
wire T_5050_29;
wire T_5050_30;
wire T_5050_31;
wire T_5050_32;
wire T_5050_33;
wire T_5050_34;
wire T_5050_35;
wire T_5050_36;
wire T_5050_37;
wire T_5050_38;
wire T_5050_39;
wire T_5050_40;
wire T_5050_41;
wire T_5050_42;
wire T_5050_43;
wire T_5050_44;
wire T_5050_45;
wire T_5050_46;
wire T_5050_47;
wire T_5050_48;
wire T_5050_49;
wire T_5050_50;
wire T_5050_51;
wire T_5050_52;
wire T_5050_53;
wire T_5050_54;
wire T_5050_55;
wire T_5050_56;
wire T_5050_57;
wire T_5050_58;
wire T_5050_59;
wire T_5050_60;
wire T_5050_61;
wire T_5050_62;
wire T_5050_63;
wire T_5050_64;
wire T_5050_65;
wire T_5050_66;
wire T_5050_67;
wire T_5050_68;
wire T_5050_69;
wire T_5050_70;
wire T_5050_71;
wire T_5050_72;
wire T_5050_73;
wire T_5050_74;
wire T_5050_75;
wire T_5050_76;
wire T_5050_77;
wire T_5050_78;
wire T_5050_79;
wire T_5050_80;
wire T_5050_81;
wire T_5050_82;
wire T_5050_83;
wire T_5050_84;
wire T_5050_85;
wire T_5050_86;
wire T_5050_87;
wire T_5050_88;
wire T_5050_89;
wire T_5050_90;
wire T_5050_91;
wire T_5050_92;
wire T_5050_93;
wire T_5050_94;
wire T_5050_95;
wire T_5050_96;
wire T_5050_97;
wire T_5050_98;
wire T_5050_99;
wire T_5050_100;
wire T_5050_101;
wire T_5050_102;
wire T_5050_103;
wire T_5050_104;
wire T_5050_105;
wire T_5050_106;
wire T_5050_107;
wire T_5050_108;
wire T_5050_109;
wire T_5050_110;
wire T_5050_111;
wire T_5050_112;
wire T_5050_113;
wire T_5050_114;
wire T_5050_115;
wire T_5050_116;
wire T_5050_117;
wire T_5050_118;
wire T_5050_119;
wire T_5050_120;
wire T_5050_121;
wire T_5050_122;
wire T_5050_123;
wire T_5050_124;
wire T_5050_125;
wire T_5050_126;
wire T_5050_127;
wire T_5184;
wire T_5191;
wire T_5195;
wire T_5199;
wire T_5206;
wire T_5210;
wire T_5214;
wire T_5239;
wire T_5246;
wire T_5250;
wire T_5254;
wire T_5261;
wire T_5265;
wire T_5269;
wire T_5294;
wire T_5298;
wire T_5302;
wire T_5306;
wire T_5310;
wire T_5314;
wire T_5318;
wire T_5322;
wire T_5326;
wire T_5330;
wire T_5334;
wire T_5338;
wire T_5342;
wire T_5346;
wire T_5350;
wire T_5354;
wire T_5406;
wire T_5410;
wire T_5414;
wire T_5418;
wire T_5422;
wire T_5426;
wire T_5430;
wire T_5434;
wire T_5438;
wire T_5442;
wire T_5446;
wire T_5450;
wire T_5454;
wire T_5458;
wire T_5462;
wire T_5466;
wire T_5470;
wire T_5474;
wire T_5478;
wire T_5482;
wire T_5746_0;
wire T_5746_1;
wire T_5746_2;
wire T_5746_3;
wire T_5746_4;
wire T_5746_5;
wire T_5746_6;
wire T_5746_7;
wire T_5746_8;
wire T_5746_9;
wire T_5746_10;
wire T_5746_11;
wire T_5746_12;
wire T_5746_13;
wire T_5746_14;
wire T_5746_15;
wire T_5746_16;
wire T_5746_17;
wire T_5746_18;
wire T_5746_19;
wire T_5746_20;
wire T_5746_21;
wire T_5746_22;
wire T_5746_23;
wire T_5746_24;
wire T_5746_25;
wire T_5746_26;
wire T_5746_27;
wire T_5746_28;
wire T_5746_29;
wire T_5746_30;
wire T_5746_31;
wire T_5746_32;
wire T_5746_33;
wire T_5746_34;
wire T_5746_35;
wire T_5746_36;
wire T_5746_37;
wire T_5746_38;
wire T_5746_39;
wire T_5746_40;
wire T_5746_41;
wire T_5746_42;
wire T_5746_43;
wire T_5746_44;
wire T_5746_45;
wire T_5746_46;
wire T_5746_47;
wire T_5746_48;
wire T_5746_49;
wire T_5746_50;
wire T_5746_51;
wire T_5746_52;
wire T_5746_53;
wire T_5746_54;
wire T_5746_55;
wire T_5746_56;
wire T_5746_57;
wire T_5746_58;
wire T_5746_59;
wire T_5746_60;
wire T_5746_61;
wire T_5746_62;
wire T_5746_63;
wire T_5746_64;
wire T_5746_65;
wire T_5746_66;
wire T_5746_67;
wire T_5746_68;
wire T_5746_69;
wire T_5746_70;
wire T_5746_71;
wire T_5746_72;
wire T_5746_73;
wire T_5746_74;
wire T_5746_75;
wire T_5746_76;
wire T_5746_77;
wire T_5746_78;
wire T_5746_79;
wire T_5746_80;
wire T_5746_81;
wire T_5746_82;
wire T_5746_83;
wire T_5746_84;
wire T_5746_85;
wire T_5746_86;
wire T_5746_87;
wire T_5746_88;
wire T_5746_89;
wire T_5746_90;
wire T_5746_91;
wire T_5746_92;
wire T_5746_93;
wire T_5746_94;
wire T_5746_95;
wire T_5746_96;
wire T_5746_97;
wire T_5746_98;
wire T_5746_99;
wire T_5746_100;
wire T_5746_101;
wire T_5746_102;
wire T_5746_103;
wire T_5746_104;
wire T_5746_105;
wire T_5746_106;
wire T_5746_107;
wire T_5746_108;
wire T_5746_109;
wire T_5746_110;
wire T_5746_111;
wire T_5746_112;
wire T_5746_113;
wire T_5746_114;
wire T_5746_115;
wire T_5746_116;
wire T_5746_117;
wire T_5746_118;
wire T_5746_119;
wire T_5746_120;
wire T_5746_121;
wire T_5746_122;
wire T_5746_123;
wire T_5746_124;
wire T_5746_125;
wire T_5746_126;
wire T_5746_127;
wire T_5878;
wire T_5880;
wire T_5885;
wire T_5887;
wire T_5889;
wire T_5891;
wire T_5893;
wire T_5895;
wire T_5900;
wire T_5902;
wire T_5904;
wire T_5906;
wire T_5908;
wire T_5910;
wire T_5933;
wire T_5935;
wire T_5940;
wire T_5942;
wire T_5944;
wire T_5946;
wire T_5948;
wire T_5950;
wire T_5955;
wire T_5957;
wire T_5959;
wire T_5961;
wire T_5963;
wire T_5965;
wire T_5988;
wire T_5990;
wire T_5992;
wire T_5994;
wire T_5996;
wire T_5998;
wire T_6000;
wire T_6002;
wire T_6004;
wire T_6006;
wire T_6008;
wire T_6010;
wire T_6012;
wire T_6014;
wire T_6016;
wire T_6018;
wire T_6020;
wire T_6022;
wire T_6024;
wire T_6026;
wire T_6028;
wire T_6030;
wire T_6032;
wire T_6034;
wire T_6036;
wire T_6038;
wire T_6040;
wire T_6042;
wire T_6044;
wire T_6046;
wire T_6048;
wire T_6050;
wire T_6100;
wire T_6102;
wire T_6104;
wire T_6106;
wire T_6108;
wire T_6110;
wire T_6112;
wire T_6114;
wire T_6116;
wire T_6118;
wire T_6120;
wire T_6122;
wire T_6124;
wire T_6126;
wire T_6128;
wire T_6130;
wire T_6132;
wire T_6134;
wire T_6136;
wire T_6138;
wire T_6140;
wire T_6142;
wire T_6144;
wire T_6146;
wire T_6148;
wire T_6150;
wire T_6152;
wire T_6154;
wire T_6156;
wire T_6158;
wire T_6160;
wire T_6162;
wire T_6164;
wire T_6166;
wire T_6168;
wire T_6170;
wire T_6172;
wire T_6174;
wire T_6176;
wire T_6178;
wire T_6442_0;
wire T_6442_1;
wire T_6442_2;
wire T_6442_3;
wire T_6442_4;
wire T_6442_5;
wire T_6442_6;
wire T_6442_7;
wire T_6442_8;
wire T_6442_9;
wire T_6442_10;
wire T_6442_11;
wire T_6442_12;
wire T_6442_13;
wire T_6442_14;
wire T_6442_15;
wire T_6442_16;
wire T_6442_17;
wire T_6442_18;
wire T_6442_19;
wire T_6442_20;
wire T_6442_21;
wire T_6442_22;
wire T_6442_23;
wire T_6442_24;
wire T_6442_25;
wire T_6442_26;
wire T_6442_27;
wire T_6442_28;
wire T_6442_29;
wire T_6442_30;
wire T_6442_31;
wire T_6442_32;
wire T_6442_33;
wire T_6442_34;
wire T_6442_35;
wire T_6442_36;
wire T_6442_37;
wire T_6442_38;
wire T_6442_39;
wire T_6442_40;
wire T_6442_41;
wire T_6442_42;
wire T_6442_43;
wire T_6442_44;
wire T_6442_45;
wire T_6442_46;
wire T_6442_47;
wire T_6442_48;
wire T_6442_49;
wire T_6442_50;
wire T_6442_51;
wire T_6442_52;
wire T_6442_53;
wire T_6442_54;
wire T_6442_55;
wire T_6442_56;
wire T_6442_57;
wire T_6442_58;
wire T_6442_59;
wire T_6442_60;
wire T_6442_61;
wire T_6442_62;
wire T_6442_63;
wire T_6442_64;
wire T_6442_65;
wire T_6442_66;
wire T_6442_67;
wire T_6442_68;
wire T_6442_69;
wire T_6442_70;
wire T_6442_71;
wire T_6442_72;
wire T_6442_73;
wire T_6442_74;
wire T_6442_75;
wire T_6442_76;
wire T_6442_77;
wire T_6442_78;
wire T_6442_79;
wire T_6442_80;
wire T_6442_81;
wire T_6442_82;
wire T_6442_83;
wire T_6442_84;
wire T_6442_85;
wire T_6442_86;
wire T_6442_87;
wire T_6442_88;
wire T_6442_89;
wire T_6442_90;
wire T_6442_91;
wire T_6442_92;
wire T_6442_93;
wire T_6442_94;
wire T_6442_95;
wire T_6442_96;
wire T_6442_97;
wire T_6442_98;
wire T_6442_99;
wire T_6442_100;
wire T_6442_101;
wire T_6442_102;
wire T_6442_103;
wire T_6442_104;
wire T_6442_105;
wire T_6442_106;
wire T_6442_107;
wire T_6442_108;
wire T_6442_109;
wire T_6442_110;
wire T_6442_111;
wire T_6442_112;
wire T_6442_113;
wire T_6442_114;
wire T_6442_115;
wire T_6442_116;
wire T_6442_117;
wire T_6442_118;
wire T_6442_119;
wire T_6442_120;
wire T_6442_121;
wire T_6442_122;
wire T_6442_123;
wire T_6442_124;
wire T_6442_125;
wire T_6442_126;
wire T_6442_127;
wire T_6576;
wire T_6583;
wire T_6587;
wire T_6591;
wire T_6598;
wire T_6602;
wire T_6606;
wire T_6631;
wire T_6638;
wire T_6642;
wire T_6646;
wire T_6653;
wire T_6657;
wire T_6661;
wire T_6686;
wire T_6690;
wire T_6694;
wire T_6698;
wire T_6702;
wire T_6706;
wire T_6710;
wire T_6714;
wire T_6718;
wire T_6722;
wire T_6726;
wire T_6730;
wire T_6734;
wire T_6738;
wire T_6742;
wire T_6746;
wire T_6798;
wire T_6802;
wire T_6806;
wire T_6810;
wire T_6814;
wire T_6818;
wire T_6822;
wire T_6826;
wire T_6830;
wire T_6834;
wire T_6838;
wire T_6842;
wire T_6846;
wire T_6850;
wire T_6854;
wire T_6858;
wire T_6862;
wire T_6866;
wire T_6870;
wire T_6874;
wire T_7138_0;
wire T_7138_1;
wire T_7138_2;
wire T_7138_3;
wire T_7138_4;
wire T_7138_5;
wire T_7138_6;
wire T_7138_7;
wire T_7138_8;
wire T_7138_9;
wire T_7138_10;
wire T_7138_11;
wire T_7138_12;
wire T_7138_13;
wire T_7138_14;
wire T_7138_15;
wire T_7138_16;
wire T_7138_17;
wire T_7138_18;
wire T_7138_19;
wire T_7138_20;
wire T_7138_21;
wire T_7138_22;
wire T_7138_23;
wire T_7138_24;
wire T_7138_25;
wire T_7138_26;
wire T_7138_27;
wire T_7138_28;
wire T_7138_29;
wire T_7138_30;
wire T_7138_31;
wire T_7138_32;
wire T_7138_33;
wire T_7138_34;
wire T_7138_35;
wire T_7138_36;
wire T_7138_37;
wire T_7138_38;
wire T_7138_39;
wire T_7138_40;
wire T_7138_41;
wire T_7138_42;
wire T_7138_43;
wire T_7138_44;
wire T_7138_45;
wire T_7138_46;
wire T_7138_47;
wire T_7138_48;
wire T_7138_49;
wire T_7138_50;
wire T_7138_51;
wire T_7138_52;
wire T_7138_53;
wire T_7138_54;
wire T_7138_55;
wire T_7138_56;
wire T_7138_57;
wire T_7138_58;
wire T_7138_59;
wire T_7138_60;
wire T_7138_61;
wire T_7138_62;
wire T_7138_63;
wire T_7138_64;
wire T_7138_65;
wire T_7138_66;
wire T_7138_67;
wire T_7138_68;
wire T_7138_69;
wire T_7138_70;
wire T_7138_71;
wire T_7138_72;
wire T_7138_73;
wire T_7138_74;
wire T_7138_75;
wire T_7138_76;
wire T_7138_77;
wire T_7138_78;
wire T_7138_79;
wire T_7138_80;
wire T_7138_81;
wire T_7138_82;
wire T_7138_83;
wire T_7138_84;
wire T_7138_85;
wire T_7138_86;
wire T_7138_87;
wire T_7138_88;
wire T_7138_89;
wire T_7138_90;
wire T_7138_91;
wire T_7138_92;
wire T_7138_93;
wire T_7138_94;
wire T_7138_95;
wire T_7138_96;
wire T_7138_97;
wire T_7138_98;
wire T_7138_99;
wire T_7138_100;
wire T_7138_101;
wire T_7138_102;
wire T_7138_103;
wire T_7138_104;
wire T_7138_105;
wire T_7138_106;
wire T_7138_107;
wire T_7138_108;
wire T_7138_109;
wire T_7138_110;
wire T_7138_111;
wire T_7138_112;
wire T_7138_113;
wire T_7138_114;
wire T_7138_115;
wire T_7138_116;
wire T_7138_117;
wire T_7138_118;
wire T_7138_119;
wire T_7138_120;
wire T_7138_121;
wire T_7138_122;
wire T_7138_123;
wire T_7138_124;
wire T_7138_125;
wire T_7138_126;
wire T_7138_127;
wire T_7269;
wire T_7270;
wire T_7271;
wire T_7272;
wire T_7273;
wire T_7274;
wire T_7275;
wire [1:0] T_7279;
wire [2:0] T_7280;
wire [1:0] T_7281;
wire [1:0] T_7282;
wire [3:0] T_7283;
wire [6:0] T_7284;
wire T_7285;
wire T_7286;
wire T_7287;
wire T_7288;
wire T_7289;
wire T_7290;
wire T_7291;
wire [1:0] T_7295;
wire [2:0] T_7296;
wire [1:0] T_7297;
wire [1:0] T_7298;
wire [3:0] T_7299;
wire [6:0] T_7300;
wire GEN_0;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire GEN_49;
wire GEN_50;
wire GEN_51;
wire GEN_52;
wire GEN_53;
wire GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire GEN_62;
wire GEN_63;
wire GEN_64;
wire GEN_65;
wire GEN_66;
wire GEN_67;
wire GEN_68;
wire GEN_69;
wire GEN_70;
wire GEN_71;
wire GEN_72;
wire GEN_73;
wire GEN_74;
wire GEN_75;
wire GEN_76;
wire GEN_77;
wire GEN_78;
wire GEN_79;
wire GEN_80;
wire GEN_81;
wire GEN_82;
wire GEN_83;
wire GEN_84;
wire GEN_85;
wire GEN_86;
wire GEN_87;
wire GEN_88;
wire GEN_89;
wire GEN_90;
wire GEN_91;
wire GEN_92;
wire GEN_93;
wire GEN_94;
wire GEN_95;
wire GEN_96;
wire GEN_97;
wire GEN_98;
wire GEN_99;
wire GEN_100;
wire GEN_101;
wire GEN_102;
wire GEN_103;
wire GEN_104;
wire GEN_105;
wire GEN_106;
wire GEN_107;
wire GEN_108;
wire GEN_109;
wire GEN_110;
wire GEN_111;
wire GEN_112;
wire GEN_113;
wire GEN_114;
wire GEN_115;
wire GEN_116;
wire GEN_117;
wire GEN_118;
wire GEN_119;
wire GEN_120;
wire GEN_121;
wire GEN_122;
wire GEN_123;
wire GEN_124;
wire GEN_125;
wire GEN_126;
wire GEN_127;
wire GEN_128;
wire GEN_129;
wire GEN_130;
wire GEN_131;
wire GEN_132;
wire GEN_133;
wire GEN_134;
wire GEN_135;
wire GEN_136;
wire GEN_137;
wire GEN_138;
wire GEN_139;
wire GEN_140;
wire GEN_141;
wire GEN_142;
wire GEN_143;
wire GEN_144;
wire GEN_145;
wire GEN_146;
wire GEN_147;
wire GEN_148;
wire GEN_1;
wire GEN_149;
wire GEN_150;
wire GEN_151;
wire GEN_152;
wire GEN_153;
wire GEN_154;
wire GEN_155;
wire GEN_156;
wire GEN_157;
wire GEN_158;
wire GEN_159;
wire GEN_160;
wire GEN_161;
wire GEN_162;
wire GEN_163;
wire GEN_164;
wire GEN_165;
wire GEN_166;
wire GEN_167;
wire GEN_168;
wire GEN_169;
wire GEN_170;
wire GEN_171;
wire GEN_172;
wire GEN_173;
wire GEN_174;
wire GEN_175;
wire GEN_176;
wire GEN_177;
wire GEN_178;
wire GEN_179;
wire GEN_180;
wire GEN_181;
wire GEN_182;
wire GEN_183;
wire GEN_184;
wire GEN_185;
wire GEN_186;
wire GEN_187;
wire GEN_188;
wire GEN_189;
wire GEN_190;
wire GEN_191;
wire GEN_192;
wire GEN_193;
wire GEN_194;
wire GEN_195;
wire GEN_196;
wire GEN_197;
wire GEN_198;
wire GEN_199;
wire GEN_200;
wire GEN_201;
wire GEN_202;
wire GEN_203;
wire GEN_204;
wire GEN_205;
wire GEN_206;
wire GEN_207;
wire GEN_208;
wire GEN_209;
wire GEN_210;
wire GEN_211;
wire GEN_212;
wire GEN_213;
wire GEN_214;
wire GEN_215;
wire GEN_216;
wire GEN_217;
wire GEN_218;
wire GEN_219;
wire GEN_220;
wire GEN_221;
wire GEN_222;
wire GEN_223;
wire GEN_224;
wire GEN_225;
wire GEN_226;
wire GEN_227;
wire GEN_228;
wire GEN_229;
wire GEN_230;
wire GEN_231;
wire GEN_232;
wire GEN_233;
wire GEN_234;
wire GEN_235;
wire GEN_236;
wire GEN_237;
wire GEN_238;
wire GEN_239;
wire GEN_240;
wire GEN_241;
wire GEN_242;
wire GEN_243;
wire GEN_244;
wire GEN_245;
wire GEN_246;
wire GEN_247;
wire GEN_248;
wire GEN_249;
wire GEN_250;
wire GEN_251;
wire GEN_252;
wire GEN_253;
wire GEN_254;
wire GEN_255;
wire GEN_256;
wire GEN_257;
wire GEN_258;
wire GEN_259;
wire GEN_260;
wire GEN_261;
wire GEN_262;
wire GEN_263;
wire GEN_264;
wire GEN_265;
wire GEN_266;
wire GEN_267;
wire GEN_268;
wire GEN_269;
wire GEN_270;
wire GEN_271;
wire GEN_272;
wire GEN_273;
wire GEN_274;
wire GEN_275;
wire T_7303;
wire GEN_2;
wire GEN_276;
wire GEN_277;
wire GEN_278;
wire GEN_279;
wire GEN_280;
wire GEN_281;
wire GEN_282;
wire GEN_283;
wire GEN_284;
wire GEN_285;
wire GEN_286;
wire GEN_287;
wire GEN_288;
wire GEN_289;
wire GEN_290;
wire GEN_291;
wire GEN_292;
wire GEN_293;
wire GEN_294;
wire GEN_295;
wire GEN_296;
wire GEN_297;
wire GEN_298;
wire GEN_299;
wire GEN_300;
wire GEN_301;
wire GEN_302;
wire GEN_303;
wire GEN_304;
wire GEN_305;
wire GEN_306;
wire GEN_307;
wire GEN_308;
wire GEN_309;
wire GEN_310;
wire GEN_311;
wire GEN_312;
wire GEN_313;
wire GEN_314;
wire GEN_315;
wire GEN_316;
wire GEN_317;
wire GEN_318;
wire GEN_319;
wire GEN_320;
wire GEN_321;
wire GEN_322;
wire GEN_323;
wire GEN_324;
wire GEN_325;
wire GEN_326;
wire GEN_327;
wire GEN_328;
wire GEN_329;
wire GEN_330;
wire GEN_331;
wire GEN_332;
wire GEN_333;
wire GEN_334;
wire GEN_335;
wire GEN_336;
wire GEN_337;
wire GEN_338;
wire GEN_339;
wire GEN_340;
wire GEN_341;
wire GEN_342;
wire GEN_343;
wire GEN_344;
wire GEN_345;
wire GEN_346;
wire GEN_347;
wire GEN_348;
wire GEN_349;
wire GEN_350;
wire GEN_351;
wire GEN_352;
wire GEN_353;
wire GEN_354;
wire GEN_355;
wire GEN_356;
wire GEN_357;
wire GEN_358;
wire GEN_359;
wire GEN_360;
wire GEN_361;
wire GEN_362;
wire GEN_363;
wire GEN_364;
wire GEN_365;
wire GEN_366;
wire GEN_367;
wire GEN_368;
wire GEN_369;
wire GEN_370;
wire GEN_371;
wire GEN_372;
wire GEN_373;
wire GEN_374;
wire GEN_375;
wire GEN_376;
wire GEN_377;
wire GEN_378;
wire GEN_379;
wire GEN_380;
wire GEN_381;
wire GEN_382;
wire GEN_383;
wire GEN_384;
wire GEN_385;
wire GEN_386;
wire GEN_387;
wire GEN_388;
wire GEN_389;
wire GEN_390;
wire GEN_391;
wire GEN_392;
wire GEN_393;
wire GEN_394;
wire GEN_395;
wire GEN_396;
wire GEN_397;
wire GEN_398;
wire GEN_399;
wire GEN_400;
wire GEN_401;
wire GEN_402;
wire GEN_3;
wire GEN_403;
wire GEN_404;
wire GEN_405;
wire GEN_406;
wire GEN_407;
wire GEN_408;
wire GEN_409;
wire GEN_410;
wire GEN_411;
wire GEN_412;
wire GEN_413;
wire GEN_414;
wire GEN_415;
wire GEN_416;
wire GEN_417;
wire GEN_418;
wire GEN_419;
wire GEN_420;
wire GEN_421;
wire GEN_422;
wire GEN_423;
wire GEN_424;
wire GEN_425;
wire GEN_426;
wire GEN_427;
wire GEN_428;
wire GEN_429;
wire GEN_430;
wire GEN_431;
wire GEN_432;
wire GEN_433;
wire GEN_434;
wire GEN_435;
wire GEN_436;
wire GEN_437;
wire GEN_438;
wire GEN_439;
wire GEN_440;
wire GEN_441;
wire GEN_442;
wire GEN_443;
wire GEN_444;
wire GEN_445;
wire GEN_446;
wire GEN_447;
wire GEN_448;
wire GEN_449;
wire GEN_450;
wire GEN_451;
wire GEN_452;
wire GEN_453;
wire GEN_454;
wire GEN_455;
wire GEN_456;
wire GEN_457;
wire GEN_458;
wire GEN_459;
wire GEN_460;
wire GEN_461;
wire GEN_462;
wire GEN_463;
wire GEN_464;
wire GEN_465;
wire GEN_466;
wire GEN_467;
wire GEN_468;
wire GEN_469;
wire GEN_470;
wire GEN_471;
wire GEN_472;
wire GEN_473;
wire GEN_474;
wire GEN_475;
wire GEN_476;
wire GEN_477;
wire GEN_478;
wire GEN_479;
wire GEN_480;
wire GEN_481;
wire GEN_482;
wire GEN_483;
wire GEN_484;
wire GEN_485;
wire GEN_486;
wire GEN_487;
wire GEN_488;
wire GEN_489;
wire GEN_490;
wire GEN_491;
wire GEN_492;
wire GEN_493;
wire GEN_494;
wire GEN_495;
wire GEN_496;
wire GEN_497;
wire GEN_498;
wire GEN_499;
wire GEN_500;
wire GEN_501;
wire GEN_502;
wire GEN_503;
wire GEN_504;
wire GEN_505;
wire GEN_506;
wire GEN_507;
wire GEN_508;
wire GEN_509;
wire GEN_510;
wire GEN_511;
wire GEN_512;
wire GEN_513;
wire GEN_514;
wire GEN_515;
wire GEN_516;
wire GEN_517;
wire GEN_518;
wire GEN_519;
wire GEN_520;
wire GEN_521;
wire GEN_522;
wire GEN_523;
wire GEN_524;
wire GEN_525;
wire GEN_526;
wire GEN_527;
wire GEN_528;
wire GEN_529;
wire T_7306;
wire T_7307;
wire T_7308;
wire T_7309;
wire T_7310;
wire [127:0] T_7312;
wire [1:0] T_7313;
wire [1:0] T_7314;
wire [3:0] T_7315;
wire [1:0] T_7316;
wire [1:0] T_7317;
wire [3:0] T_7318;
wire [7:0] T_7319;
wire [1:0] T_7320;
wire [3:0] T_7322;
wire [7:0] T_7326;
wire [15:0] T_7327;
wire [1:0] T_7328;
wire [1:0] T_7329;
wire [3:0] T_7330;
wire [1:0] T_7331;
wire [1:0] T_7332;
wire [3:0] T_7333;
wire [7:0] T_7334;
wire [1:0] T_7335;
wire [3:0] T_7337;
wire [7:0] T_7341;
wire [15:0] T_7342;
wire [31:0] T_7343;
wire [1:0] T_7344;
wire [1:0] T_7345;
wire [3:0] T_7346;
wire [1:0] T_7347;
wire [1:0] T_7348;
wire [3:0] T_7349;
wire [7:0] T_7350;
wire [1:0] T_7351;
wire [1:0] T_7352;
wire [3:0] T_7353;
wire [1:0] T_7354;
wire [1:0] T_7355;
wire [3:0] T_7356;
wire [7:0] T_7357;
wire [15:0] T_7358;
wire [31:0] T_7374;
wire [63:0] T_7375;
wire [1:0] T_7376;
wire [1:0] T_7377;
wire [3:0] T_7378;
wire [1:0] T_7379;
wire [1:0] T_7380;
wire [3:0] T_7381;
wire [7:0] T_7382;
wire [1:0] T_7383;
wire [1:0] T_7384;
wire [3:0] T_7385;
wire [1:0] T_7386;
wire [1:0] T_7387;
wire [3:0] T_7388;
wire [7:0] T_7389;
wire [15:0] T_7390;
wire [1:0] T_7391;
wire [1:0] T_7392;
wire [3:0] T_7393;
wire [7:0] T_7397;
wire [15:0] T_7405;
wire [31:0] T_7406;
wire [63:0] T_7438;
wire [127:0] T_7439;
wire [127:0] T_7440;
wire [127:0] T_7442;
wire [1:0] T_7443;
wire [1:0] T_7444;
wire [3:0] T_7445;
wire [1:0] T_7446;
wire [1:0] T_7447;
wire [3:0] T_7448;
wire [7:0] T_7449;
wire [1:0] T_7450;
wire [3:0] T_7452;
wire [7:0] T_7456;
wire [15:0] T_7457;
wire [1:0] T_7458;
wire [1:0] T_7459;
wire [3:0] T_7460;
wire [1:0] T_7461;
wire [1:0] T_7462;
wire [3:0] T_7463;
wire [7:0] T_7464;
wire [1:0] T_7465;
wire [3:0] T_7467;
wire [7:0] T_7471;
wire [15:0] T_7472;
wire [31:0] T_7473;
wire [1:0] T_7474;
wire [1:0] T_7475;
wire [3:0] T_7476;
wire [1:0] T_7477;
wire [1:0] T_7478;
wire [3:0] T_7479;
wire [7:0] T_7480;
wire [1:0] T_7481;
wire [1:0] T_7482;
wire [3:0] T_7483;
wire [1:0] T_7484;
wire [1:0] T_7485;
wire [3:0] T_7486;
wire [7:0] T_7487;
wire [15:0] T_7488;
wire [31:0] T_7504;
wire [63:0] T_7505;
wire [1:0] T_7506;
wire [1:0] T_7507;
wire [3:0] T_7508;
wire [1:0] T_7509;
wire [1:0] T_7510;
wire [3:0] T_7511;
wire [7:0] T_7512;
wire [1:0] T_7513;
wire [1:0] T_7514;
wire [3:0] T_7515;
wire [1:0] T_7516;
wire [1:0] T_7517;
wire [3:0] T_7518;
wire [7:0] T_7519;
wire [15:0] T_7520;
wire [1:0] T_7521;
wire [1:0] T_7522;
wire [3:0] T_7523;
wire [7:0] T_7527;
wire [15:0] T_7535;
wire [31:0] T_7536;
wire [63:0] T_7568;
wire [127:0] T_7569;
wire [127:0] T_7570;
wire T_7571;
wire T_7572;
wire T_7573;
wire T_7574;
wire T_7577;
wire T_7578;
wire T_7580;
wire T_7581;
wire T_7582;
wire T_7583;
wire T_7584;
wire T_7587;
wire T_7588;
wire T_7590;
wire T_7613;
wire T_7614;
wire T_7620;
wire T_7623;
wire T_7624;
wire T_7630;
wire T_7633;
wire T_7634;
wire T_7640;
wire T_7643;
wire T_7644;
wire T_7650;
wire T_7653;
wire T_7654;
wire T_7660;
wire T_7663;
wire T_7664;
wire T_7670;
wire T_7693;
wire T_7694;
wire T_7700;
wire T_7703;
wire T_7704;
wire T_7710;
wire T_7713;
wire T_7714;
wire T_7720;
wire T_7723;
wire T_7724;
wire T_7730;
wire T_7733;
wire T_7734;
wire T_7740;
wire T_7743;
wire T_7744;
wire T_7750;
wire T_7893;
wire T_7894;
wire T_7900;
wire T_7903;
wire T_7904;
wire T_7910;
wire T_7933;
wire T_7934;
wire T_7940;
wire T_7943;
wire T_7944;
wire T_7950;
wire T_7953;
wire T_7954;
wire T_7960;
wire T_7963;
wire T_7964;
wire T_7970;
wire T_7973;
wire T_7974;
wire T_7980;
wire T_7983;
wire T_7984;
wire T_7990;
wire T_8013;
wire T_8014;
wire T_8020;
wire T_8023;
wire T_8024;
wire T_8030;
wire T_8033;
wire T_8034;
wire T_8040;
wire T_8043;
wire T_8044;
wire T_8050;
wire T_8053;
wire T_8054;
wire T_8060;
wire T_8063;
wire T_8064;
wire T_8070;
wire T_8213;
wire T_8214;
wire T_8220;
wire T_8223;
wire T_8224;
wire T_8230;
wire T_8233;
wire T_8234;
wire T_8240;
wire T_8243;
wire T_8244;
wire T_8250;
wire T_8253;
wire T_8254;
wire T_8260;
wire T_8263;
wire T_8264;
wire T_8270;
wire T_8273;
wire T_8274;
wire T_8280;
wire T_8283;
wire T_8284;
wire T_8290;
wire T_8293;
wire T_8294;
wire T_8300;
wire T_8303;
wire T_8304;
wire T_8310;
wire T_8313;
wire T_8314;
wire T_8320;
wire T_8323;
wire T_8324;
wire T_8330;
wire T_8333;
wire T_8334;
wire T_8340;
wire T_8343;
wire T_8344;
wire T_8350;
wire T_8353;
wire T_8354;
wire T_8360;
wire T_8363;
wire T_8364;
wire T_8370;
wire T_8373;
wire T_8374;
wire T_8380;
wire T_8383;
wire T_8384;
wire T_8390;
wire T_8393;
wire T_8394;
wire T_8400;
wire T_8403;
wire T_8404;
wire T_8410;
wire T_8413;
wire T_8414;
wire T_8420;
wire T_8423;
wire T_8424;
wire T_8430;
wire T_8433;
wire T_8434;
wire T_8440;
wire T_8443;
wire T_8444;
wire T_8450;
wire T_8453;
wire T_8454;
wire T_8460;
wire T_8463;
wire T_8464;
wire T_8470;
wire T_8473;
wire T_8474;
wire T_8480;
wire T_8483;
wire T_8484;
wire T_8490;
wire T_8493;
wire T_8494;
wire T_8500;
wire T_8503;
wire T_8504;
wire T_8510;
wire T_8513;
wire T_8514;
wire T_8520;
wire T_8523;
wire T_8524;
wire T_8530;
wire T_8853;
wire T_8854;
wire T_8860;
wire T_8863;
wire T_8864;
wire T_8870;
wire T_8873;
wire T_8874;
wire T_8880;
wire T_8883;
wire T_8884;
wire T_8890;
wire T_8893;
wire T_8894;
wire T_8900;
wire T_8903;
wire T_8904;
wire T_8910;
wire T_8913;
wire T_8914;
wire T_8920;
wire T_8923;
wire T_8924;
wire T_8930;
wire T_8933;
wire T_8934;
wire T_8940;
wire T_8943;
wire T_8944;
wire T_8950;
wire T_8953;
wire T_8954;
wire T_8960;
wire T_8963;
wire T_8964;
wire T_8970;
wire T_8973;
wire T_8974;
wire T_8980;
wire T_8983;
wire T_8984;
wire T_8990;
wire T_8993;
wire T_8994;
wire T_9000;
wire T_9003;
wire T_9004;
wire T_9010;
wire T_9013;
wire T_9014;
wire T_9020;
wire T_9023;
wire T_9024;
wire T_9030;
wire T_9033;
wire T_9034;
wire T_9040;
wire T_9043;
wire T_9044;
wire T_9050;
wire T_9053;
wire T_9054;
wire T_9060;
wire T_9063;
wire T_9064;
wire T_9070;
wire T_9073;
wire T_9074;
wire T_9080;
wire T_9083;
wire T_9084;
wire T_9090;
wire T_9093;
wire T_9094;
wire T_9100;
wire T_9103;
wire T_9104;
wire T_9110;
wire T_9113;
wire T_9114;
wire T_9120;
wire T_9123;
wire T_9124;
wire T_9130;
wire T_9133;
wire T_9134;
wire T_9140;
wire T_9143;
wire T_9144;
wire T_9150;
wire T_9153;
wire T_9154;
wire T_9160;
wire T_9163;
wire T_9164;
wire T_9170;
wire T_9173;
wire T_9174;
wire T_9180;
wire T_9183;
wire T_9184;
wire T_9190;
wire T_9193;
wire T_9194;
wire T_9200;
wire T_9203;
wire T_9204;
wire T_9210;
wire T_9213;
wire T_9214;
wire T_9220;
wire T_9223;
wire T_9224;
wire T_9230;
wire T_9233;
wire T_9234;
wire T_9240;
wire T_9243;
wire T_9244;
wire T_9250;
wire T_10462_0;
wire T_10462_1;
wire T_10462_2;
wire T_10462_3;
wire T_10462_4;
wire T_10462_5;
wire T_10462_6;
wire T_10462_7;
wire T_10462_8;
wire T_10462_9;
wire T_10462_10;
wire T_10462_11;
wire T_10462_12;
wire T_10462_13;
wire T_10462_14;
wire T_10462_15;
wire T_10462_16;
wire T_10462_17;
wire T_10462_18;
wire T_10462_19;
wire T_10462_20;
wire T_10462_21;
wire T_10462_22;
wire T_10462_23;
wire T_10462_24;
wire T_10462_25;
wire T_10462_26;
wire T_10462_27;
wire T_10462_28;
wire T_10462_29;
wire T_10462_30;
wire T_10462_31;
wire T_10462_32;
wire T_10462_33;
wire T_10462_34;
wire T_10462_35;
wire T_10462_36;
wire T_10462_37;
wire T_10462_38;
wire T_10462_39;
wire T_10462_40;
wire T_10462_41;
wire T_10462_42;
wire T_10462_43;
wire T_10462_44;
wire T_10462_45;
wire T_10462_46;
wire T_10462_47;
wire T_10462_48;
wire T_10462_49;
wire T_10462_50;
wire T_10462_51;
wire T_10462_52;
wire T_10462_53;
wire T_10462_54;
wire T_10462_55;
wire T_10462_56;
wire T_10462_57;
wire T_10462_58;
wire T_10462_59;
wire T_10462_60;
wire T_10462_61;
wire T_10462_62;
wire T_10462_63;
wire T_10462_64;
wire T_10462_65;
wire T_10462_66;
wire T_10462_67;
wire T_10462_68;
wire T_10462_69;
wire T_10462_70;
wire T_10462_71;
wire T_10462_72;
wire T_10462_73;
wire T_10462_74;
wire T_10462_75;
wire T_10462_76;
wire T_10462_77;
wire T_10462_78;
wire T_10462_79;
wire T_10462_80;
wire T_10462_81;
wire T_10462_82;
wire T_10462_83;
wire T_10462_84;
wire T_10462_85;
wire T_10462_86;
wire T_10462_87;
wire T_10462_88;
wire T_10462_89;
wire T_10462_90;
wire T_10462_91;
wire T_10462_92;
wire T_10462_93;
wire T_10462_94;
wire T_10462_95;
wire T_10462_96;
wire T_10462_97;
wire T_10462_98;
wire T_10462_99;
wire T_10462_100;
wire T_10462_101;
wire T_10462_102;
wire T_10462_103;
wire T_10462_104;
wire T_10462_105;
wire T_10462_106;
wire T_10462_107;
wire T_10462_108;
wire T_10462_109;
wire T_10462_110;
wire T_10462_111;
wire T_10462_112;
wire T_10462_113;
wire T_10462_114;
wire T_10462_115;
wire T_10462_116;
wire T_10462_117;
wire T_10462_118;
wire T_10462_119;
wire T_10462_120;
wire T_10462_121;
wire T_10462_122;
wire T_10462_123;
wire T_10462_124;
wire T_10462_125;
wire T_10462_126;
wire T_10462_127;
wire [31:0] T_10725_0;
wire [31:0] T_10725_1;
wire [31:0] T_10725_2;
wire [31:0] T_10725_3;
wire [31:0] T_10725_4;
wire [31:0] T_10725_5;
wire [31:0] T_10725_6;
wire [31:0] T_10725_7;
wire [31:0] T_10725_8;
wire [31:0] T_10725_9;
wire [31:0] T_10725_10;
wire [31:0] T_10725_11;
wire [31:0] T_10725_12;
wire [31:0] T_10725_13;
wire [31:0] T_10725_14;
wire [31:0] T_10725_15;
wire [31:0] T_10725_16;
wire [31:0] T_10725_17;
wire [31:0] T_10725_18;
wire [31:0] T_10725_19;
wire [31:0] T_10725_20;
wire [31:0] T_10725_21;
wire [31:0] T_10725_22;
wire [31:0] T_10725_23;
wire [31:0] T_10725_24;
wire [31:0] T_10725_25;
wire [31:0] T_10725_26;
wire [31:0] T_10725_27;
wire [31:0] T_10725_28;
wire [31:0] T_10725_29;
wire [31:0] T_10725_30;
wire [31:0] T_10725_31;
wire [31:0] T_10725_32;
wire [31:0] T_10725_33;
wire [31:0] T_10725_34;
wire [31:0] T_10725_35;
wire [31:0] T_10725_36;
wire [31:0] T_10725_37;
wire [31:0] T_10725_38;
wire [31:0] T_10725_39;
wire [31:0] T_10725_40;
wire [31:0] T_10725_41;
wire [31:0] T_10725_42;
wire [31:0] T_10725_43;
wire [31:0] T_10725_44;
wire [31:0] T_10725_45;
wire [31:0] T_10725_46;
wire [31:0] T_10725_47;
wire [31:0] T_10725_48;
wire [31:0] T_10725_49;
wire [31:0] T_10725_50;
wire [31:0] T_10725_51;
wire [31:0] T_10725_52;
wire [31:0] T_10725_53;
wire [31:0] T_10725_54;
wire [31:0] T_10725_55;
wire [31:0] T_10725_56;
wire [31:0] T_10725_57;
wire [31:0] T_10725_58;
wire [31:0] T_10725_59;
wire [31:0] T_10725_60;
wire [31:0] T_10725_61;
wire [31:0] T_10725_62;
wire [31:0] T_10725_63;
wire [31:0] T_10725_64;
wire [31:0] T_10725_65;
wire [31:0] T_10725_66;
wire [31:0] T_10725_67;
wire [31:0] T_10725_68;
wire [31:0] T_10725_69;
wire [31:0] T_10725_70;
wire [31:0] T_10725_71;
wire [31:0] T_10725_72;
wire [31:0] T_10725_73;
wire [31:0] T_10725_74;
wire [31:0] T_10725_75;
wire [31:0] T_10725_76;
wire [31:0] T_10725_77;
wire [31:0] T_10725_78;
wire [31:0] T_10725_79;
wire [31:0] T_10725_80;
wire [31:0] T_10725_81;
wire [31:0] T_10725_82;
wire [31:0] T_10725_83;
wire [31:0] T_10725_84;
wire [31:0] T_10725_85;
wire [31:0] T_10725_86;
wire [31:0] T_10725_87;
wire [31:0] T_10725_88;
wire [31:0] T_10725_89;
wire [31:0] T_10725_90;
wire [31:0] T_10725_91;
wire [31:0] T_10725_92;
wire [31:0] T_10725_93;
wire [31:0] T_10725_94;
wire [31:0] T_10725_95;
wire [31:0] T_10725_96;
wire [31:0] T_10725_97;
wire [31:0] T_10725_98;
wire [31:0] T_10725_99;
wire [31:0] T_10725_100;
wire [31:0] T_10725_101;
wire [31:0] T_10725_102;
wire [31:0] T_10725_103;
wire [31:0] T_10725_104;
wire [31:0] T_10725_105;
wire [31:0] T_10725_106;
wire [31:0] T_10725_107;
wire [31:0] T_10725_108;
wire [31:0] T_10725_109;
wire [31:0] T_10725_110;
wire [31:0] T_10725_111;
wire [31:0] T_10725_112;
wire [31:0] T_10725_113;
wire [31:0] T_10725_114;
wire [31:0] T_10725_115;
wire [31:0] T_10725_116;
wire [31:0] T_10725_117;
wire [31:0] T_10725_118;
wire [31:0] T_10725_119;
wire [31:0] T_10725_120;
wire [31:0] T_10725_121;
wire [31:0] T_10725_122;
wire [31:0] T_10725_123;
wire [31:0] T_10725_124;
wire [31:0] T_10725_125;
wire [31:0] T_10725_126;
wire [31:0] T_10725_127;
wire GEN_4;
wire GEN_530;
wire GEN_531;
wire GEN_532;
wire GEN_533;
wire GEN_534;
wire GEN_535;
wire GEN_536;
wire GEN_537;
wire GEN_538;
wire GEN_539;
wire GEN_540;
wire GEN_541;
wire GEN_542;
wire GEN_543;
wire GEN_544;
wire GEN_545;
wire GEN_546;
wire GEN_547;
wire GEN_548;
wire GEN_549;
wire GEN_550;
wire GEN_551;
wire GEN_552;
wire GEN_553;
wire GEN_554;
wire GEN_555;
wire GEN_556;
wire GEN_557;
wire GEN_558;
wire GEN_559;
wire GEN_560;
wire GEN_561;
wire GEN_562;
wire GEN_563;
wire GEN_564;
wire GEN_565;
wire GEN_566;
wire GEN_567;
wire GEN_568;
wire GEN_569;
wire GEN_570;
wire GEN_571;
wire GEN_572;
wire GEN_573;
wire GEN_574;
wire GEN_575;
wire GEN_576;
wire GEN_577;
wire GEN_578;
wire GEN_579;
wire GEN_580;
wire GEN_581;
wire GEN_582;
wire GEN_583;
wire GEN_584;
wire GEN_585;
wire GEN_586;
wire GEN_587;
wire GEN_588;
wire GEN_589;
wire GEN_590;
wire GEN_591;
wire GEN_592;
wire GEN_593;
wire GEN_594;
wire GEN_595;
wire GEN_596;
wire GEN_597;
wire GEN_598;
wire GEN_599;
wire GEN_600;
wire GEN_601;
wire GEN_602;
wire GEN_603;
wire GEN_604;
wire GEN_605;
wire GEN_606;
wire GEN_607;
wire GEN_608;
wire GEN_609;
wire GEN_610;
wire GEN_611;
wire GEN_612;
wire GEN_613;
wire GEN_614;
wire GEN_615;
wire GEN_616;
wire GEN_617;
wire GEN_618;
wire GEN_619;
wire GEN_620;
wire GEN_621;
wire GEN_622;
wire GEN_623;
wire GEN_624;
wire GEN_625;
wire GEN_626;
wire GEN_627;
wire GEN_628;
wire GEN_629;
wire GEN_630;
wire GEN_631;
wire GEN_632;
wire GEN_633;
wire GEN_634;
wire GEN_635;
wire GEN_636;
wire GEN_637;
wire GEN_638;
wire GEN_639;
wire GEN_640;
wire GEN_641;
wire GEN_642;
wire GEN_643;
wire GEN_644;
wire GEN_645;
wire GEN_646;
wire GEN_647;
wire GEN_648;
wire GEN_649;
wire GEN_650;
wire GEN_651;
wire GEN_652;
wire GEN_653;
wire GEN_654;
wire GEN_655;
wire GEN_656;
wire [31:0] GEN_5;
wire [31:0] GEN_657;
wire [31:0] GEN_658;
wire [31:0] GEN_659;
wire [31:0] GEN_660;
wire [31:0] GEN_661;
wire [31:0] GEN_662;
wire [31:0] GEN_663;
wire [31:0] GEN_664;
wire [31:0] GEN_665;
wire [31:0] GEN_666;
wire [31:0] GEN_667;
wire [31:0] GEN_668;
wire [31:0] GEN_669;
wire [31:0] GEN_670;
wire [31:0] GEN_671;
wire [31:0] GEN_672;
wire [31:0] GEN_673;
wire [31:0] GEN_674;
wire [31:0] GEN_675;
wire [31:0] GEN_676;
wire [31:0] GEN_677;
wire [31:0] GEN_678;
wire [31:0] GEN_679;
wire [31:0] GEN_680;
wire [31:0] GEN_681;
wire [31:0] GEN_682;
wire [31:0] GEN_683;
wire [31:0] GEN_684;
wire [31:0] GEN_685;
wire [31:0] GEN_686;
wire [31:0] GEN_687;
wire [31:0] GEN_688;
wire [31:0] GEN_689;
wire [31:0] GEN_690;
wire [31:0] GEN_691;
wire [31:0] GEN_692;
wire [31:0] GEN_693;
wire [31:0] GEN_694;
wire [31:0] GEN_695;
wire [31:0] GEN_696;
wire [31:0] GEN_697;
wire [31:0] GEN_698;
wire [31:0] GEN_699;
wire [31:0] GEN_700;
wire [31:0] GEN_701;
wire [31:0] GEN_702;
wire [31:0] GEN_703;
wire [31:0] GEN_704;
wire [31:0] GEN_705;
wire [31:0] GEN_706;
wire [31:0] GEN_707;
wire [31:0] GEN_708;
wire [31:0] GEN_709;
wire [31:0] GEN_710;
wire [31:0] GEN_711;
wire [31:0] GEN_712;
wire [31:0] GEN_713;
wire [31:0] GEN_714;
wire [31:0] GEN_715;
wire [31:0] GEN_716;
wire [31:0] GEN_717;
wire [31:0] GEN_718;
wire [31:0] GEN_719;
wire [31:0] GEN_720;
wire [31:0] GEN_721;
wire [31:0] GEN_722;
wire [31:0] GEN_723;
wire [31:0] GEN_724;
wire [31:0] GEN_725;
wire [31:0] GEN_726;
wire [31:0] GEN_727;
wire [31:0] GEN_728;
wire [31:0] GEN_729;
wire [31:0] GEN_730;
wire [31:0] GEN_731;
wire [31:0] GEN_732;
wire [31:0] GEN_733;
wire [31:0] GEN_734;
wire [31:0] GEN_735;
wire [31:0] GEN_736;
wire [31:0] GEN_737;
wire [31:0] GEN_738;
wire [31:0] GEN_739;
wire [31:0] GEN_740;
wire [31:0] GEN_741;
wire [31:0] GEN_742;
wire [31:0] GEN_743;
wire [31:0] GEN_744;
wire [31:0] GEN_745;
wire [31:0] GEN_746;
wire [31:0] GEN_747;
wire [31:0] GEN_748;
wire [31:0] GEN_749;
wire [31:0] GEN_750;
wire [31:0] GEN_751;
wire [31:0] GEN_752;
wire [31:0] GEN_753;
wire [31:0] GEN_754;
wire [31:0] GEN_755;
wire [31:0] GEN_756;
wire [31:0] GEN_757;
wire [31:0] GEN_758;
wire [31:0] GEN_759;
wire [31:0] GEN_760;
wire [31:0] GEN_761;
wire [31:0] GEN_762;
wire [31:0] GEN_763;
wire [31:0] GEN_764;
wire [31:0] GEN_765;
wire [31:0] GEN_766;
wire [31:0] GEN_767;
wire [31:0] GEN_768;
wire [31:0] GEN_769;
wire [31:0] GEN_770;
wire [31:0] GEN_771;
wire [31:0] GEN_772;
wire [31:0] GEN_773;
wire [31:0] GEN_774;
wire [31:0] GEN_775;
wire [31:0] GEN_776;
wire [31:0] GEN_777;
wire [31:0] GEN_778;
wire [31:0] GEN_779;
wire [31:0] GEN_780;
wire [31:0] GEN_781;
wire [31:0] GEN_782;
wire [31:0] GEN_783;
wire [31:0] T_10858;
wire [1:0] T_10859;
wire [4:0] T_10861;
wire [2:0] T_10862;
wire [2:0] T_10873_opcode;
wire [1:0] T_10873_param;
wire [2:0] T_10873_size;
wire [4:0] T_10873_source;
wire T_10873_sink;
wire [1:0] T_10873_addr_lo;
wire [31:0] T_10873_data;
wire T_10873_error;
wire [2:0] GEN_784 = 3'b0;
reg [31:0] GEN_808;
wire [1:0] GEN_785 = 2'b0;
reg [31:0] GEN_809;
wire [2:0] GEN_786 = 3'b0;
reg [31:0] GEN_810;
wire [4:0] GEN_787 = 5'b0;
reg [31:0] GEN_811;
wire [28:0] GEN_788 = 29'b0;
reg [31:0] GEN_812;
wire [3:0] GEN_789 = 4'b0;
reg [31:0] GEN_813;
wire [31:0] GEN_790 = 32'b0;
reg [31:0] GEN_814;
wire GEN_791 = 1'b0;
reg [31:0] GEN_815;
sirv_rtc rtc (
.clock(rtc_clock),
.reset(rtc_reset),
.io_regs_cfg_write_valid(rtc_io_regs_cfg_write_valid),
.io_regs_cfg_write_bits(rtc_io_regs_cfg_write_bits),
.io_regs_cfg_read(rtc_io_regs_cfg_read),
.io_regs_countLo_write_valid(rtc_io_regs_countLo_write_valid),
.io_regs_countLo_write_bits(rtc_io_regs_countLo_write_bits),
.io_regs_countLo_read(rtc_io_regs_countLo_read),
.io_regs_countHi_write_valid(rtc_io_regs_countHi_write_valid),
.io_regs_countHi_write_bits(rtc_io_regs_countHi_write_bits),
.io_regs_countHi_read(rtc_io_regs_countHi_read),
.io_regs_s_write_valid(rtc_io_regs_s_write_valid),
.io_regs_s_write_bits(rtc_io_regs_s_write_bits),
.io_regs_s_read(rtc_io_regs_s_read),
.io_regs_cmp_0_write_valid(rtc_io_regs_cmp_0_write_valid),
.io_regs_cmp_0_write_bits(rtc_io_regs_cmp_0_write_bits),
.io_regs_cmp_0_read(rtc_io_regs_cmp_0_read),
.io_regs_feed_write_valid(rtc_io_regs_feed_write_valid),
.io_regs_feed_write_bits(rtc_io_regs_feed_write_bits),
.io_regs_feed_read(rtc_io_regs_feed_read),
.io_regs_key_write_valid(rtc_io_regs_key_write_valid),
.io_regs_key_write_bits(rtc_io_regs_key_write_bits),
.io_regs_key_read(rtc_io_regs_key_read),
.io_ip_0(rtc_io_ip_0)
);
sirv_pmu u_sirv_pmu (
.clock(pmu_clock),
.reset(pmu_reset),
.io_wakeup_awakeup(pmu_io_wakeup_awakeup),
.io_wakeup_dwakeup(pmu_io_wakeup_dwakeup),
.io_wakeup_rtc(pmu_io_wakeup_rtc),
.io_wakeup_reset(pmu_io_wakeup_reset),
.io_control_hfclkrst(pmu_io_control_hfclkrst),
.io_control_corerst(pmu_io_control_corerst),
.io_control_reserved1(pmu_io_control_reserved1),
.io_control_vddpaden(pmu_io_control_vddpaden),
.io_control_reserved0(pmu_io_control_reserved0),
.io_regs_ie_write_valid(pmu_io_regs_ie_write_valid),
.io_regs_ie_write_bits(pmu_io_regs_ie_write_bits),
.io_regs_ie_read(pmu_io_regs_ie_read),
.io_regs_cause_write_valid(pmu_io_regs_cause_write_valid),
.io_regs_cause_write_bits(pmu_io_regs_cause_write_bits),
.io_regs_cause_read(pmu_io_regs_cause_read),
.io_regs_sleep_write_valid(pmu_io_regs_sleep_write_valid),
.io_regs_sleep_write_bits(pmu_io_regs_sleep_write_bits),
.io_regs_sleep_read(pmu_io_regs_sleep_read),
.io_regs_key_write_valid(pmu_io_regs_key_write_valid),
.io_regs_key_write_bits(pmu_io_regs_key_write_bits),
.io_regs_key_read(pmu_io_regs_key_read),
.io_regs_wakeupProgram_0_write_valid(pmu_io_regs_wakeupProgram_0_write_valid),
.io_regs_wakeupProgram_0_write_bits(pmu_io_regs_wakeupProgram_0_write_bits),
.io_regs_wakeupProgram_0_read(pmu_io_regs_wakeupProgram_0_read),
.io_regs_wakeupProgram_1_write_valid(pmu_io_regs_wakeupProgram_1_write_valid),
.io_regs_wakeupProgram_1_write_bits(pmu_io_regs_wakeupProgram_1_write_bits),
.io_regs_wakeupProgram_1_read(pmu_io_regs_wakeupProgram_1_read),
.io_regs_wakeupProgram_2_write_valid(pmu_io_regs_wakeupProgram_2_write_valid),
.io_regs_wakeupProgram_2_write_bits(pmu_io_regs_wakeupProgram_2_write_bits),
.io_regs_wakeupProgram_2_read(pmu_io_regs_wakeupProgram_2_read),
.io_regs_wakeupProgram_3_write_valid(pmu_io_regs_wakeupProgram_3_write_valid),
.io_regs_wakeupProgram_3_write_bits(pmu_io_regs_wakeupProgram_3_write_bits),
.io_regs_wakeupProgram_3_read(pmu_io_regs_wakeupProgram_3_read),
.io_regs_wakeupProgram_4_write_valid(pmu_io_regs_wakeupProgram_4_write_valid),
.io_regs_wakeupProgram_4_write_bits(pmu_io_regs_wakeupProgram_4_write_bits),
.io_regs_wakeupProgram_4_read(pmu_io_regs_wakeupProgram_4_read),
.io_regs_wakeupProgram_5_write_valid(pmu_io_regs_wakeupProgram_5_write_valid),
.io_regs_wakeupProgram_5_write_bits(pmu_io_regs_wakeupProgram_5_write_bits),
.io_regs_wakeupProgram_5_read(pmu_io_regs_wakeupProgram_5_read),
.io_regs_wakeupProgram_6_write_valid(pmu_io_regs_wakeupProgram_6_write_valid),
.io_regs_wakeupProgram_6_write_bits(pmu_io_regs_wakeupProgram_6_write_bits),
.io_regs_wakeupProgram_6_read(pmu_io_regs_wakeupProgram_6_read),
.io_regs_wakeupProgram_7_write_valid(pmu_io_regs_wakeupProgram_7_write_valid),
.io_regs_wakeupProgram_7_write_bits(pmu_io_regs_wakeupProgram_7_write_bits),
.io_regs_wakeupProgram_7_read(pmu_io_regs_wakeupProgram_7_read),
.io_regs_sleepProgram_0_write_valid(pmu_io_regs_sleepProgram_0_write_valid),
.io_regs_sleepProgram_0_write_bits(pmu_io_regs_sleepProgram_0_write_bits),
.io_regs_sleepProgram_0_read(pmu_io_regs_sleepProgram_0_read),
.io_regs_sleepProgram_1_write_valid(pmu_io_regs_sleepProgram_1_write_valid),
.io_regs_sleepProgram_1_write_bits(pmu_io_regs_sleepProgram_1_write_bits),
.io_regs_sleepProgram_1_read(pmu_io_regs_sleepProgram_1_read),
.io_regs_sleepProgram_2_write_valid(pmu_io_regs_sleepProgram_2_write_valid),
.io_regs_sleepProgram_2_write_bits(pmu_io_regs_sleepProgram_2_write_bits),
.io_regs_sleepProgram_2_read(pmu_io_regs_sleepProgram_2_read),
.io_regs_sleepProgram_3_write_valid(pmu_io_regs_sleepProgram_3_write_valid),
.io_regs_sleepProgram_3_write_bits(pmu_io_regs_sleepProgram_3_write_bits),
.io_regs_sleepProgram_3_read(pmu_io_regs_sleepProgram_3_read),
.io_regs_sleepProgram_4_write_valid(pmu_io_regs_sleepProgram_4_write_valid),
.io_regs_sleepProgram_4_write_bits(pmu_io_regs_sleepProgram_4_write_bits),
.io_regs_sleepProgram_4_read(pmu_io_regs_sleepProgram_4_read),
.io_regs_sleepProgram_5_write_valid(pmu_io_regs_sleepProgram_5_write_valid),
.io_regs_sleepProgram_5_write_bits(pmu_io_regs_sleepProgram_5_write_bits),
.io_regs_sleepProgram_5_read(pmu_io_regs_sleepProgram_5_read),
.io_regs_sleepProgram_6_write_valid(pmu_io_regs_sleepProgram_6_write_valid),
.io_regs_sleepProgram_6_write_bits(pmu_io_regs_sleepProgram_6_write_bits),
.io_regs_sleepProgram_6_read(pmu_io_regs_sleepProgram_6_read),
.io_regs_sleepProgram_7_write_valid(pmu_io_regs_sleepProgram_7_write_valid),
.io_regs_sleepProgram_7_write_bits(pmu_io_regs_sleepProgram_7_write_bits),
.io_regs_sleepProgram_7_read(pmu_io_regs_sleepProgram_7_read),
.io_resetCauses_wdogrst(pmu_io_resetCauses_wdogrst),
.io_resetCauses_erst(pmu_io_resetCauses_erst),
.io_resetCauses_porrst(pmu_io_resetCauses_porrst)
);
sirv_wdog wdog (
.clock(wdog_clock),
.reset(wdog_reset),
.io_regs_cfg_write_valid(wdog_io_regs_cfg_write_valid),
.io_regs_cfg_write_bits(wdog_io_regs_cfg_write_bits),
.io_regs_cfg_read(wdog_io_regs_cfg_read),
.io_regs_countLo_write_valid(wdog_io_regs_countLo_write_valid),
.io_regs_countLo_write_bits(wdog_io_regs_countLo_write_bits),
.io_regs_countLo_read(wdog_io_regs_countLo_read),
.io_regs_countHi_write_valid(wdog_io_regs_countHi_write_valid),
.io_regs_countHi_write_bits(wdog_io_regs_countHi_write_bits),
.io_regs_countHi_read(wdog_io_regs_countHi_read),
.io_regs_s_write_valid(wdog_io_regs_s_write_valid),
.io_regs_s_write_bits(wdog_io_regs_s_write_bits),
.io_regs_s_read(wdog_io_regs_s_read),
.io_regs_cmp_0_write_valid(wdog_io_regs_cmp_0_write_valid),
.io_regs_cmp_0_write_bits(wdog_io_regs_cmp_0_write_bits),
.io_regs_cmp_0_read(wdog_io_regs_cmp_0_read),
.io_regs_feed_write_valid(wdog_io_regs_feed_write_valid),
.io_regs_feed_write_bits(wdog_io_regs_feed_write_bits),
.io_regs_feed_read(wdog_io_regs_feed_read),
.io_regs_key_write_valid(wdog_io_regs_key_write_valid),
.io_regs_key_write_bits(wdog_io_regs_key_write_bits),
.io_regs_key_read(wdog_io_regs_key_read),
.io_ip_0(wdog_io_ip_0),
.io_corerst(wdog_io_corerst),
.io_rst(wdog_io_rst)
);
sirv_queue u_queue_1 (
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_read(Queue_1_io_enq_bits_read),
.io_enq_bits_index(Queue_1_io_enq_bits_index),
.io_enq_bits_data(Queue_1_io_enq_bits_data),
.io_enq_bits_mask(Queue_1_io_enq_bits_mask),
.io_enq_bits_extra(Queue_1_io_enq_bits_extra),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_read(Queue_1_io_deq_bits_read),
.io_deq_bits_index(Queue_1_io_deq_bits_index),
.io_deq_bits_data(Queue_1_io_deq_bits_data),
.io_deq_bits_mask(Queue_1_io_deq_bits_mask),
.io_deq_bits_extra(Queue_1_io_deq_bits_extra),
.io_count(Queue_1_io_count)
);
assign io_interrupts_0_0 = wdog_io_ip_0;
assign io_interrupts_0_1 = rtc_io_ip_0;
assign io_in_0_a_ready = T_953_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_784;
assign io_in_0_b_bits_param = GEN_785;
assign io_in_0_b_bits_size = GEN_786;
assign io_in_0_b_bits_source = GEN_787;
assign io_in_0_b_bits_address = GEN_788;
assign io_in_0_b_bits_mask = GEN_789;
assign io_in_0_b_bits_data = GEN_790;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_992_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, T_992_bits_read};
assign io_in_0_d_bits_param = T_10873_param;
assign io_in_0_d_bits_size = T_10873_size;
assign io_in_0_d_bits_source = T_10873_source;
assign io_in_0_d_bits_sink = T_10873_sink;
assign io_in_0_d_bits_addr_lo = T_10873_addr_lo;
assign io_in_0_d_bits_data = T_992_bits_data;
assign io_in_0_d_bits_error = T_10873_error;
assign io_in_0_e_ready = 1'h1;
assign io_lfclk = io_lfextclk;
// In DFT mode the internal generated reset siganls should be disabled
assign io_moff_hfclkrst = test_mode ? erst : pmu_io_control_hfclkrst;
assign io_moff_corerst = test_mode ? erst : pmu_io_control_corerst;
assign io_wdog_rst = test_mode ? erst : wdog_io_rst;
//Bob: This reserved1 signal is actually the padrst signal used in hifive board
assign io_pmu_padrst = test_mode ? 1'b1 : pmu_io_control_reserved1;
// In DFT mode the power control siganls should be disabled
assign io_pmu_vddpaden = test_mode ? 1'b1 : pmu_io_control_vddpaden;
assign rtc_clock = clock;
assign rtc_reset = reset;
assign rtc_io_regs_cfg_write_valid = T_3904;
assign rtc_io_regs_cfg_write_bits = T_2505;
assign rtc_io_regs_countLo_write_valid = T_3824;
assign rtc_io_regs_countLo_write_bits = T_2505;
assign rtc_io_regs_countHi_write_valid = T_4264;
assign rtc_io_regs_countHi_write_bits = T_2505;
assign rtc_io_regs_s_write_valid = T_2704;
assign rtc_io_regs_s_write_bits = T_2505;
assign rtc_io_regs_cmp_0_write_valid = T_2624;
assign rtc_io_regs_cmp_0_write_bits = T_2505;
assign rtc_io_regs_feed_write_valid = T_3384;
assign rtc_io_regs_feed_write_bits = T_2505;
assign rtc_io_regs_key_write_valid = T_4064;
assign rtc_io_regs_key_write_bits = T_2505;
assign pmu_clock = clock;
assign pmu_reset = reset;
assign pmu_io_wakeup_awakeup = 1'h0;
assign pmu_io_wakeup_dwakeup = io_pmu_dwakeup;
assign pmu_io_wakeup_rtc = rtc_io_ip_0;
assign pmu_io_wakeup_reset = GEN_791;
assign pmu_io_regs_ie_write_valid = T_3744;
assign pmu_io_regs_ie_write_bits = T_3745;
assign pmu_io_regs_cause_write_valid = T_3504;
assign pmu_io_regs_cause_write_bits = T_2505;
assign pmu_io_regs_sleep_write_valid = T_4184;
assign pmu_io_regs_sleep_write_bits = T_2505;
assign pmu_io_regs_key_write_valid = T_4464;
assign pmu_io_regs_key_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_0_write_valid = T_3344;
assign pmu_io_regs_wakeupProgram_0_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_1_write_valid = T_3024;
assign pmu_io_regs_wakeupProgram_1_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_2_write_valid = T_3664;
assign pmu_io_regs_wakeupProgram_2_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_3_write_valid = T_3864;
assign pmu_io_regs_wakeupProgram_3_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_4_write_valid = T_4424;
assign pmu_io_regs_wakeupProgram_4_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_5_write_valid = T_2504;
assign pmu_io_regs_wakeupProgram_5_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_6_write_valid = T_2944;
assign pmu_io_regs_wakeupProgram_6_write_bits = T_2505;
assign pmu_io_regs_wakeupProgram_7_write_valid = T_3464;
assign pmu_io_regs_wakeupProgram_7_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_0_write_valid = T_3944;
assign pmu_io_regs_sleepProgram_0_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_1_write_valid = T_3144;
assign pmu_io_regs_sleepProgram_1_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_2_write_valid = T_2824;
assign pmu_io_regs_sleepProgram_2_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_3_write_valid = T_4144;
assign pmu_io_regs_sleepProgram_3_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_4_write_valid = T_3544;
assign pmu_io_regs_sleepProgram_4_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_5_write_valid = T_3064;
assign pmu_io_regs_sleepProgram_5_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_6_write_valid = T_2784;
assign pmu_io_regs_sleepProgram_6_write_bits = T_2505;
assign pmu_io_regs_sleepProgram_7_write_valid = T_4344;
assign pmu_io_regs_sleepProgram_7_write_bits = T_2505;
assign pmu_io_resetCauses_wdogrst = io_resetCauses_wdogrst;
assign pmu_io_resetCauses_erst = io_resetCauses_erst;
assign pmu_io_resetCauses_porrst = io_resetCauses_porrst;
assign wdog_clock = clock;
assign wdog_reset = reset;
assign wdog_io_regs_cfg_write_valid = T_2544;
assign wdog_io_regs_cfg_write_bits = T_2505;
assign wdog_io_regs_countLo_write_valid = T_3184;
assign wdog_io_regs_countLo_write_bits = T_2505;
assign wdog_io_regs_countHi_write_valid = T_3704;
assign wdog_io_regs_countHi_write_bits = T_2505;
assign wdog_io_regs_s_write_valid = T_4304;
assign wdog_io_regs_s_write_bits = T_4105;
assign wdog_io_regs_cmp_0_write_valid = T_4104;
assign wdog_io_regs_cmp_0_write_bits = T_4105;
assign wdog_io_regs_feed_write_valid = T_2864;
assign wdog_io_regs_feed_write_bits = T_2505;
assign wdog_io_regs_key_write_valid = T_3584;
assign wdog_io_regs_key_write_bits = T_2505;
assign wdog_io_corerst = pmu_io_control_corerst;
assign T_953_ready = T_7307;
assign T_953_valid = io_in_0_a_valid;
assign T_953_bits_read = T_970;
assign T_953_bits_index = T_971[9:0];
assign T_953_bits_data = io_in_0_a_bits_data;
assign T_953_bits_mask = io_in_0_a_bits_mask;
assign T_953_bits_extra = T_974;
assign T_970 = io_in_0_a_bits_opcode == 3'h4;
assign T_971 = io_in_0_a_bits_address[28:2];
assign T_972 = io_in_0_a_bits_address[1:0];
assign T_973 = {T_972,io_in_0_a_bits_source};
assign T_974 = {T_973,io_in_0_a_bits_size};
assign T_992_ready = io_in_0_d_ready;
assign T_992_valid = T_7310;
assign T_992_bits_read = Queue_1_io_deq_bits_read;
assign T_992_bits_data = T_10858;
assign T_992_bits_extra = Queue_1_io_deq_bits_extra;
assign T_1028_ready = Queue_1_io_enq_ready;
assign T_1028_valid = T_7308;
assign T_1028_bits_read = T_953_bits_read;
assign T_1028_bits_index = T_953_bits_index;
assign T_1028_bits_data = T_953_bits_data;
assign T_1028_bits_mask = T_953_bits_mask;
assign T_1028_bits_extra = T_953_bits_extra;
assign Queue_1_clock = clock;
assign Queue_1_reset = reset;
assign Queue_1_io_enq_valid = T_1028_valid;
assign Queue_1_io_enq_bits_read = T_1028_bits_read;
assign Queue_1_io_enq_bits_index = T_1028_bits_index;
assign Queue_1_io_enq_bits_data = T_1028_bits_data;
assign Queue_1_io_enq_bits_mask = T_1028_bits_mask;
assign Queue_1_io_enq_bits_extra = T_1028_bits_extra;
assign Queue_1_io_deq_ready = T_7309;
assign T_1310 = T_1028_bits_index ^ 10'h45;
assign T_1311 = T_1310 & 10'h380;
assign T_1313 = T_1311 == 10'h0;
assign T_1314 = Queue_1_io_deq_bits_index ^ 10'h45;
assign T_1315 = T_1314 & 10'h380;
assign T_1317 = T_1315 == 10'h0;
assign T_1320 = T_1028_bits_index & 10'h380;
assign T_1322 = T_1320 == 10'h0;
assign T_1323 = Queue_1_io_deq_bits_index;
assign T_1324 = T_1323 & 10'h380;
assign T_1326 = T_1324 == 10'h0;
assign T_1328 = T_1028_bits_index ^ 10'h2a;
assign T_1329 = T_1328 & 10'h380;
assign T_1331 = T_1329 == 10'h0;
assign T_1332 = Queue_1_io_deq_bits_index ^ 10'h2a;
assign T_1333 = T_1332 & 10'h380;
assign T_1335 = T_1333 == 10'h0;
assign T_1337 = T_1028_bits_index ^ 10'h18;
assign T_1338 = T_1337 & 10'h380;
assign T_1340 = T_1338 == 10'h0;
assign T_1341 = Queue_1_io_deq_bits_index ^ 10'h18;
assign T_1342 = T_1341 & 10'h380;
assign T_1344 = T_1342 == 10'h0;
assign T_1346 = T_1028_bits_index ^ 10'h25;
assign T_1347 = T_1346 & 10'h380;
assign T_1349 = T_1347 == 10'h0;
assign T_1350 = Queue_1_io_deq_bits_index ^ 10'h25;
assign T_1351 = T_1350 & 10'h380;
assign T_1353 = T_1351 == 10'h0;
assign T_1355 = T_1028_bits_index ^ 10'h14;
assign T_1356 = T_1355 & 10'h380;
assign T_1358 = T_1356 == 10'h0;
assign T_1359 = Queue_1_io_deq_bits_index ^ 10'h14;
assign T_1360 = T_1359 & 10'h380;
assign T_1362 = T_1360 == 10'h0;
assign T_1364 = T_1028_bits_index ^ 10'h2e;
assign T_1365 = T_1364 & 10'h380;
assign T_1367 = T_1365 == 10'h0;
assign T_1368 = Queue_1_io_deq_bits_index ^ 10'h2e;
assign T_1369 = T_1368 & 10'h380;
assign T_1371 = T_1369 == 10'h0;
assign T_1373 = T_1028_bits_index ^ 10'h4e;
assign T_1374 = T_1373 & 10'h380;
assign T_1376 = T_1374 == 10'h0;
assign T_1377 = Queue_1_io_deq_bits_index ^ 10'h4e;
assign T_1378 = T_1377 & 10'h380;
assign T_1380 = T_1378 == 10'h0;
assign T_1382 = T_1028_bits_index ^ 10'h4a;
assign T_1383 = T_1382 & 10'h380;
assign T_1385 = T_1383 == 10'h0;
assign T_1386 = Queue_1_io_deq_bits_index ^ 10'h4a;
assign T_1387 = T_1386 & 10'h380;
assign T_1389 = T_1387 == 10'h0;
assign T_1391 = T_1028_bits_index ^ 10'h6;
assign T_1392 = T_1391 & 10'h380;
assign T_1394 = T_1392 == 10'h0;
assign T_1395 = Queue_1_io_deq_bits_index ^ 10'h6;
assign T_1396 = T_1395 & 10'h380;
assign T_1398 = T_1396 == 10'h0;
assign T_1400 = T_1028_bits_index ^ 10'h26;
assign T_1401 = T_1400 & 10'h380;
assign T_1403 = T_1401 == 10'h0;
assign T_1404 = Queue_1_io_deq_bits_index ^ 10'h26;
assign T_1405 = T_1404 & 10'h380;
assign T_1407 = T_1405 == 10'h0;
assign T_1409 = T_1028_bits_index ^ 10'h46;
assign T_1410 = T_1409 & 10'h380;
assign T_1412 = T_1410 == 10'h0;
assign T_1413 = Queue_1_io_deq_bits_index ^ 10'h46;
assign T_1414 = T_1413 & 10'h380;
assign T_1416 = T_1414 == 10'h0;
assign T_1418 = T_1028_bits_index ^ 10'h21;
assign T_1419 = T_1418 & 10'h380;
assign T_1421 = T_1419 == 10'h0;
assign T_1422 = Queue_1_io_deq_bits_index ^ 10'h21;
assign T_1423 = T_1422 & 10'h380;
assign T_1425 = T_1423 == 10'h0;
assign T_1427 = T_1028_bits_index ^ 10'h41;
assign T_1428 = T_1427 & 10'h380;
assign T_1430 = T_1428 == 10'h0;
assign T_1431 = Queue_1_io_deq_bits_index ^ 10'h41;
assign T_1432 = T_1431 & 10'h380;
assign T_1434 = T_1432 == 10'h0;
assign T_1436 = T_1028_bits_index ^ 10'h4d;
assign T_1437 = T_1436 & 10'h380;
assign T_1439 = T_1437 == 10'h0;
assign T_1440 = Queue_1_io_deq_bits_index ^ 10'h4d;
assign T_1441 = T_1440 & 10'h380;
assign T_1443 = T_1441 == 10'h0;
assign T_1445 = T_1028_bits_index ^ 10'h29;
assign T_1446 = T_1445 & 10'h380;
assign T_1448 = T_1446 == 10'h0;
assign T_1449 = Queue_1_io_deq_bits_index ^ 10'h29;
assign T_1450 = T_1449 & 10'h380;
assign T_1452 = T_1450 == 10'h0;
assign T_1454 = T_1028_bits_index ^ 10'h49;
assign T_1455 = T_1454 & 10'h380;
assign T_1457 = T_1455 == 10'h0;
assign T_1458 = Queue_1_io_deq_bits_index ^ 10'h49;
assign T_1459 = T_1458 & 10'h380;
assign T_1461 = T_1459 == 10'h0;
assign T_1463 = T_1028_bits_index ^ 10'h2;
assign T_1464 = T_1463 & 10'h380;
assign T_1466 = T_1464 == 10'h0;
assign T_1467 = Queue_1_io_deq_bits_index ^ 10'h2;
assign T_1468 = T_1467 & 10'h380;
assign T_1470 = T_1468 == 10'h0;
assign T_1472 = T_1028_bits_index ^ 10'h20;
assign T_1473 = T_1472 & 10'h380;
assign T_1475 = T_1473 == 10'h0;
assign T_1476 = Queue_1_io_deq_bits_index ^ 10'h20;
assign T_1477 = T_1476 & 10'h380;
assign T_1479 = T_1477 == 10'h0;
assign T_1481 = T_1028_bits_index ^ 10'h22;
assign T_1482 = T_1481 & 10'h380;
assign T_1484 = T_1482 == 10'h0;
assign T_1485 = Queue_1_io_deq_bits_index ^ 10'h22;
assign T_1486 = T_1485 & 10'h380;
assign T_1488 = T_1486 == 10'h0;
assign T_1490 = T_1028_bits_index ^ 10'h2d;
assign T_1491 = T_1490 & 10'h380;
assign T_1493 = T_1491 == 10'h0;
assign T_1494 = Queue_1_io_deq_bits_index ^ 10'h2d;
assign T_1495 = T_1494 & 10'h380;
assign T_1497 = T_1495 == 10'h0;
assign T_1499 = T_1028_bits_index ^ 10'h40;
assign T_1500 = T_1499 & 10'h380;
assign T_1502 = T_1500 == 10'h0;
assign T_1503 = Queue_1_io_deq_bits_index ^ 10'h40;
assign T_1504 = T_1503 & 10'h380;
assign T_1506 = T_1504 == 10'h0;
assign T_1508 = T_1028_bits_index ^ 10'h16;
assign T_1509 = T_1508 & 10'h380;
assign T_1511 = T_1509 == 10'h0;
assign T_1512 = Queue_1_io_deq_bits_index ^ 10'h16;
assign T_1513 = T_1512 & 10'h380;
assign T_1515 = T_1513 == 10'h0;
assign T_1517 = T_1028_bits_index ^ 10'h2c;
assign T_1518 = T_1517 & 10'h380;
assign T_1520 = T_1518 == 10'h0;
assign T_1521 = Queue_1_io_deq_bits_index ^ 10'h2c;
assign T_1522 = T_1521 & 10'h380;
assign T_1524 = T_1522 == 10'h0;
assign T_1526 = T_1028_bits_index ^ 10'h47;
assign T_1527 = T_1526 & 10'h380;
assign T_1529 = T_1527 == 10'h0;
assign T_1530 = Queue_1_io_deq_bits_index ^ 10'h47;
assign T_1531 = T_1530 & 10'h380;
assign T_1533 = T_1531 == 10'h0;
assign T_1535 = T_1028_bits_index ^ 10'h51;
assign T_1536 = T_1535 & 10'h380;
assign T_1538 = T_1536 == 10'h0;
assign T_1539 = Queue_1_io_deq_bits_index ^ 10'h51;
assign T_1540 = T_1539 & 10'h380;
assign T_1542 = T_1540 == 10'h0;
assign T_1544 = T_1028_bits_index ^ 10'h4c;
assign T_1545 = T_1544 & 10'h380;
assign T_1547 = T_1545 == 10'h0;
assign T_1548 = Queue_1_io_deq_bits_index ^ 10'h4c;
assign T_1549 = T_1548 & 10'h380;
assign T_1551 = T_1549 == 10'h0;
assign T_1553 = T_1028_bits_index ^ 10'h7;
assign T_1554 = T_1553 & 10'h380;
assign T_1556 = T_1554 == 10'h0;
assign T_1557 = Queue_1_io_deq_bits_index ^ 10'h7;
assign T_1558 = T_1557 & 10'h380;
assign T_1560 = T_1558 == 10'h0;
assign T_1562 = T_1028_bits_index ^ 10'h27;
assign T_1563 = T_1562 & 10'h380;
assign T_1565 = T_1563 == 10'h0;
assign T_1566 = Queue_1_io_deq_bits_index ^ 10'h27;
assign T_1567 = T_1566 & 10'h380;
assign T_1569 = T_1567 == 10'h0;
assign T_1571 = T_1028_bits_index ^ 10'h42;
assign T_1572 = T_1571 & 10'h380;
assign T_1574 = T_1572 == 10'h0;
assign T_1575 = Queue_1_io_deq_bits_index ^ 10'h42;
assign T_1576 = T_1575 & 10'h380;
assign T_1578 = T_1576 == 10'h0;
assign T_1580 = T_1028_bits_index ^ 10'h3;
assign T_1581 = T_1580 & 10'h380;
assign T_1583 = T_1581 == 10'h0;
assign T_1584 = Queue_1_io_deq_bits_index ^ 10'h3;
assign T_1585 = T_1584 & 10'h380;
assign T_1587 = T_1585 == 10'h0;
assign T_1589 = T_1028_bits_index ^ 10'h50;
assign T_1590 = T_1589 & 10'h380;
assign T_1592 = T_1590 == 10'h0;
assign T_1593 = Queue_1_io_deq_bits_index ^ 10'h50;
assign T_1594 = T_1593 & 10'h380;
assign T_1596 = T_1594 == 10'h0;
assign T_1598 = T_1028_bits_index ^ 10'h23;
assign T_1599 = T_1598 & 10'h380;
assign T_1601 = T_1599 == 10'h0;
assign T_1602 = Queue_1_io_deq_bits_index ^ 10'h23;
assign T_1603 = T_1602 & 10'h380;
assign T_1605 = T_1603 == 10'h0;
assign T_1607 = T_1028_bits_index ^ 10'h12;
assign T_1608 = T_1607 & 10'h380;
assign T_1610 = T_1608 == 10'h0;
assign T_1611 = Queue_1_io_deq_bits_index ^ 10'h12;
assign T_1612 = T_1611 & 10'h380;
assign T_1614 = T_1612 == 10'h0;
assign T_1616 = T_1028_bits_index ^ 10'h43;
assign T_1617 = T_1616 & 10'h380;
assign T_1619 = T_1617 == 10'h0;
assign T_1620 = Queue_1_io_deq_bits_index ^ 10'h43;
assign T_1621 = T_1620 & 10'h380;
assign T_1623 = T_1621 == 10'h0;
assign T_1625 = T_1028_bits_index ^ 10'h10;
assign T_1626 = T_1625 & 10'h380;
assign T_1628 = T_1626 == 10'h0;
assign T_1629 = Queue_1_io_deq_bits_index ^ 10'h10;
assign T_1630 = T_1629 & 10'h380;
assign T_1632 = T_1630 == 10'h0;
assign T_1634 = T_1028_bits_index ^ 10'h48;
assign T_1635 = T_1634 & 10'h380;
assign T_1637 = T_1635 == 10'h0;
assign T_1638 = Queue_1_io_deq_bits_index ^ 10'h48;
assign T_1639 = T_1638 & 10'h380;
assign T_1641 = T_1639 == 10'h0;
assign T_1643 = T_1028_bits_index ^ 10'h2b;
assign T_1644 = T_1643 & 10'h380;
assign T_1646 = T_1644 == 10'h0;
assign T_1647 = Queue_1_io_deq_bits_index ^ 10'h2b;
assign T_1648 = T_1647 & 10'h380;
assign T_1650 = T_1648 == 10'h0;
assign T_1652 = T_1028_bits_index ^ 10'h28;
assign T_1653 = T_1652 & 10'h380;
assign T_1655 = T_1653 == 10'h0;
assign T_1656 = Queue_1_io_deq_bits_index ^ 10'h28;
assign T_1657 = T_1656 & 10'h380;
assign T_1659 = T_1657 == 10'h0;
assign T_1661 = T_1028_bits_index ^ 10'h17;
assign T_1662 = T_1661 & 10'h380;
assign T_1664 = T_1662 == 10'h0;
assign T_1665 = Queue_1_io_deq_bits_index ^ 10'h17;
assign T_1666 = T_1665 & 10'h380;
assign T_1668 = T_1666 == 10'h0;
assign T_1670 = T_1028_bits_index ^ 10'h8;
assign T_1671 = T_1670 & 10'h380;
assign T_1673 = T_1671 == 10'h0;
assign T_1674 = Queue_1_io_deq_bits_index ^ 10'h8;
assign T_1675 = T_1674 & 10'h380;
assign T_1677 = T_1675 == 10'h0;
assign T_1679 = T_1028_bits_index ^ 10'h4b;
assign T_1680 = T_1679 & 10'h380;
assign T_1682 = T_1680 == 10'h0;
assign T_1683 = Queue_1_io_deq_bits_index ^ 10'h4b;
assign T_1684 = T_1683 & 10'h380;
assign T_1686 = T_1684 == 10'h0;
assign T_1688 = T_1028_bits_index ^ 10'h52;
assign T_1689 = T_1688 & 10'h380;
assign T_1691 = T_1689 == 10'h0;
assign T_1692 = Queue_1_io_deq_bits_index ^ 10'h52;
assign T_1693 = T_1692 & 10'h380;
assign T_1695 = T_1693 == 10'h0;
assign T_1697 = T_1028_bits_index ^ 10'h24;
assign T_1698 = T_1697 & 10'h380;
assign T_1700 = T_1698 == 10'h0;
assign T_1701 = Queue_1_io_deq_bits_index ^ 10'h24;
assign T_1702 = T_1701 & 10'h380;
assign T_1704 = T_1702 == 10'h0;
assign T_1706 = T_1028_bits_index ^ 10'h13;
assign T_1707 = T_1706 & 10'h380;
assign T_1709 = T_1707 == 10'h0;
assign T_1710 = Queue_1_io_deq_bits_index ^ 10'h13;
assign T_1711 = T_1710 & 10'h380;
assign T_1713 = T_1711 == 10'h0;
assign T_1715 = T_1028_bits_index ^ 10'h4;
assign T_1716 = T_1715 & 10'h380;
assign T_1718 = T_1716 == 10'h0;
assign T_1719 = Queue_1_io_deq_bits_index ^ 10'h4;
assign T_1720 = T_1719 & 10'h380;
assign T_1722 = T_1720 == 10'h0;
assign T_1724 = T_1028_bits_index ^ 10'h4f;
assign T_1725 = T_1724 & 10'h380;
assign T_1727 = T_1725 == 10'h0;
assign T_1728 = Queue_1_io_deq_bits_index ^ 10'h4f;
assign T_1729 = T_1728 & 10'h380;
assign T_1731 = T_1729 == 10'h0;
assign T_1733 = T_1028_bits_index ^ 10'h2f;
assign T_1734 = T_1733 & 10'h380;
assign T_1736 = T_1734 == 10'h0;
assign T_1737 = Queue_1_io_deq_bits_index ^ 10'h2f;
assign T_1738 = T_1737 & 10'h380;
assign T_1740 = T_1738 == 10'h0;
assign T_1742 = T_1028_bits_index ^ 10'h44;
assign T_1743 = T_1742 & 10'h380;
assign T_1745 = T_1743 == 10'h0;
assign T_1746 = Queue_1_io_deq_bits_index ^ 10'h44;
assign T_1747 = T_1746 & 10'h380;
assign T_1749 = T_1747 == 10'h0;
assign T_1751 = T_1028_bits_index ^ 10'h53;
assign T_1752 = T_1751 & 10'h380;
assign T_1754 = T_1752 == 10'h0;
assign T_1755 = Queue_1_io_deq_bits_index ^ 10'h53;
assign T_1756 = T_1755 & 10'h380;
assign T_1758 = T_1756 == 10'h0;
assign T_1762_0 = T_8954;
assign T_1762_1 = T_7574;
assign T_1762_2 = T_8414;
assign T_1762_3 = T_8054;
assign T_1762_4 = T_8314;
assign T_1762_5 = T_7974;
assign T_1762_6 = T_8494;
assign T_1762_7 = T_9134;
assign T_1762_8 = T_9054;
assign T_1762_9 = T_7694;
assign T_1762_10 = T_8334;
assign T_1762_11 = T_8974;
assign T_1762_12 = T_8234;
assign T_1762_13 = T_8874;
assign T_1762_14 = T_9114;
assign T_1762_15 = T_8394;
assign T_1762_16 = T_9034;
assign T_1762_17 = T_7614;
assign T_1762_18 = T_8214;
assign T_1762_19 = T_8254;
assign T_1762_20 = T_8474;
assign T_1762_21 = T_8854;
assign T_1762_22 = T_8014;
assign T_1762_23 = T_8454;
assign T_1762_24 = T_8994;
assign T_1762_25 = T_9194;
assign T_1762_26 = T_9094;
assign T_1762_27 = T_7714;
assign T_1762_28 = T_8354;
assign T_1762_29 = T_8894;
assign T_1762_30 = T_7634;
assign T_1762_31 = T_9174;
assign T_1762_32 = T_8274;
assign T_1762_33 = T_7934;
assign T_1762_34 = T_8914;
assign T_1762_35 = T_7894;
assign T_1762_36 = T_9014;
assign T_1762_37 = T_8434;
assign T_1762_38 = T_8374;
assign T_1762_39 = T_8034;
assign T_1762_40 = T_7734;
assign T_1762_41 = T_9074;
assign T_1762_42 = T_9214;
assign T_1762_43 = T_8294;
assign T_1762_44 = T_7954;
assign T_1762_45 = T_7654;
assign T_1762_46 = T_9154;
assign T_1762_47 = T_8514;
assign T_1762_48 = T_8934;
assign T_1762_49 = T_9234;
assign T_1767_0 = T_8960;
assign T_1767_1 = T_7580;
assign T_1767_2 = T_8420;
assign T_1767_3 = T_8060;
assign T_1767_4 = T_8320;
assign T_1767_5 = T_7980;
assign T_1767_6 = T_8500;
assign T_1767_7 = T_9140;
assign T_1767_8 = T_9060;
assign T_1767_9 = T_7700;
assign T_1767_10 = T_8340;
assign T_1767_11 = T_8980;
assign T_1767_12 = T_8240;
assign T_1767_13 = T_8880;
assign T_1767_14 = T_9120;
assign T_1767_15 = T_8400;
assign T_1767_16 = T_9040;
assign T_1767_17 = T_7620;
assign T_1767_18 = T_8220;
assign T_1767_19 = T_8260;
assign T_1767_20 = T_8480;
assign T_1767_21 = T_8860;
assign T_1767_22 = T_8020;
assign T_1767_23 = T_8460;
assign T_1767_24 = T_9000;
assign T_1767_25 = T_9200;
assign T_1767_26 = T_9100;
assign T_1767_27 = T_7720;
assign T_1767_28 = T_8360;
assign T_1767_29 = T_8900;
assign T_1767_30 = T_7640;
assign T_1767_31 = T_9180;
assign T_1767_32 = T_8280;
assign T_1767_33 = T_7940;
assign T_1767_34 = T_8920;
assign T_1767_35 = T_7900;
assign T_1767_36 = T_9020;
assign T_1767_37 = T_8440;
assign T_1767_38 = T_8380;
assign T_1767_39 = T_8040;
assign T_1767_40 = T_7740;
assign T_1767_41 = T_9080;
assign T_1767_42 = T_9220;
assign T_1767_43 = T_8300;
assign T_1767_44 = T_7960;
assign T_1767_45 = T_7660;
assign T_1767_46 = T_9160;
assign T_1767_47 = T_8520;
assign T_1767_48 = T_8940;
assign T_1767_49 = T_9240;
assign T_1772_0 = 1'h1;
assign T_1772_1 = 1'h1;
assign T_1772_2 = 1'h1;
assign T_1772_3 = 1'h1;
assign T_1772_4 = 1'h1;
assign T_1772_5 = 1'h1;
assign T_1772_6 = 1'h1;
assign T_1772_7 = 1'h1;
assign T_1772_8 = 1'h1;
assign T_1772_9 = 1'h1;
assign T_1772_10 = 1'h1;
assign T_1772_11 = 1'h1;
assign T_1772_12 = 1'h1;
assign T_1772_13 = 1'h1;
assign T_1772_14 = 1'h1;
assign T_1772_15 = 1'h1;
assign T_1772_16 = 1'h1;
assign T_1772_17 = 1'h1;
assign T_1772_18 = 1'h1;
assign T_1772_19 = 1'h1;
assign T_1772_20 = 1'h1;
assign T_1772_21 = 1'h1;
assign T_1772_22 = 1'h1;
assign T_1772_23 = 1'h1;
assign T_1772_24 = 1'h1;
assign T_1772_25 = 1'h1;
assign T_1772_26 = 1'h1;
assign T_1772_27 = 1'h1;
assign T_1772_28 = 1'h1;
assign T_1772_29 = 1'h1;
assign T_1772_30 = 1'h1;
assign T_1772_31 = 1'h1;
assign T_1772_32 = 1'h1;
assign T_1772_33 = 1'h1;
assign T_1772_34 = 1'h1;
assign T_1772_35 = 1'h1;
assign T_1772_36 = 1'h1;
assign T_1772_37 = 1'h1;
assign T_1772_38 = 1'h1;
assign T_1772_39 = 1'h1;
assign T_1772_40 = 1'h1;
assign T_1772_41 = 1'h1;
assign T_1772_42 = 1'h1;
assign T_1772_43 = 1'h1;
assign T_1772_44 = 1'h1;
assign T_1772_45 = 1'h1;
assign T_1772_46 = 1'h1;
assign T_1772_47 = 1'h1;
assign T_1772_48 = 1'h1;
assign T_1772_49 = 1'h1;
assign T_1777_0 = 1'h1;
assign T_1777_1 = 1'h1;
assign T_1777_2 = 1'h1;
assign T_1777_3 = 1'h1;
assign T_1777_4 = 1'h1;
assign T_1777_5 = 1'h1;
assign T_1777_6 = 1'h1;
assign T_1777_7 = 1'h1;
assign T_1777_8 = 1'h1;
assign T_1777_9 = 1'h1;
assign T_1777_10 = 1'h1;
assign T_1777_11 = 1'h1;
assign T_1777_12 = 1'h1;
assign T_1777_13 = 1'h1;
assign T_1777_14 = 1'h1;
assign T_1777_15 = 1'h1;
assign T_1777_16 = 1'h1;
assign T_1777_17 = 1'h1;
assign T_1777_18 = 1'h1;
assign T_1777_19 = 1'h1;
assign T_1777_20 = 1'h1;
assign T_1777_21 = 1'h1;
assign T_1777_22 = 1'h1;
assign T_1777_23 = 1'h1;
assign T_1777_24 = 1'h1;
assign T_1777_25 = 1'h1;
assign T_1777_26 = 1'h1;
assign T_1777_27 = 1'h1;
assign T_1777_28 = 1'h1;
assign T_1777_29 = 1'h1;
assign T_1777_30 = 1'h1;
assign T_1777_31 = 1'h1;
assign T_1777_32 = 1'h1;
assign T_1777_33 = 1'h1;
assign T_1777_34 = 1'h1;
assign T_1777_35 = 1'h1;
assign T_1777_36 = 1'h1;
assign T_1777_37 = 1'h1;
assign T_1777_38 = 1'h1;
assign T_1777_39 = 1'h1;
assign T_1777_40 = 1'h1;
assign T_1777_41 = 1'h1;
assign T_1777_42 = 1'h1;
assign T_1777_43 = 1'h1;
assign T_1777_44 = 1'h1;
assign T_1777_45 = 1'h1;
assign T_1777_46 = 1'h1;
assign T_1777_47 = 1'h1;
assign T_1777_48 = 1'h1;
assign T_1777_49 = 1'h1;
assign T_1782_0 = 1'h1;
assign T_1782_1 = 1'h1;
assign T_1782_2 = 1'h1;
assign T_1782_3 = 1'h1;
assign T_1782_4 = 1'h1;
assign T_1782_5 = 1'h1;
assign T_1782_6 = 1'h1;
assign T_1782_7 = 1'h1;
assign T_1782_8 = 1'h1;
assign T_1782_9 = 1'h1;
assign T_1782_10 = 1'h1;
assign T_1782_11 = 1'h1;
assign T_1782_12 = 1'h1;
assign T_1782_13 = 1'h1;
assign T_1782_14 = 1'h1;
assign T_1782_15 = 1'h1;
assign T_1782_16 = 1'h1;
assign T_1782_17 = 1'h1;
assign T_1782_18 = 1'h1;
assign T_1782_19 = 1'h1;
assign T_1782_20 = 1'h1;
assign T_1782_21 = 1'h1;
assign T_1782_22 = 1'h1;
assign T_1782_23 = 1'h1;
assign T_1782_24 = 1'h1;
assign T_1782_25 = 1'h1;
assign T_1782_26 = 1'h1;
assign T_1782_27 = 1'h1;
assign T_1782_28 = 1'h1;
assign T_1782_29 = 1'h1;
assign T_1782_30 = 1'h1;
assign T_1782_31 = 1'h1;
assign T_1782_32 = 1'h1;
assign T_1782_33 = 1'h1;
assign T_1782_34 = 1'h1;
assign T_1782_35 = 1'h1;
assign T_1782_36 = 1'h1;
assign T_1782_37 = 1'h1;
assign T_1782_38 = 1'h1;
assign T_1782_39 = 1'h1;
assign T_1782_40 = 1'h1;
assign T_1782_41 = 1'h1;
assign T_1782_42 = 1'h1;
assign T_1782_43 = 1'h1;
assign T_1782_44 = 1'h1;
assign T_1782_45 = 1'h1;
assign T_1782_46 = 1'h1;
assign T_1782_47 = 1'h1;
assign T_1782_48 = 1'h1;
assign T_1782_49 = 1'h1;
assign T_1787_0 = 1'h1;
assign T_1787_1 = 1'h1;
assign T_1787_2 = 1'h1;
assign T_1787_3 = 1'h1;
assign T_1787_4 = 1'h1;
assign T_1787_5 = 1'h1;
assign T_1787_6 = 1'h1;
assign T_1787_7 = 1'h1;
assign T_1787_8 = 1'h1;
assign T_1787_9 = 1'h1;
assign T_1787_10 = 1'h1;
assign T_1787_11 = 1'h1;
assign T_1787_12 = 1'h1;
assign T_1787_13 = 1'h1;
assign T_1787_14 = 1'h1;
assign T_1787_15 = 1'h1;
assign T_1787_16 = 1'h1;
assign T_1787_17 = 1'h1;
assign T_1787_18 = 1'h1;
assign T_1787_19 = 1'h1;
assign T_1787_20 = 1'h1;
assign T_1787_21 = 1'h1;
assign T_1787_22 = 1'h1;
assign T_1787_23 = 1'h1;
assign T_1787_24 = 1'h1;
assign T_1787_25 = 1'h1;
assign T_1787_26 = 1'h1;
assign T_1787_27 = 1'h1;
assign T_1787_28 = 1'h1;
assign T_1787_29 = 1'h1;
assign T_1787_30 = 1'h1;
assign T_1787_31 = 1'h1;
assign T_1787_32 = 1'h1;
assign T_1787_33 = 1'h1;
assign T_1787_34 = 1'h1;
assign T_1787_35 = 1'h1;
assign T_1787_36 = 1'h1;
assign T_1787_37 = 1'h1;
assign T_1787_38 = 1'h1;
assign T_1787_39 = 1'h1;
assign T_1787_40 = 1'h1;
assign T_1787_41 = 1'h1;
assign T_1787_42 = 1'h1;
assign T_1787_43 = 1'h1;
assign T_1787_44 = 1'h1;
assign T_1787_45 = 1'h1;
assign T_1787_46 = 1'h1;
assign T_1787_47 = 1'h1;
assign T_1787_48 = 1'h1;
assign T_1787_49 = 1'h1;
assign T_1792_0 = T_8964;
assign T_1792_1 = T_7584;
assign T_1792_2 = T_8424;
assign T_1792_3 = T_8064;
assign T_1792_4 = T_8324;
assign T_1792_5 = T_7984;
assign T_1792_6 = T_8504;
assign T_1792_7 = T_9144;
assign T_1792_8 = T_9064;
assign T_1792_9 = T_7704;
assign T_1792_10 = T_8344;
assign T_1792_11 = T_8984;
assign T_1792_12 = T_8244;
assign T_1792_13 = T_8884;
assign T_1792_14 = T_9124;
assign T_1792_15 = T_8404;
assign T_1792_16 = T_9044;
assign T_1792_17 = T_7624;
assign T_1792_18 = T_8224;
assign T_1792_19 = T_8264;
assign T_1792_20 = T_8484;
assign T_1792_21 = T_8864;
assign T_1792_22 = T_8024;
assign T_1792_23 = T_8464;
assign T_1792_24 = T_9004;
assign T_1792_25 = T_9204;
assign T_1792_26 = T_9104;
assign T_1792_27 = T_7724;
assign T_1792_28 = T_8364;
assign T_1792_29 = T_8904;
assign T_1792_30 = T_7644;
assign T_1792_31 = T_9184;
assign T_1792_32 = T_8284;
assign T_1792_33 = T_7944;
assign T_1792_34 = T_8924;
assign T_1792_35 = T_7904;
assign T_1792_36 = T_9024;
assign T_1792_37 = T_8444;
assign T_1792_38 = T_8384;
assign T_1792_39 = T_8044;
assign T_1792_40 = T_7744;
assign T_1792_41 = T_9084;
assign T_1792_42 = T_9224;
assign T_1792_43 = T_8304;
assign T_1792_44 = T_7964;
assign T_1792_45 = T_7664;
assign T_1792_46 = T_9164;
assign T_1792_47 = T_8524;
assign T_1792_48 = T_8944;
assign T_1792_49 = T_9244;
assign T_1797_0 = T_8970;
assign T_1797_1 = T_7590;
assign T_1797_2 = T_8430;
assign T_1797_3 = T_8070;
assign T_1797_4 = T_8330;
assign T_1797_5 = T_7990;
assign T_1797_6 = T_8510;
assign T_1797_7 = T_9150;
assign T_1797_8 = T_9070;
assign T_1797_9 = T_7710;
assign T_1797_10 = T_8350;
assign T_1797_11 = T_8990;
assign T_1797_12 = T_8250;
assign T_1797_13 = T_8890;
assign T_1797_14 = T_9130;
assign T_1797_15 = T_8410;
assign T_1797_16 = T_9050;
assign T_1797_17 = T_7630;
assign T_1797_18 = T_8230;
assign T_1797_19 = T_8270;
assign T_1797_20 = T_8490;
assign T_1797_21 = T_8870;
assign T_1797_22 = T_8030;
assign T_1797_23 = T_8470;
assign T_1797_24 = T_9010;
assign T_1797_25 = T_9210;
assign T_1797_26 = T_9110;
assign T_1797_27 = T_7730;
assign T_1797_28 = T_8370;
assign T_1797_29 = T_8910;
assign T_1797_30 = T_7650;
assign T_1797_31 = T_9190;
assign T_1797_32 = T_8290;
assign T_1797_33 = T_7950;
assign T_1797_34 = T_8930;
assign T_1797_35 = T_7910;
assign T_1797_36 = T_9030;
assign T_1797_37 = T_8450;
assign T_1797_38 = T_8390;
assign T_1797_39 = T_8050;
assign T_1797_40 = T_7750;
assign T_1797_41 = T_9090;
assign T_1797_42 = T_9230;
assign T_1797_43 = T_8310;
assign T_1797_44 = T_7970;
assign T_1797_45 = T_7670;
assign T_1797_46 = T_9170;
assign T_1797_47 = T_8530;
assign T_1797_48 = T_8950;
assign T_1797_49 = T_9250;
assign T_2462 = Queue_1_io_deq_bits_mask[0];
assign T_2463 = Queue_1_io_deq_bits_mask[1];
assign T_2464 = Queue_1_io_deq_bits_mask[2];
assign T_2465 = Queue_1_io_deq_bits_mask[3];
assign T_2469 = T_2462 ? 8'hff : 8'h0;
assign T_2473 = T_2463 ? 8'hff : 8'h0;
assign T_2477 = T_2464 ? 8'hff : 8'h0;
assign T_2481 = T_2465 ? 8'hff : 8'h0;
assign T_2482 = {T_2473,T_2469};
assign T_2483 = {T_2481,T_2477};
assign T_2484 = {T_2483,T_2482};
assign T_2496 = ~ T_2484;
assign T_2498 = T_2496 == 32'h0;
assign T_2504 = T_1797_0 & T_2498;
assign T_2505 = Queue_1_io_deq_bits_data;
assign T_2520 = pmu_io_regs_wakeupProgram_5_read;
assign T_2544 = T_1797_1 & T_2498;
assign T_2560 = wdog_io_regs_cfg_read;
assign T_2584 = T_1797_2 & T_2498;
assign GEN_6 = T_2584 ? T_2505 : backupRegs_10;
assign T_2624 = T_1797_3 & T_2498;
assign T_2640 = rtc_io_regs_cmp_0_read;
assign T_2664 = T_1797_4 & T_2498;
assign GEN_7 = T_2664 ? T_2505 : backupRegs_5;
assign T_2704 = T_1797_5 & T_2498;
assign T_2720 = rtc_io_regs_s_read;
assign T_2744 = T_1797_6 & T_2498;
assign GEN_8 = T_2744 ? T_2505 : backupRegs_14;
assign T_2784 = T_1797_7 & T_2498;
assign T_2800 = pmu_io_regs_sleepProgram_6_read;
assign T_2824 = T_1797_8 & T_2498;
assign T_2840 = pmu_io_regs_sleepProgram_2_read;
assign T_2864 = T_1797_9 & T_2498;
assign T_2880 = wdog_io_regs_feed_read;
assign T_2904 = T_1797_10 & T_2498;
assign GEN_9 = T_2904 ? T_2505 : backupRegs_6;
assign T_2944 = T_1797_11 & T_2498;
assign T_2960 = pmu_io_regs_wakeupProgram_6_read;
assign T_2984 = T_1797_12 & T_2498;
assign GEN_10 = T_2984 ? T_2505 : backupRegs_1;
assign T_3024 = T_1797_13 & T_2498;
assign T_3040 = pmu_io_regs_wakeupProgram_1_read;
assign T_3064 = T_1797_14 & T_2498;
assign T_3080 = pmu_io_regs_sleepProgram_5_read;
assign T_3104 = T_1797_15 & T_2498;
assign GEN_11 = T_3104 ? T_2505 : backupRegs_9;
assign T_3144 = T_1797_16 & T_2498;
assign T_3160 = pmu_io_regs_sleepProgram_1_read;
assign T_3184 = T_1797_17 & T_2498;
assign T_3200 = wdog_io_regs_countLo_read;
assign T_3224 = T_1797_18 & T_2498;
assign GEN_12 = T_3224 ? T_2505 : backupRegs_0;
assign T_3264 = T_1797_19 & T_2498;
assign GEN_13 = T_3264 ? T_2505 : backupRegs_2;
assign T_3304 = T_1797_20 & T_2498;
assign GEN_14 = T_3304 ? T_2505 : backupRegs_13;
assign T_3344 = T_1797_21 & T_2498;
assign T_3360 = pmu_io_regs_wakeupProgram_0_read;
assign T_3384 = T_1797_22 & T_2498;
assign T_3400 = rtc_io_regs_feed_read;
assign T_3424 = T_1797_23 & T_2498;
assign GEN_15 = T_3424 ? T_2505 : backupRegs_12;
assign T_3464 = T_1797_24 & T_2498;
assign T_3480 = pmu_io_regs_wakeupProgram_7_read;
assign T_3504 = T_1797_25 & T_2498;
assign T_3520 = pmu_io_regs_cause_read;
assign T_3544 = T_1797_26 & T_2498;
assign T_3560 = pmu_io_regs_sleepProgram_4_read;
assign T_3584 = T_1797_27 & T_2498;
assign T_3600 = wdog_io_regs_key_read;
assign T_3624 = T_1797_28 & T_2498;
assign GEN_16 = T_3624 ? T_2505 : backupRegs_7;
assign T_3664 = T_1797_29 & T_2498;
assign T_3680 = pmu_io_regs_wakeupProgram_2_read;
assign T_3704 = T_1797_30 & T_2498;
assign T_3720 = wdog_io_regs_countHi_read;
assign T_3732 = T_2484[3:0];
assign T_3736 = ~ T_3732;
assign T_3738 = T_3736 == 4'h0;
assign T_3744 = T_1797_31 & T_3738;
assign T_3745 = Queue_1_io_deq_bits_data[3:0];
assign T_3760 = pmu_io_regs_ie_read;
assign T_3784 = T_1797_32 & T_2498;
assign GEN_17 = T_3784 ? T_2505 : backupRegs_3;
assign T_3824 = T_1797_33 & T_2498;
assign T_3840 = rtc_io_regs_countLo_read;
assign T_3864 = T_1797_34 & T_2498;
assign T_3880 = pmu_io_regs_wakeupProgram_3_read;
assign T_3904 = T_1797_35 & T_2498;
assign T_3920 = rtc_io_regs_cfg_read;
assign T_3944 = T_1797_36 & T_2498;
assign T_3960 = pmu_io_regs_sleepProgram_0_read;
assign T_3984 = T_1797_37 & T_2498;
assign GEN_18 = T_3984 ? T_2505 : backupRegs_11;
assign T_4024 = T_1797_38 & T_2498;
assign GEN_19 = T_4024 ? T_2505 : backupRegs_8;
assign T_4064 = T_1797_39 & T_2498;
assign T_4080 = rtc_io_regs_key_read;
assign T_4092 = T_2484[15:0];
assign T_4096 = ~ T_4092;
assign T_4098 = T_4096 == 16'h0;
assign T_4104 = T_1797_40 & T_4098;
assign T_4105 = Queue_1_io_deq_bits_data[15:0];
assign T_4120 = wdog_io_regs_cmp_0_read;
assign T_4144 = T_1797_41 & T_2498;
assign T_4160 = pmu_io_regs_sleepProgram_3_read;
assign T_4184 = T_1797_42 & T_2498;
assign T_4200 = pmu_io_regs_sleep_read;
assign T_4224 = T_1797_43 & T_2498;
assign GEN_20 = T_4224 ? T_2505 : backupRegs_4;
assign T_4264 = T_1797_44 & T_2498;
assign T_4280 = rtc_io_regs_countHi_read;
assign T_4304 = T_1797_45 & T_4098;
assign T_4320 = wdog_io_regs_s_read;
assign T_4344 = T_1797_46 & T_2498;
assign T_4360 = pmu_io_regs_sleepProgram_7_read;
assign T_4384 = T_1797_47 & T_2498;
assign GEN_21 = T_4384 ? T_2505 : backupRegs_15;
assign T_4424 = T_1797_48 & T_2498;
assign T_4440 = pmu_io_regs_wakeupProgram_4_read;
assign T_4464 = T_1797_49 & T_2498;
assign T_4480 = pmu_io_regs_key_read;
assign T_4486 = T_1322 == 1'h0;
assign T_4488 = T_4486 | T_1772_1;
assign T_4493 = T_1466 == 1'h0;
assign T_4495 = T_4493 | T_1772_17;
assign T_4497 = T_1583 == 1'h0;
assign T_4499 = T_4497 | T_1772_30;
assign T_4501 = T_1718 == 1'h0;
assign T_4503 = T_4501 | T_1772_45;
assign T_4508 = T_1394 == 1'h0;
assign T_4510 = T_4508 | T_1772_9;
assign T_4512 = T_1556 == 1'h0;
assign T_4514 = T_4512 | T_1772_27;
assign T_4516 = T_1673 == 1'h0;
assign T_4518 = T_4516 | T_1772_40;
assign T_4541 = T_1628 == 1'h0;
assign T_4543 = T_4541 | T_1772_35;
assign T_4548 = T_1610 == 1'h0;
assign T_4550 = T_4548 | T_1772_33;
assign T_4552 = T_1709 == 1'h0;
assign T_4554 = T_4552 | T_1772_44;
assign T_4556 = T_1358 == 1'h0;
assign T_4558 = T_4556 | T_1772_5;
assign T_4563 = T_1511 == 1'h0;
assign T_4565 = T_4563 | T_1772_22;
assign T_4567 = T_1664 == 1'h0;
assign T_4569 = T_4567 | T_1772_39;
assign T_4571 = T_1340 == 1'h0;
assign T_4573 = T_4571 | T_1772_3;
assign T_4596 = T_1475 == 1'h0;
assign T_4598 = T_4596 | T_1772_18;
assign T_4600 = T_1421 == 1'h0;
assign T_4602 = T_4600 | T_1772_12;
assign T_4604 = T_1484 == 1'h0;
assign T_4606 = T_4604 | T_1772_19;
assign T_4608 = T_1601 == 1'h0;
assign T_4610 = T_4608 | T_1772_32;
assign T_4612 = T_1700 == 1'h0;
assign T_4614 = T_4612 | T_1772_43;
assign T_4616 = T_1349 == 1'h0;
assign T_4618 = T_4616 | T_1772_4;
assign T_4620 = T_1403 == 1'h0;
assign T_4622 = T_4620 | T_1772_10;
assign T_4624 = T_1565 == 1'h0;
assign T_4626 = T_4624 | T_1772_28;
assign T_4628 = T_1655 == 1'h0;
assign T_4630 = T_4628 | T_1772_38;
assign T_4632 = T_1448 == 1'h0;
assign T_4634 = T_4632 | T_1772_15;
assign T_4636 = T_1331 == 1'h0;
assign T_4638 = T_4636 | T_1772_2;
assign T_4640 = T_1646 == 1'h0;
assign T_4642 = T_4640 | T_1772_37;
assign T_4644 = T_1520 == 1'h0;
assign T_4646 = T_4644 | T_1772_23;
assign T_4648 = T_1493 == 1'h0;
assign T_4650 = T_4648 | T_1772_20;
assign T_4652 = T_1367 == 1'h0;
assign T_4654 = T_4652 | T_1772_6;
assign T_4656 = T_1736 == 1'h0;
assign T_4658 = T_4656 | T_1772_47;
assign T_4708 = T_1502 == 1'h0;
assign T_4710 = T_4708 | T_1772_21;
assign T_4712 = T_1430 == 1'h0;
assign T_4714 = T_4712 | T_1772_13;
assign T_4716 = T_1574 == 1'h0;
assign T_4718 = T_4716 | T_1772_29;
assign T_4720 = T_1619 == 1'h0;
assign T_4722 = T_4720 | T_1772_34;
assign T_4724 = T_1745 == 1'h0;
assign T_4726 = T_4724 | T_1772_48;
assign T_4728 = T_1313 == 1'h0;
assign T_4730 = T_4728 | T_1772_0;
assign T_4732 = T_1412 == 1'h0;
assign T_4734 = T_4732 | T_1772_11;
assign T_4736 = T_1529 == 1'h0;
assign T_4738 = T_4736 | T_1772_24;
assign T_4740 = T_1637 == 1'h0;
assign T_4742 = T_4740 | T_1772_36;
assign T_4744 = T_1457 == 1'h0;
assign T_4746 = T_4744 | T_1772_16;
assign T_4748 = T_1385 == 1'h0;
assign T_4750 = T_4748 | T_1772_8;
assign T_4752 = T_1682 == 1'h0;
assign T_4754 = T_4752 | T_1772_41;
assign T_4756 = T_1547 == 1'h0;
assign T_4758 = T_4756 | T_1772_26;
assign T_4760 = T_1439 == 1'h0;
assign T_4762 = T_4760 | T_1772_14;
assign T_4764 = T_1376 == 1'h0;
assign T_4766 = T_4764 | T_1772_7;
assign T_4768 = T_1727 == 1'h0;
assign T_4770 = T_4768 | T_1772_46;
assign T_4772 = T_1592 == 1'h0;
assign T_4774 = T_4772 | T_1772_31;
assign T_4776 = T_1538 == 1'h0;
assign T_4778 = T_4776 | T_1772_25;
assign T_4780 = T_1691 == 1'h0;
assign T_4782 = T_4780 | T_1772_42;
assign T_4784 = T_1754 == 1'h0;
assign T_4786 = T_4784 | T_1772_49;
assign T_5050_0 = T_4488;
assign T_5050_1 = 1'h1;
assign T_5050_2 = T_4495;
assign T_5050_3 = T_4499;
assign T_5050_4 = T_4503;
assign T_5050_5 = 1'h1;
assign T_5050_6 = T_4510;
assign T_5050_7 = T_4514;
assign T_5050_8 = T_4518;
assign T_5050_9 = 1'h1;
assign T_5050_10 = 1'h1;
assign T_5050_11 = 1'h1;
assign T_5050_12 = 1'h1;
assign T_5050_13 = 1'h1;
assign T_5050_14 = 1'h1;
assign T_5050_15 = 1'h1;
assign T_5050_16 = T_4543;
assign T_5050_17 = 1'h1;
assign T_5050_18 = T_4550;
assign T_5050_19 = T_4554;
assign T_5050_20 = T_4558;
assign T_5050_21 = 1'h1;
assign T_5050_22 = T_4565;
assign T_5050_23 = T_4569;
assign T_5050_24 = T_4573;
assign T_5050_25 = 1'h1;
assign T_5050_26 = 1'h1;
assign T_5050_27 = 1'h1;
assign T_5050_28 = 1'h1;
assign T_5050_29 = 1'h1;
assign T_5050_30 = 1'h1;
assign T_5050_31 = 1'h1;
assign T_5050_32 = T_4598;
assign T_5050_33 = T_4602;
assign T_5050_34 = T_4606;
assign T_5050_35 = T_4610;
assign T_5050_36 = T_4614;
assign T_5050_37 = T_4618;
assign T_5050_38 = T_4622;
assign T_5050_39 = T_4626;
assign T_5050_40 = T_4630;
assign T_5050_41 = T_4634;
assign T_5050_42 = T_4638;
assign T_5050_43 = T_4642;
assign T_5050_44 = T_4646;
assign T_5050_45 = T_4650;
assign T_5050_46 = T_4654;
assign T_5050_47 = T_4658;
assign T_5050_48 = 1'h1;
assign T_5050_49 = 1'h1;
assign T_5050_50 = 1'h1;
assign T_5050_51 = 1'h1;
assign T_5050_52 = 1'h1;
assign T_5050_53 = 1'h1;
assign T_5050_54 = 1'h1;
assign T_5050_55 = 1'h1;
assign T_5050_56 = 1'h1;
assign T_5050_57 = 1'h1;
assign T_5050_58 = 1'h1;
assign T_5050_59 = 1'h1;
assign T_5050_60 = 1'h1;
assign T_5050_61 = 1'h1;
assign T_5050_62 = 1'h1;
assign T_5050_63 = 1'h1;
assign T_5050_64 = T_4710;
assign T_5050_65 = T_4714;
assign T_5050_66 = T_4718;
assign T_5050_67 = T_4722;
assign T_5050_68 = T_4726;
assign T_5050_69 = T_4730;
assign T_5050_70 = T_4734;
assign T_5050_71 = T_4738;
assign T_5050_72 = T_4742;
assign T_5050_73 = T_4746;
assign T_5050_74 = T_4750;
assign T_5050_75 = T_4754;
assign T_5050_76 = T_4758;
assign T_5050_77 = T_4762;
assign T_5050_78 = T_4766;
assign T_5050_79 = T_4770;
assign T_5050_80 = T_4774;
assign T_5050_81 = T_4778;
assign T_5050_82 = T_4782;
assign T_5050_83 = T_4786;
assign T_5050_84 = 1'h1;
assign T_5050_85 = 1'h1;
assign T_5050_86 = 1'h1;
assign T_5050_87 = 1'h1;
assign T_5050_88 = 1'h1;
assign T_5050_89 = 1'h1;
assign T_5050_90 = 1'h1;
assign T_5050_91 = 1'h1;
assign T_5050_92 = 1'h1;
assign T_5050_93 = 1'h1;
assign T_5050_94 = 1'h1;
assign T_5050_95 = 1'h1;
assign T_5050_96 = 1'h1;
assign T_5050_97 = 1'h1;
assign T_5050_98 = 1'h1;
assign T_5050_99 = 1'h1;
assign T_5050_100 = 1'h1;
assign T_5050_101 = 1'h1;
assign T_5050_102 = 1'h1;
assign T_5050_103 = 1'h1;
assign T_5050_104 = 1'h1;
assign T_5050_105 = 1'h1;
assign T_5050_106 = 1'h1;
assign T_5050_107 = 1'h1;
assign T_5050_108 = 1'h1;
assign T_5050_109 = 1'h1;
assign T_5050_110 = 1'h1;
assign T_5050_111 = 1'h1;
assign T_5050_112 = 1'h1;
assign T_5050_113 = 1'h1;
assign T_5050_114 = 1'h1;
assign T_5050_115 = 1'h1;
assign T_5050_116 = 1'h1;
assign T_5050_117 = 1'h1;
assign T_5050_118 = 1'h1;
assign T_5050_119 = 1'h1;
assign T_5050_120 = 1'h1;
assign T_5050_121 = 1'h1;
assign T_5050_122 = 1'h1;
assign T_5050_123 = 1'h1;
assign T_5050_124 = 1'h1;
assign T_5050_125 = 1'h1;
assign T_5050_126 = 1'h1;
assign T_5050_127 = 1'h1;
assign T_5184 = T_4486 | T_1777_1;
assign T_5191 = T_4493 | T_1777_17;
assign T_5195 = T_4497 | T_1777_30;
assign T_5199 = T_4501 | T_1777_45;
assign T_5206 = T_4508 | T_1777_9;
assign T_5210 = T_4512 | T_1777_27;
assign T_5214 = T_4516 | T_1777_40;
assign T_5239 = T_4541 | T_1777_35;
assign T_5246 = T_4548 | T_1777_33;
assign T_5250 = T_4552 | T_1777_44;
assign T_5254 = T_4556 | T_1777_5;
assign T_5261 = T_4563 | T_1777_22;
assign T_5265 = T_4567 | T_1777_39;
assign T_5269 = T_4571 | T_1777_3;
assign T_5294 = T_4596 | T_1777_18;
assign T_5298 = T_4600 | T_1777_12;
assign T_5302 = T_4604 | T_1777_19;
assign T_5306 = T_4608 | T_1777_32;
assign T_5310 = T_4612 | T_1777_43;
assign T_5314 = T_4616 | T_1777_4;
assign T_5318 = T_4620 | T_1777_10;
assign T_5322 = T_4624 | T_1777_28;
assign T_5326 = T_4628 | T_1777_38;
assign T_5330 = T_4632 | T_1777_15;
assign T_5334 = T_4636 | T_1777_2;
assign T_5338 = T_4640 | T_1777_37;
assign T_5342 = T_4644 | T_1777_23;
assign T_5346 = T_4648 | T_1777_20;
assign T_5350 = T_4652 | T_1777_6;
assign T_5354 = T_4656 | T_1777_47;
assign T_5406 = T_4708 | T_1777_21;
assign T_5410 = T_4712 | T_1777_13;
assign T_5414 = T_4716 | T_1777_29;
assign T_5418 = T_4720 | T_1777_34;
assign T_5422 = T_4724 | T_1777_48;
assign T_5426 = T_4728 | T_1777_0;
assign T_5430 = T_4732 | T_1777_11;
assign T_5434 = T_4736 | T_1777_24;
assign T_5438 = T_4740 | T_1777_36;
assign T_5442 = T_4744 | T_1777_16;
assign T_5446 = T_4748 | T_1777_8;
assign T_5450 = T_4752 | T_1777_41;
assign T_5454 = T_4756 | T_1777_26;
assign T_5458 = T_4760 | T_1777_14;
assign T_5462 = T_4764 | T_1777_7;
assign T_5466 = T_4768 | T_1777_46;
assign T_5470 = T_4772 | T_1777_31;
assign T_5474 = T_4776 | T_1777_25;
assign T_5478 = T_4780 | T_1777_42;
assign T_5482 = T_4784 | T_1777_49;
assign T_5746_0 = T_5184;
assign T_5746_1 = 1'h1;
assign T_5746_2 = T_5191;
assign T_5746_3 = T_5195;
assign T_5746_4 = T_5199;
assign T_5746_5 = 1'h1;
assign T_5746_6 = T_5206;
assign T_5746_7 = T_5210;
assign T_5746_8 = T_5214;
assign T_5746_9 = 1'h1;
assign T_5746_10 = 1'h1;
assign T_5746_11 = 1'h1;
assign T_5746_12 = 1'h1;
assign T_5746_13 = 1'h1;
assign T_5746_14 = 1'h1;
assign T_5746_15 = 1'h1;
assign T_5746_16 = T_5239;
assign T_5746_17 = 1'h1;
assign T_5746_18 = T_5246;
assign T_5746_19 = T_5250;
assign T_5746_20 = T_5254;
assign T_5746_21 = 1'h1;
assign T_5746_22 = T_5261;
assign T_5746_23 = T_5265;
assign T_5746_24 = T_5269;
assign T_5746_25 = 1'h1;
assign T_5746_26 = 1'h1;
assign T_5746_27 = 1'h1;
assign T_5746_28 = 1'h1;
assign T_5746_29 = 1'h1;
assign T_5746_30 = 1'h1;
assign T_5746_31 = 1'h1;
assign T_5746_32 = T_5294;
assign T_5746_33 = T_5298;
assign T_5746_34 = T_5302;
assign T_5746_35 = T_5306;
assign T_5746_36 = T_5310;
assign T_5746_37 = T_5314;
assign T_5746_38 = T_5318;
assign T_5746_39 = T_5322;
assign T_5746_40 = T_5326;
assign T_5746_41 = T_5330;
assign T_5746_42 = T_5334;
assign T_5746_43 = T_5338;
assign T_5746_44 = T_5342;
assign T_5746_45 = T_5346;
assign T_5746_46 = T_5350;
assign T_5746_47 = T_5354;
assign T_5746_48 = 1'h1;
assign T_5746_49 = 1'h1;
assign T_5746_50 = 1'h1;
assign T_5746_51 = 1'h1;
assign T_5746_52 = 1'h1;
assign T_5746_53 = 1'h1;
assign T_5746_54 = 1'h1;
assign T_5746_55 = 1'h1;
assign T_5746_56 = 1'h1;
assign T_5746_57 = 1'h1;
assign T_5746_58 = 1'h1;
assign T_5746_59 = 1'h1;
assign T_5746_60 = 1'h1;
assign T_5746_61 = 1'h1;
assign T_5746_62 = 1'h1;
assign T_5746_63 = 1'h1;
assign T_5746_64 = T_5406;
assign T_5746_65 = T_5410;
assign T_5746_66 = T_5414;
assign T_5746_67 = T_5418;
assign T_5746_68 = T_5422;
assign T_5746_69 = T_5426;
assign T_5746_70 = T_5430;
assign T_5746_71 = T_5434;
assign T_5746_72 = T_5438;
assign T_5746_73 = T_5442;
assign T_5746_74 = T_5446;
assign T_5746_75 = T_5450;
assign T_5746_76 = T_5454;
assign T_5746_77 = T_5458;
assign T_5746_78 = T_5462;
assign T_5746_79 = T_5466;
assign T_5746_80 = T_5470;
assign T_5746_81 = T_5474;
assign T_5746_82 = T_5478;
assign T_5746_83 = T_5482;
assign T_5746_84 = 1'h1;
assign T_5746_85 = 1'h1;
assign T_5746_86 = 1'h1;
assign T_5746_87 = 1'h1;
assign T_5746_88 = 1'h1;
assign T_5746_89 = 1'h1;
assign T_5746_90 = 1'h1;
assign T_5746_91 = 1'h1;
assign T_5746_92 = 1'h1;
assign T_5746_93 = 1'h1;
assign T_5746_94 = 1'h1;
assign T_5746_95 = 1'h1;
assign T_5746_96 = 1'h1;
assign T_5746_97 = 1'h1;
assign T_5746_98 = 1'h1;
assign T_5746_99 = 1'h1;
assign T_5746_100 = 1'h1;
assign T_5746_101 = 1'h1;
assign T_5746_102 = 1'h1;
assign T_5746_103 = 1'h1;
assign T_5746_104 = 1'h1;
assign T_5746_105 = 1'h1;
assign T_5746_106 = 1'h1;
assign T_5746_107 = 1'h1;
assign T_5746_108 = 1'h1;
assign T_5746_109 = 1'h1;
assign T_5746_110 = 1'h1;
assign T_5746_111 = 1'h1;
assign T_5746_112 = 1'h1;
assign T_5746_113 = 1'h1;
assign T_5746_114 = 1'h1;
assign T_5746_115 = 1'h1;
assign T_5746_116 = 1'h1;
assign T_5746_117 = 1'h1;
assign T_5746_118 = 1'h1;
assign T_5746_119 = 1'h1;
assign T_5746_120 = 1'h1;
assign T_5746_121 = 1'h1;
assign T_5746_122 = 1'h1;
assign T_5746_123 = 1'h1;
assign T_5746_124 = 1'h1;
assign T_5746_125 = 1'h1;
assign T_5746_126 = 1'h1;
assign T_5746_127 = 1'h1;
assign T_5878 = T_1326 == 1'h0;
assign T_5880 = T_5878 | T_1782_1;
assign T_5885 = T_1470 == 1'h0;
assign T_5887 = T_5885 | T_1782_17;
assign T_5889 = T_1587 == 1'h0;
assign T_5891 = T_5889 | T_1782_30;
assign T_5893 = T_1722 == 1'h0;
assign T_5895 = T_5893 | T_1782_45;
assign T_5900 = T_1398 == 1'h0;
assign T_5902 = T_5900 | T_1782_9;
assign T_5904 = T_1560 == 1'h0;
assign T_5906 = T_5904 | T_1782_27;
assign T_5908 = T_1677 == 1'h0;
assign T_5910 = T_5908 | T_1782_40;
assign T_5933 = T_1632 == 1'h0;
assign T_5935 = T_5933 | T_1782_35;
assign T_5940 = T_1614 == 1'h0;
assign T_5942 = T_5940 | T_1782_33;
assign T_5944 = T_1713 == 1'h0;
assign T_5946 = T_5944 | T_1782_44;
assign T_5948 = T_1362 == 1'h0;
assign T_5950 = T_5948 | T_1782_5;
assign T_5955 = T_1515 == 1'h0;
assign T_5957 = T_5955 | T_1782_22;
assign T_5959 = T_1668 == 1'h0;
assign T_5961 = T_5959 | T_1782_39;
assign T_5963 = T_1344 == 1'h0;
assign T_5965 = T_5963 | T_1782_3;
assign T_5988 = T_1479 == 1'h0;
assign T_5990 = T_5988 | T_1782_18;
assign T_5992 = T_1425 == 1'h0;
assign T_5994 = T_5992 | T_1782_12;
assign T_5996 = T_1488 == 1'h0;
assign T_5998 = T_5996 | T_1782_19;
assign T_6000 = T_1605 == 1'h0;
assign T_6002 = T_6000 | T_1782_32;
assign T_6004 = T_1704 == 1'h0;
assign T_6006 = T_6004 | T_1782_43;
assign T_6008 = T_1353 == 1'h0;
assign T_6010 = T_6008 | T_1782_4;
assign T_6012 = T_1407 == 1'h0;
assign T_6014 = T_6012 | T_1782_10;
assign T_6016 = T_1569 == 1'h0;
assign T_6018 = T_6016 | T_1782_28;
assign T_6020 = T_1659 == 1'h0;
assign T_6022 = T_6020 | T_1782_38;
assign T_6024 = T_1452 == 1'h0;
assign T_6026 = T_6024 | T_1782_15;
assign T_6028 = T_1335 == 1'h0;
assign T_6030 = T_6028 | T_1782_2;
assign T_6032 = T_1650 == 1'h0;
assign T_6034 = T_6032 | T_1782_37;
assign T_6036 = T_1524 == 1'h0;
assign T_6038 = T_6036 | T_1782_23;
assign T_6040 = T_1497 == 1'h0;
assign T_6042 = T_6040 | T_1782_20;
assign T_6044 = T_1371 == 1'h0;
assign T_6046 = T_6044 | T_1782_6;
assign T_6048 = T_1740 == 1'h0;
assign T_6050 = T_6048 | T_1782_47;
assign T_6100 = T_1506 == 1'h0;
assign T_6102 = T_6100 | T_1782_21;
assign T_6104 = T_1434 == 1'h0;
assign T_6106 = T_6104 | T_1782_13;
assign T_6108 = T_1578 == 1'h0;
assign T_6110 = T_6108 | T_1782_29;
assign T_6112 = T_1623 == 1'h0;
assign T_6114 = T_6112 | T_1782_34;
assign T_6116 = T_1749 == 1'h0;
assign T_6118 = T_6116 | T_1782_48;
assign T_6120 = T_1317 == 1'h0;
assign T_6122 = T_6120 | T_1782_0;
assign T_6124 = T_1416 == 1'h0;
assign T_6126 = T_6124 | T_1782_11;
assign T_6128 = T_1533 == 1'h0;
assign T_6130 = T_6128 | T_1782_24;
assign T_6132 = T_1641 == 1'h0;
assign T_6134 = T_6132 | T_1782_36;
assign T_6136 = T_1461 == 1'h0;
assign T_6138 = T_6136 | T_1782_16;
assign T_6140 = T_1389 == 1'h0;
assign T_6142 = T_6140 | T_1782_8;
assign T_6144 = T_1686 == 1'h0;
assign T_6146 = T_6144 | T_1782_41;
assign T_6148 = T_1551 == 1'h0;
assign T_6150 = T_6148 | T_1782_26;
assign T_6152 = T_1443 == 1'h0;
assign T_6154 = T_6152 | T_1782_14;
assign T_6156 = T_1380 == 1'h0;
assign T_6158 = T_6156 | T_1782_7;
assign T_6160 = T_1731 == 1'h0;
assign T_6162 = T_6160 | T_1782_46;
assign T_6164 = T_1596 == 1'h0;
assign T_6166 = T_6164 | T_1782_31;
assign T_6168 = T_1542 == 1'h0;
assign T_6170 = T_6168 | T_1782_25;
assign T_6172 = T_1695 == 1'h0;
assign T_6174 = T_6172 | T_1782_42;
assign T_6176 = T_1758 == 1'h0;
assign T_6178 = T_6176 | T_1782_49;
assign T_6442_0 = T_5880;
assign T_6442_1 = 1'h1;
assign T_6442_2 = T_5887;
assign T_6442_3 = T_5891;
assign T_6442_4 = T_5895;
assign T_6442_5 = 1'h1;
assign T_6442_6 = T_5902;
assign T_6442_7 = T_5906;
assign T_6442_8 = T_5910;
assign T_6442_9 = 1'h1;
assign T_6442_10 = 1'h1;
assign T_6442_11 = 1'h1;
assign T_6442_12 = 1'h1;
assign T_6442_13 = 1'h1;
assign T_6442_14 = 1'h1;
assign T_6442_15 = 1'h1;
assign T_6442_16 = T_5935;
assign T_6442_17 = 1'h1;
assign T_6442_18 = T_5942;
assign T_6442_19 = T_5946;
assign T_6442_20 = T_5950;
assign T_6442_21 = 1'h1;
assign T_6442_22 = T_5957;
assign T_6442_23 = T_5961;
assign T_6442_24 = T_5965;
assign T_6442_25 = 1'h1;
assign T_6442_26 = 1'h1;
assign T_6442_27 = 1'h1;
assign T_6442_28 = 1'h1;
assign T_6442_29 = 1'h1;
assign T_6442_30 = 1'h1;
assign T_6442_31 = 1'h1;
assign T_6442_32 = T_5990;
assign T_6442_33 = T_5994;
assign T_6442_34 = T_5998;
assign T_6442_35 = T_6002;
assign T_6442_36 = T_6006;
assign T_6442_37 = T_6010;
assign T_6442_38 = T_6014;
assign T_6442_39 = T_6018;
assign T_6442_40 = T_6022;
assign T_6442_41 = T_6026;
assign T_6442_42 = T_6030;
assign T_6442_43 = T_6034;
assign T_6442_44 = T_6038;
assign T_6442_45 = T_6042;
assign T_6442_46 = T_6046;
assign T_6442_47 = T_6050;
assign T_6442_48 = 1'h1;
assign T_6442_49 = 1'h1;
assign T_6442_50 = 1'h1;
assign T_6442_51 = 1'h1;
assign T_6442_52 = 1'h1;
assign T_6442_53 = 1'h1;
assign T_6442_54 = 1'h1;
assign T_6442_55 = 1'h1;
assign T_6442_56 = 1'h1;
assign T_6442_57 = 1'h1;
assign T_6442_58 = 1'h1;
assign T_6442_59 = 1'h1;
assign T_6442_60 = 1'h1;
assign T_6442_61 = 1'h1;
assign T_6442_62 = 1'h1;
assign T_6442_63 = 1'h1;
assign T_6442_64 = T_6102;
assign T_6442_65 = T_6106;
assign T_6442_66 = T_6110;
assign T_6442_67 = T_6114;
assign T_6442_68 = T_6118;
assign T_6442_69 = T_6122;
assign T_6442_70 = T_6126;
assign T_6442_71 = T_6130;
assign T_6442_72 = T_6134;
assign T_6442_73 = T_6138;
assign T_6442_74 = T_6142;
assign T_6442_75 = T_6146;
assign T_6442_76 = T_6150;
assign T_6442_77 = T_6154;
assign T_6442_78 = T_6158;
assign T_6442_79 = T_6162;
assign T_6442_80 = T_6166;
assign T_6442_81 = T_6170;
assign T_6442_82 = T_6174;
assign T_6442_83 = T_6178;
assign T_6442_84 = 1'h1;
assign T_6442_85 = 1'h1;
assign T_6442_86 = 1'h1;
assign T_6442_87 = 1'h1;
assign T_6442_88 = 1'h1;
assign T_6442_89 = 1'h1;
assign T_6442_90 = 1'h1;
assign T_6442_91 = 1'h1;
assign T_6442_92 = 1'h1;
assign T_6442_93 = 1'h1;
assign T_6442_94 = 1'h1;
assign T_6442_95 = 1'h1;
assign T_6442_96 = 1'h1;
assign T_6442_97 = 1'h1;
assign T_6442_98 = 1'h1;
assign T_6442_99 = 1'h1;
assign T_6442_100 = 1'h1;
assign T_6442_101 = 1'h1;
assign T_6442_102 = 1'h1;
assign T_6442_103 = 1'h1;
assign T_6442_104 = 1'h1;
assign T_6442_105 = 1'h1;
assign T_6442_106 = 1'h1;
assign T_6442_107 = 1'h1;
assign T_6442_108 = 1'h1;
assign T_6442_109 = 1'h1;
assign T_6442_110 = 1'h1;
assign T_6442_111 = 1'h1;
assign T_6442_112 = 1'h1;
assign T_6442_113 = 1'h1;
assign T_6442_114 = 1'h1;
assign T_6442_115 = 1'h1;
assign T_6442_116 = 1'h1;
assign T_6442_117 = 1'h1;
assign T_6442_118 = 1'h1;
assign T_6442_119 = 1'h1;
assign T_6442_120 = 1'h1;
assign T_6442_121 = 1'h1;
assign T_6442_122 = 1'h1;
assign T_6442_123 = 1'h1;
assign T_6442_124 = 1'h1;
assign T_6442_125 = 1'h1;
assign T_6442_126 = 1'h1;
assign T_6442_127 = 1'h1;
assign T_6576 = T_5878 | T_1787_1;
assign T_6583 = T_5885 | T_1787_17;
assign T_6587 = T_5889 | T_1787_30;
assign T_6591 = T_5893 | T_1787_45;
assign T_6598 = T_5900 | T_1787_9;
assign T_6602 = T_5904 | T_1787_27;
assign T_6606 = T_5908 | T_1787_40;
assign T_6631 = T_5933 | T_1787_35;
assign T_6638 = T_5940 | T_1787_33;
assign T_6642 = T_5944 | T_1787_44;
assign T_6646 = T_5948 | T_1787_5;
assign T_6653 = T_5955 | T_1787_22;
assign T_6657 = T_5959 | T_1787_39;
assign T_6661 = T_5963 | T_1787_3;
assign T_6686 = T_5988 | T_1787_18;
assign T_6690 = T_5992 | T_1787_12;
assign T_6694 = T_5996 | T_1787_19;
assign T_6698 = T_6000 | T_1787_32;
assign T_6702 = T_6004 | T_1787_43;
assign T_6706 = T_6008 | T_1787_4;
assign T_6710 = T_6012 | T_1787_10;
assign T_6714 = T_6016 | T_1787_28;
assign T_6718 = T_6020 | T_1787_38;
assign T_6722 = T_6024 | T_1787_15;
assign T_6726 = T_6028 | T_1787_2;
assign T_6730 = T_6032 | T_1787_37;
assign T_6734 = T_6036 | T_1787_23;
assign T_6738 = T_6040 | T_1787_20;
assign T_6742 = T_6044 | T_1787_6;
assign T_6746 = T_6048 | T_1787_47;
assign T_6798 = T_6100 | T_1787_21;
assign T_6802 = T_6104 | T_1787_13;
assign T_6806 = T_6108 | T_1787_29;
assign T_6810 = T_6112 | T_1787_34;
assign T_6814 = T_6116 | T_1787_48;
assign T_6818 = T_6120 | T_1787_0;
assign T_6822 = T_6124 | T_1787_11;
assign T_6826 = T_6128 | T_1787_24;
assign T_6830 = T_6132 | T_1787_36;
assign T_6834 = T_6136 | T_1787_16;
assign T_6838 = T_6140 | T_1787_8;
assign T_6842 = T_6144 | T_1787_41;
assign T_6846 = T_6148 | T_1787_26;
assign T_6850 = T_6152 | T_1787_14;
assign T_6854 = T_6156 | T_1787_7;
assign T_6858 = T_6160 | T_1787_46;
assign T_6862 = T_6164 | T_1787_31;
assign T_6866 = T_6168 | T_1787_25;
assign T_6870 = T_6172 | T_1787_42;
assign T_6874 = T_6176 | T_1787_49;
assign T_7138_0 = T_6576;
assign T_7138_1 = 1'h1;
assign T_7138_2 = T_6583;
assign T_7138_3 = T_6587;
assign T_7138_4 = T_6591;
assign T_7138_5 = 1'h1;
assign T_7138_6 = T_6598;
assign T_7138_7 = T_6602;
assign T_7138_8 = T_6606;
assign T_7138_9 = 1'h1;
assign T_7138_10 = 1'h1;
assign T_7138_11 = 1'h1;
assign T_7138_12 = 1'h1;
assign T_7138_13 = 1'h1;
assign T_7138_14 = 1'h1;
assign T_7138_15 = 1'h1;
assign T_7138_16 = T_6631;
assign T_7138_17 = 1'h1;
assign T_7138_18 = T_6638;
assign T_7138_19 = T_6642;
assign T_7138_20 = T_6646;
assign T_7138_21 = 1'h1;
assign T_7138_22 = T_6653;
assign T_7138_23 = T_6657;
assign T_7138_24 = T_6661;
assign T_7138_25 = 1'h1;
assign T_7138_26 = 1'h1;
assign T_7138_27 = 1'h1;
assign T_7138_28 = 1'h1;
assign T_7138_29 = 1'h1;
assign T_7138_30 = 1'h1;
assign T_7138_31 = 1'h1;
assign T_7138_32 = T_6686;
assign T_7138_33 = T_6690;
assign T_7138_34 = T_6694;
assign T_7138_35 = T_6698;
assign T_7138_36 = T_6702;
assign T_7138_37 = T_6706;
assign T_7138_38 = T_6710;
assign T_7138_39 = T_6714;
assign T_7138_40 = T_6718;
assign T_7138_41 = T_6722;
assign T_7138_42 = T_6726;
assign T_7138_43 = T_6730;
assign T_7138_44 = T_6734;
assign T_7138_45 = T_6738;
assign T_7138_46 = T_6742;
assign T_7138_47 = T_6746;
assign T_7138_48 = 1'h1;
assign T_7138_49 = 1'h1;
assign T_7138_50 = 1'h1;
assign T_7138_51 = 1'h1;
assign T_7138_52 = 1'h1;
assign T_7138_53 = 1'h1;
assign T_7138_54 = 1'h1;
assign T_7138_55 = 1'h1;
assign T_7138_56 = 1'h1;
assign T_7138_57 = 1'h1;
assign T_7138_58 = 1'h1;
assign T_7138_59 = 1'h1;
assign T_7138_60 = 1'h1;
assign T_7138_61 = 1'h1;
assign T_7138_62 = 1'h1;
assign T_7138_63 = 1'h1;
assign T_7138_64 = T_6798;
assign T_7138_65 = T_6802;
assign T_7138_66 = T_6806;
assign T_7138_67 = T_6810;
assign T_7138_68 = T_6814;
assign T_7138_69 = T_6818;
assign T_7138_70 = T_6822;
assign T_7138_71 = T_6826;
assign T_7138_72 = T_6830;
assign T_7138_73 = T_6834;
assign T_7138_74 = T_6838;
assign T_7138_75 = T_6842;
assign T_7138_76 = T_6846;
assign T_7138_77 = T_6850;
assign T_7138_78 = T_6854;
assign T_7138_79 = T_6858;
assign T_7138_80 = T_6862;
assign T_7138_81 = T_6866;
assign T_7138_82 = T_6870;
assign T_7138_83 = T_6874;
assign T_7138_84 = 1'h1;
assign T_7138_85 = 1'h1;
assign T_7138_86 = 1'h1;
assign T_7138_87 = 1'h1;
assign T_7138_88 = 1'h1;
assign T_7138_89 = 1'h1;
assign T_7138_90 = 1'h1;
assign T_7138_91 = 1'h1;
assign T_7138_92 = 1'h1;
assign T_7138_93 = 1'h1;
assign T_7138_94 = 1'h1;
assign T_7138_95 = 1'h1;
assign T_7138_96 = 1'h1;
assign T_7138_97 = 1'h1;
assign T_7138_98 = 1'h1;
assign T_7138_99 = 1'h1;
assign T_7138_100 = 1'h1;
assign T_7138_101 = 1'h1;
assign T_7138_102 = 1'h1;
assign T_7138_103 = 1'h1;
assign T_7138_104 = 1'h1;
assign T_7138_105 = 1'h1;
assign T_7138_106 = 1'h1;
assign T_7138_107 = 1'h1;
assign T_7138_108 = 1'h1;
assign T_7138_109 = 1'h1;
assign T_7138_110 = 1'h1;
assign T_7138_111 = 1'h1;
assign T_7138_112 = 1'h1;
assign T_7138_113 = 1'h1;
assign T_7138_114 = 1'h1;
assign T_7138_115 = 1'h1;
assign T_7138_116 = 1'h1;
assign T_7138_117 = 1'h1;
assign T_7138_118 = 1'h1;
assign T_7138_119 = 1'h1;
assign T_7138_120 = 1'h1;
assign T_7138_121 = 1'h1;
assign T_7138_122 = 1'h1;
assign T_7138_123 = 1'h1;
assign T_7138_124 = 1'h1;
assign T_7138_125 = 1'h1;
assign T_7138_126 = 1'h1;
assign T_7138_127 = 1'h1;
assign T_7269 = T_1028_bits_index[0];
assign T_7270 = T_1028_bits_index[1];
assign T_7271 = T_1028_bits_index[2];
assign T_7272 = T_1028_bits_index[3];
assign T_7273 = T_1028_bits_index[4];
assign T_7274 = T_1028_bits_index[5];
assign T_7275 = T_1028_bits_index[6];
assign T_7279 = {T_7271,T_7270};
assign T_7280 = {T_7279,T_7269};
assign T_7281 = {T_7273,T_7272};
assign T_7282 = {T_7275,T_7274};
assign T_7283 = {T_7282,T_7281};
assign T_7284 = {T_7283,T_7280};
assign T_7285 = Queue_1_io_deq_bits_index[0];
assign T_7286 = Queue_1_io_deq_bits_index[1];
assign T_7287 = Queue_1_io_deq_bits_index[2];
assign T_7288 = Queue_1_io_deq_bits_index[3];
assign T_7289 = Queue_1_io_deq_bits_index[4];
assign T_7290 = Queue_1_io_deq_bits_index[5];
assign T_7291 = Queue_1_io_deq_bits_index[6];
assign T_7295 = {T_7287,T_7286};
assign T_7296 = {T_7295,T_7285};
assign T_7297 = {T_7289,T_7288};
assign T_7298 = {T_7291,T_7290};
assign T_7299 = {T_7298,T_7297};
assign T_7300 = {T_7299,T_7296};
assign GEN_0 = GEN_148;
assign GEN_22 = 7'h1 == T_7284 ? T_5050_1 : T_5050_0;
assign GEN_23 = 7'h2 == T_7284 ? T_5050_2 : GEN_22;
assign GEN_24 = 7'h3 == T_7284 ? T_5050_3 : GEN_23;
assign GEN_25 = 7'h4 == T_7284 ? T_5050_4 : GEN_24;
assign GEN_26 = 7'h5 == T_7284 ? T_5050_5 : GEN_25;
assign GEN_27 = 7'h6 == T_7284 ? T_5050_6 : GEN_26;
assign GEN_28 = 7'h7 == T_7284 ? T_5050_7 : GEN_27;
assign GEN_29 = 7'h8 == T_7284 ? T_5050_8 : GEN_28;
assign GEN_30 = 7'h9 == T_7284 ? T_5050_9 : GEN_29;
assign GEN_31 = 7'ha == T_7284 ? T_5050_10 : GEN_30;
assign GEN_32 = 7'hb == T_7284 ? T_5050_11 : GEN_31;
assign GEN_33 = 7'hc == T_7284 ? T_5050_12 : GEN_32;
assign GEN_34 = 7'hd == T_7284 ? T_5050_13 : GEN_33;
assign GEN_35 = 7'he == T_7284 ? T_5050_14 : GEN_34;
assign GEN_36 = 7'hf == T_7284 ? T_5050_15 : GEN_35;
assign GEN_37 = 7'h10 == T_7284 ? T_5050_16 : GEN_36;
assign GEN_38 = 7'h11 == T_7284 ? T_5050_17 : GEN_37;
assign GEN_39 = 7'h12 == T_7284 ? T_5050_18 : GEN_38;
assign GEN_40 = 7'h13 == T_7284 ? T_5050_19 : GEN_39;
assign GEN_41 = 7'h14 == T_7284 ? T_5050_20 : GEN_40;
assign GEN_42 = 7'h15 == T_7284 ? T_5050_21 : GEN_41;
assign GEN_43 = 7'h16 == T_7284 ? T_5050_22 : GEN_42;
assign GEN_44 = 7'h17 == T_7284 ? T_5050_23 : GEN_43;
assign GEN_45 = 7'h18 == T_7284 ? T_5050_24 : GEN_44;
assign GEN_46 = 7'h19 == T_7284 ? T_5050_25 : GEN_45;
assign GEN_47 = 7'h1a == T_7284 ? T_5050_26 : GEN_46;
assign GEN_48 = 7'h1b == T_7284 ? T_5050_27 : GEN_47;
assign GEN_49 = 7'h1c == T_7284 ? T_5050_28 : GEN_48;
assign GEN_50 = 7'h1d == T_7284 ? T_5050_29 : GEN_49;
assign GEN_51 = 7'h1e == T_7284 ? T_5050_30 : GEN_50;
assign GEN_52 = 7'h1f == T_7284 ? T_5050_31 : GEN_51;
assign GEN_53 = 7'h20 == T_7284 ? T_5050_32 : GEN_52;
assign GEN_54 = 7'h21 == T_7284 ? T_5050_33 : GEN_53;
assign GEN_55 = 7'h22 == T_7284 ? T_5050_34 : GEN_54;
assign GEN_56 = 7'h23 == T_7284 ? T_5050_35 : GEN_55;
assign GEN_57 = 7'h24 == T_7284 ? T_5050_36 : GEN_56;
assign GEN_58 = 7'h25 == T_7284 ? T_5050_37 : GEN_57;
assign GEN_59 = 7'h26 == T_7284 ? T_5050_38 : GEN_58;
assign GEN_60 = 7'h27 == T_7284 ? T_5050_39 : GEN_59;
assign GEN_61 = 7'h28 == T_7284 ? T_5050_40 : GEN_60;
assign GEN_62 = 7'h29 == T_7284 ? T_5050_41 : GEN_61;
assign GEN_63 = 7'h2a == T_7284 ? T_5050_42 : GEN_62;
assign GEN_64 = 7'h2b == T_7284 ? T_5050_43 : GEN_63;
assign GEN_65 = 7'h2c == T_7284 ? T_5050_44 : GEN_64;
assign GEN_66 = 7'h2d == T_7284 ? T_5050_45 : GEN_65;
assign GEN_67 = 7'h2e == T_7284 ? T_5050_46 : GEN_66;
assign GEN_68 = 7'h2f == T_7284 ? T_5050_47 : GEN_67;
assign GEN_69 = 7'h30 == T_7284 ? T_5050_48 : GEN_68;
assign GEN_70 = 7'h31 == T_7284 ? T_5050_49 : GEN_69;
assign GEN_71 = 7'h32 == T_7284 ? T_5050_50 : GEN_70;
assign GEN_72 = 7'h33 == T_7284 ? T_5050_51 : GEN_71;
assign GEN_73 = 7'h34 == T_7284 ? T_5050_52 : GEN_72;
assign GEN_74 = 7'h35 == T_7284 ? T_5050_53 : GEN_73;
assign GEN_75 = 7'h36 == T_7284 ? T_5050_54 : GEN_74;
assign GEN_76 = 7'h37 == T_7284 ? T_5050_55 : GEN_75;
assign GEN_77 = 7'h38 == T_7284 ? T_5050_56 : GEN_76;
assign GEN_78 = 7'h39 == T_7284 ? T_5050_57 : GEN_77;
assign GEN_79 = 7'h3a == T_7284 ? T_5050_58 : GEN_78;
assign GEN_80 = 7'h3b == T_7284 ? T_5050_59 : GEN_79;
assign GEN_81 = 7'h3c == T_7284 ? T_5050_60 : GEN_80;
assign GEN_82 = 7'h3d == T_7284 ? T_5050_61 : GEN_81;
assign GEN_83 = 7'h3e == T_7284 ? T_5050_62 : GEN_82;
assign GEN_84 = 7'h3f == T_7284 ? T_5050_63 : GEN_83;
assign GEN_85 = 7'h40 == T_7284 ? T_5050_64 : GEN_84;
assign GEN_86 = 7'h41 == T_7284 ? T_5050_65 : GEN_85;
assign GEN_87 = 7'h42 == T_7284 ? T_5050_66 : GEN_86;
assign GEN_88 = 7'h43 == T_7284 ? T_5050_67 : GEN_87;
assign GEN_89 = 7'h44 == T_7284 ? T_5050_68 : GEN_88;
assign GEN_90 = 7'h45 == T_7284 ? T_5050_69 : GEN_89;
assign GEN_91 = 7'h46 == T_7284 ? T_5050_70 : GEN_90;
assign GEN_92 = 7'h47 == T_7284 ? T_5050_71 : GEN_91;
assign GEN_93 = 7'h48 == T_7284 ? T_5050_72 : GEN_92;
assign GEN_94 = 7'h49 == T_7284 ? T_5050_73 : GEN_93;
assign GEN_95 = 7'h4a == T_7284 ? T_5050_74 : GEN_94;
assign GEN_96 = 7'h4b == T_7284 ? T_5050_75 : GEN_95;
assign GEN_97 = 7'h4c == T_7284 ? T_5050_76 : GEN_96;
assign GEN_98 = 7'h4d == T_7284 ? T_5050_77 : GEN_97;
assign GEN_99 = 7'h4e == T_7284 ? T_5050_78 : GEN_98;
assign GEN_100 = 7'h4f == T_7284 ? T_5050_79 : GEN_99;
assign GEN_101 = 7'h50 == T_7284 ? T_5050_80 : GEN_100;
assign GEN_102 = 7'h51 == T_7284 ? T_5050_81 : GEN_101;
assign GEN_103 = 7'h52 == T_7284 ? T_5050_82 : GEN_102;
assign GEN_104 = 7'h53 == T_7284 ? T_5050_83 : GEN_103;
assign GEN_105 = 7'h54 == T_7284 ? T_5050_84 : GEN_104;
assign GEN_106 = 7'h55 == T_7284 ? T_5050_85 : GEN_105;
assign GEN_107 = 7'h56 == T_7284 ? T_5050_86 : GEN_106;
assign GEN_108 = 7'h57 == T_7284 ? T_5050_87 : GEN_107;
assign GEN_109 = 7'h58 == T_7284 ? T_5050_88 : GEN_108;
assign GEN_110 = 7'h59 == T_7284 ? T_5050_89 : GEN_109;
assign GEN_111 = 7'h5a == T_7284 ? T_5050_90 : GEN_110;
assign GEN_112 = 7'h5b == T_7284 ? T_5050_91 : GEN_111;
assign GEN_113 = 7'h5c == T_7284 ? T_5050_92 : GEN_112;
assign GEN_114 = 7'h5d == T_7284 ? T_5050_93 : GEN_113;
assign GEN_115 = 7'h5e == T_7284 ? T_5050_94 : GEN_114;
assign GEN_116 = 7'h5f == T_7284 ? T_5050_95 : GEN_115;
assign GEN_117 = 7'h60 == T_7284 ? T_5050_96 : GEN_116;
assign GEN_118 = 7'h61 == T_7284 ? T_5050_97 : GEN_117;
assign GEN_119 = 7'h62 == T_7284 ? T_5050_98 : GEN_118;
assign GEN_120 = 7'h63 == T_7284 ? T_5050_99 : GEN_119;
assign GEN_121 = 7'h64 == T_7284 ? T_5050_100 : GEN_120;
assign GEN_122 = 7'h65 == T_7284 ? T_5050_101 : GEN_121;
assign GEN_123 = 7'h66 == T_7284 ? T_5050_102 : GEN_122;
assign GEN_124 = 7'h67 == T_7284 ? T_5050_103 : GEN_123;
assign GEN_125 = 7'h68 == T_7284 ? T_5050_104 : GEN_124;
assign GEN_126 = 7'h69 == T_7284 ? T_5050_105 : GEN_125;
assign GEN_127 = 7'h6a == T_7284 ? T_5050_106 : GEN_126;
assign GEN_128 = 7'h6b == T_7284 ? T_5050_107 : GEN_127;
assign GEN_129 = 7'h6c == T_7284 ? T_5050_108 : GEN_128;
assign GEN_130 = 7'h6d == T_7284 ? T_5050_109 : GEN_129;
assign GEN_131 = 7'h6e == T_7284 ? T_5050_110 : GEN_130;
assign GEN_132 = 7'h6f == T_7284 ? T_5050_111 : GEN_131;
assign GEN_133 = 7'h70 == T_7284 ? T_5050_112 : GEN_132;
assign GEN_134 = 7'h71 == T_7284 ? T_5050_113 : GEN_133;
assign GEN_135 = 7'h72 == T_7284 ? T_5050_114 : GEN_134;
assign GEN_136 = 7'h73 == T_7284 ? T_5050_115 : GEN_135;
assign GEN_137 = 7'h74 == T_7284 ? T_5050_116 : GEN_136;
assign GEN_138 = 7'h75 == T_7284 ? T_5050_117 : GEN_137;
assign GEN_139 = 7'h76 == T_7284 ? T_5050_118 : GEN_138;
assign GEN_140 = 7'h77 == T_7284 ? T_5050_119 : GEN_139;
assign GEN_141 = 7'h78 == T_7284 ? T_5050_120 : GEN_140;
assign GEN_142 = 7'h79 == T_7284 ? T_5050_121 : GEN_141;
assign GEN_143 = 7'h7a == T_7284 ? T_5050_122 : GEN_142;
assign GEN_144 = 7'h7b == T_7284 ? T_5050_123 : GEN_143;
assign GEN_145 = 7'h7c == T_7284 ? T_5050_124 : GEN_144;
assign GEN_146 = 7'h7d == T_7284 ? T_5050_125 : GEN_145;
assign GEN_147 = 7'h7e == T_7284 ? T_5050_126 : GEN_146;
assign GEN_148 = 7'h7f == T_7284 ? T_5050_127 : GEN_147;
assign GEN_1 = GEN_275;
assign GEN_149 = 7'h1 == T_7284 ? T_5746_1 : T_5746_0;
assign GEN_150 = 7'h2 == T_7284 ? T_5746_2 : GEN_149;
assign GEN_151 = 7'h3 == T_7284 ? T_5746_3 : GEN_150;
assign GEN_152 = 7'h4 == T_7284 ? T_5746_4 : GEN_151;
assign GEN_153 = 7'h5 == T_7284 ? T_5746_5 : GEN_152;
assign GEN_154 = 7'h6 == T_7284 ? T_5746_6 : GEN_153;
assign GEN_155 = 7'h7 == T_7284 ? T_5746_7 : GEN_154;
assign GEN_156 = 7'h8 == T_7284 ? T_5746_8 : GEN_155;
assign GEN_157 = 7'h9 == T_7284 ? T_5746_9 : GEN_156;
assign GEN_158 = 7'ha == T_7284 ? T_5746_10 : GEN_157;
assign GEN_159 = 7'hb == T_7284 ? T_5746_11 : GEN_158;
assign GEN_160 = 7'hc == T_7284 ? T_5746_12 : GEN_159;
assign GEN_161 = 7'hd == T_7284 ? T_5746_13 : GEN_160;
assign GEN_162 = 7'he == T_7284 ? T_5746_14 : GEN_161;
assign GEN_163 = 7'hf == T_7284 ? T_5746_15 : GEN_162;
assign GEN_164 = 7'h10 == T_7284 ? T_5746_16 : GEN_163;
assign GEN_165 = 7'h11 == T_7284 ? T_5746_17 : GEN_164;
assign GEN_166 = 7'h12 == T_7284 ? T_5746_18 : GEN_165;
assign GEN_167 = 7'h13 == T_7284 ? T_5746_19 : GEN_166;
assign GEN_168 = 7'h14 == T_7284 ? T_5746_20 : GEN_167;
assign GEN_169 = 7'h15 == T_7284 ? T_5746_21 : GEN_168;
assign GEN_170 = 7'h16 == T_7284 ? T_5746_22 : GEN_169;
assign GEN_171 = 7'h17 == T_7284 ? T_5746_23 : GEN_170;
assign GEN_172 = 7'h18 == T_7284 ? T_5746_24 : GEN_171;
assign GEN_173 = 7'h19 == T_7284 ? T_5746_25 : GEN_172;
assign GEN_174 = 7'h1a == T_7284 ? T_5746_26 : GEN_173;
assign GEN_175 = 7'h1b == T_7284 ? T_5746_27 : GEN_174;
assign GEN_176 = 7'h1c == T_7284 ? T_5746_28 : GEN_175;
assign GEN_177 = 7'h1d == T_7284 ? T_5746_29 : GEN_176;
assign GEN_178 = 7'h1e == T_7284 ? T_5746_30 : GEN_177;
assign GEN_179 = 7'h1f == T_7284 ? T_5746_31 : GEN_178;
assign GEN_180 = 7'h20 == T_7284 ? T_5746_32 : GEN_179;
assign GEN_181 = 7'h21 == T_7284 ? T_5746_33 : GEN_180;
assign GEN_182 = 7'h22 == T_7284 ? T_5746_34 : GEN_181;
assign GEN_183 = 7'h23 == T_7284 ? T_5746_35 : GEN_182;
assign GEN_184 = 7'h24 == T_7284 ? T_5746_36 : GEN_183;
assign GEN_185 = 7'h25 == T_7284 ? T_5746_37 : GEN_184;
assign GEN_186 = 7'h26 == T_7284 ? T_5746_38 : GEN_185;
assign GEN_187 = 7'h27 == T_7284 ? T_5746_39 : GEN_186;
assign GEN_188 = 7'h28 == T_7284 ? T_5746_40 : GEN_187;
assign GEN_189 = 7'h29 == T_7284 ? T_5746_41 : GEN_188;
assign GEN_190 = 7'h2a == T_7284 ? T_5746_42 : GEN_189;
assign GEN_191 = 7'h2b == T_7284 ? T_5746_43 : GEN_190;
assign GEN_192 = 7'h2c == T_7284 ? T_5746_44 : GEN_191;
assign GEN_193 = 7'h2d == T_7284 ? T_5746_45 : GEN_192;
assign GEN_194 = 7'h2e == T_7284 ? T_5746_46 : GEN_193;
assign GEN_195 = 7'h2f == T_7284 ? T_5746_47 : GEN_194;
assign GEN_196 = 7'h30 == T_7284 ? T_5746_48 : GEN_195;
assign GEN_197 = 7'h31 == T_7284 ? T_5746_49 : GEN_196;
assign GEN_198 = 7'h32 == T_7284 ? T_5746_50 : GEN_197;
assign GEN_199 = 7'h33 == T_7284 ? T_5746_51 : GEN_198;
assign GEN_200 = 7'h34 == T_7284 ? T_5746_52 : GEN_199;
assign GEN_201 = 7'h35 == T_7284 ? T_5746_53 : GEN_200;
assign GEN_202 = 7'h36 == T_7284 ? T_5746_54 : GEN_201;
assign GEN_203 = 7'h37 == T_7284 ? T_5746_55 : GEN_202;
assign GEN_204 = 7'h38 == T_7284 ? T_5746_56 : GEN_203;
assign GEN_205 = 7'h39 == T_7284 ? T_5746_57 : GEN_204;
assign GEN_206 = 7'h3a == T_7284 ? T_5746_58 : GEN_205;
assign GEN_207 = 7'h3b == T_7284 ? T_5746_59 : GEN_206;
assign GEN_208 = 7'h3c == T_7284 ? T_5746_60 : GEN_207;
assign GEN_209 = 7'h3d == T_7284 ? T_5746_61 : GEN_208;
assign GEN_210 = 7'h3e == T_7284 ? T_5746_62 : GEN_209;
assign GEN_211 = 7'h3f == T_7284 ? T_5746_63 : GEN_210;
assign GEN_212 = 7'h40 == T_7284 ? T_5746_64 : GEN_211;
assign GEN_213 = 7'h41 == T_7284 ? T_5746_65 : GEN_212;
assign GEN_214 = 7'h42 == T_7284 ? T_5746_66 : GEN_213;
assign GEN_215 = 7'h43 == T_7284 ? T_5746_67 : GEN_214;
assign GEN_216 = 7'h44 == T_7284 ? T_5746_68 : GEN_215;
assign GEN_217 = 7'h45 == T_7284 ? T_5746_69 : GEN_216;
assign GEN_218 = 7'h46 == T_7284 ? T_5746_70 : GEN_217;
assign GEN_219 = 7'h47 == T_7284 ? T_5746_71 : GEN_218;
assign GEN_220 = 7'h48 == T_7284 ? T_5746_72 : GEN_219;
assign GEN_221 = 7'h49 == T_7284 ? T_5746_73 : GEN_220;
assign GEN_222 = 7'h4a == T_7284 ? T_5746_74 : GEN_221;
assign GEN_223 = 7'h4b == T_7284 ? T_5746_75 : GEN_222;
assign GEN_224 = 7'h4c == T_7284 ? T_5746_76 : GEN_223;
assign GEN_225 = 7'h4d == T_7284 ? T_5746_77 : GEN_224;
assign GEN_226 = 7'h4e == T_7284 ? T_5746_78 : GEN_225;
assign GEN_227 = 7'h4f == T_7284 ? T_5746_79 : GEN_226;
assign GEN_228 = 7'h50 == T_7284 ? T_5746_80 : GEN_227;
assign GEN_229 = 7'h51 == T_7284 ? T_5746_81 : GEN_228;
assign GEN_230 = 7'h52 == T_7284 ? T_5746_82 : GEN_229;
assign GEN_231 = 7'h53 == T_7284 ? T_5746_83 : GEN_230;
assign GEN_232 = 7'h54 == T_7284 ? T_5746_84 : GEN_231;
assign GEN_233 = 7'h55 == T_7284 ? T_5746_85 : GEN_232;
assign GEN_234 = 7'h56 == T_7284 ? T_5746_86 : GEN_233;
assign GEN_235 = 7'h57 == T_7284 ? T_5746_87 : GEN_234;
assign GEN_236 = 7'h58 == T_7284 ? T_5746_88 : GEN_235;
assign GEN_237 = 7'h59 == T_7284 ? T_5746_89 : GEN_236;
assign GEN_238 = 7'h5a == T_7284 ? T_5746_90 : GEN_237;
assign GEN_239 = 7'h5b == T_7284 ? T_5746_91 : GEN_238;
assign GEN_240 = 7'h5c == T_7284 ? T_5746_92 : GEN_239;
assign GEN_241 = 7'h5d == T_7284 ? T_5746_93 : GEN_240;
assign GEN_242 = 7'h5e == T_7284 ? T_5746_94 : GEN_241;
assign GEN_243 = 7'h5f == T_7284 ? T_5746_95 : GEN_242;
assign GEN_244 = 7'h60 == T_7284 ? T_5746_96 : GEN_243;
assign GEN_245 = 7'h61 == T_7284 ? T_5746_97 : GEN_244;
assign GEN_246 = 7'h62 == T_7284 ? T_5746_98 : GEN_245;
assign GEN_247 = 7'h63 == T_7284 ? T_5746_99 : GEN_246;
assign GEN_248 = 7'h64 == T_7284 ? T_5746_100 : GEN_247;
assign GEN_249 = 7'h65 == T_7284 ? T_5746_101 : GEN_248;
assign GEN_250 = 7'h66 == T_7284 ? T_5746_102 : GEN_249;
assign GEN_251 = 7'h67 == T_7284 ? T_5746_103 : GEN_250;
assign GEN_252 = 7'h68 == T_7284 ? T_5746_104 : GEN_251;
assign GEN_253 = 7'h69 == T_7284 ? T_5746_105 : GEN_252;
assign GEN_254 = 7'h6a == T_7284 ? T_5746_106 : GEN_253;
assign GEN_255 = 7'h6b == T_7284 ? T_5746_107 : GEN_254;
assign GEN_256 = 7'h6c == T_7284 ? T_5746_108 : GEN_255;
assign GEN_257 = 7'h6d == T_7284 ? T_5746_109 : GEN_256;
assign GEN_258 = 7'h6e == T_7284 ? T_5746_110 : GEN_257;
assign GEN_259 = 7'h6f == T_7284 ? T_5746_111 : GEN_258;
assign GEN_260 = 7'h70 == T_7284 ? T_5746_112 : GEN_259;
assign GEN_261 = 7'h71 == T_7284 ? T_5746_113 : GEN_260;
assign GEN_262 = 7'h72 == T_7284 ? T_5746_114 : GEN_261;
assign GEN_263 = 7'h73 == T_7284 ? T_5746_115 : GEN_262;
assign GEN_264 = 7'h74 == T_7284 ? T_5746_116 : GEN_263;
assign GEN_265 = 7'h75 == T_7284 ? T_5746_117 : GEN_264;
assign GEN_266 = 7'h76 == T_7284 ? T_5746_118 : GEN_265;
assign GEN_267 = 7'h77 == T_7284 ? T_5746_119 : GEN_266;
assign GEN_268 = 7'h78 == T_7284 ? T_5746_120 : GEN_267;
assign GEN_269 = 7'h79 == T_7284 ? T_5746_121 : GEN_268;
assign GEN_270 = 7'h7a == T_7284 ? T_5746_122 : GEN_269;
assign GEN_271 = 7'h7b == T_7284 ? T_5746_123 : GEN_270;
assign GEN_272 = 7'h7c == T_7284 ? T_5746_124 : GEN_271;
assign GEN_273 = 7'h7d == T_7284 ? T_5746_125 : GEN_272;
assign GEN_274 = 7'h7e == T_7284 ? T_5746_126 : GEN_273;
assign GEN_275 = 7'h7f == T_7284 ? T_5746_127 : GEN_274;
assign T_7303 = T_1028_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_402;
assign GEN_276 = 7'h1 == T_7300 ? T_6442_1 : T_6442_0;
assign GEN_277 = 7'h2 == T_7300 ? T_6442_2 : GEN_276;
assign GEN_278 = 7'h3 == T_7300 ? T_6442_3 : GEN_277;
assign GEN_279 = 7'h4 == T_7300 ? T_6442_4 : GEN_278;
assign GEN_280 = 7'h5 == T_7300 ? T_6442_5 : GEN_279;
assign GEN_281 = 7'h6 == T_7300 ? T_6442_6 : GEN_280;
assign GEN_282 = 7'h7 == T_7300 ? T_6442_7 : GEN_281;
assign GEN_283 = 7'h8 == T_7300 ? T_6442_8 : GEN_282;
assign GEN_284 = 7'h9 == T_7300 ? T_6442_9 : GEN_283;
assign GEN_285 = 7'ha == T_7300 ? T_6442_10 : GEN_284;
assign GEN_286 = 7'hb == T_7300 ? T_6442_11 : GEN_285;
assign GEN_287 = 7'hc == T_7300 ? T_6442_12 : GEN_286;
assign GEN_288 = 7'hd == T_7300 ? T_6442_13 : GEN_287;
assign GEN_289 = 7'he == T_7300 ? T_6442_14 : GEN_288;
assign GEN_290 = 7'hf == T_7300 ? T_6442_15 : GEN_289;
assign GEN_291 = 7'h10 == T_7300 ? T_6442_16 : GEN_290;
assign GEN_292 = 7'h11 == T_7300 ? T_6442_17 : GEN_291;
assign GEN_293 = 7'h12 == T_7300 ? T_6442_18 : GEN_292;
assign GEN_294 = 7'h13 == T_7300 ? T_6442_19 : GEN_293;
assign GEN_295 = 7'h14 == T_7300 ? T_6442_20 : GEN_294;
assign GEN_296 = 7'h15 == T_7300 ? T_6442_21 : GEN_295;
assign GEN_297 = 7'h16 == T_7300 ? T_6442_22 : GEN_296;
assign GEN_298 = 7'h17 == T_7300 ? T_6442_23 : GEN_297;
assign GEN_299 = 7'h18 == T_7300 ? T_6442_24 : GEN_298;
assign GEN_300 = 7'h19 == T_7300 ? T_6442_25 : GEN_299;
assign GEN_301 = 7'h1a == T_7300 ? T_6442_26 : GEN_300;
assign GEN_302 = 7'h1b == T_7300 ? T_6442_27 : GEN_301;
assign GEN_303 = 7'h1c == T_7300 ? T_6442_28 : GEN_302;
assign GEN_304 = 7'h1d == T_7300 ? T_6442_29 : GEN_303;
assign GEN_305 = 7'h1e == T_7300 ? T_6442_30 : GEN_304;
assign GEN_306 = 7'h1f == T_7300 ? T_6442_31 : GEN_305;
assign GEN_307 = 7'h20 == T_7300 ? T_6442_32 : GEN_306;
assign GEN_308 = 7'h21 == T_7300 ? T_6442_33 : GEN_307;
assign GEN_309 = 7'h22 == T_7300 ? T_6442_34 : GEN_308;
assign GEN_310 = 7'h23 == T_7300 ? T_6442_35 : GEN_309;
assign GEN_311 = 7'h24 == T_7300 ? T_6442_36 : GEN_310;
assign GEN_312 = 7'h25 == T_7300 ? T_6442_37 : GEN_311;
assign GEN_313 = 7'h26 == T_7300 ? T_6442_38 : GEN_312;
assign GEN_314 = 7'h27 == T_7300 ? T_6442_39 : GEN_313;
assign GEN_315 = 7'h28 == T_7300 ? T_6442_40 : GEN_314;
assign GEN_316 = 7'h29 == T_7300 ? T_6442_41 : GEN_315;
assign GEN_317 = 7'h2a == T_7300 ? T_6442_42 : GEN_316;
assign GEN_318 = 7'h2b == T_7300 ? T_6442_43 : GEN_317;
assign GEN_319 = 7'h2c == T_7300 ? T_6442_44 : GEN_318;
assign GEN_320 = 7'h2d == T_7300 ? T_6442_45 : GEN_319;
assign GEN_321 = 7'h2e == T_7300 ? T_6442_46 : GEN_320;
assign GEN_322 = 7'h2f == T_7300 ? T_6442_47 : GEN_321;
assign GEN_323 = 7'h30 == T_7300 ? T_6442_48 : GEN_322;
assign GEN_324 = 7'h31 == T_7300 ? T_6442_49 : GEN_323;
assign GEN_325 = 7'h32 == T_7300 ? T_6442_50 : GEN_324;
assign GEN_326 = 7'h33 == T_7300 ? T_6442_51 : GEN_325;
assign GEN_327 = 7'h34 == T_7300 ? T_6442_52 : GEN_326;
assign GEN_328 = 7'h35 == T_7300 ? T_6442_53 : GEN_327;
assign GEN_329 = 7'h36 == T_7300 ? T_6442_54 : GEN_328;
assign GEN_330 = 7'h37 == T_7300 ? T_6442_55 : GEN_329;
assign GEN_331 = 7'h38 == T_7300 ? T_6442_56 : GEN_330;
assign GEN_332 = 7'h39 == T_7300 ? T_6442_57 : GEN_331;
assign GEN_333 = 7'h3a == T_7300 ? T_6442_58 : GEN_332;
assign GEN_334 = 7'h3b == T_7300 ? T_6442_59 : GEN_333;
assign GEN_335 = 7'h3c == T_7300 ? T_6442_60 : GEN_334;
assign GEN_336 = 7'h3d == T_7300 ? T_6442_61 : GEN_335;
assign GEN_337 = 7'h3e == T_7300 ? T_6442_62 : GEN_336;
assign GEN_338 = 7'h3f == T_7300 ? T_6442_63 : GEN_337;
assign GEN_339 = 7'h40 == T_7300 ? T_6442_64 : GEN_338;
assign GEN_340 = 7'h41 == T_7300 ? T_6442_65 : GEN_339;
assign GEN_341 = 7'h42 == T_7300 ? T_6442_66 : GEN_340;
assign GEN_342 = 7'h43 == T_7300 ? T_6442_67 : GEN_341;
assign GEN_343 = 7'h44 == T_7300 ? T_6442_68 : GEN_342;
assign GEN_344 = 7'h45 == T_7300 ? T_6442_69 : GEN_343;
assign GEN_345 = 7'h46 == T_7300 ? T_6442_70 : GEN_344;
assign GEN_346 = 7'h47 == T_7300 ? T_6442_71 : GEN_345;
assign GEN_347 = 7'h48 == T_7300 ? T_6442_72 : GEN_346;
assign GEN_348 = 7'h49 == T_7300 ? T_6442_73 : GEN_347;
assign GEN_349 = 7'h4a == T_7300 ? T_6442_74 : GEN_348;
assign GEN_350 = 7'h4b == T_7300 ? T_6442_75 : GEN_349;
assign GEN_351 = 7'h4c == T_7300 ? T_6442_76 : GEN_350;
assign GEN_352 = 7'h4d == T_7300 ? T_6442_77 : GEN_351;
assign GEN_353 = 7'h4e == T_7300 ? T_6442_78 : GEN_352;
assign GEN_354 = 7'h4f == T_7300 ? T_6442_79 : GEN_353;
assign GEN_355 = 7'h50 == T_7300 ? T_6442_80 : GEN_354;
assign GEN_356 = 7'h51 == T_7300 ? T_6442_81 : GEN_355;
assign GEN_357 = 7'h52 == T_7300 ? T_6442_82 : GEN_356;
assign GEN_358 = 7'h53 == T_7300 ? T_6442_83 : GEN_357;
assign GEN_359 = 7'h54 == T_7300 ? T_6442_84 : GEN_358;
assign GEN_360 = 7'h55 == T_7300 ? T_6442_85 : GEN_359;
assign GEN_361 = 7'h56 == T_7300 ? T_6442_86 : GEN_360;
assign GEN_362 = 7'h57 == T_7300 ? T_6442_87 : GEN_361;
assign GEN_363 = 7'h58 == T_7300 ? T_6442_88 : GEN_362;
assign GEN_364 = 7'h59 == T_7300 ? T_6442_89 : GEN_363;
assign GEN_365 = 7'h5a == T_7300 ? T_6442_90 : GEN_364;
assign GEN_366 = 7'h5b == T_7300 ? T_6442_91 : GEN_365;
assign GEN_367 = 7'h5c == T_7300 ? T_6442_92 : GEN_366;
assign GEN_368 = 7'h5d == T_7300 ? T_6442_93 : GEN_367;
assign GEN_369 = 7'h5e == T_7300 ? T_6442_94 : GEN_368;
assign GEN_370 = 7'h5f == T_7300 ? T_6442_95 : GEN_369;
assign GEN_371 = 7'h60 == T_7300 ? T_6442_96 : GEN_370;
assign GEN_372 = 7'h61 == T_7300 ? T_6442_97 : GEN_371;
assign GEN_373 = 7'h62 == T_7300 ? T_6442_98 : GEN_372;
assign GEN_374 = 7'h63 == T_7300 ? T_6442_99 : GEN_373;
assign GEN_375 = 7'h64 == T_7300 ? T_6442_100 : GEN_374;
assign GEN_376 = 7'h65 == T_7300 ? T_6442_101 : GEN_375;
assign GEN_377 = 7'h66 == T_7300 ? T_6442_102 : GEN_376;
assign GEN_378 = 7'h67 == T_7300 ? T_6442_103 : GEN_377;
assign GEN_379 = 7'h68 == T_7300 ? T_6442_104 : GEN_378;
assign GEN_380 = 7'h69 == T_7300 ? T_6442_105 : GEN_379;
assign GEN_381 = 7'h6a == T_7300 ? T_6442_106 : GEN_380;
assign GEN_382 = 7'h6b == T_7300 ? T_6442_107 : GEN_381;
assign GEN_383 = 7'h6c == T_7300 ? T_6442_108 : GEN_382;
assign GEN_384 = 7'h6d == T_7300 ? T_6442_109 : GEN_383;
assign GEN_385 = 7'h6e == T_7300 ? T_6442_110 : GEN_384;
assign GEN_386 = 7'h6f == T_7300 ? T_6442_111 : GEN_385;
assign GEN_387 = 7'h70 == T_7300 ? T_6442_112 : GEN_386;
assign GEN_388 = 7'h71 == T_7300 ? T_6442_113 : GEN_387;
assign GEN_389 = 7'h72 == T_7300 ? T_6442_114 : GEN_388;
assign GEN_390 = 7'h73 == T_7300 ? T_6442_115 : GEN_389;
assign GEN_391 = 7'h74 == T_7300 ? T_6442_116 : GEN_390;
assign GEN_392 = 7'h75 == T_7300 ? T_6442_117 : GEN_391;
assign GEN_393 = 7'h76 == T_7300 ? T_6442_118 : GEN_392;
assign GEN_394 = 7'h77 == T_7300 ? T_6442_119 : GEN_393;
assign GEN_395 = 7'h78 == T_7300 ? T_6442_120 : GEN_394;
assign GEN_396 = 7'h79 == T_7300 ? T_6442_121 : GEN_395;
assign GEN_397 = 7'h7a == T_7300 ? T_6442_122 : GEN_396;
assign GEN_398 = 7'h7b == T_7300 ? T_6442_123 : GEN_397;
assign GEN_399 = 7'h7c == T_7300 ? T_6442_124 : GEN_398;
assign GEN_400 = 7'h7d == T_7300 ? T_6442_125 : GEN_399;
assign GEN_401 = 7'h7e == T_7300 ? T_6442_126 : GEN_400;
assign GEN_402 = 7'h7f == T_7300 ? T_6442_127 : GEN_401;
assign GEN_3 = GEN_529;
assign GEN_403 = 7'h1 == T_7300 ? T_7138_1 : T_7138_0;
assign GEN_404 = 7'h2 == T_7300 ? T_7138_2 : GEN_403;
assign GEN_405 = 7'h3 == T_7300 ? T_7138_3 : GEN_404;
assign GEN_406 = 7'h4 == T_7300 ? T_7138_4 : GEN_405;
assign GEN_407 = 7'h5 == T_7300 ? T_7138_5 : GEN_406;
assign GEN_408 = 7'h6 == T_7300 ? T_7138_6 : GEN_407;
assign GEN_409 = 7'h7 == T_7300 ? T_7138_7 : GEN_408;
assign GEN_410 = 7'h8 == T_7300 ? T_7138_8 : GEN_409;
assign GEN_411 = 7'h9 == T_7300 ? T_7138_9 : GEN_410;
assign GEN_412 = 7'ha == T_7300 ? T_7138_10 : GEN_411;
assign GEN_413 = 7'hb == T_7300 ? T_7138_11 : GEN_412;
assign GEN_414 = 7'hc == T_7300 ? T_7138_12 : GEN_413;
assign GEN_415 = 7'hd == T_7300 ? T_7138_13 : GEN_414;
assign GEN_416 = 7'he == T_7300 ? T_7138_14 : GEN_415;
assign GEN_417 = 7'hf == T_7300 ? T_7138_15 : GEN_416;
assign GEN_418 = 7'h10 == T_7300 ? T_7138_16 : GEN_417;
assign GEN_419 = 7'h11 == T_7300 ? T_7138_17 : GEN_418;
assign GEN_420 = 7'h12 == T_7300 ? T_7138_18 : GEN_419;
assign GEN_421 = 7'h13 == T_7300 ? T_7138_19 : GEN_420;
assign GEN_422 = 7'h14 == T_7300 ? T_7138_20 : GEN_421;
assign GEN_423 = 7'h15 == T_7300 ? T_7138_21 : GEN_422;
assign GEN_424 = 7'h16 == T_7300 ? T_7138_22 : GEN_423;
assign GEN_425 = 7'h17 == T_7300 ? T_7138_23 : GEN_424;
assign GEN_426 = 7'h18 == T_7300 ? T_7138_24 : GEN_425;
assign GEN_427 = 7'h19 == T_7300 ? T_7138_25 : GEN_426;
assign GEN_428 = 7'h1a == T_7300 ? T_7138_26 : GEN_427;
assign GEN_429 = 7'h1b == T_7300 ? T_7138_27 : GEN_428;
assign GEN_430 = 7'h1c == T_7300 ? T_7138_28 : GEN_429;
assign GEN_431 = 7'h1d == T_7300 ? T_7138_29 : GEN_430;
assign GEN_432 = 7'h1e == T_7300 ? T_7138_30 : GEN_431;
assign GEN_433 = 7'h1f == T_7300 ? T_7138_31 : GEN_432;
assign GEN_434 = 7'h20 == T_7300 ? T_7138_32 : GEN_433;
assign GEN_435 = 7'h21 == T_7300 ? T_7138_33 : GEN_434;
assign GEN_436 = 7'h22 == T_7300 ? T_7138_34 : GEN_435;
assign GEN_437 = 7'h23 == T_7300 ? T_7138_35 : GEN_436;
assign GEN_438 = 7'h24 == T_7300 ? T_7138_36 : GEN_437;
assign GEN_439 = 7'h25 == T_7300 ? T_7138_37 : GEN_438;
assign GEN_440 = 7'h26 == T_7300 ? T_7138_38 : GEN_439;
assign GEN_441 = 7'h27 == T_7300 ? T_7138_39 : GEN_440;
assign GEN_442 = 7'h28 == T_7300 ? T_7138_40 : GEN_441;
assign GEN_443 = 7'h29 == T_7300 ? T_7138_41 : GEN_442;
assign GEN_444 = 7'h2a == T_7300 ? T_7138_42 : GEN_443;
assign GEN_445 = 7'h2b == T_7300 ? T_7138_43 : GEN_444;
assign GEN_446 = 7'h2c == T_7300 ? T_7138_44 : GEN_445;
assign GEN_447 = 7'h2d == T_7300 ? T_7138_45 : GEN_446;
assign GEN_448 = 7'h2e == T_7300 ? T_7138_46 : GEN_447;
assign GEN_449 = 7'h2f == T_7300 ? T_7138_47 : GEN_448;
assign GEN_450 = 7'h30 == T_7300 ? T_7138_48 : GEN_449;
assign GEN_451 = 7'h31 == T_7300 ? T_7138_49 : GEN_450;
assign GEN_452 = 7'h32 == T_7300 ? T_7138_50 : GEN_451;
assign GEN_453 = 7'h33 == T_7300 ? T_7138_51 : GEN_452;
assign GEN_454 = 7'h34 == T_7300 ? T_7138_52 : GEN_453;
assign GEN_455 = 7'h35 == T_7300 ? T_7138_53 : GEN_454;
assign GEN_456 = 7'h36 == T_7300 ? T_7138_54 : GEN_455;
assign GEN_457 = 7'h37 == T_7300 ? T_7138_55 : GEN_456;
assign GEN_458 = 7'h38 == T_7300 ? T_7138_56 : GEN_457;
assign GEN_459 = 7'h39 == T_7300 ? T_7138_57 : GEN_458;
assign GEN_460 = 7'h3a == T_7300 ? T_7138_58 : GEN_459;
assign GEN_461 = 7'h3b == T_7300 ? T_7138_59 : GEN_460;
assign GEN_462 = 7'h3c == T_7300 ? T_7138_60 : GEN_461;
assign GEN_463 = 7'h3d == T_7300 ? T_7138_61 : GEN_462;
assign GEN_464 = 7'h3e == T_7300 ? T_7138_62 : GEN_463;
assign GEN_465 = 7'h3f == T_7300 ? T_7138_63 : GEN_464;
assign GEN_466 = 7'h40 == T_7300 ? T_7138_64 : GEN_465;
assign GEN_467 = 7'h41 == T_7300 ? T_7138_65 : GEN_466;
assign GEN_468 = 7'h42 == T_7300 ? T_7138_66 : GEN_467;
assign GEN_469 = 7'h43 == T_7300 ? T_7138_67 : GEN_468;
assign GEN_470 = 7'h44 == T_7300 ? T_7138_68 : GEN_469;
assign GEN_471 = 7'h45 == T_7300 ? T_7138_69 : GEN_470;
assign GEN_472 = 7'h46 == T_7300 ? T_7138_70 : GEN_471;
assign GEN_473 = 7'h47 == T_7300 ? T_7138_71 : GEN_472;
assign GEN_474 = 7'h48 == T_7300 ? T_7138_72 : GEN_473;
assign GEN_475 = 7'h49 == T_7300 ? T_7138_73 : GEN_474;
assign GEN_476 = 7'h4a == T_7300 ? T_7138_74 : GEN_475;
assign GEN_477 = 7'h4b == T_7300 ? T_7138_75 : GEN_476;
assign GEN_478 = 7'h4c == T_7300 ? T_7138_76 : GEN_477;
assign GEN_479 = 7'h4d == T_7300 ? T_7138_77 : GEN_478;
assign GEN_480 = 7'h4e == T_7300 ? T_7138_78 : GEN_479;
assign GEN_481 = 7'h4f == T_7300 ? T_7138_79 : GEN_480;
assign GEN_482 = 7'h50 == T_7300 ? T_7138_80 : GEN_481;
assign GEN_483 = 7'h51 == T_7300 ? T_7138_81 : GEN_482;
assign GEN_484 = 7'h52 == T_7300 ? T_7138_82 : GEN_483;
assign GEN_485 = 7'h53 == T_7300 ? T_7138_83 : GEN_484;
assign GEN_486 = 7'h54 == T_7300 ? T_7138_84 : GEN_485;
assign GEN_487 = 7'h55 == T_7300 ? T_7138_85 : GEN_486;
assign GEN_488 = 7'h56 == T_7300 ? T_7138_86 : GEN_487;
assign GEN_489 = 7'h57 == T_7300 ? T_7138_87 : GEN_488;
assign GEN_490 = 7'h58 == T_7300 ? T_7138_88 : GEN_489;
assign GEN_491 = 7'h59 == T_7300 ? T_7138_89 : GEN_490;
assign GEN_492 = 7'h5a == T_7300 ? T_7138_90 : GEN_491;
assign GEN_493 = 7'h5b == T_7300 ? T_7138_91 : GEN_492;
assign GEN_494 = 7'h5c == T_7300 ? T_7138_92 : GEN_493;
assign GEN_495 = 7'h5d == T_7300 ? T_7138_93 : GEN_494;
assign GEN_496 = 7'h5e == T_7300 ? T_7138_94 : GEN_495;
assign GEN_497 = 7'h5f == T_7300 ? T_7138_95 : GEN_496;
assign GEN_498 = 7'h60 == T_7300 ? T_7138_96 : GEN_497;
assign GEN_499 = 7'h61 == T_7300 ? T_7138_97 : GEN_498;
assign GEN_500 = 7'h62 == T_7300 ? T_7138_98 : GEN_499;
assign GEN_501 = 7'h63 == T_7300 ? T_7138_99 : GEN_500;
assign GEN_502 = 7'h64 == T_7300 ? T_7138_100 : GEN_501;
assign GEN_503 = 7'h65 == T_7300 ? T_7138_101 : GEN_502;
assign GEN_504 = 7'h66 == T_7300 ? T_7138_102 : GEN_503;
assign GEN_505 = 7'h67 == T_7300 ? T_7138_103 : GEN_504;
assign GEN_506 = 7'h68 == T_7300 ? T_7138_104 : GEN_505;
assign GEN_507 = 7'h69 == T_7300 ? T_7138_105 : GEN_506;
assign GEN_508 = 7'h6a == T_7300 ? T_7138_106 : GEN_507;
assign GEN_509 = 7'h6b == T_7300 ? T_7138_107 : GEN_508;
assign GEN_510 = 7'h6c == T_7300 ? T_7138_108 : GEN_509;
assign GEN_511 = 7'h6d == T_7300 ? T_7138_109 : GEN_510;
assign GEN_512 = 7'h6e == T_7300 ? T_7138_110 : GEN_511;
assign GEN_513 = 7'h6f == T_7300 ? T_7138_111 : GEN_512;
assign GEN_514 = 7'h70 == T_7300 ? T_7138_112 : GEN_513;
assign GEN_515 = 7'h71 == T_7300 ? T_7138_113 : GEN_514;
assign GEN_516 = 7'h72 == T_7300 ? T_7138_114 : GEN_515;
assign GEN_517 = 7'h73 == T_7300 ? T_7138_115 : GEN_516;
assign GEN_518 = 7'h74 == T_7300 ? T_7138_116 : GEN_517;
assign GEN_519 = 7'h75 == T_7300 ? T_7138_117 : GEN_518;
assign GEN_520 = 7'h76 == T_7300 ? T_7138_118 : GEN_519;
assign GEN_521 = 7'h77 == T_7300 ? T_7138_119 : GEN_520;
assign GEN_522 = 7'h78 == T_7300 ? T_7138_120 : GEN_521;
assign GEN_523 = 7'h79 == T_7300 ? T_7138_121 : GEN_522;
assign GEN_524 = 7'h7a == T_7300 ? T_7138_122 : GEN_523;
assign GEN_525 = 7'h7b == T_7300 ? T_7138_123 : GEN_524;
assign GEN_526 = 7'h7c == T_7300 ? T_7138_124 : GEN_525;
assign GEN_527 = 7'h7d == T_7300 ? T_7138_125 : GEN_526;
assign GEN_528 = 7'h7e == T_7300 ? T_7138_126 : GEN_527;
assign GEN_529 = 7'h7f == T_7300 ? T_7138_127 : GEN_528;
assign T_7306 = Queue_1_io_deq_bits_read ? GEN_2 : GEN_3;
assign T_7307 = T_1028_ready & T_7303;
assign T_7308 = T_953_valid & T_7303;
assign T_7309 = T_992_ready & T_7306;
assign T_7310 = Queue_1_io_deq_valid & T_7306;
assign T_7312 = 128'h1 << T_7284;
assign T_7313 = {1'h1,T_1322};
assign T_7314 = {T_1583,T_1466};
assign T_7315 = {T_7314,T_7313};
assign T_7316 = {1'h1,T_1718};
assign T_7317 = {T_1556,T_1394};
assign T_7318 = {T_7317,T_7316};
assign T_7319 = {T_7318,T_7315};
assign T_7320 = {1'h1,T_1673};
assign T_7322 = {2'h3,T_7320};
assign T_7326 = {4'hf,T_7322};
assign T_7327 = {T_7326,T_7319};
assign T_7328 = {1'h1,T_1628};
assign T_7329 = {T_1709,T_1610};
assign T_7330 = {T_7329,T_7328};
assign T_7331 = {1'h1,T_1358};
assign T_7332 = {T_1664,T_1511};
assign T_7333 = {T_7332,T_7331};
assign T_7334 = {T_7333,T_7330};
assign T_7335 = {1'h1,T_1340};
assign T_7337 = {2'h3,T_7335};
assign T_7341 = {4'hf,T_7337};
assign T_7342 = {T_7341,T_7334};
assign T_7343 = {T_7342,T_7327};
assign T_7344 = {T_1421,T_1475};
assign T_7345 = {T_1601,T_1484};
assign T_7346 = {T_7345,T_7344};
assign T_7347 = {T_1349,T_1700};
assign T_7348 = {T_1565,T_1403};
assign T_7349 = {T_7348,T_7347};
assign T_7350 = {T_7349,T_7346};
assign T_7351 = {T_1448,T_1655};
assign T_7352 = {T_1646,T_1331};
assign T_7353 = {T_7352,T_7351};
assign T_7354 = {T_1493,T_1520};
assign T_7355 = {T_1736,T_1367};
assign T_7356 = {T_7355,T_7354};
assign T_7357 = {T_7356,T_7353};
assign T_7358 = {T_7357,T_7350};
assign T_7374 = {16'hffff,T_7358};
assign T_7375 = {T_7374,T_7343};
assign T_7376 = {T_1430,T_1502};
assign T_7377 = {T_1619,T_1574};
assign T_7378 = {T_7377,T_7376};
assign T_7379 = {T_1313,T_1745};
assign T_7380 = {T_1529,T_1412};
assign T_7381 = {T_7380,T_7379};
assign T_7382 = {T_7381,T_7378};
assign T_7383 = {T_1457,T_1637};
assign T_7384 = {T_1682,T_1385};
assign T_7385 = {T_7384,T_7383};
assign T_7386 = {T_1439,T_1547};
assign T_7387 = {T_1727,T_1376};
assign T_7388 = {T_7387,T_7386};
assign T_7389 = {T_7388,T_7385};
assign T_7390 = {T_7389,T_7382};
assign T_7391 = {T_1538,T_1592};
assign T_7392 = {T_1754,T_1691};
assign T_7393 = {T_7392,T_7391};
assign T_7397 = {4'hf,T_7393};
assign T_7405 = {8'hff,T_7397};
assign T_7406 = {T_7405,T_7390};
assign T_7438 = {32'hffffffff,T_7406};
assign T_7439 = {T_7438,T_7375};
assign T_7440 = T_7312 & T_7439;
assign T_7442 = 128'h1 << T_7300;
assign T_7443 = {1'h1,T_1326};
assign T_7444 = {T_1587,T_1470};
assign T_7445 = {T_7444,T_7443};
assign T_7446 = {1'h1,T_1722};
assign T_7447 = {T_1560,T_1398};
assign T_7448 = {T_7447,T_7446};
assign T_7449 = {T_7448,T_7445};
assign T_7450 = {1'h1,T_1677};
assign T_7452 = {2'h3,T_7450};
assign T_7456 = {4'hf,T_7452};
assign T_7457 = {T_7456,T_7449};
assign T_7458 = {1'h1,T_1632};
assign T_7459 = {T_1713,T_1614};
assign T_7460 = {T_7459,T_7458};
assign T_7461 = {1'h1,T_1362};
assign T_7462 = {T_1668,T_1515};
assign T_7463 = {T_7462,T_7461};
assign T_7464 = {T_7463,T_7460};
assign T_7465 = {1'h1,T_1344};
assign T_7467 = {2'h3,T_7465};
assign T_7471 = {4'hf,T_7467};
assign T_7472 = {T_7471,T_7464};
assign T_7473 = {T_7472,T_7457};
assign T_7474 = {T_1425,T_1479};
assign T_7475 = {T_1605,T_1488};
assign T_7476 = {T_7475,T_7474};
assign T_7477 = {T_1353,T_1704};
assign T_7478 = {T_1569,T_1407};
assign T_7479 = {T_7478,T_7477};
assign T_7480 = {T_7479,T_7476};
assign T_7481 = {T_1452,T_1659};
assign T_7482 = {T_1650,T_1335};
assign T_7483 = {T_7482,T_7481};
assign T_7484 = {T_1497,T_1524};
assign T_7485 = {T_1740,T_1371};
assign T_7486 = {T_7485,T_7484};
assign T_7487 = {T_7486,T_7483};
assign T_7488 = {T_7487,T_7480};
assign T_7504 = {16'hffff,T_7488};
assign T_7505 = {T_7504,T_7473};
assign T_7506 = {T_1434,T_1506};
assign T_7507 = {T_1623,T_1578};
assign T_7508 = {T_7507,T_7506};
assign T_7509 = {T_1317,T_1749};
assign T_7510 = {T_1533,T_1416};
assign T_7511 = {T_7510,T_7509};
assign T_7512 = {T_7511,T_7508};
assign T_7513 = {T_1461,T_1641};
assign T_7514 = {T_1686,T_1389};
assign T_7515 = {T_7514,T_7513};
assign T_7516 = {T_1443,T_1551};
assign T_7517 = {T_1731,T_1380};
assign T_7518 = {T_7517,T_7516};
assign T_7519 = {T_7518,T_7515};
assign T_7520 = {T_7519,T_7512};
assign T_7521 = {T_1542,T_1596};
assign T_7522 = {T_1758,T_1695};
assign T_7523 = {T_7522,T_7521};
assign T_7527 = {4'hf,T_7523};
assign T_7535 = {8'hff,T_7527};
assign T_7536 = {T_7535,T_7520};
assign T_7568 = {32'hffffffff,T_7536};
assign T_7569 = {T_7568,T_7505};
assign T_7570 = T_7442 & T_7569;
assign T_7571 = T_953_valid & T_1028_ready;
assign T_7572 = T_7571 & T_1028_bits_read;
assign T_7573 = T_7440[0];
assign T_7574 = T_7572 & T_7573;
assign T_7577 = T_1028_bits_read == 1'h0;
assign T_7578 = T_7571 & T_7577;
assign T_7580 = T_7578 & T_7573;
assign T_7581 = Queue_1_io_deq_valid & T_992_ready;
assign T_7582 = T_7581 & Queue_1_io_deq_bits_read;
assign T_7583 = T_7570[0];
assign T_7584 = T_7582 & T_7583;
assign T_7587 = Queue_1_io_deq_bits_read == 1'h0;
assign T_7588 = T_7581 & T_7587;
assign T_7590 = T_7588 & T_7583;
assign T_7613 = T_7440[2];
assign T_7614 = T_7572 & T_7613;
assign T_7620 = T_7578 & T_7613;
assign T_7623 = T_7570[2];
assign T_7624 = T_7582 & T_7623;
assign T_7630 = T_7588 & T_7623;
assign T_7633 = T_7440[3];
assign T_7634 = T_7572 & T_7633;
assign T_7640 = T_7578 & T_7633;
assign T_7643 = T_7570[3];
assign T_7644 = T_7582 & T_7643;
assign T_7650 = T_7588 & T_7643;
assign T_7653 = T_7440[4];
assign T_7654 = T_7572 & T_7653;
assign T_7660 = T_7578 & T_7653;
assign T_7663 = T_7570[4];
assign T_7664 = T_7582 & T_7663;
assign T_7670 = T_7588 & T_7663;
assign T_7693 = T_7440[6];
assign T_7694 = T_7572 & T_7693;
assign T_7700 = T_7578 & T_7693;
assign T_7703 = T_7570[6];
assign T_7704 = T_7582 & T_7703;
assign T_7710 = T_7588 & T_7703;
assign T_7713 = T_7440[7];
assign T_7714 = T_7572 & T_7713;
assign T_7720 = T_7578 & T_7713;
assign T_7723 = T_7570[7];
assign T_7724 = T_7582 & T_7723;
assign T_7730 = T_7588 & T_7723;
assign T_7733 = T_7440[8];
assign T_7734 = T_7572 & T_7733;
assign T_7740 = T_7578 & T_7733;
assign T_7743 = T_7570[8];
assign T_7744 = T_7582 & T_7743;
assign T_7750 = T_7588 & T_7743;
assign T_7893 = T_7440[16];
assign T_7894 = T_7572 & T_7893;
assign T_7900 = T_7578 & T_7893;
assign T_7903 = T_7570[16];
assign T_7904 = T_7582 & T_7903;
assign T_7910 = T_7588 & T_7903;
assign T_7933 = T_7440[18];
assign T_7934 = T_7572 & T_7933;
assign T_7940 = T_7578 & T_7933;
assign T_7943 = T_7570[18];
assign T_7944 = T_7582 & T_7943;
assign T_7950 = T_7588 & T_7943;
assign T_7953 = T_7440[19];
assign T_7954 = T_7572 & T_7953;
assign T_7960 = T_7578 & T_7953;
assign T_7963 = T_7570[19];
assign T_7964 = T_7582 & T_7963;
assign T_7970 = T_7588 & T_7963;
assign T_7973 = T_7440[20];
assign T_7974 = T_7572 & T_7973;
assign T_7980 = T_7578 & T_7973;
assign T_7983 = T_7570[20];
assign T_7984 = T_7582 & T_7983;
assign T_7990 = T_7588 & T_7983;
assign T_8013 = T_7440[22];
assign T_8014 = T_7572 & T_8013;
assign T_8020 = T_7578 & T_8013;
assign T_8023 = T_7570[22];
assign T_8024 = T_7582 & T_8023;
assign T_8030 = T_7588 & T_8023;
assign T_8033 = T_7440[23];
assign T_8034 = T_7572 & T_8033;
assign T_8040 = T_7578 & T_8033;
assign T_8043 = T_7570[23];
assign T_8044 = T_7582 & T_8043;
assign T_8050 = T_7588 & T_8043;
assign T_8053 = T_7440[24];
assign T_8054 = T_7572 & T_8053;
assign T_8060 = T_7578 & T_8053;
assign T_8063 = T_7570[24];
assign T_8064 = T_7582 & T_8063;
assign T_8070 = T_7588 & T_8063;
assign T_8213 = T_7440[32];
assign T_8214 = T_7572 & T_8213;
assign T_8220 = T_7578 & T_8213;
assign T_8223 = T_7570[32];
assign T_8224 = T_7582 & T_8223;
assign T_8230 = T_7588 & T_8223;
assign T_8233 = T_7440[33];
assign T_8234 = T_7572 & T_8233;
assign T_8240 = T_7578 & T_8233;
assign T_8243 = T_7570[33];
assign T_8244 = T_7582 & T_8243;
assign T_8250 = T_7588 & T_8243;
assign T_8253 = T_7440[34];
assign T_8254 = T_7572 & T_8253;
assign T_8260 = T_7578 & T_8253;
assign T_8263 = T_7570[34];
assign T_8264 = T_7582 & T_8263;
assign T_8270 = T_7588 & T_8263;
assign T_8273 = T_7440[35];
assign T_8274 = T_7572 & T_8273;
assign T_8280 = T_7578 & T_8273;
assign T_8283 = T_7570[35];
assign T_8284 = T_7582 & T_8283;
assign T_8290 = T_7588 & T_8283;
assign T_8293 = T_7440[36];
assign T_8294 = T_7572 & T_8293;
assign T_8300 = T_7578 & T_8293;
assign T_8303 = T_7570[36];
assign T_8304 = T_7582 & T_8303;
assign T_8310 = T_7588 & T_8303;
assign T_8313 = T_7440[37];
assign T_8314 = T_7572 & T_8313;
assign T_8320 = T_7578 & T_8313;
assign T_8323 = T_7570[37];
assign T_8324 = T_7582 & T_8323;
assign T_8330 = T_7588 & T_8323;
assign T_8333 = T_7440[38];
assign T_8334 = T_7572 & T_8333;
assign T_8340 = T_7578 & T_8333;
assign T_8343 = T_7570[38];
assign T_8344 = T_7582 & T_8343;
assign T_8350 = T_7588 & T_8343;
assign T_8353 = T_7440[39];
assign T_8354 = T_7572 & T_8353;
assign T_8360 = T_7578 & T_8353;
assign T_8363 = T_7570[39];
assign T_8364 = T_7582 & T_8363;
assign T_8370 = T_7588 & T_8363;
assign T_8373 = T_7440[40];
assign T_8374 = T_7572 & T_8373;
assign T_8380 = T_7578 & T_8373;
assign T_8383 = T_7570[40];
assign T_8384 = T_7582 & T_8383;
assign T_8390 = T_7588 & T_8383;
assign T_8393 = T_7440[41];
assign T_8394 = T_7572 & T_8393;
assign T_8400 = T_7578 & T_8393;
assign T_8403 = T_7570[41];
assign T_8404 = T_7582 & T_8403;
assign T_8410 = T_7588 & T_8403;
assign T_8413 = T_7440[42];
assign T_8414 = T_7572 & T_8413;
assign T_8420 = T_7578 & T_8413;
assign T_8423 = T_7570[42];
assign T_8424 = T_7582 & T_8423;
assign T_8430 = T_7588 & T_8423;
assign T_8433 = T_7440[43];
assign T_8434 = T_7572 & T_8433;
assign T_8440 = T_7578 & T_8433;
assign T_8443 = T_7570[43];
assign T_8444 = T_7582 & T_8443;
assign T_8450 = T_7588 & T_8443;
assign T_8453 = T_7440[44];
assign T_8454 = T_7572 & T_8453;
assign T_8460 = T_7578 & T_8453;
assign T_8463 = T_7570[44];
assign T_8464 = T_7582 & T_8463;
assign T_8470 = T_7588 & T_8463;
assign T_8473 = T_7440[45];
assign T_8474 = T_7572 & T_8473;
assign T_8480 = T_7578 & T_8473;
assign T_8483 = T_7570[45];
assign T_8484 = T_7582 & T_8483;
assign T_8490 = T_7588 & T_8483;
assign T_8493 = T_7440[46];
assign T_8494 = T_7572 & T_8493;
assign T_8500 = T_7578 & T_8493;
assign T_8503 = T_7570[46];
assign T_8504 = T_7582 & T_8503;
assign T_8510 = T_7588 & T_8503;
assign T_8513 = T_7440[47];
assign T_8514 = T_7572 & T_8513;
assign T_8520 = T_7578 & T_8513;
assign T_8523 = T_7570[47];
assign T_8524 = T_7582 & T_8523;
assign T_8530 = T_7588 & T_8523;
assign T_8853 = T_7440[64];
assign T_8854 = T_7572 & T_8853;
assign T_8860 = T_7578 & T_8853;
assign T_8863 = T_7570[64];
assign T_8864 = T_7582 & T_8863;
assign T_8870 = T_7588 & T_8863;
assign T_8873 = T_7440[65];
assign T_8874 = T_7572 & T_8873;
assign T_8880 = T_7578 & T_8873;
assign T_8883 = T_7570[65];
assign T_8884 = T_7582 & T_8883;
assign T_8890 = T_7588 & T_8883;
assign T_8893 = T_7440[66];
assign T_8894 = T_7572 & T_8893;
assign T_8900 = T_7578 & T_8893;
assign T_8903 = T_7570[66];
assign T_8904 = T_7582 & T_8903;
assign T_8910 = T_7588 & T_8903;
assign T_8913 = T_7440[67];
assign T_8914 = T_7572 & T_8913;
assign T_8920 = T_7578 & T_8913;
assign T_8923 = T_7570[67];
assign T_8924 = T_7582 & T_8923;
assign T_8930 = T_7588 & T_8923;
assign T_8933 = T_7440[68];
assign T_8934 = T_7572 & T_8933;
assign T_8940 = T_7578 & T_8933;
assign T_8943 = T_7570[68];
assign T_8944 = T_7582 & T_8943;
assign T_8950 = T_7588 & T_8943;
assign T_8953 = T_7440[69];
assign T_8954 = T_7572 & T_8953;
assign T_8960 = T_7578 & T_8953;
assign T_8963 = T_7570[69];
assign T_8964 = T_7582 & T_8963;
assign T_8970 = T_7588 & T_8963;
assign T_8973 = T_7440[70];
assign T_8974 = T_7572 & T_8973;
assign T_8980 = T_7578 & T_8973;
assign T_8983 = T_7570[70];
assign T_8984 = T_7582 & T_8983;
assign T_8990 = T_7588 & T_8983;
assign T_8993 = T_7440[71];
assign T_8994 = T_7572 & T_8993;
assign T_9000 = T_7578 & T_8993;
assign T_9003 = T_7570[71];
assign T_9004 = T_7582 & T_9003;
assign T_9010 = T_7588 & T_9003;
assign T_9013 = T_7440[72];
assign T_9014 = T_7572 & T_9013;
assign T_9020 = T_7578 & T_9013;
assign T_9023 = T_7570[72];
assign T_9024 = T_7582 & T_9023;
assign T_9030 = T_7588 & T_9023;
assign T_9033 = T_7440[73];
assign T_9034 = T_7572 & T_9033;
assign T_9040 = T_7578 & T_9033;
assign T_9043 = T_7570[73];
assign T_9044 = T_7582 & T_9043;
assign T_9050 = T_7588 & T_9043;
assign T_9053 = T_7440[74];
assign T_9054 = T_7572 & T_9053;
assign T_9060 = T_7578 & T_9053;
assign T_9063 = T_7570[74];
assign T_9064 = T_7582 & T_9063;
assign T_9070 = T_7588 & T_9063;
assign T_9073 = T_7440[75];
assign T_9074 = T_7572 & T_9073;
assign T_9080 = T_7578 & T_9073;
assign T_9083 = T_7570[75];
assign T_9084 = T_7582 & T_9083;
assign T_9090 = T_7588 & T_9083;
assign T_9093 = T_7440[76];
assign T_9094 = T_7572 & T_9093;
assign T_9100 = T_7578 & T_9093;
assign T_9103 = T_7570[76];
assign T_9104 = T_7582 & T_9103;
assign T_9110 = T_7588 & T_9103;
assign T_9113 = T_7440[77];
assign T_9114 = T_7572 & T_9113;
assign T_9120 = T_7578 & T_9113;
assign T_9123 = T_7570[77];
assign T_9124 = T_7582 & T_9123;
assign T_9130 = T_7588 & T_9123;
assign T_9133 = T_7440[78];
assign T_9134 = T_7572 & T_9133;
assign T_9140 = T_7578 & T_9133;
assign T_9143 = T_7570[78];
assign T_9144 = T_7582 & T_9143;
assign T_9150 = T_7588 & T_9143;
assign T_9153 = T_7440[79];
assign T_9154 = T_7572 & T_9153;
assign T_9160 = T_7578 & T_9153;
assign T_9163 = T_7570[79];
assign T_9164 = T_7582 & T_9163;
assign T_9170 = T_7588 & T_9163;
assign T_9173 = T_7440[80];
assign T_9174 = T_7572 & T_9173;
assign T_9180 = T_7578 & T_9173;
assign T_9183 = T_7570[80];
assign T_9184 = T_7582 & T_9183;
assign T_9190 = T_7588 & T_9183;
assign T_9193 = T_7440[81];
assign T_9194 = T_7572 & T_9193;
assign T_9200 = T_7578 & T_9193;
assign T_9203 = T_7570[81];
assign T_9204 = T_7582 & T_9203;
assign T_9210 = T_7588 & T_9203;
assign T_9213 = T_7440[82];
assign T_9214 = T_7572 & T_9213;
assign T_9220 = T_7578 & T_9213;
assign T_9223 = T_7570[82];
assign T_9224 = T_7582 & T_9223;
assign T_9230 = T_7588 & T_9223;
assign T_9233 = T_7440[83];
assign T_9234 = T_7572 & T_9233;
assign T_9240 = T_7578 & T_9233;
assign T_9243 = T_7570[83];
assign T_9244 = T_7582 & T_9243;
assign T_9250 = T_7588 & T_9243;
assign T_10462_0 = T_1326;
assign T_10462_1 = 1'h1;
assign T_10462_2 = T_1470;
assign T_10462_3 = T_1587;
assign T_10462_4 = T_1722;
assign T_10462_5 = 1'h1;
assign T_10462_6 = T_1398;
assign T_10462_7 = T_1560;
assign T_10462_8 = T_1677;
assign T_10462_9 = 1'h1;
assign T_10462_10 = 1'h1;
assign T_10462_11 = 1'h1;
assign T_10462_12 = 1'h1;
assign T_10462_13 = 1'h1;
assign T_10462_14 = 1'h1;
assign T_10462_15 = 1'h1;
assign T_10462_16 = T_1632;
assign T_10462_17 = 1'h1;
assign T_10462_18 = T_1614;
assign T_10462_19 = T_1713;
assign T_10462_20 = T_1362;
assign T_10462_21 = 1'h1;
assign T_10462_22 = T_1515;
assign T_10462_23 = T_1668;
assign T_10462_24 = T_1344;
assign T_10462_25 = 1'h1;
assign T_10462_26 = 1'h1;
assign T_10462_27 = 1'h1;
assign T_10462_28 = 1'h1;
assign T_10462_29 = 1'h1;
assign T_10462_30 = 1'h1;
assign T_10462_31 = 1'h1;
assign T_10462_32 = T_1479;
assign T_10462_33 = T_1425;
assign T_10462_34 = T_1488;
assign T_10462_35 = T_1605;
assign T_10462_36 = T_1704;
assign T_10462_37 = T_1353;
assign T_10462_38 = T_1407;
assign T_10462_39 = T_1569;
assign T_10462_40 = T_1659;
assign T_10462_41 = T_1452;
assign T_10462_42 = T_1335;
assign T_10462_43 = T_1650;
assign T_10462_44 = T_1524;
assign T_10462_45 = T_1497;
assign T_10462_46 = T_1371;
assign T_10462_47 = T_1740;
assign T_10462_48 = 1'h1;
assign T_10462_49 = 1'h1;
assign T_10462_50 = 1'h1;
assign T_10462_51 = 1'h1;
assign T_10462_52 = 1'h1;
assign T_10462_53 = 1'h1;
assign T_10462_54 = 1'h1;
assign T_10462_55 = 1'h1;
assign T_10462_56 = 1'h1;
assign T_10462_57 = 1'h1;
assign T_10462_58 = 1'h1;
assign T_10462_59 = 1'h1;
assign T_10462_60 = 1'h1;
assign T_10462_61 = 1'h1;
assign T_10462_62 = 1'h1;
assign T_10462_63 = 1'h1;
assign T_10462_64 = T_1506;
assign T_10462_65 = T_1434;
assign T_10462_66 = T_1578;
assign T_10462_67 = T_1623;
assign T_10462_68 = T_1749;
assign T_10462_69 = T_1317;
assign T_10462_70 = T_1416;
assign T_10462_71 = T_1533;
assign T_10462_72 = T_1641;
assign T_10462_73 = T_1461;
assign T_10462_74 = T_1389;
assign T_10462_75 = T_1686;
assign T_10462_76 = T_1551;
assign T_10462_77 = T_1443;
assign T_10462_78 = T_1380;
assign T_10462_79 = T_1731;
assign T_10462_80 = T_1596;
assign T_10462_81 = T_1542;
assign T_10462_82 = T_1695;
assign T_10462_83 = T_1758;
assign T_10462_84 = 1'h1;
assign T_10462_85 = 1'h1;
assign T_10462_86 = 1'h1;
assign T_10462_87 = 1'h1;
assign T_10462_88 = 1'h1;
assign T_10462_89 = 1'h1;
assign T_10462_90 = 1'h1;
assign T_10462_91 = 1'h1;
assign T_10462_92 = 1'h1;
assign T_10462_93 = 1'h1;
assign T_10462_94 = 1'h1;
assign T_10462_95 = 1'h1;
assign T_10462_96 = 1'h1;
assign T_10462_97 = 1'h1;
assign T_10462_98 = 1'h1;
assign T_10462_99 = 1'h1;
assign T_10462_100 = 1'h1;
assign T_10462_101 = 1'h1;
assign T_10462_102 = 1'h1;
assign T_10462_103 = 1'h1;
assign T_10462_104 = 1'h1;
assign T_10462_105 = 1'h1;
assign T_10462_106 = 1'h1;
assign T_10462_107 = 1'h1;
assign T_10462_108 = 1'h1;
assign T_10462_109 = 1'h1;
assign T_10462_110 = 1'h1;
assign T_10462_111 = 1'h1;
assign T_10462_112 = 1'h1;
assign T_10462_113 = 1'h1;
assign T_10462_114 = 1'h1;
assign T_10462_115 = 1'h1;
assign T_10462_116 = 1'h1;
assign T_10462_117 = 1'h1;
assign T_10462_118 = 1'h1;
assign T_10462_119 = 1'h1;
assign T_10462_120 = 1'h1;
assign T_10462_121 = 1'h1;
assign T_10462_122 = 1'h1;
assign T_10462_123 = 1'h1;
assign T_10462_124 = 1'h1;
assign T_10462_125 = 1'h1;
assign T_10462_126 = 1'h1;
assign T_10462_127 = 1'h1;
assign T_10725_0 = T_2560;
assign T_10725_1 = 32'h0;
assign T_10725_2 = T_3200;
assign T_10725_3 = T_3720;
assign T_10725_4 = {{16'd0}, T_4320};
assign T_10725_5 = 32'h0;
assign T_10725_6 = T_2880;
assign T_10725_7 = T_3600;
assign T_10725_8 = {{16'd0}, T_4120};
assign T_10725_9 = 32'h0;
assign T_10725_10 = 32'h0;
assign T_10725_11 = 32'h0;
assign T_10725_12 = 32'h0;
assign T_10725_13 = 32'h0;
assign T_10725_14 = 32'h0;
assign T_10725_15 = 32'h0;
assign T_10725_16 = T_3920;
assign T_10725_17 = 32'h0;
assign T_10725_18 = T_3840;
assign T_10725_19 = T_4280;
assign T_10725_20 = T_2720;
assign T_10725_21 = 32'h0;
assign T_10725_22 = T_3400;
assign T_10725_23 = T_4080;
assign T_10725_24 = T_2640;
assign T_10725_25 = 32'h0;
assign T_10725_26 = 32'h0;
assign T_10725_27 = 32'h0;
assign T_10725_28 = 32'h0;
assign T_10725_29 = 32'h0;
assign T_10725_30 = 32'h0;
assign T_10725_31 = 32'h0;
assign T_10725_32 = backupRegs_0;
assign T_10725_33 = backupRegs_1;
assign T_10725_34 = backupRegs_2;
assign T_10725_35 = backupRegs_3;
assign T_10725_36 = backupRegs_4;
assign T_10725_37 = backupRegs_5;
assign T_10725_38 = backupRegs_6;
assign T_10725_39 = backupRegs_7;
assign T_10725_40 = backupRegs_8;
assign T_10725_41 = backupRegs_9;
assign T_10725_42 = backupRegs_10;
assign T_10725_43 = backupRegs_11;
assign T_10725_44 = backupRegs_12;
assign T_10725_45 = backupRegs_13;
assign T_10725_46 = backupRegs_14;
assign T_10725_47 = backupRegs_15;
assign T_10725_48 = 32'h0;
assign T_10725_49 = 32'h0;
assign T_10725_50 = 32'h0;
assign T_10725_51 = 32'h0;
assign T_10725_52 = 32'h0;
assign T_10725_53 = 32'h0;
assign T_10725_54 = 32'h0;
assign T_10725_55 = 32'h0;
assign T_10725_56 = 32'h0;
assign T_10725_57 = 32'h0;
assign T_10725_58 = 32'h0;
assign T_10725_59 = 32'h0;
assign T_10725_60 = 32'h0;
assign T_10725_61 = 32'h0;
assign T_10725_62 = 32'h0;
assign T_10725_63 = 32'h0;
assign T_10725_64 = T_3360;
assign T_10725_65 = T_3040;
assign T_10725_66 = T_3680;
assign T_10725_67 = T_3880;
assign T_10725_68 = T_4440;
assign T_10725_69 = T_2520;
assign T_10725_70 = T_2960;
assign T_10725_71 = T_3480;
assign T_10725_72 = T_3960;
assign T_10725_73 = T_3160;
assign T_10725_74 = T_2840;
assign T_10725_75 = T_4160;
assign T_10725_76 = T_3560;
assign T_10725_77 = T_3080;
assign T_10725_78 = T_2800;
assign T_10725_79 = T_4360;
assign T_10725_80 = {{28'd0}, T_3760};
assign T_10725_81 = T_3520;
assign T_10725_82 = T_4200;
assign T_10725_83 = T_4480;
assign T_10725_84 = 32'h0;
assign T_10725_85 = 32'h0;
assign T_10725_86 = 32'h0;
assign T_10725_87 = 32'h0;
assign T_10725_88 = 32'h0;
assign T_10725_89 = 32'h0;
assign T_10725_90 = 32'h0;
assign T_10725_91 = 32'h0;
assign T_10725_92 = 32'h0;
assign T_10725_93 = 32'h0;
assign T_10725_94 = 32'h0;
assign T_10725_95 = 32'h0;
assign T_10725_96 = 32'h0;
assign T_10725_97 = 32'h0;
assign T_10725_98 = 32'h0;
assign T_10725_99 = 32'h0;
assign T_10725_100 = 32'h0;
assign T_10725_101 = 32'h0;
assign T_10725_102 = 32'h0;
assign T_10725_103 = 32'h0;
assign T_10725_104 = 32'h0;
assign T_10725_105 = 32'h0;
assign T_10725_106 = 32'h0;
assign T_10725_107 = 32'h0;
assign T_10725_108 = 32'h0;
assign T_10725_109 = 32'h0;
assign T_10725_110 = 32'h0;
assign T_10725_111 = 32'h0;
assign T_10725_112 = 32'h0;
assign T_10725_113 = 32'h0;
assign T_10725_114 = 32'h0;
assign T_10725_115 = 32'h0;
assign T_10725_116 = 32'h0;
assign T_10725_117 = 32'h0;
assign T_10725_118 = 32'h0;
assign T_10725_119 = 32'h0;
assign T_10725_120 = 32'h0;
assign T_10725_121 = 32'h0;
assign T_10725_122 = 32'h0;
assign T_10725_123 = 32'h0;
assign T_10725_124 = 32'h0;
assign T_10725_125 = 32'h0;
assign T_10725_126 = 32'h0;
assign T_10725_127 = 32'h0;
assign GEN_4 = GEN_656;
assign GEN_530 = 7'h1 == T_7300 ? T_10462_1 : T_10462_0;
assign GEN_531 = 7'h2 == T_7300 ? T_10462_2 : GEN_530;
assign GEN_532 = 7'h3 == T_7300 ? T_10462_3 : GEN_531;
assign GEN_533 = 7'h4 == T_7300 ? T_10462_4 : GEN_532;
assign GEN_534 = 7'h5 == T_7300 ? T_10462_5 : GEN_533;
assign GEN_535 = 7'h6 == T_7300 ? T_10462_6 : GEN_534;
assign GEN_536 = 7'h7 == T_7300 ? T_10462_7 : GEN_535;
assign GEN_537 = 7'h8 == T_7300 ? T_10462_8 : GEN_536;
assign GEN_538 = 7'h9 == T_7300 ? T_10462_9 : GEN_537;
assign GEN_539 = 7'ha == T_7300 ? T_10462_10 : GEN_538;
assign GEN_540 = 7'hb == T_7300 ? T_10462_11 : GEN_539;
assign GEN_541 = 7'hc == T_7300 ? T_10462_12 : GEN_540;
assign GEN_542 = 7'hd == T_7300 ? T_10462_13 : GEN_541;
assign GEN_543 = 7'he == T_7300 ? T_10462_14 : GEN_542;
assign GEN_544 = 7'hf == T_7300 ? T_10462_15 : GEN_543;
assign GEN_545 = 7'h10 == T_7300 ? T_10462_16 : GEN_544;
assign GEN_546 = 7'h11 == T_7300 ? T_10462_17 : GEN_545;
assign GEN_547 = 7'h12 == T_7300 ? T_10462_18 : GEN_546;
assign GEN_548 = 7'h13 == T_7300 ? T_10462_19 : GEN_547;
assign GEN_549 = 7'h14 == T_7300 ? T_10462_20 : GEN_548;
assign GEN_550 = 7'h15 == T_7300 ? T_10462_21 : GEN_549;
assign GEN_551 = 7'h16 == T_7300 ? T_10462_22 : GEN_550;
assign GEN_552 = 7'h17 == T_7300 ? T_10462_23 : GEN_551;
assign GEN_553 = 7'h18 == T_7300 ? T_10462_24 : GEN_552;
assign GEN_554 = 7'h19 == T_7300 ? T_10462_25 : GEN_553;
assign GEN_555 = 7'h1a == T_7300 ? T_10462_26 : GEN_554;
assign GEN_556 = 7'h1b == T_7300 ? T_10462_27 : GEN_555;
assign GEN_557 = 7'h1c == T_7300 ? T_10462_28 : GEN_556;
assign GEN_558 = 7'h1d == T_7300 ? T_10462_29 : GEN_557;
assign GEN_559 = 7'h1e == T_7300 ? T_10462_30 : GEN_558;
assign GEN_560 = 7'h1f == T_7300 ? T_10462_31 : GEN_559;
assign GEN_561 = 7'h20 == T_7300 ? T_10462_32 : GEN_560;
assign GEN_562 = 7'h21 == T_7300 ? T_10462_33 : GEN_561;
assign GEN_563 = 7'h22 == T_7300 ? T_10462_34 : GEN_562;
assign GEN_564 = 7'h23 == T_7300 ? T_10462_35 : GEN_563;
assign GEN_565 = 7'h24 == T_7300 ? T_10462_36 : GEN_564;
assign GEN_566 = 7'h25 == T_7300 ? T_10462_37 : GEN_565;
assign GEN_567 = 7'h26 == T_7300 ? T_10462_38 : GEN_566;
assign GEN_568 = 7'h27 == T_7300 ? T_10462_39 : GEN_567;
assign GEN_569 = 7'h28 == T_7300 ? T_10462_40 : GEN_568;
assign GEN_570 = 7'h29 == T_7300 ? T_10462_41 : GEN_569;
assign GEN_571 = 7'h2a == T_7300 ? T_10462_42 : GEN_570;
assign GEN_572 = 7'h2b == T_7300 ? T_10462_43 : GEN_571;
assign GEN_573 = 7'h2c == T_7300 ? T_10462_44 : GEN_572;
assign GEN_574 = 7'h2d == T_7300 ? T_10462_45 : GEN_573;
assign GEN_575 = 7'h2e == T_7300 ? T_10462_46 : GEN_574;
assign GEN_576 = 7'h2f == T_7300 ? T_10462_47 : GEN_575;
assign GEN_577 = 7'h30 == T_7300 ? T_10462_48 : GEN_576;
assign GEN_578 = 7'h31 == T_7300 ? T_10462_49 : GEN_577;
assign GEN_579 = 7'h32 == T_7300 ? T_10462_50 : GEN_578;
assign GEN_580 = 7'h33 == T_7300 ? T_10462_51 : GEN_579;
assign GEN_581 = 7'h34 == T_7300 ? T_10462_52 : GEN_580;
assign GEN_582 = 7'h35 == T_7300 ? T_10462_53 : GEN_581;
assign GEN_583 = 7'h36 == T_7300 ? T_10462_54 : GEN_582;
assign GEN_584 = 7'h37 == T_7300 ? T_10462_55 : GEN_583;
assign GEN_585 = 7'h38 == T_7300 ? T_10462_56 : GEN_584;
assign GEN_586 = 7'h39 == T_7300 ? T_10462_57 : GEN_585;
assign GEN_587 = 7'h3a == T_7300 ? T_10462_58 : GEN_586;
assign GEN_588 = 7'h3b == T_7300 ? T_10462_59 : GEN_587;
assign GEN_589 = 7'h3c == T_7300 ? T_10462_60 : GEN_588;
assign GEN_590 = 7'h3d == T_7300 ? T_10462_61 : GEN_589;
assign GEN_591 = 7'h3e == T_7300 ? T_10462_62 : GEN_590;
assign GEN_592 = 7'h3f == T_7300 ? T_10462_63 : GEN_591;
assign GEN_593 = 7'h40 == T_7300 ? T_10462_64 : GEN_592;
assign GEN_594 = 7'h41 == T_7300 ? T_10462_65 : GEN_593;
assign GEN_595 = 7'h42 == T_7300 ? T_10462_66 : GEN_594;
assign GEN_596 = 7'h43 == T_7300 ? T_10462_67 : GEN_595;
assign GEN_597 = 7'h44 == T_7300 ? T_10462_68 : GEN_596;
assign GEN_598 = 7'h45 == T_7300 ? T_10462_69 : GEN_597;
assign GEN_599 = 7'h46 == T_7300 ? T_10462_70 : GEN_598;
assign GEN_600 = 7'h47 == T_7300 ? T_10462_71 : GEN_599;
assign GEN_601 = 7'h48 == T_7300 ? T_10462_72 : GEN_600;
assign GEN_602 = 7'h49 == T_7300 ? T_10462_73 : GEN_601;
assign GEN_603 = 7'h4a == T_7300 ? T_10462_74 : GEN_602;
assign GEN_604 = 7'h4b == T_7300 ? T_10462_75 : GEN_603;
assign GEN_605 = 7'h4c == T_7300 ? T_10462_76 : GEN_604;
assign GEN_606 = 7'h4d == T_7300 ? T_10462_77 : GEN_605;
assign GEN_607 = 7'h4e == T_7300 ? T_10462_78 : GEN_606;
assign GEN_608 = 7'h4f == T_7300 ? T_10462_79 : GEN_607;
assign GEN_609 = 7'h50 == T_7300 ? T_10462_80 : GEN_608;
assign GEN_610 = 7'h51 == T_7300 ? T_10462_81 : GEN_609;
assign GEN_611 = 7'h52 == T_7300 ? T_10462_82 : GEN_610;
assign GEN_612 = 7'h53 == T_7300 ? T_10462_83 : GEN_611;
assign GEN_613 = 7'h54 == T_7300 ? T_10462_84 : GEN_612;
assign GEN_614 = 7'h55 == T_7300 ? T_10462_85 : GEN_613;
assign GEN_615 = 7'h56 == T_7300 ? T_10462_86 : GEN_614;
assign GEN_616 = 7'h57 == T_7300 ? T_10462_87 : GEN_615;
assign GEN_617 = 7'h58 == T_7300 ? T_10462_88 : GEN_616;
assign GEN_618 = 7'h59 == T_7300 ? T_10462_89 : GEN_617;
assign GEN_619 = 7'h5a == T_7300 ? T_10462_90 : GEN_618;
assign GEN_620 = 7'h5b == T_7300 ? T_10462_91 : GEN_619;
assign GEN_621 = 7'h5c == T_7300 ? T_10462_92 : GEN_620;
assign GEN_622 = 7'h5d == T_7300 ? T_10462_93 : GEN_621;
assign GEN_623 = 7'h5e == T_7300 ? T_10462_94 : GEN_622;
assign GEN_624 = 7'h5f == T_7300 ? T_10462_95 : GEN_623;
assign GEN_625 = 7'h60 == T_7300 ? T_10462_96 : GEN_624;
assign GEN_626 = 7'h61 == T_7300 ? T_10462_97 : GEN_625;
assign GEN_627 = 7'h62 == T_7300 ? T_10462_98 : GEN_626;
assign GEN_628 = 7'h63 == T_7300 ? T_10462_99 : GEN_627;
assign GEN_629 = 7'h64 == T_7300 ? T_10462_100 : GEN_628;
assign GEN_630 = 7'h65 == T_7300 ? T_10462_101 : GEN_629;
assign GEN_631 = 7'h66 == T_7300 ? T_10462_102 : GEN_630;
assign GEN_632 = 7'h67 == T_7300 ? T_10462_103 : GEN_631;
assign GEN_633 = 7'h68 == T_7300 ? T_10462_104 : GEN_632;
assign GEN_634 = 7'h69 == T_7300 ? T_10462_105 : GEN_633;
assign GEN_635 = 7'h6a == T_7300 ? T_10462_106 : GEN_634;
assign GEN_636 = 7'h6b == T_7300 ? T_10462_107 : GEN_635;
assign GEN_637 = 7'h6c == T_7300 ? T_10462_108 : GEN_636;
assign GEN_638 = 7'h6d == T_7300 ? T_10462_109 : GEN_637;
assign GEN_639 = 7'h6e == T_7300 ? T_10462_110 : GEN_638;
assign GEN_640 = 7'h6f == T_7300 ? T_10462_111 : GEN_639;
assign GEN_641 = 7'h70 == T_7300 ? T_10462_112 : GEN_640;
assign GEN_642 = 7'h71 == T_7300 ? T_10462_113 : GEN_641;
assign GEN_643 = 7'h72 == T_7300 ? T_10462_114 : GEN_642;
assign GEN_644 = 7'h73 == T_7300 ? T_10462_115 : GEN_643;
assign GEN_645 = 7'h74 == T_7300 ? T_10462_116 : GEN_644;
assign GEN_646 = 7'h75 == T_7300 ? T_10462_117 : GEN_645;
assign GEN_647 = 7'h76 == T_7300 ? T_10462_118 : GEN_646;
assign GEN_648 = 7'h77 == T_7300 ? T_10462_119 : GEN_647;
assign GEN_649 = 7'h78 == T_7300 ? T_10462_120 : GEN_648;
assign GEN_650 = 7'h79 == T_7300 ? T_10462_121 : GEN_649;
assign GEN_651 = 7'h7a == T_7300 ? T_10462_122 : GEN_650;
assign GEN_652 = 7'h7b == T_7300 ? T_10462_123 : GEN_651;
assign GEN_653 = 7'h7c == T_7300 ? T_10462_124 : GEN_652;
assign GEN_654 = 7'h7d == T_7300 ? T_10462_125 : GEN_653;
assign GEN_655 = 7'h7e == T_7300 ? T_10462_126 : GEN_654;
assign GEN_656 = 7'h7f == T_7300 ? T_10462_127 : GEN_655;
assign GEN_5 = GEN_783;
assign GEN_657 = 7'h1 == T_7300 ? T_10725_1 : T_10725_0;
assign GEN_658 = 7'h2 == T_7300 ? T_10725_2 : GEN_657;
assign GEN_659 = 7'h3 == T_7300 ? T_10725_3 : GEN_658;
assign GEN_660 = 7'h4 == T_7300 ? T_10725_4 : GEN_659;
assign GEN_661 = 7'h5 == T_7300 ? T_10725_5 : GEN_660;
assign GEN_662 = 7'h6 == T_7300 ? T_10725_6 : GEN_661;
assign GEN_663 = 7'h7 == T_7300 ? T_10725_7 : GEN_662;
assign GEN_664 = 7'h8 == T_7300 ? T_10725_8 : GEN_663;
assign GEN_665 = 7'h9 == T_7300 ? T_10725_9 : GEN_664;
assign GEN_666 = 7'ha == T_7300 ? T_10725_10 : GEN_665;
assign GEN_667 = 7'hb == T_7300 ? T_10725_11 : GEN_666;
assign GEN_668 = 7'hc == T_7300 ? T_10725_12 : GEN_667;
assign GEN_669 = 7'hd == T_7300 ? T_10725_13 : GEN_668;
assign GEN_670 = 7'he == T_7300 ? T_10725_14 : GEN_669;
assign GEN_671 = 7'hf == T_7300 ? T_10725_15 : GEN_670;
assign GEN_672 = 7'h10 == T_7300 ? T_10725_16 : GEN_671;
assign GEN_673 = 7'h11 == T_7300 ? T_10725_17 : GEN_672;
assign GEN_674 = 7'h12 == T_7300 ? T_10725_18 : GEN_673;
assign GEN_675 = 7'h13 == T_7300 ? T_10725_19 : GEN_674;
assign GEN_676 = 7'h14 == T_7300 ? T_10725_20 : GEN_675;
assign GEN_677 = 7'h15 == T_7300 ? T_10725_21 : GEN_676;
assign GEN_678 = 7'h16 == T_7300 ? T_10725_22 : GEN_677;
assign GEN_679 = 7'h17 == T_7300 ? T_10725_23 : GEN_678;
assign GEN_680 = 7'h18 == T_7300 ? T_10725_24 : GEN_679;
assign GEN_681 = 7'h19 == T_7300 ? T_10725_25 : GEN_680;
assign GEN_682 = 7'h1a == T_7300 ? T_10725_26 : GEN_681;
assign GEN_683 = 7'h1b == T_7300 ? T_10725_27 : GEN_682;
assign GEN_684 = 7'h1c == T_7300 ? T_10725_28 : GEN_683;
assign GEN_685 = 7'h1d == T_7300 ? T_10725_29 : GEN_684;
assign GEN_686 = 7'h1e == T_7300 ? T_10725_30 : GEN_685;
assign GEN_687 = 7'h1f == T_7300 ? T_10725_31 : GEN_686;
assign GEN_688 = 7'h20 == T_7300 ? T_10725_32 : GEN_687;
assign GEN_689 = 7'h21 == T_7300 ? T_10725_33 : GEN_688;
assign GEN_690 = 7'h22 == T_7300 ? T_10725_34 : GEN_689;
assign GEN_691 = 7'h23 == T_7300 ? T_10725_35 : GEN_690;
assign GEN_692 = 7'h24 == T_7300 ? T_10725_36 : GEN_691;
assign GEN_693 = 7'h25 == T_7300 ? T_10725_37 : GEN_692;
assign GEN_694 = 7'h26 == T_7300 ? T_10725_38 : GEN_693;
assign GEN_695 = 7'h27 == T_7300 ? T_10725_39 : GEN_694;
assign GEN_696 = 7'h28 == T_7300 ? T_10725_40 : GEN_695;
assign GEN_697 = 7'h29 == T_7300 ? T_10725_41 : GEN_696;
assign GEN_698 = 7'h2a == T_7300 ? T_10725_42 : GEN_697;
assign GEN_699 = 7'h2b == T_7300 ? T_10725_43 : GEN_698;
assign GEN_700 = 7'h2c == T_7300 ? T_10725_44 : GEN_699;
assign GEN_701 = 7'h2d == T_7300 ? T_10725_45 : GEN_700;
assign GEN_702 = 7'h2e == T_7300 ? T_10725_46 : GEN_701;
assign GEN_703 = 7'h2f == T_7300 ? T_10725_47 : GEN_702;
assign GEN_704 = 7'h30 == T_7300 ? T_10725_48 : GEN_703;
assign GEN_705 = 7'h31 == T_7300 ? T_10725_49 : GEN_704;
assign GEN_706 = 7'h32 == T_7300 ? T_10725_50 : GEN_705;
assign GEN_707 = 7'h33 == T_7300 ? T_10725_51 : GEN_706;
assign GEN_708 = 7'h34 == T_7300 ? T_10725_52 : GEN_707;
assign GEN_709 = 7'h35 == T_7300 ? T_10725_53 : GEN_708;
assign GEN_710 = 7'h36 == T_7300 ? T_10725_54 : GEN_709;
assign GEN_711 = 7'h37 == T_7300 ? T_10725_55 : GEN_710;
assign GEN_712 = 7'h38 == T_7300 ? T_10725_56 : GEN_711;
assign GEN_713 = 7'h39 == T_7300 ? T_10725_57 : GEN_712;
assign GEN_714 = 7'h3a == T_7300 ? T_10725_58 : GEN_713;
assign GEN_715 = 7'h3b == T_7300 ? T_10725_59 : GEN_714;
assign GEN_716 = 7'h3c == T_7300 ? T_10725_60 : GEN_715;
assign GEN_717 = 7'h3d == T_7300 ? T_10725_61 : GEN_716;
assign GEN_718 = 7'h3e == T_7300 ? T_10725_62 : GEN_717;
assign GEN_719 = 7'h3f == T_7300 ? T_10725_63 : GEN_718;
assign GEN_720 = 7'h40 == T_7300 ? T_10725_64 : GEN_719;
assign GEN_721 = 7'h41 == T_7300 ? T_10725_65 : GEN_720;
assign GEN_722 = 7'h42 == T_7300 ? T_10725_66 : GEN_721;
assign GEN_723 = 7'h43 == T_7300 ? T_10725_67 : GEN_722;
assign GEN_724 = 7'h44 == T_7300 ? T_10725_68 : GEN_723;
assign GEN_725 = 7'h45 == T_7300 ? T_10725_69 : GEN_724;
assign GEN_726 = 7'h46 == T_7300 ? T_10725_70 : GEN_725;
assign GEN_727 = 7'h47 == T_7300 ? T_10725_71 : GEN_726;
assign GEN_728 = 7'h48 == T_7300 ? T_10725_72 : GEN_727;
assign GEN_729 = 7'h49 == T_7300 ? T_10725_73 : GEN_728;
assign GEN_730 = 7'h4a == T_7300 ? T_10725_74 : GEN_729;
assign GEN_731 = 7'h4b == T_7300 ? T_10725_75 : GEN_730;
assign GEN_732 = 7'h4c == T_7300 ? T_10725_76 : GEN_731;
assign GEN_733 = 7'h4d == T_7300 ? T_10725_77 : GEN_732;
assign GEN_734 = 7'h4e == T_7300 ? T_10725_78 : GEN_733;
assign GEN_735 = 7'h4f == T_7300 ? T_10725_79 : GEN_734;
assign GEN_736 = 7'h50 == T_7300 ? T_10725_80 : GEN_735;
assign GEN_737 = 7'h51 == T_7300 ? T_10725_81 : GEN_736;
assign GEN_738 = 7'h52 == T_7300 ? T_10725_82 : GEN_737;
assign GEN_739 = 7'h53 == T_7300 ? T_10725_83 : GEN_738;
assign GEN_740 = 7'h54 == T_7300 ? T_10725_84 : GEN_739;
assign GEN_741 = 7'h55 == T_7300 ? T_10725_85 : GEN_740;
assign GEN_742 = 7'h56 == T_7300 ? T_10725_86 : GEN_741;
assign GEN_743 = 7'h57 == T_7300 ? T_10725_87 : GEN_742;
assign GEN_744 = 7'h58 == T_7300 ? T_10725_88 : GEN_743;
assign GEN_745 = 7'h59 == T_7300 ? T_10725_89 : GEN_744;
assign GEN_746 = 7'h5a == T_7300 ? T_10725_90 : GEN_745;
assign GEN_747 = 7'h5b == T_7300 ? T_10725_91 : GEN_746;
assign GEN_748 = 7'h5c == T_7300 ? T_10725_92 : GEN_747;
assign GEN_749 = 7'h5d == T_7300 ? T_10725_93 : GEN_748;
assign GEN_750 = 7'h5e == T_7300 ? T_10725_94 : GEN_749;
assign GEN_751 = 7'h5f == T_7300 ? T_10725_95 : GEN_750;
assign GEN_752 = 7'h60 == T_7300 ? T_10725_96 : GEN_751;
assign GEN_753 = 7'h61 == T_7300 ? T_10725_97 : GEN_752;
assign GEN_754 = 7'h62 == T_7300 ? T_10725_98 : GEN_753;
assign GEN_755 = 7'h63 == T_7300 ? T_10725_99 : GEN_754;
assign GEN_756 = 7'h64 == T_7300 ? T_10725_100 : GEN_755;
assign GEN_757 = 7'h65 == T_7300 ? T_10725_101 : GEN_756;
assign GEN_758 = 7'h66 == T_7300 ? T_10725_102 : GEN_757;
assign GEN_759 = 7'h67 == T_7300 ? T_10725_103 : GEN_758;
assign GEN_760 = 7'h68 == T_7300 ? T_10725_104 : GEN_759;
assign GEN_761 = 7'h69 == T_7300 ? T_10725_105 : GEN_760;
assign GEN_762 = 7'h6a == T_7300 ? T_10725_106 : GEN_761;
assign GEN_763 = 7'h6b == T_7300 ? T_10725_107 : GEN_762;
assign GEN_764 = 7'h6c == T_7300 ? T_10725_108 : GEN_763;
assign GEN_765 = 7'h6d == T_7300 ? T_10725_109 : GEN_764;
assign GEN_766 = 7'h6e == T_7300 ? T_10725_110 : GEN_765;
assign GEN_767 = 7'h6f == T_7300 ? T_10725_111 : GEN_766;
assign GEN_768 = 7'h70 == T_7300 ? T_10725_112 : GEN_767;
assign GEN_769 = 7'h71 == T_7300 ? T_10725_113 : GEN_768;
assign GEN_770 = 7'h72 == T_7300 ? T_10725_114 : GEN_769;
assign GEN_771 = 7'h73 == T_7300 ? T_10725_115 : GEN_770;
assign GEN_772 = 7'h74 == T_7300 ? T_10725_116 : GEN_771;
assign GEN_773 = 7'h75 == T_7300 ? T_10725_117 : GEN_772;
assign GEN_774 = 7'h76 == T_7300 ? T_10725_118 : GEN_773;
assign GEN_775 = 7'h77 == T_7300 ? T_10725_119 : GEN_774;
assign GEN_776 = 7'h78 == T_7300 ? T_10725_120 : GEN_775;
assign GEN_777 = 7'h79 == T_7300 ? T_10725_121 : GEN_776;
assign GEN_778 = 7'h7a == T_7300 ? T_10725_122 : GEN_777;
assign GEN_779 = 7'h7b == T_7300 ? T_10725_123 : GEN_778;
assign GEN_780 = 7'h7c == T_7300 ? T_10725_124 : GEN_779;
assign GEN_781 = 7'h7d == T_7300 ? T_10725_125 : GEN_780;
assign GEN_782 = 7'h7e == T_7300 ? T_10725_126 : GEN_781;
assign GEN_783 = 7'h7f == T_7300 ? T_10725_127 : GEN_782;
assign T_10858 = GEN_4 ? GEN_5 : 32'h0;
assign T_10859 = T_992_bits_extra[9:8];
assign T_10861 = T_992_bits_extra[7:3];
assign T_10862 = T_992_bits_extra[2:0];
assign T_10873_opcode = 3'h0;
assign T_10873_param = 2'h0;
assign T_10873_size = T_10862;
assign T_10873_source = T_10861;
assign T_10873_sink = 1'h0;
assign T_10873_addr_lo = T_10859;
assign T_10873_data = 32'h0;
assign T_10873_error = 1'h0;
always @(posedge clock) begin // Backup register no need to be reset
if (T_3224) begin
backupRegs_0 <= T_2505;
end
if (T_2984) begin
backupRegs_1 <= T_2505;
end
if (T_3264) begin
backupRegs_2 <= T_2505;
end
if (T_3784) begin
backupRegs_3 <= T_2505;
end
if (T_4224) begin
backupRegs_4 <= T_2505;
end
if (T_2664) begin
backupRegs_5 <= T_2505;
end
if (T_2904) begin
backupRegs_6 <= T_2505;
end
if (T_3624) begin
backupRegs_7 <= T_2505;
end
if (T_4024) begin
backupRegs_8 <= T_2505;
end
if (T_3104) begin
backupRegs_9 <= T_2505;
end
if (T_2584) begin
backupRegs_10 <= T_2505;
end
if (T_3984) begin
backupRegs_11 <= T_2505;
end
if (T_3424) begin
backupRegs_12 <= T_2505;
end
if (T_3304) begin
backupRegs_13 <= T_2505;
end
if (T_2744) begin
backupRegs_14 <= T_2505;
end
if (T_4384) begin
backupRegs_15 <= T_2505;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_2_V
`define SKY130_FD_SC_HS__NOR2B_2_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_2 (
Y ,
A ,
B_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_2 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_BLACKBOX_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w8_d2_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w8_d2_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w8_d2_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w8_d2_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_hart0_server_reset_request_put O 1 reg
// hart0_server_reset_response_get O 1 reg
// RDY_hart0_server_reset_response_get O 1 reg
// imem_master_awvalid O 1 reg
// imem_master_awid O 4 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 4 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// dma_server_awready O 1 const
// dma_server_wready O 1 const
// dma_server_bvalid O 1 const
// dma_server_bid O 16 const
// dma_server_bresp O 2 const
// dma_server_arready O 1 const
// dma_server_rvalid O 1 const
// dma_server_rid O 16 const
// dma_server_rdata O 512 const
// dma_server_rresp O 2 const
// dma_server_rlast O 1 const
// RDY_set_verbosity O 1 const
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// hart0_server_reset_request_put I 1 reg
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 4 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 4 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// dma_server_awvalid I 1 unused
// dma_server_awid I 16 unused
// dma_server_awaddr I 64 unused
// dma_server_awlen I 8 unused
// dma_server_awsize I 3 unused
// dma_server_awburst I 2 unused
// dma_server_awlock I 1 unused
// dma_server_awcache I 4 unused
// dma_server_awprot I 3 unused
// dma_server_awqos I 4 unused
// dma_server_awregion I 4 unused
// dma_server_wvalid I 1 unused
// dma_server_wdata I 512 unused
// dma_server_wstrb I 64 unused
// dma_server_wlast I 1 unused
// dma_server_bready I 1 unused
// dma_server_arvalid I 1 unused
// dma_server_arid I 16 unused
// dma_server_araddr I 64 unused
// dma_server_arlen I 8 unused
// dma_server_arsize I 3 unused
// dma_server_arburst I 2 unused
// dma_server_arlock I 1 unused
// dma_server_arcache I 4 unused
// dma_server_arprot I 3 unused
// dma_server_arqos I 4 unused
// dma_server_arregion I 4 unused
// dma_server_rready I 1 unused
// m_external_interrupt_req_set_not_clear I 1 reg
// s_external_interrupt_req_set_not_clear I 1 reg
// software_interrupt_req_set_not_clear I 1 reg
// timer_interrupt_req_set_not_clear I 1 reg
// nmi_req_set_not_clear I 1
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_hart0_server_reset_request_put I 1
// EN_set_verbosity I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
// EN_hart0_server_reset_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCPU(CLK,
RST_N,
hart0_server_reset_request_put,
EN_hart0_server_reset_request_put,
RDY_hart0_server_reset_request_put,
EN_hart0_server_reset_response_get,
hart0_server_reset_response_get,
RDY_hart0_server_reset_response_get,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
dma_server_awvalid,
dma_server_awid,
dma_server_awaddr,
dma_server_awlen,
dma_server_awsize,
dma_server_awburst,
dma_server_awlock,
dma_server_awcache,
dma_server_awprot,
dma_server_awqos,
dma_server_awregion,
dma_server_awready,
dma_server_wvalid,
dma_server_wdata,
dma_server_wstrb,
dma_server_wlast,
dma_server_wready,
dma_server_bvalid,
dma_server_bid,
dma_server_bresp,
dma_server_bready,
dma_server_arvalid,
dma_server_arid,
dma_server_araddr,
dma_server_arlen,
dma_server_arsize,
dma_server_arburst,
dma_server_arlock,
dma_server_arcache,
dma_server_arprot,
dma_server_arqos,
dma_server_arregion,
dma_server_arready,
dma_server_rvalid,
dma_server_rid,
dma_server_rdata,
dma_server_rresp,
dma_server_rlast,
dma_server_rready,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
software_interrupt_req_set_not_clear,
timer_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input CLK;
input RST_N;
// action method hart0_server_reset_request_put
input hart0_server_reset_request_put;
input EN_hart0_server_reset_request_put;
output RDY_hart0_server_reset_request_put;
// actionvalue method hart0_server_reset_response_get
input EN_hart0_server_reset_response_get;
output hart0_server_reset_response_get;
output RDY_hart0_server_reset_response_get;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [3 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [3 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [3 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [3 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method dma_server_m_awvalid
input dma_server_awvalid;
input [15 : 0] dma_server_awid;
input [63 : 0] dma_server_awaddr;
input [7 : 0] dma_server_awlen;
input [2 : 0] dma_server_awsize;
input [1 : 0] dma_server_awburst;
input dma_server_awlock;
input [3 : 0] dma_server_awcache;
input [2 : 0] dma_server_awprot;
input [3 : 0] dma_server_awqos;
input [3 : 0] dma_server_awregion;
// value method dma_server_m_awready
output dma_server_awready;
// action method dma_server_m_wvalid
input dma_server_wvalid;
input [511 : 0] dma_server_wdata;
input [63 : 0] dma_server_wstrb;
input dma_server_wlast;
// value method dma_server_m_wready
output dma_server_wready;
// value method dma_server_m_bvalid
output dma_server_bvalid;
// value method dma_server_m_bid
output [15 : 0] dma_server_bid;
// value method dma_server_m_bresp
output [1 : 0] dma_server_bresp;
// value method dma_server_m_buser
// action method dma_server_m_bready
input dma_server_bready;
// action method dma_server_m_arvalid
input dma_server_arvalid;
input [15 : 0] dma_server_arid;
input [63 : 0] dma_server_araddr;
input [7 : 0] dma_server_arlen;
input [2 : 0] dma_server_arsize;
input [1 : 0] dma_server_arburst;
input dma_server_arlock;
input [3 : 0] dma_server_arcache;
input [2 : 0] dma_server_arprot;
input [3 : 0] dma_server_arqos;
input [3 : 0] dma_server_arregion;
// value method dma_server_m_arready
output dma_server_arready;
// value method dma_server_m_rvalid
output dma_server_rvalid;
// value method dma_server_m_rid
output [15 : 0] dma_server_rid;
// value method dma_server_m_rdata
output [511 : 0] dma_server_rdata;
// value method dma_server_m_rresp
output [1 : 0] dma_server_rresp;
// value method dma_server_m_rlast
output dma_server_rlast;
// value method dma_server_m_ruser
// action method dma_server_m_rready
input dma_server_rready;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method software_interrupt_req
input software_interrupt_req_set_not_clear;
// action method timer_interrupt_req
input timer_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value;
wire [15 : 0] dma_server_bid, dma_server_rid;
wire [7 : 0] imem_master_arlen,
imem_master_awlen,
imem_master_wstrb,
mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] imem_master_arcache,
imem_master_arid,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awid,
imem_master_awqos,
imem_master_awregion,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize,
mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] dma_server_bresp,
dma_server_rresp,
imem_master_arburst,
imem_master_awburst,
mem_master_arburst,
mem_master_awburst;
wire RDY_hart0_server_reset_request_put,
RDY_hart0_server_reset_response_get,
RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_set_verbosity,
RDY_set_watch_tohost,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready,
hart0_server_reset_response_get,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid;
// register cfg_logdelay
reg [63 : 0] cfg_logdelay;
wire [63 : 0] cfg_logdelay$D_IN;
wire cfg_logdelay$EN;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register imem_rg_cache_addr
reg [63 : 0] imem_rg_cache_addr;
reg [63 : 0] imem_rg_cache_addr$D_IN;
wire imem_rg_cache_addr$EN;
// register imem_rg_cache_b16
reg [15 : 0] imem_rg_cache_b16;
wire [15 : 0] imem_rg_cache_b16$D_IN;
wire imem_rg_cache_b16$EN;
// register imem_rg_f3
reg [2 : 0] imem_rg_f3;
wire [2 : 0] imem_rg_f3$D_IN;
wire imem_rg_f3$EN;
// register imem_rg_mstatus_MXR
reg imem_rg_mstatus_MXR;
wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;
// register imem_rg_pc
reg [63 : 0] imem_rg_pc;
reg [63 : 0] imem_rg_pc$D_IN;
wire imem_rg_pc$EN;
// register imem_rg_priv
reg [1 : 0] imem_rg_priv;
wire [1 : 0] imem_rg_priv$D_IN;
wire imem_rg_priv$EN;
// register imem_rg_satp
reg [63 : 0] imem_rg_satp;
wire [63 : 0] imem_rg_satp$D_IN;
wire imem_rg_satp$EN;
// register imem_rg_sstatus_SUM
reg imem_rg_sstatus_SUM;
wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;
// register imem_rg_tval
reg [63 : 0] imem_rg_tval;
reg [63 : 0] imem_rg_tval$D_IN;
wire imem_rg_tval$EN;
// register rg_csr_pc
reg [63 : 0] rg_csr_pc;
wire [63 : 0] rg_csr_pc$D_IN;
wire rg_csr_pc$EN;
// register rg_csr_val1
reg [63 : 0] rg_csr_val1;
wire [63 : 0] rg_csr_val1$D_IN;
wire rg_csr_val1$EN;
// register rg_cur_priv
reg [1 : 0] rg_cur_priv;
reg [1 : 0] rg_cur_priv$D_IN;
wire rg_cur_priv$EN;
// register rg_epoch
reg [1 : 0] rg_epoch;
reg [1 : 0] rg_epoch$D_IN;
wire rg_epoch$EN;
// register rg_mstatus_MXR
reg rg_mstatus_MXR;
wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;
// register rg_next_pc
reg [63 : 0] rg_next_pc;
reg [63 : 0] rg_next_pc$D_IN;
wire rg_next_pc$EN;
// register rg_run_on_reset
reg rg_run_on_reset;
wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;
// register rg_sstatus_SUM
reg rg_sstatus_SUM;
wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;
// register rg_start_CPI_cycles
reg [63 : 0] rg_start_CPI_cycles;
wire [63 : 0] rg_start_CPI_cycles$D_IN;
wire rg_start_CPI_cycles$EN;
// register rg_start_CPI_instrs
reg [63 : 0] rg_start_CPI_instrs;
wire [63 : 0] rg_start_CPI_instrs$D_IN;
wire rg_start_CPI_instrs$EN;
// register rg_state
reg [3 : 0] rg_state;
reg [3 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_trap_info
reg [131 : 0] rg_trap_info;
reg [131 : 0] rg_trap_info$D_IN;
wire rg_trap_info$EN;
// register rg_trap_instr
reg [31 : 0] rg_trap_instr;
wire [31 : 0] rg_trap_instr$D_IN;
wire rg_trap_instr$EN;
// register rg_trap_interrupt
reg rg_trap_interrupt;
wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;
// register stage1_rg_full
reg stage1_rg_full;
reg stage1_rg_full$D_IN;
wire stage1_rg_full$EN;
// register stage1_rg_stage_input
reg [401 : 0] stage1_rg_stage_input;
wire [401 : 0] stage1_rg_stage_input$D_IN;
wire stage1_rg_stage_input$EN;
// register stage2_rg_full
reg stage2_rg_full;
reg stage2_rg_full$D_IN;
wire stage2_rg_full$EN;
// register stage2_rg_resetting
reg stage2_rg_resetting;
wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;
// register stage2_rg_stage2
reg [495 : 0] stage2_rg_stage2;
wire [495 : 0] stage2_rg_stage2$D_IN;
wire stage2_rg_stage2$EN;
// register stage3_rg_full
reg stage3_rg_full;
reg stage3_rg_full$D_IN;
wire stage3_rg_full$EN;
// register stage3_rg_stage3
reg [238 : 0] stage3_rg_stage3;
wire [238 : 0] stage3_rg_stage3$D_IN;
wire stage3_rg_stage3$EN;
// register stageD_rg_data
reg [233 : 0] stageD_rg_data;
wire [233 : 0] stageD_rg_data$D_IN;
wire stageD_rg_data$EN;
// register stageD_rg_full
reg stageD_rg_full;
reg stageD_rg_full$D_IN;
wire stageD_rg_full$EN;
// register stageF_rg_epoch
reg [1 : 0] stageF_rg_epoch;
reg [1 : 0] stageF_rg_epoch$D_IN;
wire stageF_rg_epoch$EN;
// register stageF_rg_full
reg stageF_rg_full;
reg stageF_rg_full$D_IN;
wire stageF_rg_full$EN;
// register stageF_rg_priv
reg [1 : 0] stageF_rg_priv;
wire [1 : 0] stageF_rg_priv$D_IN;
wire stageF_rg_priv$EN;
// ports of submodule csr_regfile
wire [193 : 0] csr_regfile$csr_trap_actions;
wire [129 : 0] csr_regfile$csr_ret_actions;
wire [64 : 0] csr_regfile$read_csr;
wire [63 : 0] csr_regfile$csr_trap_actions_pc,
csr_regfile$csr_trap_actions_xtval,
csr_regfile$mav_csr_write_word,
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
csr_regfile$read_mstatus,
csr_regfile$read_satp,
csr_regfile$read_sstatus;
wire [27 : 0] csr_regfile$read_misa;
wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
csr_regfile$access_permitted_2_csr_addr,
csr_regfile$csr_counter_read_fault_csr_addr,
csr_regfile$mav_csr_write_csr_addr,
csr_regfile$mav_read_csr_csr_addr,
csr_regfile$read_csr_csr_addr,
csr_regfile$read_csr_port2_csr_addr;
wire [4 : 0] csr_regfile$interrupt_pending,
csr_regfile$ma_update_fcsr_fflags_flags,
csr_regfile$mv_update_fcsr_fflags_flags;
wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
wire [2 : 0] csr_regfile$read_frm;
wire [1 : 0] csr_regfile$access_permitted_1_priv,
csr_regfile$access_permitted_2_priv,
csr_regfile$csr_counter_read_fault_priv,
csr_regfile$csr_ret_actions_from_priv,
csr_regfile$csr_trap_actions_from_priv,
csr_regfile$interrupt_pending_cur_priv,
csr_regfile$ma_update_mstatus_fs_fs,
csr_regfile$mv_update_mstatus_fs_fs;
wire csr_regfile$EN_csr_minstret_incr,
csr_regfile$EN_csr_ret_actions,
csr_regfile$EN_csr_trap_actions,
csr_regfile$EN_debug,
csr_regfile$EN_ma_update_fcsr_fflags,
csr_regfile$EN_ma_update_mstatus_fs,
csr_regfile$EN_mav_csr_write,
csr_regfile$EN_mav_read_csr,
csr_regfile$EN_server_reset_request_put,
csr_regfile$EN_server_reset_response_get,
csr_regfile$RDY_server_reset_request_put,
csr_regfile$RDY_server_reset_response_get,
csr_regfile$access_permitted_1,
csr_regfile$access_permitted_1_read_not_write,
csr_regfile$access_permitted_2,
csr_regfile$access_permitted_2_read_not_write,
csr_regfile$csr_trap_actions_interrupt,
csr_regfile$csr_trap_actions_nmi,
csr_regfile$m_external_interrupt_req_set_not_clear,
csr_regfile$nmi_pending,
csr_regfile$nmi_req_set_not_clear,
csr_regfile$s_external_interrupt_req_set_not_clear,
csr_regfile$software_interrupt_req_set_not_clear,
csr_regfile$timer_interrupt_req_set_not_clear,
csr_regfile$wfi_resume;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule fpr_regfile
wire [63 : 0] fpr_regfile$read_rs1,
fpr_regfile$read_rs2,
fpr_regfile$read_rs3,
fpr_regfile$write_rd_rd_val;
wire [4 : 0] fpr_regfile$read_rs1_port2_rs1,
fpr_regfile$read_rs1_rs1,
fpr_regfile$read_rs2_rs2,
fpr_regfile$read_rs3_rs3,
fpr_regfile$write_rd_rd;
wire fpr_regfile$EN_server_reset_request_put,
fpr_regfile$EN_server_reset_response_get,
fpr_regfile$EN_write_rd,
fpr_regfile$RDY_server_reset_request_put,
fpr_regfile$RDY_server_reset_response_get;
// ports of submodule gpr_regfile
wire [63 : 0] gpr_regfile$read_rs1,
gpr_regfile$read_rs2,
gpr_regfile$write_rd_rd_val;
wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
gpr_regfile$read_rs1_rs1,
gpr_regfile$read_rs2_rs2,
gpr_regfile$write_rd_rd;
wire gpr_regfile$EN_server_reset_request_put,
gpr_regfile$EN_server_reset_response_get,
gpr_regfile$EN_write_rd,
gpr_regfile$RDY_server_reset_request_put,
gpr_regfile$RDY_server_reset_response_get;
// ports of submodule near_mem
reg [63 : 0] near_mem$dmem_req_store_value, near_mem$imem_req_addr;
wire [511 : 0] near_mem$dma_server_rdata, near_mem$dma_server_wdata;
wire [63 : 0] near_mem$dma_server_araddr,
near_mem$dma_server_awaddr,
near_mem$dma_server_wstrb,
near_mem$dmem_req_addr,
near_mem$dmem_req_satp,
near_mem$dmem_word64,
near_mem$imem_master_araddr,
near_mem$imem_master_awaddr,
near_mem$imem_master_rdata,
near_mem$imem_master_wdata,
near_mem$imem_pc,
near_mem$imem_req_satp,
near_mem$mem_master_araddr,
near_mem$mem_master_awaddr,
near_mem$mem_master_rdata,
near_mem$mem_master_wdata,
near_mem$mv_tohost_value,
near_mem$set_watch_tohost_tohost_addr;
wire [31 : 0] near_mem$imem_instr;
wire [15 : 0] near_mem$dma_server_arid,
near_mem$dma_server_awid,
near_mem$dma_server_bid,
near_mem$dma_server_rid;
wire [7 : 0] near_mem$dma_server_arlen,
near_mem$dma_server_awlen,
near_mem$imem_master_arlen,
near_mem$imem_master_awlen,
near_mem$imem_master_wstrb,
near_mem$mem_master_arlen,
near_mem$mem_master_awlen,
near_mem$mem_master_wstrb,
near_mem$mv_status,
near_mem$server_fence_request_put;
wire [6 : 0] near_mem$dmem_req_amo_funct7;
wire [3 : 0] near_mem$dma_server_arcache,
near_mem$dma_server_arqos,
near_mem$dma_server_arregion,
near_mem$dma_server_awcache,
near_mem$dma_server_awqos,
near_mem$dma_server_awregion,
near_mem$dmem_exc_code,
near_mem$imem_exc_code,
near_mem$imem_master_arcache,
near_mem$imem_master_arid,
near_mem$imem_master_arqos,
near_mem$imem_master_arregion,
near_mem$imem_master_awcache,
near_mem$imem_master_awid,
near_mem$imem_master_awqos,
near_mem$imem_master_awregion,
near_mem$imem_master_bid,
near_mem$imem_master_rid,
near_mem$mem_master_arcache,
near_mem$mem_master_arid,
near_mem$mem_master_arqos,
near_mem$mem_master_arregion,
near_mem$mem_master_awcache,
near_mem$mem_master_awid,
near_mem$mem_master_awqos,
near_mem$mem_master_awregion,
near_mem$mem_master_bid,
near_mem$mem_master_rid;
wire [2 : 0] near_mem$dma_server_arprot,
near_mem$dma_server_arsize,
near_mem$dma_server_awprot,
near_mem$dma_server_awsize,
near_mem$dmem_req_f3,
near_mem$imem_master_arprot,
near_mem$imem_master_arsize,
near_mem$imem_master_awprot,
near_mem$imem_master_awsize,
near_mem$imem_req_f3,
near_mem$mem_master_arprot,
near_mem$mem_master_arsize,
near_mem$mem_master_awprot,
near_mem$mem_master_awsize;
wire [1 : 0] near_mem$dma_server_arburst,
near_mem$dma_server_awburst,
near_mem$dma_server_bresp,
near_mem$dma_server_rresp,
near_mem$dmem_req_op,
near_mem$dmem_req_priv,
near_mem$imem_master_arburst,
near_mem$imem_master_awburst,
near_mem$imem_master_bresp,
near_mem$imem_master_rresp,
near_mem$imem_req_priv,
near_mem$mem_master_arburst,
near_mem$mem_master_awburst,
near_mem$mem_master_bresp,
near_mem$mem_master_rresp;
wire near_mem$EN_dmem_req,
near_mem$EN_imem_req,
near_mem$EN_ma_ddr4_ready,
near_mem$EN_server_fence_i_request_put,
near_mem$EN_server_fence_i_response_get,
near_mem$EN_server_fence_request_put,
near_mem$EN_server_fence_response_get,
near_mem$EN_server_reset_request_put,
near_mem$EN_server_reset_response_get,
near_mem$EN_set_watch_tohost,
near_mem$EN_sfence_vma_server_request_put,
near_mem$EN_sfence_vma_server_response_get,
near_mem$RDY_server_fence_i_request_put,
near_mem$RDY_server_fence_i_response_get,
near_mem$RDY_server_fence_request_put,
near_mem$RDY_server_fence_response_get,
near_mem$RDY_server_reset_request_put,
near_mem$RDY_server_reset_response_get,
near_mem$RDY_sfence_vma_server_request_put,
near_mem$RDY_sfence_vma_server_response_get,
near_mem$dma_server_arlock,
near_mem$dma_server_arready,
near_mem$dma_server_arvalid,
near_mem$dma_server_awlock,
near_mem$dma_server_awready,
near_mem$dma_server_awvalid,
near_mem$dma_server_bready,
near_mem$dma_server_bvalid,
near_mem$dma_server_rlast,
near_mem$dma_server_rready,
near_mem$dma_server_rvalid,
near_mem$dma_server_wlast,
near_mem$dma_server_wready,
near_mem$dma_server_wvalid,
near_mem$dmem_exc,
near_mem$dmem_req_mstatus_MXR,
near_mem$dmem_req_sstatus_SUM,
near_mem$dmem_valid,
near_mem$imem_exc,
near_mem$imem_is_i32_not_i16,
near_mem$imem_master_arlock,
near_mem$imem_master_arready,
near_mem$imem_master_arvalid,
near_mem$imem_master_awlock,
near_mem$imem_master_awready,
near_mem$imem_master_awvalid,
near_mem$imem_master_bready,
near_mem$imem_master_bvalid,
near_mem$imem_master_rlast,
near_mem$imem_master_rready,
near_mem$imem_master_rvalid,
near_mem$imem_master_wlast,
near_mem$imem_master_wready,
near_mem$imem_master_wvalid,
near_mem$imem_req_mstatus_MXR,
near_mem$imem_req_sstatus_SUM,
near_mem$imem_valid,
near_mem$mem_master_arlock,
near_mem$mem_master_arready,
near_mem$mem_master_arvalid,
near_mem$mem_master_awlock,
near_mem$mem_master_awready,
near_mem$mem_master_awvalid,
near_mem$mem_master_bready,
near_mem$mem_master_bvalid,
near_mem$mem_master_rlast,
near_mem$mem_master_rready,
near_mem$mem_master_rvalid,
near_mem$mem_master_wlast,
near_mem$mem_master_wready,
near_mem$mem_master_wvalid,
near_mem$set_watch_tohost_watch_tohost;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_pc_reset_value;
// ports of submodule stage1_f_reset_reqs
wire stage1_f_reset_reqs$CLR,
stage1_f_reset_reqs$DEQ,
stage1_f_reset_reqs$EMPTY_N,
stage1_f_reset_reqs$ENQ,
stage1_f_reset_reqs$FULL_N;
// ports of submodule stage1_f_reset_rsps
wire stage1_f_reset_rsps$CLR,
stage1_f_reset_rsps$DEQ,
stage1_f_reset_rsps$EMPTY_N,
stage1_f_reset_rsps$ENQ,
stage1_f_reset_rsps$FULL_N;
// ports of submodule stage2_f_reset_reqs
wire stage2_f_reset_reqs$CLR,
stage2_f_reset_reqs$DEQ,
stage2_f_reset_reqs$EMPTY_N,
stage2_f_reset_reqs$ENQ,
stage2_f_reset_reqs$FULL_N;
// ports of submodule stage2_f_reset_rsps
wire stage2_f_reset_rsps$CLR,
stage2_f_reset_rsps$DEQ,
stage2_f_reset_rsps$EMPTY_N,
stage2_f_reset_rsps$ENQ,
stage2_f_reset_rsps$FULL_N;
// ports of submodule stage2_fbox
wire [63 : 0] stage2_fbox$req_v1,
stage2_fbox$req_v2,
stage2_fbox$req_v3,
stage2_fbox$word_fst;
wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode;
wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd;
wire [2 : 0] stage2_fbox$req_rm;
wire stage2_fbox$EN_req,
stage2_fbox$EN_server_reset_request_put,
stage2_fbox$EN_server_reset_response_get,
stage2_fbox$RDY_server_reset_request_put,
stage2_fbox$RDY_server_reset_response_get,
stage2_fbox$valid;
// ports of submodule stage2_mbox
wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
wire [2 : 0] stage2_mbox$req_f3;
wire stage2_mbox$EN_req,
stage2_mbox$EN_req_reset,
stage2_mbox$EN_rsp_reset,
stage2_mbox$EN_set_verbosity,
stage2_mbox$req_is_OP_not_OP_32,
stage2_mbox$valid;
// ports of submodule stage3_f_reset_reqs
wire stage3_f_reset_reqs$CLR,
stage3_f_reset_reqs$DEQ,
stage3_f_reset_reqs$EMPTY_N,
stage3_f_reset_reqs$ENQ,
stage3_f_reset_reqs$FULL_N;
// ports of submodule stage3_f_reset_rsps
wire stage3_f_reset_rsps$CLR,
stage3_f_reset_rsps$DEQ,
stage3_f_reset_rsps$EMPTY_N,
stage3_f_reset_rsps$ENQ,
stage3_f_reset_rsps$FULL_N;
// ports of submodule stageD_f_reset_reqs
wire stageD_f_reset_reqs$CLR,
stageD_f_reset_reqs$DEQ,
stageD_f_reset_reqs$EMPTY_N,
stageD_f_reset_reqs$ENQ,
stageD_f_reset_reqs$FULL_N;
// ports of submodule stageD_f_reset_rsps
wire stageD_f_reset_rsps$CLR,
stageD_f_reset_rsps$DEQ,
stageD_f_reset_rsps$EMPTY_N,
stageD_f_reset_rsps$ENQ,
stageD_f_reset_rsps$FULL_N;
// ports of submodule stageF_branch_predictor
reg [63 : 0] stageF_branch_predictor$predict_req_pc;
wire [194 : 0] stageF_branch_predictor$bp_train_cf_info;
wire [63 : 0] stageF_branch_predictor$bp_train_pc,
stageF_branch_predictor$predict_rsp;
wire [31 : 0] stageF_branch_predictor$bp_train_instr,
stageF_branch_predictor$predict_rsp_instr;
wire stageF_branch_predictor$EN_bp_train,
stageF_branch_predictor$EN_predict_req,
stageF_branch_predictor$EN_reset,
stageF_branch_predictor$RDY_predict_req,
stageF_branch_predictor$bp_train_is_i32_not_i16,
stageF_branch_predictor$predict_rsp_is_i32_not_i16;
// ports of submodule stageF_f_reset_reqs
wire stageF_f_reset_reqs$CLR,
stageF_f_reset_reqs$DEQ,
stageF_f_reset_reqs$EMPTY_N,
stageF_f_reset_reqs$ENQ,
stageF_f_reset_reqs$FULL_N;
// ports of submodule stageF_f_reset_rsps
wire stageF_f_reset_rsps$CLR,
stageF_f_reset_rsps$DEQ,
stageF_f_reset_rsps$EMPTY_N,
stageF_f_reset_rsps$ENQ,
stageF_f_reset_rsps$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_imem_rl_assert_fail,
CAN_FIRE_RL_imem_rl_fetch_next_32b,
CAN_FIRE_RL_rl_WFI_resume,
CAN_FIRE_RL_rl_finish_FENCE,
CAN_FIRE_RL_rl_finish_FENCE_I,
CAN_FIRE_RL_rl_finish_SFENCE_VMA,
CAN_FIRE_RL_rl_pipe,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_rl_reset_from_WFI,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_RL_rl_show_pipe,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
CAN_FIRE_RL_rl_stage1_CSRR_W,
CAN_FIRE_RL_rl_stage1_CSRR_W_2,
CAN_FIRE_RL_rl_stage1_FENCE,
CAN_FIRE_RL_rl_stage1_FENCE_I,
CAN_FIRE_RL_rl_stage1_SFENCE_VMA,
CAN_FIRE_RL_rl_stage1_WFI,
CAN_FIRE_RL_rl_stage1_interrupt,
CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
CAN_FIRE_RL_rl_stage1_trap,
CAN_FIRE_RL_rl_stage1_xRET,
CAN_FIRE_RL_rl_stage2_nonpipe,
CAN_FIRE_RL_rl_trap,
CAN_FIRE_RL_rl_trap_fetch,
CAN_FIRE_RL_stage1_rl_reset,
CAN_FIRE_RL_stage2_rl_reset_begin,
CAN_FIRE_RL_stage2_rl_reset_end,
CAN_FIRE_RL_stage3_rl_reset,
CAN_FIRE_RL_stageD_rl_reset,
CAN_FIRE_RL_stageF_rl_reset,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_hart0_server_reset_request_put,
CAN_FIRE_hart0_server_reset_response_get,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_nmi_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_RL_imem_rl_assert_fail,
WILL_FIRE_RL_imem_rl_fetch_next_32b,
WILL_FIRE_RL_rl_WFI_resume,
WILL_FIRE_RL_rl_finish_FENCE,
WILL_FIRE_RL_rl_finish_FENCE_I,
WILL_FIRE_RL_rl_finish_SFENCE_VMA,
WILL_FIRE_RL_rl_pipe,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_rl_reset_from_WFI,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_RL_rl_show_pipe,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
WILL_FIRE_RL_rl_stage1_CSRR_W,
WILL_FIRE_RL_rl_stage1_CSRR_W_2,
WILL_FIRE_RL_rl_stage1_FENCE,
WILL_FIRE_RL_rl_stage1_FENCE_I,
WILL_FIRE_RL_rl_stage1_SFENCE_VMA,
WILL_FIRE_RL_rl_stage1_WFI,
WILL_FIRE_RL_rl_stage1_interrupt,
WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
WILL_FIRE_RL_rl_stage1_trap,
WILL_FIRE_RL_rl_stage1_xRET,
WILL_FIRE_RL_rl_stage2_nonpipe,
WILL_FIRE_RL_rl_trap,
WILL_FIRE_RL_rl_trap_fetch,
WILL_FIRE_RL_stage1_rl_reset,
WILL_FIRE_RL_stage2_rl_reset_begin,
WILL_FIRE_RL_stage2_rl_reset_end,
WILL_FIRE_RL_stage3_rl_reset,
WILL_FIRE_RL_stageD_rl_reset,
WILL_FIRE_RL_stageF_rl_reset,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_hart0_server_reset_request_put,
WILL_FIRE_hart0_server_reset_response_get,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_nmi_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
wire [131 : 0] MUX_rg_trap_info$write_1__VAL_1,
MUX_rg_trap_info$write_1__VAL_2,
MUX_rg_trap_info$write_1__VAL_3,
MUX_rg_trap_info$write_1__VAL_4;
wire [63 : 0] MUX_imem_rg_cache_addr$write_1__VAL_1,
MUX_imem_rg_cache_addr$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_1,
MUX_imem_rg_tval$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_3,
MUX_imem_rg_tval$write_1__VAL_4,
MUX_near_mem$imem_req_2__VAL_1,
MUX_near_mem$imem_req_2__VAL_2,
MUX_near_mem$imem_req_2__VAL_4;
wire [31 : 0] MUX_rg_trap_instr$write_1__VAL_1;
wire [3 : 0] MUX_rg_state$write_1__VAL_2,
MUX_rg_state$write_1__VAL_3,
MUX_rg_state$write_1__VAL_4;
wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
MUX_gpr_regfile$write_rd_1__SEL_2,
MUX_imem_rg_cache_addr$write_1__SEL_1,
MUX_imem_rg_cache_addr$write_1__SEL_2,
MUX_rg_next_pc$write_1__SEL_1,
MUX_rg_next_pc$write_1__SEL_2,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_11,
MUX_rg_state$write_1__SEL_12,
MUX_rg_state$write_1__SEL_13,
MUX_rg_state$write_1__SEL_14,
MUX_rg_state$write_1__SEL_15,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_5,
MUX_rg_state$write_1__SEL_7,
MUX_rg_state$write_1__SEL_8,
MUX_rg_state$write_1__SEL_9,
MUX_rg_trap_info$write_1__SEL_1,
MUX_rg_trap_instr$write_1__SEL_1,
MUX_rg_trap_interrupt$write_1__SEL_1,
MUX_stage1_rg_full$write_1__VAL_2,
MUX_stage2_rg_full$write_1__VAL_2,
MUX_stage3_rg_full$write_1__VAL_2,
MUX_stageD_rg_full$write_1__VAL_2,
MUX_stageF_rg_full$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2667;
reg [31 : 0] v__h2661;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520,
_theResult_____1_fst__h12542,
alu_outputs___1_val1__h10598,
rs1_val__h35329,
value__h8670,
value__h8884,
x_out_bypass_rd_val__h9272,
x_out_cf_info_taken_PC__h16275,
x_out_data_to_stage2_addr__h10120,
x_out_data_to_stage2_val1__h10121,
x_out_data_to_stage3_frd_val__h8345,
x_out_data_to_stage3_rd_val__h8341,
x_out_fbypass_rd_val__h9454;
reg [4 : 0] data_to_stage2_rd__h10102,
x_out_bypass_rd__h9271,
x_out_data_to_stage3_fpr_flags__h8344,
x_out_data_to_stage3_rd__h8340,
x_out_fbypass_rd__h9453;
reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q15,
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16,
alu_outputs_exc_code__h11737,
x_out_trap_info_exc_code__h8780;
reg [2 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22;
reg [1 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23;
reg CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324;
wire [429 : 0] IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511;
wire [127 : 0] csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801;
wire [63 : 0] IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1521,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531,
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259,
_theResult_____1_fst__h12535,
_theResult_____1_fst__h12570,
_theResult____h33877,
_theResult___fst__h12706,
_theResult___fst__h12713,
_theResult___fst__h12794,
_theResult___snd_fst_rd_val__h9435,
_theResult___snd_snd__h16701,
_theResult___snd_snd_rd_val__h8290,
addr_of_b32___1__h27521,
addr_of_b32___1__h32461,
addr_of_b32___1__h44012,
addr_of_b32__h27393,
addr_of_b32__h32333,
addr_of_b32__h43884,
alu_outputs___1_addr__h10323,
alu_outputs___1_addr__h10697,
alu_outputs___1_fval1__h11709,
alu_outputs___1_fval2__h10701,
alu_outputs___1_fval3__h11711,
alu_outputs___1_val1__h10496,
alu_outputs___1_val1__h10541,
alu_outputs___1_val1__h10570,
alu_outputs___1_val1__h10983,
alu_outputs___1_val1__h11011,
alu_outputs_cf_info_taken_PC__h16267,
branch_target__h10301,
cpi__h33879,
cpifrac__h33880,
data_to_stage2_addr__h10103,
data_to_stage2_val2__h10105,
delta_CPI_cycles__h33875,
delta_CPI_instrs___1__h33921,
delta_CPI_instrs__h33876,
fall_through_pc__h9846,
next_pc___1__h13967,
next_pc__h10336,
next_pc__h10371,
next_pc__h13964,
next_pc__h9847,
output_stage2___1_data_to_stage3_frd_val__h8219,
rd_val___1__h12450,
rd_val___1__h12531,
rd_val___1__h12538,
rd_val___1__h12545,
rd_val___1__h12552,
rd_val___1__h12559,
rd_val___1__h16730,
rd_val___1__h16761,
rd_val___1__h16793,
rd_val___1__h16822,
rd_val___1__h16874,
rd_val___1__h16922,
rd_val___1__h16928,
rd_val___1__h16973,
rd_val__h10612,
rd_val__h10633,
rd_val__h16602,
rd_val__h16653,
rd_val__h16675,
rd_val__h9684,
rd_val__h9717,
rd_val__h9750,
rd_val__h9781,
rd_val__h9815,
rs1_val__h34495,
rs1_val_bypassed__h5597,
rs2_val_bypassed__h5603,
trap_info_tval__h15117,
val__h9686,
val__h9719,
value__h15187,
x__h33878,
x_out_cf_info_fallthru_PC__h16274,
x_out_data_to_stage2_fval1__h10123,
x_out_data_to_stage2_fval3__h10125,
x_out_data_to_stage2_val2__h10122,
x_out_next_pc__h9864,
y__h35607;
wire [31 : 0] IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2089,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1930,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1931,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1932,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1933,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1934,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1935,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1936,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1938,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1940,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1942,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1944,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1945,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1946,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1948,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1949,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1950,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1952,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1954,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1955,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1957,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1958,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1959,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1960,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1961,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1962,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1963,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1964,
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2090,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18,
_theResult____h5881,
d_instr__h25360,
instr___1__h17725,
instr__h17902,
instr__h18047,
instr__h18239,
instr__h18434,
instr__h18663,
instr__h19116,
instr__h19232,
instr__h19297,
instr__h19614,
instr__h19952,
instr__h20136,
instr__h20265,
instr__h20492,
instr__h20747,
instr__h20919,
instr__h21088,
instr__h21277,
instr__h21466,
instr__h21583,
instr__h21761,
instr__h21880,
instr__h21975,
instr__h22111,
instr__h22247,
instr__h22383,
instr__h22521,
instr__h22659,
instr__h22817,
instr__h22913,
instr__h23066,
instr__h23265,
instr__h23416,
instr__h23621,
instr__h24421,
instr__h24586,
instr__h24785,
instr__h24936,
instr_out___1__h25362,
instr_out___1__h25384,
rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10,
rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9,
rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8,
rs1_val_bypassed597_BITS_31_TO_0__q7,
tmp__h16821,
v32__h10610,
x__h16764,
x__h16796,
x__h16931,
x__h16976,
x_out_data_to_stage1_instr__h17651;
wire [20 : 0] SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737,
decoded_instr_imm21_UJ__h30758,
stage1_rg_stage_input_BITS_30_TO_10__q1;
wire [19 : 0] imm20__h20004;
wire [12 : 0] SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762,
decoded_instr_imm13_SB__h30756,
stage1_rg_stage_input_BITS_63_TO_51__q2;
wire [11 : 0] decoded_instr_imm12_S__h30755,
imm12__h17903,
imm12__h18240,
imm12__h19876,
imm12__h20545,
imm12__h20760,
imm12__h20956,
imm12__h21293,
imm12__h22914,
imm12__h23266,
offset__h18610,
stage1_rg_stage_input_BITS_75_TO_64__q6,
stage1_rg_stage_input_BITS_87_TO_76__q17;
wire [9 : 0] decoded_instr_funct10__h30753,
nzimm10__h20543,
nzimm10__h20758;
wire [8 : 0] offset__h19241, offset__h22828;
wire [7 : 0] offset__h17775, offset__h23200;
wire [6 : 0] offset__h18182;
wire [5 : 0] imm6__h19874, shamt__h10483;
wire [4 : 0] offset_BITS_4_TO_0___h18171,
offset_BITS_4_TO_0___h18602,
offset_BITS_4_TO_0___h23541,
rd__h18242,
rs1__h18241,
x_out_data_to_stage2_rd__h10119;
wire [3 : 0] alu_outputs___1_exc_code__h10979,
cur_verbosity__h3946,
x_exc_code__h44308,
x_out_trap_info_exc_code__h15122;
wire [2 : 0] rm__h10284;
wire [1 : 0] new_epoch__h26813, sxl__h6937, uxl__h6938;
wire IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2313,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2325,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728,
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347,
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405,
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2589,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347,
IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969,
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337,
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339,
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2298,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2315,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2342,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2346,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2407,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2461,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2105,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1104,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1126,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d2758,
NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875,
NOT_rg_run_on_reset_247_248_OR_imem_rg_pc_BITS_ETC___d2255,
NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284,
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746,
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479,
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d760,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1249,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1300,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1660,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1664,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2948,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2950,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974,
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1219,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1335,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402,
NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707,
_0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2484,
csr_regfile_RDY_server_reset_request_put__219__ETC___d2231,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2953,
csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747,
csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753,
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2109,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251,
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064,
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2117,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119,
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067,
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2214,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1124,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1189,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1203,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1635,
rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2937,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2779,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2814,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2908,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2917,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2926,
rg_state_7_EQ_3_326_AND_stage3_rg_full_8_OR_st_ETC___d2338,
rg_state_7_EQ_5_941_AND_NOT_stageF_rg_full_094_ETC___d2942,
rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_094_ETC___d2865,
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1317,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1375,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1401,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d990,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d998,
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2427,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d878,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d886,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d929,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806,
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065,
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d962,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1398,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1588,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334,
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2440,
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938,
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096,
stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2379,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1006,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1009,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1021,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1024,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1039,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1042,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1053,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1056,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1070,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1073,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1085,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1088,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1109,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1110,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1113,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1131,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1132,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1135,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1208,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1209,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1210,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1213,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1214,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1215,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1278,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1368,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2381,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2383,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2385,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2387,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2389,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2395,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296,
stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2337,
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407,
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415,
stageF_f_reset_rsps_i_notEmpty__241_AND_stageD_ETC___d2261,
stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126;
// action method hart0_server_reset_request_put
assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_hart0_server_reset_request_put =
EN_hart0_server_reset_request_put ;
// actionvalue method hart0_server_reset_response_get
assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_server_reset_response_get =
EN_hart0_server_reset_response_get ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = near_mem$imem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = near_mem$imem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = near_mem$imem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = near_mem$imem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = near_mem$imem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = near_mem$imem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = near_mem$imem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = near_mem$imem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = near_mem$imem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = near_mem$imem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = near_mem$imem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = near_mem$imem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = near_mem$imem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = near_mem$imem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = near_mem$imem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = near_mem$imem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = near_mem$imem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = near_mem$imem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = near_mem$imem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = near_mem$imem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = near_mem$imem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = near_mem$imem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = near_mem$imem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = near_mem$imem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = near_mem$imem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = near_mem$imem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = near_mem$imem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = near_mem$imem_master_rready ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = near_mem$mem_master_awvalid ;
// value method mem_master_m_awid
assign mem_master_awid = near_mem$mem_master_awid ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = near_mem$mem_master_awaddr ;
// value method mem_master_m_awlen
assign mem_master_awlen = near_mem$mem_master_awlen ;
// value method mem_master_m_awsize
assign mem_master_awsize = near_mem$mem_master_awsize ;
// value method mem_master_m_awburst
assign mem_master_awburst = near_mem$mem_master_awburst ;
// value method mem_master_m_awlock
assign mem_master_awlock = near_mem$mem_master_awlock ;
// value method mem_master_m_awcache
assign mem_master_awcache = near_mem$mem_master_awcache ;
// value method mem_master_m_awprot
assign mem_master_awprot = near_mem$mem_master_awprot ;
// value method mem_master_m_awqos
assign mem_master_awqos = near_mem$mem_master_awqos ;
// value method mem_master_m_awregion
assign mem_master_awregion = near_mem$mem_master_awregion ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = near_mem$mem_master_wvalid ;
// value method mem_master_m_wdata
assign mem_master_wdata = near_mem$mem_master_wdata ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = near_mem$mem_master_wstrb ;
// value method mem_master_m_wlast
assign mem_master_wlast = near_mem$mem_master_wlast ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = near_mem$mem_master_bready ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = near_mem$mem_master_arvalid ;
// value method mem_master_m_arid
assign mem_master_arid = near_mem$mem_master_arid ;
// value method mem_master_m_araddr
assign mem_master_araddr = near_mem$mem_master_araddr ;
// value method mem_master_m_arlen
assign mem_master_arlen = near_mem$mem_master_arlen ;
// value method mem_master_m_arsize
assign mem_master_arsize = near_mem$mem_master_arsize ;
// value method mem_master_m_arburst
assign mem_master_arburst = near_mem$mem_master_arburst ;
// value method mem_master_m_arlock
assign mem_master_arlock = near_mem$mem_master_arlock ;
// value method mem_master_m_arcache
assign mem_master_arcache = near_mem$mem_master_arcache ;
// value method mem_master_m_arprot
assign mem_master_arprot = near_mem$mem_master_arprot ;
// value method mem_master_m_arqos
assign mem_master_arqos = near_mem$mem_master_arqos ;
// value method mem_master_m_arregion
assign mem_master_arregion = near_mem$mem_master_arregion ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = near_mem$mem_master_rready ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = near_mem$dma_server_awready ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = near_mem$dma_server_wready ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = near_mem$dma_server_bvalid ;
// value method dma_server_m_bid
assign dma_server_bid = near_mem$dma_server_bid ;
// value method dma_server_m_bresp
assign dma_server_bresp = near_mem$dma_server_bresp ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = near_mem$dma_server_arready ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = near_mem$dma_server_rvalid ;
// value method dma_server_m_rid
assign dma_server_rid = near_mem$dma_server_rid ;
// value method dma_server_m_rdata
assign dma_server_rdata = near_mem$dma_server_rdata ;
// value method dma_server_m_rresp
assign dma_server_rresp = near_mem$dma_server_rresp ;
// value method dma_server_m_rlast
assign dma_server_rlast = near_mem$dma_server_rlast ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = near_mem$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = near_mem$mv_status ;
// submodule csr_regfile
mkCSR_RegFile csr_regfile(.CLK(CLK),
.RST_N(RST_N),
.access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
.access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
.access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
.access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
.access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
.access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
.csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
.csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
.csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
.csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
.csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
.csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
.csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
.csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
.csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
.interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
.m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
.ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags),
.ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs),
.mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
.mav_csr_write_word(csr_regfile$mav_csr_write_word),
.mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
.mv_update_fcsr_fflags_flags(csr_regfile$mv_update_fcsr_fflags_flags),
.mv_update_mstatus_fs_fs(csr_regfile$mv_update_mstatus_fs_fs),
.nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
.read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
.read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
.s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
.software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
.EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
.EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
.EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
.EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags),
.EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs),
.EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
.EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
.EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
.EN_debug(csr_regfile$EN_debug),
.RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
.read_csr(csr_regfile$read_csr),
.read_csr_port2(),
.mav_read_csr(),
.mav_csr_write(),
.read_frm(csr_regfile$read_frm),
.read_fflags(),
.mv_update_fcsr_fflags(),
.mv_update_mstatus_fs(),
.read_misa(csr_regfile$read_misa),
.read_mstatus(csr_regfile$read_mstatus),
.read_sstatus(csr_regfile$read_sstatus),
.read_ustatus(),
.read_satp(csr_regfile$read_satp),
.csr_trap_actions(csr_regfile$csr_trap_actions),
.RDY_csr_trap_actions(),
.csr_ret_actions(csr_regfile$csr_ret_actions),
.RDY_csr_ret_actions(),
.read_csr_minstret(csr_regfile$read_csr_minstret),
.read_csr_mcycle(csr_regfile$read_csr_mcycle),
.read_csr_mtime(),
.access_permitted_1(csr_regfile$access_permitted_1),
.access_permitted_2(csr_regfile$access_permitted_2),
.csr_counter_read_fault(),
.csr_mip_read(),
.interrupt_pending(csr_regfile$interrupt_pending),
.wfi_resume(csr_regfile$wfi_resume),
.nmi_pending(csr_regfile$nmi_pending),
.RDY_debug());
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule fpr_regfile
mkFPR_RegFile fpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(fpr_regfile$read_rs1_rs1),
.read_rs2_rs2(fpr_regfile$read_rs2_rs2),
.read_rs3_rs3(fpr_regfile$read_rs3_rs3),
.write_rd_rd(fpr_regfile$write_rd_rd),
.write_rd_rd_val(fpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get),
.EN_write_rd(fpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get),
.read_rs1(fpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(fpr_regfile$read_rs2),
.read_rs3(fpr_regfile$read_rs3));
// submodule gpr_regfile
mkGPR_RegFile gpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(gpr_regfile$read_rs1_rs1),
.read_rs2_rs2(gpr_regfile$read_rs2_rs2),
.write_rd_rd(gpr_regfile$write_rd_rd),
.write_rd_rd_val(gpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
.EN_write_rd(gpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
.read_rs1(gpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(gpr_regfile$read_rs2));
// submodule near_mem
mkNear_Mem near_mem(.CLK(CLK),
.RST_N(RST_N),
.dma_server_araddr(near_mem$dma_server_araddr),
.dma_server_arburst(near_mem$dma_server_arburst),
.dma_server_arcache(near_mem$dma_server_arcache),
.dma_server_arid(near_mem$dma_server_arid),
.dma_server_arlen(near_mem$dma_server_arlen),
.dma_server_arlock(near_mem$dma_server_arlock),
.dma_server_arprot(near_mem$dma_server_arprot),
.dma_server_arqos(near_mem$dma_server_arqos),
.dma_server_arregion(near_mem$dma_server_arregion),
.dma_server_arsize(near_mem$dma_server_arsize),
.dma_server_arvalid(near_mem$dma_server_arvalid),
.dma_server_awaddr(near_mem$dma_server_awaddr),
.dma_server_awburst(near_mem$dma_server_awburst),
.dma_server_awcache(near_mem$dma_server_awcache),
.dma_server_awid(near_mem$dma_server_awid),
.dma_server_awlen(near_mem$dma_server_awlen),
.dma_server_awlock(near_mem$dma_server_awlock),
.dma_server_awprot(near_mem$dma_server_awprot),
.dma_server_awqos(near_mem$dma_server_awqos),
.dma_server_awregion(near_mem$dma_server_awregion),
.dma_server_awsize(near_mem$dma_server_awsize),
.dma_server_awvalid(near_mem$dma_server_awvalid),
.dma_server_bready(near_mem$dma_server_bready),
.dma_server_rready(near_mem$dma_server_rready),
.dma_server_wdata(near_mem$dma_server_wdata),
.dma_server_wlast(near_mem$dma_server_wlast),
.dma_server_wstrb(near_mem$dma_server_wstrb),
.dma_server_wvalid(near_mem$dma_server_wvalid),
.dmem_req_addr(near_mem$dmem_req_addr),
.dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
.dmem_req_f3(near_mem$dmem_req_f3),
.dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
.dmem_req_op(near_mem$dmem_req_op),
.dmem_req_priv(near_mem$dmem_req_priv),
.dmem_req_satp(near_mem$dmem_req_satp),
.dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
.dmem_req_store_value(near_mem$dmem_req_store_value),
.imem_master_arready(near_mem$imem_master_arready),
.imem_master_awready(near_mem$imem_master_awready),
.imem_master_bid(near_mem$imem_master_bid),
.imem_master_bresp(near_mem$imem_master_bresp),
.imem_master_bvalid(near_mem$imem_master_bvalid),
.imem_master_rdata(near_mem$imem_master_rdata),
.imem_master_rid(near_mem$imem_master_rid),
.imem_master_rlast(near_mem$imem_master_rlast),
.imem_master_rresp(near_mem$imem_master_rresp),
.imem_master_rvalid(near_mem$imem_master_rvalid),
.imem_master_wready(near_mem$imem_master_wready),
.imem_req_addr(near_mem$imem_req_addr),
.imem_req_f3(near_mem$imem_req_f3),
.imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
.imem_req_priv(near_mem$imem_req_priv),
.imem_req_satp(near_mem$imem_req_satp),
.imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
.mem_master_arready(near_mem$mem_master_arready),
.mem_master_awready(near_mem$mem_master_awready),
.mem_master_bid(near_mem$mem_master_bid),
.mem_master_bresp(near_mem$mem_master_bresp),
.mem_master_bvalid(near_mem$mem_master_bvalid),
.mem_master_rdata(near_mem$mem_master_rdata),
.mem_master_rid(near_mem$mem_master_rid),
.mem_master_rlast(near_mem$mem_master_rlast),
.mem_master_rresp(near_mem$mem_master_rresp),
.mem_master_rvalid(near_mem$mem_master_rvalid),
.mem_master_wready(near_mem$mem_master_wready),
.server_fence_request_put(near_mem$server_fence_request_put),
.set_watch_tohost_tohost_addr(near_mem$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(near_mem$set_watch_tohost_watch_tohost),
.EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
.EN_imem_req(near_mem$EN_imem_req),
.EN_dmem_req(near_mem$EN_dmem_req),
.EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
.EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
.EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
.EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
.EN_sfence_vma_server_request_put(near_mem$EN_sfence_vma_server_request_put),
.EN_sfence_vma_server_response_get(near_mem$EN_sfence_vma_server_response_get),
.EN_set_watch_tohost(near_mem$EN_set_watch_tohost),
.EN_ma_ddr4_ready(near_mem$EN_ma_ddr4_ready),
.RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
.imem_valid(near_mem$imem_valid),
.imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
.imem_pc(near_mem$imem_pc),
.imem_instr(near_mem$imem_instr),
.imem_exc(near_mem$imem_exc),
.imem_exc_code(near_mem$imem_exc_code),
.imem_tval(),
.imem_master_awvalid(near_mem$imem_master_awvalid),
.imem_master_awid(near_mem$imem_master_awid),
.imem_master_awaddr(near_mem$imem_master_awaddr),
.imem_master_awlen(near_mem$imem_master_awlen),
.imem_master_awsize(near_mem$imem_master_awsize),
.imem_master_awburst(near_mem$imem_master_awburst),
.imem_master_awlock(near_mem$imem_master_awlock),
.imem_master_awcache(near_mem$imem_master_awcache),
.imem_master_awprot(near_mem$imem_master_awprot),
.imem_master_awqos(near_mem$imem_master_awqos),
.imem_master_awregion(near_mem$imem_master_awregion),
.imem_master_wvalid(near_mem$imem_master_wvalid),
.imem_master_wdata(near_mem$imem_master_wdata),
.imem_master_wstrb(near_mem$imem_master_wstrb),
.imem_master_wlast(near_mem$imem_master_wlast),
.imem_master_bready(near_mem$imem_master_bready),
.imem_master_arvalid(near_mem$imem_master_arvalid),
.imem_master_arid(near_mem$imem_master_arid),
.imem_master_araddr(near_mem$imem_master_araddr),
.imem_master_arlen(near_mem$imem_master_arlen),
.imem_master_arsize(near_mem$imem_master_arsize),
.imem_master_arburst(near_mem$imem_master_arburst),
.imem_master_arlock(near_mem$imem_master_arlock),
.imem_master_arcache(near_mem$imem_master_arcache),
.imem_master_arprot(near_mem$imem_master_arprot),
.imem_master_arqos(near_mem$imem_master_arqos),
.imem_master_arregion(near_mem$imem_master_arregion),
.imem_master_rready(near_mem$imem_master_rready),
.dmem_valid(near_mem$dmem_valid),
.dmem_word64(near_mem$dmem_word64),
.dmem_st_amo_val(),
.dmem_exc(near_mem$dmem_exc),
.dmem_exc_code(near_mem$dmem_exc_code),
.mem_master_awvalid(near_mem$mem_master_awvalid),
.mem_master_awid(near_mem$mem_master_awid),
.mem_master_awaddr(near_mem$mem_master_awaddr),
.mem_master_awlen(near_mem$mem_master_awlen),
.mem_master_awsize(near_mem$mem_master_awsize),
.mem_master_awburst(near_mem$mem_master_awburst),
.mem_master_awlock(near_mem$mem_master_awlock),
.mem_master_awcache(near_mem$mem_master_awcache),
.mem_master_awprot(near_mem$mem_master_awprot),
.mem_master_awqos(near_mem$mem_master_awqos),
.mem_master_awregion(near_mem$mem_master_awregion),
.mem_master_wvalid(near_mem$mem_master_wvalid),
.mem_master_wdata(near_mem$mem_master_wdata),
.mem_master_wstrb(near_mem$mem_master_wstrb),
.mem_master_wlast(near_mem$mem_master_wlast),
.mem_master_bready(near_mem$mem_master_bready),
.mem_master_arvalid(near_mem$mem_master_arvalid),
.mem_master_arid(near_mem$mem_master_arid),
.mem_master_araddr(near_mem$mem_master_araddr),
.mem_master_arlen(near_mem$mem_master_arlen),
.mem_master_arsize(near_mem$mem_master_arsize),
.mem_master_arburst(near_mem$mem_master_arburst),
.mem_master_arlock(near_mem$mem_master_arlock),
.mem_master_arcache(near_mem$mem_master_arcache),
.mem_master_arprot(near_mem$mem_master_arprot),
.mem_master_arqos(near_mem$mem_master_arqos),
.mem_master_arregion(near_mem$mem_master_arregion),
.mem_master_rready(near_mem$mem_master_rready),
.RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
.RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
.RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
.RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
.RDY_sfence_vma_server_request_put(near_mem$RDY_sfence_vma_server_request_put),
.RDY_sfence_vma_server_response_get(near_mem$RDY_sfence_vma_server_response_get),
.dma_server_awready(near_mem$dma_server_awready),
.dma_server_wready(near_mem$dma_server_wready),
.dma_server_bvalid(near_mem$dma_server_bvalid),
.dma_server_bid(near_mem$dma_server_bid),
.dma_server_bresp(near_mem$dma_server_bresp),
.dma_server_arready(near_mem$dma_server_arready),
.dma_server_rvalid(near_mem$dma_server_rvalid),
.dma_server_rid(near_mem$dma_server_rid),
.dma_server_rdata(near_mem$dma_server_rdata),
.dma_server_rresp(near_mem$dma_server_rresp),
.dma_server_rlast(near_mem$dma_server_rlast),
.RDY_set_watch_tohost(),
.mv_tohost_value(near_mem$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(near_mem$mv_status));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(soc_map$m_pc_reset_value),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule stage1_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage1_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_reqs$ENQ),
.DEQ(stage1_f_reset_reqs$DEQ),
.CLR(stage1_f_reset_reqs$CLR),
.FULL_N(stage1_f_reset_reqs$FULL_N),
.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));
// submodule stage1_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage1_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_rsps$ENQ),
.DEQ(stage1_f_reset_rsps$DEQ),
.CLR(stage1_f_reset_rsps$CLR),
.FULL_N(stage1_f_reset_rsps$FULL_N),
.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));
// submodule stage2_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage2_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_reqs$ENQ),
.DEQ(stage2_f_reset_reqs$DEQ),
.CLR(stage2_f_reset_reqs$CLR),
.FULL_N(stage2_f_reset_reqs$FULL_N),
.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));
// submodule stage2_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage2_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_rsps$ENQ),
.DEQ(stage2_f_reset_rsps$DEQ),
.CLR(stage2_f_reset_rsps$CLR),
.FULL_N(stage2_f_reset_rsps$FULL_N),
.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));
// submodule stage2_fbox
mkFBox_Top stage2_fbox(.verbosity(4'd0),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(stage2_fbox$req_f7),
.req_opcode(stage2_fbox$req_opcode),
.req_rm(stage2_fbox$req_rm),
.req_rs2(stage2_fbox$req_rs2),
.req_v1(stage2_fbox$req_v1),
.req_v2(stage2_fbox$req_v2),
.req_v3(stage2_fbox$req_v3),
.EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put),
.EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get),
.EN_req(stage2_fbox$EN_req),
.RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put),
.RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get),
.valid(stage2_fbox$valid),
.word_fst(stage2_fbox$word_fst),
.word_snd(stage2_fbox$word_snd));
// submodule stage2_mbox
mkRISCV_MBox stage2_mbox(.CLK(CLK),
.RST_N(RST_N),
.req_f3(stage2_mbox$req_f3),
.req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
.req_v1(stage2_mbox$req_v1),
.req_v2(stage2_mbox$req_v2),
.set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
.EN_set_verbosity(stage2_mbox$EN_set_verbosity),
.EN_req_reset(stage2_mbox$EN_req_reset),
.EN_rsp_reset(stage2_mbox$EN_rsp_reset),
.EN_req(stage2_mbox$EN_req),
.RDY_set_verbosity(),
.RDY_req_reset(),
.RDY_rsp_reset(),
.valid(stage2_mbox$valid),
.word(stage2_mbox$word));
// submodule stage3_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage3_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_reqs$ENQ),
.DEQ(stage3_f_reset_reqs$DEQ),
.CLR(stage3_f_reset_reqs$CLR),
.FULL_N(stage3_f_reset_reqs$FULL_N),
.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));
// submodule stage3_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage3_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_rsps$ENQ),
.DEQ(stage3_f_reset_rsps$DEQ),
.CLR(stage3_f_reset_rsps$CLR),
.FULL_N(stage3_f_reset_rsps$FULL_N),
.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));
// submodule stageD_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stageD_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_reqs$ENQ),
.DEQ(stageD_f_reset_reqs$DEQ),
.CLR(stageD_f_reset_reqs$CLR),
.FULL_N(stageD_f_reset_reqs$FULL_N),
.EMPTY_N(stageD_f_reset_reqs$EMPTY_N));
// submodule stageD_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stageD_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_rsps$ENQ),
.DEQ(stageD_f_reset_rsps$DEQ),
.CLR(stageD_f_reset_rsps$CLR),
.FULL_N(stageD_f_reset_rsps$FULL_N),
.EMPTY_N(stageD_f_reset_rsps$EMPTY_N));
// submodule stageF_branch_predictor
mkBranch_Predictor stageF_branch_predictor(.CLK(CLK),
.RST_N(RST_N),
.bp_train_cf_info(stageF_branch_predictor$bp_train_cf_info),
.bp_train_instr(stageF_branch_predictor$bp_train_instr),
.bp_train_is_i32_not_i16(stageF_branch_predictor$bp_train_is_i32_not_i16),
.bp_train_pc(stageF_branch_predictor$bp_train_pc),
.predict_req_pc(stageF_branch_predictor$predict_req_pc),
.predict_rsp_instr(stageF_branch_predictor$predict_rsp_instr),
.predict_rsp_is_i32_not_i16(stageF_branch_predictor$predict_rsp_is_i32_not_i16),
.EN_reset(stageF_branch_predictor$EN_reset),
.EN_predict_req(stageF_branch_predictor$EN_predict_req),
.EN_bp_train(stageF_branch_predictor$EN_bp_train),
.RDY_reset(),
.RDY_predict_req(stageF_branch_predictor$RDY_predict_req),
.predict_rsp(stageF_branch_predictor$predict_rsp),
.RDY_bp_train());
// submodule stageF_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stageF_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_reqs$ENQ),
.DEQ(stageF_f_reset_reqs$DEQ),
.CLR(stageF_f_reset_reqs$CLR),
.FULL_N(stageF_f_reset_reqs$FULL_N),
.EMPTY_N(stageF_f_reset_reqs$EMPTY_N));
// submodule stageF_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stageF_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_rsps$ENQ),
.DEQ(stageF_f_reset_rsps$DEQ),
.CLR(stageF_f_reset_rsps$CLR),
.FULL_N(stageF_f_reset_rsps$FULL_N),
.EMPTY_N(stageF_f_reset_rsps$EMPTY_N));
// rule RL_rl_show_pipe
assign CAN_FIRE_RL_rl_show_pipe =
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
rg_state != 4'd0 &&
rg_state != 4'd1 &&
rg_state != 4'd12 ;
assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;
// rule RL_rl_stage2_nonpipe
assign CAN_FIRE_RL_rl_stage2_nonpipe =
rg_state == 4'd3 && !stage3_rg_full && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156 ;
assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;
// rule RL_rl_stage1_trap
assign CAN_FIRE_RL_rl_stage1_trap =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2779 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;
// rule RL_rl_trap
assign CAN_FIRE_RL_rl_trap =
rg_state == 4'd4 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;
// rule RL_rl_stage1_CSRR_W
assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
// rule RL_rl_stage1_CSRR_W_2
assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
// rule RL_rl_stage1_CSRR_S_or_C
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;
// rule RL_rl_stage1_CSRR_S_or_C_2
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
// rule RL_rl_stage1_restart_after_csrrx
assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_094_ETC___d2865 ;
assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;
// rule RL_rl_stage1_xRET
assign CAN_FIRE_RL_rl_stage1_xRET =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753 &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 &&
IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;
// rule RL_rl_stage1_FENCE_I
assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;
assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;
// rule RL_rl_finish_FENCE_I
assign CAN_FIRE_RL_rl_finish_FENCE_I =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_i_response_get &&
rg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;
// rule RL_rl_stage1_FENCE
assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;
assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;
// rule RL_rl_finish_FENCE
assign CAN_FIRE_RL_rl_finish_FENCE =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_response_get &&
rg_state == 4'd10 ;
assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;
// rule RL_rl_stage1_SFENCE_VMA
assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_14 ;
assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_14 ;
// rule RL_rl_finish_SFENCE_VMA
assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_sfence_vma_server_response_get &&
rg_state == 4'd11 ;
assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
// rule RL_rl_stage1_WFI
assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_15 ;
assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_15 ;
// rule RL_rl_WFI_resume
assign CAN_FIRE_RL_rl_WFI_resume =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2937 ;
assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;
// rule RL_rl_reset_from_WFI
assign CAN_FIRE_RL_rl_reset_from_WFI =
rg_state == 4'd12 && f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_5 ;
// rule RL_rl_trap_fetch
assign CAN_FIRE_RL_rl_trap_fetch =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_5_941_AND_NOT_stageF_rg_full_094_ETC___d2942 ;
assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;
// rule RL_rl_stage1_interrupt
assign CAN_FIRE_RL_rl_stage1_interrupt =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2953 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;
// rule RL_imem_rl_assert_fail
assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete =
gpr_regfile$RDY_server_reset_response_get &&
fpr_regfile$RDY_server_reset_response_get &&
near_mem$RDY_server_reset_response_get &&
csr_regfile$RDY_server_reset_response_get &&
stageF_f_reset_rsps_i_notEmpty__241_AND_stageD_ETC___d2261 &&
rg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_pipe
assign CAN_FIRE_RL_rl_pipe =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2325 &&
rg_state_7_EQ_3_326_AND_stage3_rg_full_8_OR_st_ETC___d2338 &&
(NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2346 ||
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347 ||
stage2_rg_full ||
stage3_rg_full) ;
assign WILL_FIRE_RL_rl_pipe =
CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start =
gpr_regfile$RDY_server_reset_request_put &&
fpr_regfile$RDY_server_reset_request_put &&
near_mem$RDY_server_reset_request_put &&
csr_regfile_RDY_server_reset_request_put__219__ETC___d2231 &&
rg_state == 4'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_imem_rl_fetch_next_32b
assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
imem_rg_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
CAN_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_stage3_rl_reset
assign CAN_FIRE_RL_stage3_rl_reset =
stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;
// rule RL_stage2_rl_reset_end
assign CAN_FIRE_RL_stage2_rl_reset_end =
stage2_fbox$RDY_server_reset_response_get &&
stage2_f_reset_rsps$FULL_N &&
stage2_rg_resetting ;
assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;
// rule RL_stage2_rl_reset_begin
assign CAN_FIRE_RL_stage2_rl_reset_begin =
stage2_fbox$RDY_server_reset_request_put &&
stage2_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_stage2_rl_reset_begin =
CAN_FIRE_RL_stage2_rl_reset_begin ;
// rule RL_stage1_rl_reset
assign CAN_FIRE_RL_stage1_rl_reset =
stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;
// rule RL_stageD_rl_reset
assign CAN_FIRE_RL_stageD_rl_reset =
stageD_f_reset_reqs$EMPTY_N && stageD_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageD_rl_reset = CAN_FIRE_RL_stageD_rl_reset ;
// rule RL_stageF_rl_reset
assign CAN_FIRE_RL_stageF_rl_reset =
stageF_f_reset_reqs$EMPTY_N && stageF_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageF_rl_reset = CAN_FIRE_RL_stageF_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ;
assign MUX_gpr_regfile$write_rd_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ;
assign MUX_imem_rg_cache_addr$write_1__SEL_1 =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
assign MUX_imem_rg_cache_addr$write_1__SEL_2 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ;
assign MUX_rg_next_pc$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 ;
assign MUX_rg_next_pc$write_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
assign MUX_rg_state$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 ;
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset_complete &&
!WILL_FIRE_RL_imem_rl_fetch_next_32b ;
assign MUX_rg_state$write_1__SEL_5 =
CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
assign MUX_rg_state$write_1__SEL_7 =
WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign MUX_rg_state$write_1__SEL_8 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
assign MUX_rg_state$write_1__SEL_9 =
WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
assign MUX_rg_state$write_1__SEL_10 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004 ;
assign MUX_rg_state$write_1__SEL_11 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019 ;
assign MUX_rg_state$write_1__SEL_12 =
near_mem$RDY_server_fence_i_request_put &&
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2908 ;
assign MUX_rg_state$write_1__SEL_13 =
near_mem$RDY_server_fence_request_put &&
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2917 ;
assign MUX_rg_state$write_1__SEL_14 =
near_mem$RDY_sfence_vma_server_request_put &&
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2926 ;
assign MUX_rg_state$write_1__SEL_15 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign MUX_rg_trap_info$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ;
assign MUX_rg_trap_instr$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ;
assign MUX_rg_trap_interrupt$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
always@(rg_trap_instr or
csr_regfile$read_csr or
y__h35607 or
IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b110:
MUX_csr_regfile$mav_csr_write_2__VAL_2 =
IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856;
default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
csr_regfile$read_csr[63:0] & y__h35607;
endcase
end
assign MUX_imem_rg_cache_addr$write_1__VAL_1 =
(near_mem$imem_valid && !near_mem$imem_exc) ?
near_mem$imem_pc :
64'h0000000000000001 ;
assign MUX_imem_rg_cache_addr$write_1__VAL_2 =
near_mem$imem_exc ? 64'h0000000000000001 : near_mem$imem_pc ;
assign MUX_imem_rg_tval$write_1__VAL_1 =
(NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h27521 :
soc_map$m_pc_reset_value ;
assign MUX_imem_rg_tval$write_1__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h32461 :
stageF_branch_predictor$predict_rsp ;
assign MUX_imem_rg_tval$write_1__VAL_3 =
(NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h44012 :
rg_next_pc ;
assign MUX_imem_rg_tval$write_1__VAL_4 = near_mem$imem_pc + 64'd4 ;
assign MUX_near_mem$imem_req_2__VAL_1 =
(NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h27521 :
addr_of_b32__h27393 ;
assign MUX_near_mem$imem_req_2__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h32461 :
addr_of_b32__h32333 ;
assign MUX_near_mem$imem_req_2__VAL_4 =
(NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h44012 :
addr_of_b32__h43884 ;
assign MUX_rg_state$write_1__VAL_2 = rg_run_on_reset ? 4'd3 : 4'd2 ;
assign MUX_rg_state$write_1__VAL_3 =
csr_regfile$access_permitted_1 ? 4'd8 : 4'd4 ;
assign MUX_rg_state$write_1__VAL_4 =
csr_regfile$access_permitted_2 ? 4'd8 : 4'd4 ;
assign MUX_rg_trap_info$write_1__VAL_1 =
{ stage1_rg_stage_input[401:338],
4'd2,
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[327:264] :
trap_info_tval__h15117 } ;
assign MUX_rg_trap_info$write_1__VAL_2 =
{ value__h8670,
near_mem$dmem_exc_code,
stage2_rg_stage2[389:326] } ;
assign MUX_rg_trap_info$write_1__VAL_3 =
{ stage1_rg_stage_input[401:338],
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:264] :
{ alu_outputs_exc_code__h11737, trap_info_tval__h15117 } } ;
assign MUX_rg_trap_info$write_1__VAL_4 =
{ stage1_rg_stage_input[401:338], x_exc_code__h44308, 64'd0 } ;
assign MUX_rg_trap_instr$write_1__VAL_1 = stage1_rg_stage_input[263:232] ;
assign MUX_stage1_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728 ;
assign MUX_stage2_rg_full$write_1__VAL_2 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full) :
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ;
assign MUX_stage3_rg_full$write_1__VAL_2 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) ;
assign MUX_stageD_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full ;
assign MUX_stageF_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ?
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full :
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112) &&
stageF_rg_full ;
// register cfg_logdelay
assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
assign cfg_logdelay$EN = EN_set_verbosity ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register imem_rg_cache_addr
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_cache_addr$write_1__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
near_mem$imem_pc or MUX_rg_state$write_1__SEL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_cache_addr$D_IN = near_mem$imem_pc;
MUX_rg_state$write_1__SEL_7:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
default: imem_rg_cache_addr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_cache_addr$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_cache_b16
assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
assign imem_rg_cache_b16$EN =
MUX_rg_state$write_1__SEL_7 && near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
!near_mem$imem_exc ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register imem_rg_f3
assign imem_rg_f3$D_IN = 3'b010 ;
assign imem_rg_f3$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_mstatus_MXR
assign imem_rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign imem_rg_mstatus_MXR$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_pc
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_pc$D_IN = soc_map$m_pc_reset_value;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_pc$D_IN = stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7: imem_rg_pc$D_IN = rg_next_pc;
default: imem_rg_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_pc$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_priv
assign imem_rg_priv$D_IN = rg_cur_priv ;
assign imem_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_satp
assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
assign imem_rg_satp$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_sstatus_SUM
assign imem_rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
assign imem_rg_sstatus_SUM$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_tval
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_tval$write_1__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_tval$write_1__VAL_2 or
MUX_rg_state$write_1__SEL_7 or
MUX_imem_rg_tval$write_1__VAL_3 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_2;
MUX_rg_state$write_1__SEL_7:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_3;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_4;
default: imem_rg_tval$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_tval$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register rg_csr_pc
assign rg_csr_pc$D_IN = stage1_rg_stage_input[401:338] ;
assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_csr_val1
assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h10121 ;
assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_cur_priv
always@(WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or
csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_trap:
rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
WILL_FIRE_RL_rl_stage1_xRET:
rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64];
WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_cur_priv$EN =
WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_epoch
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h26813 or
MUX_rg_state$write_1__SEL_7 or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
rg_epoch$D_IN = new_epoch__h26813;
MUX_rg_state$write_1__SEL_7: rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_reset_start: rg_epoch$D_IN = 2'd0;
default: rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mstatus_MXR
assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_next_pc
always@(MUX_rg_next_pc$write_1__SEL_1 or
x_out_next_pc__h9864 or
MUX_rg_next_pc$write_1__SEL_2 or
WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h9864;
MUX_rg_next_pc$write_1__SEL_2: rg_next_pc$D_IN = x_out_next_pc__h9864;
WILL_FIRE_RL_rl_trap:
rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130];
WILL_FIRE_RL_rl_stage1_xRET:
rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66];
default: rg_next_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_next_pc$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_xRET ;
// register rg_run_on_reset
assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;
// register rg_sstatus_SUM
assign rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_start_CPI_cycles
assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
assign rg_start_CPI_cycles$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_start_CPI_instrs
assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
assign rg_start_CPI_instrs$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_state
always@(WILL_FIRE_RL_rl_reset_complete or
MUX_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
MUX_rg_state$write_1__VAL_4 or
WILL_FIRE_RL_rl_reset_from_WFI or
WILL_FIRE_RL_rl_reset_start or
MUX_rg_state$write_1__SEL_7 or
MUX_rg_state$write_1__SEL_8 or
MUX_rg_state$write_1__SEL_1 or
MUX_rg_state$write_1__SEL_9 or
WILL_FIRE_RL_rl_stage1_CSRR_W or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
WILL_FIRE_RL_rl_stage1_FENCE_I or
WILL_FIRE_RL_rl_stage1_FENCE or
WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_reset_complete:
rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_CSRR_W_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd3;
MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4;
MUX_rg_state$write_1__SEL_1 || MUX_rg_state$write_1__SEL_9:
rg_state$D_IN = 4'd5;
WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd6;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd7;
WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9;
WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10;
WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd11;
WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12;
default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 ||
WILL_FIRE_RL_rl_reset_complete ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
WILL_FIRE_RL_rl_reset_from_WFI ||
WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_stage1_WFI ;
// register rg_trap_info
always@(MUX_rg_trap_info$write_1__SEL_1 or
MUX_rg_trap_info$write_1__VAL_1 or
WILL_FIRE_RL_rl_stage2_nonpipe or
MUX_rg_trap_info$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_trap or
MUX_rg_trap_info$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_trap_info$write_1__SEL_1:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
WILL_FIRE_RL_rl_stage2_nonpipe:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_trap:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_interrupt:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
default: rg_trap_info$D_IN =
132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_trap_info$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register rg_trap_instr
assign rg_trap_instr$D_IN =
MUX_rg_trap_instr$write_1__SEL_1 ?
stage1_rg_stage_input[263:232] :
stage2_rg_stage2[429:398] ;
assign rg_trap_instr$EN =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
// register rg_trap_interrupt
assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
assign rg_trap_interrupt$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register stage1_rg_full
always@(WILL_FIRE_RL_stage1_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage1_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stage1_rg_full$D_IN = 1'd0;
default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage1_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage1_rl_reset ;
// register stage1_rg_stage_input
assign stage1_rg_stage_input$D_IN =
{ stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168],
stageD_rg_data[165:96],
_theResult____h5881,
stageD_rg_data[79:0],
_theResult____h5881[6:0],
_theResult____h5881[11:7],
_theResult____h5881[19:15],
_theResult____h5881[24:20],
_theResult____h5881[31:27],
_theResult____h5881[31:20],
_theResult____h5881[14:12],
_theResult____h5881[31:27],
_theResult____h5881[31:25],
decoded_instr_funct10__h30753,
_theResult____h5881[31:20],
decoded_instr_imm12_S__h30755,
decoded_instr_imm13_SB__h30756,
_theResult____h5881[31:12],
decoded_instr_imm21_UJ__h30758,
_theResult____h5881[27:20],
_theResult____h5881[26:25] } ;
assign stage1_rg_stage_input$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full ;
// register stage2_rg_full
always@(WILL_FIRE_RL_stage2_rl_reset_begin or
WILL_FIRE_RL_rl_pipe or
MUX_stage2_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap:
stage2_rg_full$D_IN = 1'd0;
default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage2_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage2_rl_reset_begin ;
// register stage2_rg_resetting
assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_rg_resetting$EN =
WILL_FIRE_RL_stage2_rl_reset_end ||
WILL_FIRE_RL_stage2_rl_reset_begin ;
// register stage2_rg_stage2
assign stage2_rg_stage2$D_IN =
{ rg_cur_priv,
stage1_rg_stage_input[401:338],
IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511 } ;
assign stage2_rg_stage2$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2407 ;
// register stage3_rg_full
always@(WILL_FIRE_RL_stage3_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage3_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1)
case (1'b1)
WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage3_rg_full$D_IN = MUX_stage3_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage3_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stage3_rl_reset ;
// register stage3_rg_stage3
assign stage3_rg_stage3$D_IN =
{ stage2_rg_stage2[493:398],
stage2_rg_stage2[495:494],
1'd1,
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_rd_val__h8341,
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3,
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4,
x_out_data_to_stage3_fpr_flags__h8344,
x_out_data_to_stage3_frd_val__h8345 } ;
assign stage3_rg_stage3$EN =
WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) ;
// register stageD_rg_data
assign stageD_rg_data$D_IN =
{ imem_rg_pc,
stageF_rg_epoch,
stageF_rg_priv,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11,
near_mem$imem_exc,
near_mem$imem_exc_code,
imem_rg_tval,
d_instr__h25360,
stageF_branch_predictor$predict_rsp } ;
assign stageD_rg_data$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ;
// register stageD_rg_full
always@(WILL_FIRE_RL_stageD_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageD_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stageD_rl_reset: stageD_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageD_rg_full$D_IN = MUX_stageD_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stageD_rg_full$D_IN = 1'd0;
default: stageD_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageD_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stageD_rl_reset ;
// register stageF_rg_epoch
always@(WILL_FIRE_RL_stageF_rl_reset or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_rg_epoch or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h26813 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_epoch$D_IN = 2'd0;
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_rg_epoch$D_IN = stageF_rg_epoch;
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_trap_fetch: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_WFI_resume: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_finish_SFENCE_VMA:
stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_finish_FENCE: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_finish_FENCE_I: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_epoch$D_IN = new_epoch__h26813;
default: stageF_rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stageF_rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_stageF_rl_reset ;
// register stageF_rg_full
always@(WILL_FIRE_RL_stageF_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageF_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageF_rg_full$D_IN = MUX_stageF_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_full$D_IN = 1'd1;
default: stageF_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageF_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stageF_rl_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register stageF_rg_priv
assign stageF_rg_priv$D_IN = rg_cur_priv ;
assign stageF_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// submodule csr_regfile
assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_2_read_not_write =
rs1_val__h35329 == 64'd0 ;
assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
assign csr_regfile$csr_ret_actions_from_priv =
(stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884) ?
2'b11 :
((stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892) ?
2'b01 :
2'b0) ;
assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[67:64] ;
assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
assign csr_regfile$csr_trap_actions_interrupt =
rg_trap_interrupt && !csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_nmi =
rg_trap_interrupt && csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_pc = rg_trap_info[131:68] ;
assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[63:0] ;
assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
assign csr_regfile$m_external_interrupt_req_set_not_clear =
m_external_interrupt_req_set_not_clear ;
assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[68:64] ;
assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ;
assign csr_regfile$mav_csr_write_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$mav_csr_write_word =
MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
rs1_val__h34495 :
MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
assign csr_regfile$mv_update_fcsr_fflags_flags = 5'h0 ;
assign csr_regfile$mv_update_mstatus_fs_fs = 2'h0 ;
assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
assign csr_regfile$s_external_interrupt_req_set_not_clear =
s_external_interrupt_req_set_not_clear ;
assign csr_regfile$software_interrupt_req_set_not_clear =
software_interrupt_req_set_not_clear ;
assign csr_regfile$timer_interrupt_req_set_not_clear =
timer_interrupt_req_set_not_clear ;
assign csr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign csr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign csr_regfile$EN_mav_read_csr = 1'b0 ;
assign csr_regfile$EN_mav_csr_write =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
rg_trap_instr[19:15] != 5'd0 ;
assign csr_regfile$EN_ma_update_fcsr_fflags =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[70] ;
assign csr_regfile$EN_ma_update_mstatus_fs =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
(stage3_rg_stage3[70] || stage3_rg_stage3[69]) ;
assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_csr_minstret_incr =
WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_debug = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset_start ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = rg_run_on_reset ;
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule fpr_regfile
assign fpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign fpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign fpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign fpr_regfile$read_rs3_rs3 = stage1_rg_stage_input[129:125] ;
assign fpr_regfile$write_rd_rd = stage3_rg_stage3[139:135] ;
assign fpr_regfile$write_rd_rd_val = stage3_rg_stage3[63:0] ;
assign fpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign fpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign fpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[69] ;
// submodule gpr_regfile
assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign gpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign gpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign gpr_regfile$write_rd_rd =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_2) ?
rg_trap_instr[11:7] :
stage3_rg_stage3[139:135] ;
assign gpr_regfile$write_rd_rd_val =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_2) ?
csr_regfile$read_csr[63:0] :
stage3_rg_stage3[134:71] ;
assign gpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign gpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign gpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
!stage3_rg_stage3[69] ;
// submodule near_mem
assign near_mem$dma_server_araddr = dma_server_araddr ;
assign near_mem$dma_server_arburst = dma_server_arburst ;
assign near_mem$dma_server_arcache = dma_server_arcache ;
assign near_mem$dma_server_arid = dma_server_arid ;
assign near_mem$dma_server_arlen = dma_server_arlen ;
assign near_mem$dma_server_arlock = dma_server_arlock ;
assign near_mem$dma_server_arprot = dma_server_arprot ;
assign near_mem$dma_server_arqos = dma_server_arqos ;
assign near_mem$dma_server_arregion = dma_server_arregion ;
assign near_mem$dma_server_arsize = dma_server_arsize ;
assign near_mem$dma_server_arvalid = dma_server_arvalid ;
assign near_mem$dma_server_awaddr = dma_server_awaddr ;
assign near_mem$dma_server_awburst = dma_server_awburst ;
assign near_mem$dma_server_awcache = dma_server_awcache ;
assign near_mem$dma_server_awid = dma_server_awid ;
assign near_mem$dma_server_awlen = dma_server_awlen ;
assign near_mem$dma_server_awlock = dma_server_awlock ;
assign near_mem$dma_server_awprot = dma_server_awprot ;
assign near_mem$dma_server_awqos = dma_server_awqos ;
assign near_mem$dma_server_awregion = dma_server_awregion ;
assign near_mem$dma_server_awsize = dma_server_awsize ;
assign near_mem$dma_server_awvalid = dma_server_awvalid ;
assign near_mem$dma_server_bready = dma_server_bready ;
assign near_mem$dma_server_rready = dma_server_rready ;
assign near_mem$dma_server_wdata = dma_server_wdata ;
assign near_mem$dma_server_wlast = dma_server_wlast ;
assign near_mem$dma_server_wstrb = dma_server_wstrb ;
assign near_mem$dma_server_wvalid = dma_server_wvalid ;
assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h10120 ;
assign near_mem$dmem_req_amo_funct7 =
x_out_data_to_stage2_val1__h10121[6:0] ;
assign near_mem$dmem_req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
assign near_mem$dmem_req_op =
(stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111)) ?
2'd0 :
((stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111)) ?
2'd1 :
2'd2) ;
assign near_mem$dmem_req_priv =
csr_regfile$read_mstatus[17] ?
csr_regfile$read_mstatus[12:11] :
rg_cur_priv ;
assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ;
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 or
alu_outputs___1_fval2__h10701 or branch_target__h10301)
begin
case (stage1_rg_stage_input[151:145])
7'b0100111:
near_mem$dmem_req_store_value = alu_outputs___1_fval2__h10701;
7'b1100011: near_mem$dmem_req_store_value = branch_target__h10301;
default: near_mem$dmem_req_store_value =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531;
endcase
end
assign near_mem$imem_master_arready = imem_master_arready ;
assign near_mem$imem_master_awready = imem_master_awready ;
assign near_mem$imem_master_bid = imem_master_bid ;
assign near_mem$imem_master_bresp = imem_master_bresp ;
assign near_mem$imem_master_bvalid = imem_master_bvalid ;
assign near_mem$imem_master_rdata = imem_master_rdata ;
assign near_mem$imem_master_rid = imem_master_rid ;
assign near_mem$imem_master_rlast = imem_master_rlast ;
assign near_mem$imem_master_rresp = imem_master_rresp ;
assign near_mem$imem_master_rvalid = imem_master_rvalid ;
assign near_mem$imem_master_wready = imem_master_wready ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_near_mem$imem_req_2__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_near_mem$imem_req_2__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4 or
MUX_rg_state$write_1__SEL_7 or MUX_near_mem$imem_req_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_4;
MUX_rg_state$write_1__SEL_7:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_4;
default: near_mem$imem_req_addr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign near_mem$imem_req_f3 =
WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
assign near_mem$imem_req_mstatus_MXR =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
csr_regfile$read_mstatus[19] :
imem_rg_mstatus_MXR ;
assign near_mem$imem_req_priv =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
rg_cur_priv :
imem_rg_priv ;
assign near_mem$imem_req_satp =
WILL_FIRE_RL_imem_rl_fetch_next_32b ?
imem_rg_satp :
csr_regfile$read_satp ;
assign near_mem$imem_req_sstatus_SUM =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
csr_regfile$read_sstatus[18] :
imem_rg_sstatus_SUM ;
assign near_mem$mem_master_arready = mem_master_arready ;
assign near_mem$mem_master_awready = mem_master_awready ;
assign near_mem$mem_master_bid = mem_master_bid ;
assign near_mem$mem_master_bresp = mem_master_bresp ;
assign near_mem$mem_master_bvalid = mem_master_bvalid ;
assign near_mem$mem_master_rdata = mem_master_rdata ;
assign near_mem$mem_master_rid = mem_master_rid ;
assign near_mem$mem_master_rlast = mem_master_rlast ;
assign near_mem$mem_master_rresp = mem_master_rresp ;
assign near_mem$mem_master_rvalid = mem_master_rvalid ;
assign near_mem$mem_master_wready = mem_master_wready ;
assign near_mem$server_fence_request_put =
8'b10101010 /* unspecified value */ ;
assign near_mem$set_watch_tohost_tohost_addr =
set_watch_tohost_tohost_addr ;
assign near_mem$set_watch_tohost_watch_tohost =
set_watch_tohost_watch_tohost ;
assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
assign near_mem$EN_imem_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign near_mem$EN_dmem_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541 ;
assign near_mem$EN_server_fence_i_request_put =
MUX_rg_state$write_1__SEL_12 ;
assign near_mem$EN_server_fence_i_response_get =
CAN_FIRE_RL_rl_finish_FENCE_I ;
assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_13 ;
assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
assign near_mem$EN_sfence_vma_server_request_put =
MUX_rg_state$write_1__SEL_14 ;
assign near_mem$EN_sfence_vma_server_response_get =
CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
assign near_mem$EN_set_watch_tohost = EN_set_watch_tohost ;
assign near_mem$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule stage1_f_reset_reqs
assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_reqs$CLR = 1'b0 ;
// submodule stage1_f_reset_rsps
assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage1_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_f_reset_reqs
assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_f_reset_reqs$CLR = 1'b0 ;
// submodule stage2_f_reset_rsps
assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage2_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_fbox
assign stage2_fbox$req_f7 = MUX_rg_trap_instr$write_1__VAL_1[31:25] ;
assign stage2_fbox$req_opcode = MUX_rg_trap_instr$write_1__VAL_1[6:0] ;
assign stage2_fbox$req_rm = rm__h10284 ;
assign stage2_fbox$req_rs2 = MUX_rg_trap_instr$write_1__VAL_1[24:20] ;
assign stage2_fbox$req_v1 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505 ?
x_out_data_to_stage2_val1__h10121 :
x_out_data_to_stage2_fval1__h10123 ;
assign stage2_fbox$req_v2 = alu_outputs___1_fval2__h10701 ;
assign stage2_fbox$req_v3 = x_out_data_to_stage2_fval3__h10125 ;
assign stage2_fbox$EN_server_reset_request_put =
CAN_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_fbox$EN_server_reset_response_get =
CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_fbox$EN_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591 ;
// submodule stage2_mbox
assign stage2_mbox$req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign stage2_mbox$req_is_OP_not_OP_32 =
!MUX_rg_trap_instr$write_1__VAL_1[3] ;
assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h10121 ;
assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h10122 ;
assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
assign stage2_mbox$EN_set_verbosity = 1'b0 ;
assign stage2_mbox$EN_req_reset = 1'b0 ;
assign stage2_mbox$EN_rsp_reset = 1'b0 ;
assign stage2_mbox$EN_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575 ;
// submodule stage3_f_reset_reqs
assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_reqs$CLR = 1'b0 ;
// submodule stage3_f_reset_rsps
assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage3_f_reset_rsps$CLR = 1'b0 ;
// submodule stageD_f_reset_reqs
assign stageD_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageD_f_reset_reqs$DEQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_reqs$CLR = 1'b0 ;
// submodule stageD_f_reset_rsps
assign stageD_f_reset_rsps$ENQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageD_f_reset_rsps$CLR = 1'b0 ;
// submodule stageF_branch_predictor
assign stageF_branch_predictor$bp_train_cf_info =
(stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) ?
{ CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432,
x_out_cf_info_fallthru_PC__h16274,
alu_outputs_cf_info_taken_PC__h16267 } :
195'h6AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign stageF_branch_predictor$bp_train_instr = d_instr__h25360 ;
assign stageF_branch_predictor$bp_train_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$bp_train_pc = imem_rg_pc ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_branch_predictor$predict_req_pc = soc_map$m_pc_reset_value;
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_branch_predictor$predict_req_pc =
stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7:
stageF_branch_predictor$predict_req_pc = rg_next_pc;
default: stageF_branch_predictor$predict_req_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign stageF_branch_predictor$predict_rsp_instr = d_instr__h25360 ;
assign stageF_branch_predictor$predict_rsp_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$EN_reset = 1'b0 ;
assign stageF_branch_predictor$EN_predict_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign stageF_branch_predictor$EN_bp_train =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ;
// submodule stageF_f_reset_reqs
assign stageF_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageF_f_reset_reqs$DEQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_reqs$CLR = 1'b0 ;
// submodule stageF_f_reset_rsps
assign stageF_f_reset_rsps$ENQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageF_f_reset_rsps$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 =
next_pc__h9847 == stage1_rg_stage_input[215:152] ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112) :
stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2313 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full ||
!stageF_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2325 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2313 ||
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 ||
(imem_rg_pc[1:0] == 2'b0 || near_mem$imem_exc ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 :
!stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 =
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 ||
!stageD_rg_full) &&
stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347 :
stage1_rg_full ;
assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2089 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086 ?
{ 16'b0,
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ?
near_mem$imem_instr[31:16] :
imem_rg_cache_b16 } :
near_mem$imem_instr ;
assign IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347 =
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112) ;
assign IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 =
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 ;
assign IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2589 =
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
stage1_rg_stage_input[151:145] != 7'b0000111 &&
stage1_rg_stage_input[151:145] != 7'b0100111 ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 =
x_out_fbypass_rd__h9453 == stage1_rg_stage_input[139:135] ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 =
x_out_fbypass_rd__h9453 == stage1_rg_stage_input[134:130] ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347 =
x_out_fbypass_rd__h9453 == stage1_rg_stage_input[129:125] ;
assign IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856 =
csr_regfile$read_csr[63:0] | rs1_val__h35329 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1930 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b001) ?
instr__h24785 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h24936 :
32'h0) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1931 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h24586 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1930 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1932 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b001 &&
csr_regfile$read_misa[3]) ?
instr__h24421 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1931 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1933 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b011 &&
csr_regfile$read_misa[5]) ?
instr__h23621 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1932 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1934 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h23416 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1933 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1935 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h23265 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1934 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1936 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h23066 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1935 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1938 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] == 5'd0 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h22817 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h22913 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1936) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1940 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h22521 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h22659 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1938) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1942 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h22247 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h22383 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1940) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1944 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b11) ?
instr__h21975 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b10) ?
instr__h22111 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1942) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1945 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h21880 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1944 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1946 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h21761 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1945 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1948 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b01 &&
imm6__h19874 != 6'd0) ?
instr__h21466 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b10) ?
instr__h21583 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1946) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1949 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b0 &&
imm6__h19874 != 6'd0) ?
instr__h21277 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1948 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1950 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h19874 != 6'd0) ?
instr__h21088 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1949 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1952 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] == 5'd2 &&
nzimm10__h20543 != 10'd0) ?
instr__h20747 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b0 &&
nzimm10__h20758 != 10'd0) ?
instr__h20919 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1950) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1954 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h19874 != 6'd0 ||
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] == 5'd0 &&
imm6__h19874 == 6'd0) ?
instr__h20265 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b001 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h20492 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1952) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1955 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[75:71] != 5'd2 &&
imm6__h19874 != 6'd0) ?
instr__h20136 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1954 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1957 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h19614 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b010 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h19952 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1955) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1958 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h19297 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1957 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1959 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h19232 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1958 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1960 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h19116 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1959 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1961 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h18663 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1960 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1962 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h18434 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1961 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1963 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h18239 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1962 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1964 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h18047 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1963 ;
assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2090 =
(imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11) ?
instr_out___1__h25384 :
IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2089 ;
assign IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884 ||
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892) ;
assign IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169 &&
(stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] == 12'b0 ||
stage1_rg_stage_input[87:76] == 12'b000000000001 ||
(rg_cur_priv != 2'b11 ||
stage1_rg_stage_input[87:76] != 12'b001100000010) &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d2758) :
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b111 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260 =
rs1_val_bypassed__h5597 +
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 =
rs1_val_bypassed__h5597 == rs2_val_bypassed__h5603 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423 =
(rs1_val_bypassed__h5597 ^ 64'h8000000000000000) <
(rs2_val_bypassed__h5603 ^ 64'h8000000000000000) ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 =
rs1_val_bypassed__h5597 < rs2_val_bypassed__h5603 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260[31:0] ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1521 =
((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
alu_outputs___1_val1__h10496 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ?
rs1_val_bypassed__h5597 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1521 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ?
rs2_val_bypassed__h5603 :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d760 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
(stage1_rg_stage_input[151:145] != 7'b1100111 ||
stage1_rg_stage_input[112:110] != 3'd0) ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d962 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 &&
stage1_rg_stage_input[112:110] == 3'd0 ;
assign IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511 =
{ stage1_rg_stage_input[263:232],
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22,
data_to_stage2_rd__h10102,
data_to_stage2_addr__h10103,
x_out_data_to_stage2_val1__h10121,
data_to_stage2_val2__h10105,
alu_outputs___1_fval1__h11709,
alu_outputs___1_fval2__h10701,
alu_outputs___1_fval3__h11711,
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0001111 &&
stage1_rg_stage_input[151:145] != 7'b1110011 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
(stage1_rg_stage_input[151:145] == 7'b0000111 ||
stage1_rg_stage_input[151:145] != 7'b0100111 &&
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2461),
stage1_rg_stage_input[151:145] == 7'b0100111,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505,
rm__h10284 } ;
assign IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 =
x_out_bypass_rd__h9271 == stage1_rg_stage_input[139:135] ;
assign IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339 =
x_out_bypass_rd__h9271 == stage1_rg_stage_input[134:130] ;
assign NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 =
cur_verbosity__h3946 > 4'd1 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2298 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2298 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) &&
stage1_rg_full &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2315 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2315 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2342 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
(!stage1_rg_full || stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) &&
(!stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2346 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2342 ||
(!stage1_rg_full ||
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343) &&
(!stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2407 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111 ||
stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111 ||
stage1_rg_stage_input[151:145] == 7'b0101111) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0000111 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0100111 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2589 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
stage1_rg_stage_input[151:145] == 7'b0101111 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2461 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 &&
(stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2440 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
stage1_rg_stage_input[104:98] != 7'h71 &&
stage1_rg_stage_input[104:98] != 7'h51 &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
stage1_rg_stage_input[104:98] != 7'h70 &&
stage1_rg_stage_input[104:98] != 7'h50 ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 &&
(_0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2484 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00011 ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0) &&
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input[104:98] == 7'h69 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h79 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h78) ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 =
csr_regfile$read_mstatus[14:13] != 2'h0 &&
((stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm != 3'b101 &&
csr_regfile$read_frm != 3'b110 &&
csr_regfile$read_frm != 3'b111 :
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110) ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 =
imem_rg_pc[1:0] != 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 &&
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067 &&
imem_rg_cache_b16[1:0] == 2'b11 ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086 =
imem_rg_pc[1:0] != 2'b0 &&
(imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] != 2'b11 ||
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 &&
imem_rg_cache_b16[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2105 =
!near_mem$imem_exc &&
(imem_rg_pc[1:0] == 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 ||
!near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067 ||
imem_rg_cache_b16[1:0] != 2'b11) &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112 =
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2105 &&
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2109 &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] == 2'b11) ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1104 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1126 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1124 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201 =
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[21]) &&
(rg_cur_priv != 2'b0 || !csr_regfile$read_misa[13]) ||
stage1_rg_stage_input[87:76] != 12'b000100000101 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b000000000001 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d2758 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[22]) ||
stage1_rg_stage_input[87:76] != 12'b000100000010) &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201 ;
assign NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 =
rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h43884 == near_mem$imem_pc ;
assign NOT_rg_run_on_reset_247_248_OR_imem_rg_pc_BITS_ETC___d2255 =
!rg_run_on_reset ||
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284 =
soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h27393 == near_mem$imem_pc ;
assign NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746 =
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00010 &&
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h71 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h79 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) ;
assign NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559 =
(stage1_rg_stage_input[109:105] != 5'b00010 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
stage1_rg_stage_input[109:105] != 5'b00011 &&
stage1_rg_stage_input[109:105] != 5'b0 &&
stage1_rg_stage_input[109:105] != 5'b00001 &&
stage1_rg_stage_input[109:105] != 5'b01100 &&
stage1_rg_stage_input[109:105] != 5'b01000 &&
stage1_rg_stage_input[109:105] != 5'b00100 &&
stage1_rg_stage_input[109:105] != 5'b10000 &&
stage1_rg_stage_input[109:105] != 5'b11000 &&
stage1_rg_stage_input[109:105] != 5'b10100 &&
stage1_rg_stage_input[109:105] != 5'b11100 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157 =
stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[263:260] != 4'b0 &&
stage1_rg_stage_input[263:260] != 4'b1000 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164 =
stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479 =
(stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) &&
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 ;
assign NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169 =
stage1_rg_stage_input[144:140] != 5'd0 ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001 ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774 =
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:258] != 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772) ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 =
stage1_rg_stage_input[151:145] != 7'b0111011 ||
stage1_rg_stage_input[104:98] != 7'b0000001 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011 ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d760 =
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:258] != 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
stage1_rg_stage_input[151:145] == 7'b1100011 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
(stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1249 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
stage1_rg_stage_input[151:145] == 7'b1101111 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1300 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1660 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1664 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334 =
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2948 =
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2950 =
(NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343) &&
stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2948 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) ;
assign NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 =
(stage1_rg_stage_input[99:98] != 2'b0 &&
stage1_rg_stage_input[99:98] != 2'b01 ||
stage1_rg_stage_input[151:145] != 7'b1000011 &&
stage1_rg_stage_input[151:145] != 7'b1000111 &&
stage1_rg_stage_input[151:145] != 7'b1001111 &&
stage1_rg_stage_input[151:145] != 7'b1001011) &&
stage1_rg_stage_input[104:98] != 7'h0 &&
stage1_rg_stage_input[104:98] != 7'h04 &&
stage1_rg_stage_input[104:98] != 7'h08 &&
stage1_rg_stage_input[104:98] != 7'h0C &&
(stage1_rg_stage_input[104:98] != 7'h2C ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h10 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h10 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h10 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h14 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h14 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h70 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h50 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h50 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h50 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h70 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h78 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00010 &&
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
stage1_rg_stage_input[104:98] != 7'b0000001 &&
stage1_rg_stage_input[104:98] != 7'h05 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[104:98] != 7'h0D &&
(stage1_rg_stage_input[104:98] != 7'h2D ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h11 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h11 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h11 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h15 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h15 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h20 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h21 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h51 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h51 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h51 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h71 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00001) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b011 ||
stage1_rg_stage_input[112:110] == 3'b111) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065 ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1126 ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1219 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b1100011 ||
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011 ||
stage1_rg_stage_input[151:145] == 7'b0011011 ||
stage1_rg_stage_input[151:145] == 7'b0111011 ||
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111)) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1335 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 =
!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 &&
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 =
!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 &&
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 &&
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 =
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148 =
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156 =
(stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2) &&
near_mem$dmem_valid &&
near_mem$dmem_exc ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177 =
(stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 ||
!near_mem$dmem_valid ||
!near_mem$dmem_exc) &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289 =
stage2_rg_stage2[397:395] != 3'd2 &&
((stage2_rg_stage2[397:395] == 3'd3) ?
!stage2_mbox$valid :
!stage2_rg_stage2[5] && !stage2_fbox$valid) ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402 =
stage2_rg_stage2[397:395] != 3'd2 &&
((stage2_rg_stage2[397:395] == 3'd3) ?
stage2_mbox$valid :
!stage2_rg_stage2[5] && stage2_fbox$valid) ;
assign NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 =
stageF_branch_predictor$predict_rsp[1:0] != 2'b0 &&
near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h32333 == near_mem$imem_pc ;
assign SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259 =
{ {52{stage1_rg_stage_input_BITS_87_TO_76__q17[11]}},
stage1_rg_stage_input_BITS_87_TO_76__q17 } ;
assign SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737 =
{ {9{offset__h18610[11]}}, offset__h18610 } ;
assign SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762 =
{ {4{offset__h19241[8]}}, offset__h19241 } ;
assign _0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2484 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893 ||
(stage1_rg_stage_input[104:98] == 7'h60 ||
stage1_rg_stage_input[104:98] == 7'h68) &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign _theResult_____1_fst__h12535 =
(stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) ?
rd_val___1__h12531 :
_theResult_____1_fst__h12542 ;
assign _theResult_____1_fst__h12570 =
rs1_val_bypassed__h5597 & _theResult___snd_snd__h16701 ;
assign _theResult____h33877 =
(delta_CPI_instrs__h33876 == 64'd0) ?
delta_CPI_instrs___1__h33921 :
delta_CPI_instrs__h33876 ;
assign _theResult____h5881 = x_out_data_to_stage1_instr__h17651 ;
assign _theResult___fst__h12706 =
(stage1_rg_stage_input[112:110] == 3'b001 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0 &&
!stage1_rg_stage_input[262]) ?
rd_val___1__h16761 :
_theResult___fst__h12713 ;
assign _theResult___fst__h12713 =
stage1_rg_stage_input[262] ?
rd_val___1__h16822 :
rd_val___1__h16793 ;
assign _theResult___fst__h12794 =
{ {32{rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8[31]}},
rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 } ;
assign _theResult___snd_fst_rd_val__h9435 =
stage2_rg_stage2[5] ?
stage2_fbox$word_fst :
stage2_rg_stage2[197:134] ;
assign _theResult___snd_snd__h16701 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259 :
rs2_val_bypassed__h5603 ;
assign _theResult___snd_snd_rd_val__h8290 =
stage2_rg_stage2[5] ?
stage2_rg_stage2[325:262] :
stage2_fbox$word_fst ;
assign addr_of_b32___1__h27521 = addr_of_b32__h27393 + 64'd4 ;
assign addr_of_b32___1__h32461 = addr_of_b32__h32333 + 64'd4 ;
assign addr_of_b32___1__h44012 = addr_of_b32__h43884 + 64'd4 ;
assign addr_of_b32__h27393 = { soc_map$m_pc_reset_value[63:2], 2'd0 } ;
assign addr_of_b32__h32333 =
{ stageF_branch_predictor$predict_rsp[63:2], 2'd0 } ;
assign addr_of_b32__h43884 = { rg_next_pc[63:2], 2'd0 } ;
assign alu_outputs___1_addr__h10323 =
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 ?
branch_target__h10301 :
x_out_cf_info_fallthru_PC__h16274 ;
assign alu_outputs___1_addr__h10697 =
rs1_val_bypassed__h5597 +
{ {52{stage1_rg_stage_input_BITS_75_TO_64__q6[11]}},
stage1_rg_stage_input_BITS_75_TO_64__q6 } ;
assign alu_outputs___1_exc_code__h10979 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
(stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065 ?
4'd2 :
((stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0) ?
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 :
4'd2)) :
4'd2 ;
assign alu_outputs___1_fval1__h11709 = x_out_data_to_stage2_fval1__h10123 ;
assign alu_outputs___1_fval2__h10701 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344) ?
x_out_fbypass_rd_val__h9454 :
rd_val__h9781 ;
assign alu_outputs___1_fval3__h11711 = x_out_data_to_stage2_fval3__h10125 ;
assign alu_outputs___1_val1__h10496 =
(stage1_rg_stage_input[112:110] == 3'b001) ?
rd_val__h16602 :
(stage1_rg_stage_input[262] ?
rd_val__h16675 :
rd_val__h16653) ;
assign alu_outputs___1_val1__h10541 =
(stage1_rg_stage_input[112:110] == 3'd0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262])) ?
rd_val___1__h12450 :
_theResult_____1_fst__h12535 ;
assign alu_outputs___1_val1__h10570 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
rd_val___1__h16730 :
_theResult___fst__h12706 ;
assign alu_outputs___1_val1__h10983 =
stage1_rg_stage_input[112] ?
{ 59'd0, stage1_rg_stage_input[139:135] } :
rs1_val_bypassed__h5597 ;
assign alu_outputs___1_val1__h11011 =
{ 57'd0, stage1_rg_stage_input[104:98] } ;
assign alu_outputs_cf_info_taken_PC__h16267 =
x_out_cf_info_taken_PC__h16275 ;
assign branch_target__h10301 =
stage1_rg_stage_input[401:338] +
{ {51{stage1_rg_stage_input_BITS_63_TO_51__q2[12]}},
stage1_rg_stage_input_BITS_63_TO_51__q2 } ;
assign cpi__h33879 = x__h33878 / 64'd10 ;
assign cpifrac__h33880 = x__h33878 % 64'd10 ;
assign csr_regfile_RDY_server_reset_request_put__219__ETC___d2231 =
csr_regfile$RDY_server_reset_request_put &&
f_reset_reqs$EMPTY_N &&
stageF_f_reset_reqs$FULL_N &&
stageD_f_reset_reqs$FULL_N &&
stage1_f_reset_reqs$FULL_N &&
stage2_f_reset_reqs$FULL_N &&
stage3_f_reset_reqs$FULL_N ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685 ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ||
!stage1_rg_full ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739 =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735 ||
!stage1_rg_full ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2953 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
rg_state == 4'd3 &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2950 &&
!stage2_rg_full &&
!stage3_rg_full ;
assign csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801 =
delta_CPI_cycles__h33875 * 64'd10 ;
assign csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1000 &&
stageD_rg_data[75:71] != 5'd0 ;
assign csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] != 5'd0 ;
assign csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
((stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm == 3'b101 ||
csr_regfile$read_frm == 3'b110 ||
csr_regfile$read_frm == 3'b111 :
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110) ;
assign cur_verbosity__h3946 =
(csr_regfile$read_csr_minstret < cfg_logdelay) ?
4'd0 :
cfg_verbosity ;
assign d_instr__h25360 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ?
instr_out___1__h25362 :
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2090 ;
assign data_to_stage2_addr__h10103 = x_out_data_to_stage2_addr__h10120 ;
assign data_to_stage2_val2__h10105 = x_out_data_to_stage2_val2__h10122 ;
assign decoded_instr_funct10__h30753 =
{ _theResult____h5881[31:25], _theResult____h5881[14:12] } ;
assign decoded_instr_imm12_S__h30755 =
{ _theResult____h5881[31:25], _theResult____h5881[11:7] } ;
assign decoded_instr_imm13_SB__h30756 =
{ _theResult____h5881[31],
_theResult____h5881[7],
_theResult____h5881[30:25],
_theResult____h5881[11:8],
1'b0 } ;
assign decoded_instr_imm21_UJ__h30758 =
{ _theResult____h5881[31],
_theResult____h5881[19:12],
_theResult____h5881[20],
_theResult____h5881[30:21],
1'b0 } ;
assign delta_CPI_cycles__h33875 =
csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
assign delta_CPI_instrs___1__h33921 = delta_CPI_instrs__h33876 + 64'd1 ;
assign delta_CPI_instrs__h33876 =
csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
assign fall_through_pc__h9846 =
stage1_rg_stage_input[401:338] +
(stage1_rg_stage_input[333] ? 64'd4 : 64'd2) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2109 =
imem_rg_pc[1:0] == 2'b0 ||
(!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] == 2'b11) &&
(!imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 ||
imem_rg_cache_b16[1:0] == 2'b11) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 =
imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
near_mem$imem_exc ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ;
assign imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 =
imem_rg_pc[63:2] == imem_rg_cache_addr[63:2] ;
assign imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 =
imem_rg_pc[63:2] == near_mem$imem_pc[63:2] ;
assign imm12__h17903 = { 4'd0, offset__h17775 } ;
assign imm12__h18240 = { 5'd0, offset__h18182 } ;
assign imm12__h19876 = { {6{imm6__h19874[5]}}, imm6__h19874 } ;
assign imm12__h20545 = { {2{nzimm10__h20543[9]}}, nzimm10__h20543 } ;
assign imm12__h20760 = { 2'd0, nzimm10__h20758 } ;
assign imm12__h20956 = { 6'b0, imm6__h19874 } ;
assign imm12__h21293 = { 6'b010000, imm6__h19874 } ;
assign imm12__h22914 = { 3'd0, offset__h22828 } ;
assign imm12__h23266 = { 4'd0, offset__h23200 } ;
assign imm20__h20004 = { {14{imm6__h19874[5]}}, imm6__h19874 } ;
assign imm6__h19874 = { stageD_rg_data[76], stageD_rg_data[70:66] } ;
assign instr___1__h17725 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h17902 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1964 ;
assign instr__h17902 =
{ imm12__h17903, 8'd18, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h18047 =
{ 4'd0,
stageD_rg_data[72:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd18,
offset_BITS_4_TO_0___h18171,
7'b0100011 } ;
assign instr__h18239 =
{ imm12__h18240, rs1__h18241, 3'b010, rd__h18242, 7'b0000011 } ;
assign instr__h18434 =
{ 5'd0,
stageD_rg_data[69],
stageD_rg_data[76],
rd__h18242,
rs1__h18241,
3'b010,
offset_BITS_4_TO_0___h18602,
7'b0100011 } ;
assign instr__h18663 =
{ SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[20],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[10:1],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[11],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[19:12],
12'd111 } ;
assign instr__h19116 = { 12'd0, stageD_rg_data[75:71], 15'd103 } ;
assign instr__h19232 = { 12'd0, stageD_rg_data[75:71], 15'd231 } ;
assign instr__h19297 =
{ SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[12],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[10:5],
5'd0,
rs1__h18241,
3'b0,
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[4:1],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[11],
7'b1100011 } ;
assign instr__h19614 =
{ SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[12],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[10:5],
5'd0,
rs1__h18241,
3'b001,
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[4:1],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[11],
7'b1100011 } ;
assign instr__h19952 =
{ imm12__h19876, 8'd0, stageD_rg_data[75:71], 7'b0010011 } ;
assign instr__h20136 =
{ imm20__h20004, stageD_rg_data[75:71], 7'b0110111 } ;
assign instr__h20265 =
{ imm12__h19876,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h20492 =
{ imm12__h19876,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0011011 } ;
assign instr__h20747 =
{ imm12__h20545,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h20919 = { imm12__h20760, 8'd16, rd__h18242, 7'b0010011 } ;
assign instr__h21088 =
{ imm12__h20956,
stageD_rg_data[75:71],
3'b001,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h21277 =
{ imm12__h20956, rs1__h18241, 3'b101, rs1__h18241, 7'b0010011 } ;
assign instr__h21466 =
{ imm12__h21293, rs1__h18241, 3'b101, rs1__h18241, 7'b0010011 } ;
assign instr__h21583 =
{ imm12__h19876, rs1__h18241, 3'b111, rs1__h18241, 7'b0010011 } ;
assign instr__h21761 =
{ 7'b0,
stageD_rg_data[70:66],
8'd0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h21880 =
{ 7'b0,
stageD_rg_data[70:66],
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h21975 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b111,
rs1__h18241,
7'b0110011 } ;
assign instr__h22111 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b110,
rs1__h18241,
7'b0110011 } ;
assign instr__h22247 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b100,
rs1__h18241,
7'b0110011 } ;
assign instr__h22383 =
{ 7'b0100000,
rd__h18242,
rs1__h18241,
3'b0,
rs1__h18241,
7'b0110011 } ;
assign instr__h22521 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b0,
rs1__h18241,
7'b0111011 } ;
assign instr__h22659 =
{ 7'b0100000,
rd__h18242,
rs1__h18241,
3'b0,
rs1__h18241,
7'b0111011 } ;
assign instr__h22817 =
{ 12'b000000000001,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b1110011 } ;
assign instr__h22913 =
{ imm12__h22914, 8'd19, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h23066 =
{ 3'd0,
stageD_rg_data[73:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd19,
offset_BITS_4_TO_0___h23541,
7'b0100011 } ;
assign instr__h23265 =
{ imm12__h23266, rs1__h18241, 3'b011, rd__h18242, 7'b0000011 } ;
assign instr__h23416 =
{ 4'd0,
stageD_rg_data[70:69],
stageD_rg_data[76],
rd__h18242,
rs1__h18241,
3'b011,
offset_BITS_4_TO_0___h23541,
7'b0100011 } ;
assign instr__h23621 =
{ imm12__h17903, 8'd18, stageD_rg_data[75:71], 7'b0000111 } ;
assign instr__h24421 =
{ imm12__h22914, 8'd19, stageD_rg_data[75:71], 7'b0000111 } ;
assign instr__h24586 =
{ 3'd0,
stageD_rg_data[73:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd19,
offset_BITS_4_TO_0___h23541,
7'b0100111 } ;
assign instr__h24785 =
{ imm12__h23266, rs1__h18241, 3'b011, rd__h18242, 7'b0000111 } ;
assign instr__h24936 =
{ 4'd0,
stageD_rg_data[70:69],
stageD_rg_data[76],
rd__h18242,
rs1__h18241,
3'b011,
offset_BITS_4_TO_0___h23541,
7'b0100111 } ;
assign instr_out___1__h25362 =
{ near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
assign instr_out___1__h25384 = { 16'b0, near_mem$imem_instr[15:0] } ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2117 =
near_mem$imem_exc ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 =
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2117 ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11 ;
assign near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067 =
near_mem$imem_pc == imem_rg_pc + 64'd2 ;
assign near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2214 =
near_mem$imem_valid && near_mem$imem_exc &&
near_mem$imem_exc_code != 4'd0 &&
near_mem$imem_exc_code != 4'd1 &&
near_mem$imem_exc_code != 4'd2 &&
near_mem$imem_exc_code != 4'd3 &&
near_mem$imem_exc_code != 4'd4 &&
near_mem$imem_exc_code != 4'd5 &&
near_mem$imem_exc_code != 4'd6 &&
near_mem$imem_exc_code != 4'd7 &&
near_mem$imem_exc_code != 4'd8 &&
near_mem$imem_exc_code != 4'd9 &&
near_mem$imem_exc_code != 4'd11 &&
near_mem$imem_exc_code != 4'd12 &&
near_mem$imem_exc_code != 4'd13 &&
near_mem$imem_exc_code != 4'd15 ;
assign new_epoch__h26813 = rg_epoch + 2'd1 ;
assign next_pc___1__h13967 = stage1_rg_stage_input[401:338] + 64'd2 ;
assign next_pc__h10336 =
stage1_rg_stage_input[401:338] +
{ {43{stage1_rg_stage_input_BITS_30_TO_10__q1[20]}},
stage1_rg_stage_input_BITS_30_TO_10__q1 } ;
assign next_pc__h10371 =
{ IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260[63:1],
1'd0 } ;
assign next_pc__h13964 = stage1_rg_stage_input[401:338] + 64'd4 ;
assign next_pc__h9847 = x_out_next_pc__h9864 ;
assign nzimm10__h20543 =
{ stageD_rg_data[76],
stageD_rg_data[68:67],
stageD_rg_data[69],
stageD_rg_data[66],
stageD_rg_data[70],
4'b0 } ;
assign nzimm10__h20758 =
{ stageD_rg_data[74:71],
stageD_rg_data[76:75],
stageD_rg_data[69],
stageD_rg_data[70],
2'b0 } ;
assign offset_BITS_4_TO_0___h18171 = { stageD_rg_data[75:73], 2'b0 } ;
assign offset_BITS_4_TO_0___h18602 =
{ stageD_rg_data[75:74], stageD_rg_data[70], 2'b0 } ;
assign offset_BITS_4_TO_0___h23541 = { stageD_rg_data[75:74], 3'b0 } ;
assign offset__h17775 =
{ stageD_rg_data[67:66],
stageD_rg_data[76],
stageD_rg_data[70:68],
2'b0 } ;
assign offset__h18182 =
{ stageD_rg_data[69],
stageD_rg_data[76:74],
stageD_rg_data[70],
2'b0 } ;
assign offset__h18610 =
{ stageD_rg_data[76],
stageD_rg_data[72],
stageD_rg_data[74:73],
stageD_rg_data[70],
stageD_rg_data[71],
stageD_rg_data[66],
stageD_rg_data[75],
stageD_rg_data[69:67],
1'b0 } ;
assign offset__h19241 =
{ stageD_rg_data[76],
stageD_rg_data[70:69],
stageD_rg_data[66],
stageD_rg_data[75:74],
stageD_rg_data[68:67],
1'b0 } ;
assign offset__h22828 =
{ stageD_rg_data[68:66],
stageD_rg_data[76],
stageD_rg_data[70:69],
3'b0 } ;
assign offset__h23200 =
{ stageD_rg_data[70:69], stageD_rg_data[76:74], 3'b0 } ;
assign output_stage2___1_data_to_stage3_frd_val__h8219 =
stage2_rg_stage2[5] ?
((stage2_rg_stage2[412:410] == 3'b010) ?
{ 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } :
near_mem$dmem_word64) :
stage2_rg_stage2[197:134] ;
assign rd__h18242 = { 2'b01, stageD_rg_data[68:66] } ;
assign rd_val___1__h12450 =
rs1_val_bypassed__h5597 + _theResult___snd_snd__h16701 ;
assign rd_val___1__h12531 =
rs1_val_bypassed__h5597 - _theResult___snd_snd__h16701 ;
assign rd_val___1__h12538 =
((rs1_val_bypassed__h5597 ^ 64'h8000000000000000) <
(_theResult___snd_snd__h16701 ^ 64'h8000000000000000)) ?
64'd1 :
64'd0 ;
assign rd_val___1__h12545 =
(rs1_val_bypassed__h5597 < _theResult___snd_snd__h16701) ?
64'd1 :
64'd0 ;
assign rd_val___1__h12552 =
rs1_val_bypassed__h5597 ^ _theResult___snd_snd__h16701 ;
assign rd_val___1__h12559 =
rs1_val_bypassed__h5597 | _theResult___snd_snd__h16701 ;
assign rd_val___1__h16730 =
{ {32{IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18[31]}},
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18 } ;
assign rd_val___1__h16761 = { {32{x__h16764[31]}}, x__h16764 } ;
assign rd_val___1__h16793 = { {32{x__h16796[31]}}, x__h16796 } ;
assign rd_val___1__h16822 = { {32{tmp__h16821[31]}}, tmp__h16821 } ;
assign rd_val___1__h16874 =
{ {32{rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9[31]}},
rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 } ;
assign rd_val___1__h16922 =
{ {32{rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10[31]}},
rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 } ;
assign rd_val___1__h16928 = { {32{x__h16931[31]}}, x__h16931 } ;
assign rd_val___1__h16973 = { {32{x__h16976[31]}}, x__h16976 } ;
assign rd_val__h10612 = { {32{v32__h10610[31]}}, v32__h10610 } ;
assign rd_val__h10633 = stage1_rg_stage_input[401:338] + rd_val__h10612 ;
assign rd_val__h16602 = rs1_val_bypassed__h5597 << shamt__h10483 ;
assign rd_val__h16653 = rs1_val_bypassed__h5597 >> shamt__h10483 ;
assign rd_val__h16675 =
rs1_val_bypassed__h5597 >> shamt__h10483 |
~(64'hFFFFFFFFFFFFFFFF >> shamt__h10483) &
{64{rs1_val_bypassed__h5597[63]}} ;
assign rd_val__h9684 =
(!stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407) ?
stage3_rg_stage3[134:71] :
gpr_regfile$read_rs1 ;
assign rd_val__h9717 =
(!stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415) ?
stage3_rg_stage3[134:71] :
gpr_regfile$read_rs2 ;
assign rd_val__h9750 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs1 ;
assign rd_val__h9781 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs2 ;
assign rd_val__h9815 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[139:135] == stage1_rg_stage_input[129:125]) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs3 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1124 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
stage1_rg_stage_input[87:76] == 12'b000100000101 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1189 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[22]) ||
stage1_rg_stage_input[87:76] != 12'b000100000010 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1203 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1635 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 &&
stage1_rg_stage_input[87:76] != 12'b000000000001 ;
assign rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2937 =
rg_state == 4'd12 && csr_regfile$wfi_resume &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753 =
rg_state == 4'd3 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750 &&
!stage3_rg_full &&
!stage2_rg_full ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2779 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753 &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 &&
(stage1_rg_stage_input[332] ||
((stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
((stage1_rg_stage_input[151:145] == 7'b1100111) ?
stage1_rg_stage_input[112:110] != 3'd0 :
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774))) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2814 =
rg_state == 4'd3 &&
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2814 &&
!stage3_rg_full &&
!stage2_rg_full &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2908 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2917 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2926 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_stage3_rg_full_8_OR_st_ETC___d2338 =
rg_state == 4'd3 &&
(stage3_rg_full || stage2_rg_full || stage1_rg_full ||
stageD_rg_full ||
stageF_rg_full) &&
stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2337 ;
assign rg_state_7_EQ_5_941_AND_NOT_stageF_rg_full_094_ETC___d2942 =
rg_state == 4'd5 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_094_ETC___d2865 =
rg_state == 4'd8 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797 =
rg_trap_info[131:68] == csr_regfile$csr_trap_actions[193:130] ;
assign rm__h10284 =
(stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm :
stage1_rg_stage_input[112:110] ;
assign rs1__h18241 = { 2'b01, stageD_rg_data[73:71] } ;
assign rs1_val__h34495 =
(rg_trap_instr[14:12] == 3'b001) ?
rg_csr_val1 :
{ 59'd0, rg_trap_instr[19:15] } ;
assign rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 =
rs1_val_bypassed__h5597[31:0] - rs2_val_bypassed__h5603[31:0] ;
assign rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 =
rs1_val_bypassed__h5597[31:0] + rs2_val_bypassed__h5603[31:0] ;
assign rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 =
rs1_val_bypassed__h5597[31:0] >> rs2_val_bypassed__h5603[4:0] |
~(32'hFFFFFFFF >> rs2_val_bypassed__h5603[4:0]) &
{32{rs1_val_bypassed597_BITS_31_TO_0__q7[31]}} ;
assign rs1_val_bypassed597_BITS_31_TO_0__q7 =
rs1_val_bypassed__h5597[31:0] ;
assign rs1_val_bypassed__h5597 =
(stage1_rg_stage_input[139:135] == 5'd0) ? 64'd0 : val__h9686 ;
assign rs2_val_bypassed__h5603 =
(stage1_rg_stage_input[134:130] == 5'd0) ? 64'd0 : val__h9719 ;
assign shamt__h10483 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
stage1_rg_stage_input[81:76] :
rs2_val_bypassed__h5603[5:0] ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1317 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111) ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1375 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
stage1_rg_stage_input[151:145] == 7'b0101111 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1401 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1398 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d990 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d998 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995 ;
assign stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363 =
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349) ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2427 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869 ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10284 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[104:98] == 7'h78 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869 =
stage1_rg_stage_input[104:98] == 7'h0 ||
stage1_rg_stage_input[104:98] == 7'h04 ||
stage1_rg_stage_input[104:98] == 7'h08 ||
stage1_rg_stage_input[104:98] == 7'h0C ||
stage1_rg_stage_input[104:98] == 7'h2C &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h10 && rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h10 &&
(rm__h10284 == 3'b001 || rm__h10284 == 3'b010) ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d878 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869 ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10284 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h60 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h60 &&
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[104:98] == 7'h70 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d886 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d878 ||
stage1_rg_stage_input[104:98] == 7'h50 &&
(rm__h10284 == 3'b010 || rm__h10284 == 3'b001 ||
rm__h10284 == 3'b0) ||
stage1_rg_stage_input[104:98] == 7'h70 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d886 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[104:98] == 7'h78 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918 =
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input[104:98] == 7'h05 ||
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[104:98] == 7'h0D ||
stage1_rg_stage_input[104:98] == 7'h2D &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h11 && rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h11 &&
(rm__h10284 == 3'b001 || rm__h10284 == 3'b010) ||
stage1_rg_stage_input[104:98] == 7'h15 && rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h15 && rm__h10284 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h20 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d929 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918 ||
stage1_rg_stage_input[104:98] == 7'h21 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h51 && rm__h10284 == 3'b010 ||
stage1_rg_stage_input[104:98] == 7'h51 &&
(rm__h10284 == 3'b001 || rm__h10284 == 3'b0) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d929 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'd0 ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035 =
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
(stage1_rg_stage_input[263:260] == 4'b0 ||
stage1_rg_stage_input[263:260] == 4'b1000) ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049 =
stage1_rg_stage_input[112:110] == 3'b001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b0 ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806 =
stage1_rg_stage_input[112:110] == 3'd0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) ||
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262] ||
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 ;
assign stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065 =
stage1_rg_stage_input[144:140] == 5'd0 &&
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ;
assign stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103 =
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) &&
stage1_rg_stage_input[87:76] == 12'b000100000010 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341 =
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 ||
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892 =
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 =
stage1_rg_stage_input[151:145] == 7'b0111011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d962 =
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 ||
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:258] == 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960) ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1398 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1588 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 =
stage1_rg_stage_input[335:334] == rg_epoch ;
assign stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2440 =
(stage1_rg_stage_input[99:98] == 2'b0 ||
stage1_rg_stage_input[99:98] == 2'b01) &&
(stage1_rg_stage_input[151:145] == 7'b1000011 ||
stage1_rg_stage_input[151:145] == 7'b1000111 ||
stage1_rg_stage_input[151:145] == 7'b1001111 ||
stage1_rg_stage_input[151:145] == 7'b1001011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2427 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918 ||
stage1_rg_stage_input[104:98] == 7'h21 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938 =
(stage1_rg_stage_input[99:98] == 2'b0 ||
stage1_rg_stage_input[99:98] == 2'b01) &&
(stage1_rg_stage_input[151:145] == 7'b1000011 ||
stage1_rg_stage_input[151:145] == 7'b1000111 ||
stage1_rg_stage_input[151:145] == 7'b1001111 ||
stage1_rg_stage_input[151:145] == 7'b1001011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893 ||
(stage1_rg_stage_input[104:98] == 7'h60 ||
stage1_rg_stage_input[104:98] == 7'h68) &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096 =
stage1_rg_stage_input[332] ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001 ;
assign stage1_rg_stage_input_BITS_30_TO_10__q1 =
stage1_rg_stage_input[30:10] ;
assign stage1_rg_stage_input_BITS_63_TO_51__q2 =
stage1_rg_stage_input[63:51] ;
assign stage1_rg_stage_input_BITS_75_TO_64__q6 =
stage1_rg_stage_input[75:64] ;
assign stage1_rg_stage_input_BITS_87_TO_76__q17 =
stage1_rg_stage_input[87:76] ;
assign stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2379 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1006 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1006 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1009 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1021 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1021 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1024 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1039 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1039 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1042 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1053 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1053 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1056 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1070 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1070 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1073 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1085 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1085 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1088 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1109 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1104 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1110 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1109 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1110 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1113 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1131 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1132 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1131 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1132 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1135 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1208 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1189) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1203) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1209 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
rg_cur_priv != 2'b11 ||
stage1_rg_stage_input[87:76] != 12'b001100000010) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1208 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1210 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1209 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1213 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b111) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b0001111 ||
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b0001111 ||
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1210 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1214 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1213 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1215 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1214 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1215 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1278 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1100111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0000111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0100111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1368 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] == 7'b1100011 ||
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0101111) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5] &&
stage2_fbox$valid ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 &&
(IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 ||
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 &&
(IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 ||
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 ||
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2381 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2383 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2385 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2387 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2389 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2395 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402) ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 =
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 ||
!near_mem$dmem_valid ||
!near_mem$dmem_exc ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215 =
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244 =
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5) ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296 =
stage2_rg_stage2[397:395] == 3'd2 ||
((stage2_rg_stage2[397:395] == 3'd3) ?
stage2_mbox$valid :
stage2_rg_stage2[5] || stage2_fbox$valid) ;
assign stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2337 =
(stage3_rg_full || !stage2_rg_full ||
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168) &&
(stage3_rg_full || stage2_rg_full || !stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334) ;
assign stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407 =
stage3_rg_stage3[139:135] == stage1_rg_stage_input[139:135] ;
assign stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415 =
stage3_rg_stage3[139:135] == stage1_rg_stage_input[134:130] ;
assign stageF_f_reset_rsps_i_notEmpty__241_AND_stageD_ETC___d2261 =
stageF_f_reset_rsps$EMPTY_N && stageD_f_reset_rsps$EMPTY_N &&
stage1_f_reset_rsps$EMPTY_N &&
stage2_f_reset_rsps$EMPTY_N &&
stage3_f_reset_rsps$EMPTY_N &&
f_reset_rsps$FULL_N &&
NOT_rg_run_on_reset_247_248_OR_imem_rg_pc_BITS_ETC___d2255 ;
assign stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126 =
stageF_rg_full && near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 &&
!near_mem$imem_exc ;
assign sxl__h6937 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[35:34] :
2'd0 ;
assign tmp__h16821 =
rs1_val_bypassed__h5597[31:0] >> stage1_rg_stage_input[80:76] |
~(32'hFFFFFFFF >> stage1_rg_stage_input[80:76]) &
{32{rs1_val_bypassed597_BITS_31_TO_0__q7[31]}} ;
assign trap_info_tval__h15117 =
(stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1635)) ?
(stage1_rg_stage_input[333] ?
{ 32'd0, stage1_rg_stage_input[263:232] } :
{ 48'd0, stage1_rg_stage_input[231:216] }) :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 ;
assign uxl__h6938 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[33:32] :
2'd0 ;
assign v32__h10610 = { stage1_rg_stage_input[50:31], 12'h0 } ;
assign val__h9686 =
(stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 &&
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337) ?
x_out_bypass_rd_val__h9272 :
rd_val__h9684 ;
assign val__h9719 =
(stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 &&
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) ?
x_out_bypass_rd_val__h9272 :
rd_val__h9717 ;
assign value__h15187 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[327:264] :
trap_info_tval__h15117 ;
assign x__h16764 =
rs1_val_bypassed__h5597[31:0] << stage1_rg_stage_input[80:76] ;
assign x__h16796 =
rs1_val_bypassed__h5597[31:0] >> stage1_rg_stage_input[80:76] ;
assign x__h16931 =
rs1_val_bypassed__h5597[31:0] << rs2_val_bypassed__h5603[4:0] ;
assign x__h16976 =
rs1_val_bypassed__h5597[31:0] >> rs2_val_bypassed__h5603[4:0] ;
assign x__h33878 =
csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801[63:0] /
_theResult____h33877 ;
assign x_exc_code__h44308 =
(csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
csr_regfile$interrupt_pending[3:0] :
4'd0 ;
assign x_out_cf_info_fallthru_PC__h16274 =
stage1_rg_stage_input[333] ?
next_pc__h13964 :
next_pc___1__h13967 ;
assign x_out_data_to_stage1_instr__h17651 =
stageD_rg_data[165] ? stageD_rg_data[95:64] : instr___1__h17725 ;
assign x_out_data_to_stage2_fval1__h10123 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343) ?
x_out_fbypass_rd_val__h9454 :
rd_val__h9750 ;
assign x_out_data_to_stage2_fval3__h10125 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ?
x_out_fbypass_rd_val__h9454 :
rd_val__h9815 ;
assign x_out_data_to_stage2_rd__h10119 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ?
data_to_stage2_rd__h10102 :
5'd0 ;
assign x_out_data_to_stage2_val2__h10122 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
branch_target__h10301 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 ;
assign x_out_next_pc__h9864 =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 ?
data_to_stage2_addr__h10103 :
fall_through_pc__h9846 ;
assign x_out_trap_info_exc_code__h15122 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:328] :
alu_outputs_exc_code__h11737 ;
assign y__h35607 = ~rs1_val__h35329 ;
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4: value__h8670 = stage2_rg_stage2[493:430];
default: value__h8670 = stage2_rg_stage2[493:430];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_exc_code)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
x_out_trap_info_exc_code__h8780 = near_mem$dmem_exc_code;
default: x_out_trap_info_exc_code__h8780 = 4'd2;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4: value__h8884 = stage2_rg_stage2[389:326];
default: value__h8884 = 64'd0;
endcase
end
always@(stage2_rg_stage2 or stage2_fbox$word_snd)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
x_out_data_to_stage3_fpr_flags__h8344 = 5'd0;
default: x_out_data_to_stage3_fpr_flags__h8344 = stage2_fbox$word_snd;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4:
x_out_data_to_stage3_rd__h8340 = stage2_rg_stage2[394:390];
3'd2: x_out_data_to_stage3_rd__h8340 = 5'd0;
default: x_out_data_to_stage3_rd__h8340 = stage2_rg_stage2[394:390];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4: x_out_bypass_rd__h9271 = stage2_rg_stage2[394:390];
default: x_out_bypass_rd__h9271 = stage2_rg_stage2[394:390];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4: x_out_fbypass_rd__h9453 = stage2_rg_stage2[394:390];
default: x_out_fbypass_rd__h9453 = stage2_rg_stage2[394:390];
endcase
end
always@(rg_trap_instr or rg_csr_val1)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b011: rs1_val__h35329 = rg_csr_val1;
default: rs1_val__h35329 = { 59'd0, rg_trap_instr[19:15] };
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$word_fst or
output_stage2___1_data_to_stage3_frd_val__h8219)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd2, 3'd3:
x_out_data_to_stage3_frd_val__h8345 = stage2_rg_stage2[197:134];
3'd1, 3'd4:
x_out_data_to_stage3_frd_val__h8345 =
output_stage2___1_data_to_stage3_frd_val__h8219;
default: x_out_data_to_stage3_frd_val__h8345 = stage2_fbox$word_fst;
endcase
end
always@(stage2_rg_stage2 or
_theResult___snd_snd_rd_val__h8290 or
near_mem$dmem_word64 or stage2_mbox$word)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd2:
x_out_data_to_stage3_rd_val__h8341 = stage2_rg_stage2[325:262];
3'd1, 3'd4: x_out_data_to_stage3_rd_val__h8341 = near_mem$dmem_word64;
3'd3: x_out_data_to_stage3_rd_val__h8341 = stage2_mbox$word;
default: x_out_data_to_stage3_rd_val__h8341 =
_theResult___snd_snd_rd_val__h8290;
endcase
end
always@(stage2_rg_stage2 or
_theResult___snd_snd_rd_val__h8290 or stage2_mbox$word)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4:
x_out_bypass_rd_val__h9272 = stage2_rg_stage2[325:262];
3'd3: x_out_bypass_rd_val__h9272 = stage2_mbox$word;
default: x_out_bypass_rd_val__h9272 =
_theResult___snd_snd_rd_val__h8290;
endcase
end
always@(stage2_rg_stage2 or _theResult___snd_fst_rd_val__h9435)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4: x_out_fbypass_rd_val__h9454 = stage2_rg_stage2[197:134];
default: x_out_fbypass_rd_val__h9454 =
_theResult___snd_fst_rd_val__h9435;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0000111,
7'b0010011,
7'b0010111,
7'b0011011,
7'b0110011,
7'b0110111,
7'b0111011,
7'b1100111,
7'b1101111:
data_to_stage2_rd__h10102 = stage1_rg_stage_input[144:140];
7'b1100011: data_to_stage2_rd__h10102 = 5'd0;
default: data_to_stage2_rd__h10102 = stage1_rg_stage_input[144:140];
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
near_mem$dmem_valid;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!near_mem$dmem_valid;
3'd3:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!stage2_mbox$valid;
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
!near_mem$dmem_valid || near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
!stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
stage2_rg_stage2[397:395] == 3'd5 && !stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
near_mem$dmem_valid && !near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
stage2_rg_stage2[397:395] != 3'd5 || stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 =
stage2_rg_stage2[5];
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5 =
!stage2_rg_stage2[5];
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273 =
near_mem$dmem_valid && near_mem$dmem_exc ||
stage2_rg_stage2[394:390] == 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] != 3'd3 && stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[394:390] != 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 =
stage2_rg_stage2[397:395] != 3'd2 &&
(stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5]);
endcase
end
always@(stage2_rg_stage2 or
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289 or
near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[394:390] != 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 =
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289;
endcase
end
always@(stage2_rg_stage2 or
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296 or
near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 =
near_mem$dmem_valid && near_mem$dmem_exc ||
stage2_rg_stage2[394:390] == 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 =
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296;
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305 =
near_mem$dmem_valid && near_mem$dmem_exc ||
!stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 =
near_mem$dmem_valid && near_mem$dmem_exc ||
!stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5] ||
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5] &&
!stage2_fbox$valid;
endcase
end
always@(stage1_rg_stage_input or
_theResult___fst__h12794 or
rd_val___1__h16874 or
rd_val___1__h16928 or rd_val___1__h16973 or rd_val___1__h16922)
begin
case (stage1_rg_stage_input[97:88])
10'b0: alu_outputs___1_val1__h10598 = rd_val___1__h16874;
10'b0000000001: alu_outputs___1_val1__h10598 = rd_val___1__h16928;
10'b0000000101: alu_outputs___1_val1__h10598 = rd_val___1__h16973;
10'b0100000000: alu_outputs___1_val1__h10598 = rd_val___1__h16922;
default: alu_outputs___1_val1__h10598 = _theResult___fst__h12794;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423)
begin
case (stage1_rg_stage_input[112:110])
3'd0:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b001:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b100:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b101:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b110:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
default: IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423)
begin
case (stage1_rg_stage_input[112:110])
3'd0:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b001:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b100:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b101:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b110:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
default: IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
stage1_rg_stage_input[112:110] == 3'b111 &&
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b010, 3'b011, 3'b100, 3'b110:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 =
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[263] &&
stage1_rg_stage_input[262] &&
stage1_rg_stage_input[261:257] != 5'b0;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 =
stage1_rg_stage_input[112:110] != 3'b111 ||
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[263] &&
stage1_rg_stage_input[262] &&
stage1_rg_stage_input[261:257] != 5'b0;
endcase
end
always@(stage1_rg_stage_input or
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 or
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 or
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746 or
csr_regfile$read_mstatus or
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559)
begin
case (stage1_rg_stage_input[151:145])
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750 =
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750 =
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 ||
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 &&
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[151:145] == 7'b0001111 ||
stage1_rg_stage_input[151:145] == 7'b1110011 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
stage1_rg_stage_input[112:110] != 3'd0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0 ||
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0);
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b010, 3'b011, 3'b100, 3'b110:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 =
stage1_rg_stage_input[151:145] == 7'b0010011 ||
!stage1_rg_stage_input[263] ||
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[261:257] == 5'b0;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 =
stage1_rg_stage_input[112:110] == 3'b111 &&
(stage1_rg_stage_input[151:145] == 7'b0010011 ||
!stage1_rg_stage_input[263] ||
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[261:257] == 5'b0);
endcase
end
always@(stage1_rg_stage_input or
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 or
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938 or
rm__h10284 or csr_regfile$read_mstatus)
begin
case (stage1_rg_stage_input[151:145])
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952 =
csr_regfile$read_mstatus[14:13] != 2'h0 &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011);
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952 =
(stage1_rg_stage_input[109:105] == 5'b00010 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[109:105] == 5'b00011 ||
stage1_rg_stage_input[109:105] == 5'b0 ||
stage1_rg_stage_input[109:105] == 5'b00001 ||
stage1_rg_stage_input[109:105] == 5'b01100 ||
stage1_rg_stage_input[109:105] == 5'b01000 ||
stage1_rg_stage_input[109:105] == 5'b00100 ||
stage1_rg_stage_input[109:105] == 5'b10000 ||
stage1_rg_stage_input[109:105] == 5'b11000 ||
stage1_rg_stage_input[109:105] == 5'b10100 ||
stage1_rg_stage_input[109:105] == 5'b11100) &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011);
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 &&
(stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00011 ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0);
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[151:145] != 7'b0001111 &&
stage1_rg_stage_input[151:145] != 7'b1110011 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 or
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0 &&
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[112:110] == 3'b101 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0;
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input[97:88] == 10'b0 ||
stage1_rg_stage_input[97:88] == 10'b0100000000 ||
stage1_rg_stage_input[97:88] == 10'b0000000001 ||
stage1_rg_stage_input[97:88] == 10'b0000000101 ||
stage1_rg_stage_input[97:88] == 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111 ||
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14;
endcase
end
always@(rg_cur_priv)
begin
case (rg_cur_priv)
2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd8;
2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd9;
default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd11;
endcase
end
always@(stage1_rg_stage_input or CASE_rg_cur_priv_0b0_8_0b1_9_11__q15)
begin
case (stage1_rg_stage_input[87:76])
12'b0:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 =
CASE_rg_cur_priv_0b0_8_0b1_9_11__q15;
12'b000000000001:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 = 4'd3;
default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or alu_outputs___1_exc_code__h10979)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0001111,
7'b0010011,
7'b0010111,
7'b0011011,
7'b0100011,
7'b0110011,
7'b0110111,
7'b0111011,
7'b1100011:
alu_outputs_exc_code__h11737 = 4'd2;
7'b1100111, 7'b1101111: alu_outputs_exc_code__h11737 = 4'd0;
7'b1110011:
alu_outputs_exc_code__h11737 = alu_outputs___1_exc_code__h10979;
default: alu_outputs_exc_code__h11737 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or
_theResult_____1_fst__h12570 or
rd_val___1__h12538 or
rd_val___1__h12545 or rd_val___1__h12552 or rd_val___1__h12559)
begin
case (stage1_rg_stage_input[112:110])
3'b010: _theResult_____1_fst__h12542 = rd_val___1__h12538;
3'b011: _theResult_____1_fst__h12542 = rd_val___1__h12545;
3'b100: _theResult_____1_fst__h12542 = rd_val___1__h12552;
3'b110: _theResult_____1_fst__h12542 = rd_val___1__h12559;
default: _theResult_____1_fst__h12542 = _theResult_____1_fst__h12570;
endcase
end
always@(stage1_rg_stage_input or
alu_outputs___1_addr__h10697 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260 or
rs1_val_bypassed__h5597 or
alu_outputs___1_addr__h10323 or next_pc__h10371 or next_pc__h10336)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011, 7'b0000111:
x_out_data_to_stage2_addr__h10120 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260;
7'b0100011:
x_out_data_to_stage2_addr__h10120 = alu_outputs___1_addr__h10697;
7'b0101111: x_out_data_to_stage2_addr__h10120 = rs1_val_bypassed__h5597;
7'b1100011:
x_out_data_to_stage2_addr__h10120 = alu_outputs___1_addr__h10323;
7'b1100111: x_out_data_to_stage2_addr__h10120 = next_pc__h10371;
7'b1101111: x_out_data_to_stage2_addr__h10120 = next_pc__h10336;
default: x_out_data_to_stage2_addr__h10120 =
alu_outputs___1_addr__h10697;
endcase
end
always@(stage1_rg_stage_input or
next_pc__h10371 or branch_target__h10301 or next_pc__h10336)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011: x_out_cf_info_taken_PC__h16275 = branch_target__h10301;
7'b1101111: x_out_cf_info_taken_PC__h16275 = next_pc__h10336;
default: x_out_cf_info_taken_PC__h16275 = next_pc__h10371;
endcase
end
always@(stage1_rg_stage_input or rs2_val_bypassed__h5603)
begin
case (stage1_rg_stage_input[151:145])
7'b0100011, 7'b0101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 =
rs2_val_bypassed__h5603;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 =
rs2_val_bypassed__h5603;
endcase
end
always@(stage1_rg_stage_input or
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645 or
data_to_stage2_addr__h10103)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 =
data_to_stage2_addr__h10103;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 =
(stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645) ?
stage1_rg_stage_input[401:338] :
64'd0;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 =
near_mem$dmem_valid && !near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 =
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!near_mem$dmem_valid || near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!stage2_fbox$valid;
endcase
end
always@(stage1_rg_stage_input or
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 or
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 or
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746 or
csr_regfile$read_mstatus or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157 or
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559 or
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0001111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164 &&
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157;
7'b0100011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559;
7'b1110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 ||
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 &&
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[112:110] != 3'd0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0 ||
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0);
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768;
endcase
end
always@(stage1_rg_stage_input or
rs1_val_bypassed__h5597 or
alu_outputs___1_val1__h10541 or
rd_val__h10633 or
alu_outputs___1_val1__h10570 or
alu_outputs___1_val1__h11011 or
rd_val__h10612 or
alu_outputs___1_val1__h10598 or alu_outputs___1_val1__h10983)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10541;
7'b0010111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
rd_val__h10633;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10570;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h11011;
7'b0110111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
rd_val__h10612;
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10598;
7'b1110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10983;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
rs1_val_bypassed__h5597;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522 or
x_out_cf_info_fallthru_PC__h16274)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
x_out_data_to_stage2_val1__h10121 =
x_out_cf_info_fallthru_PC__h16274;
default: x_out_data_to_stage2_val1__h10121 =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011, 7'b0000111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd1;
7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd0;
7'b0100011, 7'b0100111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd2;
7'b0101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd4;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd5;
endcase
end
always@(stage1_rg_stage_input or
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011, 7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd0;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ?
3'd3 :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd0;
7'b1100111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd2;
7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd1;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'hFFFFFFFFFFFFFFFF;
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY 2'd0;
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_logdelay$EN)
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (imem_rg_cache_addr$EN)
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
if (rg_cur_priv$EN)
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
if (rg_run_on_reset$EN)
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (stage1_rg_full$EN)
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
if (stage2_rg_full$EN)
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
if (stage2_rg_resetting$EN)
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
stage2_rg_resetting$D_IN;
if (stage3_rg_full$EN)
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
if (stageD_rg_full$EN)
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY stageD_rg_full$D_IN;
if (stageF_rg_epoch$EN)
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY stageF_rg_epoch$D_IN;
if (stageF_rg_full$EN)
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY stageF_rg_full$D_IN;
end
if (imem_rg_cache_b16$EN)
imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
if (imem_rg_mstatus_MXR$EN)
imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
if (imem_rg_priv$EN)
imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
if (imem_rg_satp$EN)
imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
if (imem_rg_sstatus_SUM$EN)
imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
if (imem_rg_tval$EN)
imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
if (rg_epoch$EN) rg_epoch <= `BSV_ASSIGNMENT_DELAY rg_epoch$D_IN;
if (rg_mstatus_MXR$EN)
rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
if (rg_sstatus_SUM$EN)
rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
if (rg_start_CPI_cycles$EN)
rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
if (rg_start_CPI_instrs$EN)
rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
if (rg_trap_info$EN)
rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
if (rg_trap_instr$EN)
rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
if (rg_trap_interrupt$EN)
rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
if (stage1_rg_stage_input$EN)
stage1_rg_stage_input <= `BSV_ASSIGNMENT_DELAY
stage1_rg_stage_input$D_IN;
if (stage2_rg_stage2$EN)
stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
if (stage3_rg_stage3$EN)
stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
if (stageD_rg_data$EN)
stageD_rg_data <= `BSV_ASSIGNMENT_DELAY stageD_rg_data$D_IN;
if (stageF_rg_priv$EN)
stageF_rg_priv <= `BSV_ASSIGNMENT_DELAY stageF_rg_priv$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
cfg_verbosity = 4'hA;
imem_rg_cache_addr = 64'hAAAAAAAAAAAAAAAA;
imem_rg_cache_b16 = 16'hAAAA;
imem_rg_f3 = 3'h2;
imem_rg_mstatus_MXR = 1'h0;
imem_rg_pc = 64'hAAAAAAAAAAAAAAAA;
imem_rg_priv = 2'h2;
imem_rg_satp = 64'hAAAAAAAAAAAAAAAA;
imem_rg_sstatus_SUM = 1'h0;
imem_rg_tval = 64'hAAAAAAAAAAAAAAAA;
rg_csr_pc = 64'hAAAAAAAAAAAAAAAA;
rg_csr_val1 = 64'hAAAAAAAAAAAAAAAA;
rg_cur_priv = 2'h2;
rg_epoch = 2'h2;
rg_mstatus_MXR = 1'h0;
rg_next_pc = 64'hAAAAAAAAAAAAAAAA;
rg_run_on_reset = 1'h0;
rg_sstatus_SUM = 1'h0;
rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
rg_state = 4'hA;
rg_trap_info = 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_trap_instr = 32'hAAAAAAAA;
rg_trap_interrupt = 1'h0;
stage1_rg_full = 1'h0;
stage1_rg_stage_input =
402'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage2_rg_full = 1'h0;
stage2_rg_resetting = 1'h0;
stage2_rg_stage2 =
496'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage3_rg_full = 1'h0;
stage3_rg_stage3 =
239'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_data =
234'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_full = 1'h0;
stageF_rg_epoch = 2'h2;
stageF_rg_full = 1'h0;
stageF_rg_priv = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x epoch:%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_cur_priv,
csr_regfile$read_mstatus,
rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write("MStatus{",
"sd:%0d",
csr_regfile$read_mstatus[14:13] == 2'h3 ||
csr_regfile$read_mstatus[16:15] == 2'h3);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
$write(" sxl:%0d uxl:%0d", sxl__h6937, uxl__h6938);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tw:%0d", csr_regfile$read_mstatus[21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" sum:%0d", csr_regfile$read_mstatus[18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" spp:%0d", csr_regfile$read_mstatus[8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" pies:%0d_%0d%0d",
csr_regfile$read_mstatus[7],
csr_regfile$read_mstatus[5],
csr_regfile$read_mstatus[4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" ies:%0d_%0d%0d",
csr_regfile$read_mstatus[3],
csr_regfile$read_mstatus[1],
csr_regfile$read_mstatus[0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[140]))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("Rd %0d ", stage3_rg_stage3[139:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[140]))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("rd_val:%h", stage3_rg_stage3[134:71]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_stage3[69] || !stage3_rg_full ||
!stage3_rg_stage3[140]))
$write("FRd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("FRd %0d ", stage3_rg_stage3[139:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_stage3[69] || !stage3_rg_full ||
!stage3_rg_stage3[140]))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("frd_val:%h", stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage2: pc 0x%08h instr 0x%08h priv %0d",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[493:430]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Output_Stage2", " NONPIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("Output_Stage2", " PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full)
$write("Output_Stage2", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3)
$write(" fflags: %05b",
"'h%h",
x_out_data_to_stage3_fpr_flags__h8344);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215)
$write(" frd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_frd_val__h8345);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_rd_val__h8341);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8670);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", x_out_trap_info_exc_code__h8780);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8884, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8670);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", x_out_trap_info_exc_code__h8780);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8884, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279))
$write("Rd %0d ", x_out_bypass_rd__h9271);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297))
$write("rd_val:%h", x_out_bypass_rd_val__h9272);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305))
$write("FRd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310)
$write("FRd %0d ", x_out_fbypass_rd__h9453);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324)
$write("frd_val:%h", x_out_fbypass_rd_val__h9454);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage1: pc 0x%08h instr 0x%08h priv %0d",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("Output_Stage1",
" BUSY pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("Output_Stage1",
" NONPIPE: pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("Output_Stage1");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
$write("Output_Stage1", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d990)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d998)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1009)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1024)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1042)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1056)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1073)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1088)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1113)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1135)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1219)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334)
$write("CONTROL_DISCARD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("{", "CF_None");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
$write("{", "BR ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243)
$write("{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1249)
$write("JAL [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h16275,
x_out_cf_info_fallthru_PC__h16274);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1278)
$write("JALR [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h16275,
x_out_cf_info_fallthru_PC__h16274);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
if (stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432)
$write("taken ");
else
$write("fallthru ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
$write("[%h->%h %h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_fallthru_PC__h16274,
x_out_cf_info_taken_PC__h16275);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1300)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1317)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1335)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1368)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1375)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1401)
$write("OP_Stage2_FD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h10119);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h10120,
x_out_data_to_stage2_val1__h10121,
x_out_data_to_stage2_val2__h10122);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" fval1:%h fval2:%h fval3:%h}",
x_out_data_to_stage2_fval1__h10123,
alu_outputs___1_fval2__h10701,
x_out_data_to_stage2_fval3__h10125);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1588)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("'h%h", stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("'h%h", x_out_trap_info_exc_code__h15122);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("'h%h", value__h15187, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1660)
$write("\n redirect next_pc:%h", x_out_next_pc__h9864);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1664)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageD: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
stageD_rg_data[233:170],
x_out_data_to_stage1_instr__h17651,
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
stageD_rg_data[165])
$write(" instr_C:%0h", stageD_rg_data[79:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
!stageD_rg_data[165])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write(" instr:%0h pred_pc:%0h",
x_out_data_to_stage1_instr__h17651,
stageD_rg_data[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] != 4'd0 &&
stageD_rg_data[163:160] != 4'd1 &&
stageD_rg_data[163:160] != 4'd2 &&
stageD_rg_data[163:160] != 4'd3 &&
stageD_rg_data[163:160] != 4'd4 &&
stageD_rg_data[163:160] != 4'd5 &&
stageD_rg_data[163:160] != 4'd6 &&
stageD_rg_data[163:160] != 4'd7 &&
stageD_rg_data[163:160] != 4'd8 &&
stageD_rg_data[163:160] != 4'd9 &&
stageD_rg_data[163:160] != 4'd11 &&
stageD_rg_data[163:160] != 4'd12 &&
stageD_rg_data[163:160] != 4'd13 &&
stageD_rg_data[163:160] != 4'd15)
$write("unknown trap Exc_Code %d", stageD_rg_data[163:160]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" tval %0h", stageD_rg_data[159:96]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageF: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
imem_rg_pc,
d_instr__h25360,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageF");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write(" BUSY: pc:%h", imem_rg_pc);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119)
$write("data_to_StageD {pc:%h priv:%0d epoch:%0d",
imem_rg_pc,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126)
$write(" instr:%h pred_pc:%h",
d_instr__h25360,
stageF_branch_predictor$predict_rsp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2214)
$write("unknown trap Exc_Code %d", near_mem$imem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage2_nonpipe &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage2_nonpipe -> CPU_TRAP",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_trap &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$display("%0d: %m.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
csr_regfile$read_csr_mcycle,
csr_regfile$csr_trap_actions[193:130],
rg_trap_instr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
cpi__h33879,
cpifrac__h33880,
delta_CPI_cycles__h33875,
_theResult____h33877);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_trap_info[131:68],
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3946 != 4'd0)
$display(" mcause:0x%0h epc 0x%0h tval:0x%0h next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
csr_regfile$csr_trap_actions[65:2],
rg_trap_info[131:68],
rg_trap_info[63:0],
csr_regfile$csr_trap_actions[193:130],
csr_regfile$csr_trap_actions[1:0],
csr_regfile$csr_trap_actions[129:66]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h34495,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
!csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h34495,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_S_or_C",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h35329,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
!csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h35329,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_restart_after_csrrx",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3946 != 4'd0)
$display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d",
csr_regfile$csr_ret_actions[129:66],
csr_regfile$csr_ret_actions[63:0],
csr_regfile$csr_ret_actions[65:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU.rl_stage1_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_from_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_interrupt &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
if (WILL_FIRE_RL_imem_rl_assert_fail)
begin
v__h2667 = $stime;
#0;
end
v__h2661 = v__h2667 / 32'd10;
if (WILL_FIRE_RL_imem_rl_assert_fail)
$display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
v__h2661);
if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
csr_regfile$read_csr_mcycle,
soc_map$m_pc_reset_value);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
soc_map$m_pc_reset_value,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
soc_map$m_pc_reset_value,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[140] &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage3_rg_stage3[69])
$display(" S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[139:135],
stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[140] &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
!stage3_rg_stage3[69])
$display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[139:135],
stage3_rg_stage3[134:71]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write(" S3.enq: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2379)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2381)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2383)
$write(" fflags: %05b",
"'h%h",
x_out_data_to_stage3_fpr_flags__h8344);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2385)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2387)
$write(" frd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_frd_val__h8345);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2389)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_rd_val__h8341);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2395)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) &&
stage1_rg_full &&
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" rl_pipe: Discarding stage1 due to redirection");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626)
$write("OP_Stage2_FD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h10119);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h10120,
x_out_data_to_stage2_val1__h10121,
x_out_data_to_stage2_val2__h10122);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" fval1:%h fval2:%h fval3:%h}",
x_out_data_to_stage2_fval1__h10123,
alu_outputs___1_fval2__h10701,
x_out_data_to_stage2_fval3__h10125);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU_Stage1.enq: 0x%08h", stageD_rg_data[233:170]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU_StageD.enq (Data_StageF_to_StageD)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
stageF_branch_predictor$predict_rsp,
stageF_rg_epoch,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$write("CPU: Bluespec RISC-V Flute v3.0");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
end
// synopsys translate_on
endmodule // mkCPU
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fifoMux.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module fifoMux (
currEndP,
//TxFifo
TxFifoREn,
TxFifoEP0REn,
TxFifoEP1REn,
TxFifoEP2REn,
TxFifoEP3REn,
TxFifoData,
TxFifoEP0Data,
TxFifoEP1Data,
TxFifoEP2Data,
TxFifoEP3Data,
TxFifoEmpty,
TxFifoEP0Empty,
TxFifoEP1Empty,
TxFifoEP2Empty,
TxFifoEP3Empty,
//RxFifo
RxFifoWEn,
RxFifoEP0WEn,
RxFifoEP1WEn,
RxFifoEP2WEn,
RxFifoEP3WEn,
RxFifoFull,
RxFifoEP0Full,
RxFifoEP1Full,
RxFifoEP2Full,
RxFifoEP3Full
);
input [3:0] currEndP;
//TxFifo
input TxFifoREn;
output TxFifoEP0REn;
output TxFifoEP1REn;
output TxFifoEP2REn;
output TxFifoEP3REn;
output [7:0] TxFifoData;
input [7:0] TxFifoEP0Data;
input [7:0] TxFifoEP1Data;
input [7:0] TxFifoEP2Data;
input [7:0] TxFifoEP3Data;
output TxFifoEmpty;
input TxFifoEP0Empty;
input TxFifoEP1Empty;
input TxFifoEP2Empty;
input TxFifoEP3Empty;
//RxFifo
input RxFifoWEn;
output RxFifoEP0WEn;
output RxFifoEP1WEn;
output RxFifoEP2WEn;
output RxFifoEP3WEn;
output RxFifoFull;
input RxFifoEP0Full;
input RxFifoEP1Full;
input RxFifoEP2Full;
input RxFifoEP3Full;
wire [3:0] currEndP;
//TxFifo
wire TxFifoREn;
reg TxFifoEP0REn;
reg TxFifoEP1REn;
reg TxFifoEP2REn;
reg TxFifoEP3REn;
reg [7:0] TxFifoData;
wire [7:0] TxFifoEP0Data;
wire [7:0] TxFifoEP1Data;
wire [7:0] TxFifoEP2Data;
wire [7:0] TxFifoEP3Data;
reg TxFifoEmpty;
wire TxFifoEP0Empty;
wire TxFifoEP1Empty;
wire TxFifoEP2Empty;
wire TxFifoEP3Empty;
//RxFifo
wire RxFifoWEn;
reg RxFifoEP0WEn;
reg RxFifoEP1WEn;
reg RxFifoEP2WEn;
reg RxFifoEP3WEn;
reg RxFifoFull;
wire RxFifoEP0Full;
wire RxFifoEP1Full;
wire RxFifoEP2Full;
wire RxFifoEP3Full;
//internal wires and regs
//combinatorially mux TX and RX fifos for end points 0 through 3
always @(currEndP or
TxFifoREn or
RxFifoWEn or
TxFifoEP0Data or
TxFifoEP1Data or
TxFifoEP2Data or
TxFifoEP3Data or
TxFifoEP0Empty or
TxFifoEP1Empty or
TxFifoEP2Empty or
TxFifoEP3Empty or
RxFifoEP0Full or
RxFifoEP1Full or
RxFifoEP2Full or
RxFifoEP3Full)
begin
case (currEndP[1:0])
2'b00: begin
TxFifoEP0REn <= TxFifoREn;
TxFifoEP1REn <= 1'b0;
TxFifoEP2REn <= 1'b0;
TxFifoEP3REn <= 1'b0;
TxFifoData <= TxFifoEP0Data;
TxFifoEmpty <= TxFifoEP0Empty;
RxFifoEP0WEn <= RxFifoWEn;
RxFifoEP1WEn <= 1'b0;
RxFifoEP2WEn <= 1'b0;
RxFifoEP3WEn <= 1'b0;
RxFifoFull <= RxFifoEP0Full;
end
2'b01: begin
TxFifoEP0REn <= 1'b0;
TxFifoEP1REn <= TxFifoREn;
TxFifoEP2REn <= 1'b0;
TxFifoEP3REn <= 1'b0;
TxFifoData <= TxFifoEP1Data;
TxFifoEmpty <= TxFifoEP1Empty;
RxFifoEP0WEn <= 1'b0;
RxFifoEP1WEn <= RxFifoWEn;
RxFifoEP2WEn <= 1'b0;
RxFifoEP3WEn <= 1'b0;
RxFifoFull <= RxFifoEP1Full;
end
2'b10: begin
TxFifoEP0REn <= 1'b0;
TxFifoEP1REn <= 1'b0;
TxFifoEP2REn <= TxFifoREn;
TxFifoEP3REn <= 1'b0;
TxFifoData <= TxFifoEP2Data;
TxFifoEmpty <= TxFifoEP2Empty;
RxFifoEP0WEn <= 1'b0;
RxFifoEP1WEn <= 1'b0;
RxFifoEP2WEn <= RxFifoWEn;
RxFifoEP3WEn <= 1'b0;
RxFifoFull <= RxFifoEP2Full;
end
2'b11: begin
TxFifoEP0REn <= 1'b0;
TxFifoEP1REn <= 1'b0;
TxFifoEP2REn <= 1'b0;
TxFifoEP3REn <= TxFifoREn;
TxFifoData <= TxFifoEP3Data;
TxFifoEmpty <= TxFifoEP3Empty;
RxFifoEP0WEn <= 1'b0;
RxFifoEP1WEn <= 1'b0;
RxFifoEP2WEn <= 1'b0;
RxFifoEP3WEn <= RxFifoWEn;
RxFifoFull <= RxFifoEP3Full;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRBP_BLACKBOX_V
|
`timescale 1 ns / 1 ps
module axis_ram_writer #
(
parameter integer ADDR_WIDTH = 20,
parameter integer AXI_ID_WIDTH = 6,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 64,
parameter integer AXIS_TDATA_WIDTH = 64
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [AXI_ADDR_WIDTH-1:0] cfg_data,
output wire [ADDR_WIDTH-1:0] sts_data,
// Master side
output wire [AXI_ID_WIDTH-1:0] m_axi_awid, // AXI master: Write address ID
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, // AXI master: Write address
output wire [3:0] m_axi_awlen, // AXI master: Write burst length
output wire [2:0] m_axi_awsize, // AXI master: Write burst size
output wire [1:0] m_axi_awburst, // AXI master: Write burst type
output wire [3:0] m_axi_awcache, // AXI master: Write memory type
output wire m_axi_awvalid, // AXI master: Write address valid
input wire m_axi_awready, // AXI master: Write address ready
output wire [AXI_ID_WIDTH-1:0] m_axi_wid, // AXI master: Write data ID
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, // AXI master: Write data
output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, // AXI master: Write strobes
output wire m_axi_wlast, // AXI master: Write last
output wire m_axi_wvalid, // AXI master: Write valid
input wire m_axi_wready, // AXI master: Write ready
output wire m_axi_bready, // AXI master: Write response ready
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_SIZE = clogb2((AXI_DATA_WIDTH/8)-1);
reg int_awvalid_reg, int_awvalid_next;
reg int_wvalid_reg, int_wvalid_next;
reg [ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [AXI_ID_WIDTH-1:0] int_wid_reg, int_wid_next;
wire int_full_wire, int_empty_wire, int_rden_wire;
wire int_wlast_wire, int_tready_wire;
wire [71:0] int_wdata_wire;
assign int_tready_wire = ~int_full_wire;
assign int_wlast_wire = &int_addr_reg[3:0];
assign int_rden_wire = m_axi_wready & int_wvalid_reg;
FIFO36E1 #(
.FIRST_WORD_FALL_THROUGH("TRUE"),
.ALMOST_EMPTY_OFFSET(13'hf),
.DATA_WIDTH(72),
.FIFO_MODE("FIFO36_72")
) fifo_0 (
.FULL(int_full_wire),
.ALMOSTEMPTY(int_empty_wire),
.RST(~aresetn),
.WRCLK(aclk),
.WREN(int_tready_wire & s_axis_tvalid),
.DI({{(72-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata}),
.RDCLK(aclk),
.RDEN(m_axi_wready & int_wvalid_reg),
.DO(int_wdata_wire)
);
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awvalid_reg <= 1'b0;
int_wvalid_reg <= 1'b0;
int_addr_reg <= {(ADDR_WIDTH){1'b0}};
int_wid_reg <= {(AXI_ID_WIDTH){1'b0}};
end
else
begin
int_awvalid_reg <= int_awvalid_next;
int_wvalid_reg <= int_wvalid_next;
int_addr_reg <= int_addr_next;
int_wid_reg <= int_wid_next;
end
end
always @*
begin
int_awvalid_next = int_awvalid_reg;
int_wvalid_next = int_wvalid_reg;
int_addr_next = int_addr_reg;
int_wid_next = int_wid_reg;
if(~int_empty_wire & ~int_awvalid_reg & ~int_wvalid_reg)
begin
int_awvalid_next = 1'b1;
int_wvalid_next = 1'b1;
end
if(m_axi_awready & int_awvalid_reg)
begin
int_awvalid_next = 1'b0;
end
if(int_rden_wire)
begin
int_addr_next = int_addr_reg + 1'b1;
end
if(m_axi_wready & int_wlast_wire)
begin
int_wid_next = int_wid_reg + 1'b1;
if(int_empty_wire)
begin
int_wvalid_next = 1'b0;
end
else
begin
int_awvalid_next = 1'b1;
end
end
end
assign sts_data = int_addr_reg;
assign m_axi_awid = int_wid_reg;
assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1'b0}}};
assign m_axi_awlen = 4'd15;
assign m_axi_awsize = ADDR_SIZE;
assign m_axi_awburst = 2'b01;
assign m_axi_awcache = 4'b0011;
assign m_axi_awvalid = int_awvalid_reg;
assign m_axi_wid = int_wid_reg;
assign m_axi_wdata = int_wdata_wire[AXI_DATA_WIDTH-1:0];
assign m_axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
assign m_axi_wlast = int_wlast_wire;
assign m_axi_wvalid = int_wvalid_reg;
assign m_axi_bready = 1'b1;
assign s_axis_tready = int_tready_wire;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_M_V
`define SKY130_FD_SC_LP__A221O_M_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_m (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_m (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_M_V
|
module op();
localparam ADD = 'b000;
localparam AND = 'b001;
localparam NAND = 'b010;
localparam OR = 'b011;
localparam XOR = 'b100;
localparam SGT = 'b101;
localparam SLL = 'b110;
localparam SRL = 'b111;
endmodule
module reg_file
#(parameter d_width = 32, reg_ct = 32, ra_width = $clog2(reg_ct) )
( output reg[d_width-1:0] ra, rb,
input [d_width-1:0] rd,
input [ra_width-1:0] addr_a, addr_b, addr_d,
input clk);
reg [d_width-1:0] regs[reg_ct-1:0];
always @(negedge clk) begin
regs[addr_d] <= rd;
end
always @(posedge clk) begin
ra <= regs[addr_a];
rb <= regs[addr_b];
end
endmodule
module alu #(parameter d_width = 32, op_width = 3)
( output reg [d_width-1:0]res,
input [d_width-1:0]ra, rb,
input [op_width-1:0]aop);
always @(ra,rb,aop)
(* full_case, parallel_case *)
case (aop)
op.ADD : res <= ra + rb;
op.AND : res <= ra & rb;
op.NAND: res <= ra ~& rb;
op.OR : res <= ra | rb;
op.XOR : res <= ra ^ rb;
op.SGT : res <= (ra > rb) ? 1 : 0;
endcase
endmodule
module shifter #(parameter d_width = 32, ra_width = 5)
( output reg [d_width-1:0]res,
input [d_width-1:0] rin,
input [ra_width-1:0] shift,
input dir);
always @(dir, shift, rin)
if (~dir)
res <= (rin << shift);
else
res <= (rin >> shift);
endmodule
module control #(parameter d_width = 32, reg_ct = 32,
ra_width = $clog2(reg_ct), op_width = 3)
( output reg[op_width-1:0] alu_op,
output reg shift_dir, select_alu,
input [op_width-1:0] opcode,
input clk
);
always @(posedge clk) begin
alu_op <= opcode;
select_alu <= ( opcode == op.SLL
|| opcode == op.SRL ) ? 0 : 1;
shift_dir <= opcode[0];
end
endmodule
module mux_out #(parameter d_width = 32)
( output reg[d_width-1:0]out,
input [d_width-1:0]a, b,
input sel);
always @(a,b,sel) begin
if (sel)
out <= a;
else
out <= b;
end
endmodule
module cpu #(parameter d_width = 32, reg_ct = 32,
op_width = 3, ra_width = $clog2(reg_ct),
ins_width = op_width + ra_width + ra_width + ra_width)
( input [ins_width-1:0]ins,
input clk
);
localparam opc_end = ins_width - op_width;
localparam ar_d_end = opc_end - ra_width;
localparam ar1_end = ar_d_end - ra_width;
localparam ar2_end = ar1_end - ra_width; /* must be zero */
wire [op_width-1:0] alu_op;
wire [op_width-1:0] opcode = ins[ins_width-1:opc_end];
wire s_alu, shift_dir;
wire [ra_width-1:0]
ar1 = ins[ar_d_end-1:ar1_end],
ar2 = ins[ar1_end-1:ar2_end],
ar_dest = ins[opc_end-1:ar_d_end];
wire [d_width-1:0] r1, r2;
wire [d_width-1:0] shift_res, alu_res;
wire [d_width-1:0] result;
mux_out #(.d_width(d_width))
muxo (.out(result), .a(alu_res), .b(shift_res), .sel(s_alu));
control #(.ra_width(ra_width), .d_width(d_width), .reg_ct(reg_ct),
.op_width(op_width))
ctrl(.alu_op(alu_op), .select_alu(s_alu), .opcode(opcode),
.shift_dir(shift_dir), .clk(clk));
shifter #(.ra_width(ra_width), .d_width(d_width))
sh(.res(shift_res), .rin(r1), .shift(ar2), .dir(shift_dir));
alu #(.op_width(op_width), .d_width(d_width))
alui(.res(alu_res), .ra(r1), .rb(r2), .aop(alu_op));
reg_file #(.ra_width(ra_width), .d_width(d_width), .reg_ct(reg_ct))
regs(.ra(r1), .rb(r2), .rd(result), .addr_a(ar1),
.addr_b(ar2), .addr_d(ar_dest), .clk(clk));
endmodule
module tb();
reg [17:0] ins;
reg clk;
cpu cpu1(ins, clk);
task setr;
input [3:0]ra;
input [31:0] rv;
begin
cpu1.regs.regs[ra] = rv;
end
endtask
task pregs;
integer i;
begin
$display("regs:");
for(i = 0; i < 32; i = i + 1) begin
$display("\t%d:%d",i, cpu1.regs.regs[i]);
end
end
endtask
task proc;
input [17:0]cins;
reg [3:0] op;
reg [4:0] rdest;
reg [4:0] rs1;
reg [4:0] rs2;
begin
op = cins[17:15];
rdest = cins[14:10];
rs1 = cins[9:5];
rs2 = cins[4:0];
ins = cins;
#10 clk = 1;
#10 clk = 0;
#10;
$display("op: %3b; rs1(%2d): %d; rs2(%2d): %d; rdest(%2d): %d",
op, rs1, cpu1.regs.regs[rs1], rs2,
cpu1.regs.regs[rs2], rdest,
cpu1.regs.regs[rdest]);
end
endtask
initial begin
clk = 0;
setr(1, 5);
setr(2, 6);
/* add %0, %2, %1 # %0 = %1 + %2 */
proc('b000_00000_00010_00001);
/* XOR %3, %2 %1 # %3 = %0 ^ %2 */
proc('b100_00011_00010_00001);
/* sll %4, %3, 5 # %4 = %3 << 5 */
proc('b110_00100_00011_00101);
/* slr %5, %4, 4 # %5 = %4 << 4 */
proc('b111_00101_00100_00100);
/* sgt %6, %5, %4 # %6 = %5 > %4 */
proc('b101_00110_00101_00100);
/* sgt %6, %4, %5 # %6 = %4 > %5 */
proc('b101_00110_00100_00101);
/* nand %7, %6, %5 # %7 = %6 ~& %5 */
proc('b010_00111_00110_00101);
/* or %8, %6, %5 # %8 = %6 | %5 */
proc('b011_01000_00110_00101);
/* and %25, %8, %5 # %25 = %8 & %5 */
proc('b001_11001_01000_00101);
pregs();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_BLACKBOX_V
`define SKY130_FD_SC_HS__O41A_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_TB_V
`define SKY130_FD_SC_MS__SEDFXTP_TB_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sedfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sedfxtp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFSTP_PP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfstp (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
`define WAITING_FOR_ICT 6'b000001
`define WAITING_FOR_P0 6'b000010
`define WAITING_FOR_P1 6'b000100
`define WAITING_FOR_P2 6'b001000
`define WAITING_FOR_P3 6'b010000
`define WAITING_FOR_CMD 6'b100000
module rx_DS_char(
input rxClk,
input rxReset,
input [1:0] d,
input dValid,
output [7:0] q,
output nchar,
output lchar,
output parityError
);
reg nchar, nnchar;
reg lchar, nlchar;
reg parityError;
always @(posedge rxClk) begin
if(rxReset) begin
nchar <= 0;
lchar <= 0;
end
else begin
nchar <= nnchar;
lchar <= nlchar;
end
end
reg [5:0] state;
reg [5:0] nstate;
always @(posedge rxClk) begin
if (rxReset) begin
state <= `WAITING_FOR_ICT;
end
else begin
state <= nstate;
end
end
reg [1:0] qp0, qp1, qp2, qp3;
reg bits01, bits23, bits45, bits67;
assign q = {qp3, qp2, qp1, qp0};
always @(posedge rxClk) begin
if(rxReset) begin
qp0 <= 0;
qp1 <= 0;
qp2 <= 0;
qp3 <= 0;
end
else begin
if(bits01) begin
qp0 <= d;
end
if(bits23) begin
qp1 <= d;
end
if(bits45) begin
qp2 <= d;
end
if(bits67) begin
qp3 <= d;
end
end
end
reg [1:0] parityPair;
reg zeroParity, accumulateParity;
always @(posedge rxClk) begin
if(rxReset | zeroParity) begin
parityPair = 0;
end
else begin
if(accumulateParity) begin
parityPair = parityPair ^ d;
end
end
end
wire paritySoFar = ^(d ^ parityPair);
reg parityErrorDetect;
always @(posedge rxClk) begin
if(rxReset) begin
parityError <= 0;
end
else begin
parityError <= parityError | parityErrorDetect;
end
end
always @(*) begin
nstate = state;
bits01 = 0;
bits23 = 0;
bits45 = 0;
bits67 = 0;
nlchar = 0;
nnchar = 0;
zeroParity = 0;
accumulateParity = 0;
parityErrorDetect = 0;
if(dValid && (state == `WAITING_FOR_ICT)) begin
if(d[1] == 1'b0) begin
nstate = `WAITING_FOR_P0;
end
else begin
nstate = `WAITING_FOR_CMD;
end
parityErrorDetect = ~paritySoFar;
zeroParity = 1;
end
if(dValid && (state == `WAITING_FOR_CMD)) begin
bits01 = 1;
nstate = `WAITING_FOR_ICT;
nlchar = 1;
accumulateParity = 1;
end
if(dValid && (state == `WAITING_FOR_P0)) begin
bits01 = 1;
nstate = `WAITING_FOR_P1;
accumulateParity = 1;
end
if(dValid && (state == `WAITING_FOR_P1)) begin
bits23 = 1;
nstate = `WAITING_FOR_P2;
accumulateParity = 1;
end
if(dValid && (state == `WAITING_FOR_P2)) begin
bits45 = 1;
nstate = `WAITING_FOR_P3;
accumulateParity = 1;
end
if(dValid && (state == `WAITING_FOR_P3)) begin
bits67 = 1;
nstate = `WAITING_FOR_ICT;
nnchar = 1;
accumulateParity = 1;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_16k.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_16k.v //
// Description : Implements 16 KB Dual Ported Memory //
// - Output Regs are always enabled //
// - if NO_DECODE_LOGIC = TRUE -> 8xRAMB18E1 in TDP mode //
// - if INTERFACE_SPEED = 500 MHz -> 8xRAMB18E1 in TDP mode //
// - if INTERFACE_SPEED = 250 MHz -> 4xRAMB36E1 in SDP mode //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_16k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_16k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
)
(
input clk_i, // user clock
input reset_i, // bram reset
input [9:0] waddr0_i, // write address
input [9:0] waddr1_i, // write address
input [9:0] waddr2_i, // write address
input [9:0] waddr3_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input [7:0] wen_i, // write enable
input [9:0] raddr0_i, // write address
input [9:0] raddr1_i, // write address
input [9:0] raddr2_i, // write address
input [9:0] raddr3_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input [7:0] ren_i // read enable
);
// Local Params
localparam TCQ = 1;
genvar i;
wire [79:0] waddr;
wire [79:0] raddr;
wire [7:0] wen;
wire [7:0] ren;
wire [255:0] rdata_w;
wire [31:0] rdop_w;
wire [255:0] wdata_w;
wire [31:0] wdip_w;
reg raddr0_q = 1'b0;
reg raddr0_qq = 1'b0;
assign wen = {wen_i[7], wen_i[6], wen_i[5], wen_i[4], wen_i[3], wen_i[2], wen_i[1], wen_i[0]};
assign ren = {ren_i[7], ren_i[6], ren_i[5], ren_i[4], ren_i[3], ren_i[2], ren_i[1], ren_i[0]};
generate
if ((INTERFACE_SPEED == "500 MHZ") || (NO_DECODE_LOGIC == "TRUE")) begin : SPEED_500MHz_OR_NO_DECODE_LOGIC
assign waddr = {waddr3_i, waddr3_i, waddr2_i, waddr2_i, waddr1_i, waddr1_i, waddr0_i, waddr0_i};
assign raddr = {raddr3_i, raddr3_i, raddr2_i, raddr2_i, raddr1_i, raddr1_i, raddr0_i, raddr0_i};
for (i = 0; i < 8; i = i + 1) begin : RAMB18E1
RAMB18E1 #(
.SIM_DEVICE ("7SERIES"),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.SRVAL_A ( 18'h00000 ),
.INIT_FILE ( "NONE" ),
.RAM_MODE ( "TDP" ),
.READ_WIDTH_A ( 18 ),
.READ_WIDTH_B ( 18 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.INIT_A ( 18'h00000 ),
.INIT_B ( 18'h00000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 18 ),
.WRITE_WIDTH_B ( 18 ),
.SRVAL_B ( 18'h00000 ))
u_fifo (
.CLKARDCLK(clk_i),
.CLKBWRCLK(clk_i),
.ENARDEN(1'b1),
.ENBWREN(ren[i]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1 ),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.ADDRARDADDR({waddr[(10*i)+9:(10*i)+0], 4'b0}),
.ADDRBWRADDR({raddr[(10*i)+9:(10*i)+0], 4'b0}),
.DIADI(wdata_i[(16*i)+15:(16*i)+0]),
.DIPADIP(wdip_i[(2*i)+1:(2*i)+0]),
.DIBDI({16'b0}),
.DIPBDIP(2'b0),
.DOADO(),
.DOBDO(rdata_o[(16*i)+15:(16*i)+0]),
.DOPADOP(),
.DOPBDOP(rdop_o[(2*i)+1:(2*i)+0]),
.WEA({wen[i], wen[i]}),
.WEBWE({1'b0, 1'b0, 1'b0, 1'b0})
);
end
end else begin : SPEED_250MHz
always @(posedge clk_i) begin
if (reset_i) begin
raddr0_q <= #(TCQ) 1'b0;
raddr0_qq <= #(TCQ) 1'b0;
end else begin
raddr0_q <= #(TCQ) raddr0_i[9];
raddr0_qq <= #(TCQ) raddr0_q;
end
end
assign rdata_o = raddr0_qq ? rdata_w[255:128] : rdata_w[127:0];
assign rdop_o = raddr0_qq ? rdop_w[31:16] : rdop_w[15:0];
assign wdata_w = {wdata_i, wdata_i};
assign wdip_w = {wdip_i, wdip_i};
assign waddr = {44'b0, waddr0_i[8:0], waddr1_i[8:0], waddr2_i[8:0], waddr3_i[8:0]};
assign raddr = {44'b0, raddr0_i[8:0], raddr1_i[8:0], raddr2_i[8:0], raddr3_i[8:0]};
for (i = 0; i < 4; i = i + 1) begin : RAMB36E1
RAMB36E1 #(
.SIM_DEVICE ("7SERIES"),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.INIT_FILE ( "NONE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.RAM_MODE ( "SDP" ),
.RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
.READ_WIDTH_A ( 72 ),
.READ_WIDTH_B ( 0 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 0 ),
.WRITE_WIDTH_B ( 72 )
)
u_fifo (
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA( ),
.CASCADEOUTB( ),
.CLKARDCLK(clk_i),
.CLKBWRCLK(clk_i),
.DBITERR( ),
.ENARDEN(((i > 1) ? (raddr0_i[9] & ren[2*i]) : (~raddr0_i[9] & ren[2*i]))),
.ENBWREN(1'b1 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.REGCEAREGCE(1'b1 ),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR( ),
.ADDRARDADDR({1'b1 , raddr[(9*i)+8:(9*i)+0], 6'b0}),
.ADDRBWRADDR({1'b1 , waddr[(9*i)+8:(9*i)+0], 6'b0}),
.DIADI(wdata_w[(2*32*i)+31:(2*32*i)+0]),
.DIBDI(wdata_w[(2*32*i)+63:(2*32*i)+32]),
.DIPADIP(wdip_w[(2*4*i)+3:(2*4*i)+0]),
.DIPBDIP(wdip_w[(2*4*i)+7:(2*4*i)+4]),
.DOADO(rdata_w[(2*32*i)+31:(2*32*i)+0]),
.DOBDO(rdata_w[(2*32*i)+63:(2*32*i)+32]),
.DOPADOP(rdop_w[(2*4*i)+3:(2*4*i)+0]),
.DOPBDOP(rdop_w[(2*4*i)+7:(2*4*i)+4]),
.ECCPARITY(),
.RDADDRECC(),
.WEA(4'b0),
.WEBWE({8{((i > 1) ? (waddr0_i[9] & wen[2*i]) : (~waddr0_i[9] & wen[2*i]))}})
);
end
end
endgenerate
endmodule // pcie_bram_7vx_16k
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_PP_SYMBOL_V
`define SKY130_FD_SC_HS__OR4_PP_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_PP_SYMBOL_V
|
//
// Copyright (c) 2015 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module pdp1_opr_decoder(op_i, op_mask, op_ac, op_io,
op_pf, op_tw, op_r_ac, op_r_io, op_r_pf);
parameter pdp_model = "PDP-1";
input op_i;
input [0:11] op_mask;
input [0:17] op_ac;
input [0:17] op_io;
input [0:5] op_pf;
input [0:17] op_tw;
output [0:17] op_r_ac;
output [0:17] op_r_io;
output [0:5] op_r_pf;
wire [0:18] w_ac_immed1;
wire [0:18] w_ac_immed2;
wire [0:18] w_ac_immed3;
wire [0:18] w_ac_immed4;
wire [0:18] w_io_immed1;
reg [0:5] r_pf_mask;
assign w_ac_immed4 = (op_mask[4]) ? 18'b0 : op_ac;
assign w_ac_immed3 = (op_mask[1]) ? (w_ac_immed4 | op_tw) : w_ac_immed4;
assign w_ac_immed2 = (op_mask[5]) ? (w_ac_immed3 | op_pf) : w_ac_immed3;
assign w_ac_immed1 = (op_mask[2]) ? ~w_ac_immed2 : w_ac_immed2;
assign w_io_immed1 = (op_mask[0]) ? 18'b0 : op_io;
generate
if(pdp_model == "PDP-1D") begin
assign w_io_immed1 = (op_i) ? ~w_io_immed2 : w_io_immed2;
assign op_r_ac = (op_mask[6]) ? w_io_immed1 : w_ac_immed1;
assign op_r_io = (op_mask[7]) ? w_ac_immed1 : w_io_immed1;
end
else begin
assign op_r_io = w_io_immed1;
assign op_r_ac = w_ac_immed1;
end
endgenerate
assign op_r_pf = (|op_mask[8:11]) ?
((op_mask[8]) ? op_pf | r_pf_mask :
op_pf & ~r_pf_mask) :
op_pf;
always @(op_mask or op_pf) begin
case(op_mask[9:11])
3'b000:
r_pf_mask = 6'b000000;
3'b001:
r_pf_mask = 6'b000001;
3'b010:
r_pf_mask = 6'b000010;
3'b011:
r_pf_mask = 6'b000100;
3'b100:
r_pf_mask = 6'b001000;
3'b101:
r_pf_mask = 6'b010000;
3'b110:
r_pf_mask = 6'b100000;
3'b111:
r_pf_mask = 6'b111111;
endcase // case (op_mask[9:11])
end
endmodule // pdp1_opr_decoder
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_2_V
`define SKY130_FD_SC_LP__A21BOI_2_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_TB_V
`define SKY130_FD_SC_LS__FA_TB_V
/**
* fa: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fa.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_TB_V
`define SKY130_FD_SC_LS__AND2B_TB_V
/**
* and2b: 2-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_ls__and2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_TB_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:10 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_sim_netlist.v
// Design : ip_design_nco_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_nco_0_0,nco,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "nco,Vivado 2017.3" *)
(* hls_module = "yes" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
ap_clk,
ap_rst_n);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWADDR" *) input [5:0]s_axi_AXILiteS_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWVALID" *) input s_axi_AXILiteS_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWREADY" *) output s_axi_AXILiteS_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WDATA" *) input [31:0]s_axi_AXILiteS_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WSTRB" *) input [3:0]s_axi_AXILiteS_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WVALID" *) input s_axi_AXILiteS_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WREADY" *) output s_axi_AXILiteS_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BRESP" *) output [1:0]s_axi_AXILiteS_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BVALID" *) output s_axi_AXILiteS_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BREADY" *) input s_axi_AXILiteS_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARADDR" *) input [5:0]s_axi_AXILiteS_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARVALID" *) input s_axi_AXILiteS_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARREADY" *) output s_axi_AXILiteS_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RDATA" *) output [31:0]s_axi_AXILiteS_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RRESP" *) output [1:0]s_axi_AXILiteS_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RVALID" *) output s_axi_AXILiteS_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_AXILiteS, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_AXILiteS_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_AXILiteS, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input ap_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input ap_rst_n;
wire ap_clk;
wire ap_rst_n;
wire [5:0]s_axi_AXILiteS_ARADDR;
wire s_axi_AXILiteS_ARREADY;
wire s_axi_AXILiteS_ARVALID;
wire [5:0]s_axi_AXILiteS_AWADDR;
wire s_axi_AXILiteS_AWREADY;
wire s_axi_AXILiteS_AWVALID;
wire s_axi_AXILiteS_BREADY;
wire [1:0]s_axi_AXILiteS_BRESP;
wire s_axi_AXILiteS_BVALID;
wire [31:0]s_axi_AXILiteS_RDATA;
wire s_axi_AXILiteS_RREADY;
wire [1:0]s_axi_AXILiteS_RRESP;
wire s_axi_AXILiteS_RVALID;
wire [31:0]s_axi_AXILiteS_WDATA;
wire s_axi_AXILiteS_WREADY;
wire [3:0]s_axi_AXILiteS_WSTRB;
wire s_axi_AXILiteS_WVALID;
(* C_S_AXI_AXILITES_ADDR_WIDTH = "6" *)
(* C_S_AXI_AXILITES_DATA_WIDTH = "32" *)
(* C_S_AXI_AXILITES_WSTRB_WIDTH = "4" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_WSTRB_WIDTH = "4" *)
(* ap_ST_st1_fsm_0 = "2'b01" *)
(* ap_ST_st2_fsm_1 = "2'b10" *)
(* ap_const_int64_8 = "8" *)
(* ap_const_logic_0 = "1'b0" *)
(* ap_const_logic_1 = "1'b1" *)
(* ap_const_lv1_1 = "1'b1" *)
(* ap_const_lv32_0 = "0" *)
(* ap_const_lv32_1 = "1" *)
(* ap_const_lv32_4 = "4" *)
(* ap_const_lv32_F = "15" *)
(* ap_true = "1'b1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco inst
(.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.s_axi_AXILiteS_ARADDR(s_axi_AXILiteS_ARADDR),
.s_axi_AXILiteS_ARREADY(s_axi_AXILiteS_ARREADY),
.s_axi_AXILiteS_ARVALID(s_axi_AXILiteS_ARVALID),
.s_axi_AXILiteS_AWADDR(s_axi_AXILiteS_AWADDR),
.s_axi_AXILiteS_AWREADY(s_axi_AXILiteS_AWREADY),
.s_axi_AXILiteS_AWVALID(s_axi_AXILiteS_AWVALID),
.s_axi_AXILiteS_BREADY(s_axi_AXILiteS_BREADY),
.s_axi_AXILiteS_BRESP(s_axi_AXILiteS_BRESP),
.s_axi_AXILiteS_BVALID(s_axi_AXILiteS_BVALID),
.s_axi_AXILiteS_RDATA(s_axi_AXILiteS_RDATA),
.s_axi_AXILiteS_RREADY(s_axi_AXILiteS_RREADY),
.s_axi_AXILiteS_RRESP(s_axi_AXILiteS_RRESP),
.s_axi_AXILiteS_RVALID(s_axi_AXILiteS_RVALID),
.s_axi_AXILiteS_WDATA(s_axi_AXILiteS_WDATA),
.s_axi_AXILiteS_WREADY(s_axi_AXILiteS_WREADY),
.s_axi_AXILiteS_WSTRB(s_axi_AXILiteS_WSTRB),
.s_axi_AXILiteS_WVALID(s_axi_AXILiteS_WVALID));
endmodule
(* C_S_AXI_AXILITES_ADDR_WIDTH = "6" *) (* C_S_AXI_AXILITES_DATA_WIDTH = "32" *) (* C_S_AXI_AXILITES_WSTRB_WIDTH = "4" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_WSTRB_WIDTH = "4" *) (* ap_ST_st1_fsm_0 = "2'b01" *)
(* ap_ST_st2_fsm_1 = "2'b10" *) (* ap_const_int64_8 = "8" *) (* ap_const_logic_0 = "1'b0" *)
(* ap_const_logic_1 = "1'b1" *) (* ap_const_lv1_1 = "1'b1" *) (* ap_const_lv32_0 = "0" *)
(* ap_const_lv32_1 = "1" *) (* ap_const_lv32_4 = "4" *) (* ap_const_lv32_F = "15" *)
(* ap_true = "1'b1" *) (* hls_module = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco
(s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
ap_clk,
ap_rst_n);
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [5:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [31:0]s_axi_AXILiteS_WDATA;
input [3:0]s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [5:0]s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [31:0]s_axi_AXILiteS_RDATA;
output [1:0]s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0]s_axi_AXILiteS_BRESP;
input ap_clk;
input ap_rst_n;
wire \<const0> ;
wire [1:1]ap_NS_fsm;
wire ap_clk;
wire ap_rst_n;
wire ap_rst_n_inv;
wire ap_sig_bdd_66;
wire ap_sig_bdd_79;
wire [15:0]int_sine_sample_V;
wire nco_AXILiteS_s_axi_U_n_10;
wire nco_AXILiteS_s_axi_U_n_11;
wire nco_AXILiteS_s_axi_U_n_12;
wire nco_AXILiteS_s_axi_U_n_13;
wire nco_AXILiteS_s_axi_U_n_14;
wire nco_AXILiteS_s_axi_U_n_15;
wire nco_AXILiteS_s_axi_U_n_16;
wire nco_AXILiteS_s_axi_U_n_17;
wire nco_AXILiteS_s_axi_U_n_18;
wire nco_AXILiteS_s_axi_U_n_3;
wire nco_AXILiteS_s_axi_U_n_4;
wire nco_AXILiteS_s_axi_U_n_5;
wire nco_AXILiteS_s_axi_U_n_6;
wire nco_AXILiteS_s_axi_U_n_7;
wire nco_AXILiteS_s_axi_U_n_8;
wire nco_AXILiteS_s_axi_U_n_9;
wire [5:0]s_axi_AXILiteS_ARADDR;
wire s_axi_AXILiteS_ARREADY;
wire s_axi_AXILiteS_ARVALID;
wire [5:0]s_axi_AXILiteS_AWADDR;
wire s_axi_AXILiteS_AWREADY;
wire s_axi_AXILiteS_AWVALID;
wire s_axi_AXILiteS_BREADY;
wire s_axi_AXILiteS_BVALID;
wire [15:0]\^s_axi_AXILiteS_RDATA ;
wire s_axi_AXILiteS_RREADY;
wire s_axi_AXILiteS_RVALID;
wire [31:0]s_axi_AXILiteS_WDATA;
wire s_axi_AXILiteS_WREADY;
wire [3:0]s_axi_AXILiteS_WSTRB;
wire s_axi_AXILiteS_WVALID;
wire [11:0]sel;
wire [15:0]temp_V_reg;
assign s_axi_AXILiteS_BRESP[1] = \<const0> ;
assign s_axi_AXILiteS_BRESP[0] = \<const0> ;
assign s_axi_AXILiteS_RDATA[31] = \<const0> ;
assign s_axi_AXILiteS_RDATA[30] = \<const0> ;
assign s_axi_AXILiteS_RDATA[29] = \<const0> ;
assign s_axi_AXILiteS_RDATA[28] = \<const0> ;
assign s_axi_AXILiteS_RDATA[27] = \<const0> ;
assign s_axi_AXILiteS_RDATA[26] = \<const0> ;
assign s_axi_AXILiteS_RDATA[25] = \<const0> ;
assign s_axi_AXILiteS_RDATA[24] = \<const0> ;
assign s_axi_AXILiteS_RDATA[23] = \<const0> ;
assign s_axi_AXILiteS_RDATA[22] = \<const0> ;
assign s_axi_AXILiteS_RDATA[21] = \<const0> ;
assign s_axi_AXILiteS_RDATA[20] = \<const0> ;
assign s_axi_AXILiteS_RDATA[19] = \<const0> ;
assign s_axi_AXILiteS_RDATA[18] = \<const0> ;
assign s_axi_AXILiteS_RDATA[17] = \<const0> ;
assign s_axi_AXILiteS_RDATA[16] = \<const0> ;
assign s_axi_AXILiteS_RDATA[15:0] = \^s_axi_AXILiteS_RDATA [15:0];
assign s_axi_AXILiteS_RRESP[1] = \<const0> ;
assign s_axi_AXILiteS_RRESP[0] = \<const0> ;
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\ap_CS_fsm[1]_i_1
(.I0(ap_sig_bdd_79),
.O(ap_NS_fsm));
(* FSM_ENCODING = "none" *)
FDSE #(
.INIT(1'b1))
\ap_CS_fsm_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(ap_sig_bdd_79),
.Q(ap_sig_bdd_66),
.S(ap_rst_n_inv));
(* FSM_ENCODING = "none" *)
FDRE #(
.INIT(1'b0))
\ap_CS_fsm_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(ap_NS_fsm),
.Q(ap_sig_bdd_79),
.R(ap_rst_n_inv));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi nco_AXILiteS_s_axi_U
(.O({nco_AXILiteS_s_axi_U_n_3,nco_AXILiteS_s_axi_U_n_4,nco_AXILiteS_s_axi_U_n_5,nco_AXILiteS_s_axi_U_n_6}),
.Q(ap_sig_bdd_79),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.ap_rst_n_inv(ap_rst_n_inv),
.out(int_sine_sample_V),
.s_axi_AXILiteS_ARADDR(s_axi_AXILiteS_ARADDR[4:0]),
.s_axi_AXILiteS_ARREADY(s_axi_AXILiteS_ARREADY),
.s_axi_AXILiteS_ARVALID(s_axi_AXILiteS_ARVALID),
.s_axi_AXILiteS_AWADDR(s_axi_AXILiteS_AWADDR[4:0]),
.s_axi_AXILiteS_AWREADY(s_axi_AXILiteS_AWREADY),
.s_axi_AXILiteS_AWVALID(s_axi_AXILiteS_AWVALID),
.s_axi_AXILiteS_BREADY(s_axi_AXILiteS_BREADY),
.s_axi_AXILiteS_BVALID(s_axi_AXILiteS_BVALID),
.s_axi_AXILiteS_RDATA(\^s_axi_AXILiteS_RDATA ),
.s_axi_AXILiteS_RREADY(s_axi_AXILiteS_RREADY),
.s_axi_AXILiteS_RVALID(s_axi_AXILiteS_RVALID),
.s_axi_AXILiteS_WDATA(s_axi_AXILiteS_WDATA[15:0]),
.s_axi_AXILiteS_WREADY(s_axi_AXILiteS_WREADY),
.s_axi_AXILiteS_WSTRB(s_axi_AXILiteS_WSTRB[1:0]),
.s_axi_AXILiteS_WVALID(s_axi_AXILiteS_WVALID),
.sel(sel),
.temp_V_reg(temp_V_reg),
.\temp_V_reg[11] ({nco_AXILiteS_s_axi_U_n_11,nco_AXILiteS_s_axi_U_n_12,nco_AXILiteS_s_axi_U_n_13,nco_AXILiteS_s_axi_U_n_14}),
.\temp_V_reg[15] ({nco_AXILiteS_s_axi_U_n_15,nco_AXILiteS_s_axi_U_n_16,nco_AXILiteS_s_axi_U_n_17,nco_AXILiteS_s_axi_U_n_18}),
.\temp_V_reg[7] ({nco_AXILiteS_s_axi_U_n_7,nco_AXILiteS_s_axi_U_n_8,nco_AXILiteS_s_axi_U_n_9,nco_AXILiteS_s_axi_U_n_10}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V sine_lut_V_U
(.Q({ap_sig_bdd_79,ap_sig_bdd_66}),
.SR(ap_rst_n_inv),
.ap_clk(ap_clk),
.out(int_sine_sample_V),
.sel(sel));
FDRE #(
.INIT(1'b0))
\temp_V_reg[0]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_6),
.Q(temp_V_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[10]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_12),
.Q(temp_V_reg[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[11]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_11),
.Q(temp_V_reg[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[12]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_18),
.Q(temp_V_reg[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[13]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_17),
.Q(temp_V_reg[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[14]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_16),
.Q(temp_V_reg[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[15]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_15),
.Q(temp_V_reg[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[1]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_5),
.Q(temp_V_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[2]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_4),
.Q(temp_V_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[3]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_3),
.Q(temp_V_reg[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[4]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_10),
.Q(temp_V_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[5]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_9),
.Q(temp_V_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[6]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_8),
.Q(temp_V_reg[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[7]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_7),
.Q(temp_V_reg[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[8]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_14),
.Q(temp_V_reg[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_V_reg[9]
(.C(ap_clk),
.CE(ap_sig_bdd_66),
.D(nco_AXILiteS_s_axi_U_n_13),
.Q(temp_V_reg[9]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi
(s_axi_AXILiteS_RVALID,
ap_rst_n_inv,
s_axi_AXILiteS_ARREADY,
O,
\temp_V_reg[7] ,
\temp_V_reg[11] ,
\temp_V_reg[15] ,
sel,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BVALID,
ap_clk,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
out,
temp_V_reg,
ap_rst_n,
Q,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_BREADY);
output s_axi_AXILiteS_RVALID;
output ap_rst_n_inv;
output s_axi_AXILiteS_ARREADY;
output [3:0]O;
output [3:0]\temp_V_reg[7] ;
output [3:0]\temp_V_reg[11] ;
output [3:0]\temp_V_reg[15] ;
output [11:0]sel;
output [15:0]s_axi_AXILiteS_RDATA;
output s_axi_AXILiteS_AWREADY;
output s_axi_AXILiteS_WREADY;
output s_axi_AXILiteS_BVALID;
input ap_clk;
input s_axi_AXILiteS_ARVALID;
input s_axi_AXILiteS_RREADY;
input [4:0]s_axi_AXILiteS_ARADDR;
input [15:0]s_axi_AXILiteS_WDATA;
input [1:0]s_axi_AXILiteS_WSTRB;
input [15:0]out;
input [15:0]temp_V_reg;
input ap_rst_n;
input [0:0]Q;
input [4:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_AWVALID;
input s_axi_AXILiteS_WVALID;
input s_axi_AXILiteS_BREADY;
wire [3:0]O;
wire [0:0]Q;
wire ap_clk;
wire ap_rst_n;
wire ap_rst_n_inv;
wire ar_hs;
wire int_sine_sample_V_ap_vld;
wire int_sine_sample_V_ap_vld_i_1_n_0;
wire int_sine_sample_V_ap_vld_i_2_n_0;
wire \int_step_size_V[0]_i_1_n_0 ;
wire \int_step_size_V[10]_i_1_n_0 ;
wire \int_step_size_V[11]_i_1_n_0 ;
wire \int_step_size_V[12]_i_1_n_0 ;
wire \int_step_size_V[13]_i_1_n_0 ;
wire \int_step_size_V[14]_i_1_n_0 ;
wire \int_step_size_V[15]_i_2_n_0 ;
wire \int_step_size_V[15]_i_3_n_0 ;
wire \int_step_size_V[1]_i_1_n_0 ;
wire \int_step_size_V[2]_i_1_n_0 ;
wire \int_step_size_V[3]_i_1_n_0 ;
wire \int_step_size_V[4]_i_1_n_0 ;
wire \int_step_size_V[5]_i_1_n_0 ;
wire \int_step_size_V[6]_i_1_n_0 ;
wire \int_step_size_V[7]_i_1_n_0 ;
wire \int_step_size_V[8]_i_1_n_0 ;
wire \int_step_size_V[9]_i_1_n_0 ;
wire [15:0]out;
wire p_0_in;
wire q0_reg_0_i_10_n_0;
wire q0_reg_0_i_11_n_0;
wire q0_reg_0_i_12_n_0;
wire q0_reg_0_i_12_n_1;
wire q0_reg_0_i_12_n_2;
wire q0_reg_0_i_12_n_3;
wire q0_reg_0_i_13_n_0;
wire q0_reg_0_i_14_n_0;
wire q0_reg_0_i_15_n_0;
wire q0_reg_0_i_16_n_0;
wire q0_reg_0_i_17_n_0;
wire q0_reg_0_i_18_n_0;
wire q0_reg_0_i_19_n_0;
wire q0_reg_0_i_1_n_1;
wire q0_reg_0_i_1_n_2;
wire q0_reg_0_i_1_n_3;
wire q0_reg_0_i_20_n_0;
wire q0_reg_0_i_2_n_0;
wire q0_reg_0_i_2_n_1;
wire q0_reg_0_i_2_n_2;
wire q0_reg_0_i_2_n_3;
wire q0_reg_0_i_3_n_0;
wire q0_reg_0_i_3_n_1;
wire q0_reg_0_i_3_n_2;
wire q0_reg_0_i_3_n_3;
wire q0_reg_0_i_4_n_0;
wire q0_reg_0_i_5_n_0;
wire q0_reg_0_i_6_n_0;
wire q0_reg_0_i_7_n_0;
wire q0_reg_0_i_8_n_0;
wire q0_reg_0_i_9_n_0;
wire \rdata[0]_i_1_n_0 ;
wire \rdata[0]_i_2_n_0 ;
wire \rdata[10]_i_1_n_0 ;
wire \rdata[11]_i_1_n_0 ;
wire \rdata[12]_i_1_n_0 ;
wire \rdata[13]_i_1_n_0 ;
wire \rdata[14]_i_1_n_0 ;
wire \rdata[15]_i_1_n_0 ;
wire \rdata[15]_i_3_n_0 ;
wire \rdata[1]_i_1_n_0 ;
wire \rdata[2]_i_1_n_0 ;
wire \rdata[3]_i_1_n_0 ;
wire \rdata[4]_i_1_n_0 ;
wire \rdata[5]_i_1_n_0 ;
wire \rdata[6]_i_1_n_0 ;
wire \rdata[7]_i_1_n_0 ;
wire \rdata[8]_i_1_n_0 ;
wire \rdata[9]_i_1_n_0 ;
wire \rstate[0]_i_2_n_0 ;
wire [4:0]s_axi_AXILiteS_ARADDR;
wire s_axi_AXILiteS_ARREADY;
wire s_axi_AXILiteS_ARVALID;
wire [4:0]s_axi_AXILiteS_AWADDR;
wire s_axi_AXILiteS_AWREADY;
wire s_axi_AXILiteS_AWVALID;
wire s_axi_AXILiteS_BREADY;
wire s_axi_AXILiteS_BVALID;
wire [15:0]s_axi_AXILiteS_RDATA;
wire s_axi_AXILiteS_RREADY;
wire s_axi_AXILiteS_RVALID;
wire [15:0]s_axi_AXILiteS_WDATA;
wire s_axi_AXILiteS_WREADY;
wire [1:0]s_axi_AXILiteS_WSTRB;
wire s_axi_AXILiteS_WVALID;
wire [11:0]sel;
wire [15:0]step_size_V;
wire \temp_V[0]_i_2_n_0 ;
wire \temp_V[0]_i_3_n_0 ;
wire \temp_V[0]_i_4_n_0 ;
wire \temp_V[0]_i_5_n_0 ;
wire \temp_V[12]_i_2_n_0 ;
wire \temp_V[12]_i_3_n_0 ;
wire \temp_V[12]_i_4_n_0 ;
wire \temp_V[12]_i_5_n_0 ;
wire \temp_V[4]_i_2_n_0 ;
wire \temp_V[4]_i_3_n_0 ;
wire \temp_V[4]_i_4_n_0 ;
wire \temp_V[4]_i_5_n_0 ;
wire \temp_V[8]_i_2_n_0 ;
wire \temp_V[8]_i_3_n_0 ;
wire \temp_V[8]_i_4_n_0 ;
wire \temp_V[8]_i_5_n_0 ;
wire [15:0]temp_V_reg;
wire \temp_V_reg[0]_i_1_n_0 ;
wire \temp_V_reg[0]_i_1_n_1 ;
wire \temp_V_reg[0]_i_1_n_2 ;
wire \temp_V_reg[0]_i_1_n_3 ;
wire [3:0]\temp_V_reg[11] ;
wire \temp_V_reg[12]_i_1_n_1 ;
wire \temp_V_reg[12]_i_1_n_2 ;
wire \temp_V_reg[12]_i_1_n_3 ;
wire [3:0]\temp_V_reg[15] ;
wire \temp_V_reg[4]_i_1_n_0 ;
wire \temp_V_reg[4]_i_1_n_1 ;
wire \temp_V_reg[4]_i_1_n_2 ;
wire \temp_V_reg[4]_i_1_n_3 ;
wire [3:0]\temp_V_reg[7] ;
wire \temp_V_reg[8]_i_1_n_0 ;
wire \temp_V_reg[8]_i_1_n_1 ;
wire \temp_V_reg[8]_i_1_n_2 ;
wire \temp_V_reg[8]_i_1_n_3 ;
wire waddr;
wire \waddr_reg_n_0_[0] ;
wire \waddr_reg_n_0_[1] ;
wire \waddr_reg_n_0_[2] ;
wire \waddr_reg_n_0_[3] ;
wire \waddr_reg_n_0_[4] ;
wire [1:0]wstate;
wire \wstate[0]_i_1_n_0 ;
wire \wstate[1]_i_1_n_0 ;
wire [3:3]NLW_q0_reg_0_i_1_CO_UNCONNECTED;
wire [3:0]NLW_q0_reg_0_i_12_O_UNCONNECTED;
wire [3:3]\NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hFFEFFFFFAAAAAAAA))
int_sine_sample_V_ap_vld_i_1
(.I0(Q),
.I1(int_sine_sample_V_ap_vld_i_2_n_0),
.I2(ar_hs),
.I3(s_axi_AXILiteS_ARADDR[3]),
.I4(s_axi_AXILiteS_ARADDR[2]),
.I5(int_sine_sample_V_ap_vld),
.O(int_sine_sample_V_ap_vld_i_1_n_0));
LUT3 #(
.INIT(8'hFB))
int_sine_sample_V_ap_vld_i_2
(.I0(s_axi_AXILiteS_ARADDR[1]),
.I1(s_axi_AXILiteS_ARADDR[4]),
.I2(s_axi_AXILiteS_ARADDR[0]),
.O(int_sine_sample_V_ap_vld_i_2_n_0));
FDRE int_sine_sample_V_ap_vld_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_sine_sample_V_ap_vld_i_1_n_0),
.Q(int_sine_sample_V_ap_vld),
.R(ap_rst_n_inv));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[0]_i_1
(.I0(s_axi_AXILiteS_WDATA[0]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[0]),
.O(\int_step_size_V[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[10]_i_1
(.I0(s_axi_AXILiteS_WDATA[10]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[10]),
.O(\int_step_size_V[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[11]_i_1
(.I0(s_axi_AXILiteS_WDATA[11]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[11]),
.O(\int_step_size_V[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[12]_i_1
(.I0(s_axi_AXILiteS_WDATA[12]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[12]),
.O(\int_step_size_V[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[13]_i_1
(.I0(s_axi_AXILiteS_WDATA[13]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[13]),
.O(\int_step_size_V[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[14]_i_1
(.I0(s_axi_AXILiteS_WDATA[14]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[14]),
.O(\int_step_size_V[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0001))
\int_step_size_V[15]_i_1
(.I0(\waddr_reg_n_0_[0] ),
.I1(\waddr_reg_n_0_[2] ),
.I2(\waddr_reg_n_0_[1] ),
.I3(\int_step_size_V[15]_i_3_n_0 ),
.O(p_0_in));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[15]_i_2
(.I0(s_axi_AXILiteS_WDATA[15]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[15]),
.O(\int_step_size_V[15]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFF7FFF))
\int_step_size_V[15]_i_3
(.I0(\waddr_reg_n_0_[4] ),
.I1(\waddr_reg_n_0_[3] ),
.I2(s_axi_AXILiteS_WVALID),
.I3(wstate[0]),
.I4(wstate[1]),
.O(\int_step_size_V[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[1]_i_1
(.I0(s_axi_AXILiteS_WDATA[1]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[1]),
.O(\int_step_size_V[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[2]_i_1
(.I0(s_axi_AXILiteS_WDATA[2]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[2]),
.O(\int_step_size_V[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[3]_i_1
(.I0(s_axi_AXILiteS_WDATA[3]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[3]),
.O(\int_step_size_V[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[4]_i_1
(.I0(s_axi_AXILiteS_WDATA[4]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[4]),
.O(\int_step_size_V[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[5]_i_1
(.I0(s_axi_AXILiteS_WDATA[5]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[5]),
.O(\int_step_size_V[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[6]_i_1
(.I0(s_axi_AXILiteS_WDATA[6]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[6]),
.O(\int_step_size_V[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[7]_i_1
(.I0(s_axi_AXILiteS_WDATA[7]),
.I1(s_axi_AXILiteS_WSTRB[0]),
.I2(step_size_V[7]),
.O(\int_step_size_V[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[8]_i_1
(.I0(s_axi_AXILiteS_WDATA[8]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[8]),
.O(\int_step_size_V[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\int_step_size_V[9]_i_1
(.I0(s_axi_AXILiteS_WDATA[9]),
.I1(s_axi_AXILiteS_WSTRB[1]),
.I2(step_size_V[9]),
.O(\int_step_size_V[9]_i_1_n_0 ));
FDRE \int_step_size_V_reg[0]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[0]_i_1_n_0 ),
.Q(step_size_V[0]),
.R(1'b0));
FDRE \int_step_size_V_reg[10]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[10]_i_1_n_0 ),
.Q(step_size_V[10]),
.R(1'b0));
FDRE \int_step_size_V_reg[11]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[11]_i_1_n_0 ),
.Q(step_size_V[11]),
.R(1'b0));
FDRE \int_step_size_V_reg[12]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[12]_i_1_n_0 ),
.Q(step_size_V[12]),
.R(1'b0));
FDRE \int_step_size_V_reg[13]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[13]_i_1_n_0 ),
.Q(step_size_V[13]),
.R(1'b0));
FDRE \int_step_size_V_reg[14]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[14]_i_1_n_0 ),
.Q(step_size_V[14]),
.R(1'b0));
FDRE \int_step_size_V_reg[15]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[15]_i_2_n_0 ),
.Q(step_size_V[15]),
.R(1'b0));
FDRE \int_step_size_V_reg[1]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[1]_i_1_n_0 ),
.Q(step_size_V[1]),
.R(1'b0));
FDRE \int_step_size_V_reg[2]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[2]_i_1_n_0 ),
.Q(step_size_V[2]),
.R(1'b0));
FDRE \int_step_size_V_reg[3]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[3]_i_1_n_0 ),
.Q(step_size_V[3]),
.R(1'b0));
FDRE \int_step_size_V_reg[4]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[4]_i_1_n_0 ),
.Q(step_size_V[4]),
.R(1'b0));
FDRE \int_step_size_V_reg[5]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[5]_i_1_n_0 ),
.Q(step_size_V[5]),
.R(1'b0));
FDRE \int_step_size_V_reg[6]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[6]_i_1_n_0 ),
.Q(step_size_V[6]),
.R(1'b0));
FDRE \int_step_size_V_reg[7]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[7]_i_1_n_0 ),
.Q(step_size_V[7]),
.R(1'b0));
FDRE \int_step_size_V_reg[8]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[8]_i_1_n_0 ),
.Q(step_size_V[8]),
.R(1'b0));
FDRE \int_step_size_V_reg[9]
(.C(ap_clk),
.CE(p_0_in),
.D(\int_step_size_V[9]_i_1_n_0 ),
.Q(step_size_V[9]),
.R(1'b0));
CARRY4 q0_reg_0_i_1
(.CI(q0_reg_0_i_2_n_0),
.CO({NLW_q0_reg_0_i_1_CO_UNCONNECTED[3],q0_reg_0_i_1_n_1,q0_reg_0_i_1_n_2,q0_reg_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,temp_V_reg[14:12]}),
.O(sel[11:8]),
.S({q0_reg_0_i_4_n_0,q0_reg_0_i_5_n_0,q0_reg_0_i_6_n_0,q0_reg_0_i_7_n_0}));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_10
(.I0(temp_V_reg[9]),
.I1(step_size_V[9]),
.O(q0_reg_0_i_10_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_11
(.I0(temp_V_reg[8]),
.I1(step_size_V[8]),
.O(q0_reg_0_i_11_n_0));
CARRY4 q0_reg_0_i_12
(.CI(1'b0),
.CO({q0_reg_0_i_12_n_0,q0_reg_0_i_12_n_1,q0_reg_0_i_12_n_2,q0_reg_0_i_12_n_3}),
.CYINIT(1'b0),
.DI(temp_V_reg[3:0]),
.O(NLW_q0_reg_0_i_12_O_UNCONNECTED[3:0]),
.S({q0_reg_0_i_17_n_0,q0_reg_0_i_18_n_0,q0_reg_0_i_19_n_0,q0_reg_0_i_20_n_0}));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_13
(.I0(temp_V_reg[7]),
.I1(step_size_V[7]),
.O(q0_reg_0_i_13_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_14
(.I0(temp_V_reg[6]),
.I1(step_size_V[6]),
.O(q0_reg_0_i_14_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_15
(.I0(temp_V_reg[5]),
.I1(step_size_V[5]),
.O(q0_reg_0_i_15_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_16
(.I0(temp_V_reg[4]),
.I1(step_size_V[4]),
.O(q0_reg_0_i_16_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_17
(.I0(temp_V_reg[3]),
.I1(step_size_V[3]),
.O(q0_reg_0_i_17_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_18
(.I0(temp_V_reg[2]),
.I1(step_size_V[2]),
.O(q0_reg_0_i_18_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_19
(.I0(temp_V_reg[1]),
.I1(step_size_V[1]),
.O(q0_reg_0_i_19_n_0));
CARRY4 q0_reg_0_i_2
(.CI(q0_reg_0_i_3_n_0),
.CO({q0_reg_0_i_2_n_0,q0_reg_0_i_2_n_1,q0_reg_0_i_2_n_2,q0_reg_0_i_2_n_3}),
.CYINIT(1'b0),
.DI(temp_V_reg[11:8]),
.O(sel[7:4]),
.S({q0_reg_0_i_8_n_0,q0_reg_0_i_9_n_0,q0_reg_0_i_10_n_0,q0_reg_0_i_11_n_0}));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_20
(.I0(temp_V_reg[0]),
.I1(step_size_V[0]),
.O(q0_reg_0_i_20_n_0));
CARRY4 q0_reg_0_i_3
(.CI(q0_reg_0_i_12_n_0),
.CO({q0_reg_0_i_3_n_0,q0_reg_0_i_3_n_1,q0_reg_0_i_3_n_2,q0_reg_0_i_3_n_3}),
.CYINIT(1'b0),
.DI(temp_V_reg[7:4]),
.O(sel[3:0]),
.S({q0_reg_0_i_13_n_0,q0_reg_0_i_14_n_0,q0_reg_0_i_15_n_0,q0_reg_0_i_16_n_0}));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_4
(.I0(temp_V_reg[15]),
.I1(step_size_V[15]),
.O(q0_reg_0_i_4_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_5
(.I0(temp_V_reg[14]),
.I1(step_size_V[14]),
.O(q0_reg_0_i_5_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_6
(.I0(temp_V_reg[13]),
.I1(step_size_V[13]),
.O(q0_reg_0_i_6_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_7
(.I0(temp_V_reg[12]),
.I1(step_size_V[12]),
.O(q0_reg_0_i_7_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_8
(.I0(temp_V_reg[11]),
.I1(step_size_V[11]),
.O(q0_reg_0_i_8_n_0));
LUT2 #(
.INIT(4'h6))
q0_reg_0_i_9
(.I0(temp_V_reg[10]),
.I1(step_size_V[10]),
.O(q0_reg_0_i_9_n_0));
LUT6 #(
.INIT(64'h0020FFFF00200000))
\rdata[0]_i_1
(.I0(\rdata[0]_i_2_n_0 ),
.I1(s_axi_AXILiteS_ARADDR[0]),
.I2(s_axi_AXILiteS_ARADDR[4]),
.I3(s_axi_AXILiteS_ARADDR[1]),
.I4(ar_hs),
.I5(s_axi_AXILiteS_RDATA[0]),
.O(\rdata[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\rdata[0]_i_2
(.I0(step_size_V[0]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(int_sine_sample_V_ap_vld),
.I3(s_axi_AXILiteS_ARADDR[2]),
.I4(out[0]),
.O(\rdata[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\rdata[10]_i_1
(.I0(step_size_V[10]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[10]),
.O(\rdata[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\rdata[11]_i_1
(.I0(step_size_V[11]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[11]),
.O(\rdata[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\rdata[12]_i_1
(.I0(step_size_V[12]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[12]),
.O(\rdata[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\rdata[13]_i_1
(.I0(step_size_V[13]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[13]),
.O(\rdata[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\rdata[14]_i_1
(.I0(step_size_V[14]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[14]),
.O(\rdata[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000FFFB00000000))
\rdata[15]_i_1
(.I0(s_axi_AXILiteS_ARADDR[1]),
.I1(s_axi_AXILiteS_ARADDR[4]),
.I2(s_axi_AXILiteS_ARADDR[0]),
.I3(s_axi_AXILiteS_ARADDR[2]),
.I4(s_axi_AXILiteS_RVALID),
.I5(s_axi_AXILiteS_ARVALID),
.O(\rdata[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\rdata[15]_i_2
(.I0(s_axi_AXILiteS_ARVALID),
.I1(s_axi_AXILiteS_RVALID),
.O(ar_hs));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\rdata[15]_i_3
(.I0(step_size_V[15]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[15]),
.O(\rdata[15]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\rdata[1]_i_1
(.I0(step_size_V[1]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[1]),
.O(\rdata[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\rdata[2]_i_1
(.I0(step_size_V[2]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[2]),
.O(\rdata[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\rdata[3]_i_1
(.I0(step_size_V[3]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[3]),
.O(\rdata[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\rdata[4]_i_1
(.I0(step_size_V[4]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[4]),
.O(\rdata[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\rdata[5]_i_1
(.I0(step_size_V[5]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[5]),
.O(\rdata[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\rdata[6]_i_1
(.I0(step_size_V[6]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[6]),
.O(\rdata[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\rdata[7]_i_1
(.I0(step_size_V[7]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[7]),
.O(\rdata[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\rdata[8]_i_1
(.I0(step_size_V[8]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[8]),
.O(\rdata[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\rdata[9]_i_1
(.I0(step_size_V[9]),
.I1(s_axi_AXILiteS_ARADDR[3]),
.I2(out[9]),
.O(\rdata[9]_i_1_n_0 ));
FDRE \rdata_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\rdata[0]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[0]),
.R(1'b0));
FDRE \rdata_reg[10]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[10]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[10]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[11]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[11]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[11]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[12]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[12]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[12]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[13]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[13]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[13]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[14]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[14]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[14]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[15]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[15]_i_3_n_0 ),
.Q(s_axi_AXILiteS_RDATA[15]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[1]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[1]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[1]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[2]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[2]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[2]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[3]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[3]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[3]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[4]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[4]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[4]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[5]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[5]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[5]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[6]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[6]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[6]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[7]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[7]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[7]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[8]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[8]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[8]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[9]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[9]_i_1_n_0 ),
.Q(s_axi_AXILiteS_RDATA[9]),
.R(\rdata[15]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\rstate[0]_i_1
(.I0(ap_rst_n),
.O(ap_rst_n_inv));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h3A))
\rstate[0]_i_2
(.I0(s_axi_AXILiteS_ARVALID),
.I1(s_axi_AXILiteS_RREADY),
.I2(s_axi_AXILiteS_RVALID),
.O(\rstate[0]_i_2_n_0 ));
FDRE \rstate_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\rstate[0]_i_2_n_0 ),
.Q(s_axi_AXILiteS_RVALID),
.R(ap_rst_n_inv));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT1 #(
.INIT(2'h1))
s_axi_AXILiteS_ARREADY_INST_0
(.I0(s_axi_AXILiteS_RVALID),
.O(s_axi_AXILiteS_ARREADY));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h1))
s_axi_AXILiteS_AWREADY_INST_0
(.I0(wstate[1]),
.I1(wstate[0]),
.O(s_axi_AXILiteS_AWREADY));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h2))
s_axi_AXILiteS_BVALID_INST_0
(.I0(wstate[1]),
.I1(wstate[0]),
.O(s_axi_AXILiteS_BVALID));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h2))
s_axi_AXILiteS_WREADY_INST_0
(.I0(wstate[0]),
.I1(wstate[1]),
.O(s_axi_AXILiteS_WREADY));
LUT2 #(
.INIT(4'h6))
\temp_V[0]_i_2
(.I0(step_size_V[3]),
.I1(temp_V_reg[3]),
.O(\temp_V[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[0]_i_3
(.I0(step_size_V[2]),
.I1(temp_V_reg[2]),
.O(\temp_V[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[0]_i_4
(.I0(step_size_V[1]),
.I1(temp_V_reg[1]),
.O(\temp_V[0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[0]_i_5
(.I0(step_size_V[0]),
.I1(temp_V_reg[0]),
.O(\temp_V[0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[12]_i_2
(.I0(temp_V_reg[15]),
.I1(step_size_V[15]),
.O(\temp_V[12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[12]_i_3
(.I0(step_size_V[14]),
.I1(temp_V_reg[14]),
.O(\temp_V[12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[12]_i_4
(.I0(step_size_V[13]),
.I1(temp_V_reg[13]),
.O(\temp_V[12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[12]_i_5
(.I0(step_size_V[12]),
.I1(temp_V_reg[12]),
.O(\temp_V[12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[4]_i_2
(.I0(step_size_V[7]),
.I1(temp_V_reg[7]),
.O(\temp_V[4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[4]_i_3
(.I0(step_size_V[6]),
.I1(temp_V_reg[6]),
.O(\temp_V[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[4]_i_4
(.I0(step_size_V[5]),
.I1(temp_V_reg[5]),
.O(\temp_V[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[4]_i_5
(.I0(step_size_V[4]),
.I1(temp_V_reg[4]),
.O(\temp_V[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[8]_i_2
(.I0(step_size_V[11]),
.I1(temp_V_reg[11]),
.O(\temp_V[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[8]_i_3
(.I0(step_size_V[10]),
.I1(temp_V_reg[10]),
.O(\temp_V[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[8]_i_4
(.I0(step_size_V[9]),
.I1(temp_V_reg[9]),
.O(\temp_V[8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\temp_V[8]_i_5
(.I0(step_size_V[8]),
.I1(temp_V_reg[8]),
.O(\temp_V[8]_i_5_n_0 ));
CARRY4 \temp_V_reg[0]_i_1
(.CI(1'b0),
.CO({\temp_V_reg[0]_i_1_n_0 ,\temp_V_reg[0]_i_1_n_1 ,\temp_V_reg[0]_i_1_n_2 ,\temp_V_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(step_size_V[3:0]),
.O(O),
.S({\temp_V[0]_i_2_n_0 ,\temp_V[0]_i_3_n_0 ,\temp_V[0]_i_4_n_0 ,\temp_V[0]_i_5_n_0 }));
CARRY4 \temp_V_reg[12]_i_1
(.CI(\temp_V_reg[8]_i_1_n_0 ),
.CO({\NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED [3],\temp_V_reg[12]_i_1_n_1 ,\temp_V_reg[12]_i_1_n_2 ,\temp_V_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,step_size_V[14:12]}),
.O(\temp_V_reg[15] ),
.S({\temp_V[12]_i_2_n_0 ,\temp_V[12]_i_3_n_0 ,\temp_V[12]_i_4_n_0 ,\temp_V[12]_i_5_n_0 }));
CARRY4 \temp_V_reg[4]_i_1
(.CI(\temp_V_reg[0]_i_1_n_0 ),
.CO({\temp_V_reg[4]_i_1_n_0 ,\temp_V_reg[4]_i_1_n_1 ,\temp_V_reg[4]_i_1_n_2 ,\temp_V_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(step_size_V[7:4]),
.O(\temp_V_reg[7] ),
.S({\temp_V[4]_i_2_n_0 ,\temp_V[4]_i_3_n_0 ,\temp_V[4]_i_4_n_0 ,\temp_V[4]_i_5_n_0 }));
CARRY4 \temp_V_reg[8]_i_1
(.CI(\temp_V_reg[4]_i_1_n_0 ),
.CO({\temp_V_reg[8]_i_1_n_0 ,\temp_V_reg[8]_i_1_n_1 ,\temp_V_reg[8]_i_1_n_2 ,\temp_V_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(step_size_V[11:8]),
.O(\temp_V_reg[11] ),
.S({\temp_V[8]_i_2_n_0 ,\temp_V[8]_i_3_n_0 ,\temp_V[8]_i_4_n_0 ,\temp_V[8]_i_5_n_0 }));
LUT3 #(
.INIT(8'h02))
\waddr[4]_i_1
(.I0(s_axi_AXILiteS_AWVALID),
.I1(wstate[0]),
.I2(wstate[1]),
.O(waddr));
FDRE \waddr_reg[0]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_AXILiteS_AWADDR[0]),
.Q(\waddr_reg_n_0_[0] ),
.R(1'b0));
FDRE \waddr_reg[1]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_AXILiteS_AWADDR[1]),
.Q(\waddr_reg_n_0_[1] ),
.R(1'b0));
FDRE \waddr_reg[2]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_AXILiteS_AWADDR[2]),
.Q(\waddr_reg_n_0_[2] ),
.R(1'b0));
FDRE \waddr_reg[3]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_AXILiteS_AWADDR[3]),
.Q(\waddr_reg_n_0_[3] ),
.R(1'b0));
FDRE \waddr_reg[4]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_AXILiteS_AWADDR[4]),
.Q(\waddr_reg_n_0_[4] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0454))
\wstate[0]_i_1
(.I0(wstate[1]),
.I1(s_axi_AXILiteS_AWVALID),
.I2(wstate[0]),
.I3(s_axi_AXILiteS_WVALID),
.O(\wstate[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0838))
\wstate[1]_i_1
(.I0(s_axi_AXILiteS_WVALID),
.I1(wstate[0]),
.I2(wstate[1]),
.I3(s_axi_AXILiteS_BREADY),
.O(\wstate[1]_i_1_n_0 ));
FDRE \wstate_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\wstate[0]_i_1_n_0 ),
.Q(wstate[0]),
.R(ap_rst_n_inv));
FDRE \wstate_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\wstate[1]_i_1_n_0 ),
.Q(wstate[1]),
.R(ap_rst_n_inv));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V
(out,
ap_clk,
Q,
SR,
sel);
output [15:0]out;
input ap_clk;
input [1:0]Q;
input [0:0]SR;
input [11:0]sel;
wire [1:0]Q;
wire [0:0]SR;
wire ap_clk;
wire [15:0]out;
wire [11:0]sel;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom nco_sine_lut_V_rom_U
(.Q(Q),
.SR(SR),
.ap_clk(ap_clk),
.out(out),
.sel(sel));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom
(out,
ap_clk,
Q,
SR,
sel);
output [15:0]out;
input ap_clk;
input [1:0]Q;
input [0:0]SR;
input [11:0]sel;
wire [1:0]Q;
wire [0:0]SR;
wire ap_clk;
wire [15:0]out;
wire [11:0]sel;
wire NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_q0_reg_0_DBITERR_UNCONNECTED;
wire NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_q0_reg_0_SBITERR_UNCONNECTED;
wire [31:8]NLW_q0_reg_0_DOADO_UNCONNECTED;
wire [31:0]NLW_q0_reg_0_DOBDO_UNCONNECTED;
wire [3:1]NLW_q0_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_q0_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_q0_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_q0_reg_0_RDADDRECC_UNCONNECTED;
wire NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED;
wire NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED;
wire NLW_q0_reg_1_DBITERR_UNCONNECTED;
wire NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED;
wire NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED;
wire NLW_q0_reg_1_SBITERR_UNCONNECTED;
wire [31:7]NLW_q0_reg_1_DOADO_UNCONNECTED;
wire [31:0]NLW_q0_reg_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_q0_reg_1_DOPADOP_UNCONNECTED;
wire [3:0]NLW_q0_reg_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_q0_reg_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_q0_reg_1_RDADDRECC_UNCONNECTED;
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* RTL_RAM_BITS = "65536" *)
(* RTL_RAM_NAME = "sine_lut_V_U/nco_sine_lut_V_rom_U/q0" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "4095" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "8" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h07FF001FFC00FFE003FF001FF800FFC007FE007FF003FF003FF801FF801FF800),
.INITP_01(256'hE0007FFE0007FFC001FFF0007FFC003FFC003FFC003FFC007FF800FFF001FFC0),
.INITP_02(256'hE000000FFFFFE000007FFFF800007FFFE00007FFFC0001FFFE0001FFFC0007FF),
.INITP_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000001FFFFFFFFF00000001FFFFFF),
.INITP_04(256'hFFFFFF00000001FFFFFFFFF000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFE),
.INITP_05(256'hFFC0007FFF0000FFFF00007FFFC0000FFFFC00003FFFFC00000FFFFFE000000F),
.INITP_06(256'h07FF001FFE003FFC007FF8007FF8007FF8007FFC001FFF0007FFC000FFFC000F),
.INITP_07(256'h003FF003FF003FF801FF801FFC00FFC007FE003FF001FF800FFE007FF001FFC0),
.INITP_08(256'hF800FFE003FF001FFC00FFE007FF003FF801FF800FFC00FFC007FE007FE007FE),
.INITP_09(256'h1FFF8001FFF8003FFE000FFF8003FFC003FFC003FFC003FF8007FF000FFE003F),
.INITP_0A(256'h1FFFFFF000001FFFFF800007FFFF80001FFFF80003FFFE0001FFFE0003FFF800),
.INITP_0B(256'h00000000000000000000000000001FFFFFFFFFFFE000000000FFFFFFFE000000),
.INITP_0C(256'h000000FFFFFFFE000000000FFFFFFFFFFFF00000000000000000000000000000),
.INITP_0D(256'h003FFF8000FFFF0000FFFF80003FFFF00003FFFFC00003FFFFF000001FFFFFF0),
.INITP_0E(256'hF800FFE001FFC003FF8007FF8007FF8007FF8003FFE000FFF8003FFF0003FFF0),
.INITP_0F(256'hFFC00FFC00FFC007FE007FE003FF003FF801FFC00FFE007FF001FF800FFE003F),
.INIT_00(256'h0AF1D8BFA68D745B41280FF6DDC4AB92785F462D14FBE2C9AF967D644B321900),
.INIT_01(256'h2C13FAE1C8AF967D644B321900E7CEB59C836A51371E05ECD3BAA1886F563D23),
.INIT_02(256'h4B321900E7CEB59C846B52392007EED5BCA38A71583F260DF4DBC2A990775E45),
.INIT_03(256'h634B321901E8CFB69E856C543B2209F1D8BFA68D755C432A11F9E0C7AE957C64),
.INIT_04(256'h745C432B12FAE2C9B19880674F361E05EDD4BCA38B7259412810F7DEC6AD957C),
.INIT_05(256'h7B634B331B03EBD3BBA28A725A422A11F9E1C9B09880684F371F06EED6BDA58C),
.INIT_06(256'h776048301901E9D1BAA28A725A432B13FBE3CBB39B836C543C240CF4DCC4AC94),
.INIT_07(256'h664F382009F2DAC3AC947D664E371F08F1D9C2AA937B644C341D05EED6BEA78F),
.INIT_08(256'h462F1802EBD4BDA68F79624B341D06EFD8C1AA937C654E372008F1DAC3AC957D),
.INIT_09(256'h15FEE8D2BCA68F79634C362009F3DCC6AF99836C553F2812FBE5CEB7A18A735D),
.INIT_0A(256'hD1BBA6907B654F39240EF8E2CDB7A18B755F49341E08F2DCC6B099836D57412B),
.INIT_0B(256'h79644F3A2510FBE6D1BCA7927D67523D2812FDE8D2BDA8927D68523D2712FCE7),
.INIT_0C(256'h0BF7E3CFBAA6927D6954402C1703EEDAC5B09C87735E4934200BF6E1CDB8A38E),
.INIT_0D(256'h86725F4B382411FDEAD6C2AF9B87735F4C382410FCE8D4C0AC9884705C48341F),
.INIT_0E(256'hE8D5C2B09D8A7765523F2C1906F3E0CDBAA794816E5A4734210EFAE7D4C0AD99),
.INIT_0F(256'h2F1D0BF9E8D6C4B2A08E7C6A574533210FFCEAD8C6B3A18E7C6A574532200DFA),
.INIT_10(256'h5A4938281605F4E3D2C1B09F8D7C6B5A4837251403F1E0CEBCAB998876645241),
.INIT_11(256'h69594938281808F8E8D8C7B7A796867665554434231302F1E1D0BFAF9E8D7C6B),
.INIT_12(256'h58493A2B1C0DFEEEDFD0C1B1A293837464554536261607F7E7D8C8B8A8988879),
.INIT_13(256'h281A0CFEF0E2D4C6B7A99B8C7E706153443627190AFBEDDECFC1B2A394857667),
.INIT_14(256'hD8CBBEB1A496897C6F6254473A2C1F1204F7E9DCCEC0B3A597897C6E60524436),
.INIT_15(256'h65594D4135291D1105F9EDE0D4C8BBAFA3968A7D7164574B3E3125180BFEF1E5),
.INIT_16(256'hD0C5BAAFA4998E83786D62574C41352A1F1308FDF1E6DACFC3B7ACA094897D71),
.INIT_17(256'h170D03FAF0E6DCD2C8BEB4AAA0968C82786D63594F443A2F251A1005FBF0E5DA),
.INIT_18(256'h39312820170E06FDF4EBE2DAD1C8BFB6ADA39A91887F756C635950473D342A20),
.INIT_19(256'h372F282119120A02FBF3ECE4DCD4CCC5BDB5ADA59D958C847C746C635B534A42),
.INIT_1A(256'h0E0802FCF5EFE9E2DCD6CFC9C2BBB5AEA7A19A938C857E777069625B544D453E),
.INIT_1B(256'hC0BBB6B1ACA7A19C97928C87827C77716C66615B55504A443E38332D27211B14),
.INIT_1C(256'h4A47433F3B37332F2B27231F1B17130E0A0601FDF8F4EFEBE6E1DDD8D3CECAC5),
.INIT_1D(256'hAEACA9A6A4A19E9C999693908D8A8784817E7B7874716E6A6764605D5955524E),
.INIT_1E(256'hEBE9E8E7E5E4E2E1DFDEDCDAD8D7D5D3D1CFCDCBC9C7C5C3C1BFBCBAB8B5B3B1),
.INIT_1F(256'hFFFFFFFFFFFFFFFEFEFEFDFDFCFCFBFBFAF9F9F8F7F6F5F4F3F2F1F0EFEEEDEC),
.INIT_20(256'hEDEEEFF0F1F2F3F4F5F6F7F8F9F9FAFBFBFCFCFDFDFEFEFEFFFFFFFFFFFFFF00),
.INIT_21(256'hB3B5B8BABCBFC1C3C5C7C9CBCDCFD1D3D5D7D8DADCDEDFE1E2E4E5E7E8E9EBEC),
.INIT_22(256'h5255595D6064676A6E7174787B7E8184878A8D909396999C9EA1A4A6A9ACAEB1),
.INIT_23(256'hCACED3D8DDE1E6EBEFF4F8FD01060A0E13171B1F23272B2F33373B3F43474A4E),
.INIT_24(256'h1B21272D33383E444A50555B61666C71777C82878C92979CA1A7ACB1B6BBC0C5),
.INIT_25(256'h454D545B626970777E858C939AA1A7AEB5BBC2C9CFD6DCE2E9EFF5FC02080E14),
.INIT_26(256'h4A535B636C747C848C959DA5ADB5BDC5CCD4DCE4ECF3FB020A121921282F373E),
.INIT_27(256'h2A343D475059636C757F88919AA3ADB6BFC8D1DAE2EBF4FD060E172028313942),
.INIT_28(256'hE5F0FB05101A252F3A444F59636D78828C96A0AAB4BEC8D2DCE6F0FA030D1720),
.INIT_29(256'h7D8994A0ACB7C3CFDAE6F1FD08131F2A35414C57626D78838E99A4AFBAC5D0DA),
.INIT_2A(256'hF1FE0B1825313E4B5764717D8A96A3AFBBC8D4E0EDF905111D2935414D596571),
.INIT_2B(256'h4452606E7C8997A5B3C0CEDCE9F704121F2C3A4754626F7C8996A4B1BECBD8E5),
.INIT_2C(256'h768594A3B2C1CFDEEDFB0A192736445361707E8C9BA9B7C6D4E2F0FE0C1A2836),
.INIT_2D(256'h8898A8B8C8D8E7F707162636455564748393A2B1C1D0DFEEFE0D1C2B3A495867),
.INIT_2E(256'h7C8D9EAFBFD0E1F102132334445565768696A7B7C7D8E8F80818283849596979),
.INIT_2F(256'h5264768899ABBCCEE0F103142537485A6B7C8D9FB0C1D2E3F405162838495A6B),
.INIT_30(256'h0D203245576A7C8EA1B3C6D8EAFC0F213345576A7C8EA0B2C4D6E8F90B1D2F41),
.INIT_31(256'hADC0D4E7FA0E2134475A6E8194A7BACDE0F306192C3F5265778A9DB0C2D5E8FA),
.INIT_32(256'h34485C708498ACC0D4E8FC1024384C5F73879BAFC2D6EAFD1124384B5F728699),
.INIT_33(256'hA3B8CDE1F60B2034495E73879CB0C5DAEE03172C4054697D92A6BACFE3F70B1F),
.INIT_34(256'hFC12273D52687D92A8BDD2E8FD12283D52677D92A7BCD1E6FB10253A4F64798E),
.INIT_35(256'h41576D8399B0C6DCF2081E34495F758BA1B7CDE2F80E24394F657B90A6BBD1E7),
.INIT_36(256'h738AA1B7CEE5FB12283F556C8399AFC6DCF30920364C63798FA6BCD2E8FE152B),
.INIT_37(256'h95ACC3DAF10820374E657C93AAC1D8EF061D344B62798FA6BDD4EB02182F465D),
.INIT_38(256'hA7BED6EE051D344C647B93AAC2D9F1081F374E667D94ACC3DAF20920384F667D),
.INIT_39(256'hACC4DCF40C243C546C839BB3CBE3FB132B435A728AA2BAD1E90119304860778F),
.INIT_3A(256'hA5BDD6EE061F374F688098B0C9E1F9112A425A728AA2BBD3EB031B334B637B94),
.INIT_3B(256'h95ADC6DEF710284159728BA3BCD4ED051E364F678098B1C9E2FA122B435C748C),
.INIT_3C(256'h7C95AEC7E0F9112A435C758DA6BFD8F109223B546C859EB6CFE80119324B637C),
.INIT_3D(256'h5E7790A9C2DBF40D263F58718AA3BCD5EE072039526B849CB5CEE70019324B64),
.INIT_3E(256'h3D566F88A1BAD3EC051E37516A839CB5CEE70019324B647D96AFC8E1FA132C45),
.INIT_3F(256'h19324B647D96AFC9E2FB142D465F7892ABC4DDF60F28415B748DA6BFD8F10A23),
.INIT_40(256'hF50E274059728BA4BED7F009223B546D87A0B9D2EB041D365069829BB4CDE600),
.INIT_41(256'hD3EC051E375069829BB4CDE6FF18314A637C95AEC8E1FA132C455E7790A9C2DC),
.INIT_42(256'hB4CDE6FF18314A637B94ADC6DFF8112A435C758EA7C0D9F20B243D566F88A1BA),
.INIT_43(256'h9CB4CDE6FE173049617A93ABC4DDF60E274059728AA3BCD5EE061F38516A839B),
.INIT_44(256'h8BA3BCD4ED051D364E677F98B0C9E1FA122B435C748DA6BED7EF082139526A83),
.INIT_45(256'h849CB4CCE4FC142C445D758DA5BDD5EE061E364F677F97B0C8E0F91129425A73),
.INIT_46(256'h889FB7CFE6FE162E455D758DA5BCD4EC041C344C647C93ABC3DBF30B233B536B),
.INIT_47(256'h99B0C7DFF60D253C536B8299B1C8E0F70E263D556C849BB3CBE2FA1129415870),
.INIT_48(256'hB9D0E7FD142B425970869DB4CBE2F910273E556C839AB1C8DFF70E253C536A82),
.INIT_49(256'hEA01172D435970869CB3C9DFF60C233950667C93AAC0D7ED041A31485E758CA2),
.INIT_4A(256'h2E44596F849AB0C6DBF1071D32485E748AA0B6CBE1F70D23394F667C92A8BED4),
.INIT_4B(256'h869BB0C5DAEF04192E43586D8298ADC2D7ED02172D42576D8297ADC2D8ED0318),
.INIT_4C(256'hF4081C3045596D8296ABBFD3E8FC11253A4F63788CA1B6CBDFF4091E32475C71),
.INIT_4D(256'h798DA0B4C7DBEE0215293D5064788CA0B3C7DBEF03172B3F53677B8FA3B7CBE0),
.INIT_4E(256'h172A3D4F6275889AADC0D3E6F90C1F3245586B7E91A5B8CBDEF105182B3F5266),
.INIT_4F(256'hD0E2F40617293B4D5F718395A8BACCDEF0031527394C5E718395A8BACDDFF205),
.INIT_50(256'hA5B6C7D7E9FA0B1C2D3E4F60728394A5B7C8DAEBFC0E1F3143546677899BADBE),
.INIT_51(256'h96A6B6C7D7E7F70717273848586979899AAABBCBDCECFD0E1E2F405061728394),
.INIT_52(256'hA7B6C5D4E3F20111202F3E4E5D6C7C8B9BAABAC9D9E9F8081827374757677786),
.INIT_53(256'hD7E5F3010F1D2B3948566473818F9EACBBC9D8E6F5041221303E4D5C6B7A8998),
.INIT_54(256'h2734414E5B697683909DABB8C5D3E0EDFB081623313F4C5A687683919FADBBC9),
.INIT_55(256'h9AA6B2BECAD6E2EEFA06121F2B3744505C6975828E9BA8B4C1CEDAE7F4010E1A),
.INIT_56(256'h2F3A45505B66717C87929DA8B3BECAD5E0ECF7020E1925303C48535F6B76828E),
.INIT_57(256'hE8F2FC050F19232D37414B555F69737D87929CA6B0BBC5D0DAE5EFFA040F1A25),
.INIT_58(256'hC6CED7DFE8F1F9020B141D252E374049525C656E77808A939CA6AFB8C2CBD5DF),
.INIT_59(256'hC8D0D7DEE6EDF5FD040C131B232B333A424A525A626A737B838B939CA4ACB5BD),
.INIT_5A(256'hF1F7FD030A10161D232930363D444A51585E656C737A81888F969DA4ABB2BAC1),
.INIT_5B(256'h3F44494E53585E63686D73787D83888E93999EA4AAAFB5BBC1C7CCD2D8DEE4EB),
.INIT_5C(256'hB5B8BCC0C4C8CCD0D4D8DCE0E4E8ECF1F5F9FE02070B1014191E22272C31353A),
.INIT_5D(256'h515356595B5E616366696C6F7275787B7E8184878B8E9195989B9FA2A6AAADB1),
.INIT_5E(256'h141617181A1B1D1E2021232527282A2C2E30323436383A3C3E404345474A4C4E),
.INIT_5F(256'h000000000000000101010202030304040506060708090A0B0C0D0E0F10111213),
.INIT_60(256'h1211100F0E0D0C0B0A0908070606050404030302020101010000000000000000),
.INIT_61(256'h4C4A474543403E3C3A38363432302E2C2A2827252321201E1D1B1A1817161413),
.INIT_62(256'hADAAA6A29F9B9895918E8B8784817E7B7875726F6C696663615E5B595653514E),
.INIT_63(256'h35312C27221E1914100B0702FEF9F5F1ECE8E4E0DCD8D4D0CCC8C4C0BCB8B5B1),
.INIT_64(256'hE4DED8D2CCC7C1BBB5AFAAA49E99938E88837D78736D68635E58534E49443F3A),
.INIT_65(256'hBAB2ABA49D968F88817A736C655E58514A443D363029231D16100A03FDF7F1EB),
.INIT_66(256'hB5ACA49C938B837B736A625A524A423A332B231B130C04FDF5EDE6DED7D0C8C1),
.INIT_67(256'hD5CBC2B8AFA69C938A80776E655C524940372E251D140B02F9F1E8DFD7CEC6BD),
.INIT_68(256'h1A0F04FAEFE5DAD0C5BBB0A69C92877D73695F554B41372D23190F05FCF2E8DF),
.INIT_69(256'h82766B5F53483C3025190E02F7ECE0D5CABEB3A89D92877C71665B50453A2F25),
.INIT_6A(256'h0E01F4E7DACEC1B4A89B8E8275695C5044372B1F1206FAEEE2D6CABEB2A69A8E),
.INIT_6B(256'hBBAD9F918376685A4C3F31231608FBEDE0D3C5B8AB9D908376695B4E4134271A),
.INIT_6C(256'h897A6B5C4D3E30211204F5E6D8C9BBAC9E8F8173645648392B1D0F01F3E5D7C9),
.INIT_6D(256'h7767574737271808F8E9D9C9BAAA9B8B7C6C5D4E3E2F201101F2E3D4C5B6A798),
.INIT_6E(256'h83726150402F1E0EFDECDCCBBBAA9A897969584838271707F7E7D7C7B6A69686),
.INIT_6F(256'hAD9B8977665443311F0EFCEBDAC8B7A5948372604F3E2D1C0BFAE9D7C7B6A594),
.INIT_70(256'hF2DFCDBAA89583715E4C39271503F0DECCBAA89583715F4D3B291706F4E2D0BE),
.INIT_71(256'h523F2B1805F1DECBB8A5917E6B5845321F0CF9E6D3C0AD9A8875624F3D2A1705),
.INIT_72(256'hCBB7A38F7B67533F2B1703EFDBC7B3A08C7864503D291502EEDBC7B4A08D7966),
.INIT_73(256'h5C47321E09F4DFCBB6A18C78634F3A2511FCE8D3BFAB96826D5945301C08F4E0),
.INIT_74(256'h03EDD8C2AD97826D57422D1702EDD7C2AD98826D58432E1904EFDAC5B09B8671),
.INIT_75(256'hBEA8927C664F39230DF7E1CBB6A08A745E48321D07F1DBC6B09A846F59442E18),
.INIT_76(256'h8C755E48311A04EDD7C0AA937C665039230CF6DFC9B39C867059432D1701EAD4),
.INIT_77(256'h6A533C250EF7DFC8B19A836C553E2710F9E2CBB49D867059422B14FDE7D0B9A2),
.INIT_78(256'h58412911FAE2CBB39B846C553D260EF7E0C8B199826B533C250DF6DFC7B09982),
.INIT_79(256'h533B230BF3DBC3AB937C644C341C04ECD4BCA58D755D452E16FEE6CFB79F8870),
.INIT_7A(256'h5A422911F9E0C8B0977F674F361E06EED5BDA58D755D442C14FCE4CCB49C846B),
.INIT_7B(256'h6A52392108EFD7BEA68D745C432B12FAE1C9B0987F674E361D05EDD4BCA38B73),
.INIT_7C(256'h836A51381F06EED5BCA38A725940270EF6DDC4AB937A61493017FEE6CDB49C83),
.INIT_7D(256'hA1886F563D240BF2D9C0A78E755C432A11F8DFC6AD947B634A3118FFE6CDB49B),
.INIT_7E(256'hC2A990775E452C13FAE1C8AE957C634A3118FFE6CDB49B826950371E05ECD3BA),
.INIT_7F(256'hE6CDB49B826950361D04EBD2B9A0876D543B2209F0D7BEA48B725940270EF5DC),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(0))
q0_reg_0
(.ADDRARDADDR({1'b1,sel,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ap_clk),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_q0_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b1}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_q0_reg_0_DOADO_UNCONNECTED[31:8],out[7:0]}),
.DOBDO(NLW_q0_reg_0_DOBDO_UNCONNECTED[31:0]),
.DOPADOP({NLW_q0_reg_0_DOPADOP_UNCONNECTED[3:1],out[8]}),
.DOPBDOP(NLW_q0_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_q0_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(Q[0]),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_q0_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(Q[1]),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(SR),
.RSTREGB(1'b0),
.SBITERR(NLW_q0_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d7" *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* RTL_RAM_BITS = "65536" *)
(* RTL_RAM_NAME = "sine_lut_V_U/nco_sine_lut_V_rom_U/q0" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "4095" *)
(* bram_slice_begin = "9" *)
(* bram_slice_end = "15" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0101010101010101010101000000000000000000000000000000000000000000),
.INIT_01(256'h0303020202020202020202020202020202020202020202010101010101010101),
.INIT_02(256'h0404040404040404040404040404030303030303030303030303030303030303),
.INIT_03(256'h0606060606050505050505050505050505050505050505050504040404040404),
.INIT_04(256'h0707070707070707070707070707070706060606060606060606060606060606),
.INIT_05(256'h0909090909090808080808080808080808080808080808080808080707070707),
.INIT_06(256'h0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A09090909090909090909090909090909),
.INIT_07(256'h0C0C0C0C0C0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A),
.INIT_08(256'h0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C),
.INIT_09(256'h0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0D0D0D0D0D0D0D0D),
.INIT_0A(256'h101010101010101010100F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F),
.INIT_0B(256'h1111111111111111111111111111111111111010101010101010101010101010),
.INIT_0C(256'h1312121212121212121212121212121212121212121212121212111111111111),
.INIT_0D(256'h1414141414141413131313131313131313131313131313131313131313131313),
.INIT_0E(256'h1515151515151515151515151514141414141414141414141414141414141414),
.INIT_0F(256'h1616161616161616161616161616161616151515151515151515151515151515),
.INIT_10(256'h1717171717171717171717171717171717171717171616161616161616161616),
.INIT_11(256'h1818181818181818181818181818181818181818181818171717171717171717),
.INIT_12(256'h1919191919191919191919191919191919191919191919181818181818181818),
.INIT_13(256'h1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1919191919191919191919),
.INIT_14(256'h1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A),
.INIT_15(256'h1C1C1C1C1C1C1C1C1C1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B),
.INIT_16(256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C),
.INIT_17(256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1C1C1C1C),
.INIT_18(256'h1E1E1E1E1E1E1E1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D),
.INIT_19(256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E),
.INIT_1A(256'h1F1F1F1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E),
.INIT_1B(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_1C(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_1D(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_1E(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_1F(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_20(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F20),
.INIT_21(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_22(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_23(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_24(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F),
.INIT_25(256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F),
.INIT_26(256'h1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E),
.INIT_27(256'h1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1E1E1E1E1E1E1E1E),
.INIT_28(256'h1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D),
.INIT_29(256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C),
.INIT_2A(256'h1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C1C1C1C1C1C1C),
.INIT_2B(256'h1A1A1A1A1A1A1A1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B),
.INIT_2C(256'h191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A),
.INIT_2D(256'h1818181818181818191919191919191919191919191919191919191919191919),
.INIT_2E(256'h1717171717171717181818181818181818181818181818181818181818181818),
.INIT_2F(256'h1616161616161616161617171717171717171717171717171717171717171717),
.INIT_30(256'h1515151515151515151515151515161616161616161616161616161616161616),
.INIT_31(256'h1414141414141414141414141414141414141515151515151515151515151515),
.INIT_32(256'h1313131313131313131313131313131313131313131313131414141414141414),
.INIT_33(256'h1111111111121212121212121212121212121212121212121212121212121313),
.INIT_34(256'h1010101010101010101010101011111111111111111111111111111111111111),
.INIT_35(256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1010101010101010101010),
.INIT_36(256'h0D0D0D0D0D0D0D0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F),
.INIT_37(256'h0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D),
.INIT_38(256'h0A0A0A0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C),
.INIT_39(256'h0909090909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A),
.INIT_3A(256'h0707070708080808080808080808080808080808080808080809090909090909),
.INIT_3B(256'h0606060606060606060606060606060707070707070707070707070707070707),
.INIT_3C(256'h0404040404040505050505050505050505050505050505050505060606060606),
.INIT_3D(256'h0303030303030303030303030303030303040404040404040404040404040404),
.INIT_3E(256'h0101010101010101020202020202020202020202020202020202020202030303),
.INIT_3F(256'h0000000000000000000000000000000000000000010101010101010101010101),
.INIT_40(256'h7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F00),
.INIT_41(256'h7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E7E7E7E7E7E),
.INIT_42(256'h7B7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C),
.INIT_43(256'h79797979797A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B),
.INIT_44(256'h7878787878787878787878787878787879797979797979797979797979797979),
.INIT_45(256'h7676767676767777777777777777777777777777777777777777777878787878),
.INIT_46(256'h7575757575757575757575757575757576767676767676767676767676767676),
.INIT_47(256'h7373737373747474747474747474747474747474747474747474747575757575),
.INIT_48(256'h7272727272727272727272727272727373737373737373737373737373737373),
.INIT_49(256'h7071717171717171717171717171717171717171717171717272727272727272),
.INIT_4A(256'h6F6F6F6F6F6F6F6F6F6F70707070707070707070707070707070707070707070),
.INIT_4B(256'h6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F),
.INIT_4C(256'h6C6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E),
.INIT_4D(256'h6B6B6B6B6B6B6B6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C),
.INIT_4E(256'h6A6A6A6A6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B),
.INIT_4F(256'h69696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A6A6A),
.INIT_50(256'h6868686868686868686868686868686868686868686969696969696969696969),
.INIT_51(256'h6767676767676767676767676767676767676767676767686868686868686868),
.INIT_52(256'h6666666666666666666666666666666666666666666666676767676767676767),
.INIT_53(256'h6565656565656565656565656565656565656565656666666666666666666666),
.INIT_54(256'h6464646464646464646464646464646464656565656565656565656565656565),
.INIT_55(256'h6363636363636363636464646464646464646464646464646464646464646464),
.INIT_56(256'h6363636363636363636363636363636363636363636363636363636363636363),
.INIT_57(256'h6262626262626262626262626262626262626262626262626262626263636363),
.INIT_58(256'h6161616161616162626262626262626262626262626262626262626262626262),
.INIT_59(256'h6161616161616161616161616161616161616161616161616161616161616161),
.INIT_5A(256'h6060606161616161616161616161616161616161616161616161616161616161),
.INIT_5B(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_5C(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_5D(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_5E(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_5F(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_60(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_61(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_62(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_63(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_64(256'h6060606060606060606060606060606060606060606060606060606060606060),
.INIT_65(256'h6161616161616161616161616161616161616161616161616161616160606060),
.INIT_66(256'h6161616161616161616161616161616161616161616161616161616161616161),
.INIT_67(256'h6262626262626262626262626262626262626262626262626161616161616161),
.INIT_68(256'h6363636262626262626262626262626262626262626262626262626262626262),
.INIT_69(256'h6363636363636363636363636363636363636363636363636363636363636363),
.INIT_6A(256'h6464646464646464646464646464646464646464646463636363636363636363),
.INIT_6B(256'h6565656565656565656565656565646464646464646464646464646464646464),
.INIT_6C(256'h6666666666666666666665656565656565656565656565656565656565656565),
.INIT_6D(256'h6767676767676767666666666666666666666666666666666666666666666666),
.INIT_6E(256'h6868686868686868676767676767676767676767676767676767676767676767),
.INIT_6F(256'h6969696969696969696968686868686868686868686868686868686868686868),
.INIT_70(256'h6A6A6A6A6A6A6A6A6A6A6A6A6A6A696969696969696969696969696969696969),
.INIT_71(256'h6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6A6A6A6A6A6A6A6A6A6A6A6A6A6A),
.INIT_72(256'h6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6B6B6B6B6B6B6B6B),
.INIT_73(256'h6E6E6E6E6E6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6C6C),
.INIT_74(256'h6F6F6F6F6F6F6F6F6F6F6F6F6F6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E),
.INIT_75(256'h7070707070707070707070707070707070707070706F6F6F6F6F6F6F6F6F6F6F),
.INIT_76(256'h7272727272727271717171717171717171717171717171717171717171717070),
.INIT_77(256'h7373737373737373737373737373737372727272727272727272727272727272),
.INIT_78(256'h7575757574747474747474747474747474747474747474747474737373737373),
.INIT_79(256'h7676767676767676767676767676767575757575757575757575757575757575),
.INIT_7A(256'h7878787877777777777777777777777777777777777777777776767676767676),
.INIT_7B(256'h7979797979797979797979797979797878787878787878787878787878787878),
.INIT_7C(256'h7B7B7B7B7B7B7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A797979797979),
.INIT_7D(256'h7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B),
.INIT_7E(256'h7E7E7E7E7E7E7E7E7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7C7C7C),
.INIT_7F(256'h7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7E7E7E7E7E7E7E7E7E7E7E7E),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(0))
q0_reg_1
(.ADDRARDADDR({1'b1,sel,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ap_clk),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_q0_reg_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_q0_reg_1_DOADO_UNCONNECTED[31:7],out[15:9]}),
.DOBDO(NLW_q0_reg_1_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_q0_reg_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_q0_reg_1_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_q0_reg_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(Q[0]),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_q0_reg_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(Q[1]),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(SR),
.RSTREGB(1'b0),
.SBITERR(NLW_q0_reg_1_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_noise.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU noise channel.
***************************************************************************************************/
`timescale 1ps / 1ps
module apu_noise
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire apu_cycle_pulse_in, // 1 clk pulse on every apu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] noise_out, // noise channel output
output wire active_out // noise channel active (length counter > 0)
);
//
// Envelope
//
wire envelope_generator_wr;
wire envelope_generator_restart;
wire [3:0] envelope_generator_out;
apu_envelope_generator envelope_generator(
.clk_in(clk_in),
.rst_in(rst_in),
.eg_pulse_in(eg_pulse_in),
.env_in(d_in[5:0]),
.env_wr_in(envelope_generator_wr),
.env_restart(envelope_generator_restart),
.env_out(envelope_generator_out)
);
assign envelope_generator_wr = wr_in && (a_in == 2'b00);
assign envelope_generator_restart = wr_in && (a_in == 2'b11);
//
// Timer
//
reg [10:0] q_timer_period;
wire [10:0] d_timer_period;
wire timer_pulse;
always @(posedge clk_in)
begin
if (rst_in)
q_timer_period <= 11'h000;
else
q_timer_period <= d_timer_period;
end
apu_div #(.PERIOD_BITS(12)) timer(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(apu_cycle_pulse_in),
.reload_in(1'b0),
.period_in({ q_timer_period, 1'b0 }),
.pulse_out(timer_pulse)
);
assign d_timer_period = (!wr_in || (a_in != 2'b10)) ? q_timer_period :
(d_in[3:0] == 4'h0) ? 11'h002 :
(d_in[3:0] == 4'h1) ? 11'h004 :
(d_in[3:0] == 4'h2) ? 11'h008 :
(d_in[3:0] == 4'h3) ? 11'h010 :
(d_in[3:0] == 4'h4) ? 11'h020 :
(d_in[3:0] == 4'h5) ? 11'h030 :
(d_in[3:0] == 4'h6) ? 11'h040 :
(d_in[3:0] == 4'h7) ? 11'h050 :
(d_in[3:0] == 4'h8) ? 11'h065 :
(d_in[3:0] == 4'h9) ? 11'h07F :
(d_in[3:0] == 4'hA) ? 11'h0BE :
(d_in[3:0] == 4'hB) ? 11'h0FE :
(d_in[3:0] == 4'hC) ? 11'h17D :
(d_in[3:0] == 4'hD) ? 11'h1FC :
(d_in[3:0] == 4'hE) ? 11'h3F9 :
11'h7F2;
//
// Shift Register
//
reg [14:0] q_lfsr;
wire [14:0] d_lfsr;
reg q_mode;
wire d_mode;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_lfsr <= 15'h0001;
q_mode <= 1'b0;
end
else
begin
q_lfsr <= d_lfsr;
q_mode <= d_mode;
end
end
assign d_lfsr = (timer_pulse) ? { q_lfsr[0] ^ ((q_mode) ? q_lfsr[6] : q_lfsr[1]), q_lfsr[14:1] } :
q_lfsr;
assign d_mode = (wr_in && (a_in == 2'b10)) ? d_in[7] : q_mode;
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
always @(posedge clk_in)
begin
if (rst_in)
q_length_counter_halt <= 1'b0;
else
q_length_counter_halt <= d_length_counter_halt;
end
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[5] : q_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
apu_length_counter length_counter(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign length_counter_wr = wr_in && (a_in == 2'b11);
//
// Output
//
assign noise_out = (q_lfsr[0] && length_counter_en) ? envelope_generator_out : 4'h0;
assign active_out = length_counter_en;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_2_V
`define SKY130_FD_SC_HD__NOR4B_2_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_2_V
`define SKY130_FD_SC_LP__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_2_V
|
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_divide
//
// Description : Parameterized divider megafunction. This function performs a
// divide operation such that denom * quotient + remain = numer
// The function allows for all combinations of signed(two's
// complement) and unsigned inputs. If any of the inputs is
// signed, the output is signed. Otherwise the output is unsigned.
// The function also allows the remainder to be specified as
// always positive (in which case remain >= 0); otherwise remain
// is zero or the same sign as the numerator
// (this parameter is ignored in the case of purely unsigned
// division). Finally the function is also pipelinable.
//
// Limitation : n/a
//
// Results expected: Return quotient and remainder.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_divide (
numer, // The numerator (Required)
denom, // The denominator (Required)
clock, // Clock input for pipelined usage
aclr, // Asynchronous clear signal
clken, // Clock enable for pipelined usage.
quotient, // Quotient (Required)
remain // Remainder (Required)
);
/* verilator lint_off WIDTH */
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthn = 1; // Width of the numer[] and quotient[] port. (Required)
parameter lpm_widthd = 1; // Width of the denom[] and remain[] port. (Required)
parameter lpm_nrepresentation = "UNSIGNED"; // The representation of numer
parameter lpm_drepresentation = "UNSIGNED"; // The representation of denom
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_divide";
parameter lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
// INPUT PORT DECLARATION
input [lpm_widthn-1:0] numer;
input [lpm_widthd-1:0] denom;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_widthn-1:0] quotient;
output [lpm_widthd-1:0] remain;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_widthn-1:0] quotient_pipe [lpm_pipeline+1:0];
reg [lpm_widthd-1:0] remain_pipe [lpm_pipeline+1:0];
reg [lpm_widthn-1:0] tmp_quotient;
reg [lpm_widthd-1:0] tmp_remain;
reg [lpm_widthn-1:0] t_numer;
reg [lpm_widthn-1:0] t_q;
reg [lpm_widthd-1:0] t_denom;
reg [lpm_widthd-1:0] t_r;
reg sign_q;
reg sign_r;
reg sign_n;
reg sign_d;
reg [8*5:1] lpm_remainderpositive;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_widthn > 0
if (lpm_widthn <= 0)
begin
$display("Error! LPM_WIDTHN must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthd > 0
if (lpm_widthd <= 0)
begin
$display("Error! LPM_WIDTHD must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_nrepresentation value
if ((lpm_nrepresentation != "SIGNED") && (lpm_nrepresentation != "UNSIGNED"))
begin
$display("Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_drepresentation value
if ((lpm_drepresentation != "SIGNED") && (lpm_drepresentation != "UNSIGNED"))
begin
$display("Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_remainderpositive value
lpm_remainderpositive = eva.GET_PARAMETER_VALUE(lpm_hint, "LPM_REMAINDERPOSITIVE");
if ((lpm_remainderpositive == "TRUE") &&
(lpm_remainderpositive == "FALSE"))
begin
$display("Error! LPM_REMAINDERPOSITIVE value must be \"TRUE\" or \"FALSE\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] = {lpm_widthn{1'b0}};
remain_pipe[i] = {lpm_widthd{1'b0}};
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(numer or denom or lpm_remainderpositive)
begin
sign_q = 1'b0;
sign_r = 1'b0;
sign_n = 1'b0;
sign_d = 1'b0;
t_numer = numer;
t_denom = denom;
if (lpm_nrepresentation == "SIGNED")
if (numer[lpm_widthn-1] == 1'b1)
begin
t_numer = ~numer + 1; // numer is negative number
sign_n = 1'b1;
end
if (lpm_drepresentation == "SIGNED")
if (denom[lpm_widthd-1] == 1'b1)
begin
t_denom = ~denom + 1; // denom is negative numbrt
sign_d = 1'b1;
end
t_q = t_numer / t_denom; // get quotient
t_r = t_numer % t_denom; // get remainder
sign_q = sign_n ^ sign_d;
sign_r = (t_r != {lpm_widthd{1'b0}}) ? sign_n : 1'b0;
// Pipeline the result
tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q;
tmp_remain = (sign_r == 1'b1) ? (~t_r + 1) : t_r;
// Recalculate the quotient and remainder if remainder is negative number
// and LPM_REMAINDERPOSITIVE=TRUE.
if ((sign_r) && (lpm_remainderpositive == "TRUE"))
begin
tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 );
tmp_remain = tmp_remain + t_denom;
end
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] <= {lpm_widthn{1'b0}};
remain_pipe[i] <= {lpm_widthd{1'b0}};
end
pipe_ptr <= 0;
end
else if (i_clken)
begin
quotient_pipe[pipe_ptr] <= tmp_quotient;
remain_pipe[pipe_ptr] <= tmp_remain;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient;
assign remain = (lpm_pipeline > 0) ? remain_pipe[pipe_ptr] : tmp_remain;
/* verilator lint_on WIDTH */
endmodule // lpm_divide
// END OF MODULE
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dffsle_ns.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// dffrle_ns -- Positive-edge triggered flop with set_l, enable, without scan.
// _____________________________________________________________________________
//
// Description:
// Wrapper around a 'dffe_ns' flip-flop to create a Positive-edge triggered flop
// with set_l, enable, without scan.
// _____________________________________________________________________________
module dffsle_ns (/*AUTOARG*/
// Outputs
q,
// Inputs
din, en, set_l, clk
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input set_l; // set
input clk; // clk
output [SIZE-1:0] q; // output
wire en_wire;
wire [SIZE-1:0] din_wire, q_wire;
// Enable Interpretation. Ultimate interpretation depends on design
//
// set_l en out
//---------------------
// 0 x 1 ; set dominates
// 1 1 din
// 1 0 q
//
//// synopsys sync_set_reset "set_l"
//always @ (posedge clk)
// if (!set_l)
// q[SIZE-1:0] <= {SIZE{1'b1}};
// else if (en)
// q[SIZE-1:0] <= din[SIZE-1:0];
// When 'set_l' is asserted, the value of '1' is forced onto the .din flop input and the .en pin
// is forced on to load the '1' into the flop on the next clock.
assign din_wire[SIZE-1:0] = ((en)? din[SIZE-1:0]: q_wire[SIZE-1:0]) | {SIZE{(~set_l)}};
assign en_wire = en || (~set_l);
dffe_ns #(SIZE) dff_reg (.din(din_wire[SIZE-1:0]), .en(en_wire), .q(q_wire[SIZE-1:0]), .clk(clk));
assign q = q_wire;
endmodule
// Local Variables:
// verilog-library-directories:()
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-module-parents:("jbi_int_arb")
// End:
|
/***************************************************************************************************
** fpga_nes/hw/src/wram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Work RAM module; implements 2KB of on-board WRAM as fpga block RAM.
***************************************************************************************************/
`timescale 1ps / 1ps
module wram(
input clk_in, // system clock
input en_in, // chip enable
input r_nw_in, // read/write select (read: 0, write: 1)
input [10:0] a_in, // memory address
input [ 7:0] d_in, // data input
output [ 7:0] d_out // data output
);
wire wram_bram_we;
wire [7:0] wram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) wram_bram(
.clk(clk_in),
.we(wram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(wram_bram_dout)
);
assign wram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? wram_bram_dout : 8'h00;
endmodule
|
`define bsg_mem_1rw_sync_mask_write_byte_macro(words,bits) \
if (els_p == words && data_width_p == bits) \
begin: macro \
hard_mem_1rw_byte_mask_d``words``_w``bits``_wrapper \
mem \
(.clk_i (clk_i) \
,.reset_i (reset_i) \
,.v_i (v_i) \
,.w_i (w_i) \
,.addr_i (addr_i) \
,.data_i (data_i) \
,.write_mask_i (write_mask_i) \
,.data_o (data_o) \
); \
end: macro
module bsg_mem_1rw_sync_mask_write_byte #( parameter `BSG_INV_PARAM(els_p )
, parameter `BSG_INV_PARAM(data_width_p )
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter write_mask_width_lp = data_width_p>>3
)
( input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [data_width_p-1:0] data_i
, input [write_mask_width_lp-1:0] write_mask_i
, output logic [data_width_p-1:0] data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_1rw_sync_mask_write_byte_macro(512,64) else
// no hardened version found
begin : notmacro
bsg_mem_1rw_sync_mask_write_byte_synth #(.data_width_p(data_width_p), .els_p(els_p))
synth
(.*);
end // block: notmacro
// synopsys translate_off
always_comb
begin
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
end
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
`include "minsoc_defines.v"
module xilinx_dcm(
clk_i,
clk_o
);
//
// Parameters
//
parameter divisor = 2;
input clk_i;
output clk_o;
`ifdef SPARTAN2
`define XILINX_DLL
`elsif VIRTEX
`define XILINX_DLL
`endif // !SPARTAN2/VIRTEX
`ifdef SPARTAN3
`define XILINX_DCM
`elsif VIRTEX2
`define XILINX_DCM
`endif // !SPARTAN3/VIRTEX2
`ifdef SPARTAN6 //SPARTAN3E
`define XILINX_DCM_SP
`elsif SPARTAN3A
`define XILINX_DCM_SP
`endif // !SPARTAN3E/SPARTAN3A
`ifdef VIRTEX4
`define XILINX_DCM_ADV
`define XILINX_DCM_COMPONENT "VIRTEX4"
`elsif VIRTEX5
`define XILINX_DCM_ADV
`define XILINX_DCM_COMPONENT "VIRTEX5"
`endif // !VIRTEX4/VIRTEX5
wire CLKIN_IN;
wire CLKDV_OUT;
assign CLKIN_IN = clk_i;
assign clk_o = CLKDV_OUT;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFB_IN;
wire CLKDV_BUF;
`ifdef XILINX_FPGA
IBUFG CLKIN_IBUFG_INST (
.I(CLKIN_IN),
.O(CLKIN_IBUFG)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
BUFG CLKDV_BUFG_INST (
.I(CLKDV_BUF),
.O(CLKDV_OUT)
);
`ifdef XILINX_DLL
CLKDLL #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF Values
.STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE
) CLKDLL_inst (
.CLK0(CLK0_BUF), // 0 degree DLL CLK output
.CLK180(), // 180 degree DLL CLK output
.CLK270(), // 270 degree DLL CLK output
.CLK2X(), // 2X DLL CLK output
.CLK90(), // 90 degree DLL CLK output
.CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE)
.LOCKED(), // DLL LOCK status output
.CLKFB(CLKFB_IN), // DLL clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL)
.RST(1'b0) // DLL asynchronous reset input
);
`elsif XILINX_DCM
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
`elsif XILINX_DCM_SP
DCM_SP #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(40.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
`elsif XILINX_DCM_ADV
DCM_ADV #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE"
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
.SIM_DEVICE(`XILINX_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5"
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
) DCM_ADV_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
.DRDY(), // Ready output signal from the DRP
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.DADDR(7'h00), // 7-bit address for the DRP
.DCLK(1'b0), // Clock for the DRP
.DEN(1'b0), // Enable input for the DRP
.DI(16'h0000), // 16-bit data input for the DRP
.DWE(1'b0), // Active high allows for writing configuration memory
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
`endif // !XILINX_FPGA
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:44:30 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_rst_clk_wiz_1_100M_0/system_rst_clk_wiz_1_100M_0_sim_netlist.v
// Design : system_rst_clk_wiz_1_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rst_clk_wiz_1_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rst_clk_wiz_1_100M_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "artix7" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
system_rst_clk_wiz_1_100M_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_rst_clk_wiz_1_100M_0_cdc_sync
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_rst_clk_wiz_1_100M_0_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* ORIG_REF_NAME = "lpf" *)
module system_rst_clk_wiz_1_100M_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
system_rst_clk_wiz_1_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
system_rst_clk_wiz_1_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "artix7" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
(* ORIG_REF_NAME = "proc_sys_reset" *)
module system_rst_clk_wiz_1_100M_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
system_rst_clk_wiz_1_100M_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
system_rst_clk_wiz_1_100M_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "sequence_psr" *)
module system_rst_clk_wiz_1_100M_0_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
system_rst_clk_wiz_1_100M_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module system_rst_clk_wiz_1_100M_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// This computes new prime every 5 seconds
// and displays lower 5 bits via LEDs.
module blink (
input clk_12MHz,
output [4:0] LED);
// WLOG=5 (i.e. 32-bit primes) takes a LOT more time to build...
localparam WLOG = 4;
localparam W = 1 << WLOG;
localparam HI = W - 1;
wire rdy, err;
wire [HI:0] res;
reg go;
reg [31:0] clk_count;
reg blink;
wire rst;
wire por_rst;
wire clk;
wire clk_rdy;
// TODO: pass from outside and verify?
localparam F = 16;
clk_gen #(.F(F)) clk_gen_inst (.clk_12MHz(clk_12MHz), .clk(clk), .ready(clk_rdy));
por por_inst(.clk(clk), .rst(por_rst));
assign rst = por_rst || !clk_rdy;
primogen #(.WIDTH_LOG(WLOG)) pg(
.clk(clk),
.go(go),
.rst(rst),
.ready(rdy),
.error(err),
.res(res));
localparam BLINK_COUNT = F * 1000000 * 5; // Every 5 sec.
always @(posedge clk) begin
if (rst) begin
blink <= 0;
clk_count <= 0;
end else begin
if (clk_count == BLINK_COUNT) begin
blink <= 1;
clk_count <= 0;
end else begin
blink <= 0;
clk_count <= clk_count + 1'd1;
end
end
end
always @(posedge clk) begin
if (rst) begin
go <= 0;
end else begin
go <= 0;
// !go - give primogen 1 clock to register inputs
if (rdy && !err && !go && blink) begin
go <= 1;
end
end
end
assign LED[3:0] = res[3:0];
assign LED[4] = err;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_5_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_5_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_5_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_5_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311AI_4_V
`define SKY130_FD_SC_HS__O311AI_4_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311ai_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311AI_4_V
|
//% @file Clock_SR.v
//% @brief This module generate shift register's control clock.
//% @author pyxiong
//%
//% After the last bit is written into shift register, clock clk_sr
//% must stop until start is asserted.
`timescale 1ns / 1ps
module Clock_SR #(parameter WIDTH=170,//% @param input data's width controls thestatus of state machine.
parameter CNT_WIDTH=8, //% @param 2**CNT_WIDTH must be greater than WIDTH.
parameter DIV_WIDTH=6, //% @param width of division factor
parameter COUNT_WIDTH=64 //% @param Width of internal counter, it must be greater than 2**DIV_WIDTH.
)(
input clk_in, //% module's internal control clock.
input rst, //% reset
input[CNT_WIDTH-1:0] count, //% count from 0 to WIDTH+1, controls the total active duration of clk_sr.
input start, //% start signal
input start_tmp, //% one clk(divided) period behind start signal.
input [DIV_WIDTH-1:0] div, //% clock frequency division factor 2**div.
input [COUNT_WIDTH-1:0] counter, //% CLock_Div's internal counter
output reg clk_sr //% shift register's control clock
);
//reg [COUNT_WIDTH-1:0] counter;
reg [1:0] current_state, next_state;
parameter s0 = 2'b01;
parameter s1 = 2'b10;
//parameter s2 = 3'b100;
always@(posedge clk_in or posedge rst)
begin
if(rst)
begin current_state <= s0; end
else
begin current_state <= next_state; end
end
always@(current_state or rst or count or start or start_tmp)
begin
if(rst)
begin next_state = s0; end
else
begin
case(current_state)
s0:next_state=(start==0&&start_tmp==1)?s1:s0;
s1:next_state=(count==WIDTH+1'b1)?s0:s1;
// s2:next_state=s0;
default:next_state=s0;
endcase
end
end
always@(posedge clk_in or posedge rst)
begin
if(rst)
begin
clk_sr<=1;
end
else
begin
case(next_state)
s0:
begin
clk_sr<=1;
end
s1:
begin
clk_sr<=~counter[div-1];
end
default:
begin
clk_sr<=1;
end
endcase
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// //
// Copyright 2013, 2014 Rok Krajnc //
// //
// This file is part of Minimig //
// //
// Minimig is free software; you can redistribute it and/or modify //
// it under the terms of the GNU General Public License as published by //
// the Free Software Foundation; either version 3 of the License, or //
// (at your option) any later version. //
// //
// Minimig is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// This is Cart module with support for HRTmon monitor. //
// This module is based on existing ActionReplay.v module by Jakub Bednarski //
// and code from WinUAE ar.cpp file. The module requires the ctrl firmware //
// to load the special hrtmon.rom file to address 0xa00000. The module //
// requires one 512KB RAM bank. The start address (entry point) is 0xa0000c. //
// TODO : custom registers and CIA registers shadow implemented as in WinUAE. //
// TODO : for better compatibility, load the monitor to $A10000 //
// (requires recompilation!). //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// Changelog //
// RK: //
// 2013-11-27 - initial version //
// 2014-09-27 - cleanup, clock enable added //
// 2015-05-03 - added custom registers mirror //
// //
////////////////////////////////////////////////////////////////////////////////
module cart
(
input wire clk,
input wire clk7_en,
input wire clk7n_en,
input wire cpu_rst,
input wire [ 24-1:1] cpu_address,
input wire [ 24-1:1] cpu_address_in,
input wire _cpu_as,
input wire cpu_rd,
input wire cpu_hwr,
input wire cpu_lwr,
input wire [ 32-1:0] cpu_vbr,
input wire [ 9-1:1] reg_address_in,
input wire [ 16-1:0] reg_data_in,
input wire dbr,
input wire ovl,
input wire freeze,
output wire [ 16-1:0] cart_data_out,
output reg int7 = 1'b0,
output wire sel_cart,
output wire ovr,
// output reg aron = 1'b1
output wire aron
);
//// internal signals ////
reg [32-1:0] nmi_vec_adr=0;
reg freeze_d=0;
wire freeze_req;
wire int7_req;
wire int7_ack;
reg l_int7_req=0;
reg l_int7_ack=0;
reg l_int7=0;
reg active=0;
wire sel_custom_mirror;
wire [16-1:0] nmi_adr_out;
reg [16-1:0] custom_mirror_q;
wire [16-1:0] custom_mirror_out;
reg [16-1:0] custom_mirror [0:256-1];
//// code ////
// cart is activated by writing to its area during bootloading
`define ARON_HACK
`ifndef ARON_HACK
always @ (posedge clk) begin
if (clk7_en) begin
if (cpu_rst && (cpu_address_in[23:19]==5'b1010_0) && cpu_lwr && !aron)
aron <= 1'b1;
end
end
`else
// TODO enable cart from firmware when uploading
assign aron = 1'b1;
`endif
// cart selected
assign sel_cart = ~dbr && (cpu_address_in[23:19]==5'b1010_0); // $A00000
// latch VBR + NMI vector offset
always @ (posedge clk) begin
if (clk7_en) begin
nmi_vec_adr <= #1 cpu_vbr + 32'h0000007c; // $7C = NMI vector offset
end
end
// override decoding of NMI
//assign ovr = active && ~dbr && ~ovl && cpu_rd && (cpu_address_in[23:2]==22'b0000_0000_0000_0000_0111_11);
assign ovr = active && ~dbr && ~ovl && cpu_rd && (cpu_address_in[23:2] == nmi_vec_adr[23:2]);
// custom NMI vector address output
assign nmi_adr_out = ovr ? (!cpu_address_in[1] ? 16'h00a1 : 16'h000c) : 16'h0000;
// freeze button
always @ (posedge clk) begin
if (clk7_en) begin
freeze_d <= freeze;
end
end
assign freeze_req = freeze && ~freeze_d;
// int7 request
assign int7_req = /*aron &&*/ freeze_req;
// level7 interrupt ack cycle, on Amiga interrupt vector number is read from kickstart rom
// A[23:4] all high, A[3:1] vector number
assign int7_ack = &cpu_address_in && ~_cpu_as;
// level 7 interrupt request logic
// interrupt request lines are sampled during S4->S5 transition (falling cpu clock edge)
always @ (posedge clk) begin
if (clk7_en) begin
if (cpu_rst)
int7 <= 1'b0;
else if (int7_req)
int7 <= 1'b1;
else if (int7_ack)
int7 <= 1'b0;
end
end
// latches
always @ (posedge clk) begin
if (clk7_en) begin
l_int7_req <= int7_req;
l_int7_ack <= int7_ack;
end
end
always @ (posedge clk) begin
if (clk7_en) begin
if (cpu_rst)
l_int7 <= 1'b0;
else if (l_int7_req)
l_int7 <= 1'b1;
else if (l_int7_ack && cpu_rd)
l_int7 <= 1'b0;
end
end
// overlay active
always @ (posedge clk) begin
if (clk7_en) begin
if (cpu_rst)
active <= #1 1'b0;
else if (/*aron &&*/ l_int7 && l_int7_ack && cpu_rd)
active <= #1 1'b1;
else if (sel_cart && cpu_rd)
active <= #1 1'b0;
end
end
// custom registers mirror memory
assign sel_custom_mirror = ~dbr && cpu_rd && (cpu_address_in[23:12]==12'b1010_1001_1111); // $A9F000
always @ (posedge clk) begin
if (clk7_en) begin
custom_mirror[reg_address_in] <= #1 reg_data_in;
end
custom_mirror_q <= #1 custom_mirror[cpu_address_in[8:1]];
end
assign custom_mirror_out = sel_custom_mirror ? custom_mirror_q : 16'h0000;
// cart data output
assign cart_data_out = custom_mirror_out | nmi_adr_out;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module timestamp_core #(
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001
) (
input wire CLK,
input wire DI,
input wire EXT_ENABLE,
input wire [63:0] EXT_TIMESTAMP,
output wire [63:0] TIMESTAMP_OUT,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD
);
localparam VERSION = 2;
//output format:
//31-28: ID, 27-24: 0x1, 23-0: 23-0th bit of timestamp data
//31-28: ID, 27-24: 0x2, 23-0: 47-24th bit of timestamp data
//31-28: ID, 27-24: 0x3, 23-16: 0x00, 15-0: 63-48th bit timestamp data
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN, CONF_EXT_ENABLE; //TODO add enable/disable by software
reg CONF_EXT_TIMESTAMP;
reg [7:0] LOST_DATA_CNT;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_EXT_TIMESTAMP <= 0;
CONF_EXT_ENABLE <= 0;
end
else if(BUS_WR) begin
if(BUS_ADD == 2) begin
CONF_EN <= BUS_DATA_IN[0];
CONF_EXT_TIMESTAMP <= BUS_DATA_IN[1];
CONF_EXT_ENABLE <= BUS_DATA_IN[2];
end
end
end
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {5'b0, CONF_EXT_ENABLE, CONF_EXT_TIMESTAMP, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire EN_SYNC;
assign EN_SYNC = CONF_EN | (EXT_ENABLE & CONF_EXT_ENABLE);
reg [7:0] sync_cnt;
always @(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
reg [1:0] DI_FF;
wire DI_SYNC;
always @(posedge CLK) begin
if(RST_SYNC)
DI_FF <=2'b0;
else
DI_FF <= {DI_FF[0],DI};
end
assign DI_SYNC = ~DI_FF[1] & DI_FF[0];
reg [63:0] curr_timestamp;
always @(posedge CLK) begin
if(RST_SYNC)
curr_timestamp <= 0;
else
curr_timestamp <= curr_timestamp + 1;
end
reg [63:0] timestamp_out;
reg [1:0] cdc_fifo_write_reg;
reg [3:0] bit_cnt;
always @(posedge CLK) begin // TODO better fo separate cdc_fifo_write_reg?
if(RST_SYNC | ~EN_SYNC) begin
timestamp_out <= 0;
cdc_fifo_write_reg <= 0;
end
else if(DI_SYNC & cdc_fifo_write_reg==0) begin
if (CONF_EXT_TIMESTAMP)
timestamp_out <= EXT_TIMESTAMP;
else
timestamp_out <= curr_timestamp;
cdc_fifo_write_reg <= 1;
end
else if (cdc_fifo_write_reg==1)
cdc_fifo_write_reg <= 2;
else
cdc_fifo_write_reg <= 0;
end
assign TIMESTAMP_OUT = timestamp_out;
wire [63:0] cdc_data_in;
assign cdc_data_in = timestamp_out;
wire cdc_fifo_write;
assign cdc_fifo_write = cdc_fifo_write_reg[1];
wire fifo_full,fifo_write,cdc_fifo_empty;
wire wfull;
always @(posedge CLK) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != 8'b1111_1111)
LOST_DATA_CNT <= LOST_DATA_CNT + 1;
end
wire [63:0] cdc_data_out;
wire cdc_fifo_read;
cdc_syncfifo #(
.DSIZE(64),
.ASIZE(8)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(cdc_data_in),
.winc(cdc_fifo_write),
.wclk(CLK),
.wrst(RST_LONG),
.rinc(cdc_fifo_read),
.rclk(BUS_CLK),
.rrst(RST_LONG)
);
reg [1:0] byte2_cnt, byte2_cnt_prev;
always @(posedge BUS_CLK)
byte2_cnt_prev <= byte2_cnt;
assign cdc_fifo_read = (byte2_cnt_prev==0 & byte2_cnt!=0);
assign fifo_write = byte2_cnt_prev != 0;
always @(posedge BUS_CLK)
if(RST)
byte2_cnt <= 0;
else if(!cdc_fifo_empty && !fifo_full && byte2_cnt == 0)
byte2_cnt <= 3;
else if (!fifo_full & byte2_cnt != 0)
byte2_cnt <= byte2_cnt - 1;
reg [63:0] data_buf;
always @(posedge BUS_CLK)
if(cdc_fifo_read)
data_buf <= cdc_data_out;
wire [31:0] fifo_write_data_byte [3:0];
assign fifo_write_data_byte[0] = {IDENTIFIER,4'b0001,data_buf[23:0]};
assign fifo_write_data_byte[1] = {IDENTIFIER,4'b0010,data_buf[47:24]};
assign fifo_write_data_byte[2] = {IDENTIFIER,4'b0011,8'b0,data_buf[63:48]};
wire [31:0] fifo_data_in;
assign fifo_data_in = fifo_write_data_byte[byte2_cnt];
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(1024)
) fifo_i (
.clk(BUS_CLK),
.reset(RST_LONG | BUS_RST),
.write(fifo_write),
.read(FIFO_READ),
.data_in(fifo_data_in),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]),
.size()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_SYMBOL_V
`define SKY130_FD_SC_HS__MUX2I_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_PP_BLACKBOX_V
|
/**
\file "shoelace.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: shoelace.v,v 1.3 2010/04/06 00:08:37 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`define inv_delay 0.010
`include "clkgen.v"
/* the humble inverter */
module inverter (in, out);
parameter DELAY=`inv_delay;
input in;
output out;
reg __o;
wire out = __o;
always @(in)
begin
#DELAY __o <= ~in;
end
endmodule
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
/* our top-level */
module TOP;
wire in, in1, in2, in3, in4;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
/**
assign in1 = ~out0;
assign in2 = ~out1;
assign in3 = ~out2;
assign in4 = ~out3;
**/
inverter q0(out0, in1);
inverter q1(out1, in2);
inverter q2(out2, in3);
inverter q3(out3, in4);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_confirm_connections();
$prsim_verbose_transport(1);
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.in1", "in1");
$to_prsim("TOP.in2", "in2");
$to_prsim("TOP.in3", "in3");
$to_prsim("TOP.in4", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #5 $finish;
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
//Additional connections
//Serial
output ext_tx, //FPGA Tx
input ext_rx, //FPGA Rx
//Spi
output ext_miso, //35
input ext_mosi, //34
input ext_ss, //40
input ext_sck, //41
input [NUM_ULTRASONICS-1:0] echo, //ultrasonic received dur.
output [NUM_ULTRASONICS-1:0] trigger //ultrasonic start
);
wire rst = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
//assign ext_miso = 1'bz;
assign ext_tx = 1'bz;
//Setup clock
wire clk_10us;
clk_divider #(.DIV(500)) div_clk10us(
.clk(clk),
.rst(rst),
.div_clk(clk_10us));
//Setup hcsr04s
wire measure_dist;
assign measure_dist = 1'b1;
parameter NUM_ULTRASONICS = 9;
//Each distance takes 16 bits
wire [NUM_ULTRASONICS * 16 -1:0] us_dists;
wire [NUM_ULTRASONICS - 1: 0] us_dists_valid;
genvar i;
generate
for (i = 0; i < NUM_ULTRASONICS; i=i+1) begin: us_gen_loop
hcsr04 #(
.TRIGGER_DURATION(1),
.MAX_COUNT(3800)
) ultrasonic(
.clk(clk),
.tclk(clk_10us),
.rst(rst),
.measure(measure_dist),
.echo(echo[i]),
.ticks(us_dists[16*i+16 - 1: 16*i]),
.valid(us_dists_valid[i]),
.trigger(trigger[i]));
end
endgenerate
//Setup comm protocol
localparam ADDR_SPACE = 64;
wire [8*ADDR_SPACE -1:0] mojo_com_rx_arr;
wire [8*ADDR_SPACE -1:0] mojo_com_tx_arr;
//assign mojo_com_tx_arr = {8'hde,8'had,8'hbe,8'hef, us_dists};
assign mojo_com_tx_arr = {300'b0,8'hde,8'had,8'hbe,8'hef, us_dists[15:0]};
wire mojo_com_rx_busy, mojo_com_new_rx, mojo_com_tx_busy;
mojo_com #(
.ADDR_SPACE(ADDR_SPACE))
com_unit(
.clk(clk),
.rst(rst),
//SPI wires
.ss(ext_ss),
.sck(ext_sck),
.mosi(ext_mosi),
.miso(ext_miso),
//Interface wires
.rx_arr(mojo_com_rx_arr),
.rx_busy(mojo_com_rx_busy),
.new_rx(mojo_com_new_rx),
.tx_arr(mojo_com_tx_arr),
.tx_busy(mojo_com_tx_busy)
);
assign led = mojo_com_rx_arr[15:8];
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:18:02 06/09/2015
// Design Name: aesmodule
// Module Name: F:/Projects/Xilinx/Rijndael/test_aesmodule.v
// Project Name: Rijndael
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: aesmodule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_aesmodule;
// Inputs
reg [127:0] in;
reg decr;
reg clk;
reg reset;
// Outputs
wire [127:0] out;
wire ready;
// Instantiate the Unit Under Test (UUT)
aesmodule uut (
.out(out),
.ready(ready),
.in(in),
.decr(decr),
.clk(clk),
.reset(reset)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
// Initialize Inputs
decr = 0;
reset = 0;
in = 128'h3243f6a8_885a308d_313198a2_e0370734;
//in = 128'h3925841d_02dc09fb_dc118597_196a0b32;
#2;
reset = 1;
#3;
reset = 0;
#5;
// Add stimulus here
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A22OI_FUNCTIONAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_BLACKBOX_V
/**
* top_power_hvc_wpad: A power pad with an ESD high-voltage clamp.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpad (
P_PAD ,
AMUXBUS_A ,
AMUXBUS_B ,
OGC_HVC ,
DRN_HVC ,
SRC_BDY_HVC,
P_CORE ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
inout P_PAD ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout OGC_HVC ;
inout DRN_HVC ;
inout SRC_BDY_HVC;
inout P_CORE ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_2_V
`define SKY130_FD_SC_HD__A41O_2_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41o_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41o_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_2_V
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
// 000 AND
// 001 OR
// 010 ADD
// 110 Sub
// 111 Less than
module proj3_testbench;
reg [2:0] opcode;
reg [15:0] A, B;
reg clk;
wire [15:0] out, out2;
ALU16 A1(A,B,opcode,out);
ALU16_LA A2(A, B, opcode, out2);
always
#15 clk =~clk;
initial begin
clk = 1'b0;
A = 4'h0001;
B = 4'h0003;
opcode = 3'b000;
end
always @(posedge clk)
A=A+1;
endmodule
|
`include "defines.v"
module div (
input wire clk,
input wire rst,
input wire signed_div_i,
input wire[`RegBus] opdata1_i, // 被除数
input wire[`RegBus] opdata2_i, // 除数
input wire start_i,
input wire annul_i,
output reg[`DoubleRegBus] result_o,
output reg result_ready_o
);
wire[32:0] div_temp;
reg[5:0] cnt;
reg[`DoubleRegBus] dividend;
reg[1:0] state; // DivFree, DivOn, DivByZero, DivEnd 状态
reg[`RegBus] divisor;
wire[`RegBus] temp_op1;
wire[`RegBus] temp_op2;
// reg[1:0] new_state;
assign div_temp = dividend[63:31] - divisor;
// always @(posedge clk) begin
// if (rst == `RstEnable) begin
// state <= `DivFree;
// new_state <= `DivFree;
// end
// else begin
// state <= new_state;
// end
// end
assign temp_op1 = (signed_div_i == `DivSigned && opdata1_i[31] == 1'b1) ? (~opdata1_i + 1) : opdata1_i;
assign temp_op2 = (signed_div_i == `DivSigned && opdata2_i[31] == 1'b1) ? (~opdata2_i + 1) : opdata2_i;
// always @(*) begin
always @(posedge clk) begin
if (rst == `RstEnable) begin
state <= `DivFree;
result_ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord, `ZeroWord};
end
else begin
case (state)
`DivFree: begin
if (start_i == `DivStart && annul_i == `DivNotAnnul) begin
if (opdata2_i == `ZeroWord) begin
state <= `DivByZero;
end
else begin
state <= `DivOn;
// new_state <= `DivOn;
cnt <= 0;
// if (signed_div_i == `DivSigned && opdata1_i[31] == 1'b1) begin
// temp_op1 <= ~opdata1_i + 1;
// end
// else begin
// temp_op1 <= opdata1_i;
// end
// if (signed_div_i == `DivSigned && opdata2_i[31] == 1'b1) begin
// temp_op2 <= ~opdata2_i + 1;
// end
// else begin
// temp_op2 <= opdata2_i;
// end
// test
// temp_op1 <= 32'h1111;
// temp_op2 <= 32'h2222;
dividend <= {`ZeroWord, temp_op1};
divisor <= temp_op2;
end
end
else begin
result_ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord, `ZeroWord};
end
end
`DivOn: begin
if (annul_i == `DivNotAnnul) begin
if (cnt != 32) begin // 试商法还未结束
if (div_temp[32] == 1'b1) begin
// 表示 (minuted - n) 的结果小于 0
// dividend 左移一位
dividend <= {dividend[62:0], 1'b0};
end
else begin
dividend <= {div_temp[31:0], dividend[30:0], 1'b1};
end
cnt <= cnt + 1;
end
else begin // 试商法结束
if (signed_div_i == `DivSigned && (opdata1_i[31] ^ opdata2_i[31]) == 1'b1) begin
dividend[31:0] <= ~dividend[31:0] + 1;
end
if (signed_div_i == `DivSigned && opdata1_i[31] == 1'b1) begin
dividend[63:32] <= ~dividend[63:32] + 1;
end
state <= `DivEnd;
cnt <= 0;
end
end
else begin
state <= `DivFree;
end
end
`DivByZero: begin
dividend <= {`ZeroWord, `ZeroWord};
state <= `DivEnd;
end
`DivEnd: begin
result_o <= {dividend[63:32], dividend[31:0]};
result_ready_o <= `DivResultReady;
if (start_i == `DivNotStart) begin
state <= `DivFree;
result_ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord, `ZeroWord};
end
end
endcase
end
end
endmodule |
//=========================================================
// Integrated Instruction/Data memory (seperate ports)
//=========================================================
`define EOF 32'hFFFF_FFFF
`define NULL 0
`timescale 1ns/100ps
module Memory(
inst_addr,
instr,
data_addr,
data_in,
mem_read,
mem_write,
data_out
);
// Interface
input [4*8:1] inst_addr;
output [31:0] instr;
input [4*8:1] data_addr;
input [31:0] data_in;
input mem_read;
input mem_write;
output [31:0] data_out;
// Memory is byte-addressable, instructions are word-aligned
// Memory with 2k 8-bit
// Data address range: 0x0000 ~ 0x2FFC
// Instruction address range: 0x3000 ~ 0x3FFC
parameter MEM_SIZE=32'h00004000;
integer i;
integer file, r;
reg [7:0] memory [0:MEM_SIZE-1];
reg [31:0] data_addr_reg, inst_addr_reg;
reg [12*8:1] rest;
initial
begin : file_block
// for(i=0; i<2048; i=i+1) begin
// memory[i] = 8'b0;
// end
file = $fopen("MinMax.hexdump","r");
if (file == `NULL)
disable file_block;
for (i = 0; i < 3 ; i=i+1)
begin
r = $fscanf(file, "%h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h\n", data_addr_reg, memory[data_addr_reg], memory[data_addr_reg+1], memory[data_addr_reg+2], memory[data_addr_reg+3], memory[data_addr_reg+4], memory[data_addr_reg+5], memory[data_addr_reg+6], memory[data_addr_reg+7], memory[data_addr_reg+8], memory[data_addr_reg+9], memory[data_addr_reg+10], memory[data_addr_reg+11], memory[data_addr_reg+12], memory[data_addr_reg+13], memory[data_addr_reg+14], memory[data_addr_reg+15]);
end // for first loop
r = $fscanf(file, "%s\n", rest);
for (i = 0; i < 8 ; i=i+1)
begin
r = $fscanf(file, "%h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h\n", inst_addr_reg, memory[inst_addr_reg], memory[inst_addr_reg+1], memory[inst_addr_reg+2], memory[inst_addr_reg+3], memory[inst_addr_reg+4], memory[inst_addr_reg+5], memory[inst_addr_reg+6], memory[inst_addr_reg+7], memory[inst_addr_reg+8], memory[inst_addr_reg+9], memory[inst_addr_reg+10], memory[inst_addr_reg+11], memory[inst_addr_reg+12], memory[inst_addr_reg+13], memory[inst_addr_reg+14], memory[inst_addr_reg+15]);
end // for second loop
$fclose(file);
end // initial
// Read data
assign data_out = (mem_read) ? {memory[data_addr+3], memory[data_addr+2], memory[data_addr+1], memory[data_addr]} : 32'b0;
//write data
always @ (posedge mem_write or data_addr or data_in)
begin
if (mem_write ==1) begin
memory[data_addr+3] <= data_in[31:24];
memory[data_addr+2] <= data_in[23:16];
memory[data_addr+1] <= data_in[15:8];
memory[data_addr] <= data_in[7:0];
end
end
// Read instruction
assign instr = {memory[inst_addr+3], memory[inst_addr+2], memory[inst_addr+1], memory[inst_addr]} ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HS__AND4BB_FUNCTIONAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4bb (
VPWR,
VGND,
X ,
A_N ,
B_N ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
// Local signals
wire D nor0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_FUNCTIONAL_V |
(** * Sub: Subtyping *)
Require Import SfLib.
Require Import Maps.
Require Import Types.
(* ###################################################### *)
(** * Concepts *)
(** We now turn to the study of _subtyping_, a key feature
needed to support the object-oriented programming style. *)
(* ###################################################### *)
(** ** A Motivating Example *)
(** Suppose we are writing a program involving two record types
defined as follows:
Person = {name:String, age:Nat}
Student = {name:String, age:Nat, gpa:Nat}
*)
(** In the simply typed lamdba-calculus with records, the term
(\r:Person. (r.age)+1) {name="Pat",age=21,gpa=1}
is not typable, since it applies a function that wants a one-field
record to an argument that actually provides two fields, while the
[T_App] rule demands that the domain type of the function being
applied must match the type of the argument precisely.
But this is silly: we're passing the function a _better_ argument
than it needs! The only thing the body of the function can
possibly do with its record argument [r] is project the field [age]
from it: nothing else is allowed by the type, and the presence or
absence of an extra [gpa] field makes no difference at all. So,
intuitively, it seems that this function should be applicable to
any record value that has at least an [age] field.
More generally, a record with more fields is "at least as good in
any context" as one with just a subset of these fields, in the
sense that any value belonging to the longer record type can be
used _safely_ in any context expecting the shorter record type. If
the context expects something with the shorter type but we actually
give it something with the longer type, nothing bad will
happen (formally, the program will not get stuck).
The principle at work here is called _subtyping_. We say that "[S]
is a subtype of [T]", written [S <: T], if a value of type [S] can
safely be used in any context where a value of type [T] is
expected. The idea of subtyping applies not only to records, but
to all of the type constructors in the language -- functions,
pairs, etc. *)
(** ** Subtyping and Object-Oriented Languages *)
(** Subtyping plays a fundamental role in many programming
languages -- in particular, it is closely related to the notion of
_subclassing_ in object-oriented languages.
An _object_ in Java, C[#], etc. can be thought of as a record,
some of whose fields are functions ("methods") and some of whose
fields are data values ("fields" or "instance variables").
Invoking a method [m] of an object [o] on some arguments [a1..an]
roughly consists of projecting out the [m] field of [o] and
applying it to [a1..an].
The type of an object is called a _class_ -- or, in some
languages, an _interface_. It describes which methods and which
data fields the object offers. Classes and interfaces are related
by the _subclass_ and _subinterface_ relations. An object
belonging to a subclass (or subinterface) is required to provide
all the methods and fields of one belonging to a superclass (or
superinterface), plus possibly some more.
The fact that an object from a subclass can be used in place of
one from a superclass provides a degree of flexibility that is is
extremely handy for organizing complex libraries. For example, a
GUI toolkit like Java's Swing framework might define an abstract
interface [Component] that collects together the common fields and
methods of all objects having a graphical representation that can
be displayed on the screen and interact with the user, such as the
buttons, checkboxes, and scrollbars of a typical GUI. A method
that relies only on this common interface can now be applied to
any of these objects.
Of course, real object-oriented languages include many other
features besides these. For example, fields can be updated.
Fields and methods can be declared [private]. Classes can give
_initializers_ that are used when constructing objects. Code in
subclasses can cooperate with code in superclasses via
_inheritance_. Classes can have static methods and fields. Etc.,
etc.
To keep things simple here, we won't deal with any of these
issues -- in fact, we won't even talk any more about objects or
classes. (There is a lot of discussion in [Pierce 2002], if
you are interested.) Instead, we'll study the core concepts
behind the subclass / subinterface relation in the simplified
setting of the STLC. *)
(** ** The Subsumption Rule *)
(** Our goal for this chapter is to add subtyping to the simply typed
lambda-calculus (with some of the basic extensions from [MoreStlc]).
This involves two steps:
- Defining a binary _subtype relation_ between types.
- Enriching the typing relation to take subtyping into account.
The second step is actually very simple. We add just a single rule
to the typing relation: the so-called _rule of subsumption_:
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
This rule says, intuitively, that it is OK to "forget" some of
what we know about a term. *)
(** For example, we may know that [t] is a record with two
fields (e.g., [S = {x:A->A, y:B->B}]), but choose to forget about
one of the fields ([T = {y:B->B}]) so that we can pass [t] to a
function that requires just a single-field record. *)
(** ** The Subtype Relation *)
(** The first step -- the definition of the relation [S <: T] -- is
where all the action is. Let's look at each of the clauses of its
definition. *)
(** *** Structural Rules *)
(** To start off, we impose two "structural rules" that are
independent of any particular type constructor: a rule of
_transitivity_, which says intuitively that, if [S] is
better (richer, safer) than [U] and [U] is better than [T],
then [S] is better than [T]...
S <: U U <: T
---------------- (S_Trans)
S <: T
... and a rule of _reflexivity_, since certainly any type [T] is
as good as itself:
------ (S_Refl)
T <: T
*)
(** *** Products *)
(** Now we consider the individual type constructors, one by one,
beginning with product types. We consider one pair to be a subtype
of another if each of its components is.
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1 * S2 <: T1 * T2
*)
(** *** Arrows *)
(** The subtyping rule for arrows is a little less intuitive.
Suppose we have functions [f] and [g] with these types:
f : C -> Student
g : (C->Person) -> D
That is, [f] is a function that yields a record of type [Student],
and [g] is a (higher-order) function that expects its argument to be
a function yielding a record of type [Person]. Also suppose that
[Student] is a subtype of [Person]. Then the application [g f] is
safe even though their types do not match up precisely, because
the only thing [g] can do with [f] is to apply it to some
argument (of type [C]); the result will actually be a [Student],
while [g] will be expecting a [Person], but this is safe because
the only thing [g] can then do is to project out the two fields
that it knows about ([name] and [age]), and these will certainly
be among the fields that are present.
This example suggests that the subtyping rule for arrow types
should say that two arrow types are in the subtype relation if
their results are:
S2 <: T2
---------------- (S_Arrow_Co)
S1 -> S2 <: S1 -> T2
We can generalize this to allow the arguments of the two arrow
types to be in the subtype relation as well:
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1 -> S2 <: T1 -> T2
But notice that the argument types are subtypes "the other way round":
in order to conclude that [S1->S2] to be a subtype of [T1->T2], it
must be the case that [T1] is a subtype of [S1]. The arrow
constructor is said to be _contravariant_ in its first argument
and _covariant_ in its second.
Here is an example that illustrates this:
f : Person -> C
g : (Student -> C) -> D
The application [g f] is safe, because the only thing the body of
[g] can do with [f] is to apply it to some argument of type
[Student]. Since [f] requires records having (at least) the
fields of a [Person], this will always work. So [Person -> C] is a
subtype of [Student -> C] since [Student] is a subtype of
[Person].
The intuition is that, if we have a function [f] of type [S1->S2],
then we know that [f] accepts elements of type [S1]; clearly, [f]
will also accept elements of any subtype [T1] of [S1]. The type of
[f] also tells us that it returns elements of type [S2]; we can
also view these results belonging to any supertype [T2] of
[S2]. That is, any function [f] of type [S1->S2] can also be
viewed as having type [T1->T2]. *)
(** *** Records *)
(** What about subtyping for record types? *)
(** The basic intuition is that it is always safe to use a "bigger"
record in place of a "smaller" one. That is, given a record type,
adding extra fields will always result in a subtype. If some code
is expecting a record with fields [x] and [y], it is perfectly safe
for it to receive a record with fields [x], [y], and [z]; the [z]
field will simply be ignored. For example,
{name:String, age:Nat, gpa:Nat} <: {name:String, age:Nat}
{name:String, age:Nat} <: {name:String} {name:String} <: {}
This is known as "width subtyping" for records. *)
(** We can also create a subtype of a record type by replacing the type
of one of its fields with a subtype. If some code is expecting a
record with a field [x] of type [T], it will be happy with a record
having a field [x] of type [S] as long as [S] is a subtype of
[T]. For example,
{x:Student} <: {x:Person}
This is known as "depth subtyping". *)
(** Finally, although the fields of a record type are written in a
particular order, the order does not really matter. For example,
{name:String,age:Nat} <: {age:Nat,name:String}
This is known as "permutation subtyping". *)
(** We _could_ formalize these requirements in a single subtyping rule
for records as follows:
forall jk in j1..jn,
exists ip in i1..im, such that
jk=ip and Sp <: Tk
---------------------------------- (S_Rcd)
{i1:S1...im:Sm} <: {j1:T1...jn:Tn}
That is, the record on the left should have all the field labels of
the one on the right (and possibly more), while the types of the
common fields should be in the subtype relation.
However, this rule is rather heavy and hard to read, so it is often
decomposed into three simpler rules, which can be combined using
[S_Trans] to achieve all the same effects. *)
(** First, adding fields to the end of a record type gives a subtype:
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
We can use [S_RcdWidth] to drop later fields of a multi-field
record while keeping earlier fields, showing for example that
[{age:Nat,name:String} <: {name:String}]. *)
(** Second, subtyping can be applied inside the components of a compound
record type:
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
For example, we can use [S_RcdDepth] and [S_RcdWidth] together to
show that [{y:Student, x:Nat} <: {y:Person}]. *)
(** Third, subtyping can reorder fields. For example, we
want [{name:String, gpa:Nat, age:Nat} <: Person]. (We
haven't quite achieved this yet: using just [S_RcdDepth] and
[S_RcdWidth] we can only drop fields from the _end_ of a record
type.) So we add:
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
*)
(** It is worth noting that full-blown language designs may choose not
to adopt all of these subtyping rules. For example, in Java:
- A subclass may not change the argument or result types of a
method of its superclass (i.e., no depth subtyping or no arrow
subtyping, depending how you look at it).
- Each class member (field or method) can be assigned a single
index, adding new indices "on the right" as more members are
added in subclasses (i.e., no permutation for classes).
- A class may implement multiple interfaces -- so-called "multiple
inheritance" of interfaces (i.e., permutation is allowed for
interfaces). *)
(** **** Exercise: 2 stars, recommended (arrow_sub_wrong) *)
(** Suppose we had incorrectly defined subtyping as covariant on both
the right and the left of arrow types:
S1 <: T1 S2 <: T2
-------------------- (S_Arrow_wrong)
S1 -> S2 <: T1 -> T2
Give a concrete example of functions [f] and [g] with the following types...
f : Student -> Nat
g : (Person -> Nat) -> Nat
... such that the application [g f] will get stuck during
execution.
[] *)
(** *** Top *)
(** Finally, it is convenient to give the subtype relation a maximum
element -- a type that lies above every other type and is
inhabited by all (well-typed) values. We do this by adding to the
language one new type constant, called [Top], together with a
subtyping rule that places it above every other type in the
subtype relation:
-------- (S_Top)
S <: Top
The [Top] type is an analog of the [Object] type in Java and C[#]. *)
(* ############################################### *)
(** *** Summary *)
(** In summary, we form the STLC with subtyping by starting with the
pure STLC (over some set of base types) and then...
- adding a base type [Top],
- adding the rule of subsumption
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
to the typing relation, and
- defining a subtype relation as follows:
S <: U U <: T
---------------- (S_Trans)
S <: T
------ (S_Refl)
T <: T
-------- (S_Top)
S <: Top
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1 * S2 <: T1 * T2
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1 -> S2 <: T1 -> T2
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
*)
(* ############################################### *)
(** ** Exercises *)
(** **** Exercise: 1 star, optional (subtype_instances_tf_1) *)
(** Suppose we have types [S], [T], [U], and [V] with [S <: T]
and [U <: V]. Which of the following subtyping assertions
are then true? Write _true_ or _false_ after each one.
([A], [B], and [C] here are base types.)
- [T->S <: T->S]
- [Top->U <: S->Top]
- [(C->C) -> (A*B) <: (C->C) -> (Top*B)]
- [T->T->U <: S->S->V]
- [(T->T)->U <: (S->S)->V]
- [((T->S)->T)->U <: ((S->T)->S)->V]
- [S*V <: T*U]
[] *)
(** **** Exercise: 2 stars (subtype_order) *)
(** The following types happen to form a linear order with respect to subtyping:
- [Top]
- [Top -> Student]
- [Student -> Person]
- [Student -> Top]
- [Person -> Student]
Write these types in order from the most specific to the most general.
Where does the type [Top->Top->Student] fit into this order?
[] *)
(** **** Exercise: 1 star (subtype_instances_tf_2) *)
(** Which of the following statements are true? Write _true_ or
_false_ after each one.
forall S T,
S <: T ->
S->S <: T->T
forall S,
S <: A->A ->
exists T,
S = T->T /\ T <: A
forall S T1 T2,
(S <: T1 -> T2) ->
exists S1 S2,
S = S1 -> S2 /\ T1 <: S1 /\ S2 <: T2
exists S,
S <: S->S
exists S,
S->S <: S
forall S T1 T2,
S <: T1*T2 ->
exists S1 S2,
S = S1*S2 /\ S1 <: T1 /\ S2 <: T2
[] *)
(** **** Exercise: 1 star (subtype_concepts_tf) *)
(** Which of the following statements are true, and which are false?
- There exists a type that is a supertype of every other type.
- There exists a type that is a subtype of every other type.
- There exists a pair type that is a supertype of every other
pair type.
- There exists a pair type that is a subtype of every other
pair type.
- There exists an arrow type that is a supertype of every other
arrow type.
- There exists an arrow type that is a subtype of every other
arrow type.
- There is an infinite descending chain of distinct types in the
subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a subtype of [Si].
- There is an infinite _ascending_ chain of distinct types in
the subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a supertype of [Si].
[] *)
(** **** Exercise: 2 stars (proper_subtypes) *)
(** Is the following statement true or false? Briefly explain your
answer.
forall T,
~(exists n, T = TBase n) ->
exists S,
S <: T /\ S <> T
[] *)
(** **** Exercise: 2 stars (small_large_1) *)
(**
- What is the _smallest_ type [T] ("smallest" in the subtype
relation) that makes the following assertion true? (Assume we
have [Unit] among the base types and [unit] as a constant of this
type.)
empty |- (\p:T*Top. p.fst) ((\z:A.z), unit) : A->A
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars (small_large_2) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
empty |- (\p:(A->A * B->B). p) ((\z:A.z), (\z:B.z)) : T
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars, optional (small_large_3) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
a:A |- (\p:(A*T). (p.snd) (p.fst)) (a , \z:A.z) : A
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars (small_large_4) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
exists S,
empty |- (\p:(A*T). (p.snd) (p.fst)) : S
- What is the _largest_ type [T] that makes the same
assertion true?
[] *)
(** **** Exercise: 2 stars (smallest_1) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
exists S, exists t,
empty |- (\x:T. x x) t : S
]]
[] *)
(** **** Exercise: 2 stars (smallest_2) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
empty |- (\x:Top. x) ((\z:A.z) , (\z:B.z)) : T
]]
[] *)
(** **** Exercise: 3 stars, optional (count_supertypes) *)
(** How many supertypes does the record type [{x:A, y:C->C}] have? That is,
how many different types [T] are there such that [{x:A, y:C->C} <:
T]? (We consider two types to be different if they are written
differently, even if each is a subtype of the other. For example,
[{x:A,y:B}] and [{y:B,x:A}] are different.)
[] *)
(** **** Exercise: 2 stars (pair_permutation) *)
(** The subtyping rule for product types
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1*S2 <: T1*T2
intuitively corresponds to the "depth" subtyping rule for records.
Extending the analogy, we might consider adding a "permutation" rule
--------------
T1*T2 <: T2*T1
for products. Is this a good idea? Briefly explain why or why not.
[] *)
(* ###################################################### *)
(** * Formal Definitions *)
(** Most of the definitions needed to formalize what we've discussed
above -- in particular, the syntax and operational semantics of
the language -- are identical to what we saw in the last chapter.
We just need to extend the typing relation with the subsumption
rule and add a new [Inductive] definition for the subtyping
relation. Let's first do the identical bits. *)
(* ###################################################### *)
(** ** Core Definitions *)
(* ################################### *)
(** *** Syntax *)
(** In the rest of the chapter, we formalize just base types,
booleans, arrow types, [Unit], and [Top], omitting record types
and leaving product types as an exercise. For the sake of more
interesting examples, we'll add an arbitrary set of base types
like [String], [Float], etc. (Since they are just for examples,
we won't bother adding any operations over these base types, but
we could easily do so.) *)
Inductive ty : Type :=
| TTop : ty
| TBool : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
| TUnit : ty
.
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tunit : tm
.
(* ################################### *)
(** *** Substitution *)
(** The definition of substitution remains exactly the same as for the
pure STLC. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if beq_id x y then s else t
| tabs y T t1 =>
tabs y T (if beq_id x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
tunit
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################### *)
(** *** Reduction *)
(** Likewise the definitions of the [value] property and the [step]
relation. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse
| v_unit :
value tunit
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
(* ###################################################################### *)
(** ** Subtyping *)
(** Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(** The definition of subtyping is just what we sketched in the
motivating discussion. *)
Reserved Notation "T '<:' U" (at level 40).
Inductive subtype : ty -> ty -> Prop :=
| S_Refl : forall T,
T <: T
| S_Trans : forall S U T,
S <: U ->
U <: T ->
S <: T
| S_Top : forall S,
S <: TTop
| S_Arrow : forall S1 S2 T1 T2,
T1 <: S1 ->
S2 <: T2 ->
(TArrow S1 S2) <: (TArrow T1 T2)
where "T '<:' U" := (subtype T U).
(** Note that we don't need any special rules for base types: they are
automatically subtypes of themselves (by [S_Refl]) and [Top] (by
[S_Top]), and that's all we want. *)
Hint Constructors subtype.
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Notation String := (TBase (Id 9)).
Notation Float := (TBase (Id 10)).
Notation Integer := (TBase (Id 11)).
Example subtyping_example_0 :
(TArrow C TBool) <: (TArrow C TTop).
(* C->Bool <: C->Top *)
Proof. auto. Qed.
(** **** Exercise: 2 stars, optional (subtyping_judgements) *)
(** (Wait to do this exercise after you have added product types to the
language -- see exercise [products] -- at least up to this point
in the file).
Recall that, in chapter [MoreStlc], the optional section "Encoding
Records" describes how records can be encoded as pairs.
Using this encoding, define pair types representing the following
record types:
Person := { name : String }
Student := { name : String ;
gpa : Float }
Employee := { name : String ;
ssn : Integer }
*)
Definition Person : ty :=
(* FILL IN HERE *) admit.
Definition Student : ty :=
(* FILL IN HERE *) admit.
Definition Employee : ty :=
(* FILL IN HERE *) admit.
(** Now use the definition of the subtype relation to prove the following: *)
Example sub_student_person :
Student <: Person.
Proof.
(* FILL IN HERE *) Admitted.
Example sub_employee_person :
Employee <: Person.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 1 star, optional (subtyping_example_1) *)
Example subtyping_example_1 :
(TArrow TTop Student) <: (TArrow (TArrow C C) Person).
(* Top->Student <: (C->C)->Person *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (subtyping_example_2) *)
Example subtyping_example_2 :
(TArrow TTop Person) <: (TArrow Person TTop).
(* Top->Person <: Person->Top *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(* ###################################################################### *)
(** ** Typing *)
(** The only change to the typing relation is the addition of the rule
of subsumption, [T_Sub]. *)
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Same as before *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(update Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- (tif t1 t2 t3) \in T
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* New rule of subsumption *)
| T_Sub : forall Gamma t S T,
Gamma |- t \in S ->
S <: T ->
Gamma |- t \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(** The following hints help [auto] and [eauto] construct typing
derivations. (See chapter [UseAuto] for more on hints.) *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
Module Examples2.
Import Examples.
(** Do the following exercises after you have added product types to
the language. For each informal typing judgement, write it as a
formal statement in Coq and prove it. *)
(** **** Exercise: 1 star, optional (typing_example_0) *)
(* empty |- ((\z:A.z), (\z:B.z))
: (A->A * B->B) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_1) *)
(* empty |- (\x:(Top * B->B). x.snd) ((\z:A.z), (\z:B.z))
: B->B *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_2) *)
(* empty |- (\z:(C->C)->(Top * B->B). (z (\x:C.x)).snd)
(\z:C->C. ((\z:A.z), (\z:B.z)))
: B->B *)
(* FILL IN HERE *)
(** [] *)
End Examples2.
(* ###################################################################### *)
(** * Properties *)
(** The fundamental properties of the system that we want to
check are the same as always: progress and preservation. Unlike
the extension of the STLC with references (chapter [References]),
we don't need to change the _statements_ of these properties to
take subtyping into account. However, their proofs do become a
little bit more involved. *)
(* ###################################################################### *)
(** ** Inversion Lemmas for Subtyping *)
(** Before we look at the properties of the typing relation, we need
to establish a couple of critical structural properties of the
subtype relation:
- [Bool] is the only subtype of [Bool], and
- every subtype of an arrow type is itself an arrow type. *)
(** These are called _inversion lemmas_ because they play a
similar role in proofs as the built-in [inversion] tactic: given a
hypothesis that there exists a derivation of some subtyping
statement [S <: T] and some constraints on the shape of [S] and/or
[T], each inversion lemma reasons about what this derivation must
look like to tell us something further about the shapes of [S] and
[T] and the existence of subtype relations between their parts. *)
(** **** Exercise: 2 stars, optional (sub_inversion_Bool) *)
Lemma sub_inversion_Bool : forall U,
U <: TBool ->
U = TBool.
Proof with auto.
intros U Hs.
remember TBool as V.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
U <: (TArrow V1 V2) ->
exists U1, exists U2,
U = (TArrow U1 U2) /\ (V1 <: U1) /\ (U2 <: V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################## *)
(** ** Canonical Forms *)
(** The proof of the progress theorem -- that a well-typed
non-value can always take a step -- doesn't need to change too
much: we just need one small refinement. When we're considering
the case where the term in question is an application [t1 t2]
where both [t1] and [t2] are values, we need to know that [t1] has
the _form_ of a lambda-abstraction, so that we can apply the
[ST_AppAbs] reduction rule. In the ordinary STLC, this is
obvious: we know that [t1] has a function type [T11->T12], and
there is only one rule that can be used to give a function type to
a value -- rule [T_Abs] -- and the form of the conclusion of this
rule forces [t1] to be an abstraction.
In the STLC with subtyping, this reasoning doesn't quite work
because there's another rule that can be used to show that a value
has a function type: subsumption. Fortunately, this possibility
doesn't change things much: if the last rule used to show [Gamma
|- t1 : T11->T12] is subsumption, then there is some
_sub_-derivation whose subject is also [t1], and we can reason by
induction until we finally bottom out at a use of [T_Abs].
This bit of reasoning is packaged up in the following lemma, which
tells us the possible "canonical forms" (i.e., values) of function
type. *)
(** **** Exercise: 3 stars, optional (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
Gamma |- s \in (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Similarly, the canonical forms of type [Bool] are the constants
[true] and [false]. *)
Lemma canonical_forms_of_Bool : forall Gamma s,
Gamma |- s \in TBool ->
value s ->
(s = ttrue \/ s = tfalse).
Proof with eauto.
intros Gamma s Hty Hv.
remember TBool as T.
induction Hty; try solve by inversion...
- (* T_Sub *)
subst. apply sub_inversion_Bool in H. subst...
Qed.
(* ########################################## *)
(** ** Progress *)
(** The proof of progress now proceeds just like the one for the
pure STLC, except that in several places we invoke canonical forms
lemmas... *)
(** _Theorem_ (Progress): For any term [t] and type [T], if [empty |-
t : T] then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given, with [empty |- t : T]. Proceed
by induction on the typing derivation.
The cases for [T_Abs], [T_Unit], [T_True] and [T_False] are
immediate because abstractions, [unit], [true], and [false] are
already values. The [T_Var] case is vacuous because variables
cannot be typed in the empty context. The remaining cases are
more interesting:
- If the last step in the typing derivation uses rule [T_App],
then there are terms [t1] [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and [empty |-
t2 : T1]. Moreover, by the induction hypothesis, either [t1] is
a value or it steps, and either [t2] is a value or it steps.
There are three possibilities to consider:
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==> t1' t2]
by [ST_App1].
- Suppose [t1] is a value and [t2 ==> t2'] for some term [t2'].
Then [t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a
value.
- Finally, suppose [t1] and [t2] are both values. By the lemma
about canonical forms for arrow types, we know that [t1] has the
form [\x:S1.s2] for some [x], [S1], and [s2]. But then
[(\x:S1.s2) t2 ==> [x:=t2]s2] by [ST_AppAbs], since [t2] is a
value.
- If the final step of the derivation uses rule [T_If], then there
are terms [t1], [t2], and [t3] such that [t = if t1 then t2 else
t3], with [empty |- t1 : Bool] and with [empty |- t2 : T] and
[empty |- t3 : T]. Moreover, by the induction hypothesis,
either [t1] is a value or it steps.
- If [t1] is a value, then by the canonical forms lemma for
booleans, either [t1 = true] or [t1 = false]. In either
case, [t] can step, using rule [ST_IfTrue] or [ST_IfFalse].
- If [t1] can step, then so can [t], by rule [ST_If].
- If the final step of the derivation is by [T_Sub], then there is
a type [S] such that [S <: T] and [empty |- t : S]. The desired
result is exactly the induction hypothesis for the typing
subderivation. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
induction Ht;
intros HeqGamma; subst...
- (* T_Var *)
inversion H.
- (* T_App *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
* (* t2 steps *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_If *)
right.
destruct IHHt1.
+ (* t1 is a value *) eauto.
+ assert (t1 = ttrue \/ t1 = tfalse)
by (eapply canonical_forms_of_Bool; eauto).
inversion H0; subst...
+ inversion H. rename x into t1'. eauto.
Qed.
(* ########################################## *)
(** ** Inversion Lemmas for Typing *)
(** The proof of the preservation theorem also becomes a little more
complex with the addition of subtyping. The reason is that, as
with the "inversion lemmas for subtyping" above, there are a
number of facts about the typing relation that are immediate from
the definition in the pure STLC (formally: that can be obtained
directly from the [inversion] tactic) but that require real proofs
in the presence of subtyping because there are multiple ways to
derive the same [has_type] statement.
The following inversion lemma tells us that, if we have a
derivation of some typing statement [Gamma |- \x:S1.t2 : T] whose
subject is an abstraction, then there must be some subderivation
giving a type to the body [t2]. *)
(** _Lemma_: If [Gamma |- \x:S1.t2 : T], then there is a type [S2]
such that [Gamma, x:S1 |- t2 : S2] and [S1 -> S2 <: T].
(Notice that the lemma does _not_ say, "then [T] itself is an arrow
type" -- this is tempting, but false!)
_Proof_: Let [Gamma], [x], [S1], [t2] and [T] be given as
described. Proceed by induction on the derivation of [Gamma |-
\x:S1.t2 : T]. Cases [T_Var], [T_App], are vacuous as those
rules cannot be used to give a type to a syntactic abstraction.
- If the last step of the derivation is a use of [T_Abs] then
there is a type [T12] such that [T = S1 -> T12] and [Gamma,
x:S1 |- t2 : T12]. Picking [T12] for [S2] gives us what we
need: [S1 -> T12 <: S1 -> T12] follows from [S_Refl].
- If the last step of the derivation is a use of [T_Sub] then
there is a type [S] such that [S <: T] and [Gamma |- \x:S1.t2 :
S]. The IH for the typing subderivation tell us that there is
some type [S2] with [S1 -> S2 <: S] and [Gamma, x:S1 |- t2 :
S2]. Picking type [S2] gives us what we need, since [S1 -> S2
<: T] then follows by [S_Trans]. *)
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
Gamma |- (tabs x S1 t2) \in T ->
(exists S2, (TArrow S1 S2) <: T
/\ (update Gamma x S1) |- t2 \in S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
induction H;
inversion Heqt; subst; intros; try solve by inversion.
- (* T_Abs *)
exists T12...
- (* T_Sub *)
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
(** Similarly... *)
Lemma typing_inversion_var : forall Gamma x T,
Gamma |- (tvar x) \in T ->
exists S,
Gamma x = Some S /\ S <: T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_Var *)
exists T...
- (* T_Sub *)
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
Gamma |- (tapp t1 t2) \in T2 ->
exists T1,
Gamma |- t1 \in (TArrow T1 T2) /\
Gamma |- t2 \in T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_App *)
exists T1...
- (* T_Sub *)
destruct IHHty as [U1 [Hty1 Hty2]]...
Qed.
Lemma typing_inversion_true : forall Gamma T,
Gamma |- ttrue \in T ->
TBool <: T.
Proof with eauto.
intros Gamma T Htyp. remember ttrue as tu.
induction Htyp;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_false : forall Gamma T,
Gamma |- tfalse \in T ->
TBool <: T.
Proof with eauto.
intros Gamma T Htyp. remember tfalse as tu.
induction Htyp;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_if : forall Gamma t1 t2 t3 T,
Gamma |- (tif t1 t2 t3) \in T ->
Gamma |- t1 \in TBool
/\ Gamma |- t2 \in T
/\ Gamma |- t3 \in T.
Proof with eauto.
intros Gamma t1 t2 t3 T Hty.
remember (tif t1 t2 t3) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_If *)
auto.
- (* T_Sub *)
destruct (IHHty H0) as [H1 [H2 H3]]...
Qed.
Lemma typing_inversion_unit : forall Gamma T,
Gamma |- tunit \in T ->
TUnit <: T.
Proof with eauto.
intros Gamma T Htyp. remember tunit as tu.
induction Htyp;
inversion Heqtu; subst; intros...
Qed.
(** The inversion lemmas for typing and for subtyping between arrow
types can be packaged up as a useful "combination lemma" telling
us exactly what we'll actually require below. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
empty |- (tabs x S1 s2) \in (TArrow T1 T2) ->
T1 <: S1
/\ (update empty x S1) |- s2 \in T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
inversion Hty as [S2 [Hsub Hty1]].
apply sub_inversion_arrow in Hsub.
inversion Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(** ** Context Invariance *)
(** The context invariance lemma follows the same pattern as in the
pure STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold update, t_update. destruct (beq_idP x x0)...
- (* T_If *)
apply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp;
subst; inversion Hafi; subst...
- (* T_Abs *)
destruct (IHHtyp H4) as [T Hctx]. exists T.
unfold update, t_update in Hctx.
rewrite <- beq_id_false_iff in H2.
rewrite H2 in Hctx... Qed.
(* ########################################## *)
(** ** Substitution *)
(** The _substitution lemma_ is proved along the same lines as
for the pure STLC. The only significant change is that there are
several places where, instead of the built-in [inversion] tactic,
we need to use the inversion lemmas that we proved above to
extract structural information from assumptions about the
well-typedness of subterms. *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(update Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
induction t; intros; simpl.
- (* tvar *)
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt)
as [T [Hctx Hsub]].
unfold update, t_update in Hctx.
destruct (beq_idP x y) as [Hxy|Hxy]; eauto;
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra)
as [T' HT']...
inversion HT'.
- (* tapp *)
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
- (* tabs *)
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (beq_idP x y) as [Hxy|Hxy].
+ (* x=y *)
eapply context_invariance...
subst.
intros x Hafi. unfold update, t_update.
destruct (beq_id y x)...
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z)...
subst.
rewrite <- beq_id_false_iff in Hxy. rewrite Hxy...
- (* ttrue *)
assert (TBool <: S)
by apply (typing_inversion_true _ _ Htypt)...
- (* tfalse *)
assert (TBool <: S)
by apply (typing_inversion_false _ _ Htypt)...
- (* tif *)
assert ((update Gamma x U) |- t1 \in TBool
/\ (update Gamma x U) |- t2 \in S
/\ (update Gamma x U) |- t3 \in S)
by apply (typing_inversion_if _ _ _ _ _ Htypt).
inversion H as [H1 [H2 H3]].
apply IHt1 in H1. apply IHt2 in H2. apply IHt3 in H3.
auto.
- (* tunit *)
assert (TUnit <: S)
by apply (typing_inversion_unit _ _ Htypt)...
Qed.
(* ########################################## *)
(** ** Preservation *)
(** The proof of preservation now proceeds pretty much as in earlier
chapters, using the substitution lemma at the appropriate point
and again using inversion lemmas from above to extract structural
information from typing assumptions. *)
(** _Theorem_ (Preservation): If [t], [t'] are terms and [T] is a type
such that [empty |- t : T] and [t ==> t'], then [empty |- t' :
T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
proceed by induction on the structure of this typing derivation,
leaving [t'] general. The cases [T_Abs], [T_Unit], [T_True], and
[T_False] cases are vacuous because abstractions and constants
don't step. Case [T_Var] is vacuous as well, since the context is
empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] and [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and
[empty |- t2 : T1].
By the definition of the step relation, there are three ways
[t1 t2] can step. Cases [ST_App1] and [ST_App2] follow
immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then [t1 =
\x:S.t12] for some type [S] and term [t12], and [t' =
[x:=t2]t12].
By lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by the substitution lemma
([substitution_preserves_typing]) that [empty |- [x:=t2]
t12 : T2] as desired.
- If the final step of the derivation uses rule [T_If], then
there are terms [t1], [t2], and [t3] such that [t = if t1 then
t2 else t3], with [empty |- t1 : Bool] and with [empty |- t2 :
T] and [empty |- t3 : T]. Moreover, by the induction
hypothesis, if [t1] steps to [t1'] then [empty |- t1' : Bool].
There are three cases to consider, depending on which rule was
used to show [t ==> t'].
- If [t ==> t'] by rule [ST_If], then [t' = if t1' then t2
else t3] with [t1 ==> t1']. By the induction hypothesis,
[empty |- t1' : Bool], and so [empty |- t' : T] by [T_If].
- If [t ==> t'] by rule [ST_IfTrue] or [ST_IfFalse], then
either [t' = t2] or [t' = t3], and [empty |- t' : T]
follows by assumption.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub]. [] *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
inversion HE; subst...
+ (* ST_AppAbs *)
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Qed.
(** ** Records, via Products and Top *)
(** This formalization of the STLC with subtyping omits record
types for brevity. If we want to deal with them more seriously,
we have two choices.
First, we can treat them as part of the core language, writing
down proper syntax, typing, and subtyping rules for them. Chapter
[RecordSub] shows how this extension works.
On the other hand, if we are treating them as a derived form that
is desugared in the parser, then we shouldn't need any new rules:
we should just check that the existing rules for subtyping product
and [Unit] types give rise to reasonable rules for record
subtyping via this encoding. To do this, we just need to make one
small change to the encoding described earlier: instead of using
[Unit] as the base case in the encoding of tuples and the "don't
care" placeholder in the encoding of records, we use [Top]. So:
{a:Nat, b:Nat} ----> {Nat,Nat} i.e., (Nat,(Nat,Top))
{c:Nat, a:Nat} ----> {Nat,Top,Nat} i.e., (Nat,(Top,(Nat,Top)))
The encoding of record values doesn't change at all. It is
easy (and instructive) to check that the subtyping rules above are
validated by the encoding. *)
(* ###################################################### *)
(** ** Exercises *)
(** **** Exercise: 2 stars (variations) *)
(** Each part of this problem suggests a different way of changing the
definition of the STLC with Unit and subtyping. (These changes
are not cumulative: each part starts from the original language.)
In each part, list which properties (Progress, Preservation, both,
or neither) become false. If a property becomes false, give a
counterexample.
- Suppose we add the following typing rule:
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
- Suppose we add the following reduction rule:
-------------------- (ST_Funny21)
unit ==> (\x:Top. x)
- Suppose we add the following subtyping rule:
---------------- (S_Funny3)
Unit <: Top->Top
- Suppose we add the following subtyping rule:
---------------- (S_Funny4)
Top->Top <: Unit
- Suppose we add the following reduction rule:
--------------------- (ST_Funny5)
(unit t) ==> (t unit)
- Suppose we add the same reduction rule _and_ a new typing rule:
--------------------- (ST_Funny5)
(unit t) ==> (t unit)
------------------------ (T_Funny6)
empty |- Unit : Top->Top
- Suppose we _change_ the arrow subtyping rule to:
S1 <: T1 S2 <: T2
----------------- (S_Arrow')
S1->S2 <: T1->T2
[] *)
(* ###################################################################### *)
(** * Exercise: Adding Products *)
(** **** Exercise: 4 stars (products) *)
(** Adding pairs, projections, and product types to the system we have
defined is a relatively straightforward matter. Carry out this
extension:
- Add constructors for pairs, first and second projections, and
product types to the definitions of [ty] and [tm]. (Don't
forget to add corresponding cases to [T_cases] and [t_cases].)
- Extend the substitution function and value relation as in
chapter [MoreSTLC].
- Extend the operational semantics with the same reduction rules
as in chapter [MoreSTLC].
- Extend the subtyping relation with this rule:
S1 <: T1 S2 <: T2
--------------------- (Sub_Prod)
S1 * S2 <: T1 * T2
- Extend the typing relation with the same rules for pairs and
projections as in chapter [MoreSTLC].
- Extend the proofs of progress, preservation, and all their
supporting lemmas to deal with the new constructs. (You'll also
need to add some completely new lemmas.)
[] *)
(** $Date: 2016-05-26 17:51:14 -0400 (Thu, 26 May 2016) $ *)
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module rotate (
input [15:0] x,
input [ 4:0] y,
input [ 1:0] func, // 00: ror, 01: rol, 10: rcr, 11: rcl
input cfi,
input word_op,
output [15:0] out,
output cfo,
input ofi,
output ofo
);
// Net declarations
wire [4:0] ror16, rol16, rcr16, rcl16, rot16;
wire [3:0] ror8, rol8, rcr8, rcl8, rot8;
wire [7:0] out8;
wire [15:0] out16;
wire co8, co16;
wire unchanged;
// Module instantiation
rxr8 rxr8_0 (
.x (x[7:0]),
.ci (cfi),
.y (rot8),
.e (func[1]),
.w (out8),
.co (co8)
);
rxr16 rxr16_0 (
.x (x),
.ci (cfi),
.y (rot16),
.e (func[1]),
.w (out16),
.co (co16)
);
// Continuous assignments
assign unchanged = word_op ? (y==5'b0) : (y[3:0]==4'b0);
assign ror16 = { 1'b0, y[3:0] };
assign rol16 = { 1'b0, -y[3:0] };
assign ror8 = { 1'b0, y[2:0] };
assign rol8 = { 1'b0, -y[2:0] };
assign rcr16 = (y <= 5'd16) ? y : { 1'b0, y[3:0] - 4'b1 };
assign rcl16 = (y <= 5'd17) ? 5'd17 - y : 6'd34 - y;
assign rcr8 = y[3:0] <= 4'd8 ? y[3:0] : { 1'b0, y[2:0] - 3'b1 };
assign rcl8 = y[3:0] <= 4'd9 ? 4'd9 - y[3:0] : 5'd18 - y[3:0];
assign rot8 = func[1] ? (func[0] ? rcl8 : rcr8 )
: (func[0] ? rol8 : ror8 );
assign rot16 = func[1] ? (func[0] ? rcl16 : rcr16 )
: (func[0] ? rol16 : ror16 );
assign out = word_op ? out16 : { x[15:8], out8 };
assign cfo = unchanged ? cfi : (func[1] ? (word_op ? co16 : co8)
: (func[0] ? out[0]
: (word_op ? out[15] : out[7])));
// Overflow
assign ofo = unchanged ? ofi : (func[0] ? // left
(word_op ? cfo^out[15] : cfo^out[7])
: // right
(word_op ? out[15]^out[14] : out[7]^out[6]));
endmodule
module rxr16 (
input [15:0] x,
input ci,
input [ 4:0] y,
input e,
output reg [15:0] w,
output reg co
);
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[15:1]} : {ci, x[0], x[15:1]};
5'd02: {co,w} <= e ? {x[ 1:0], ci, x[15: 2]} : {ci, x[ 1:0], x[15: 2]};
5'd03: {co,w} <= e ? {x[ 2:0], ci, x[15: 3]} : {ci, x[ 2:0], x[15: 3]};
5'd04: {co,w} <= e ? {x[ 3:0], ci, x[15: 4]} : {ci, x[ 3:0], x[15: 4]};
5'd05: {co,w} <= e ? {x[ 4:0], ci, x[15: 5]} : {ci, x[ 4:0], x[15: 5]};
5'd06: {co,w} <= e ? {x[ 5:0], ci, x[15: 6]} : {ci, x[ 5:0], x[15: 6]};
5'd07: {co,w} <= e ? {x[ 6:0], ci, x[15: 7]} : {ci, x[ 6:0], x[15: 7]};
5'd08: {co,w} <= e ? {x[ 7:0], ci, x[15: 8]} : {ci, x[ 7:0], x[15: 8]};
5'd09: {co,w} <= e ? {x[ 8:0], ci, x[15: 9]} : {ci, x[ 8:0], x[15: 9]};
5'd10: {co,w} <= e ? {x[ 9:0], ci, x[15:10]} : {ci, x[ 9:0], x[15:10]};
5'd11: {co,w} <= e ? {x[10:0], ci, x[15:11]} : {ci, x[10:0], x[15:11]};
5'd12: {co,w} <= e ? {x[11:0], ci, x[15:12]} : {ci, x[11:0], x[15:12]};
5'd13: {co,w} <= e ? {x[12:0], ci, x[15:13]} : {ci, x[12:0], x[15:13]};
5'd14: {co,w} <= e ? {x[13:0], ci, x[15:14]} : {ci, x[13:0], x[15:14]};
5'd15: {co,w} <= e ? {x[14:0], ci, x[15]} : {ci, x[14:0], x[15]};
5'd16: {co,w} <= {x,ci};
endcase
endmodule
module rxr8 (
input [7:0] x,
input ci,
input [3:0] y,
input e,
output reg [7:0] w,
output reg co
);
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[7:1]} : {ci, x[0], x[7:1]};
5'd02: {co,w} <= e ? {x[1:0], ci, x[7:2]} : {ci, x[1:0], x[7:2]};
5'd03: {co,w} <= e ? {x[2:0], ci, x[7:3]} : {ci, x[2:0], x[7:3]};
5'd04: {co,w} <= e ? {x[3:0], ci, x[7:4]} : {ci, x[3:0], x[7:4]};
5'd05: {co,w} <= e ? {x[4:0], ci, x[7:5]} : {ci, x[4:0], x[7:5]};
5'd06: {co,w} <= e ? {x[5:0], ci, x[7:6]} : {ci, x[5:0], x[7:6]};
5'd07: {co,w} <= e ? {x[6:0], ci, x[7]} : {ci, x[6:0], x[7]};
5'd08: {co,w} <= {x,ci};
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLRTN_PP_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A211O_FUNCTIONAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_FUNCTIONAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Sun Jun 18 18:41:11 2017
// Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk_out1,
reset,
locked,
clk_in1);
output clk_out1;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
(clk_out1,
reset,
locked,
clk_in1);
output clk_out1;
input reset;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire locked;
wire reset;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.250000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(12.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// Modifications Copryright (c) 2017 Simon Southwell. All rights reserved.
module CMD_Decode(
// USB JTAG
iRXD_DATA, oTXD_DATA, iRXD_Ready, iTXD_Done, oTXD_Start,
// LED
oLED_RED,oLED_GREEN,
// 7-SEG
oSEG7_DIG, iDIG,
// VGA
oOSD_CUR_EN, oCursor_X, oCursor_Y,
oCursor_R, oCursor_G, oCursor_B,
// FLASH
oFL_DATA, iFL_DATA, oFL_ADDR, iFL_Ready, oFL_Start, oFL_CMD,
// SDRAM
oSDR_DATA, iSDR_DATA, oSDR_ADDR, iSDR_Done, oSDR_WR, oSDR_RD,
// SRAM
oSR_DATA, iSR_DATA, oSR_ADDR, oSR_WE_N, oSR_OE_N,
// PS2
iPS2_ScanCode, iPS2_Ready,
// Async Port Select
oSDR_Select, oFL_Select, oSR_Select,
// Control
iCLK, iRST_n
);
// Include paramater definitions
`include "RS232_Command.vh"
`include "Flash_Command.vh"
// USB JTAG
input [7:0] iRXD_DATA;
input iRXD_Ready, iTXD_Done;
output [7:0] oTXD_DATA;
output oTXD_Start;
// LED
output reg [9:0] oLED_RED;
output reg [7:0] oLED_GREEN;
// 7-SEG
output reg [31:0] oSEG7_DIG;
input [31:0] iDIG;
// VGA
output reg [9:0] oCursor_X;
output reg [9:0] oCursor_Y;
output reg [9:0] oCursor_R;
output reg [9:0] oCursor_G;
output reg [9:0] oCursor_B;
output reg [1:0] oOSD_CUR_EN;
// FLASH
input [7:0] iFL_DATA;
input iFL_Ready;
output reg [21:0] oFL_ADDR;
output reg [7:0] oFL_DATA;
output reg [2:0] oFL_CMD;
output reg oFL_Start;
// SDRAM
input [15:0] iSDR_DATA;
input iSDR_Done;
output reg [21:0] oSDR_ADDR;
output reg [15:0] oSDR_DATA;
output oSDR_RD;
output oSDR_WR;
// SRAM
input [15:0] iSR_DATA;
output reg [15:0] oSR_DATA;
output reg [17:0] oSR_ADDR;
output oSR_OE_N;
output oSR_WE_N;
// PS2
input [7:0] iPS2_ScanCode;
input iPS2_Ready;
// Async Port Select
output reg [1:0] oSDR_Select;
output reg [1:0] oFL_Select;
output reg [1:0] oSR_Select;
// Control
input iCLK;
input iRST_n;
// Internal Register
reg [63:0] CMD_Tmp;
reg [2:0] mFL_ST, mSDR_ST, mPS2_ST, mSR_ST, mLCD_ST, mSEG7_ST;
// SDRAM Control Register
reg mSDR_WRn, mSDR_Start;
// SRAM Control Register
reg mSR_WRn, mSR_Start;
// Active Flag
reg f_SETUP, f_LED, f_SEG7, f_SDR_SEL, f_FL_SEL, f_SR_SEL;
reg f_FLASH, f_SDRAM, f_PS2, f_SRAM, f_VGA;
reg active_last;
// USB JTAG TXD Output
reg oFL_TXD_Start, oSDR_TXD_Start, oPS2_TXD_Start, oSR_TXD_Start, oSEG7_TXD_Start;
reg [7:0] oFL_TXD_DATA, oSDR_TXD_DATA, oPS2_TXD_DATA, oSR_TXD_DATA;
// TXD Output Select Register
reg sel_FL, sel_SDR, sel_PS2, sel_SR, sel_SEG7;
wire [7:0] CMD_Action = CMD_Tmp[63:56];
wire [7:0] CMD_Target = CMD_Tmp[55:48];
wire [23:0] CMD_ADDR = CMD_Tmp[47:24];
wire [15:0] CMD_DATA = CMD_Tmp[23: 8];
wire [7:0] CMD_MODE = CMD_Tmp[ 7: 0];
wire [7:0] Pre_Target = CMD_Tmp[47:40];
wire active = f_SETUP | f_LED | f_SEG7 | f_SDR_SEL | f_FL_SEL | f_SR_SEL |
f_FLASH | f_SDRAM | f_PS2 | f_SRAM | f_VGA;
wire going_inactive = active_last & ~active;
assign oTXD_Start = sel_FL ? oFL_TXD_Start :
sel_SDR ? oSDR_TXD_Start :
sel_SR ? oSR_TXD_Start :
sel_SEG7 ? oSEG7_TXD_Start :
oPS2_TXD_Start;
assign oTXD_DATA = sel_FL ? oFL_TXD_DATA :
sel_SDR ? oSDR_TXD_DATA :
sel_SR ? oSR_TXD_DATA :
sel_SEG7 ? oSEG7_DIG[7:0] :
oPS2_TXD_DATA;
/////////////////////////////////////////////////////////
//////////////// Async Source Select /////////////
always @(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oSDR_Select <= 2'b00;
oFL_Select <= 2'b00;
oSR_Select <= 2'b00;
f_SDR_SEL <= 1'b0;
f_FL_SEL <= 1'b0;
f_SR_SEL <= 1'b0;
end
else
begin
if (iRXD_Ready == 1'b1)
begin
case (Pre_Target)
SDRSEL : begin f_SDR_SEL <= 1'b1; end
FLSEL : begin f_FL_SEL <= 1'b1; end
SRSEL : begin f_SR_SEL <= 1'b1; end
endcase
end
if ((CMD_Action == SETUP) && (CMD_MODE == OUTSEL) && (CMD_ADDR == 24'h123456))
begin
if (f_SDR_SEL)
begin
oSDR_Select <= CMD_DATA[1:0];
end
else if (f_FL_SEL)
begin
oFL_Select <= CMD_DATA[1:0];
end
else if (f_SR_SEL)
begin
oSR_Select <= CMD_DATA[1:0];
end
end
if (f_SDR_SEL)
begin
f_SDR_SEL <= 1'b0;
end
if (f_FL_SEL)
begin
f_FL_SEL <= 1'b0;
end
if (f_SR_SEL)
begin
f_SR_SEL <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////
///////////////// TXD Output Select /////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
sel_FL <= 1'b0;
sel_SDR <= 1'b0;
sel_PS2 <= 1'b0;
sel_SR <= 1'b0;
sel_SEG7 <= 1'b0;
f_SETUP <= 1'b0;
end
else
begin
if (iRXD_Ready && (Pre_Target == SET_REG))
begin
f_SETUP<=1;
end
if (f_SETUP)
begin
if ((CMD_Action == SETUP) && (CMD_MODE == OUTSEL) && (CMD_ADDR == 24'h123456))
begin
sel_FL <= 1'b0;
sel_SDR <= 1'b0;
sel_PS2 <= 1'b0;
sel_SR <= 1'b0;
sel_SEG7 <= 1'b0;
case(CMD_DATA[7:0])
FLASH:
begin
sel_FL <= 1'b1;
end
SDRAM:
begin
sel_SDR <= 1'b1;
end
PS2:
begin
sel_PS2 <= 1'b1;
end
SRAM:
begin
sel_SR <= 1'b1;
end
SEG7:
begin
sel_SEG7 <= 1'b1;
end
endcase
end
f_SETUP <= 0;
end
end
end
/////////////////////////////////////////////////////////
/////// Shift Register For Command Temp /////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
CMD_Tmp <= {64{1'b0}};
active_last <= 1'b0;
end
else
begin
active_last <= active;
if (iRXD_Ready)
begin
CMD_Tmp <= {CMD_Tmp[55:0], iRXD_DATA};
end
else if (going_inactive)
begin
CMD_Tmp <= {64{1'b0}};
end
end
end
/////////////////////////////////////////////////////////
//////////////// LED Control /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oLED_RED <= {10{1'b0}};
oLED_GREEN <= {8{1'b0}};
f_LED <= 1'b0;
end
else
begin
if (iRXD_Ready && (Pre_Target == LED))
begin
f_LED <= 1'b1;
end
if (f_LED)
begin
if ((CMD_Action == WRITE) && (CMD_MODE == DISPLAY))
begin
oLED_RED <= CMD_ADDR[9:0];
oLED_GREEN <= CMD_DATA[7:0];
end
f_LED <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////
//////////////// 7-SEG Control /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oSEG7_DIG <= {32{1'b0}};
f_SEG7 <= 1'b0;
oSEG7_TXD_Start <= 1'b0;
mSEG7_ST <= 3'b000;
end
else
begin
if (iRXD_Ready && (Pre_Target == SEG7) )
begin
f_SEG7 <= 1'b1;
end
if (f_SEG7)
begin
if ((CMD_Action == WRITE) && (CMD_MODE == DISPLAY))
begin
oSEG7_DIG <= {CMD_ADDR[15:0], CMD_DATA};
f_SEG7 <= 1'b0;
end
else if ((CMD_Action == READ) && (CMD_MODE == NORMAL))
begin
case(mSEG7_ST)
3'b000:
begin
oSEG7_TXD_Start <= 1'b1;
oSEG7_DIG <= iDIG;
mSEG7_ST <= 3'b001;
end
3'b001:
begin
if(iTXD_Done)
begin
oSEG7_TXD_Start <= 1'b0;
mSEG7_ST <= 3'b010;
end
end
3'b010:
begin
oSEG7_TXD_Start <= 1'b1;
oSEG7_DIG <= {8'h00, iDIG[31:8]};
mSEG7_ST <= 3'b011;
end
3'b011:
begin
if(iTXD_Done)
begin
oSEG7_TXD_Start <= 1'b0;
mSEG7_ST <= 3'b000;
f_SEG7 <= 1'b0;
end
end
endcase
end
else
begin
f_SEG7 <= 1'b0;
end
end
end
end
/////////////////////////////////////////////////////////
//////////////// Flash Control /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if(!iRST_n)
begin
oFL_TXD_Start <= 1'b0;
oFL_Start <= 1'b0;
f_FLASH <= 1'b0;
mFL_ST <= 3'b000;
end
else
begin
if (CMD_Action == READ)
begin
oFL_CMD <= CMD_READ;
end
else if (CMD_Action == WRITE)
begin
oFL_CMD <= CMD_WRITE;
end
else if (CMD_Action == ERASE)
begin
oFL_CMD <= CMD_CHP_ERA;
end
else
begin
oFL_CMD <= 3'b000;
end
if (iRXD_Ready && (Pre_Target == FLASH))
begin
f_FLASH <= 1'b1;
end
if (f_FLASH)
begin
case(mFL_ST)
3'b000:
begin
if ((CMD_MODE == NORMAL) && (CMD_Target == FLASH) && (CMD_DATA[15:8] == 8'hFF))
begin
oFL_ADDR <= CMD_ADDR[21:0];
oFL_DATA <= CMD_DATA[7:0];
oFL_Start <= 1'b1;
mFL_ST <= 3'b001;
end
else
begin
mFL_ST <= 3'b000;
f_FLASH <= 1'b0;
end
end
3'b001:
begin
if (iFL_Ready)
begin
mFL_ST <= 3'b010;
oFL_Start <= 1'b0;
end
end
3'b010:
begin
oFL_Start <= 1'b1;
mFL_ST <= 3'b011;
end
3'b011:
begin
if (iFL_Ready)
begin
mFL_ST <= 3'b100;
oFL_Start <= 1'b0;
end
end
3'b100:
begin
oFL_Start <= 1'b1;
mFL_ST <= 3'b101;
end
3'b101:
begin
if (iFL_Ready)
begin
if (oFL_CMD == CMD_READ)
begin
mFL_ST <= 3'b110;
end
else
begin
mFL_ST <= 3'b000;
f_FLASH <= 1'b0;
end
oFL_Start <= 1'b0;
end
end
3'b110:
begin
oFL_TXD_DATA <= iFL_DATA;
oFL_TXD_Start <= 1'b1;
mFL_ST <= 3'b111;
end
3'b111:
begin
if (iTXD_Done)
begin
oFL_TXD_Start <= 1'b0;
mFL_ST <= 3'b000;
f_FLASH <= 1'b0;
end
end
endcase
end
end
end
/////////////////////////////////////////////////////////
///////////////// PS2 Control /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oPS2_TXD_Start <= 1'b0;
f_PS2 <= 1'b0;
mPS2_ST <= 3'b000;
end
else
begin
if (iPS2_Ready && iPS2_ScanCode!=8'h2e)
begin
f_PS2 <= 1'b1;
oPS2_TXD_DATA <= iPS2_ScanCode;
end
if (f_PS2)
begin
case(mPS2_ST)
3'b000:
begin
oPS2_TXD_Start <= 1'b1;
mPS2_ST <= 1'b1;
end
3'b001:
begin
if(iTXD_Done)
begin
oPS2_TXD_Start <= 1'b0;
mPS2_ST <= 3'b000;
f_PS2 <= 1'b0;
end
end
endcase
end
end
end
reg [15:0] SDR_DATA_reg;
/////////////////////////////////////////////////////////
//////////////// Sdram Control /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oSDR_TXD_Start <= 1'b0;
mSDR_WRn <= 1'b0;
mSDR_Start <= 1'b0;
f_SDRAM <= 1'b0;
mSDR_ST <= 3'b000;
oSDR_ADDR <= 22'h000000;
end
else
begin
if (CMD_Action == READ)
begin
mSDR_WRn <= 1'b0;
end
else if( CMD_Action == WRITE )
begin
mSDR_WRn <= 1'b1;
end
if (iRXD_Ready && (Pre_Target == SDRAM))
begin
f_SDRAM <= 1'b1;
end
if (f_SDRAM)
begin
case(mSDR_ST)
3'b000:
begin
if ((CMD_MODE == NORMAL) && (CMD_Target == SDRAM))
begin
oSDR_ADDR <= CMD_ADDR[21:0];
oSDR_DATA <= CMD_DATA;
mSDR_Start <= 1'b1;
mSDR_ST <= 3'b001;
end
else
begin
mSDR_ST <= 3'b000;
f_SDRAM <= 1'b0;
end
end
3'b001:
begin
if (iSDR_Done)
begin
if (mSDR_WRn == 1'b0)
begin
mSDR_ST <= 3'b010;
end
else
begin
mSDR_ST <= 3'b000;
f_SDRAM <= 1'b0;
mSDR_Start <= 1'b0;
end
end
else
SDR_DATA_reg <= iSDR_DATA;
end
3'b010:
begin
oSDR_TXD_DATA <= SDR_DATA_reg[7:0];
oSDR_TXD_Start <= 1'b1;
mSDR_ST <= 3'b011;
end
3'b011:
begin
if (iTXD_Done)
begin
oSDR_TXD_Start <= 1'b0;
mSDR_ST <= 3'b100;
end
end
3'b100:
begin
oSDR_TXD_DATA <= SDR_DATA_reg[15:8];
oSDR_TXD_Start <= 1'b1;
mSDR_ST <= 3'b101;
end
3'b101:
begin
if (iTXD_Done)
begin
mSDR_Start <= 1'b0;
oSDR_TXD_Start <= 1'b0;
mSDR_ST <= 3'b000;
f_SDRAM <= 1'b0;
end
end
endcase
end
end
end
assign oSDR_WR = mSDR_WRn & mSDR_Start;
assign oSDR_RD = ~mSDR_WRn & mSDR_Start;
/////////////////////////////////////////////////////////
//////////////// SRAM Control /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oSR_TXD_Start <= 1'b0;
mSR_WRn <= 1'b0;
mSR_Start <= 1'b0;
f_SRAM <= 1'b0;
mSR_ST <= 3'b000;
end
else
begin
if (CMD_Action == READ)
begin
mSR_WRn <= 1'b0;
end
else if (CMD_Action == WRITE)
begin
mSR_WRn <= 1'b1;
end
if (iRXD_Ready && (Pre_Target == SRAM))
begin
f_SRAM <= 1'b1;
end
if (f_SRAM)
begin
case(mSR_ST)
3'b000:
begin
if ((CMD_MODE == NORMAL) && (CMD_Target == SRAM))
begin
oSR_ADDR <= CMD_ADDR[17:0];
oSR_DATA <= CMD_DATA;
mSR_Start <= 1'b1;
mSR_ST <= 3'b001;
end
else
begin
mSR_ST <= 3'b000;
f_SRAM <= 1'b0;
end
end
3'b001:
begin
if (mSR_WRn == 1'b0)
begin
mSR_ST <= 3'b010;
end
else
begin
mSR_ST <= 3'b000;
f_SRAM <= 1'b0;
mSR_Start <= 1'b0;
end
end
3'b010:
begin
oSR_TXD_DATA <= iSR_DATA[7:0];
oSR_TXD_Start <= 1'b1;
mSR_ST <= 3'b011;
end
3'b011:
begin
if (iTXD_Done)
begin
oSR_TXD_Start <= 1'b0;
mSR_ST <= 3'b100;
end
end
3'b100:
begin
oSR_TXD_DATA <= iSR_DATA[15:8];
oSR_TXD_Start <= 1'b1;
mSR_ST <= 3'b101;
end
3'b101:
begin
if (iTXD_Done)
begin
mSR_Start <= 1'b0;
oSR_TXD_Start <= 1'b0;
mSR_ST <= 3'b000;
f_SRAM <= 1'b0;
end
end
endcase
end
end
end
assign oSR_OE_N = mSR_WRn;
assign oSR_WE_N = ~(mSR_WRn & mSR_Start);
/////////////////////////////////////////////////////////
//////////////////// VGA Control /////////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oCursor_X <= {10{1'b0}};
oCursor_Y <= {10{1'b0}};
oCursor_R <= {10{1'b0}};
oCursor_G <= {10{1'b0}};
oCursor_B <= {10{1'b0}};
oOSD_CUR_EN <= 2'b00;
f_VGA <= 1'b0;
end
else
begin
if (iRXD_Ready && (Pre_Target == VGA))
begin
f_VGA <= 1'b1;
end
if (f_VGA)
begin
if ((CMD_Action == WRITE) && (CMD_MODE == DISPLAY))
begin
case(CMD_ADDR[2:0])
3'b000: oOSD_CUR_EN <= CMD_DATA[1:0];
3'b001: oCursor_X <= CMD_DATA[9:0];
3'b010: oCursor_Y <= CMD_DATA[9:0];
3'b011: oCursor_R <= CMD_DATA[9:0];
3'b100: oCursor_G <= CMD_DATA[9:0];
3'b101: oCursor_B <= CMD_DATA[9:0];
endcase
end
f_VGA <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:24:21 12/06/2016
// Design Name:
// Module Name: vga_sync
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_sync(
input wire clk, clr,
output reg hsync, vsync,
output wire video_on,
output wire [9:0] pixel_x, pixel_y
);
parameter hpixels = 800;
parameter vlines = 525;
parameter hbp = 144;
parameter hfp = 784;
parameter vbp = 35;
parameter vfp = 515;
reg [9:0] hc, vc;
assign pixel_x = hc - hbp - 1;
assign pixel_y = vc - vbp - 1;
always @ (posedge clk or posedge clr)
begin
if (clr == 1)
hc <= 0;
else
begin
if (hc == hpixels - 1)
begin
hc <= 0;
end
else
begin
hc <= hc + 1;
end
end
end
always @*
begin
if(hc >= 96)
hsync = 1;
else
hsync = 0;
end
always @(posedge clk or posedge clr)
begin
if (clr == 1)
begin
vc <= 0;
end
else
begin
if (hc == hpixels - 1)
begin
if (vc == vlines - 1)
begin
vc <= 0;
end
else
begin
vc <= vc + 1;
end
end
end
end
always @*
begin
if(vc >= 2)
vsync = 1;
else
vsync = 0;
end
assign video_on = (hc < hfp) && (hc > hbp) && (vc < vfp) && (vc > vbp);
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : chip_top.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/chip.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "timer.h"
module timer (
input wire clk,
input wire reset,
input wire cs_n,
input wire as_n,
input wire rw,
input wire [`TimerAddrBus] addr,
input wire [`WordDataBus] wr_data,
output reg [`WordDataBus] rd_data,
output reg rdy_n,
output reg irq
);
reg mode;
reg start;
reg [`WordDataBus] expr_val;
reg [`WordDataBus] counter;
wire expr_flag = ((start == `ENABLE) && (counter == expr_val)) ?
`ENABLE : `DISABLE;
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
rd_data <= #1 `WORD_DATA_W'h0;
rdy_n <= #1 `DISABLE_N;
start <= #1 `DISABLE;
mode <= #1 `TIMER_MODE_ONE_SHOT;
irq <= #1 `DISABLE;
expr_val <= #1 `WORD_DATA_W'h0;
counter <= #1 `WORD_DATA_W'h0;
end else begin
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N)) begin
rdy_n <= #1 `ENABLE_N;
end else begin
rdy_n <= #1 `DISABLE_N;
end
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N) && (rw == `READ)) begin
case (addr)
`TIMER_ADDR_CTRL : begin
rd_data <= #1 {{`WORD_DATA_W-2{1'b0}}, mode, start};
end
`TIMER_ADDR_INTR : begin
rd_data <= #1 {{`WORD_DATA_W-1{1'b0}}, irq};
end
`TIMER_ADDR_EXPR : begin
rd_data <= #1 expr_val;
end
`TIMER_ADDR_COUNTER : begin
rd_data <= #1 counter;
end
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_CTRL)) begin
start <= #1 wr_data[`TimerStartLoc];
mode <= #1 wr_data[`TimerModeLoc];
end else if ((expr_flag == `ENABLE) &&
(mode == `TIMER_MODE_ONE_SHOT)) begin
start <= #1 `DISABLE;
end
if (expr_flag == `ENABLE) begin
irq <= #1 `ENABLE;
end else if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_INTR)) begin
irq <= #1 wr_data[`TimerIrqLoc];
end
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_EXPR)) begin
expr_val <= #1 wr_data;
end
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N) &&
(rw == `WRITE) && (addr == `TIMER_ADDR_COUNTER)) begin
counter <= #1 wr_data;
end else if (expr_flag == `ENABLE) begin
counter <= #1 `WORD_DATA_W'h0;
end else if (start == `ENABLE) begin
counter <= #1 counter + 1'd1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 22:07:06
// Design Name:
// Module Name: lab4_3_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab4_3_1(
input m,clk,
output reg [3:0] Z
);
//reg n;
reg [1:0] state,nextstate;
parameter S0 = 2'b00,S1 = 2'b01,S2 = 2'b11,S3 = 2'b10;
initial
begin
state = S0;
// n = 0;
end
always @(posedge clk)
begin
// if(n == 10000000)
// begin
state = nextstate;
// n = 0;
// end
// else
// begin
// n = n + 1;
// end
end
always @(state)
begin
case(state)
S0:if(m) Z = 4'b0001;else Z = 4'b0001;
S1:if(m) Z = 4'b0010;else Z = 4'b1000;
S2:if(m) Z = 4'b0100;else Z = 4'b0100;
S3:if(m) Z = 4'b1000;else Z = 4'b0010;
endcase
end
always @(state)
begin
case(state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S3;
S3: nextstate = S0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
/**************************************************************/
/* _____ _ _ */
/* | ____|_ __ ___ _ __ __ _ _ _| | __ _| |__ ___ */
/* | _| | '_ \ / _ \ '__/ _` | | | | | / _` | '_ \/ __| */
/* | |___| | | | __/ | | (_| | |_| | |__| (_| | |_) \__ \ */
/* |_____|_| |_|\___|_| \__, |\__, |_____\__,_|_.__/|___/ */
/* |___/ |___/ */
/**************************************************************/
/* Por: Lucas Teske - lucas at teske dot com dot br */
/* See link below for more info */
/* https://github.com/racerxdl/SuperINT */
/**************************************************************/
module LedPWM(
input clk,
input [7:0] value,
output out
);
reg [7:0] PWMCounter;
reg outreg;
always @(posedge clk)
begin
if(PWMCounter <= value & value != 0)
outreg <= 1;
else
outreg <= 0;
PWMCounter <= PWMCounter+1;
end
assign out = outreg;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A21BOI_BEHAVIORAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_1_V
`define SKY130_FD_SC_LP__O32AI_1_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_1_V
|
/*
Execute Module (64-bit, Primary)
*/
`include "CoreDefs.v"
`include "ExShad64.v"
module ExOp64_3A(
/* verilator lint_off UNUSED */
clock, reset,
opCmd, opStepPc,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRn, regValRn,
immValRi, idInGenPc,
regOutId, regOutVal,
regOutOK,
memAddr, memData,
memLoad, memStore,
memOpMode, memOpCmd2,
ctlInSr, ctlOutSr,
ctlInPr, ctlOutPr,
ctlInPc, ctlOutPc,
ctlInMach, ctlOutMach,
ctlInMacl, ctlOutMacl,
ctlInSp, ctlOutSp,
ctlInGbr, ctlOutGbr,
ctlInVbr, ctlOutVbr,
ctlInSSr, ctlOutSSr,
ctlInSPc, ctlOutSPc,
ctlInSGr, ctlOutSGr
);
input clock;
input reset;
input[7:0] opCmd; //command opcode
input[3:0] opStepPc;
input[63:0] idInGenPc; //ID's Next PC (Next Fetch)
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRn;
input[63:0] regValRs; //Rs input value
input[63:0] regValRt; //Rt input value
input[63:0] regValRn; //Rn input value
input[63:0] immValRi; //immediate/disp value
output[63:0] regOutVal; //Rn output value
output[6:0] regOutId; //Rn, value to write
output[1:0] regOutOK; //execute status
/* Memory */
output[63:0] memAddr; //memory address
output[63:0] memData; //memory data (write)
output memLoad; //load from memory
output memStore; //store to memory
output[4:0] memOpMode; //mem op mode
output[7:0] memOpCmd2; //mem EX chain
/* Special Registers */
input[63:0] ctlInSr; //SR in
input[63:0] ctlInPr; //PR in
input[63:0] ctlInPc; //PC in
output[63:0] ctlOutSr; //SR out
output[63:0] ctlOutPr; //PR out
output[63:0] ctlOutPc; //PC out
input[63:0] ctlInMach; //MACH:MACL in
input[63:0] ctlInMacl; //MACH:MACL in
output[63:0] ctlOutMach; //MACH:MACL out
output[63:0] ctlOutMacl; //MACH:MACL out
input[63:0] ctlInSp; //SP in
output[63:0] ctlOutSp; //SP out
input[63:0] ctlInGbr;
input[63:0] ctlInVbr;
input[63:0] ctlInSSr;
input[63:0] ctlInSPc;
input[63:0] ctlInSGr;
output[63:0] ctlOutGbr;
output[63:0] ctlOutVbr;
output[63:0] ctlOutSSr;
output[63:0] ctlOutSPc;
output[63:0] ctlOutSGr;
/* Temporary */
reg[63:0] tRegOutVal; //Rn, output value
reg[6:0] tRegOutId; //Rn, output register
reg[1:0] tRegOutOK; //execute status
reg[63:0] tMemAddr; //memory address
reg[63:0] tMemData; //memory data (write)
reg tMemLoad; //load from memory
reg tMemStore; //store to memory
reg[4:0] tMemOpMode; //mem op mode
reg[7:0] tMemOpCmd2; //mem EX chain
assign memAddr = tMemAddr;
assign memData = tMemData;
assign memLoad = tMemLoad;
assign memStore = tMemStore;
assign memOpMode = tMemOpMode;
assign memOpCmd2 = tMemOpCmd2;
/* verilator lint_off UNOPTFLAT */
reg[63:0] tAguRtRi; //AGU Rt+Ri
reg[63:0] tAguRtRiSc; //AGU (Rt+Ri)*Sc
reg[63:0] tAguAddr; //AGU Address
reg[63:0] tCtlOutSr;
reg[63:0] tCtlOutPr;
reg[63:0] tCtlOutPc;
reg[63:0] tCtlOutMach;
reg[63:0] tCtlOutMacl;
reg[63:0] tCtlOutSp;
reg[63:0] tCtlNxtPc;
reg[63:0] tCtlBraPc;
reg[63:0] tCtlPrPc;
reg[63:0] tCtlOutGbr;
reg[63:0] tCtlOutVbr;
reg[63:0] tCtlOutSSr;
reg[63:0] tCtlOutSPc;
reg[63:0] tCtlOutSGr;
/* verilator lint_on UNOPTFLAT */
assign regOutVal = tRegOutVal;
assign regOutId = tRegOutId;
assign regOutOK = tRegOutOK;
assign ctlOutSr = tCtlOutSr;
assign ctlOutPr = tCtlOutPr;
assign ctlOutPc = tCtlOutPc;
assign ctlOutMach = tCtlOutMach;
assign ctlOutMacl = tCtlOutMacl;
assign ctlOutSp = tCtlOutSp;
assign ctlOutGbr = tCtlOutGbr;
assign ctlOutVbr = tCtlOutVbr;
assign ctlOutSSr = tCtlOutSSr;
assign ctlOutSPc = tCtlOutSPc;
assign ctlOutSGr = tCtlOutSGr;
reg tInAluC;
reg tOutAluC;
reg tTriggerExc;
reg[1:0] tMacOp;
reg[63:0] tMacValRs;
reg[63:0] tMacValRt;
reg[127:0] tMacValRu;
reg[127:0] tMacValRuA;
reg[1:0] tMacOpA;
reg[1:0] tMacOpB;
reg[63:0] tShadValRs;
reg[ 7:0] tShadValRt;
wire[63:0] tShadValRn;
reg[ 2:0] tShadOp;
// reg[63:0] tShadValRu;
ExShad64 sh64(
clock, reset,
tShadValRs, tShadValRt,
tShadValRn, tShadOp);
reg[64:0] tAluDn1;
reg[64:0] tAluDn2;
reg tAluQ0;
reg tAluM0;
reg tAluT0;
reg tAluQ1;
reg tAluM1;
reg tAluT1;
reg tAluQ2;
reg tAluM2;
reg tAluT2;
/* EX */
always @*
begin
tRegOutVal=0;
tRegOutId=UREG_ZZR;
tRegOutOK=UMEM_OK_OK;
tMemAddr=0;
tMemData=0;
tMemLoad=0;
tMemStore=0;
tMemOpMode=0;
tMemOpCmd2=0;
tInAluC=1'bX;
tOutAluC=1'bX;
tMacValRs=64'hX;
tMacValRt=64'hX;
// tMacValRu=64'hX;
tMacOp=0;
tShadValRs=64'hXXXXXXXX;
tShadValRt=8'hXX;
tShadOp=0;
tTriggerExc=0;
tCtlNxtPc=ctlInPc+{60'h0, opStepPc};
tCtlPrPc=tCtlNxtPc + 2;
tCtlBraPc=tCtlPrPc + (immValRi<<1);
tCtlOutSr=ctlInSr;
tCtlOutPr=ctlInPr;
tCtlOutPc=idInGenPc;
tCtlOutMach=ctlInMach;
tCtlOutMacl=ctlInMacl;
tCtlOutSp=ctlInSp;
tCtlOutGbr = ctlInGbr;
tCtlOutVbr = ctlInVbr;
tCtlOutSSr = ctlInSSr;
tCtlOutSPc = ctlInSPc;
tCtlOutSGr = ctlInSGr;
/*
tAguRtRi=regValRt+immValRi;
if(regIdRt==UREG_R0)
begin
tAguAddr=opCmd[2]?
(regValRs+tAguRtRi):
(regValRn+tAguRtRi);
end
else
begin
case(opCmd[2:0])
3'h0: tAguAddr=regValRn+tAguRtRi;
3'h1: tAguAddr=regValRn+(tAguRtRi<<1);
3'h2: tAguAddr=regValRn+(tAguRtRi<<2);
3'h3: tAguAddr=regValRn+(tAguRtRi<<3);
3'h4: tAguAddr=regValRs+tAguRtRi;
3'h5: tAguAddr=regValRs+(tAguRtRi<<1);
3'h6: tAguAddr=regValRs+(tAguRtRi<<2);
3'h7: tAguAddr=regValRs+(tAguRtRi<<3);
endcase
end
*/
tAguRtRi=regValRt+immValRi;
case(opCmd[1:0])
2'h0: tAguRtRiSc=tAguRtRi;
2'h1: tAguRtRiSc={tAguRtRi[62:0], 1'b0};
2'h2: tAguRtRiSc={tAguRtRi[61:0], 2'b0};
2'h3: tAguRtRiSc={tAguRtRi[60:0], 3'b0};
endcase
tAguAddr=(opCmd[2]?regValRs:regValRn)+
((regIdRt==UREG_R0)?tAguRtRi:tAguRtRiSc);
casez(opCmd)
UCMD_NONE: begin
end
UCMD_MOV_RR: begin
tRegOutVal=regValRs;
tRegOutId=regIdRn;
end
UCMD_MOV_RI: begin
tRegOutVal=immValRi;
tRegOutId=regIdRn;
end
UCMD_LEAB_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAW_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAL_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAQ_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_MOVB_RM: begin
tMemOpMode=5'h00;
if(regIdRt==UREG_MR_MEMDEC)
begin
tMemAddr=tAguAddr-1;
tMemData=regValRs;
tMemStore=1;
tRegOutVal=regValRn-1;
tRegOutId=regIdRn;
end
else
begin
tMemAddr=tAguAddr;
tMemData=regValRs;
tMemStore=1;
end
end
UCMD_MOVW_RM: begin
tMemOpMode=5'h01;
if(regIdRt==UREG_MR_MEMDEC)
begin
tMemAddr=tAguAddr-2;
tMemData=regValRs;
tMemStore=1;
tRegOutVal=regValRn-2;
tRegOutId=regIdRn;
end
else
begin
tMemAddr=tAguAddr;
tMemData=regValRs;
tMemStore=1;
end
end
UCMD_MOVL_RM: begin
tMemOpMode=5'h02;
if(regIdRt==UREG_MR_MEMDEC)
begin
tMemAddr=tAguAddr-4;
tMemData=regValRs;
tMemStore=1;
tRegOutVal=regValRn-4;
tRegOutId=regIdRn;
end
else
begin
tMemAddr=tAguAddr;
tMemData=regValRs;
tMemStore=1;
end
end
UCMD_MOVQ_RM: begin
tMemOpMode=5'h03;
if(regIdRt==UREG_MR_MEMDEC)
begin
tMemAddr=tAguAddr-8;
tMemData=regValRs;
tMemStore=1;
tRegOutVal=regValRn-8;
tRegOutId=regIdRn;
end
else
begin
tMemAddr=tAguAddr;
tMemData=regValRs;
tMemStore=1;
end
end
UCMD_MOVB_MR: begin
tMemAddr=tAguAddr;
tMemLoad=1;
tMemOpMode=5'h00;
if(regIdRt==UREG_MR_MEMINC)
begin
tRegOutVal=regValRs+1;
tRegOutId=regIdRs;
end
end
UCMD_MOVW_MR: begin
tMemAddr=tAguAddr;
tMemLoad=1;
tMemOpMode=5'h01;
if(regIdRt==UREG_MR_MEMINC)
begin
tRegOutVal=regValRs+2;
tRegOutId=regIdRs;
end
end
UCMD_MOVL_MR: begin
tMemAddr=tAguAddr;
tMemLoad=1;
tMemOpMode=5'h02;
if(regIdRt==UREG_MR_MEMINC)
begin
tRegOutVal=regValRs+4;
tRegOutId=regIdRs;
end
end
UCMD_MOVQ_MR: begin
tMemAddr=tAguAddr;
tMemLoad=1;
tMemOpMode=5'h03;
if(regIdRt==UREG_MR_MEMINC)
begin
tRegOutVal=regValRs+8;
tRegOutId=regIdRs;
end
end
UCMD_ALU_ADD: begin
tRegOutVal=regValRs+regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_SUB: begin
tRegOutVal=regValRs-regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_MUL: begin
// tRegOutVal=regValRs*regValRt;
tRegOutId=regIdRn;
tMacValRs = {32'h0, regValRs[31:0]};
tMacValRt = {32'h0, regValRt[31:0]};
tMacOp = 2'h3;
end
UCMD_ALU_AND: begin
tRegOutVal=regValRs®ValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_OR: begin
tRegOutVal=regValRs|regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_XOR: begin
tRegOutVal=regValRs^regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_ADDC: begin
tInAluC=ctlInSr[0];
{tOutAluC, tRegOutVal}=
{ 1'b0, regValRs+regValRt}+
{64'h0, tInAluC};
tCtlOutSr[0]=tOutAluC;
tRegOutId=regIdRn;
end
UCMD_ALU_SUBC: begin
tInAluC=ctlInSr[0];
{tOutAluC, tRegOutVal}=
{ 1'b0, regValRs-regValRt}-
{64'h0, tInAluC};
tCtlOutSr[0]=tOutAluC;
tRegOutId=regIdRn;
end
UCMD_ALU_ADDV: begin
{tOutAluC, tRegOutVal}=
{ regValRs[63], regValRs}+
{ regValRt[63], regValRt};
tCtlOutSr[0]=tOutAluC^tRegOutVal[63];
tRegOutId=regIdRn;
end
UCMD_ALU_SUBV: begin
{tOutAluC, tRegOutVal}=
{ regValRs[63], regValRs}-
{ regValRt[63], regValRt};
tCtlOutSr[0]=tOutAluC^tRegOutVal[63];
tRegOutId=regIdRn;
end
UCMD_ALU_SHAD: begin
tShadValRs=regValRs;
tShadOp=2;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHLD: begin
tShadValRs=regValRs;
tShadOp=1;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHADR: begin
tShadValRs=regValRs;
tShadOp=4;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHLDR: begin
tShadValRs=regValRs;
tShadOp=3;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_LDSH16: begin
tRegOutVal={regValRs[47:0], 16'h0} +
regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_NOT: begin
tRegOutVal=~regValRs;
tRegOutId=regIdRn;
end
UCMD_ALU_SWAPB: begin
tRegOutVal={
regValRs[55:48],
regValRs[63:56],
regValRs[39:32],
regValRs[47:40],
regValRs[23:16],
regValRs[31:24],
regValRs[ 7: 0],
regValRs[15: 8]
};
tRegOutId=regIdRn;
end
UCMD_ALU_SWAPW: begin
tRegOutVal={
regValRs[47:32],
regValRs[63:48],
regValRs[15: 0],
regValRs[31:16]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTUB: begin
tRegOutVal={56'h0, regValRs[7:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTUW: begin
tRegOutVal={48'h0, regValRs[15:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTSB: begin
tRegOutVal={regValRs[7]?56'hFF_FFFF_FFFF_FFFF:56'h0, regValRs[7:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTSW: begin
tRegOutVal={regValRs[15]?48'hFFFF_FFFF_FFFF:48'h0, regValRs[15:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_NEG: begin
tRegOutVal=-regValRs;
tRegOutId=regIdRn;
end
UCMD_ALU_NEGC: begin
{tOutAluC, tRegOutVal}=
{1'b1, ~regValRs}+
(ctlInSr[0] ? 65'h0 : 65'h1);
tRegOutId=regIdRn;
end
UCMD_ALU_DIV0S: begin
tCtlOutSr[8] = regValRs[63];
tCtlOutSr[9] = regValRt[63];
tCtlOutSr[0] = regValRs[63] ^ regValRt[63];
end
UCMD_ALU_DIV1: begin
tAluQ0 = ctlInSr[8];
tAluM0 = ctlInSr[9];
tAluT0 = ctlInSr[0];
tAluQ1 = regValRs[63];
tAluDn1[64:1] = regValRs;
tAluDn1[ 0] = tAluT0;
if (tAluQ0 == tAluM0)
tAluDn2 = tAluDn1 - {1'b0, regValRt};
else
tAluDn2 = tAluDn1 + {1'b0, regValRt};
tAluM1 = tAluDn2[64];
tAluQ2 = (tAluQ1 ^ tAluM0) ^ tAluM1;
tAluT2 = ! (tAluQ2 ^ tAluM0);
tRegOutVal = tAluDn2[63:0];
tCtlOutSr[8] = tAluQ2;
tCtlOutSr[0] = tAluT2;
tRegOutId=regIdRn;
end
UCMD_CMP_EQ: begin
tCtlOutSr[0]=(regValRs[31:0]==regValRt[31:0]);
end
UCMD_CMP_GT: begin
tCtlOutSr[0]=(regValRs[31:0]>regValRt[31:0])^
(regValRs[31]^regValRt[31]);
end
UCMD_CMP_HI: begin
tCtlOutSr[0]=(regValRs[31:0]>regValRt[31:0]);
end
UCMD_CMP_GE: begin
tCtlOutSr[0]=(regValRs[31:0]>=regValRt[31:0])^
(regValRs[31]^regValRt[31]);
end
UCMD_CMP_HS: begin
tCtlOutSr[0]=(regValRs[31:0]>=regValRt[31:0]);
end
UCMD_CMP_TST: begin
tCtlOutSr[0]=((regValRs[31:0] & regValRt[31:0])==0);
end
UCMD_ALU_MULUW: begin
tMacValRs = {48'h0, regValRs[15:0]};
tMacValRt = {48'h0, regValRt[15:0]};
tMacOp = 2'h1;
end
UCMD_ALU_MULSW: begin
tMacValRs = {
regValRs[15]?48'hFFFFFFFFFFFF:48'h000000000000,
regValRs[15:0]};
tMacValRt = {
regValRt[15]?48'hFFFFFFFFFFFF:48'h000000000000,
regValRt[15:0]};
tMacOp = 2'h1;
end
UCMD_ALU_DMULU: begin
tMacValRs = {32'h0, regValRs[31:0]};
tMacValRt = {32'h0, regValRt[31:0]};
tMacOp = 2'h1;
end
UCMD_ALU_DMULS: begin
tMacValRs = {regValRs[31]?32'hFFFFFFFF:32'h00000000, regValRs[31:0]};
tMacValRt = {regValRt[31]?32'hFFFFFFFF:32'h00000000, regValRt[31:0]};
tMacOp = 2'h1;
end
UCMD_BRAx: begin
tCtlOutPc=tCtlBraPc;
end
UCMD_BSRx: begin
tCtlOutPc=tCtlBraPc;
tCtlOutPr=tCtlPrPc;
end
UCMD_RTSx: begin
tCtlOutPc=ctlInPr;
end
UCMD_RTEx: begin
tCtlOutPc=ctlInSPc;
tCtlOutSr=ctlInSSr;
tCtlOutSp=ctlInSGr;
end
default: begin end
endcase
if(tMacOp!=0)
begin
case(tMacOp)
2'h0:
{tCtlOutMach, tCtlOutMacl} =
{ ctlInMach, ctlInMacl };
2'h1:
{tCtlOutMach, tCtlOutMacl} = tMacValRu;
2'h2:
{tCtlOutMach, tCtlOutMacl} =
{ ctlInMach, ctlInMacl } + tMacValRu;
2'h3: begin
{tCtlOutMach, tCtlOutMacl} =
{ ctlInMach, ctlInMacl };
tRegOutVal = tMacValRu[63:0];
end
endcase
tRegOutOK = (tMacOpB==tMacOp) ?
UMEM_OK_OK : UMEM_OK_HOLD;
end
if(tShadOp!=0)
tRegOutVal = tShadValRn;
if(tTriggerExc)
begin
tCtlOutSSr = ctlInSr;
tCtlOutSPc = ctlInPc;
tCtlOutSGr = ctlInSp;
tCtlOutPc=ctlInVbr+64'h00000100;
tCtlOutSr=ctlInSr;
tCtlOutSr[30:28]=3'b111;
end
end
reg[63:0] tMacValRsA;
reg[63:0] tMacValRtA;
reg[31:0] tMacValRuA_AA;
reg[31:0] tMacValRuA_AB;
reg[31:0] tMacValRuA_AC;
reg[31:0] tMacValRuA_AD;
reg[31:0] tMacValRuA_BA;
reg[31:0] tMacValRuA_BB;
reg[31:0] tMacValRuA_BC;
reg[31:0] tMacValRuA_BD;
reg[31:0] tMacValRuA_CA;
reg[31:0] tMacValRuA_CB;
reg[31:0] tMacValRuA_CC;
reg[31:0] tMacValRuA_CD;
reg[31:0] tMacValRuA_DA;
reg[31:0] tMacValRuA_DB;
reg[31:0] tMacValRuA_DC;
reg[31:0] tMacValRuA_DD;
reg[1:0] tMacOpA0;
reg[1:0] tMacOpA1;
reg[31:0] tMacValRuB_AA;
reg[31:0] tMacValRuB_AB;
reg[31:0] tMacValRuB_AC;
reg[31:0] tMacValRuB_AD;
reg[31:0] tMacValRuB_BA;
reg[31:0] tMacValRuB_BB;
reg[31:0] tMacValRuB_BC;
reg[31:0] tMacValRuB_BD;
reg[31:0] tMacValRuB_CA;
reg[31:0] tMacValRuB_CB;
reg[31:0] tMacValRuB_CC;
reg[31:0] tMacValRuB_CD;
reg[31:0] tMacValRuB_DA;
reg[31:0] tMacValRuB_DB;
reg[31:0] tMacValRuB_DC;
reg[31:0] tMacValRuB_DD;
reg[1:0] tMacOpB0;
reg[1:0] tMacOpB1;
always @*
begin
/* EX+1 */
tMacValRuA_AA =
{16'h0, tMacValRsA[15: 0]} *
{16'h0, tMacValRtA[15: 0]};
tMacValRuA_AB =
{16'h0, tMacValRsA[15: 0]} *
{16'h0, tMacValRtA[31:16]};
tMacValRuA_AC =
{16'h0, tMacValRsA[15: 0]} *
{16'h0, tMacValRtA[47:32]};
tMacValRuA_AD =
{16'h0, tMacValRsA[15: 0]} *
{16'h0, tMacValRtA[63:48]};
tMacValRuA_BA =
{16'h0, tMacValRsA[31:16]} *
{16'h0, tMacValRtA[15: 0]};
tMacValRuA_BB =
{16'h0, tMacValRsA[31:16]} *
{16'h0, tMacValRtA[31:16]};
tMacValRuA_BC =
{16'h0, tMacValRsA[31:16]} *
{16'h0, tMacValRtA[47:32]};
tMacValRuA_BD =
{16'h0, tMacValRsA[31:16]} *
{16'h0, tMacValRtA[56:48]};
tMacValRuA_CA =
{16'h0, tMacValRsA[47:32]} *
{16'h0, tMacValRtA[15: 0]};
tMacValRuA_CB =
{16'h0, tMacValRsA[47:32]} *
{16'h0, tMacValRtA[31:16]};
tMacValRuA_CC =
{16'h0, tMacValRsA[47:32]} *
{16'h0, tMacValRtA[47:32]};
tMacValRuA_CD =
{16'h0, tMacValRsA[47:32]} *
{16'h0, tMacValRtA[63:48]};
tMacValRuA_DA =
{16'h0, tMacValRsA[63:48]} *
{16'h0, tMacValRtA[15: 0]};
tMacValRuA_DB =
{16'h0, tMacValRsA[63:48]} *
{16'h0, tMacValRtA[31:16]};
tMacValRuA_DC =
{16'h0, tMacValRsA[63:48]} *
{16'h0, tMacValRtA[47:32]};
tMacValRuA_DD =
{16'h0, tMacValRsA[63:48]} *
{16'h0, tMacValRtA[56:48]};
tMacOpA1=tMacOpA0;
/* EX+2 */
tMacValRuA = {tMacValRuB_DD, tMacValRuB_CC, tMacValRuB_BB, tMacValRuB_AA} +
{ 48'h0, tMacValRuB_AD, tMacValRuB_AB, 16'h0} +
{ 48'h0, tMacValRuB_DA, tMacValRuB_BA, 16'h0} +
{ 64'h0, tMacValRuB_AC, 32'h0} +
{ 64'h0, tMacValRuB_CA, 32'h0};
tMacOpB1 = tMacOpB0;
end
always @ (posedge clock)
begin
/* EX+0 */
tMacValRsA <= tMacValRs;
tMacValRtA <= tMacValRt;
tMacOpA0 <= tMacOp;
/* EX+1 */
tMacValRuB_AA <= tMacValRuA_AA;
tMacValRuB_AB <= tMacValRuA_AB;
tMacValRuB_AC <= tMacValRuA_AC;
tMacValRuB_AD <= tMacValRuA_AD;
tMacValRuB_BA <= tMacValRuA_BA;
tMacValRuB_BB <= tMacValRuA_BB;
tMacValRuB_BA <= tMacValRuA_BC;
tMacValRuB_BB <= tMacValRuA_BD;
tMacValRuB_CA <= tMacValRuA_CA;
tMacValRuB_CB <= tMacValRuA_DB;
tMacValRuB_CC <= tMacValRuA_CC;
tMacValRuB_CD <= tMacValRuA_CD;
tMacValRuB_DA <= tMacValRuA_DA;
tMacValRuB_DB <= tMacValRuA_DB;
tMacValRuB_DC <= tMacValRuA_DC;
tMacValRuB_DD <= tMacValRuA_DD;
tMacOpB0 <= tMacOpA1;
/* EX+2 */
tMacValRu <= tMacValRuA;
tMacOpB <= tMacOpB1;
end
endmodule
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
wire r1,r2;
wire a1,a2;
wire r,a;
two_phase_event_gen U_PORT1_EVENT_GEN (
.run(rst_async_n),
.req(r1),
.ack(a1)
);
two_phase_event_gen U_PORT2_EVENT_GEN (
.run(rst_async_n),
.req(r2),
.ack(a2)
);
and_r1_2ph U_ASYNC_AND(
// Input ports (req/ack)
.r1(r1),
.a1(a1),
.r2(r2),
.a2(a2),
// Output ports
.r(r),
.a(a),
.rstn(rst_async_n)
);
two_phase_slave U_SLAVE(.req(r), .ack(a));
// assign #55 a = r;
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
reg clk;
initial clk = 0;
always
#100 clk = ~clk;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n = 1'b0;
#5;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#200000;
$display("-I- Done !");
$finish;
end
// four_phase_assertion U_CHECKER0(.req(r0),.ack(a0),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER1(.req(r1),.ack(a1),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER2(.req(r2),.ack(a2),.rstn(rst_async_n));
// just for debug
//assign input_port1_ongoing_req = r1 ^ a1;
//assign input_port2_ongoing_req = r2 ^ a2;
//assign output_port1_unstable = g1 ^ d1;
//assign output_port2_unstable = g2 ^ d2;
//
event error1;
event error2;
assign r1_qual = r1 & a1;
assign r2_qual = r2 & a2;
assign r_qual = r & a;
// If r rises, it is because of one of the incoming request
always@(posedge r)
if(! (r1 | r2)) ->error1;
initial begin
#1;
@(error1 or error2);
$display("-E error found in protocol");
#100;
$finish;
end
endmodule // tb
|
/*
*
* Clock, reset generation unit for ML501 board
*
* Implements clock generation according to design defines
*
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
`include "synthesis-defines.v"
module clkgen
(
// Main clocks in, depending on board
sys_clk_in_p, sys_clk_in_n,
// Wishbone clock and reset out
wb_clk_o,
wb_rst_o,
// JTAG clock
`ifdef JTAG_DEBUG
tck_pad_i,
dbg_tck_o,
`endif
// Main memory clocks
`ifdef XILINX_DDR2
ddr2_if_clk_o,
ddr2_if_rst_o,
clk200_o,
`endif
// Asynchronous, active low reset in
rst_n_pad_i
);
input sys_clk_in_p,sys_clk_in_n;
output wb_rst_o;
output wb_clk_o;
`ifdef JTAG_DEBUG
input tck_pad_i;
output dbg_tck_o;
`endif
`ifdef XILINX_DDR2
output ddr2_if_clk_o;
output ddr2_if_rst_o;
output clk200_o;
`endif
// Asynchronous, active low reset (pushbutton, typically)
input rst_n_pad_i;
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
// Xilinx synthesis tools appear cluey enough to instantiate buffers when and
// where they're needed, so we do simple assigns for this tech.
assign async_rst_n = rst_n_pad_i;
// Everyone likes active-high reset signals...
assign async_rst = ~async_rst_n;
`ifdef JTAG_DEBUG
assign dbg_tck_o = tck_pad_i;
`endif
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
// An active-low synchronous reset from ethernet PLL
wire sync_eth_rst_n;
wire sys_clk_in_200;
/* DCM0 wires */
wire dcm0_clk0_prebufg, dcm0_clk0;
wire dcm0_clkfx_prebufg, dcm0_clkfx;
wire dcm0_clkdv_prebufg, dcm0_clkdv;
wire dcm0_locked;
/* Dif. input buffer for 200MHz board clock, generate SE 200MHz */
IBUFGDS_LVPECL_25 sys_clk_in_ibufds
(
.O(sys_clk_in_200),
.I(sys_clk_in_p),
.IB(sys_clk_in_n));
/* DCM providing main system/Wishbone clock */
DCM_BASE dcm0
(
// Outputs
.CLK0 (dcm0_clk0_prebufg),
.CLK180 (),
.CLK270 (),
.CLK2X180 (),
.CLK2X (),
.CLK90 (),
.CLKDV (dcm0_clkdv_prebufg),
.CLKFX180 (),
.CLKFX (dcm0_clkfx_prebufg),
.LOCKED (dcm0_locked),
// Inputs
.CLKFB (dcm0_clk0),
.CLKIN (sys_clk_in_200),
.RST (1'b0));
// Generate 150 MHz from CLKFX
defparam dcm0.CLKFX_MULTIPLY = 3;
defparam dcm0.CLKFX_DIVIDE = 4;
// Generate 50 MHz from CLKDV
defparam dcm0.CLKDV_DIVIDE = 4;
BUFG dcm0_clk0_bufg
(// Outputs
.O (dcm0_clk0),
// Inputs
.I (dcm0_clk0_prebufg));
BUFG dcm0_clkfx_bufg
(// Outputs
.O (dcm0_clkfx),
// Inputs
.I (dcm0_clkfx_prebufg));
BUFG dcm0_clkdv_bufg
(// Outputs
.O (dcm0_clkdv),
// Inputs
.I (dcm0_clkdv_prebufg));
assign wb_clk_o = dcm0_clkdv;
assign sync_rst_n = dcm0_locked;
`ifdef XILINX_DDR2
assign ddr2_if_clk_o = dcm0_clkfx; // 150 MHz
assign clk200_o = dcm0_clk0; // 200 MHz
`endif
//
// Reset generation
//
//
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
`ifdef XILINX_DDR2
// Reset generation for DDR2 controller
reg [15:0] ddr2_if_rst_shr;
always @(posedge ddr2_if_clk_o or posedge async_rst)
if (async_rst)
ddr2_if_rst_shr <= 16'hffff;
else
ddr2_if_rst_shr <= {ddr2_if_rst_shr[14:0], ~(sync_rst_n)};
assign ddr2_if_rst_o = ddr2_if_rst_shr[15];
`endif
endmodule // clkgen |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:35:17 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/crash_pixel/crash_pixel_sim_netlist.v
// Design : crash_pixel
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "crash_pixel,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module crash_pixel
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "12" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "crash_pixel.mem" *)
(* C_INIT_FILE_NAME = "crash_pixel.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2703" *)
(* C_READ_DEPTH_B = "2703" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "2703" *)
(* C_WRITE_DEPTH_B = "2703" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
crash_pixel_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module crash_pixel_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
crash_pixel_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[3:0]),
.douta(douta[3:0]),
.wea(wea));
crash_pixel_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:4]),
.douta(douta[11:4]),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module crash_pixel_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
crash_pixel_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module crash_pixel_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
crash_pixel_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module crash_pixel_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000330000000000000000),
.INIT_02(256'h0000660000000000477200000000000000000000000000000000000006600000),
.INIT_03(256'h0481000000000006500000000036983000000000000000000000003610000000),
.INIT_04(256'h0000000000003620000000000166000000002888830000000000000000000000),
.INIT_05(256'h0000000000000000000000001640000000027876200016778888300000000000),
.INIT_06(256'h0688788888300000000000000000000000007730000000288882002588887883),
.INIT_07(256'h0000288877667887888883000000000000000000000000069820000002888720),
.INIT_08(256'h0000068886342002887888887888888820000000000000000000000000688740),
.INIT_09(256'h0000000000000000688788850038888888888888888310100000000000000000),
.INIT_0A(256'h7888888630000000000000000006887888766788888888888888887777667600),
.INIT_0B(256'h8888888888888887883000000000000000001478888878888778888888888887),
.INIT_0C(256'h8888888888888888888888888878830000000000000000048878888888888888),
.INIT_0D(256'h4358887788888888888888888888888888877874200000000000000377788788),
.INIT_0E(256'h0000000000488877888888888888888888888888888888887500000000000001),
.INIT_0F(256'h8888882000000000000057888778888888888888888888888888888888830000),
.INIT_10(256'h8888888888888888830000000000025887788888888888888888888888888888),
.INIT_11(256'h8888888888888888888888888888766750000000377788788888888888888888),
.INIT_12(256'h0247877888888888888888888888888888888778888743342000114887888888),
.INIT_13(256'h7889710000000057888888888888888888888888888888888888878888830000),
.INIT_14(256'h8888888887787443000000000048888888888888888888888888888888888888),
.INIT_15(256'h8888888888888888788888750000000000002588888888888888888888888888),
.INIT_16(256'h8888888888888888888888888887888884000000000000178778888888888888),
.INIT_17(256'h0036887888888888888888888888888888887787444410000000000037887788),
.INIT_18(256'h0000000000001788887788888888888888888888888888888750000000000000),
.INIT_19(256'h8888888200000000000000378888877888888888888888888888888888883000),
.INIT_1A(256'h8888888888888888883000000000000002444446887888888888888888888888),
.INIT_1B(256'h8888888888888888888888888888820000000000000000000037788888888888),
.INIT_1C(256'h0000000000688888888888888888888888888888530000000000000000000016),
.INIT_1D(256'h0000000000000000000006888888888888888888888888888778600000000000),
.INIT_1E(256'h8778888888741000000000000000000068888888888888888888888888887786),
.INIT_1F(256'h7887777888888877777778840000000000000000024788887788888788888788),
.INIT_20(256'h8887138878878861138888888311111598860000000000000000388887788788),
.INIT_21(256'h0000000003588630147887885200388788882000002444300000000000000003),
.INIT_22(256'h0000000000000000000078784000068887610000788878820000000000000000),
.INIT_23(256'h5888820000000000000000000000000688840000688850000001688788200000),
.INIT_24(256'h8740000000016888200000000000000000000000007985200006889500000002),
.INIT_25(256'h2100000006982000000000006982000000000000000000000001167600000068),
.INIT_26(256'h0000000000A00000000077300000000000035820000000000000000000000098),
.INIT_27(256'h0000000000000000000000000000000640000000000000028300000000000000),
.INIT_28(256'h0000014100000000000000000000000000000000000000000000000000283000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:4],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module crash_pixel_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h4F4F4F00004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_01(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_02(256'h4F004F4F4F4F4F4F4F4F4F4F4F006666004F4F4F4F4F4F4F4F4F4F000000004F),
.INIT_03(256'h4F4F4F4F4F11111100004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_04(256'h4F4F4F4F4F4F4F4F4F4F4F1111114F4F4F4F4F4F4F4F4F0000DDCC00004F4F4F),
.INIT_05(256'h4F4F0000CCCC00004F4F4F4F4F00000088DDDD55004F4F4F4F4F4F4F4F4F4F4F),
.INIT_06(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0077DD33004F4F4F4F4F4F),
.INIT_07(256'h0088FF22004F4F4F4F4F4F4F000000CCBB004F4F4F000000001177DDFFFF6600),
.INIT_08(256'h0000111155FFFFFFFF66004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_09(256'h4F4F4F4F4F4F4F4F4F4F4F0077DD44114F4F4F4F4F4F4F000011DDCC11114F4F),
.INIT_0A(256'h4F4F0044DDFFFFDD4400000033DDDDEEFFFFFFFF66004F4F4F4F4F4F4F4F4F4F),
.INIT_0B(256'h004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F1122CC99004F4F4F4F),
.INIT_0C(256'h4F4F0000EEDD771100004F4F4F0055FFFFFFFF44000044AAFFFFFFFFFFFFFF66),
.INIT_0D(256'h11CCFFFFFFFFFFFFFFFF66004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0E(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F0011CCFFFF441100004F4F0055FFFFFFFF5511),
.INIT_0F(256'h00004F0055FFFFFFFFEEDDDDFFFFFFFFFFFFFFFFFF66004F4F4F4F4F4F4F4F4F),
.INIT_10(256'h55004F4F000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0011CCFFFFEE8800),
.INIT_11(256'h4F4F4F0011CCFFFFFFDD777755000044FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFF77224F22111111114F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_13(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000CCFFFFFFFFFFFFBB111166FFFFFFFFFF),
.INIT_14(256'hFFFFFFDDDDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEEEFFEEDDDDEECC1100),
.INIT_15(256'hFFFFFFFFFFFFFFCC7700004F4F4F4F4F4F4F4F4F4F4F4F4F4F0000CCFFFFFFFF),
.INIT_16(256'h4F4F00003388EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF660000004F4F4F4F4F4F4F4F4F4F),
.INIT_18(256'h4F4F4F4F4F4F4F4F4F4F4F4F11111188FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_19(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF66004F),
.INIT_1A(256'hFFFFFFFFFFFFFF8844004F4F4F4F4F4F4F4F4F4F00000066DDDDEEFFFFFFFFFF),
.INIT_1B(256'h7777BBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEBB00004F4F4F4F4F4F4F4F4F4F0044),
.INIT_1D(256'h4F4F4F4F4F4F4F4F4F1188FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF771100004F),
.INIT_1F(256'hFFFFFFFFFFFF55000000004F4F4F4F4F4F4F0000BBEEFFFFFFFFFFFFFFFFFFFF),
.INIT_20(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_21(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77111111114F4F4F4F4F4F005599FF),
.INIT_22(256'hBB00000000004F0077EEEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_23(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEDDDDDD),
.INIT_24(256'hFFFFFFFFFFFFFFFFFFFFFFFF8877778855004F11222299FFFFFFFFFFFFFFFFFF),
.INIT_25(256'h004499FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_26(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77004F4F00),
.INIT_27(256'hFFFFFFFFEE33114F4F4F4F4F0000BBEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_28(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_29(256'hFFFFFFFFFFFFFFFFFFFFFFFFFF888877004F4F4F4F4F4F4F4F0077FFFFFFFFFF),
.INIT_2A(256'h4F4F4F0066AAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEBB0000004F4F4F4F4F),
.INIT_2C(256'hFF88114F4F4F4F4F4F4F4F4F4F1133EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2E(256'hFFFFFFFFFFFFFFFF8888888833004F4F4F4F4F4F4F4F4F0066EEFFFFFFFFFFFF),
.INIT_2F(256'h4F0066CCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_30(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEBB00000000004F4F4F4F4F4F4F4F),
.INIT_31(256'h4F4F4F4F4F4F4F4F4F4F4F1133EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_32(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77110000),
.INIT_33(256'hFFFFFFFFFFFFFF5500004F4F4F4F4F4F4F4F4F4F4F0077FFFFFFFFFFFFFFFFFF),
.INIT_34(256'h00559988888888CCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_35(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF55004F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_36(256'h4F4F4F4F4F4F4F4F4F4F4F4F00000000000066EEFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_37(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF55004F),
.INIT_38(256'hFFFFFFFFFFFFFFFFAA66004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F1133DD),
.INIT_39(256'h4F4F4F4F4F4F4F4F0000DDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD00004F4F4F4F4F4F4F4F4F),
.INIT_3B(256'h00004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0011DDFFFFFFFFFFFFFFFFFFFF),
.INIT_3C(256'hDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCC),
.INIT_3D(256'hFFFFFFFFFFFFFFFFFFFFEE8833004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000),
.INIT_3E(256'h4F4F4F4F4F4F4F4F004488EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3F(256'hFFFFFFFFEEEEEEFFFFFFFFFFFFFFEEEEEEEEEEEEFFFFFF77114F4F4F4F4F4F4F),
.INIT_40(256'hFFFFFFCC11004F4F4F4F4F4F4F4F4F4F4F4F4F0077FFFFFFFFEEEEFFFFFFFFFF),
.INIT_41(256'hFFFFFFFF3366FFFFFFFFFFFFFFFFBB111166FFFFFFFFFFFFFF661111111111BB),
.INIT_42(256'hFFFFFFFF4400000000005588888877114F4F4F4F4F4F4F4F4F4F4F4F4F4F0066),
.INIT_43(256'h4F4F4F4F4F4F4F4F1177BBFFFFCC77002288EEFFFFFFFFFFAA55000066FFFFFF),
.INIT_44(256'hFFFFDD33004F4F4FEEFFFFFFFFFFFF55004F4F4F4F00000000004F4F4F4F4F4F),
.INIT_45(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0011EEFFFFFF8800000000CCFFFF),
.INIT_46(256'hFFFFFF99004F0000CCFFFFFFAA11004F4F4F1122CCFFFFFFFFFF55004F4F4F4F),
.INIT_47(256'hAAFFFFFFFF55004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0011DD),
.INIT_48(256'h4F4F4F4F4F4F4F4F0011EEFFFF9955004F0000CCFFFFFFAA004F4F4F4F4F0066),
.INIT_49(256'hFFEE99004F4F4F4F4F4F0033DDFFFFFF55004F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_4A(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F1122CCEECC11004F4F0000CCFF),
.INIT_4B(256'h3311114F4F4F4F0000CCFFFF55114F4F4F4F4F4F4F4F1111CCFFFF55004F4F4F),
.INIT_4C(256'h4F4F0066AAFF55004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F9999),
.INIT_4D(256'h4F4F4F4F4F4F4F4F4F4FAA0000004F4F4F4F0000EEEE7711004F4F4F4F4F4F4F),
.INIT_4E(256'h99004F4F4F4F4F4F4F4F4F4F4F4F0044FF66004F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_4F(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000CC),
.INIT_50(256'h4F4F4F4F4F4F4F4F4F4F11114F4F4F4F4F4F4F4F4F4F4F4F4F0044FF66004F4F),
.INIT_51(256'h4F4F4F4F00228833004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_52(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00004F4F4F4F4F4F4F4F4F),
.INIT_53(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000000004F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_54(256'h00000000000000000000000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module crash_pixel_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
crash_pixel_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "crash_pixel.mem" *)
(* C_INIT_FILE_NAME = "crash_pixel.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2703" *) (* C_READ_DEPTH_B = "2703" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "2703" *) (* C_WRITE_DEPTH_B = "2703" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module crash_pixel_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [11:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [11:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [11:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
crash_pixel_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module crash_pixel_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
crash_pixel_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module main(CLOCK_50, KEY, LEDR, SW, UART_RXD, UART_TXD);
input CLOCK_50;
input KEY[3:0];
output [17:0] LEDR;
input [17:0] SW;
input UART_RXD;
output UART_TXD;
integer i;
// Regs
reg [7:0] current_value, value_into_genetico;
reg [10:0] current_circuit_les[8:0];
reg [3:0] current_circuit_outs[1:0];
// Wires
wire [31:0] data_to_send, rs232_received_data;
wire [7:0] mem_out, genetico_out;
wire rx_done, tx_done, tx_send, start_sampling, start_sending, mem_write,
finished_sampling, finished_sending, mem_addr, fetch_value, serial_reset,
insert_value, done_receiving, set_current_circuit;
wire [15:0] sampler_mem_addr, sender_mem_addr;
wire [7:0] received_data[199:0];
assign LEDR[7:0] = current_value;
assign LEDR[17:10] = genetico_out;
assign data_to_send = {24'b0, mem_out};
always @(posedge CLOCK_50) begin
if (fetch_value)
current_value <= received_data[1];
if (insert_value)
value_into_genetico <= current_value;
if (set_current_circuit) begin
for (i = 0; i < 9; i = i + 1) begin
current_circuit_les[i][10:8] <= received_data[(i * 3) + 1][2:0];
current_circuit_les[i][7:4] <= received_data[(i * 3) + 2][3:0];
current_circuit_les[i][3:0] <= received_data[(i * 3) + 3][3:0];
end
for (i = 0; i < 2; i = i + 1) begin
current_circuit_outs[i] <= received_data[i + 27 + 1][3:0];
end
end
end
sampler sampler(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iStartSignal(start_sampling),
.oAddress(sampler_mem_addr),
.oFinished(finished_sampling)
);
sender sender(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iTxDone(tx_done),
.iStartSignal(start_sending),
.oAddress(sender_mem_addr),
.oFinished(finished_sending),
.oTxSend(tx_send)
);
main_fsm fsm(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iDoneReceiving(done_receiving),
.iReceivedData(received_data),
.iSamplingDone(finished_sampling),
.iSendingDone(finished_sending),
.oMemWrite(mem_write),
.oMemAddr(mem_addr),
.oStartSampling(start_sampling),
.oStartSending(start_sending),
.oFetchValue(fetch_value),
.oSetCurrentCircuit(set_current_circuit),
.oInsertValue(insert_value),
.oResetSerial(serial_reset)
);
memoria memoria(
.address(mem_addr ? sender_mem_addr : sampler_mem_addr),
.clock(CLOCK_50),
.data(genetico_out),
.wren(mem_write),
.q(mem_out)
);
data_receiver data_receiver(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iRxDone(rx_done),
.iReceivedData(rs232_received_data),
.oResultData(received_data),
.oDoneReceiving(done_receiving)
);
uart rs232(
.sys_clk(CLOCK_50),
.sys_rst(~KEY[1] | serial_reset),
.csr_a(14'b0),
.csr_we(tx_send),
.csr_di(data_to_send),
.csr_do(rs232_received_data),
.rx_irq(rx_done),
.tx_irq(tx_done),
.uart_rx(UART_RXD),
.uart_tx(UART_TXD)
);
genetico genetico(
.conf_les(current_circuit_les),
.conf_outs(current_circuit_outs),
.in(value_into_genetico),
.out(genetico_out)
);
endmodule |
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_no_transition (clock, reset, enable, test_expr, start_state, next_state, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr, start_state, next_state;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NO_TRANSITION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_no_transition_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_no_transition_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_no_transition_psl_logic.v"
`else
`endmodule // ovl_no_transition
`endif
|
`include "constants.vh"
`default_nettype none
module tag_generator(
input wire clk,
input wire reset,
input wire branchvalid1,
input wire branchvalid2,
input wire prmiss,
input wire prsuccess,
input wire enable,
input wire [`SPECTAG_LEN-1:0] tagregfix,
output wire [`SPECTAG_LEN-1:0] sptag1,
output wire [`SPECTAG_LEN-1:0] sptag2,
output wire speculative1,
output wire speculative2,
output wire attachable,
output reg [`SPECTAG_LEN-1:0] tagreg
);
// reg [`SPECTAG_LEN-1:0] tagreg;
reg [`BRDEPTH_LEN-1:0] brdepth;
assign sptag1 = (branchvalid1) ?
{tagreg[`SPECTAG_LEN-2:0], tagreg[`SPECTAG_LEN-1]}
: tagreg;
assign sptag2 = (branchvalid2) ?
{sptag1[`SPECTAG_LEN-2:0], sptag1[`SPECTAG_LEN-1]}
: sptag1;
assign speculative1 = (brdepth != 0) ? 1'b1 : 1'b0;
assign speculative2 = ((brdepth != 0) || branchvalid1) ? 1'b1 : 1'b0;
assign attachable = (brdepth + branchvalid1 + branchvalid2)
> (`BRANCH_ENT_NUM + prsuccess) ? 1'b0 : 1'b1;
always @ (posedge clk) begin
if (reset) begin
tagreg <= `SPECTAG_LEN'b1;
brdepth <= `BRDEPTH_LEN'b0;
end else begin
tagreg <= prmiss ? tagregfix :
~enable ? tagreg :
sptag2;
brdepth <= prmiss ? `BRDEPTH_LEN'b0 :
~enable ? brdepth - prsuccess :
brdepth + branchvalid1 + branchvalid2 - prsuccess;
end
end
endmodule // tag_generator
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_1_V
`define SKY130_FD_SC_MS__O2BB2AI_1_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_1_V
|
/******************************************************************************
-- (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_0.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_0 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_0 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_0 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_0 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_0 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_0
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_0 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_0 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_0 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_0 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_0 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_0 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_0 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_0 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_0 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_0 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_0 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_0
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_0 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_0
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_0
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_0
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_0) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_0_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_0_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_0_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_0",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_0" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_0_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 2000; // 2 ns
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
BLK_MEM_GEN_v8_0_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN (1'b0),
.DBITERR_IN (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN ({C_ADDRB_WIDTH{1'b0}}),
.RDADDRECC ()
);
// Port B
BLK_MEM_GEN_v8_0_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN (sbiterr_in),
.DBITERR_IN (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN (rdaddrecc_in),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_0_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision <= collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision <= 0;
end
end else begin
is_collision <= 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision <= 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision <= 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a <= collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a <= 0;
end
end else begin
is_collision_a <= 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a <= collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a <= 0;
end
end else begin
is_collision_delay_a <= 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b <= collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b <= 0;
end
end else begin
is_collision_b <= 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b <= collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b <= 0;
end
end else begin
is_collision_delay_b <= 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_0
#(parameter C_CORENAME = "blk_mem_gen_v8_0",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_0_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_0_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_0_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_0_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_0
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_0
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_0
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_0_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_0_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// Major Functions: DE2 TV Box
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Joe Yang :| 05/07/05 :| Initial Revision
// V1.1 :| Johnny Chen :| 05/09/05 :| Changed YCbCr2RGB Block,
// RGB output 8 Bits => 10 Bits
// V1.2 :| Johnny Chen :| 05/10/05 :| H_SYNC & V_SYNC Timing fixed.
// V1.3 :| Johnny Chen :| 05/11/16 :| Added FLASH Address FL_ADDR[21:20]
// V1.4 :| Joe Yang :| 06/07/20 :| Modify Output Color
// V2.0 :| Johnny Chen :| 06/11/20 :| New Version for DE2 v2.X PCB.
// --------------------------------------------------------------------
module DE2_TV
(
//////////////////// Clock Input ////////////////////
OSC_27, // 27 MHz
OSC_50, // 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Button[3:0]
//////////////////// DPDT Switch ////////////////////
DPDT_SW, // DPDT Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digital 0
HEX1, // Seven Segment Digital 1
HEX2, // Seven Segment Digital 2
HEX3, // Seven Segment Digital 3
HEX4, // Seven Segment Digital 4
HEX5, // Seven Segment Digital 5
HEX6, // Seven Segment Digital 6
HEX7, // Seven Segment Digital 7
//////////////////////// LED ////////////////////////
LED_GREEN, // LED Green[8:0]
LED_RED, // LED Red[17:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
//////////////////////// IRDA ////////////////////////
IRDA_TXD, // IRDA Transmitter
IRDA_RXD, // IRDA Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 0
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 22 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Adress bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////
OTG_DATA, // ISP1362 Data bus 16 Bits
OTG_ADDR, // ISP1362 Address 2 Bits
OTG_CS_N, // ISP1362 Chip Select
OTG_RD_N, // ISP1362 Write
OTG_WR_N, // ISP1362 Read
OTG_RST_N, // ISP1362 Reset
OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0, // ISP1362 Interrupt 0
OTG_INT1, // ISP1362 Interrupt 1
OTG_DREQ0, // ISP1362 DMA Request 0
OTG_DREQ1, // ISP1362 DMA Request 1
OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_DAT3, // SD Card Data 3
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (data in)
TCK, // CPLD -> FPGA (clk)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
//////////// Ethernet Interface ////////////////////////
ENET_DATA, // DM9000A DATA bus 16Bits
ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N, // DM9000A Chip Select
ENET_WR_N, // DM9000A Write
ENET_RD_N, // DM9000A Read
ENET_RST_N, // DM9000A Reset
ENET_INT, // DM9000A Interrupt
ENET_CLK, // DM9000A Clock 25 MHz
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////// TV Decoder ////////////////////////
TD_DATA, // TV Decoder Data bus 8 bits
TD_HS, // TV Decoder H_SYNC
TD_VS, // TV Decoder V_SYNC
TD_RESET, // TV Decoder Reset
TD_CLK, // TV Decoder Line Locked Clock
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input OSC_27; // 27 MHz
input OSC_50; // 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Button[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [17:0] DPDT_SW; // DPDT Switch[17:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] HEX0; // Seven Segment Digital 0
output [6:0] HEX1; // Seven Segment Digital 1
output [6:0] HEX2; // Seven Segment Digital 2
output [6:0] HEX3; // Seven Segment Digital 3
output [6:0] HEX4; // Seven Segment Digital 4
output [6:0] HEX5; // Seven Segment Digital 5
output [6:0] HEX6; // Seven Segment Digital 6
output [6:0] HEX7; // Seven Segment Digital 7
//////////////////////////// LED ////////////////////////////
output [8:0] LED_GREEN; // LED Green[8:0]
output [17:0] LED_RED; // LED Red[17:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
//////////////////////////// IRDA ////////////////////////////
output IRDA_TXD; // IRDA Transmitter
input IRDA_RXD; // IRDA Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM High-byte Data Mask
output SRAM_LB_N; // SRAM Low-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////////////
inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
output OTG_CS_N; // ISP1362 Chip Select
output OTG_RD_N; // ISP1362 Write
output OTG_WR_N; // ISP1362 Read
output OTG_RST_N; // ISP1362 Reset
output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
input OTG_INT0; // ISP1362 Interrupt 0
input OTG_INT1; // ISP1362 Interrupt 1
input OTG_DREQ0; // ISP1362 DMA Request 0
input OTG_DREQ1; // ISP1362 DMA Request 1
output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
inout SD_DAT; // SD Card Data
inout SD_DAT3; // SD Card Data 3
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
input TD_CLK; // TV Decoder Line Locked Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
////////////////////////////////////////////////////////////////////
// Enable TV Decoder
assign TD_RESET = KEY[0];
// For Audio CODEC
wire AUD_CTRL_CLK; // For Audio Controller
assign AUD_XCK = AUD_CTRL_CLK;
assign LED_GREEN = VGA_Y;
assign LED_RED[9:0] = VGA_X;
assign LED_RED[17:14] ={TD_Stable,DLY0,DLY1,DLY2};
assign GPIO_0[4:0]={TD_DATA,TD_Stable,TD_VS,TD_HS,TD_CLK};
assign GPIO_0[5]=0;
// 7 segment LUT
SEG7_LUT_8 u0 ( .oSEG0(HEX0),
.oSEG1(HEX1),
.oSEG2(HEX2),
.oSEG3(HEX3),
.oSEG4(HEX4),
.oSEG5(HEX5),
.oSEG6(HEX6),
.oSEG7(HEX7),
.iDIG(DPDT_SW) );
// Audio CODEC and video decoder setting
I2C_AV_Config u1 ( // Host Side
.iCLK(OSC_50),
.iRST_N(KEY[0]),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
// TV Decoder Stable Check
TD_Detect u2 ( .oTD_Stable(TD_Stable),
.iTD_VS(TD_VS),
.iTD_HS(TD_HS),
.iRST_N(KEY[0]) );
// Reset Delay Timer
Reset_Delay u3 ( .iCLK(OSC_50),
// .iRST(TD_Stable),
.iRST(KEY[1]),
.oRST_0(DLY0),
.oRST_1(DLY1),
.oRST_2(DLY2));
// ITU-R 656 to YUV 4:2:2
ITU_656_Decoder u4 ( // TV Decoder Input
.iTD_DATA(TD_DATA),
// Position Output
.oTV_X(TV_X),
// YUV 4:2:2 Output
.oYCbCr(YCbCr),
.oDVAL(TV_DVAL),
// Control Signals
.iSwap_CbCr(Quotient[0]),
.iSkip(Remain==4'h0),
.iRST_N(DLY1),
.iCLK_27(TD_CLK) );
// For Down Sample 720 to 640
DIV u5 ( .aclr(!DLY0),
.clock(TD_CLK),
.denom(4'h9),
.numer(TV_X),
.quotient(Quotient),
.remain(Remain));
// SDRAM frame buffer
Sdram_Control_4Port u6 ( // HOST Side
.REF_CLK(OSC_27),
.CLK_18(AUD_CTRL_CLK),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA(YCbCr),
.WR1(TV_DVAL),
.WR1_FULL(WR1_FULL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*507), // 525-18
.WR1_LENGTH(9'h80),
.WR1_LOAD(!DLY0),
.WR1_CLK(TD_CLK),
// FIFO Read Side 1
.RD1_DATA(m1YCbCr),
.RD1(m1VGA_Read),
.RD1_ADDR(640*13), // Read odd field and bypess blanking
.RD1_MAX_ADDR(640*253),
.RD1_LENGTH(9'h80),
.RD1_LOAD(!DLY0),
.RD1_CLK(OSC_27),
// FIFO Read Side 2
.RD2_DATA(m2YCbCr),
.RD2(m2VGA_Read),
.RD2_ADDR(640*267), // Read even field and bypess blanking
.RD2_MAX_ADDR(640*507),
.RD2_LENGTH(9'h80),
.RD2_LOAD(!DLY0),
.RD2_CLK(OSC_27),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
// YUV 4:2:2 to YUV 4:4:4
YUV422_to_444 u7 ( // YUV 4:2:2 Input
.iYCbCr(mYCbCr),
// YUV 4:4:4 Output
.oY(mY),
.oCb(mCb),
.oCr(mCr),
// Control Signals
.iX(VGA_X),
.iCLK(OSC_27),
.iRST_N(DLY0));
// YCbCr 8-bit to RGB-10 bit
YCbCr2RGB u8 ( // Output Side
.Red(mRed),
.Green(mGreen),
.Blue(mBlue),
.oDVAL(mDVAL),
// Input Side
.iY(mY),
.iCb(mCb),
.iCr(mCr),
.iDVAL(VGA_Read),
// Control Signal
.iRESET(!DLY2),
.iCLK(OSC_27));
// VGA Controller
VGA_Ctrl u9 ( // Host Side
.iRed(mRed),
.iGreen(mGreen),
.iBlue(mBlue),
.oCurrent_X(VGA_X),
.oCurrent_Y(VGA_Y),
.oRequest(VGA_Read),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
.oVGA_CLOCK(VGA_CLK),
// Control Signal
.iCLK(OSC_27),
// .iCLK(halfre[0]),
.iRST_N(DLY2) );
// For ITU-R 656 Decoder
wire [15:0] YCbCr;
wire [9:0] TV_X;
wire TV_DVAL;
// For VGA Controller
wire [9:0] mRed;
wire [9:0] mGreen;
wire [9:0] mBlue;
wire [10:0] VGA_X;
wire [10:0] VGA_Y;
wire VGA_Read; // VGA data request
wire m1VGA_Read; // Read odd field
wire m2VGA_Read; // Read even field
// For YUV 4:2:2 to YUV 4:4:4
wire [7:0] mY;
wire [7:0] mCb;
wire [7:0] mCr;
// For field select
wire [15:0] mYCbCr;
wire [15:0] mYCbCr_d;
wire [15:0] m1YCbCr;
wire [15:0] m2YCbCr;
wire [15:0] m3YCbCr;
// For Delay Timer
wire TD_Stable;
wire DLY0;
wire DLY1;
wire DLY2;
// For Down Sample
wire [3:0] Remain;
wire [9:0] Quotient;
assign m1VGA_Read = VGA_Y[0] ? 1'b0 : VGA_Read ;
assign m2VGA_Read = VGA_Y[0] ? VGA_Read : 1'b0 ;
assign mYCbCr_d = !VGA_Y[0] ? m1YCbCr :
m2YCbCr ;
assign mYCbCr = m5YCbCr;
wire mDVAL;
// Line buffer, delay one line
Line_Buffer u10 ( .clken(VGA_Read),
.clock(OSC_27),
.shiftin(mYCbCr_d),
.shiftout(m3YCbCr));
Line_Buffer u11 ( .clken(VGA_Read),
.clock(OSC_27),
.shiftin(m3YCbCr),
.shiftout(m4YCbCr));
wire [15:0] m4YCbCr;
wire [15:0] m5YCbCr;
wire [8:0] Tmp1,Tmp2;
wire [7:0] Tmp3,Tmp4;
assign Tmp1 = m4YCbCr[7:0]+mYCbCr_d[7:0];
assign Tmp2 = m4YCbCr[15:8]+mYCbCr_d[15:8];
assign Tmp3 = Tmp1[8:2]+m3YCbCr[7:1];
assign Tmp4 = Tmp2[8:2]+m3YCbCr[15:9];
assign m5YCbCr = {Tmp4,Tmp3};
/*
AUDIO_DAC u12 ( // Audio Side
.oAUD_BCK(AUD_BCLK),
.oAUD_DATA(AUD_DACDAT),
.oAUD_LRCK(AUD_DACLRCK),
// Control Signals
.iSrc_Select(2'b01),
.iCLK_18_4(AUD_CTRL_CLK),
.iRST_N(DLY1) );
*/
reg [1:0] halfre;
always @(posedge OSC_50 or negedge KEY[0])
begin
if(!KEY[0])
begin
halfre<=2'b00;
end
halfre<=halfre+1'b1;
end
endmodule
|
// UC Berkeley CS251
// Spring 2018
// Arya Reais-Parsi ([email protected])
// emacs --batch riscv_top.v -f verilog-batch-auto
`include "const.vh"
module riscv_top
(
input clk,
input reset,
output mem_req_valid,
input mem_req_ready,
output mem_req_rw,
output [`MEM_ADDR_BITS-1:0] mem_req_addr,
output [`MEM_TAG_BITS-1:0] mem_req_tag,
output mem_req_data_valid,
input mem_req_data_ready,
output [`MEM_DATA_BITS-1:0] mem_req_data_bits,
output [(`MEM_DATA_BITS/8)-1:0] mem_req_data_mask,
input mem_resp_valid,
input [`MEM_TAG_BITS-1:0] mem_resp_tag,
input [`MEM_DATA_BITS-1:0] mem_resp_data,
output [31:0] csr
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] dcache_addr; // From cpu of Riscv141.v
wire [31:0] dcache_din; // From cpu of Riscv141.v
wire [31:0] dcache_dout; // From mem of Memory141.v
wire dcache_val;
wire dcache_re; // From cpu of Riscv141.v
wire [3:0] dcache_we; // From cpu of Riscv141.v
wire [31:0] icache_addr; // From cpu of Riscv141.v
wire [31:0] icache_dout; // From mem of Memory141.v
wire icache_re; // From cpu of Riscv141.v
wire stall; // From mem of Memory141.v
// End of automatics
Memory141 mem(
/*AUTOINST*/
// Outputs
.dcache_dout (dcache_dout[31:0]),
.dcache_val (dcache_val),
.icache_dout (icache_dout[31:0]),
.stall (stall),
.mem_req_valid (mem_req_valid),
.mem_req_rw (mem_req_rw),
.mem_req_addr (mem_req_addr[`MEM_ADDR_BITS-1:0]),
.mem_req_tag (mem_req_tag[`MEM_TAG_BITS-1:0]),
.mem_req_data_valid (mem_req_data_valid),
.mem_req_data_bits (mem_req_data_bits[`MEM_DATA_BITS-1:0]),
.mem_req_data_mask (mem_req_data_mask[(`MEM_DATA_BITS/8)-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.dcache_addr (dcache_addr[31:0]),
.icache_addr (icache_addr[31:0]),
.dcache_we (dcache_we[3:0]),
.dcache_re (dcache_re),
.icache_re (icache_re),
.dcache_din (dcache_din[31:0]),
.mem_req_ready (mem_req_ready),
.mem_req_data_ready (mem_req_data_ready),
.mem_resp_valid (mem_resp_valid),
.mem_resp_data (mem_resp_data[`MEM_DATA_BITS-1:0]),
.mem_resp_tag (mem_resp_tag[`MEM_TAG_BITS-1:0]));
// RISC-V 141 CPU
Riscv141 cpu(
/*AUTOINST*/
// Outputs
.dcache_addr (dcache_addr[31:0]),
.icache_addr (icache_addr[31:0]),
.dcache_we (dcache_we[3:0]),
.dcache_re (dcache_re),
.icache_re (icache_re),
.dcache_din (dcache_din[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.dcache_dout (dcache_dout[31:0]),
.dcache_val (dcache_val),
.icache_dout (icache_dout[31:0]),
.csr (csr),
.stall (stall));
endmodule
// Local Variables:
// verilog-library-extensions:(".v" ".vh")
// verilog-library-directories:(".")
// End:
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 12:52:18 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n167, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381, mult_x_19_n1319,
mult_x_19_n1318, mult_x_19_n1317, mult_x_19_n1316, mult_x_19_n1315,
mult_x_19_n1314, mult_x_19_n1313, mult_x_19_n1312, mult_x_19_n1311,
mult_x_19_n1310, mult_x_19_n1309, mult_x_19_n1308, mult_x_19_n1307,
mult_x_19_n1306, mult_x_19_n1305, mult_x_19_n1304, mult_x_19_n1303,
mult_x_19_n1295, mult_x_19_n1294, mult_x_19_n1293, mult_x_19_n1292,
mult_x_19_n1291, mult_x_19_n1290, mult_x_19_n1289, mult_x_19_n1288,
mult_x_19_n1287, mult_x_19_n1286, mult_x_19_n1285, mult_x_19_n1284,
mult_x_19_n1283, mult_x_19_n1282, mult_x_19_n1281, mult_x_19_n1280,
mult_x_19_n1279, mult_x_19_n1278, mult_x_19_n1277, mult_x_19_n1276,
mult_x_19_n1271, mult_x_19_n1270, mult_x_19_n1269, mult_x_19_n1268,
mult_x_19_n1267, mult_x_19_n1265, mult_x_19_n1264, mult_x_19_n1263,
mult_x_19_n1262, mult_x_19_n1261, mult_x_19_n1260, mult_x_19_n1259,
mult_x_19_n1258, mult_x_19_n1257, mult_x_19_n1256, mult_x_19_n1255,
mult_x_19_n1254, mult_x_19_n1253, mult_x_19_n1252, mult_x_19_n1251,
mult_x_19_n1250, mult_x_19_n1249, mult_x_19_n1241, mult_x_19_n1240,
mult_x_19_n1239, mult_x_19_n1238, mult_x_19_n1237, mult_x_19_n1236,
mult_x_19_n1235, mult_x_19_n1234, mult_x_19_n1233, mult_x_19_n1232,
mult_x_19_n1231, mult_x_19_n1230, mult_x_19_n1229, mult_x_19_n1228,
mult_x_19_n1227, mult_x_19_n1226, mult_x_19_n1225, mult_x_19_n1224,
mult_x_19_n1223, mult_x_19_n1222, mult_x_19_n1217, mult_x_19_n1216,
mult_x_19_n1215, mult_x_19_n1214, mult_x_19_n1213, mult_x_19_n1211,
mult_x_19_n1210, mult_x_19_n1209, mult_x_19_n1208, mult_x_19_n1207,
mult_x_19_n1206, mult_x_19_n1205, mult_x_19_n1204, mult_x_19_n1203,
mult_x_19_n1202, mult_x_19_n1201, mult_x_19_n1200, mult_x_19_n1199,
mult_x_19_n1198, mult_x_19_n1197, mult_x_19_n1196, mult_x_19_n1195,
mult_x_19_n1187, mult_x_19_n1186, mult_x_19_n1185, mult_x_19_n1184,
mult_x_19_n1183, mult_x_19_n1182, mult_x_19_n1181, mult_x_19_n1180,
mult_x_19_n1179, mult_x_19_n1178, mult_x_19_n1177, mult_x_19_n1176,
mult_x_19_n1175, mult_x_19_n1174, mult_x_19_n1173, mult_x_19_n1172,
mult_x_19_n1171, mult_x_19_n1170, mult_x_19_n1169, mult_x_19_n1163,
mult_x_19_n1162, mult_x_19_n1161, mult_x_19_n1160, mult_x_19_n1159,
mult_x_19_n1158, mult_x_19_n1157, mult_x_19_n1156, mult_x_19_n1155,
mult_x_19_n1154, mult_x_19_n1153, mult_x_19_n1152, mult_x_19_n1151,
mult_x_19_n1150, mult_x_19_n1149, mult_x_19_n1148, mult_x_19_n1147,
mult_x_19_n1146, mult_x_19_n1145, mult_x_19_n1144, mult_x_19_n1143,
mult_x_19_n1142, mult_x_19_n1141, mult_x_19_n862, mult_x_19_n859,
mult_x_19_n857, mult_x_19_n856, mult_x_19_n855, mult_x_19_n854,
mult_x_19_n852, mult_x_19_n851, mult_x_19_n850, mult_x_19_n849,
mult_x_19_n847, mult_x_19_n846, mult_x_19_n845, mult_x_19_n842,
mult_x_19_n840, mult_x_19_n839, mult_x_19_n838, mult_x_19_n835,
mult_x_19_n834, mult_x_19_n833, mult_x_19_n832, mult_x_19_n831,
mult_x_19_n829, mult_x_19_n828, mult_x_19_n827, mult_x_19_n826,
mult_x_19_n825, mult_x_19_n824, mult_x_19_n823, mult_x_19_n821,
mult_x_19_n820, mult_x_19_n819, mult_x_19_n818, mult_x_19_n817,
mult_x_19_n816, mult_x_19_n815, mult_x_19_n813, mult_x_19_n812,
mult_x_19_n811, mult_x_19_n810, mult_x_19_n809, mult_x_19_n808,
mult_x_19_n807, mult_x_19_n805, mult_x_19_n804, mult_x_19_n803,
mult_x_19_n802, mult_x_19_n801, mult_x_19_n800, mult_x_19_n797,
mult_x_19_n795, mult_x_19_n794, mult_x_19_n793, mult_x_19_n792,
mult_x_19_n791, mult_x_19_n790, mult_x_19_n787, mult_x_19_n786,
mult_x_19_n785, mult_x_19_n784, mult_x_19_n783, mult_x_19_n782,
mult_x_19_n781, mult_x_19_n780, mult_x_19_n778, mult_x_19_n777,
mult_x_19_n776, mult_x_19_n775, mult_x_19_n774, mult_x_19_n773,
mult_x_19_n772, mult_x_19_n771, mult_x_19_n770, mult_x_19_n769,
mult_x_19_n767, mult_x_19_n766, mult_x_19_n765, mult_x_19_n764,
mult_x_19_n763, mult_x_19_n762, mult_x_19_n761, mult_x_19_n760,
mult_x_19_n759, mult_x_19_n758, mult_x_19_n756, mult_x_19_n755,
mult_x_19_n754, mult_x_19_n753, mult_x_19_n752, mult_x_19_n751,
mult_x_19_n750, mult_x_19_n749, mult_x_19_n748, mult_x_19_n747,
mult_x_19_n745, mult_x_19_n744, mult_x_19_n743, mult_x_19_n742,
mult_x_19_n741, mult_x_19_n740, mult_x_19_n739, mult_x_19_n738,
mult_x_19_n737, mult_x_19_n736, mult_x_19_n734, mult_x_19_n733,
mult_x_19_n732, mult_x_19_n731, mult_x_19_n730, mult_x_19_n729,
mult_x_19_n728, mult_x_19_n727, mult_x_19_n726, mult_x_19_n725,
mult_x_19_n724, mult_x_19_n723, mult_x_19_n722, mult_x_19_n721,
mult_x_19_n720, mult_x_19_n719, mult_x_19_n718, mult_x_19_n717,
mult_x_19_n716, mult_x_19_n715, mult_x_19_n714, mult_x_19_n713,
mult_x_19_n712, mult_x_19_n711, mult_x_19_n710, mult_x_19_n709,
mult_x_19_n708, mult_x_19_n707, mult_x_19_n706, mult_x_19_n705,
mult_x_19_n704, mult_x_19_n703, mult_x_19_n702, mult_x_19_n701,
mult_x_19_n700, mult_x_19_n699, mult_x_19_n698, mult_x_19_n697,
mult_x_19_n696, mult_x_19_n695, mult_x_19_n694, mult_x_19_n693,
mult_x_19_n692, mult_x_19_n691, mult_x_19_n690, mult_x_19_n689,
mult_x_19_n688, mult_x_19_n687, mult_x_19_n686, mult_x_19_n685,
mult_x_19_n684, mult_x_19_n683, mult_x_19_n682, mult_x_19_n681,
mult_x_19_n680, mult_x_19_n679, mult_x_19_n678, mult_x_19_n677,
mult_x_19_n676, mult_x_19_n675, mult_x_19_n674, mult_x_19_n673,
mult_x_19_n672, mult_x_19_n671, mult_x_19_n669, mult_x_19_n668,
mult_x_19_n667, mult_x_19_n666, mult_x_19_n665, mult_x_19_n664,
mult_x_19_n663, mult_x_19_n662, mult_x_19_n661, mult_x_19_n659,
mult_x_19_n658, mult_x_19_n657, mult_x_19_n656, mult_x_19_n655,
mult_x_19_n654, mult_x_19_n653, mult_x_19_n652, mult_x_19_n651,
mult_x_19_n650, mult_x_19_n649, mult_x_19_n648, mult_x_19_n647,
mult_x_19_n646, mult_x_19_n645, mult_x_19_n644, mult_x_19_n643,
mult_x_19_n642, mult_x_19_n640, mult_x_19_n638, mult_x_19_n637,
mult_x_19_n636, mult_x_19_n635, mult_x_19_n634, mult_x_19_n633,
mult_x_19_n631, mult_x_19_n630, mult_x_19_n629, mult_x_19_n628,
mult_x_19_n627, mult_x_19_n626, mult_x_19_n625, mult_x_19_n624,
mult_x_19_n623, mult_x_19_n622, mult_x_19_n621, mult_x_19_n620,
mult_x_19_n619, mult_x_19_n618, mult_x_19_n617, mult_x_19_n616,
mult_x_19_n614, mult_x_19_n613, mult_x_19_n612, mult_x_19_n611,
mult_x_19_n610, mult_x_19_n609, mult_x_19_n607, mult_x_19_n606,
mult_x_19_n605, mult_x_19_n604, mult_x_19_n603, mult_x_19_n602,
mult_x_19_n601, mult_x_19_n600, mult_x_19_n599, mult_x_19_n598,
mult_x_19_n597, mult_x_19_n596, mult_x_19_n594, mult_x_19_n593,
mult_x_19_n592, mult_x_19_n591, mult_x_19_n590, mult_x_19_n588,
mult_x_19_n587, mult_x_19_n586, mult_x_19_n585, mult_x_19_n584,
mult_x_19_n583, mult_x_19_n582, mult_x_19_n581, mult_x_19_n580,
mult_x_19_n579, mult_x_19_n577, mult_x_19_n576, mult_x_19_n575,
mult_x_19_n573, mult_x_19_n572, mult_x_19_n571, mult_x_19_n570,
mult_x_19_n569, mult_x_19_n568, DP_OP_32J1_122_6543_n22,
DP_OP_32J1_122_6543_n21, DP_OP_32J1_122_6543_n20,
DP_OP_32J1_122_6543_n19, DP_OP_32J1_122_6543_n18,
DP_OP_32J1_122_6543_n17, DP_OP_32J1_122_6543_n16,
DP_OP_32J1_122_6543_n15, DP_OP_32J1_122_6543_n9,
DP_OP_32J1_122_6543_n8, DP_OP_32J1_122_6543_n7,
DP_OP_32J1_122_6543_n6, DP_OP_32J1_122_6543_n5,
DP_OP_32J1_122_6543_n4, DP_OP_32J1_122_6543_n3,
DP_OP_32J1_122_6543_n2, DP_OP_32J1_122_6543_n1, n392, n393, n394,
n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405,
n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416,
n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438,
n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460,
n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504,
n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515,
n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526,
n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537,
n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, n548,
n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559,
n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, n570,
n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592,
n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614,
n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636,
n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658,
n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768,
n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779,
n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790,
n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801,
n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812,
n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834,
n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845,
n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n2053), .Q(Op_MY[31]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n2053), .Q(zero_flag), .QN(n2051) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(clk), .RN(n2072), .Q(
FS_Module_state_reg[0]), .QN(n2038) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n2054), .Q(Op_MX[21]), .QN(n394) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n2054), .Q(Op_MX[20]), .QN(n479) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n2054), .Q(Op_MX[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n2054), .Q(Op_MX[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n2054), .Q(Op_MX[17]), .QN(n486) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n2054), .Q(Op_MX[16]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n2054), .Q(Op_MX[15]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n2055), .Q(Op_MX[14]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n2055), .Q(Op_MX[13]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n2055), .Q(Op_MX[12]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n2055), .Q(Op_MX[11]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n2055), .Q(Op_MX[9]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n2055), .Q(Op_MX[7]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n2055), .Q(Op_MX[6]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n2055), .Q(Op_MX[5]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n2056), .Q(Op_MX[4]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n2056), .Q(Op_MX[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n2056), .Q(Op_MX[2]), .QN(n485) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n2056), .Q(Op_MX[1]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n2056), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n2058),
.Q(Add_result[0]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n2060), .Q(Op_MY[21]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n2060), .Q(Op_MY[20]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n2060), .Q(Op_MY[18]), .QN(n397) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n2060), .Q(Op_MY[17]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n2060), .Q(Op_MY[15]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n2060), .Q(Op_MY[14]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n2060), .Q(Op_MY[13]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n2060), .Q(Op_MY[12]), .QN(n400) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n2061), .Q(Op_MY[11]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n2061), .Q(Op_MY[10]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n2061), .Q(Op_MY[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n2061), .Q(Op_MY[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n2061), .Q(Op_MY[7]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n2061), .Q(Op_MY[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n2061), .Q(Op_MY[5]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n2061), .Q(Op_MY[4]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n2061), .Q(Op_MY[3]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n2061), .Q(Op_MY[2]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n2062), .Q(Op_MY[1]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n2062), .Q(Op_MY[0]), .QN(n482) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_36_ ( .D(n274), .CK(clk), .RN(n2073),
.QN(n418) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_31_ ( .D(n269), .CK(clk), .RN(n2073),
.QN(n419) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_30_ ( .D(n268), .CK(clk), .RN(n2073),
.QN(n420) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_29_ ( .D(n267), .CK(clk), .RN(n2073),
.QN(n421) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_28_ ( .D(n266), .CK(clk), .RN(n2073),
.QN(n422) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_23_ ( .D(n261), .CK(clk), .RN(n2072),
.Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_22_ ( .D(n260), .CK(clk), .RN(n2071),
.Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_1_ ( .D(n239), .CK(clk), .RN(n2071),
.Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(n2071),
.Q(P_Sgf[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(clk),
.RN(n1644), .Q(Sgf_normalized_result[23]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_38_ ( .D(n276), .CK(clk), .RN(n2074),
.QN(n423) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_37_ ( .D(n275), .CK(clk), .RN(n2073),
.QN(n415) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_39_ ( .D(n277), .CK(clk), .RN(n2074),
.QN(n414) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_44_ ( .D(n282), .CK(clk), .RN(n2074),
.QN(n412) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_47_ ( .D(n237), .CK(clk), .RN(n2072),
.Q(P_Sgf[47]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_43_ ( .D(n281), .CK(clk), .RN(n2074),
.QN(n425) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_40_ ( .D(n278), .CK(clk), .RN(n2074),
.QN(n417) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_46_ ( .D(n284), .CK(clk), .RN(n2074),
.Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_42_ ( .D(n280), .CK(clk), .RN(n2074),
.QN(n413) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_45_ ( .D(n283), .CK(clk), .RN(n2074),
.QN(n424) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_41_ ( .D(n279), .CK(clk), .RN(n2074),
.QN(n416) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[7]), .QN(n2050) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(clk),
.RN(n2064), .Q(Sgf_normalized_result[10]), .QN(n2049) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[6]), .QN(n2047) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[4]), .QN(n2046) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[5]), .QN(n2042) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(clk),
.RN(n2063), .Q(Sgf_normalized_result[9]), .QN(n2041) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[3]), .QN(n2040) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n2053), .Q(FSM_selector_A),
.QN(n2048) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[8]), .QN(n2037) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(clk), .RN(n2062), .Q(
FSM_selector_B[0]), .QN(n2036) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[1]), .QN(n2043) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n2066), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n2066), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n2066), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n2066), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n2066), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n2066), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n2066), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n2066), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n2066), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n2066), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n2067), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n2067), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n2067), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n2067), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n2067), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n2067), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n2067), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n2067), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n2067), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n2067), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n2068), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n2068), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n2068), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n2068), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n2068), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n2068), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n2068), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n2068), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n2068), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n2068), .Q(final_result_ieee[29]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n2062), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n2064),
.Q(exp_oper_result[8]) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n2062), .Q(
FSM_selector_B[1]), .QN(n2039) );
CMPR42X2TS mult_x_19_U662 ( .A(mult_x_19_n1276), .B(mult_x_19_n699), .C(
mult_x_19_n696), .D(mult_x_19_n1252), .ICI(mult_x_19_n1228), .S(
mult_x_19_n687), .ICO(mult_x_19_n685), .CO(mult_x_19_n686) );
CMPR42X2TS mult_x_19_U727 ( .A(mult_x_19_n859), .B(mult_x_19_n1271), .C(
mult_x_19_n862), .D(mult_x_19_n1295), .ICI(mult_x_19_n1319), .S(
mult_x_19_n857), .ICO(mult_x_19_n855), .CO(mult_x_19_n856) );
CMPR42X2TS mult_x_19_U725 ( .A(mult_x_19_n854), .B(mult_x_19_n1270), .C(
mult_x_19_n855), .D(mult_x_19_n1318), .ICI(mult_x_19_n1294), .S(
mult_x_19_n852), .ICO(mult_x_19_n850), .CO(mult_x_19_n851) );
CMPR42X2TS mult_x_19_U723 ( .A(mult_x_19_n849), .B(mult_x_19_n1293), .C(
mult_x_19_n1269), .D(mult_x_19_n850), .ICI(mult_x_19_n1317), .S(
mult_x_19_n847), .ICO(mult_x_19_n845), .CO(mult_x_19_n846) );
CMPR42X2TS mult_x_19_U720 ( .A(mult_x_19_n842), .B(mult_x_19_n1268), .C(
mult_x_19_n1292), .D(mult_x_19_n1316), .ICI(mult_x_19_n845), .S(
mult_x_19_n840), .ICO(mult_x_19_n838), .CO(mult_x_19_n839) );
CMPR42X2TS mult_x_19_U717 ( .A(mult_x_19_n1291), .B(mult_x_19_n1267), .C(
mult_x_19_n835), .D(mult_x_19_n838), .ICI(mult_x_19_n1315), .S(
mult_x_19_n833), .ICO(mult_x_19_n831), .CO(mult_x_19_n832) );
CMPR42X2TS mult_x_19_U714 ( .A(mult_x_19_n1314), .B(mult_x_19_n834), .C(
mult_x_19_n828), .D(mult_x_19_n1290), .ICI(mult_x_19_n831), .S(
mult_x_19_n826), .ICO(mult_x_19_n824), .CO(mult_x_19_n825) );
CMPR42X2TS mult_x_19_U712 ( .A(mult_x_19_n823), .B(mult_x_19_n1217), .C(
mult_x_19_n829), .D(mult_x_19_n1241), .ICI(mult_x_19_n1289), .S(
mult_x_19_n821), .ICO(mult_x_19_n819), .CO(mult_x_19_n820) );
CMPR42X2TS mult_x_19_U711 ( .A(mult_x_19_n1265), .B(mult_x_19_n827), .C(
mult_x_19_n1313), .D(mult_x_19_n824), .ICI(mult_x_19_n821), .S(
mult_x_19_n818), .ICO(mult_x_19_n816), .CO(mult_x_19_n817) );
CMPR42X2TS mult_x_19_U709 ( .A(mult_x_19_n815), .B(mult_x_19_n1216), .C(
mult_x_19_n819), .D(mult_x_19_n1264), .ICI(mult_x_19_n1312), .S(
mult_x_19_n813), .ICO(mult_x_19_n811), .CO(mult_x_19_n812) );
CMPR42X2TS mult_x_19_U708 ( .A(mult_x_19_n1240), .B(mult_x_19_n1288), .C(
mult_x_19_n820), .D(mult_x_19_n816), .ICI(mult_x_19_n813), .S(
mult_x_19_n810), .ICO(mult_x_19_n808), .CO(mult_x_19_n809) );
CMPR42X2TS mult_x_19_U705 ( .A(mult_x_19_n1263), .B(mult_x_19_n1311), .C(
mult_x_19_n812), .D(mult_x_19_n808), .ICI(mult_x_19_n805), .S(
mult_x_19_n802), .ICO(mult_x_19_n800), .CO(mult_x_19_n801) );
CMPR42X2TS mult_x_19_U701 ( .A(mult_x_19_n803), .B(mult_x_19_n1310), .C(
mult_x_19_n804), .D(mult_x_19_n795), .ICI(mult_x_19_n800), .S(
mult_x_19_n792), .ICO(mult_x_19_n790), .CO(mult_x_19_n791) );
CMPR42X2TS mult_x_19_U698 ( .A(mult_x_19_n1237), .B(mult_x_19_n1213), .C(
mult_x_19_n1285), .D(mult_x_19_n787), .ICI(mult_x_19_n1261), .S(
mult_x_19_n785), .ICO(mult_x_19_n783), .CO(mult_x_19_n784) );
CMPR42X2TS mult_x_19_U697 ( .A(mult_x_19_n793), .B(mult_x_19_n1309), .C(
mult_x_19_n794), .D(mult_x_19_n785), .ICI(mult_x_19_n790), .S(
mult_x_19_n782), .ICO(mult_x_19_n780), .CO(mult_x_19_n781) );
CMPR42X2TS mult_x_19_U694 ( .A(mult_x_19_n1260), .B(mult_x_19_n786), .C(
mult_x_19_n1308), .D(mult_x_19_n777), .ICI(mult_x_19_n1284), .S(
mult_x_19_n775), .ICO(mult_x_19_n773), .CO(mult_x_19_n774) );
CMPR42X2TS mult_x_19_U693 ( .A(mult_x_19_n783), .B(mult_x_19_n1236), .C(
mult_x_19_n784), .D(mult_x_19_n775), .ICI(mult_x_19_n780), .S(
mult_x_19_n772), .ICO(mult_x_19_n770), .CO(mult_x_19_n771) );
CMPR42X2TS mult_x_19_U691 ( .A(mult_x_19_n769), .B(mult_x_19_n1163), .C(
mult_x_19_n778), .D(mult_x_19_n1187), .ICI(mult_x_19_n1211), .S(
mult_x_19_n767), .ICO(mult_x_19_n765), .CO(mult_x_19_n766) );
CMPR42X2TS mult_x_19_U690 ( .A(mult_x_19_n1235), .B(mult_x_19_n776), .C(
mult_x_19_n1283), .D(mult_x_19_n1259), .ICI(mult_x_19_n773), .S(
mult_x_19_n764), .ICO(mult_x_19_n762), .CO(mult_x_19_n763) );
CMPR42X2TS mult_x_19_U689 ( .A(mult_x_19_n1307), .B(mult_x_19_n767), .C(
mult_x_19_n774), .D(mult_x_19_n764), .ICI(mult_x_19_n770), .S(
mult_x_19_n761), .ICO(mult_x_19_n759), .CO(mult_x_19_n760) );
CMPR42X1TS mult_x_19_U687 ( .A(mult_x_19_n758), .B(mult_x_19_n1162), .C(
mult_x_19_n765), .D(mult_x_19_n1210), .ICI(mult_x_19_n1258), .S(
mult_x_19_n756), .ICO(mult_x_19_n754), .CO(mult_x_19_n755) );
CMPR42X2TS mult_x_19_U686 ( .A(mult_x_19_n1186), .B(mult_x_19_n1234), .C(
mult_x_19_n766), .D(mult_x_19_n762), .ICI(mult_x_19_n1306), .S(
mult_x_19_n753), .ICO(mult_x_19_n751), .CO(mult_x_19_n752) );
CMPR42X2TS mult_x_19_U685 ( .A(mult_x_19_n1282), .B(mult_x_19_n756), .C(
mult_x_19_n763), .D(mult_x_19_n759), .ICI(mult_x_19_n753), .S(
mult_x_19_n750), .ICO(mult_x_19_n748), .CO(mult_x_19_n749) );
CMPR42X1TS mult_x_19_U683 ( .A(mult_x_19_n747), .B(mult_x_19_n1185), .C(
mult_x_19_n1161), .D(mult_x_19_n1233), .ICI(mult_x_19_n754), .S(
mult_x_19_n745), .ICO(mult_x_19_n743), .CO(mult_x_19_n744) );
CMPR42X2TS mult_x_19_U679 ( .A(mult_x_19_n736), .B(mult_x_19_n1160), .C(
mult_x_19_n1184), .D(mult_x_19_n1208), .ICI(mult_x_19_n1304), .S(
mult_x_19_n734), .ICO(mult_x_19_n732), .CO(mult_x_19_n733) );
CMPR42X2TS mult_x_19_U677 ( .A(mult_x_19_n740), .B(mult_x_19_n744), .C(
mult_x_19_n741), .D(mult_x_19_n731), .ICI(mult_x_19_n737), .S(
mult_x_19_n728), .ICO(mult_x_19_n726), .CO(mult_x_19_n727) );
CMPR42X2TS mult_x_19_U675 ( .A(mult_x_19_n725), .B(mult_x_19_n1183), .C(
mult_x_19_n1159), .D(mult_x_19_n1231), .ICI(mult_x_19_n1207), .S(
mult_x_19_n723), .ICO(mult_x_19_n721), .CO(mult_x_19_n722) );
CMPR42X2TS mult_x_19_U673 ( .A(mult_x_19_n729), .B(mult_x_19_n723), .C(
mult_x_19_n730), .D(mult_x_19_n720), .ICI(mult_x_19_n726), .S(
mult_x_19_n717), .ICO(mult_x_19_n715), .CO(mult_x_19_n716) );
CMPR42X2TS mult_x_19_U670 ( .A(mult_x_19_n1254), .B(mult_x_19_n1182), .C(
mult_x_19_n1278), .D(mult_x_19_n1230), .ICI(mult_x_19_n722), .S(
mult_x_19_n709), .ICO(mult_x_19_n707), .CO(mult_x_19_n708) );
CMPR42X2TS mult_x_19_U667 ( .A(mult_x_19_n713), .B(mult_x_19_n703), .C(
mult_x_19_n1181), .D(mult_x_19_n1157), .ICI(mult_x_19_n1205), .S(
mult_x_19_n701), .ICO(mult_x_19_n699), .CO(mult_x_19_n700) );
CMPR42X2TS mult_x_19_U666 ( .A(mult_x_19_n1277), .B(mult_x_19_n1229), .C(
mult_x_19_n710), .D(mult_x_19_n1253), .ICI(mult_x_19_n707), .S(
mult_x_19_n698), .ICO(mult_x_19_n696), .CO(mult_x_19_n697) );
CMPR42X2TS mult_x_19_U665 ( .A(mult_x_19_n711), .B(mult_x_19_n701), .C(
mult_x_19_n708), .D(mult_x_19_n698), .ICI(mult_x_19_n704), .S(
mult_x_19_n695), .ICO(mult_x_19_n693), .CO(mult_x_19_n694) );
CMPR42X2TS mult_x_19_U663 ( .A(mult_x_19_n702), .B(mult_x_19_n1156), .C(
mult_x_19_n1204), .D(mult_x_19_n692), .ICI(mult_x_19_n1180), .S(
mult_x_19_n690), .ICO(mult_x_19_n688), .CO(mult_x_19_n689) );
CMPR42X2TS mult_x_19_U661 ( .A(mult_x_19_n700), .B(mult_x_19_n690), .C(
mult_x_19_n697), .D(mult_x_19_n687), .ICI(mult_x_19_n693), .S(
mult_x_19_n684), .ICO(mult_x_19_n682), .CO(mult_x_19_n683) );
CMPR42X2TS mult_x_19_U658 ( .A(mult_x_19_n688), .B(mult_x_19_n1155), .C(
mult_x_19_n1251), .D(mult_x_19_n1203), .ICI(mult_x_19_n685), .S(
mult_x_19_n676), .ICO(mult_x_19_n674), .CO(mult_x_19_n675) );
CMPR42X2TS mult_x_19_U654 ( .A(mult_x_19_n1202), .B(mult_x_19_n677), .C(
mult_x_19_n1178), .D(mult_x_19_n1226), .ICI(mult_x_19_n669), .S(
mult_x_19_n666), .ICO(mult_x_19_n664), .CO(mult_x_19_n665) );
CMPR42X2TS mult_x_19_U650 ( .A(mult_x_19_n1249), .B(mult_x_19_n1153), .C(
mult_x_19_n668), .D(mult_x_19_n1225), .ICI(mult_x_19_n659), .S(
mult_x_19_n656), .ICO(mult_x_19_n654), .CO(mult_x_19_n655) );
CMPR42X2TS mult_x_19_U649 ( .A(mult_x_19_n1201), .B(mult_x_19_n664), .C(
mult_x_19_n665), .D(mult_x_19_n656), .ICI(mult_x_19_n661), .S(
mult_x_19_n653), .ICO(mult_x_19_n651), .CO(mult_x_19_n652) );
CMPR42X2TS mult_x_19_U647 ( .A(n2032), .B(mult_x_19_n1200), .C(
mult_x_19_n1176), .D(mult_x_19_n1224), .ICI(mult_x_19_n658), .S(
mult_x_19_n647), .ICO(mult_x_19_n645), .CO(mult_x_19_n646) );
CMPR42X2TS mult_x_19_U642 ( .A(mult_x_19_n649), .B(mult_x_19_n645), .C(
mult_x_19_n646), .D(mult_x_19_n638), .ICI(mult_x_19_n642), .S(
mult_x_19_n635), .ICO(mult_x_19_n633), .CO(mult_x_19_n634) );
CMPR42X2TS mult_x_19_U639 ( .A(mult_x_19_n1150), .B(n2034), .C(
mult_x_19_n1222), .D(mult_x_19_n631), .ICI(mult_x_19_n636), .S(
mult_x_19_n629), .ICO(mult_x_19_n627), .CO(mult_x_19_n628) );
CMPR42X2TS mult_x_19_U638 ( .A(mult_x_19_n1198), .B(mult_x_19_n1174), .C(
mult_x_19_n637), .D(mult_x_19_n629), .ICI(mult_x_19_n633), .S(
mult_x_19_n626), .ICO(mult_x_19_n624), .CO(mult_x_19_n625) );
CMPR42X2TS mult_x_19_U635 ( .A(mult_x_19_n1149), .B(mult_x_19_n627), .C(
mult_x_19_n628), .D(mult_x_19_n621), .ICI(mult_x_19_n624), .S(
mult_x_19_n618), .ICO(mult_x_19_n616), .CO(mult_x_19_n617) );
CMPR42X2TS mult_x_19_U632 ( .A(mult_x_19_n619), .B(mult_x_19_n1172), .C(
mult_x_19_n614), .D(mult_x_19_n620), .ICI(mult_x_19_n616), .S(
mult_x_19_n611), .ICO(mult_x_19_n609), .CO(mult_x_19_n610) );
CMPR42X1TS mult_x_19_U630 ( .A(n2025), .B(n2023), .C(n471), .D(
mult_x_19_n1195), .ICI(mult_x_19_n612), .S(mult_x_19_n607), .ICO(
mult_x_19_n605), .CO(mult_x_19_n606) );
CMPR42X2TS mult_x_19_U629 ( .A(mult_x_19_n1171), .B(mult_x_19_n1147), .C(
mult_x_19_n613), .D(mult_x_19_n607), .ICI(mult_x_19_n609), .S(
mult_x_19_n604), .ICO(mult_x_19_n602), .CO(mult_x_19_n603) );
CMPR42X2TS mult_x_19_U621 ( .A(mult_x_19_n593), .B(n462), .C(mult_x_19_n588),
.D(mult_x_19_n1144), .ICI(mult_x_19_n590), .S(mult_x_19_n586), .ICO(
mult_x_19_n584), .CO(mult_x_19_n585) );
CMPR42X1TS mult_x_19_U619 ( .A(mult_x_19_n583), .B(n470), .C(mult_x_19_n1143), .D(mult_x_19_n587), .ICI(mult_x_19_n584), .S(mult_x_19_n581), .ICO(
mult_x_19_n579), .CO(mult_x_19_n580) );
CMPR42X1TS mult_x_19_U615 ( .A(n2020), .B(n397), .C(mult_x_19_n1141), .D(
n468), .ICI(mult_x_19_n575), .S(mult_x_19_n573), .ICO(mult_x_19_n571),
.CO(mult_x_19_n572) );
CMPR32X2TS DP_OP_32J1_122_6543_U10 ( .A(S_Oper_A_exp[0]), .B(n2017), .C(
DP_OP_32J1_122_6543_n22), .CO(DP_OP_32J1_122_6543_n9), .S(
Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_32J1_122_6543_U8 ( .A(DP_OP_32J1_122_6543_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_32J1_122_6543_n8), .CO(
DP_OP_32J1_122_6543_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_32J1_122_6543_U6 ( .A(DP_OP_32J1_122_6543_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_32J1_122_6543_n6), .CO(
DP_OP_32J1_122_6543_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_32J1_122_6543_U5 ( .A(DP_OP_32J1_122_6543_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_32J1_122_6543_n5), .CO(
DP_OP_32J1_122_6543_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_32J1_122_6543_U4 ( .A(DP_OP_32J1_122_6543_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_32J1_122_6543_n4), .CO(
DP_OP_32J1_122_6543_n3), .S(Exp_module_Data_S[6]) );
CMPR42X2TS mult_x_19_U628 ( .A(n2018), .B(n2024), .C(n2022), .D(
mult_x_19_n605), .ICI(n474), .S(mult_x_19_n601), .ICO(mult_x_19_n599),
.CO(mult_x_19_n600) );
CMPR42X2TS mult_x_19_U669 ( .A(mult_x_19_n712), .B(mult_x_19_n718), .C(
mult_x_19_n709), .D(mult_x_19_n719), .ICI(mult_x_19_n715), .S(
mult_x_19_n706), .ICO(mult_x_19_n704), .CO(mult_x_19_n705) );
CMPR42X2TS mult_x_19_U633 ( .A(n400), .B(mult_x_19_n622), .C(mult_x_19_n1196), .D(n472), .ICI(mult_x_19_n1148), .S(mult_x_19_n614), .ICO(mult_x_19_n612),
.CO(mult_x_19_n613) );
CMPR42X2TS mult_x_19_U681 ( .A(mult_x_19_n755), .B(mult_x_19_n751), .C(
mult_x_19_n752), .D(mult_x_19_n742), .ICI(mult_x_19_n748), .S(
mult_x_19_n739), .ICO(mult_x_19_n737), .CO(mult_x_19_n738) );
CMPR42X2TS mult_x_19_U655 ( .A(n2029), .B(mult_x_19_n680), .C(n2031), .D(
mult_x_19_n1154), .ICI(mult_x_19_n1250), .S(mult_x_19_n669), .ICO(
mult_x_19_n667), .CO(mult_x_19_n668) );
CMPR42X2TS mult_x_19_U651 ( .A(n2030), .B(n2027), .C(n2033), .D(
mult_x_19_n1177), .ICI(mult_x_19_n667), .S(mult_x_19_n659), .ICO(
mult_x_19_n657), .CO(mult_x_19_n658) );
CMPR42X2TS mult_x_19_U657 ( .A(mult_x_19_n679), .B(mult_x_19_n689), .C(
mult_x_19_n676), .D(mult_x_19_n686), .ICI(mult_x_19_n682), .S(
mult_x_19_n673), .ICO(mult_x_19_n671), .CO(mult_x_19_n672) );
CMPR42X2TS mult_x_19_U636 ( .A(mult_x_19_n623), .B(n473), .C(mult_x_19_n630),
.D(mult_x_19_n1173), .ICI(mult_x_19_n1197), .S(mult_x_19_n621), .ICO(
mult_x_19_n619), .CO(mult_x_19_n620) );
CMPR42X2TS mult_x_19_U646 ( .A(mult_x_19_n650), .B(mult_x_19_n654), .C(
mult_x_19_n647), .D(mult_x_19_n655), .ICI(mult_x_19_n651), .S(
mult_x_19_n644), .ICO(mult_x_19_n642), .CO(mult_x_19_n643) );
CMPR42X2TS mult_x_19_U653 ( .A(mult_x_19_n674), .B(mult_x_19_n678), .C(
mult_x_19_n675), .D(mult_x_19_n666), .ICI(mult_x_19_n671), .S(
mult_x_19_n663), .ICO(mult_x_19_n661), .CO(mult_x_19_n662) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n2069), .Q(final_result_ieee[30]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n2054), .Q(Op_MX[22]), .QN(n484) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(clk), .RN(n2065),
.Q(underflow_flag) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(clk),
.RN(n2064), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(clk),
.RN(n2063), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(clk),
.RN(n2064), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(clk),
.RN(n2063), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(clk),
.RN(n2063), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(clk),
.RN(n1644), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(clk),
.RN(n2064), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(clk),
.RN(n1643), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(clk),
.RN(n1643), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(clk),
.RN(n1643), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n2064), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(clk),
.RN(n2063), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n2053), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n2053), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n2059), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n2054), .Q(Op_MX[24]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n1644),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n2064),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n2062),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n2062),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n2062),
.Q(exp_oper_result[0]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n2059), .Q(Op_MY[27]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n2059), .Q(Op_MY[23]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(n2071),
.Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_17_ ( .D(n255), .CK(clk), .RN(n2070),
.Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_20_ ( .D(n258), .CK(clk), .RN(n2070),
.Q(P_Sgf[20]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n2059), .Q(FSM_add_overflow_flag) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n2065), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_35_ ( .D(n273), .CK(clk), .RN(n2073),
.Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_34_ ( .D(n272), .CK(clk), .RN(n2073),
.Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_33_ ( .D(n271), .CK(clk), .RN(n2073),
.Q(P_Sgf[33]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n2053), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n2053), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n2053), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n2053), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n2054), .Q(Op_MX[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n2056),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n2056),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n2056),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n2056),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n2057),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n2057),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n2057),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n2057),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n2057),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n2057),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n2057),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n2057),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n2057),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n2057),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n2058),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n2058),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n2058),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n2058),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n2058),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n2058),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n2058),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n2058),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n2058),
.Q(Add_result[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n2062),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n2062),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n2063),
.Q(exp_oper_result[6]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n2059), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n2059), .Q(Op_MY[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n2059), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n2059), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n2059), .Q(Op_MY[24]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_32_ ( .D(n270), .CK(clk), .RN(n2073),
.Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_27_ ( .D(n265), .CK(clk), .RN(n2072),
.Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_26_ ( .D(n264), .CK(clk), .RN(n2072),
.Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_25_ ( .D(n263), .CK(clk), .RN(n2072),
.Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_24_ ( .D(n262), .CK(clk), .RN(n2072),
.Q(P_Sgf[24]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n2074), .Q(
FS_Module_state_reg[3]), .QN(n2044) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(n2072),
.Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_19_ ( .D(n257), .CK(clk), .RN(n2070),
.Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_16_ ( .D(n254), .CK(clk), .RN(n2070),
.Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(n2072),
.Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_21_ ( .D(n259), .CK(clk), .RN(n2070),
.Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_15_ ( .D(n253), .CK(clk), .RN(n2070),
.Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(n2072),
.Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_18_ ( .D(n256), .CK(clk), .RN(n2070),
.Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_14_ ( .D(n252), .CK(clk), .RN(n2070),
.Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(n2071),
.Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(n2071),
.Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_13_ ( .D(n251), .CK(clk), .RN(n2070),
.Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(n2071),
.Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_12_ ( .D(n250), .CK(clk), .RN(n2070),
.Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(n2071),
.Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_11_ ( .D(n249), .CK(clk), .RN(n2071),
.Q(P_Sgf[11]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(n2071),
.Q(P_Sgf[7]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[2]), .QN(n2035) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n2055), .Q(Op_MX[10]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n2059), .Q(Op_MY[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n2069), .Q(final_result_ieee[31]), .QN(n2052) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n1643), .Q(FSM_selector_C),
.QN(n2045) );
ADDFHX2TS DP_OP_32J1_122_6543_U2 ( .A(n2017), .B(S_Oper_A_exp[8]), .CI(
DP_OP_32J1_122_6543_n2), .CO(DP_OP_32J1_122_6543_n1), .S(
Exp_module_Data_S[8]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n2055), .Q(Op_MX[8]), .QN(n396) );
ADDFHX2TS DP_OP_32J1_122_6543_U9 ( .A(DP_OP_32J1_122_6543_n21), .B(
S_Oper_A_exp[1]), .CI(DP_OP_32J1_122_6543_n9), .CO(
DP_OP_32J1_122_6543_n8), .S(Exp_module_Data_S[1]) );
ADDFHX2TS DP_OP_32J1_122_6543_U7 ( .A(DP_OP_32J1_122_6543_n19), .B(
S_Oper_A_exp[3]), .CI(DP_OP_32J1_122_6543_n7), .CO(
DP_OP_32J1_122_6543_n6), .S(Exp_module_Data_S[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n2056), .Q(Op_MX[0]), .QN(n393) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n2060), .Q(Op_MY[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n2060), .Q(Op_MY[19]) );
CMPR32X2TS DP_OP_32J1_122_6543_U3 ( .A(DP_OP_32J1_122_6543_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_32J1_122_6543_n3), .CO(
DP_OP_32J1_122_6543_n2), .S(Exp_module_Data_S[7]) );
AO21X1TS U406 ( .A0(underflow_flag), .A1(n2006), .B0(n1978), .Y(n201) );
MX2X2TS U407 ( .A(n1613), .B(n448), .S0(n1917), .Y(n274) );
INVX2TS U408 ( .A(n2011), .Y(n2010) );
INVX2TS U409 ( .A(n2016), .Y(n2009) );
CLKXOR2X2TS U410 ( .A(n1637), .B(n1636), .Y(n1639) );
XNOR2X2TS U411 ( .A(n1608), .B(n1607), .Y(n1609) );
BUFX3TS U412 ( .A(n1868), .Y(n1917) );
BUFX3TS U413 ( .A(n1868), .Y(n1974) );
BUFX3TS U414 ( .A(n1868), .Y(n1638) );
BUFX3TS U415 ( .A(n2011), .Y(n2015) );
OAI21X2TS U416 ( .A0(n426), .A1(n837), .B0(n836), .Y(n840) );
NOR2X1TS U417 ( .A(n1540), .B(n1552), .Y(n1543) );
INVX2TS U418 ( .A(n1939), .Y(n1954) );
NAND2X1TS U419 ( .A(n801), .B(n1579), .Y(n803) );
OAI21X1TS U420 ( .A0(n1541), .A1(n1552), .B0(n1553), .Y(n1542) );
OR3X1TS U421 ( .A(underflow_flag), .B(overflow_flag), .C(n2012), .Y(n2011)
);
INVX2TS U422 ( .A(n432), .Y(n434) );
NOR2X1TS U423 ( .A(n1633), .B(n1566), .Y(n1590) );
NOR2X2TS U424 ( .A(n2038), .B(FS_Module_state_reg[1]), .Y(n1688) );
BUFX3TS U425 ( .A(n1868), .Y(n1972) );
INVX2TS U426 ( .A(n2016), .Y(n2012) );
NOR2X2TS U427 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n1684) );
INVX2TS U428 ( .A(n1661), .Y(n1774) );
INVX2TS U429 ( .A(n717), .Y(n799) );
NAND2X2TS U430 ( .A(n812), .B(n779), .Y(n1624) );
CLKBUFX2TS U431 ( .A(n2014), .Y(n2016) );
NOR2X4TS U432 ( .A(n690), .B(n1657), .Y(n1868) );
OAI21X1TS U433 ( .A0(n765), .A1(n770), .B0(n771), .Y(n752) );
NOR2X1TS U434 ( .A(n1655), .B(n2043), .Y(n1661) );
NOR2X1TS U435 ( .A(n1656), .B(n2043), .Y(n690) );
AND2X2TS U436 ( .A(n1692), .B(n1672), .Y(n2014) );
NOR2X1TS U437 ( .A(n2043), .B(FS_Module_state_reg[2]), .Y(n1692) );
NOR2XLTS U438 ( .A(n2044), .B(n2038), .Y(n1672) );
NOR2X4TS U439 ( .A(n693), .B(n819), .Y(n779) );
NOR2XLTS U440 ( .A(n1690), .B(n1665), .Y(n1655) );
NAND2X1TS U441 ( .A(mult_x_19_n597), .B(mult_x_19_n592), .Y(n820) );
INVX2TS U442 ( .A(n1611), .Y(n678) );
NOR2X4TS U443 ( .A(n1552), .B(n1544), .Y(n661) );
NOR2X4TS U444 ( .A(n1560), .B(n1558), .Y(n1551) );
OAI21X2TS U445 ( .A0(n1553), .A1(n1544), .B0(n1545), .Y(n660) );
NOR2X2TS U446 ( .A(n1887), .B(n1888), .Y(n659) );
NAND2X2TS U447 ( .A(n1619), .B(n784), .Y(n681) );
NOR2X4TS U448 ( .A(mult_x_19_n706), .B(mult_x_19_n716), .Y(n1544) );
NAND2X1TS U449 ( .A(FS_Module_state_reg[2]), .B(n2044), .Y(n1675) );
NOR2X4TS U450 ( .A(mult_x_19_n635), .B(mult_x_19_n643), .Y(n718) );
NOR2X6TS U451 ( .A(mult_x_19_n717), .B(mult_x_19_n727), .Y(n1552) );
NAND2X2TS U452 ( .A(mult_x_19_n728), .B(mult_x_19_n738), .Y(n1561) );
NOR2X2TS U453 ( .A(mult_x_19_n611), .B(mult_x_19_n617), .Y(n826) );
INVX2TS U454 ( .A(n1566), .Y(n1574) );
NAND2X4TS U455 ( .A(n795), .B(n805), .Y(n669) );
NAND2X2TS U456 ( .A(mult_x_19_n750), .B(mult_x_19_n760), .Y(n1889) );
NAND2X1TS U457 ( .A(n1690), .B(FSM_add_overflow_flag), .Y(n1656) );
XOR2X1TS U458 ( .A(n898), .B(Op_MX[20]), .Y(mult_x_19_n1145) );
OR2X4TS U459 ( .A(mult_x_19_n618), .B(mult_x_19_n625), .Y(n805) );
INVX2TS U460 ( .A(n1965), .Y(n656) );
INVX2TS U461 ( .A(n723), .Y(n794) );
INVX2TS U462 ( .A(n1963), .Y(n1959) );
NOR2X2TS U463 ( .A(n1666), .B(FS_Module_state_reg[0]), .Y(n1690) );
NAND2X1TS U464 ( .A(n2035), .B(FS_Module_state_reg[3]), .Y(n1666) );
NAND2X2TS U465 ( .A(mult_x_19_n634), .B(mult_x_19_n626), .Y(n723) );
OR2X2TS U466 ( .A(mult_x_19_n833), .B(mult_x_19_n839), .Y(n488) );
NAND2X2TS U467 ( .A(mult_x_19_n826), .B(mult_x_19_n832), .Y(n1921) );
NOR2BX2TS U468 ( .AN(n1657), .B(FS_Module_state_reg[1]), .Y(n1680) );
OAI21X1TS U469 ( .A0(n404), .A1(n1051), .B0(n1035), .Y(n1036) );
OAI21X1TS U470 ( .A0(n1211), .A1(n905), .B0(n870), .Y(n871) );
OA21XLTS U471 ( .A0(n1383), .A1(n1382), .B0(n1381), .Y(n2034) );
XOR2X1TS U472 ( .A(n1028), .B(n1694), .Y(mult_x_19_n1222) );
OAI21X1TS U473 ( .A0(n404), .A1(n1354), .B0(n1353), .Y(n1356) );
CMPR32X2TS U474 ( .A(n1505), .B(mult_x_19_n648), .C(n1504), .CO(n1234), .S(
mult_x_19_n640) );
NAND2X1TS U475 ( .A(mult_x_19_n857), .B(n641), .Y(n1876) );
OA21XLTS U476 ( .A0(n1291), .A1(n1382), .B0(n1290), .Y(n471) );
XOR2X1TS U477 ( .A(n1118), .B(n1117), .Y(mult_x_19_n1285) );
CLKXOR2X2TS U478 ( .A(n1017), .B(n1319), .Y(mult_x_19_n1204) );
CLKXOR2X2TS U479 ( .A(n1407), .B(n1459), .Y(n1416) );
XOR2X1TS U480 ( .A(n1087), .B(n1695), .Y(mult_x_19_n1276) );
OAI21X1TS U481 ( .A0(n1318), .A1(n1288), .B0(n1287), .Y(n1289) );
OAI21X1TS U482 ( .A0(n1501), .A1(n1288), .B0(n1079), .Y(n1080) );
OAI21X1TS U483 ( .A0(n405), .A1(n1474), .B0(n1042), .Y(n1043) );
ADDFX2TS U484 ( .A(n1445), .B(n1444), .CI(n1443), .CO(mult_x_19_n827), .S(
mult_x_19_n828) );
XOR2X2TS U485 ( .A(n1059), .B(n1694), .Y(mult_x_19_n1239) );
XOR2X2TS U486 ( .A(n1082), .B(n431), .Y(mult_x_19_n1260) );
OAI21X1TS U487 ( .A0(n1196), .A1(n1330), .B0(n517), .Y(n858) );
OA21XLTS U488 ( .A0(n1376), .A1(n1500), .B0(n1375), .Y(n395) );
CLKXOR2X2TS U489 ( .A(n1366), .B(n429), .Y(mult_x_19_n1163) );
OAI21X1TS U490 ( .A0(n1312), .A1(n1207), .B0(n1206), .Y(n1208) );
INVX6TS U491 ( .A(n949), .Y(n1376) );
NOR2X1TS U492 ( .A(n561), .B(n560), .Y(n1844) );
INVX6TS U493 ( .A(n895), .Y(n1308) );
AOI222X1TS U494 ( .A0(n1454), .A1(n1493), .B0(n1396), .B1(n1379), .C0(n1242),
.C1(n1280), .Y(n1243) );
INVX6TS U495 ( .A(n866), .Y(n1342) );
INVX6TS U496 ( .A(n924), .Y(n1291) );
AOI21X2TS U497 ( .A0(n1128), .A1(n1127), .B0(n1126), .Y(n1133) );
BUFX12TS U498 ( .A(n747), .Y(n1211) );
OR2X2TS U499 ( .A(n553), .B(n552), .Y(n1839) );
XOR2X2TS U500 ( .A(n532), .B(n1413), .Y(n849) );
INVX2TS U501 ( .A(n1195), .Y(n436) );
INVX3TS U502 ( .A(n889), .Y(n894) );
INVX3TS U503 ( .A(n923), .Y(n911) );
XOR2X2TS U504 ( .A(n625), .B(n431), .Y(n1446) );
BUFX6TS U505 ( .A(n917), .Y(n1396) );
NAND2X1TS U506 ( .A(n990), .B(n988), .Y(n706) );
BUFX3TS U507 ( .A(n1051), .Y(n1484) );
OAI21X2TS U508 ( .A0(n957), .A1(n928), .B0(n930), .Y(n987) );
OAI21X2TS U509 ( .A0(n482), .A1(n1399), .B0(n510), .Y(n511) );
XOR2X2TS U510 ( .A(n600), .B(Op_MX[8]), .Y(n620) );
OAI21X1TS U511 ( .A0(n1467), .A1(n1427), .B0(n1424), .Y(n1425) );
AOI22X2TS U512 ( .A0(n1269), .A1(n1528), .B0(n1452), .B1(n1464), .Y(n508) );
XOR2X1TS U513 ( .A(n550), .B(n1392), .Y(n553) );
BUFX6TS U514 ( .A(n917), .Y(n1452) );
BUFX4TS U515 ( .A(n1217), .Y(n1410) );
BUFX6TS U516 ( .A(n536), .Y(n1330) );
INVX4TS U517 ( .A(mult_x_19_n769), .Y(n1529) );
OAI21X2TS U518 ( .A0(n1467), .A1(n1474), .B0(n1466), .Y(n1468) );
NAND2XLTS U519 ( .A(n1397), .B(Op_MY[0]), .Y(n510) );
XOR2X2TS U520 ( .A(n1449), .B(n1485), .Y(n1469) );
INVX6TS U521 ( .A(n844), .Y(n1517) );
NAND2X1TS U522 ( .A(n1217), .B(Op_MY[0]), .Y(n535) );
CLKINVX6TS U523 ( .A(n1195), .Y(n435) );
BUFX6TS U524 ( .A(n1217), .Y(n1265) );
INVX8TS U525 ( .A(n1048), .Y(n1479) );
INVX8TS U526 ( .A(n730), .Y(n957) );
INVX4TS U527 ( .A(n1177), .Y(n1182) );
CLKBUFX2TS U528 ( .A(n519), .Y(n1184) );
BUFX4TS U529 ( .A(n1070), .Y(n1258) );
INVX4TS U530 ( .A(n480), .Y(n1373) );
BUFX8TS U531 ( .A(n1051), .Y(n1474) );
BUFX4TS U532 ( .A(n1512), .Y(n1382) );
BUFX6TS U533 ( .A(n1482), .Y(n1463) );
OR2X2TS U534 ( .A(n1209), .B(n1326), .Y(n883) );
NOR2X4TS U535 ( .A(n393), .B(n542), .Y(n1388) );
NAND2X2TS U536 ( .A(n1336), .B(n1300), .Y(n913) );
NAND2X2TS U537 ( .A(n2021), .B(n2020), .Y(n1105) );
NAND2X2TS U538 ( .A(n406), .B(n527), .Y(n529) );
BUFX8TS U539 ( .A(n1274), .Y(n1347) );
BUFX4TS U540 ( .A(Op_MY[17]), .Y(n1300) );
BUFX4TS U541 ( .A(Op_MX[14]), .Y(n1992) );
INVX6TS U542 ( .A(n397), .Y(n2021) );
NAND2X4TS U543 ( .A(n932), .B(n732), .Y(n734) );
BUFX4TS U544 ( .A(Op_MY[20]), .Y(n2019) );
INVX8TS U545 ( .A(n896), .Y(n1326) );
BUFX6TS U546 ( .A(Op_MY[22]), .Y(n1209) );
NAND2X2TS U547 ( .A(n959), .B(n955), .Y(n705) );
CLKINVX6TS U548 ( .A(Op_MY[21]), .Y(n896) );
CLKINVX2TS U549 ( .A(n528), .Y(n492) );
CLKINVX6TS U550 ( .A(Op_MX[17]), .Y(n519) );
NOR2X4TS U551 ( .A(n728), .B(n991), .Y(n932) );
NAND2X2TS U552 ( .A(n2026), .B(n1686), .Y(n959) );
NAND2X2TS U553 ( .A(n1377), .B(n2025), .Y(n988) );
NAND2X2TS U554 ( .A(n1516), .B(n1438), .Y(n522) );
INVX8TS U555 ( .A(Op_MX[14]), .Y(n2018) );
NOR2X2TS U556 ( .A(n1377), .B(n2025), .Y(n728) );
NAND2X2TS U557 ( .A(n1438), .B(n1357), .Y(n562) );
BUFX8TS U558 ( .A(Op_MY[5]), .Y(n1283) );
BUFX8TS U559 ( .A(Op_MY[10]), .Y(n1384) );
BUFX8TS U560 ( .A(Op_MY[11]), .Y(n1377) );
INVX8TS U561 ( .A(Op_MX[5]), .Y(n1284) );
INVX8TS U562 ( .A(n1505), .Y(n1686) );
BUFX16TS U563 ( .A(Op_MY[2]), .Y(n1516) );
BUFX8TS U564 ( .A(Op_MY[14]), .Y(n2022) );
INVX8TS U565 ( .A(Op_MY[6]), .Y(n2029) );
INVX8TS U566 ( .A(Op_MY[15]), .Y(n925) );
CLKINVX6TS U567 ( .A(Op_MY[13]), .Y(n2023) );
NAND2X2TS U568 ( .A(n581), .B(n494), .Y(n496) );
INVX2TS U569 ( .A(n1129), .Y(n1131) );
INVX6TS U570 ( .A(n517), .Y(n1408) );
NAND2X2TS U571 ( .A(n1357), .B(n1283), .Y(n566) );
CLKINVX3TS U572 ( .A(n517), .Y(n1263) );
AOI21X2TS U573 ( .A0(n1103), .A1(n1102), .B0(n1101), .Y(n1108) );
OAI21XLTS U574 ( .A0(n1261), .A1(n1412), .B0(n1169), .Y(n1170) );
XOR2X2TS U575 ( .A(n588), .B(Op_MX[8]), .Y(n601) );
CLKINVX6TS U576 ( .A(n747), .Y(n1196) );
XOR2X1TS U577 ( .A(n1095), .B(n1117), .Y(mult_x_19_n1279) );
NOR2XLTS U578 ( .A(n1698), .B(n1789), .Y(n1699) );
INVX2TS U579 ( .A(n432), .Y(n433) );
INVX2TS U580 ( .A(n777), .Y(n816) );
NOR2X2TS U581 ( .A(mult_x_19_n749), .B(mult_x_19_n739), .Y(n1558) );
NAND2X2TS U582 ( .A(mult_x_19_n643), .B(mult_x_19_n635), .Y(n793) );
CLKBUFX2TS U583 ( .A(n1884), .Y(n1885) );
NAND2X1TS U584 ( .A(n1661), .B(n1704), .Y(n1659) );
OR2X2TS U585 ( .A(mult_x_19_n577), .B(mult_x_19_n580), .Y(n784) );
NOR3XLTS U586 ( .A(Op_MX[1]), .B(Op_MX[2]), .C(Op_MX[24]), .Y(n1998) );
OAI21XLTS U587 ( .A0(n1932), .A1(n1931), .B0(n1930), .Y(n1937) );
BUFX3TS U588 ( .A(n1680), .Y(n2017) );
INVX2TS U589 ( .A(n1754), .Y(n1748) );
NOR4X1TS U590 ( .A(Exp_module_Data_S[8]), .B(Exp_module_Data_S[7]), .C(n1977), .D(n2006), .Y(n1978) );
INVX2TS U591 ( .A(n2006), .Y(n1671) );
INVX2TS U592 ( .A(n2011), .Y(n2008) );
OR2X2TS U593 ( .A(n1676), .B(n1666), .Y(n1754) );
CLKMX2X2TS U594 ( .A(n1589), .B(P_Sgf[32]), .S0(n1972), .Y(n270) );
CLKMX2X2TS U595 ( .A(n1602), .B(n446), .S0(n1972), .Y(n268) );
OAI21XLTS U596 ( .A0(n1754), .A1(Sgf_normalized_result[0]), .B0(n1668), .Y(
n309) );
CLKXOR2X4TS U597 ( .A(n962), .B(n961), .Y(n392) );
INVX2TS U598 ( .A(n1970), .Y(n1696) );
CLKINVX3TS U599 ( .A(n1979), .Y(n1970) );
NAND2X4TS U600 ( .A(n1688), .B(n1684), .Y(n1979) );
CLKMX2X2TS U601 ( .A(n1968), .B(P_Sgf[21]), .S0(n1638), .Y(n259) );
CLKMX2X2TS U602 ( .A(n1893), .B(P_Sgf[22]), .S0(n1638), .Y(n260) );
NOR2X4TS U603 ( .A(n681), .B(n1626), .Y(n683) );
AND2X2TS U604 ( .A(n1619), .B(n1618), .Y(n1620) );
INVX2TS U605 ( .A(n749), .Y(n833) );
CLKMX2X2TS U606 ( .A(n1853), .B(P_Sgf[5]), .S0(n1974), .Y(n243) );
AND2X2TS U607 ( .A(n1535), .B(n1534), .Y(n1536) );
CLKMX2X2TS U608 ( .A(n1849), .B(P_Sgf[4]), .S0(n1917), .Y(n242) );
OR2X2TS U609 ( .A(n758), .B(n896), .Y(n760) );
CLKMX2X2TS U610 ( .A(n1843), .B(P_Sgf[3]), .S0(n1638), .Y(n241) );
OAI21X1TS U611 ( .A0(n1318), .A1(n1474), .B0(n1294), .Y(n1295) );
OAI21X1TS U612 ( .A0(n398), .A1(n1207), .B0(n1006), .Y(n1007) );
OAI21X1TS U613 ( .A0(n404), .A1(n1207), .B0(n1008), .Y(n1009) );
OAI21X1TS U614 ( .A0(n404), .A1(n1143), .B0(n1149), .Y(n1151) );
OAI21X1TS U615 ( .A0(n1196), .A1(n1143), .B0(n480), .Y(n1188) );
OAI21X1TS U616 ( .A0(n1391), .A1(n1390), .B0(n1389), .Y(n1393) );
OAI21X1TS U617 ( .A0(n1391), .A1(n1274), .B0(n1123), .Y(n1124) );
OAI21X1TS U618 ( .A0(n1196), .A1(n1354), .B0(n1195), .Y(n1197) );
CLKMX2X2TS U619 ( .A(Add_result[16]), .B(n1738), .S0(n1748), .Y(n293) );
OAI21X1TS U620 ( .A0(n1196), .A1(n1051), .B0(n1048), .Y(n1028) );
OAI21X1TS U621 ( .A0(n1196), .A1(n1362), .B0(n1122), .Y(n1087) );
INVX6TS U622 ( .A(n1233), .Y(n1391) );
OAI21X1TS U623 ( .A0(n1261), .A1(n1362), .B0(n1141), .Y(n1142) );
CLKMX2X2TS U624 ( .A(n1838), .B(P_Sgf[2]), .S0(n1974), .Y(n240) );
CLKMX2X2TS U625 ( .A(n1883), .B(P_Sgf[1]), .S0(n1631), .Y(n239) );
CLKMX2X2TS U626 ( .A(Add_result[13]), .B(n1755), .S0(n1806), .Y(n296) );
XOR2X1TS U627 ( .A(n556), .B(n1392), .Y(n561) );
CLKMX2X2TS U628 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n438), .Y(n345) );
CLKMX2X2TS U629 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n438), .Y(n334) );
CLKMX2X2TS U630 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n438), .Y(n326) );
CLKMX2X2TS U631 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n438), .Y(n319) );
CLKMX2X2TS U632 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n438), .Y(n325) );
CLKMX2X2TS U633 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n438), .Y(n318) );
CLKMX2X2TS U634 ( .A(Add_result[10]), .B(n1773), .S0(n1834), .Y(n299) );
CLKINVX2TS U635 ( .A(n1880), .Y(n1882) );
CLKMX2X2TS U636 ( .A(Add_result[9]), .B(n1779), .S0(n1806), .Y(n300) );
CLKMX2X2TS U637 ( .A(Add_result[12]), .B(n1760), .S0(n1834), .Y(n297) );
CLKMX2X2TS U638 ( .A(Add_result[7]), .B(n1791), .S0(n1834), .Y(n302) );
CLKMX2X2TS U639 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n438), .Y(n330) );
CLKMX2X2TS U640 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n438), .Y(n332) );
INVX4TS U641 ( .A(n1970), .Y(n438) );
CLKMX2X2TS U642 ( .A(Add_result[6]), .B(n1796), .S0(n1806), .Y(n303) );
CLKMX2X2TS U643 ( .A(Add_result[11]), .B(n1765), .S0(n1806), .Y(n298) );
CLKMX2X2TS U644 ( .A(Add_result[8]), .B(n1784), .S0(n1806), .Y(n301) );
OAI21X1TS U645 ( .A0(FS_Module_state_reg[1]), .A1(n1675), .B0(n1642), .Y(
n377) );
AO21X1TS U646 ( .A0(n1225), .A1(n1324), .B0(n1265), .Y(n973) );
INVX4TS U647 ( .A(n1182), .Y(n1314) );
CLKMX2X2TS U648 ( .A(Add_result[1]), .B(n1822), .S0(n1806), .Y(n308) );
CLKMX2X2TS U649 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n1971), .Y(n352) );
CLKMX2X2TS U650 ( .A(Add_result[3]), .B(n1813), .S0(n1806), .Y(n306) );
INVX4TS U651 ( .A(n1122), .Y(n1119) );
CLKMX2X2TS U652 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n1971), .Y(n353) );
CLKMX2X2TS U653 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n1971), .Y(n356) );
CLKMX2X2TS U654 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n1693), .Y(n357) );
CLKMX2X2TS U655 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n1969), .Y(n340) );
CLKMX2X2TS U656 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n437), .Y(n365) );
CLKMX2X2TS U657 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n438), .Y(n336) );
CLKMX2X2TS U658 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n1969), .Y(n359) );
CLKMX2X2TS U659 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n1693), .Y(n363) );
BUFX12TS U660 ( .A(n1420), .Y(n1426) );
CLKMX2X2TS U661 ( .A(Data_MX[17]), .B(n1685), .S0(n1693), .Y(n361) );
CLKMX2X2TS U662 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n1969), .Y(n322) );
CLKMX2X2TS U663 ( .A(Data_MY[9]), .B(n1686), .S0(n1969), .Y(n321) );
CLKMX2X2TS U664 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n1979), .Y(n371) );
CLKMX2X2TS U665 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n1969), .Y(n347) );
CLKMX2X2TS U666 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n1971), .Y(n323) );
CLKMX2X2TS U667 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n1971), .Y(n348) );
CLKMX2X2TS U668 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n1969), .Y(n342) );
CLKMX2X2TS U669 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n1693), .Y(n317) );
CLKMX2X2TS U670 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n1969), .Y(n316) );
CLKMX2X2TS U671 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n1693), .Y(n339) );
CLKMX2X2TS U672 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n1979), .Y(n313) );
CLKMX2X2TS U673 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n1693), .Y(n372) );
CLKMX2X2TS U674 ( .A(Data_MX[2]), .B(n1150), .S0(n1693), .Y(n346) );
CLKMX2X2TS U675 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n1969), .Y(n312) );
OAI21X1TS U676 ( .A0(n2035), .A1(n1681), .B0(FS_Module_state_reg[3]), .Y(
n1682) );
CLKMX2X2TS U677 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n1971), .Y(n351) );
CLKMX2X2TS U678 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n1971), .Y(n350) );
CLKMX2X2TS U679 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n1969), .Y(n374) );
AO21X1TS U680 ( .A0(n1433), .A1(n1324), .B0(n1352), .Y(n1067) );
OAI211XLTS U681 ( .A0(n1669), .A1(n2036), .B0(n1754), .C0(n2006), .Y(n236)
);
AO21X1TS U682 ( .A0(n1386), .A1(n1324), .B0(n1498), .Y(n1146) );
INVX4TS U683 ( .A(n1970), .Y(n1693) );
CLKINVX2TS U684 ( .A(n1656), .Y(n1658) );
INVX4TS U685 ( .A(n1970), .Y(n1969) );
INVX4TS U686 ( .A(n1754), .Y(n1806) );
INVX4TS U687 ( .A(n1970), .Y(n1971) );
INVX3TS U688 ( .A(n1195), .Y(n1349) );
CLKINVX1TS U689 ( .A(n1690), .Y(n1654) );
INVX2TS U690 ( .A(n912), .Y(n914) );
INVX4TS U691 ( .A(n1184), .Y(n1413) );
BUFX12TS U692 ( .A(n1239), .Y(n1352) );
NOR2X4TS U693 ( .A(n2024), .B(n2022), .Y(n936) );
INVX3TS U694 ( .A(n2029), .Y(n1432) );
INVX4TS U695 ( .A(n2023), .Y(n1493) );
INVX3TS U696 ( .A(n2027), .Y(n1259) );
INVX4TS U697 ( .A(n2018), .Y(n1428) );
NOR2X4TS U698 ( .A(n2021), .B(n2020), .Y(n1104) );
INVX4TS U699 ( .A(n1505), .Y(n1198) );
INVX4TS U700 ( .A(n397), .Y(n1340) );
CLKMX2X2TS U701 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
BUFX12TS U702 ( .A(Op_MY[4]), .Y(n1357) );
CLKMX2X2TS U703 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
BUFX12TS U704 ( .A(Op_MY[19]), .Y(n2020) );
CLKMX2X2TS U705 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
INVX4TS U706 ( .A(n485), .Y(n1392) );
BUFX3TS U707 ( .A(Op_MY[1]), .Y(n1510) );
MX2X2TS U708 ( .A(n1609), .B(n447), .S0(n1972), .Y(n269) );
CLKMX2X2TS U709 ( .A(n1639), .B(P_Sgf[27]), .S0(n1972), .Y(n265) );
CLKMX2X2TS U710 ( .A(n1961), .B(P_Sgf[20]), .S0(n1974), .Y(n258) );
CLKMX2X2TS U711 ( .A(n1832), .B(P_Sgf[23]), .S0(n1917), .Y(n261) );
CLKMX2X2TS U712 ( .A(n1951), .B(P_Sgf[18]), .S0(n1638), .Y(n256) );
CLKMX2X2TS U713 ( .A(n1958), .B(P_Sgf[19]), .S0(n1917), .Y(n257) );
CLKMX2X2TS U714 ( .A(n1938), .B(P_Sgf[16]), .S0(n1917), .Y(n254) );
CLKMX2X2TS U715 ( .A(n1942), .B(P_Sgf[17]), .S0(n1974), .Y(n255) );
OAI21X2TS U716 ( .A0(n799), .A1(n798), .B0(n797), .Y(n800) );
CLKMX2X2TS U717 ( .A(n1929), .B(P_Sgf[15]), .S0(n1638), .Y(n253) );
CLKMX2X2TS U718 ( .A(n1925), .B(P_Sgf[14]), .S0(n1974), .Y(n252) );
CLKMX2X2TS U719 ( .A(n1918), .B(P_Sgf[13]), .S0(n1917), .Y(n251) );
CLKMX2X2TS U720 ( .A(n1913), .B(P_Sgf[12]), .S0(n1638), .Y(n250) );
CLKMX2X2TS U721 ( .A(n1904), .B(P_Sgf[11]), .S0(n461), .Y(n249) );
NOR2X4TS U722 ( .A(n1597), .B(n1569), .Y(n666) );
CLKMX2X2TS U723 ( .A(n1900), .B(P_Sgf[10]), .S0(n1917), .Y(n248) );
CLKMX2X2TS U724 ( .A(n1878), .B(P_Sgf[9]), .S0(n1631), .Y(n247) );
AND2X2TS U725 ( .A(n1628), .B(n1627), .Y(n1629) );
AOI21X2TS U726 ( .A0(n780), .A1(n784), .B0(n679), .Y(n680) );
NAND2X2TS U727 ( .A(mult_x_19_n604), .B(mult_x_19_n610), .Y(n827) );
CLKMX2X2TS U728 ( .A(Add_result[23]), .B(n1702), .S0(n1748), .Y(n286) );
CLKMX2X2TS U729 ( .A(Add_result[22]), .B(n1707), .S0(n1748), .Y(n287) );
CLKMX2X2TS U730 ( .A(n1874), .B(P_Sgf[8]), .S0(n1974), .Y(n246) );
CLKMX2X2TS U731 ( .A(n1869), .B(P_Sgf[7]), .S0(n1917), .Y(n245) );
CLKMX2X2TS U732 ( .A(n1862), .B(P_Sgf[6]), .S0(n1638), .Y(n244) );
CLKMX2X2TS U733 ( .A(Add_result[21]), .B(n1712), .S0(n1748), .Y(n288) );
CLKMX2X2TS U734 ( .A(n1975), .B(Exp_module_Overflow_flag_A), .S0(n1917), .Y(
n225) );
CLKMX2X2TS U735 ( .A(Add_result[20]), .B(n1718), .S0(n1748), .Y(n289) );
OR2X2TS U736 ( .A(mult_x_19_n572), .B(mult_x_19_n570), .Y(n490) );
XOR2X1TS U737 ( .A(n1268), .B(n1267), .Y(mult_x_19_n1172) );
CLKMX2X2TS U738 ( .A(exp_oper_result[8]), .B(Exp_module_Data_S[8]), .S0(
n1973), .Y(n226) );
OR2X2TS U739 ( .A(mult_x_19_n857), .B(n641), .Y(n481) );
CLKMX2X2TS U740 ( .A(Add_result[19]), .B(n1723), .S0(n1748), .Y(n290) );
OAI21X1TS U741 ( .A0(n1308), .A1(n536), .B0(n1266), .Y(n1268) );
OAI21X1TS U742 ( .A0(n1856), .A1(n1855), .B0(n1854), .Y(n1861) );
CLKMX2X2TS U743 ( .A(exp_oper_result[7]), .B(Exp_module_Data_S[7]), .S0(
n1973), .Y(n227) );
CLKMX2X2TS U744 ( .A(Add_result[18]), .B(n1728), .S0(n1748), .Y(n291) );
OR2X2TS U745 ( .A(n636), .B(n635), .Y(n1871) );
CLKMX2X2TS U746 ( .A(Add_result[17]), .B(n1733), .S0(n1748), .Y(n292) );
CLKMX2X2TS U747 ( .A(exp_oper_result[6]), .B(Exp_module_Data_S[6]), .S0(
n1973), .Y(n228) );
NAND2X2TS U748 ( .A(n596), .B(n595), .Y(n1858) );
OAI21X1TS U749 ( .A0(n405), .A1(n1500), .B0(n1245), .Y(n1246) );
XOR2X1TS U750 ( .A(n1002), .B(n1319), .Y(mult_x_19_n1196) );
XOR2X1TS U751 ( .A(n1188), .B(Op_MX[2]), .Y(mult_x_19_n1303) );
OAI21X1TS U752 ( .A0(n1391), .A1(n1406), .B0(n1173), .Y(n1174) );
OAI21X1TS U753 ( .A0(n1383), .A1(n1500), .B0(n1189), .Y(n1190) );
OAI21X1TS U754 ( .A0(n392), .A1(n1274), .B0(n1139), .Y(n1140) );
OAI21X1TS U755 ( .A0(n403), .A1(n1436), .B0(n1199), .Y(n1200) );
OAI21X1TS U756 ( .A0(n1501), .A1(n1427), .B0(n1018), .Y(n1019) );
OAI21X1TS U757 ( .A0(n1211), .A1(n1143), .B0(n1144), .Y(n1145) );
OAI21X1TS U758 ( .A0(n1383), .A1(n1347), .B0(n1277), .Y(n1278) );
OAI21X1TS U759 ( .A0(n403), .A1(n1274), .B0(n1134), .Y(n1135) );
OAI21X1TS U760 ( .A0(n392), .A1(n1436), .B0(n1193), .Y(n1194) );
OAI21X1TS U761 ( .A0(n392), .A1(n1456), .B0(n963), .Y(n964) );
OAI21X1TS U762 ( .A0(n403), .A1(n1390), .B0(n1159), .Y(n1160) );
OAI21X1TS U763 ( .A0(n1383), .A1(n1330), .B0(n996), .Y(n997) );
OAI21X1TS U764 ( .A0(n1383), .A1(n1427), .B0(n1022), .Y(n1023) );
CLKMX2X2TS U765 ( .A(exp_oper_result[5]), .B(Exp_module_Data_S[5]), .S0(
n1973), .Y(n229) );
ADDFHX2TS U766 ( .A(n790), .B(n789), .CI(n788), .CO(n538), .S(mult_x_19_n797) );
OAI21X1TS U767 ( .A0(n392), .A1(n1406), .B0(n1175), .Y(n1176) );
OAI21X1TS U768 ( .A0(n1383), .A1(n1288), .B0(n1083), .Y(n1084) );
OAI21X1TS U769 ( .A0(n403), .A1(n1484), .B0(n1281), .Y(n1282) );
CLKMX2X2TS U770 ( .A(exp_oper_result[4]), .B(Exp_module_Data_S[4]), .S0(
n1973), .Y(n230) );
CLKMX2X2TS U771 ( .A(Add_result[15]), .B(n1743), .S0(n1834), .Y(n294) );
ADDHX2TS U772 ( .A(n1509), .B(n1508), .CO(n1487), .S(mult_x_19_n849) );
INVX6TS U773 ( .A(n500), .Y(n1371) );
ADDHX2TS U774 ( .A(n849), .B(n848), .CO(n788), .S(mult_x_19_n807) );
CLKMX2X2TS U775 ( .A(exp_oper_result[3]), .B(Exp_module_Data_S[3]), .S0(
n1973), .Y(n231) );
ADDHX2TS U776 ( .A(n847), .B(n846), .CO(n848), .S(mult_x_19_n815) );
ADDHX2TS U777 ( .A(n1507), .B(n1506), .CO(n1509), .S(mult_x_19_n854) );
CLKMX2X2TS U778 ( .A(Add_result[14]), .B(n1749), .S0(n1834), .Y(n295) );
OAI21X1TS U779 ( .A0(n1261), .A1(n1484), .B0(n1061), .Y(n1062) );
OAI21X1TS U780 ( .A0(n1261), .A1(n1436), .B0(n1260), .Y(n1262) );
OAI21X1TS U781 ( .A0(n1261), .A1(n1390), .B0(n615), .Y(n616) );
XNOR2X2TS U782 ( .A(n534), .B(n486), .Y(n847) );
CLKMX2X2TS U783 ( .A(exp_oper_result[2]), .B(Exp_module_Data_S[2]), .S0(
n1973), .Y(n232) );
CLKMX2X2TS U784 ( .A(exp_oper_result[0]), .B(Exp_module_Data_S[0]), .S0(
n1973), .Y(n234) );
OAI21X1TS U785 ( .A0(n1523), .A1(n1406), .B0(n1255), .Y(n1256) );
OAI21X1TS U786 ( .A0(n401), .A1(n1484), .B0(n1063), .Y(n1064) );
ADDHX2TS U787 ( .A(n620), .B(n619), .CO(n1447), .S(n634) );
CLKMX2X2TS U788 ( .A(exp_oper_result[1]), .B(Exp_module_Data_S[1]), .S0(
n1973), .Y(n233) );
OAI21X1TS U789 ( .A0(n401), .A1(n1436), .B0(n1240), .Y(n1241) );
OAI21X1TS U790 ( .A0(n1441), .A1(n1436), .B0(n1085), .Y(n1086) );
OAI21X2TS U791 ( .A0(n609), .A1(n608), .B0(n607), .Y(n614) );
OAI21X1TS U792 ( .A0(n1523), .A1(n1436), .B0(n1249), .Y(n1250) );
XOR2X2TS U793 ( .A(n551), .B(n1363), .Y(n559) );
OAI21X1TS U794 ( .A0(n1523), .A1(n1456), .B0(n969), .Y(n970) );
OAI21X2TS U795 ( .A0(n482), .A1(n1427), .B0(n466), .Y(n1429) );
XOR2X2TS U796 ( .A(n537), .B(n1413), .Y(n1321) );
AOI222X1TS U797 ( .A0(n1420), .A1(n1460), .B0(n1419), .B1(n1984), .C0(n1418),
.C1(n1510), .Y(n1213) );
CLKMX2X2TS U798 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n437), .Y(n338) );
CLKMX2X2TS U799 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n437), .Y(n370) );
OAI211X1TS U800 ( .A0(n1683), .A1(n2051), .B0(n1682), .C0(n1774), .Y(n380)
);
OR2X2TS U801 ( .A(FSM_selector_C), .B(n1659), .Y(n409) );
CLKMX2X2TS U802 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n437), .Y(n369) );
AO21X1TS U803 ( .A0(Sgf_normalized_result[23]), .A1(n1774), .B0(n1705), .Y(
n310) );
AO22X1TS U804 ( .A0(Sgf_normalized_result[4]), .A1(n2008), .B0(
final_result_ieee[4]), .B1(n2007), .Y(n196) );
AO22X1TS U805 ( .A0(Sgf_normalized_result[8]), .A1(n2008), .B0(
final_result_ieee[8]), .B1(n2007), .Y(n192) );
CLKMX2X2TS U806 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n437), .Y(n331) );
CLKMX2X2TS U807 ( .A(n1879), .B(P_Sgf[0]), .S0(n461), .Y(n238) );
CLKMX2X2TS U808 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n437), .Y(n344) );
AO22X1TS U809 ( .A0(Sgf_normalized_result[7]), .A1(n2008), .B0(
final_result_ieee[7]), .B1(n2007), .Y(n193) );
AO22X1TS U810 ( .A0(Sgf_normalized_result[6]), .A1(n2008), .B0(
final_result_ieee[6]), .B1(n2007), .Y(n194) );
CLKMX2X2TS U811 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n437), .Y(n329) );
CLKMX2X2TS U812 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n437), .Y(n335) );
AO22X1TS U813 ( .A0(Sgf_normalized_result[5]), .A1(n2008), .B0(
final_result_ieee[5]), .B1(n2007), .Y(n195) );
OAI21X2TS U814 ( .A0(n482), .A1(n536), .B0(n535), .Y(n537) );
OR2X2TS U815 ( .A(n1704), .B(FSM_selector_C), .Y(n1825) );
NOR2X4TS U816 ( .A(n1704), .B(n2045), .Y(n1713) );
BUFX4TS U817 ( .A(n1868), .Y(n1631) );
ADDHX2TS U818 ( .A(n429), .B(n521), .CO(n1394), .S(n790) );
INVX4TS U819 ( .A(n1970), .Y(n437) );
BUFX4TS U820 ( .A(n1868), .Y(n461) );
NAND2X4TS U821 ( .A(n860), .B(n738), .Y(n879) );
XOR2X2TS U822 ( .A(n511), .B(n429), .Y(n521) );
OAI21X1TS U823 ( .A0(n1467), .A1(n1500), .B0(n545), .Y(n546) );
OAI21X2TS U824 ( .A0(n1467), .A1(n1288), .B0(n599), .Y(n600) );
INVX4TS U825 ( .A(n512), .Y(n582) );
AO22X1TS U826 ( .A0(n1970), .A1(Data_MY[31]), .B0(n1979), .B1(Op_MY[31]),
.Y(n381) );
AOI222X1TS U827 ( .A0(n1369), .A1(n1368), .B0(n1386), .B1(n1367), .C0(n1373),
.C1(n1453), .Y(n1370) );
NAND2X2TS U828 ( .A(n1352), .B(n1470), .Y(n587) );
AO22X1TS U829 ( .A0(n1970), .A1(Data_MX[31]), .B0(n1979), .B1(Op_MX[31]),
.Y(n343) );
AOI222X1TS U830 ( .A0(n1388), .A1(n1481), .B0(n1496), .B1(n1985), .C0(n1373),
.C1(n1472), .Y(n555) );
AOI22X2TS U831 ( .A0(n1433), .A1(n1464), .B0(n1352), .B1(n1528), .Y(n599) );
NOR2X6TS U832 ( .A(n516), .B(n465), .Y(n1217) );
NAND3X1TS U833 ( .A(n1651), .B(n1650), .C(n1649), .Y(n1653) );
NOR2X1TS U834 ( .A(n1811), .B(Sgf_normalized_result[2]), .Y(n1812) );
OAI21X1TS U835 ( .A0(FSM_selector_B[0]), .A1(n810), .B0(n856), .Y(n811) );
NAND2X2TS U836 ( .A(n1684), .B(n1640), .Y(n1643) );
INVX12TS U837 ( .A(n1284), .Y(n1695) );
INVX12TS U838 ( .A(n2023), .Y(n2024) );
NOR2X1TS U839 ( .A(n1698), .B(n2042), .Y(n1700) );
INVX3TS U840 ( .A(n896), .Y(n1306) );
INVX12TS U841 ( .A(n2018), .Y(n1459) );
CLKMX2X2TS U842 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
CLKMX2X2TS U843 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
CLKMX2X2TS U844 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
BUFX8TS U845 ( .A(Op_MY[16]), .Y(n1336) );
CLKMX2X2TS U846 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
NOR2X1TS U847 ( .A(n2043), .B(n2038), .Y(n1667) );
OR2X2TS U848 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
OAI21X4TS U849 ( .A0(n1637), .A1(n722), .B0(n721), .Y(n725) );
BUFX8TS U850 ( .A(n843), .Y(n1518) );
XOR2X4TS U851 ( .A(Op_MX[20]), .B(n394), .Y(n745) );
INVX12TS U852 ( .A(Op_MX[11]), .Y(n1285) );
OAI21X1TS U853 ( .A0(n1383), .A1(n1399), .B0(n1243), .Y(n1244) );
NAND2X2TS U854 ( .A(n522), .B(n527), .Y(n491) );
NAND2X4TS U855 ( .A(Op_MY[1]), .B(n1516), .Y(n527) );
OAI21X1TS U856 ( .A0(n392), .A1(n1390), .B0(n1161), .Y(n1162) );
NOR2X4TS U857 ( .A(n1686), .B(n1384), .Y(n701) );
AOI222X1TS U858 ( .A0(n1269), .A1(n1280), .B0(n1452), .B1(n1304), .C0(n1242),
.C1(n1686), .Y(n1222) );
OAI21X2TS U859 ( .A0(n1376), .A1(n1474), .B0(n1049), .Y(n1050) );
ADDFX2TS U860 ( .A(n1492), .B(n1491), .CI(n1490), .CO(mult_x_19_n834), .S(
mult_x_19_n835) );
XNOR2X1TS U861 ( .A(n395), .B(Op_MX[2]), .Y(mult_x_19_n1314) );
OR2X8TS U862 ( .A(mult_x_19_n761), .B(mult_x_19_n771), .Y(n407) );
NAND2X2TS U863 ( .A(n1105), .B(n1100), .Y(n737) );
OR2X4TS U864 ( .A(mult_x_19_n604), .B(mult_x_19_n610), .Y(n399) );
XOR2X1TS U865 ( .A(n977), .B(n1267), .Y(mult_x_19_n1171) );
OAI21X1TS U866 ( .A0(n404), .A1(n536), .B0(n976), .Y(n977) );
ADDFHX2TS U867 ( .A(n1336), .B(n925), .CI(n859), .CO(mult_x_19_n587), .S(
mult_x_19_n588) );
OAI21X2TS U868 ( .A0(n681), .A1(n1627), .B0(n680), .Y(n682) );
OAI2BB1X4TS U869 ( .A0N(n902), .A1N(n900), .B0(n899), .Y(n889) );
AND3X4TS U870 ( .A(n745), .B(n744), .C(n484), .Y(n1378) );
XNOR2X4TS U871 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n744) );
ADDFHX2TS U872 ( .A(n1528), .B(n1527), .CI(n1526), .CO(mult_x_19_n724), .S(
mult_x_19_n725) );
AOI21X2TS U873 ( .A0(n1831), .A1(n1551), .B0(n1550), .Y(n1556) );
NAND2X4TS U874 ( .A(n661), .B(n1551), .Y(n663) );
AOI21X2TS U875 ( .A0(n987), .A1(n990), .B0(n989), .Y(n995) );
NAND2X4TS U876 ( .A(mult_x_19_n761), .B(mult_x_19_n771), .Y(n1965) );
OR2X4TS U877 ( .A(n1532), .B(n1533), .Y(n464) );
AOI21X4TS U878 ( .A0(n1897), .A1(n1894), .B0(n642), .Y(n643) );
NAND2X4TS U879 ( .A(n702), .B(n704), .Y(n928) );
XOR2X2TS U880 ( .A(n1156), .B(n1502), .Y(mult_x_19_n1308) );
OAI21X4TS U881 ( .A0(n1637), .A1(n1633), .B0(n1634), .Y(n1576) );
OAI21X4TS U882 ( .A0(n1637), .A1(n1568), .B0(n1567), .Y(n1571) );
NOR2X2TS U883 ( .A(n1855), .B(n1857), .Y(n598) );
OR2X8TS U884 ( .A(n1633), .B(n664), .Y(n1604) );
OAI21X2TS U885 ( .A0(n1291), .A1(n1427), .B0(n1016), .Y(n1017) );
NAND2X4TS U886 ( .A(n881), .B(n883), .Y(n741) );
NOR2X4TS U887 ( .A(n2020), .B(n2019), .Y(n888) );
OAI21X4TS U888 ( .A0(n692), .A1(n461), .B0(n691), .Y(n281) );
CMPR42X2TS U889 ( .A(mult_x_19_n681), .B(n478), .C(mult_x_19_n1179), .D(
mult_x_19_n691), .ICI(mult_x_19_n1227), .S(mult_x_19_n679), .ICO(
mult_x_19_n677), .CO(mult_x_19_n678) );
NOR2X4TS U890 ( .A(n513), .B(n565), .Y(n581) );
OAI21X2TS U891 ( .A0(n1308), .A1(n1354), .B0(n1071), .Y(n1072) );
NAND2X4TS U892 ( .A(mult_x_19_n695), .B(mult_x_19_n705), .Y(n1634) );
NOR2X4TS U893 ( .A(mult_x_19_n695), .B(mult_x_19_n705), .Y(n1633) );
NAND2X4TS U894 ( .A(mult_x_19_n653), .B(mult_x_19_n662), .Y(n1605) );
AOI222X4TS U895 ( .A0(n1269), .A1(n1205), .B0(n917), .B1(n1309), .C0(n1242),
.C1(n1340), .Y(n904) );
AOI222X4TS U896 ( .A0(n1269), .A1(n1340), .B0(n917), .B1(n1338), .C0(n1242),
.C1(n1251), .Y(n907) );
AOI222X4TS U897 ( .A0(n1269), .A1(n1497), .B0(n1396), .B1(n1495), .C0(n1242),
.C1(n1493), .Y(n943) );
AOI222X2TS U898 ( .A0(n1397), .A1(n1387), .B0(n1452), .B1(n1987), .C0(n1242),
.C1(n1384), .Y(n953) );
OAI21X4TS U899 ( .A0(n787), .A1(n461), .B0(n786), .Y(n280) );
NOR2X4TS U900 ( .A(n1624), .B(n1626), .Y(n1614) );
AND2X4TS U901 ( .A(n730), .B(n729), .Y(n736) );
XOR2X2TS U902 ( .A(n1356), .B(n1355), .Y(mult_x_19_n1252) );
OAI21X4TS U903 ( .A0(n1848), .A1(n1844), .B0(n1845), .Y(n1851) );
OAI21X1TS U904 ( .A0(n1513), .A1(n1390), .B0(n549), .Y(n550) );
OAI21X1TS U905 ( .A0(n1501), .A1(n1500), .B0(n1499), .Y(n1503) );
NAND2X4TS U906 ( .A(Op_MY[1]), .B(Op_MY[0]), .Y(n528) );
XOR2X1TS U907 ( .A(n529), .B(n528), .Y(n530) );
OAI21X1TS U908 ( .A0(n1261), .A1(n1456), .B0(n965), .Y(n966) );
OAI21X1TS U909 ( .A0(n1523), .A1(n1390), .B0(n555), .Y(n556) );
OAI21X4TS U910 ( .A0(n669), .A1(n793), .B0(n668), .Y(n670) );
OA21X4TS U911 ( .A0(n1475), .A1(n1382), .B0(n845), .Y(n1514) );
NAND2X4TS U912 ( .A(mult_x_19_n611), .B(mult_x_19_n617), .Y(n1611) );
OAI21X4TS U913 ( .A0(n930), .A1(n734), .B0(n733), .Y(n735) );
CMPR42X2TS U914 ( .A(mult_x_19_n1281), .B(mult_x_19_n1209), .C(
mult_x_19_n1305), .D(mult_x_19_n1257), .ICI(mult_x_19_n745), .S(
mult_x_19_n742), .ICO(mult_x_19_n740), .CO(mult_x_19_n741) );
NOR2X4TS U915 ( .A(n608), .B(n610), .Y(n494) );
NAND2X4TS U916 ( .A(n566), .B(n562), .Y(n580) );
CMPR42X2TS U917 ( .A(mult_x_19_n797), .B(mult_x_19_n1214), .C(
mult_x_19_n1262), .D(mult_x_19_n1238), .ICI(mult_x_19_n1286), .S(
mult_x_19_n795), .ICO(mult_x_19_n793), .CO(mult_x_19_n794) );
OAI21X1TS U918 ( .A0(n1383), .A1(n1474), .B0(n1247), .Y(n1248) );
AOI222X2TS U919 ( .A0(n1410), .A1(n1481), .B0(n1409), .B1(n1985), .C0(n1408),
.C1(n1516), .Y(n518) );
OAI21X4TS U920 ( .A0(n809), .A1(n461), .B0(n808), .Y(n273) );
XOR2X4TS U921 ( .A(n807), .B(n806), .Y(n809) );
AOI21X1TS U922 ( .A0(n1233), .A1(n1232), .B0(n1231), .Y(n1504) );
OAI21X4TS U923 ( .A0(n776), .A1(n426), .B0(n777), .Y(n695) );
OAI21X1TS U924 ( .A0(n403), .A1(n1456), .B0(n1222), .Y(n1223) );
OAI21X4TS U925 ( .A0(n1597), .A1(n1591), .B0(n1598), .Y(n665) );
NOR2X4TS U926 ( .A(n1129), .B(n701), .Y(n704) );
OAI21X1TS U927 ( .A0(n1501), .A1(n1330), .B0(n985), .Y(n986) );
NOR2X8TS U928 ( .A(mult_x_19_n801), .B(mult_x_19_n792), .Y(n1946) );
OAI21X1TS U929 ( .A0(n1371), .A1(n1390), .B0(n1370), .Y(n1372) );
AOI21X4TS U930 ( .A0(n1550), .A1(n661), .B0(n660), .Y(n662) );
NAND2X4TS U931 ( .A(n913), .B(n920), .Y(n861) );
OAI21X4TS U932 ( .A0(n1603), .A1(n673), .B0(n672), .Y(n674) );
NOR2X4TS U933 ( .A(n879), .B(n741), .Y(n873) );
NOR2X4TS U934 ( .A(n2019), .B(n1326), .Y(n890) );
OAI21X1TS U935 ( .A0(n405), .A1(n1427), .B0(n1014), .Y(n1015) );
OAI21X1TS U936 ( .A0(n405), .A1(n1347), .B0(n1114), .Y(n1115) );
OAI21X2TS U937 ( .A0(n405), .A1(n1330), .B0(n1203), .Y(n1204) );
OAI21X2TS U938 ( .A0(n1637), .A1(n1596), .B0(n1595), .Y(n1601) );
XNOR2X4TS U939 ( .A(n1601), .B(n1600), .Y(n1602) );
NOR3X4TS U940 ( .A(n2035), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[0]), .Y(n1657) );
NOR2X4TS U941 ( .A(n909), .B(n912), .Y(n860) );
CMPR42X2TS U942 ( .A(mult_x_19_n743), .B(mult_x_19_n1256), .C(
mult_x_19_n1232), .D(mult_x_19_n1280), .ICI(mult_x_19_n734), .S(
mult_x_19_n731), .ICO(mult_x_19_n729), .CO(mult_x_19_n730) );
OAI21X2TS U943 ( .A0(n799), .A1(n718), .B0(n793), .Y(n719) );
AOI21X4TS U944 ( .A0(n880), .A1(n883), .B0(n739), .Y(n740) );
AOI21X2TS U945 ( .A0(n902), .A1(n881), .B0(n880), .Y(n885) );
NOR2X4TS U946 ( .A(mult_x_19_n598), .B(mult_x_19_n603), .Y(n693) );
CMPR42X2TS U947 ( .A(mult_x_19_n1146), .B(mult_x_19_n1170), .C(
mult_x_19_n606), .D(mult_x_19_n601), .ICI(mult_x_19_n602), .S(
mult_x_19_n598), .ICO(mult_x_19_n596), .CO(mult_x_19_n597) );
NAND2X4TS U948 ( .A(n891), .B(n899), .Y(n880) );
NOR2X4TS U949 ( .A(n928), .B(n734), .Y(n729) );
CMPR42X2TS U950 ( .A(mult_x_19_n1169), .B(mult_x_19_n594), .C(mult_x_19_n600), .D(mult_x_19_n1145), .ICI(mult_x_19_n596), .S(mult_x_19_n592), .ICO(
mult_x_19_n590), .CO(mult_x_19_n591) );
INVX12TS U951 ( .A(n676), .Y(n1625) );
OAI21X1TS U952 ( .A0(n1312), .A1(n536), .B0(n979), .Y(n980) );
NAND2X2TS U953 ( .A(n1614), .B(n1619), .Y(n782) );
NAND2X4TS U954 ( .A(mult_x_19_n717), .B(mult_x_19_n727), .Y(n1553) );
CMPR42X2TS U955 ( .A(mult_x_19_n1303), .B(mult_x_19_n732), .C(
mult_x_19_n1255), .D(mult_x_19_n1279), .ICI(mult_x_19_n733), .S(
mult_x_19_n720), .ICO(mult_x_19_n718), .CO(mult_x_19_n719) );
OAI21X1TS U956 ( .A0(n398), .A1(n1143), .B0(n1147), .Y(n1148) );
OAI21X1TS U957 ( .A0(n1291), .A1(n1330), .B0(n983), .Y(n984) );
ADDFHX2TS U958 ( .A(Op_MY[0]), .B(n1525), .CI(n1524), .CO(n1526), .S(
mult_x_19_n736) );
INVX6TS U959 ( .A(n1182), .Y(n1418) );
BUFX6TS U960 ( .A(n1423), .Y(n1419) );
CLKBUFX2TS U961 ( .A(n1239), .Y(n1434) );
OA21X1TS U962 ( .A0(n1523), .A1(n1522), .B0(n1521), .Y(n1527) );
NAND2X1TS U963 ( .A(n626), .B(n955), .Y(n627) );
CLKBUFX2TS U964 ( .A(n1388), .Y(n1369) );
OAI21X2TS U965 ( .A0(n482), .A1(n1288), .B0(n587), .Y(n588) );
NAND2X1TS U966 ( .A(n583), .B(n607), .Y(n584) );
BUFX3TS U967 ( .A(n1274), .Y(n1362) );
NOR2X4TS U968 ( .A(n577), .B(n576), .Y(n574) );
BUFX4TS U969 ( .A(n843), .Y(n1333) );
OAI21X1TS U970 ( .A0(n1817), .A1(n2040), .B0(n1697), .Y(n1788) );
NOR2X4TS U971 ( .A(mult_x_19_n673), .B(mult_x_19_n683), .Y(n1569) );
NOR2X4TS U972 ( .A(n1438), .B(n1357), .Y(n513) );
BUFX3TS U973 ( .A(n1207), .Y(n1406) );
OAI21X1TS U974 ( .A0(n1391), .A1(n1456), .B0(n953), .Y(n954) );
BUFX4TS U975 ( .A(n978), .Y(n1409) );
XNOR2X2TS U976 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n515) );
BUFX12TS U977 ( .A(n1354), .Y(n1288) );
CLKBUFX2TS U978 ( .A(n1136), .Y(n1272) );
INVX8TS U979 ( .A(n952), .Y(n1450) );
OAI21X1TS U980 ( .A0(n398), .A1(n1051), .B0(n1033), .Y(n1034) );
BUFX4TS U981 ( .A(n1041), .Y(n1480) );
OAI21X2TS U982 ( .A0(n1467), .A1(n1330), .B0(n533), .Y(n534) );
NOR2X4TS U983 ( .A(n1357), .B(n1283), .Y(n565) );
NOR2X1TS U984 ( .A(n872), .B(n1209), .Y(n742) );
BUFX3TS U985 ( .A(n1334), .Y(n1520) );
BUFX3TS U986 ( .A(n1397), .Y(n1269) );
BUFX3TS U987 ( .A(n1088), .Y(n1359) );
OA21XLTS U988 ( .A0(n1371), .A1(n1512), .B0(n1303), .Y(n2033) );
CMPR42X2TS U989 ( .A(mult_x_19_n724), .B(mult_x_19_n1158), .C(mult_x_19_n714), .D(mult_x_19_n1206), .ICI(mult_x_19_n721), .S(mult_x_19_n712), .ICO(
mult_x_19_n710), .CO(mult_x_19_n711) );
OAI21XLTS U990 ( .A0(n1523), .A1(n1274), .B0(n602), .Y(n603) );
XOR2X1TS U991 ( .A(n1364), .B(n1363), .Y(mult_x_19_n1295) );
AOI21X1TS U992 ( .A0(n1700), .A1(n1788), .B0(n1699), .Y(n1770) );
NOR2X4TS U993 ( .A(mult_x_19_n586), .B(mult_x_19_n591), .Y(n1626) );
AO21XLTS U994 ( .A0(n1333), .A1(n1324), .B0(n1323), .Y(n1325) );
NOR2X4TS U995 ( .A(mult_x_19_n653), .B(mult_x_19_n662), .Y(n1578) );
NAND2X1TS U996 ( .A(n636), .B(n635), .Y(n1870) );
INVX2TS U997 ( .A(n1857), .Y(n1859) );
NOR2X4TS U998 ( .A(mult_x_19_n826), .B(mult_x_19_n832), .Y(n647) );
INVX2TS U999 ( .A(n1788), .Y(n1805) );
INVX2TS U1000 ( .A(n1770), .Y(n1783) );
NAND2X1TS U1001 ( .A(n594), .B(n593), .Y(n1854) );
MX2X1TS U1002 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
XOR2X1TS U1003 ( .A(n2017), .B(n811), .Y(DP_OP_32J1_122_6543_n22) );
CLKAND2X2TS U1004 ( .A(n548), .B(Op_MX[2]), .Y(n1881) );
INVX2TS U1005 ( .A(n1879), .Y(n548) );
NAND2X4TS U1006 ( .A(mult_x_19_n739), .B(mult_x_19_n749), .Y(n1828) );
CLKINVX12TS U1007 ( .A(n1625), .Y(n427) );
NAND4XLTS U1008 ( .A(n2000), .B(n1999), .C(n1998), .D(n411), .Y(n2001) );
NAND4XLTS U1009 ( .A(n1996), .B(n1995), .C(n410), .D(n1994), .Y(n2002) );
NOR2X2TS U1010 ( .A(n936), .B(n938), .Y(n732) );
OAI21X1TS U1011 ( .A0(n402), .A1(n1406), .B0(n1405), .Y(n1407) );
NAND2X1TS U1012 ( .A(n2022), .B(n1297), .Y(n939) );
NAND2X1TS U1013 ( .A(n929), .B(n932), .Y(n935) );
NOR2X2TS U1014 ( .A(n2025), .B(n2024), .Y(n991) );
NAND2X1TS U1015 ( .A(n2025), .B(n2024), .Y(n992) );
NAND2X2TS U1016 ( .A(n2028), .B(n2026), .Y(n955) );
NOR2X2TS U1017 ( .A(n2028), .B(n2026), .Y(n956) );
CLKBUFX2TS U1018 ( .A(n1482), .Y(n1060) );
NOR2X2TS U1019 ( .A(n2030), .B(n2028), .Y(n610) );
NOR2X4TS U1020 ( .A(n1283), .B(n2030), .Y(n608) );
OAI21XLTS U1021 ( .A0(n1371), .A1(n1436), .B0(n1191), .Y(n1192) );
OAI21XLTS U1022 ( .A0(n1291), .A1(n1500), .B0(n1157), .Y(n1158) );
NOR2X2TS U1023 ( .A(n1384), .B(n1377), .Y(n1129) );
NAND2X1TS U1024 ( .A(n1209), .B(n1326), .Y(n882) );
NAND2X2TS U1025 ( .A(n2020), .B(n2019), .Y(n899) );
INVX2TS U1026 ( .A(Op_MX[1]), .Y(n541) );
OAI21XLTS U1027 ( .A0(n1371), .A1(n1406), .B0(n1180), .Y(n1181) );
OAI21XLTS U1028 ( .A0(n1291), .A1(n1288), .B0(n1077), .Y(n1078) );
AO21XLTS U1029 ( .A0(n1359), .A1(n1324), .B0(n1136), .Y(n1091) );
AOI222X1TS U1030 ( .A0(n1404), .A1(n1497), .B0(n1419), .B1(n1495), .C0(n1314), .C1(n1493), .Y(n1018) );
OA21X1TS U1031 ( .A0(n401), .A1(n1522), .B0(n1185), .Y(n1186) );
OAI21X1TS U1032 ( .A0(n1308), .A1(n1051), .B0(n1037), .Y(n1038) );
OA21XLTS U1033 ( .A0(n392), .A1(n1512), .B0(n1335), .Y(n2031) );
OAI21X1TS U1034 ( .A0(n1211), .A1(n1207), .B0(n1001), .Y(n1002) );
OAI21XLTS U1035 ( .A0(n1342), .A1(n1399), .B0(n907), .Y(n908) );
NAND2X1TS U1036 ( .A(n2019), .B(n1326), .Y(n891) );
AO21XLTS U1037 ( .A0(n1403), .A1(n1324), .B0(n1404), .Y(n1005) );
NOR2X1TS U1038 ( .A(n1336), .B(n1300), .Y(n912) );
OAI21X1TS U1039 ( .A0(n1291), .A1(n1399), .B0(n926), .Y(n927) );
OAI21XLTS U1040 ( .A0(n402), .A1(n1274), .B0(n1273), .Y(n1275) );
NAND2X1TS U1041 ( .A(n1482), .B(n1470), .Y(n1448) );
OAI21X1TS U1042 ( .A0(n401), .A1(n1362), .B0(n1361), .Y(n1364) );
ADDHX1TS U1043 ( .A(n1447), .B(n1446), .CO(mult_x_19_n862), .S(n640) );
AOI222X1TS U1044 ( .A0(n1239), .A1(n1472), .B0(n1258), .B1(n1471), .C0(n435),
.C1(n1470), .Y(n624) );
OAI21XLTS U1045 ( .A0(n1371), .A1(n1274), .B0(n1137), .Y(n1138) );
CLKXOR2X4TS U1046 ( .A(n524), .B(n523), .Y(n1513) );
NAND2X1TS U1047 ( .A(n477), .B(n522), .Y(n523) );
OA21XLTS U1048 ( .A0(n403), .A1(n1512), .B0(n1305), .Y(n2032) );
CMPR42X1TS U1049 ( .A(mult_x_19_n640), .B(mult_x_19_n1223), .C(
mult_x_19_n1175), .D(mult_x_19_n1151), .ICI(mult_x_19_n1199), .S(
mult_x_19_n638), .ICO(mult_x_19_n636), .CO(mult_x_19_n637) );
BUFX4TS U1050 ( .A(n1041), .Y(n1465) );
XOR2X1TS U1051 ( .A(n708), .B(n1997), .Y(mult_x_19_n1262) );
BUFX3TS U1052 ( .A(n1354), .Y(n1436) );
CMPR42X1TS U1053 ( .A(mult_x_19_n807), .B(mult_x_19_n1239), .C(
mult_x_19_n1215), .D(mult_x_19_n1287), .ICI(mult_x_19_n811), .S(
mult_x_19_n805), .ICO(mult_x_19_n803), .CO(mult_x_19_n804) );
NAND2X1TS U1054 ( .A(n567), .B(n566), .Y(n568) );
AOI21X2TS U1055 ( .A0(n582), .A1(n564), .B0(n563), .Y(n569) );
AO21XLTS U1056 ( .A0(n1452), .A1(n1351), .B0(n1269), .Y(n875) );
INVX2TS U1057 ( .A(n1378), .Y(n844) );
CLKINVX3TS U1058 ( .A(n844), .Y(n1327) );
INVX2TS U1059 ( .A(n504), .Y(n952) );
BUFX3TS U1060 ( .A(n1512), .Y(n1522) );
NAND2X2TS U1061 ( .A(n779), .B(n683), .Y(n685) );
OAI21XLTS U1062 ( .A0(n1308), .A1(n905), .B0(n897), .Y(n898) );
XOR2X1TS U1063 ( .A(n1344), .B(n1343), .Y(mult_x_19_n1229) );
BUFX6TS U1064 ( .A(n1207), .Y(n1427) );
XOR2X1TS U1065 ( .A(n1331), .B(n1413), .Y(mult_x_19_n1179) );
CLKBUFX2TS U1066 ( .A(n1397), .Y(n1454) );
AOI21X1TS U1067 ( .A0(n796), .A1(n795), .B0(n794), .Y(n797) );
NAND2X1TS U1068 ( .A(n834), .B(n490), .Y(n764) );
NOR2X4TS U1069 ( .A(n685), .B(n776), .Y(n832) );
OAI21XLTS U1070 ( .A0(n1312), .A1(n905), .B0(n904), .Y(n906) );
BUFX3TS U1071 ( .A(n1152), .Y(n1386) );
NAND2X4TS U1072 ( .A(n507), .B(n528), .Y(n1467) );
OR2X1TS U1073 ( .A(Op_MY[1]), .B(Op_MY[0]), .Y(n507) );
INVX4TS U1074 ( .A(n482), .Y(n1464) );
CLKINVX6TS U1075 ( .A(Op_MY[9]), .Y(n1505) );
NOR2X1TS U1076 ( .A(n1770), .B(n1701), .Y(n1764) );
NAND2X1TS U1077 ( .A(n1579), .B(n716), .Y(n711) );
AND3X1TS U1078 ( .A(n1688), .B(P_Sgf[47]), .C(n1665), .Y(n1669) );
INVX8TS U1079 ( .A(n1285), .Y(n1694) );
INVX12TS U1080 ( .A(n519), .Y(n1685) );
INVX2TS U1081 ( .A(n1863), .Y(n1865) );
OAI21XLTS U1082 ( .A0(n1907), .A1(n1906), .B0(n1905), .Y(n1912) );
CLKMX2X2TS U1083 ( .A(n1565), .B(P_Sgf[24]), .S0(n1631), .Y(n262) );
MX2X1TS U1084 ( .A(n1549), .B(P_Sgf[26]), .S0(n1972), .Y(n264) );
XOR2X1TS U1085 ( .A(n1548), .B(n1547), .Y(n1549) );
OAI21X2TS U1086 ( .A0(n1637), .A1(n1583), .B0(n1582), .Y(n1588) );
MX2X1TS U1087 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n1696), .Y(n337) );
MX2X1TS U1088 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n1696), .Y(n341) );
MX2X1TS U1089 ( .A(Add_result[2]), .B(n1818), .S0(n1834), .Y(n307) );
INVX2TS U1090 ( .A(n1817), .Y(n1811) );
MX2X1TS U1091 ( .A(Add_result[4]), .B(n1807), .S0(n1834), .Y(n305) );
MX2X1TS U1092 ( .A(Add_result[5]), .B(n1801), .S0(n1806), .Y(n304) );
MX2X1TS U1093 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n1979), .Y(n367) );
OAI21X2TS U1094 ( .A0(n727), .A1(n461), .B0(n726), .Y(n272) );
XOR2X2TS U1095 ( .A(n725), .B(n724), .Y(n727) );
MX2X1TS U1096 ( .A(FSM_add_overflow_flag), .B(n1835), .S0(n1806), .Y(n285)
);
INVX2TS U1097 ( .A(n1855), .Y(n1850) );
MX2X1TS U1098 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n1979), .Y(n368) );
MX2X1TS U1099 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n1696), .Y(n373) );
MX2X1TS U1100 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n437), .Y(n366) );
NAND2X1TS U1101 ( .A(n1631), .B(n452), .Y(n786) );
NAND2X1TS U1102 ( .A(n1974), .B(n453), .Y(n841) );
NAND2X1TS U1103 ( .A(n1638), .B(n454), .Y(n824) );
NAND2X1TS U1104 ( .A(n1917), .B(n455), .Y(n830) );
INVX2TS U1105 ( .A(n697), .Y(n698) );
NOR2BX1TS U1106 ( .AN(n441), .B(n696), .Y(n697) );
CLKMX2X2TS U1107 ( .A(n1577), .B(n444), .S0(n1972), .Y(n266) );
CLKMX2X2TS U1108 ( .A(n1572), .B(n445), .S0(n1972), .Y(n267) );
MX2X1TS U1109 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n1696), .Y(n314) );
MX2X1TS U1110 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n1693), .Y(n315) );
MX2X1TS U1111 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n1693), .Y(n320) );
MX2X1TS U1112 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n1696), .Y(n324) );
MX2X1TS U1113 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n1693), .Y(n327) );
MX2X1TS U1114 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n1696), .Y(n328) );
MX2X1TS U1115 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n438), .Y(n333) );
MX2X1TS U1116 ( .A(Data_MX[5]), .B(n1695), .S0(n1971), .Y(n349) );
MX2X1TS U1117 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n1971), .Y(n354) );
MX2X1TS U1118 ( .A(Data_MX[11]), .B(n1694), .S0(n1971), .Y(n355) );
MX2X1TS U1119 ( .A(Data_MX[14]), .B(n1992), .S0(n1979), .Y(n358) );
MX2X1TS U1120 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n1979), .Y(n360) );
MX2X1TS U1121 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n1979), .Y(n362) );
MX2X1TS U1122 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n1969), .Y(n364) );
NAND4XLTS U1123 ( .A(n1983), .B(n1982), .C(n1981), .D(n1980), .Y(n2004) );
NAND4XLTS U1124 ( .A(n1991), .B(n1990), .C(n1989), .D(n1988), .Y(n2003) );
BUFX4TS U1125 ( .A(n1423), .Y(n1403) );
OAI21X4TS U1126 ( .A0(n687), .A1(n426), .B0(n686), .Y(n689) );
OAI21X4TS U1127 ( .A0(n782), .A1(n426), .B0(n781), .Y(n785) );
INVX16TS U1128 ( .A(n1625), .Y(n426) );
AOI21X4TS U1129 ( .A0(n805), .A1(n794), .B0(n667), .Y(n668) );
INVX2TS U1130 ( .A(n396), .Y(n1997) );
XNOR2X4TS U1131 ( .A(n874), .B(n1324), .Y(n398) );
XNOR2X4TS U1132 ( .A(n609), .B(n584), .Y(n401) );
XNOR2X4TS U1133 ( .A(n957), .B(n627), .Y(n402) );
XNOR2X4TS U1134 ( .A(n1133), .B(n1132), .Y(n403) );
XNOR2X4TS U1135 ( .A(n885), .B(n884), .Y(n404) );
XNOR2X4TS U1136 ( .A(n916), .B(n915), .Y(n405) );
AND3X4TS U1137 ( .A(n516), .B(n465), .C(n515), .Y(n1224) );
OR2X2TS U1138 ( .A(Op_MY[1]), .B(n1516), .Y(n406) );
OA21XLTS U1139 ( .A0(n1261), .A1(n1512), .B0(n1187), .Y(n408) );
INVX2TS U1140 ( .A(n479), .Y(n1993) );
NOR4X1TS U1141 ( .A(Op_MX[22]), .B(n429), .C(Op_MX[15]), .D(n1992), .Y(n410)
);
NOR4X1TS U1142 ( .A(Op_MX[11]), .B(n431), .C(Op_MX[0]), .D(Op_MX[5]), .Y(
n411) );
NAND2X4TS U1143 ( .A(mult_x_19_n792), .B(mult_x_19_n801), .Y(n1947) );
ADDFX2TS U1144 ( .A(n634), .B(n633), .CI(n632), .CO(n635), .S(n618) );
BUFX12TS U1145 ( .A(n574), .Y(n1136) );
XOR2X2TS U1146 ( .A(n923), .B(n922), .Y(n924) );
INVX4TS U1147 ( .A(n647), .Y(n1922) );
OAI21X2TS U1148 ( .A0(n1857), .A1(n1854), .B0(n1858), .Y(n597) );
OAI21X2TS U1149 ( .A0(n1475), .A1(n1330), .B0(n531), .Y(n532) );
NAND2X4TS U1150 ( .A(mult_x_19_n684), .B(mult_x_19_n694), .Y(n1573) );
AOI222X2TS U1151 ( .A0(n1520), .A1(n1984), .B0(n1518), .B1(n1471), .C0(n1517), .C1(n1470), .Y(n845) );
INVX16TS U1152 ( .A(n1625), .Y(n428) );
OAI21X2TS U1153 ( .A0(n1475), .A1(n1427), .B0(n1421), .Y(n1422) );
INVX2TS U1154 ( .A(n479), .Y(n429) );
INVX2TS U1155 ( .A(n479), .Y(n430) );
INVX2TS U1156 ( .A(n396), .Y(n431) );
INVX2TS U1157 ( .A(n1713), .Y(n432) );
NOR4X1TS U1158 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[9]), .Y(
n1645) );
NOR4X1TS U1159 ( .A(P_Sgf[13]), .B(P_Sgf[11]), .C(P_Sgf[12]), .D(P_Sgf[10]),
.Y(n1646) );
XNOR2X2TS U1160 ( .A(n544), .B(n1502), .Y(n1837) );
NOR4X1TS U1161 ( .A(Op_MY[13]), .B(Op_MY[12]), .C(Op_MY[7]), .D(Op_MY[6]),
.Y(n1991) );
INVX2TS U1162 ( .A(n425), .Y(n439) );
INVX2TS U1163 ( .A(n424), .Y(n440) );
NAND2X4TS U1164 ( .A(n1972), .B(n2006), .Y(n1973) );
INVX2TS U1165 ( .A(n423), .Y(n441) );
INVX2TS U1166 ( .A(n416), .Y(n442) );
INVX2TS U1167 ( .A(n417), .Y(n443) );
CLKMX2X2TS U1168 ( .A(n1557), .B(P_Sgf[25]), .S0(n461), .Y(n263) );
INVX2TS U1169 ( .A(n422), .Y(n444) );
INVX2TS U1170 ( .A(n421), .Y(n445) );
INVX2TS U1171 ( .A(n420), .Y(n446) );
INVX2TS U1172 ( .A(n419), .Y(n447) );
INVX2TS U1173 ( .A(n418), .Y(n448) );
INVX2TS U1174 ( .A(n409), .Y(n449) );
INVX2TS U1175 ( .A(n409), .Y(n450) );
INVX2TS U1176 ( .A(n409), .Y(n451) );
INVX2TS U1177 ( .A(n413), .Y(n452) );
INVX2TS U1178 ( .A(n412), .Y(n453) );
INVX2TS U1179 ( .A(n414), .Y(n454) );
INVX2TS U1180 ( .A(n415), .Y(n455) );
NAND2X1TS U1181 ( .A(n1974), .B(P_Sgf[33]), .Y(n714) );
NAND2X1TS U1182 ( .A(n1631), .B(P_Sgf[34]), .Y(n726) );
NAND2X1TS U1183 ( .A(n461), .B(P_Sgf[35]), .Y(n808) );
NOR2X2TS U1184 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n1817) );
NOR4X1TS U1185 ( .A(P_Sgf[2]), .B(P_Sgf[3]), .C(P_Sgf[4]), .D(P_Sgf[5]), .Y(
n1648) );
NOR4X1TS U1186 ( .A(n1985), .B(n1984), .C(Op_MY[1]), .D(Op_MY[0]), .Y(n1990)
);
CLKXOR2X2TS U1187 ( .A(n586), .B(n1392), .Y(n596) );
OAI21X1TS U1188 ( .A0(n1475), .A1(n1288), .B0(n624), .Y(n625) );
OAI21XLTS U1189 ( .A0(n1475), .A1(n1500), .B0(n543), .Y(n544) );
OAI21X1TS U1190 ( .A0(n1475), .A1(n1399), .B0(n1398), .Y(n1400) );
OAI21X1TS U1191 ( .A0(n1475), .A1(n1474), .B0(n1473), .Y(n1476) );
NOR2XLTS U1192 ( .A(n1681), .B(n1679), .Y(n379) );
OAI22X2TS U1193 ( .A0(ack_FSM), .A1(n1641), .B0(beg_FSM), .B1(n2053), .Y(
n1681) );
XOR2X1TS U1194 ( .A(n1457), .B(n1993), .Y(mult_x_19_n1158) );
XOR2X1TS U1195 ( .A(n506), .B(n1993), .Y(mult_x_19_n1156) );
AOI222X1TS U1196 ( .A0(n1498), .A1(n1497), .B0(n1496), .B1(n1495), .C0(n1494), .C1(n1493), .Y(n1499) );
CLKINVX3TS U1197 ( .A(n925), .Y(n1497) );
CLKINVX3TS U1198 ( .A(n400), .Y(n1387) );
NOR2XLTS U1199 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n810) );
NOR3XLTS U1200 ( .A(Op_MY[10]), .B(Op_MY[9]), .C(Op_MY[23]), .Y(n1988) );
BUFX3TS U1201 ( .A(n1660), .Y(n456) );
BUFX3TS U1202 ( .A(n1660), .Y(n457) );
NOR2X2TS U1203 ( .A(n2045), .B(n1659), .Y(n1660) );
INVX2TS U1204 ( .A(n1825), .Y(n458) );
INVX2TS U1205 ( .A(n1825), .Y(n459) );
INVX2TS U1206 ( .A(n1825), .Y(n460) );
NAND2X1TS U1207 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n1697) );
NAND2X1TS U1208 ( .A(n1638), .B(n439), .Y(n691) );
NAND2X1TS U1209 ( .A(n1972), .B(n440), .Y(n774) );
OAI21X2TS U1210 ( .A0(n1211), .A1(n1051), .B0(n1210), .Y(n1212) );
AOI22X2TS U1211 ( .A0(n1225), .A1(n1464), .B0(n1510), .B1(n1265), .Y(n533)
);
AOI222X1TS U1212 ( .A0(n1410), .A1(n1460), .B0(n1409), .B1(n1984), .C0(n1408), .C1(n1510), .Y(n525) );
OAI21X2TS U1213 ( .A0(n1211), .A1(n1362), .B0(n1089), .Y(n1090) );
NAND2X4TS U1214 ( .A(n992), .B(n988), .Y(n931) );
OA21XLTS U1215 ( .A0(n1318), .A1(n1382), .B0(n1301), .Y(n462) );
NAND2X1TS U1216 ( .A(n784), .B(n783), .Y(n463) );
XNOR2X4TS U1217 ( .A(n1992), .B(Op_MX[15]), .Y(n465) );
NAND2X1TS U1218 ( .A(n1426), .B(n1464), .Y(n466) );
OA21XLTS U1219 ( .A0(n398), .A1(n1522), .B0(n1328), .Y(n467) );
OA21XLTS U1220 ( .A0(n404), .A1(n1522), .B0(n1322), .Y(n468) );
OA21XLTS U1221 ( .A0(n1342), .A1(n1382), .B0(n867), .Y(n469) );
OA21XLTS U1222 ( .A0(n1312), .A1(n1522), .B0(n1311), .Y(n470) );
OA21XLTS U1223 ( .A0(n1501), .A1(n1382), .B0(n1293), .Y(n472) );
OA21XLTS U1224 ( .A0(n1376), .A1(n1382), .B0(n1296), .Y(n473) );
OA21XLTS U1225 ( .A0(n405), .A1(n1382), .B0(n1299), .Y(n474) );
OA21XLTS U1226 ( .A0(n1308), .A1(n1522), .B0(n1307), .Y(n475) );
NAND2X1TS U1227 ( .A(n772), .B(n771), .Y(n476) );
OR2X2TS U1228 ( .A(n1516), .B(n1438), .Y(n477) );
OA21XLTS U1229 ( .A0(n402), .A1(n1512), .B0(n1302), .Y(n478) );
NAND3X2TS U1230 ( .A(n542), .B(n541), .C(n393), .Y(n480) );
AOI22X1TS U1231 ( .A0(n843), .A1(n1464), .B0(n1323), .B1(n1510), .Y(n483) );
INVX2TS U1232 ( .A(n485), .Y(n1150) );
OR2X4TS U1233 ( .A(mult_x_19_n782), .B(mult_x_19_n791), .Y(n487) );
NAND2X1TS U1234 ( .A(n574), .B(n1470), .Y(n489) );
INVX2TS U1235 ( .A(n1680), .Y(n1683) );
NOR2X2TS U1236 ( .A(n2026), .B(Op_MY[9]), .Y(n958) );
NOR2X2TS U1237 ( .A(n2022), .B(n1297), .Y(n938) );
NOR2X2TS U1238 ( .A(n888), .B(n890), .Y(n881) );
AOI222X1TS U1239 ( .A0(n1397), .A1(n1472), .B0(n1396), .B1(n1471), .C0(n1450), .C1(n1470), .Y(n1398) );
AOI222X1TS U1240 ( .A0(n1520), .A1(n1985), .B0(n1518), .B1(n1984), .C0(n1517), .C1(n1510), .Y(n1511) );
INVX2TS U1241 ( .A(n513), .Y(n564) );
BUFX4TS U1242 ( .A(n1070), .Y(n1433) );
BUFX3TS U1243 ( .A(n868), .Y(n1456) );
NAND2X1TS U1244 ( .A(n564), .B(n562), .Y(n514) );
OAI21X2TS U1245 ( .A0(n482), .A1(n1474), .B0(n1448), .Y(n1449) );
OAI21X1TS U1246 ( .A0(n1513), .A1(n1484), .B0(n1461), .Y(n1462) );
NAND2X1TS U1247 ( .A(n1323), .B(Op_MY[0]), .Y(n700) );
BUFX4TS U1248 ( .A(n868), .Y(n1399) );
CLKXOR2X2TS U1249 ( .A(n558), .B(n1363), .Y(n573) );
INVX2TS U1250 ( .A(n530), .Y(n1475) );
NOR2X4TS U1251 ( .A(mult_x_19_n810), .B(mult_x_19_n817), .Y(n1933) );
OAI31X1TS U1252 ( .A0(FS_Module_state_reg[1]), .A1(n1654), .A2(n1689), .B0(
n2045), .Y(n375) );
INVX16TS U1253 ( .A(n2029), .Y(n2030) );
INVX12TS U1254 ( .A(Op_MY[7]), .Y(n2027) );
INVX16TS U1255 ( .A(n2027), .Y(n2028) );
BUFX20TS U1256 ( .A(Op_MY[8]), .Y(n2026) );
BUFX20TS U1257 ( .A(Op_MY[3]), .Y(n1438) );
AOI21X4TS U1258 ( .A0(n477), .A1(n492), .B0(n491), .Y(n512) );
NAND2X2TS U1259 ( .A(n2030), .B(n2028), .Y(n611) );
NAND2X4TS U1260 ( .A(n1283), .B(n2030), .Y(n607) );
NAND2X1TS U1261 ( .A(n611), .B(n607), .Y(n493) );
AOI21X4TS U1262 ( .A0(n580), .A1(n494), .B0(n493), .Y(n495) );
OAI21X4TS U1263 ( .A0(n512), .A1(n496), .B0(n495), .Y(n730) );
NOR2X4TS U1264 ( .A(n956), .B(n958), .Y(n702) );
INVX2TS U1265 ( .A(n702), .Y(n498) );
INVX2TS U1266 ( .A(n705), .Y(n497) );
OAI21X4TS U1267 ( .A0(n957), .A1(n498), .B0(n497), .Y(n1128) );
INVX2TS U1268 ( .A(n701), .Y(n1127) );
NAND2X4TS U1269 ( .A(n1686), .B(n1384), .Y(n1125) );
NAND2X1TS U1270 ( .A(n1127), .B(n1125), .Y(n499) );
XNOR2X4TS U1271 ( .A(n1128), .B(n499), .Y(n500) );
XNOR2X4TS U1272 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n502) );
XOR2X4TS U1273 ( .A(Op_MX[20]), .B(Op_MX[19]), .Y(n503) );
NAND2BX4TS U1274 ( .AN(n502), .B(n503), .Y(n868) );
NOR2X8TS U1275 ( .A(n503), .B(n502), .Y(n1397) );
BUFX3TS U1276 ( .A(Op_MY[10]), .Y(n1368) );
XNOR2X4TS U1277 ( .A(Op_MX[18]), .B(Op_MX[19]), .Y(n501) );
NOR2BX4TS U1278 ( .AN(n502), .B(n501), .Y(n917) );
INVX2TS U1279 ( .A(n1505), .Y(n1367) );
AND3X4TS U1280 ( .A(n503), .B(n502), .C(n501), .Y(n504) );
AOI222X1TS U1281 ( .A0(n1454), .A1(n1368), .B0(n1452), .B1(n1367), .C0(n1450), .C1(n2026), .Y(n505) );
OAI21X1TS U1282 ( .A0(n1371), .A1(n1456), .B0(n505), .Y(n506) );
BUFX3TS U1283 ( .A(Op_MY[1]), .Y(n1528) );
OAI21X4TS U1284 ( .A0(n1467), .A1(n1399), .B0(n508), .Y(n509) );
XOR2X4TS U1285 ( .A(n509), .B(n429), .Y(n1395) );
XOR2X4TS U1286 ( .A(n582), .B(n514), .Y(n1523) );
XOR2X4TS U1287 ( .A(n1685), .B(Op_MX[16]), .Y(n516) );
NAND2BX4TS U1288 ( .AN(n465), .B(n516), .Y(n536) );
BUFX4TS U1289 ( .A(n536), .Y(n1412) );
BUFX3TS U1290 ( .A(Op_MY[4]), .Y(n1481) );
NOR2BX4TS U1291 ( .AN(n465), .B(n515), .Y(n978) );
BUFX3TS U1292 ( .A(Op_MY[3]), .Y(n1985) );
INVX4TS U1293 ( .A(n1224), .Y(n517) );
OAI21X1TS U1294 ( .A0(n1523), .A1(n1412), .B0(n518), .Y(n520) );
XOR2X1TS U1295 ( .A(n520), .B(n1413), .Y(n539) );
NAND2X1TS U1296 ( .A(n527), .B(n528), .Y(n524) );
BUFX3TS U1297 ( .A(Op_MY[3]), .Y(n1460) );
BUFX3TS U1298 ( .A(Op_MY[2]), .Y(n1984) );
OAI21X2TS U1299 ( .A0(n1513), .A1(n1412), .B0(n525), .Y(n526) );
XOR2X4TS U1300 ( .A(n526), .B(n1413), .Y(n789) );
BUFX3TS U1301 ( .A(Op_MY[2]), .Y(n1472) );
BUFX3TS U1302 ( .A(Op_MY[1]), .Y(n1471) );
INVX4TS U1303 ( .A(n482), .Y(n1470) );
AOI222X2TS U1304 ( .A0(n1410), .A1(n1472), .B0(n1409), .B1(n1471), .C0(n1408), .C1(n1470), .Y(n531) );
BUFX8TS U1305 ( .A(n978), .Y(n1225) );
ADDFHX2TS U1306 ( .A(n540), .B(n539), .CI(n538), .CO(mult_x_19_n786), .S(
mult_x_19_n787) );
XOR2X4TS U1307 ( .A(Op_MX[2]), .B(Op_MX[1]), .Y(n542) );
NAND2BX2TS U1308 ( .AN(n393), .B(n542), .Y(n1143) );
BUFX3TS U1309 ( .A(n1143), .Y(n1500) );
NOR2BX4TS U1310 ( .AN(n393), .B(n541), .Y(n1152) );
BUFX3TS U1311 ( .A(n1152), .Y(n1496) );
AOI222X1TS U1312 ( .A0(n1388), .A1(n1472), .B0(n1496), .B1(n1471), .C0(n1373), .C1(n1470), .Y(n543) );
INVX2TS U1313 ( .A(n485), .Y(n1502) );
BUFX4TS U1314 ( .A(n1388), .Y(n1498) );
AOI22X1TS U1315 ( .A0(n1498), .A1(n1528), .B0(n1386), .B1(n1464), .Y(n545)
);
XOR2X1TS U1316 ( .A(n546), .B(n1502), .Y(n1880) );
NAND2X1TS U1317 ( .A(n1388), .B(Op_MY[0]), .Y(n547) );
OAI21X1TS U1318 ( .A0(n482), .A1(n1500), .B0(n547), .Y(n1879) );
NAND2X2TS U1319 ( .A(n1880), .B(n1881), .Y(n1836) );
NOR2X4TS U1320 ( .A(n1837), .B(n1836), .Y(n1841) );
BUFX3TS U1321 ( .A(n1143), .Y(n1390) );
AOI222X1TS U1322 ( .A0(n1388), .A1(n1460), .B0(n1496), .B1(n1984), .C0(n1373), .C1(n1510), .Y(n549) );
XNOR2X4TS U1323 ( .A(Op_MX[2]), .B(Op_MX[3]), .Y(n576) );
XOR2X4TS U1324 ( .A(n1695), .B(Op_MX[4]), .Y(n577) );
NAND2BX4TS U1325 ( .AN(n576), .B(n577), .Y(n1274) );
OAI21X2TS U1326 ( .A0(n482), .A1(n1347), .B0(n489), .Y(n551) );
CLKINVX3TS U1327 ( .A(n1284), .Y(n1363) );
NAND2X1TS U1328 ( .A(n553), .B(n552), .Y(n1840) );
INVX2TS U1329 ( .A(n1840), .Y(n554) );
AOI21X4TS U1330 ( .A0(n1841), .A1(n1839), .B0(n554), .Y(n1848) );
XNOR2X2TS U1331 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n575) );
NOR2BX4TS U1332 ( .AN(n576), .B(n575), .Y(n1088) );
AOI22X1TS U1333 ( .A0(n1088), .A1(n1464), .B0(n1136), .B1(n1528), .Y(n557)
);
OAI21X1TS U1334 ( .A0(n1467), .A1(n1347), .B0(n557), .Y(n558) );
ADDHX1TS U1335 ( .A(n1695), .B(n559), .CO(n572), .S(n552) );
NAND2X1TS U1336 ( .A(n561), .B(n560), .Y(n1845) );
INVX2TS U1337 ( .A(n562), .Y(n563) );
INVX2TS U1338 ( .A(n565), .Y(n567) );
XNOR2X4TS U1339 ( .A(n569), .B(n568), .Y(n1441) );
BUFX3TS U1340 ( .A(Op_MY[5]), .Y(n1439) );
BUFX3TS U1341 ( .A(Op_MY[4]), .Y(n1519) );
AOI222X1TS U1342 ( .A0(n1388), .A1(n1439), .B0(n1496), .B1(n1519), .C0(n1373), .C1(n1460), .Y(n570) );
OAI21X1TS U1343 ( .A0(n1441), .A1(n1390), .B0(n570), .Y(n571) );
XOR2X1TS U1344 ( .A(n571), .B(n1392), .Y(n594) );
CMPR22X2TS U1345 ( .A(n573), .B(n572), .CO(n592), .S(n560) );
BUFX4TS U1346 ( .A(n574), .Y(n1360) );
BUFX6TS U1347 ( .A(n1088), .Y(n1345) );
NAND3X4TS U1348 ( .A(n577), .B(n576), .C(n575), .Y(n1122) );
INVX6TS U1349 ( .A(n1122), .Y(n1358) );
AOI222X1TS U1350 ( .A0(n1360), .A1(n1472), .B0(n1345), .B1(n1471), .C0(n1358), .C1(n1470), .Y(n578) );
OAI21X1TS U1351 ( .A0(n1475), .A1(n1347), .B0(n578), .Y(n579) );
XOR2X1TS U1352 ( .A(n579), .B(n1363), .Y(n591) );
NOR2X2TS U1353 ( .A(n594), .B(n593), .Y(n1855) );
AOI21X4TS U1354 ( .A0(n582), .A1(n581), .B0(n580), .Y(n609) );
INVX2TS U1355 ( .A(n608), .Y(n583) );
BUFX3TS U1356 ( .A(Op_MY[5]), .Y(n1986) );
AOI222X1TS U1357 ( .A0(n1388), .A1(n1432), .B0(n1386), .B1(n1986), .C0(n1373), .C1(n1481), .Y(n585) );
OAI21X1TS U1358 ( .A0(n401), .A1(n1390), .B0(n585), .Y(n586) );
XNOR2X4TS U1359 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n622) );
XOR2X4TS U1360 ( .A(Op_MX[8]), .B(Op_MX[7]), .Y(n623) );
NAND2BX4TS U1361 ( .AN(n622), .B(n623), .Y(n1354) );
NOR2X8TS U1362 ( .A(n623), .B(n622), .Y(n1239) );
AOI222X1TS U1363 ( .A0(n1360), .A1(n1460), .B0(n1345), .B1(n1984), .C0(n1358), .C1(n1510), .Y(n589) );
OAI21X1TS U1364 ( .A0(n1513), .A1(n1362), .B0(n589), .Y(n590) );
XOR2X1TS U1365 ( .A(n590), .B(n1363), .Y(n605) );
ADDHX1TS U1366 ( .A(n592), .B(n591), .CO(n604), .S(n593) );
NOR2X4TS U1367 ( .A(n596), .B(n595), .Y(n1857) );
AOI21X4TS U1368 ( .A0(n1851), .A1(n598), .B0(n597), .Y(n1867) );
XNOR2X2TS U1369 ( .A(Op_MX[6]), .B(Op_MX[7]), .Y(n621) );
NOR2BX4TS U1370 ( .AN(n622), .B(n621), .Y(n1070) );
ADDHX1TS U1371 ( .A(n1997), .B(n601), .CO(n619), .S(n606) );
AOI222X1TS U1372 ( .A0(n1360), .A1(n1481), .B0(n1345), .B1(n1985), .C0(n1358), .C1(n1516), .Y(n602) );
XOR2X1TS U1373 ( .A(n603), .B(n1363), .Y(n633) );
ADDFHX2TS U1374 ( .A(n606), .B(n605), .CI(n604), .CO(n632), .S(n595) );
INVX2TS U1375 ( .A(n610), .Y(n612) );
NAND2X1TS U1376 ( .A(n612), .B(n611), .Y(n613) );
XOR2X4TS U1377 ( .A(n614), .B(n613), .Y(n1261) );
INVX2TS U1378 ( .A(n2029), .Y(n1257) );
AOI222X1TS U1379 ( .A0(n1369), .A1(n1259), .B0(n1496), .B1(n1257), .C0(n1373), .C1(n1439), .Y(n615) );
XOR2X1TS U1380 ( .A(n616), .B(n1392), .Y(n617) );
NOR2X2TS U1381 ( .A(n618), .B(n617), .Y(n1863) );
NAND2X2TS U1382 ( .A(n618), .B(n617), .Y(n1864) );
OAI21X4TS U1383 ( .A0(n1867), .A1(n1863), .B0(n1864), .Y(n1873) );
NAND3X2TS U1384 ( .A(n623), .B(n622), .C(n621), .Y(n1195) );
INVX2TS U1385 ( .A(n956), .Y(n626) );
BUFX3TS U1386 ( .A(Op_MY[8]), .Y(n1453) );
INVX2TS U1387 ( .A(n2027), .Y(n1451) );
AOI222X1TS U1388 ( .A0(n1369), .A1(n1453), .B0(n1386), .B1(n1451), .C0(n1373), .C1(n1432), .Y(n628) );
OAI21X1TS U1389 ( .A0(n402), .A1(n1390), .B0(n628), .Y(n629) );
XOR2X1TS U1390 ( .A(n629), .B(n1392), .Y(n639) );
AOI222X1TS U1391 ( .A0(n1360), .A1(n1439), .B0(n1345), .B1(n1519), .C0(n1358), .C1(n1438), .Y(n630) );
OAI21X1TS U1392 ( .A0(n1441), .A1(n1362), .B0(n630), .Y(n631) );
XOR2X1TS U1393 ( .A(n631), .B(n1363), .Y(n638) );
INVX2TS U1394 ( .A(n1870), .Y(n637) );
AOI21X4TS U1395 ( .A0(n1873), .A1(n1871), .B0(n637), .Y(n1875) );
OR2X4TS U1396 ( .A(mult_x_19_n852), .B(mult_x_19_n856), .Y(n1897) );
CMPR32X2TS U1397 ( .A(n640), .B(n639), .C(n638), .CO(n641), .S(n636) );
NAND2X2TS U1398 ( .A(n1897), .B(n481), .Y(n644) );
INVX2TS U1399 ( .A(n1876), .Y(n1894) );
NAND2X2TS U1400 ( .A(mult_x_19_n852), .B(mult_x_19_n856), .Y(n1896) );
INVX2TS U1401 ( .A(n1896), .Y(n642) );
OAI21X4TS U1402 ( .A0(n1875), .A1(n644), .B0(n643), .Y(n1901) );
NOR2X4TS U1403 ( .A(mult_x_19_n847), .B(mult_x_19_n851), .Y(n1906) );
NOR2X4TS U1404 ( .A(mult_x_19_n840), .B(mult_x_19_n846), .Y(n1908) );
NOR2X2TS U1405 ( .A(n1906), .B(n1908), .Y(n646) );
NAND2X2TS U1406 ( .A(mult_x_19_n847), .B(mult_x_19_n851), .Y(n1905) );
NAND2X2TS U1407 ( .A(mult_x_19_n840), .B(mult_x_19_n846), .Y(n1909) );
OAI21X2TS U1408 ( .A0(n1908), .A1(n1905), .B0(n1909), .Y(n645) );
AOI21X4TS U1409 ( .A0(n1901), .A1(n646), .B0(n645), .Y(n1914) );
NAND2X2TS U1410 ( .A(n1922), .B(n488), .Y(n650) );
NAND2X2TS U1411 ( .A(mult_x_19_n833), .B(mult_x_19_n839), .Y(n1915) );
INVX2TS U1412 ( .A(n1915), .Y(n1919) );
INVX2TS U1413 ( .A(n1921), .Y(n648) );
AOI21X4TS U1414 ( .A0(n1922), .A1(n1919), .B0(n648), .Y(n649) );
OAI21X4TS U1415 ( .A0(n1914), .A1(n650), .B0(n649), .Y(n1926) );
NOR2X4TS U1416 ( .A(mult_x_19_n818), .B(mult_x_19_n825), .Y(n1931) );
NOR2X4TS U1417 ( .A(n1933), .B(n1931), .Y(n652) );
NAND2X4TS U1418 ( .A(mult_x_19_n818), .B(mult_x_19_n825), .Y(n1930) );
NAND2X2TS U1419 ( .A(mult_x_19_n810), .B(mult_x_19_n817), .Y(n1934) );
OAI21X4TS U1420 ( .A0(n1933), .A1(n1930), .B0(n1934), .Y(n651) );
AOI21X4TS U1421 ( .A0(n1926), .A1(n652), .B0(n651), .Y(n1939) );
NOR2X4TS U1422 ( .A(mult_x_19_n802), .B(mult_x_19_n809), .Y(n1940) );
NOR2X4TS U1423 ( .A(n1940), .B(n1946), .Y(n1953) );
NAND2X4TS U1424 ( .A(n1953), .B(n487), .Y(n655) );
NAND2X4TS U1425 ( .A(mult_x_19_n802), .B(mult_x_19_n809), .Y(n1943) );
OAI21X4TS U1426 ( .A0(n1946), .A1(n1943), .B0(n1947), .Y(n1952) );
NAND2X2TS U1427 ( .A(mult_x_19_n782), .B(mult_x_19_n791), .Y(n1955) );
INVX2TS U1428 ( .A(n1955), .Y(n653) );
AOI21X4TS U1429 ( .A0(n1952), .A1(n487), .B0(n653), .Y(n654) );
OAI21X4TS U1430 ( .A0(n1939), .A1(n655), .B0(n654), .Y(n1884) );
NOR2X4TS U1431 ( .A(mult_x_19_n772), .B(mult_x_19_n781), .Y(n1963) );
NAND2X4TS U1432 ( .A(n407), .B(n1959), .Y(n1887) );
NOR2X8TS U1433 ( .A(mult_x_19_n750), .B(mult_x_19_n760), .Y(n1888) );
NAND2X4TS U1434 ( .A(mult_x_19_n772), .B(mult_x_19_n781), .Y(n1962) );
INVX2TS U1435 ( .A(n1962), .Y(n657) );
AOI21X4TS U1436 ( .A0(n407), .A1(n657), .B0(n656), .Y(n1886) );
OAI21X4TS U1437 ( .A0(n1886), .A1(n1888), .B0(n1889), .Y(n658) );
AOI21X4TS U1438 ( .A0(n1884), .A1(n659), .B0(n658), .Y(n1539) );
NOR2X8TS U1439 ( .A(mult_x_19_n728), .B(mult_x_19_n738), .Y(n1560) );
OAI21X4TS U1440 ( .A0(n1828), .A1(n1560), .B0(n1561), .Y(n1550) );
NAND2X2TS U1441 ( .A(mult_x_19_n706), .B(mult_x_19_n716), .Y(n1545) );
OAI21X4TS U1442 ( .A0(n1539), .A1(n663), .B0(n662), .Y(n709) );
NOR2X8TS U1443 ( .A(mult_x_19_n684), .B(mult_x_19_n694), .Y(n1566) );
NOR2X8TS U1444 ( .A(mult_x_19_n672), .B(mult_x_19_n663), .Y(n1597) );
NAND2X4TS U1445 ( .A(n1574), .B(n666), .Y(n664) );
NOR2X8TS U1446 ( .A(mult_x_19_n652), .B(mult_x_19_n644), .Y(n1584) );
NOR2X8TS U1447 ( .A(n1578), .B(n1584), .Y(n716) );
OR2X4TS U1448 ( .A(mult_x_19_n634), .B(mult_x_19_n626), .Y(n795) );
NOR2X4TS U1449 ( .A(n669), .B(n718), .Y(n671) );
NAND2X4TS U1450 ( .A(n716), .B(n671), .Y(n673) );
NOR2X4TS U1451 ( .A(n1604), .B(n673), .Y(n675) );
OAI21X4TS U1452 ( .A0(n1566), .A1(n1634), .B0(n1573), .Y(n1594) );
NAND2X4TS U1453 ( .A(mult_x_19_n673), .B(mult_x_19_n683), .Y(n1591) );
NAND2X2TS U1454 ( .A(mult_x_19_n663), .B(mult_x_19_n672), .Y(n1598) );
AOI21X4TS U1455 ( .A0(n1594), .A1(n666), .B0(n665), .Y(n1603) );
NAND2X2TS U1456 ( .A(mult_x_19_n644), .B(mult_x_19_n652), .Y(n1585) );
OAI21X4TS U1457 ( .A0(n1605), .A1(n1584), .B0(n1585), .Y(n717) );
NAND2X2TS U1458 ( .A(mult_x_19_n618), .B(mult_x_19_n625), .Y(n804) );
INVX2TS U1459 ( .A(n804), .Y(n667) );
AOI21X4TS U1460 ( .A0(n717), .A1(n671), .B0(n670), .Y(n672) );
AOI21X4TS U1461 ( .A0(n709), .A1(n675), .B0(n674), .Y(n676) );
NOR2X4TS U1462 ( .A(mult_x_19_n597), .B(mult_x_19_n592), .Y(n819) );
OR2X4TS U1463 ( .A(mult_x_19_n585), .B(mult_x_19_n581), .Y(n1619) );
INVX2TS U1464 ( .A(n826), .Y(n1610) );
NAND2X4TS U1465 ( .A(n1610), .B(n399), .Y(n776) );
INVX2TS U1466 ( .A(n832), .Y(n687) );
INVX2TS U1467 ( .A(n827), .Y(n677) );
AOI21X4TS U1468 ( .A0(n399), .A1(n678), .B0(n677), .Y(n777) );
NAND2X2TS U1469 ( .A(mult_x_19_n598), .B(mult_x_19_n603), .Y(n813) );
OAI21X4TS U1470 ( .A0(n813), .A1(n819), .B0(n820), .Y(n778) );
NAND2X2TS U1471 ( .A(mult_x_19_n586), .B(mult_x_19_n591), .Y(n1627) );
NAND2X1TS U1472 ( .A(mult_x_19_n581), .B(mult_x_19_n585), .Y(n1618) );
INVX2TS U1473 ( .A(n1618), .Y(n780) );
NAND2X1TS U1474 ( .A(mult_x_19_n577), .B(mult_x_19_n580), .Y(n783) );
INVX2TS U1475 ( .A(n783), .Y(n679) );
AOI21X4TS U1476 ( .A0(n778), .A1(n683), .B0(n682), .Y(n684) );
OAI21X4TS U1477 ( .A0(n777), .A1(n685), .B0(n684), .Y(n835) );
INVX2TS U1478 ( .A(n835), .Y(n686) );
OR2X2TS U1479 ( .A(mult_x_19_n573), .B(mult_x_19_n576), .Y(n834) );
NAND2X1TS U1480 ( .A(mult_x_19_n573), .B(mult_x_19_n576), .Y(n749) );
NAND2X1TS U1481 ( .A(n834), .B(n749), .Y(n688) );
XOR2X4TS U1482 ( .A(n689), .B(n688), .Y(n692) );
INVX2TS U1483 ( .A(n693), .Y(n815) );
NAND2X1TS U1484 ( .A(n815), .B(n813), .Y(n694) );
XOR2X4TS U1485 ( .A(n695), .B(n694), .Y(n699) );
INVX2TS U1486 ( .A(n1972), .Y(n696) );
OAI21X4TS U1487 ( .A0(n699), .A1(n1974), .B0(n698), .Y(n276) );
NAND2BX4TS U1488 ( .AN(n745), .B(n484), .Y(n1512) );
NOR2X6TS U1489 ( .A(n745), .B(n484), .Y(n1334) );
BUFX8TS U1490 ( .A(n1334), .Y(n1323) );
OAI21X4TS U1491 ( .A0(n482), .A1(n1382), .B0(n700), .Y(mult_x_19_n769) );
INVX12TS U1492 ( .A(n400), .Y(n2025) );
NAND2X2TS U1493 ( .A(n1384), .B(n1377), .Y(n1130) );
NAND2X1TS U1494 ( .A(n1130), .B(n1125), .Y(n703) );
AOI21X4TS U1495 ( .A0(n705), .A1(n704), .B0(n703), .Y(n930) );
INVX2TS U1496 ( .A(n728), .Y(n990) );
XNOR2X4TS U1497 ( .A(n987), .B(n706), .Y(n1233) );
BUFX3TS U1498 ( .A(Op_MY[11]), .Y(n1987) );
AOI222X1TS U1499 ( .A0(n1239), .A1(n1387), .B0(n1433), .B1(n1987), .C0(n436),
.C1(n1384), .Y(n707) );
OAI21X1TS U1500 ( .A0(n1391), .A1(n1436), .B0(n707), .Y(n708) );
INVX8TS U1501 ( .A(n709), .Y(n1637) );
INVX4TS U1502 ( .A(n1604), .Y(n1579) );
INVX6TS U1503 ( .A(n1603), .Y(n1581) );
AOI21X1TS U1504 ( .A0(n1581), .A1(n716), .B0(n717), .Y(n710) );
OAI21X2TS U1505 ( .A0(n1637), .A1(n711), .B0(n710), .Y(n713) );
INVX2TS U1506 ( .A(n718), .Y(n791) );
NAND2X1TS U1507 ( .A(n791), .B(n793), .Y(n712) );
XOR2X4TS U1508 ( .A(n713), .B(n712), .Y(n715) );
OAI21X4TS U1509 ( .A0(n715), .A1(n1631), .B0(n714), .Y(n271) );
INVX2TS U1510 ( .A(n716), .Y(n792) );
NOR2X2TS U1511 ( .A(n792), .B(n718), .Y(n720) );
NAND2X2TS U1512 ( .A(n720), .B(n1579), .Y(n722) );
AOI21X2TS U1513 ( .A0(n1581), .A1(n720), .B0(n719), .Y(n721) );
NAND2X1TS U1514 ( .A(n795), .B(n723), .Y(n724) );
INVX12TS U1515 ( .A(n925), .Y(n1297) );
NOR2X2TS U1516 ( .A(n1297), .B(n1336), .Y(n909) );
NOR2X4TS U1517 ( .A(n1300), .B(n2021), .Y(n864) );
NOR2X4TS U1518 ( .A(n864), .B(n1104), .Y(n738) );
INVX2TS U1519 ( .A(n873), .Y(n743) );
NAND2X2TS U1520 ( .A(n2024), .B(n2022), .Y(n945) );
NAND2X1TS U1521 ( .A(n939), .B(n945), .Y(n731) );
AOI21X4TS U1522 ( .A0(n931), .A1(n732), .B0(n731), .Y(n733) );
NOR2X8TS U1523 ( .A(n736), .B(n735), .Y(n923) );
NAND2X2TS U1524 ( .A(n1297), .B(n1336), .Y(n920) );
NAND2X2TS U1525 ( .A(n1300), .B(n2021), .Y(n1100) );
AOI21X4TS U1526 ( .A0(n861), .A1(n738), .B0(n737), .Y(n878) );
INVX2TS U1527 ( .A(n882), .Y(n739) );
OAI21X4TS U1528 ( .A0(n878), .A1(n741), .B0(n740), .Y(n872) );
OAI21X4TS U1529 ( .A0(n743), .A1(n923), .B0(n742), .Y(n747) );
NOR2BX4TS U1530 ( .AN(n745), .B(n744), .Y(n843) );
AOI21X1TS U1531 ( .A0(n1327), .A1(n1209), .B0(n1333), .Y(n746) );
OA21XLTS U1532 ( .A0(n1211), .A1(n1522), .B0(n746), .Y(n748) );
NOR2X2TS U1533 ( .A(mult_x_19_n569), .B(n751), .Y(n770) );
NOR2X2TS U1534 ( .A(n764), .B(n770), .Y(n753) );
NAND2X2TS U1535 ( .A(n832), .B(n753), .Y(n1532) );
OA21XLTS U1536 ( .A0(n1196), .A1(n1522), .B0(n844), .Y(n757) );
CMPR32X2TS U1537 ( .A(n896), .B(mult_x_19_n568), .C(n748), .CO(n754), .S(
n751) );
NOR2X2TS U1538 ( .A(n755), .B(n754), .Y(n1533) );
NAND2X1TS U1539 ( .A(mult_x_19_n572), .B(mult_x_19_n570), .Y(n838) );
INVX2TS U1540 ( .A(n838), .Y(n750) );
AOI21X1TS U1541 ( .A0(n833), .A1(n490), .B0(n750), .Y(n765) );
NAND2X1TS U1542 ( .A(mult_x_19_n569), .B(n751), .Y(n771) );
AOI21X4TS U1543 ( .A0(n835), .A1(n753), .B0(n752), .Y(n1531) );
NAND2X1TS U1544 ( .A(n755), .B(n754), .Y(n1534) );
OA21X4TS U1545 ( .A0(n1531), .A1(n1533), .B0(n1534), .Y(n756) );
OAI21X4TS U1546 ( .A0(n427), .A1(n464), .B0(n756), .Y(n762) );
CMPR32X2TS U1547 ( .A(n1209), .B(n896), .C(n757), .CO(n758), .S(n755) );
NAND2X1TS U1548 ( .A(n758), .B(n896), .Y(n759) );
NAND2X1TS U1549 ( .A(n760), .B(n759), .Y(n761) );
XNOR2X4TS U1550 ( .A(n762), .B(n761), .Y(n763) );
MX2X4TS U1551 ( .A(n763), .B(P_Sgf[47]), .S0(n1631), .Y(n237) );
INVX2TS U1552 ( .A(n764), .Y(n767) );
NAND2X1TS U1553 ( .A(n832), .B(n767), .Y(n769) );
INVX2TS U1554 ( .A(n765), .Y(n766) );
AOI21X1TS U1555 ( .A0(n835), .A1(n767), .B0(n766), .Y(n768) );
OAI21X2TS U1556 ( .A0(n428), .A1(n769), .B0(n768), .Y(n773) );
INVX2TS U1557 ( .A(n770), .Y(n772) );
XOR2X4TS U1558 ( .A(n773), .B(n476), .Y(n775) );
OAI21X4TS U1559 ( .A0(n775), .A1(n1631), .B0(n774), .Y(n283) );
INVX2TS U1560 ( .A(n776), .Y(n812) );
AOI21X4TS U1561 ( .A0(n816), .A1(n779), .B0(n778), .Y(n1623) );
OAI21X4TS U1562 ( .A0(n1623), .A1(n1626), .B0(n1627), .Y(n1615) );
AOI21X4TS U1563 ( .A0(n1615), .A1(n1619), .B0(n780), .Y(n781) );
XOR2X4TS U1564 ( .A(n785), .B(n463), .Y(n787) );
NAND2X2TS U1565 ( .A(n791), .B(n795), .Y(n798) );
NOR2X2TS U1566 ( .A(n792), .B(n798), .Y(n801) );
INVX2TS U1567 ( .A(n793), .Y(n796) );
AOI21X2TS U1568 ( .A0(n1581), .A1(n801), .B0(n800), .Y(n802) );
OAI21X2TS U1569 ( .A0(n1637), .A1(n803), .B0(n802), .Y(n807) );
NAND2X1TS U1570 ( .A(n805), .B(n804), .Y(n806) );
OR2X2TS U1571 ( .A(FSM_selector_B[1]), .B(n2036), .Y(n856) );
NAND2X1TS U1572 ( .A(n812), .B(n815), .Y(n818) );
INVX2TS U1573 ( .A(n813), .Y(n814) );
AOI21X1TS U1574 ( .A0(n816), .A1(n815), .B0(n814), .Y(n817) );
OAI21X2TS U1575 ( .A0(n428), .A1(n818), .B0(n817), .Y(n823) );
INVX2TS U1576 ( .A(n819), .Y(n821) );
NAND2X1TS U1577 ( .A(n821), .B(n820), .Y(n822) );
XOR2X4TS U1578 ( .A(n823), .B(n822), .Y(n825) );
OAI21X4TS U1579 ( .A0(n825), .A1(n1631), .B0(n824), .Y(n277) );
OAI21X2TS U1580 ( .A0(n426), .A1(n826), .B0(n1611), .Y(n829) );
NAND2X1TS U1581 ( .A(n399), .B(n827), .Y(n828) );
XOR2X4TS U1582 ( .A(n829), .B(n828), .Y(n831) );
OAI21X4TS U1583 ( .A0(n831), .A1(n461), .B0(n830), .Y(n275) );
NAND2X1TS U1584 ( .A(n832), .B(n834), .Y(n837) );
AOI21X1TS U1585 ( .A0(n835), .A1(n834), .B0(n833), .Y(n836) );
NAND2X1TS U1586 ( .A(n490), .B(n838), .Y(n839) );
XOR2X4TS U1587 ( .A(n840), .B(n839), .Y(n842) );
OAI21X4TS U1588 ( .A0(n842), .A1(n1631), .B0(n841), .Y(n282) );
OA21X4TS U1589 ( .A0(n1467), .A1(n1382), .B0(n483), .Y(n1530) );
NOR3BX1TS U1590 ( .AN(Op_MY[30]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n850) );
XOR2X1TS U1591 ( .A(n2017), .B(n850), .Y(DP_OP_32J1_122_6543_n15) );
OAI2BB1X1TS U1592 ( .A0N(Op_MY[29]), .A1N(n2039), .B0(n856), .Y(n851) );
XOR2X1TS U1593 ( .A(n2017), .B(n851), .Y(DP_OP_32J1_122_6543_n16) );
OAI2BB1X1TS U1594 ( .A0N(Op_MY[28]), .A1N(n2039), .B0(n856), .Y(n852) );
XOR2X1TS U1595 ( .A(n2017), .B(n852), .Y(DP_OP_32J1_122_6543_n17) );
OAI2BB1X1TS U1596 ( .A0N(Op_MY[27]), .A1N(n2039), .B0(n856), .Y(n853) );
XOR2X1TS U1597 ( .A(n2017), .B(n853), .Y(DP_OP_32J1_122_6543_n18) );
OAI2BB1X1TS U1598 ( .A0N(Op_MY[26]), .A1N(n2039), .B0(n856), .Y(n854) );
XOR2X1TS U1599 ( .A(n2017), .B(n854), .Y(DP_OP_32J1_122_6543_n19) );
OAI2BB1X1TS U1600 ( .A0N(Op_MY[25]), .A1N(n2039), .B0(n856), .Y(n855) );
XOR2X1TS U1601 ( .A(n2017), .B(n855), .Y(DP_OP_32J1_122_6543_n20) );
OAI2BB1X1TS U1602 ( .A0N(Op_MY[24]), .A1N(n2039), .B0(n856), .Y(n857) );
XOR2X1TS U1603 ( .A(n2017), .B(n857), .Y(DP_OP_32J1_122_6543_n21) );
XOR2X1TS U1604 ( .A(n858), .B(n1685), .Y(n859) );
INVX2TS U1605 ( .A(n860), .Y(n863) );
INVX2TS U1606 ( .A(n861), .Y(n862) );
OAI21X4TS U1607 ( .A0(n923), .A1(n863), .B0(n862), .Y(n1103) );
INVX2TS U1608 ( .A(n864), .Y(n1102) );
NAND2X1TS U1609 ( .A(n1102), .B(n1100), .Y(n865) );
XNOR2X4TS U1610 ( .A(n1103), .B(n865), .Y(n866) );
INVX2TS U1611 ( .A(n397), .Y(n1315) );
BUFX3TS U1612 ( .A(Op_MY[17]), .Y(n1338) );
AOI222X1TS U1613 ( .A0(n1323), .A1(n1315), .B0(n1333), .B1(n1338), .C0(n1327), .C1(n1336), .Y(n867) );
CMPR32X2TS U1614 ( .A(n925), .B(mult_x_19_n599), .C(n469), .CO(
mult_x_19_n593), .S(mult_x_19_n594) );
CLKBUFX2TS U1615 ( .A(n868), .Y(n905) );
OAI21X1TS U1616 ( .A0(n1196), .A1(n905), .B0(n952), .Y(n869) );
XOR2X1TS U1617 ( .A(n869), .B(n1993), .Y(mult_x_19_n1141) );
AOI21X1TS U1618 ( .A0(n1242), .A1(n1209), .B0(n1452), .Y(n870) );
XOR2X1TS U1619 ( .A(n871), .B(n430), .Y(mult_x_19_n1142) );
AOI21X4TS U1620 ( .A0(n911), .A1(n873), .B0(n872), .Y(n874) );
BUFX3TS U1621 ( .A(Op_MY[22]), .Y(n1324) );
BUFX3TS U1622 ( .A(Op_MY[22]), .Y(n1351) );
AOI21X1TS U1623 ( .A0(n1242), .A1(n1326), .B0(n875), .Y(n876) );
OAI21X1TS U1624 ( .A0(n398), .A1(n905), .B0(n876), .Y(n877) );
XOR2X1TS U1625 ( .A(n877), .B(n430), .Y(mult_x_19_n1143) );
OAI21X4TS U1626 ( .A0(n923), .A1(n879), .B0(n878), .Y(n902) );
NAND2X1TS U1627 ( .A(n883), .B(n882), .Y(n884) );
INVX2TS U1628 ( .A(n896), .Y(n1350) );
BUFX3TS U1629 ( .A(Op_MY[20]), .Y(n1205) );
AOI222X1TS U1630 ( .A0(n1269), .A1(n1351), .B0(n1452), .B1(n1350), .C0(n504),
.C1(n1205), .Y(n886) );
OAI21X1TS U1631 ( .A0(n404), .A1(n905), .B0(n886), .Y(n887) );
XOR2X1TS U1632 ( .A(n887), .B(Op_MX[20]), .Y(mult_x_19_n1144) );
INVX2TS U1633 ( .A(n888), .Y(n900) );
INVX2TS U1634 ( .A(n890), .Y(n892) );
NAND2X1TS U1635 ( .A(n892), .B(n891), .Y(n893) );
XOR2X4TS U1636 ( .A(n894), .B(n893), .Y(n895) );
BUFX3TS U1637 ( .A(Op_MY[20]), .Y(n1310) );
BUFX3TS U1638 ( .A(Op_MY[19]), .Y(n1316) );
AOI222X1TS U1639 ( .A0(n1269), .A1(n1306), .B0(n917), .B1(n1310), .C0(n504),
.C1(n1316), .Y(n897) );
NAND2X1TS U1640 ( .A(n900), .B(n899), .Y(n901) );
XNOR2X4TS U1641 ( .A(n902), .B(n901), .Y(n903) );
INVX8TS U1642 ( .A(n903), .Y(n1312) );
BUFX3TS U1643 ( .A(Op_MY[19]), .Y(n1309) );
XOR2X1TS U1644 ( .A(n906), .B(n429), .Y(mult_x_19_n1146) );
BUFX3TS U1645 ( .A(Op_MY[16]), .Y(n1251) );
XOR2X1TS U1646 ( .A(n908), .B(n430), .Y(mult_x_19_n1148) );
INVX2TS U1647 ( .A(n909), .Y(n921) );
INVX2TS U1648 ( .A(n920), .Y(n910) );
AOI21X4TS U1649 ( .A0(n911), .A1(n921), .B0(n910), .Y(n916) );
NAND2X1TS U1650 ( .A(n914), .B(n913), .Y(n915) );
BUFX3TS U1651 ( .A(Op_MY[17]), .Y(n1313) );
BUFX3TS U1652 ( .A(Op_MY[16]), .Y(n1298) );
AOI222X1TS U1653 ( .A0(n1454), .A1(n1313), .B0(n1396), .B1(n1298), .C0(n504),
.C1(n1497), .Y(n918) );
OAI21X1TS U1654 ( .A0(n405), .A1(n1399), .B0(n918), .Y(n919) );
XOR2X1TS U1655 ( .A(n919), .B(n1993), .Y(mult_x_19_n1149) );
NAND2X1TS U1656 ( .A(n921), .B(n920), .Y(n922) );
INVX2TS U1657 ( .A(n925), .Y(n1292) );
BUFX3TS U1658 ( .A(Op_MY[14]), .Y(n1374) );
AOI222X1TS U1659 ( .A0(n1269), .A1(n1251), .B0(n1396), .B1(n1292), .C0(n1242), .C1(n1374), .Y(n926) );
XOR2X1TS U1660 ( .A(n927), .B(n1993), .Y(mult_x_19_n1150) );
INVX2TS U1661 ( .A(n928), .Y(n929) );
INVX2TS U1662 ( .A(n930), .Y(n933) );
AOI21X4TS U1663 ( .A0(n933), .A1(n932), .B0(n931), .Y(n934) );
OAI21X4TS U1664 ( .A0(n957), .A1(n935), .B0(n934), .Y(n948) );
INVX2TS U1665 ( .A(n936), .Y(n946) );
INVX2TS U1666 ( .A(n945), .Y(n937) );
AOI21X4TS U1667 ( .A0(n948), .A1(n946), .B0(n937), .Y(n942) );
INVX2TS U1668 ( .A(n938), .Y(n940) );
NAND2X1TS U1669 ( .A(n940), .B(n939), .Y(n941) );
XNOR2X4TS U1670 ( .A(n942), .B(n941), .Y(n1501) );
BUFX3TS U1671 ( .A(Op_MY[14]), .Y(n1495) );
OAI21X1TS U1672 ( .A0(n1501), .A1(n1399), .B0(n943), .Y(n944) );
XOR2X1TS U1673 ( .A(n944), .B(n430), .Y(mult_x_19_n1151) );
NAND2X1TS U1674 ( .A(n946), .B(n945), .Y(n947) );
XNOR2X4TS U1675 ( .A(n948), .B(n947), .Y(n949) );
INVX2TS U1676 ( .A(n2023), .Y(n1380) );
AOI222X1TS U1677 ( .A0(n1397), .A1(n1374), .B0(n1396), .B1(n1380), .C0(n1450), .C1(n1387), .Y(n950) );
OAI21X1TS U1678 ( .A0(n1376), .A1(n1399), .B0(n950), .Y(n951) );
XOR2X1TS U1679 ( .A(n951), .B(n430), .Y(mult_x_19_n1152) );
INVX2TS U1680 ( .A(n952), .Y(n1242) );
XOR2X1TS U1681 ( .A(n954), .B(n1993), .Y(mult_x_19_n1154) );
OAI21X2TS U1682 ( .A0(n957), .A1(n956), .B0(n955), .Y(n962) );
INVX2TS U1683 ( .A(n958), .Y(n960) );
NAND2X1TS U1684 ( .A(n960), .B(n959), .Y(n961) );
BUFX3TS U1685 ( .A(Op_MY[8]), .Y(n1332) );
AOI222X1TS U1686 ( .A0(n1454), .A1(n1198), .B0(n1452), .B1(n1332), .C0(n1450), .C1(n2028), .Y(n963) );
XOR2X1TS U1687 ( .A(n964), .B(n430), .Y(mult_x_19_n1157) );
AOI222X1TS U1688 ( .A0(n1454), .A1(n1259), .B0(n1396), .B1(n1257), .C0(n1450), .C1(n1283), .Y(n965) );
XOR2X1TS U1689 ( .A(n966), .B(n1993), .Y(mult_x_19_n1159) );
AOI222X1TS U1690 ( .A0(n1397), .A1(n1439), .B0(n1396), .B1(n1519), .C0(n1450), .C1(n1460), .Y(n967) );
OAI21X1TS U1691 ( .A0(n1441), .A1(n1456), .B0(n967), .Y(n968) );
XOR2X1TS U1692 ( .A(n968), .B(n430), .Y(mult_x_19_n1161) );
AOI222X1TS U1693 ( .A0(n1397), .A1(n1481), .B0(n1396), .B1(n1985), .C0(n1450), .C1(n1472), .Y(n969) );
XOR2X1TS U1694 ( .A(n970), .B(Op_MX[20]), .Y(mult_x_19_n1162) );
AOI21X1TS U1695 ( .A0(n1263), .A1(n1209), .B0(n1225), .Y(n971) );
OAI21X1TS U1696 ( .A0(n1211), .A1(n536), .B0(n971), .Y(n972) );
INVX2TS U1697 ( .A(n1184), .Y(n1267) );
XOR2X1TS U1698 ( .A(n972), .B(n1267), .Y(mult_x_19_n1169) );
AOI21X1TS U1699 ( .A0(n1263), .A1(n1326), .B0(n973), .Y(n974) );
OAI21X1TS U1700 ( .A0(n398), .A1(n536), .B0(n974), .Y(n975) );
XOR2X1TS U1701 ( .A(n975), .B(n1267), .Y(mult_x_19_n1170) );
AOI222X1TS U1702 ( .A0(n1265), .A1(n1351), .B0(n1225), .B1(n1350), .C0(n1263), .C1(n2019), .Y(n976) );
CLKBUFX2TS U1703 ( .A(n978), .Y(n1264) );
AOI222X1TS U1704 ( .A0(n1265), .A1(n1205), .B0(n1264), .B1(n1309), .C0(n1263), .C1(n2021), .Y(n979) );
XOR2X1TS U1705 ( .A(n980), .B(n1267), .Y(mult_x_19_n1173) );
AOI222X1TS U1706 ( .A0(n1265), .A1(n1340), .B0(n1264), .B1(n1338), .C0(n1263), .C1(n1336), .Y(n981) );
OAI21X1TS U1707 ( .A0(n1342), .A1(n1330), .B0(n981), .Y(n982) );
XOR2X1TS U1708 ( .A(n982), .B(n1267), .Y(mult_x_19_n1175) );
AOI222X1TS U1709 ( .A0(n1265), .A1(n1251), .B0(n1409), .B1(n1292), .C0(n1263), .C1(n2022), .Y(n983) );
XOR2X1TS U1710 ( .A(n984), .B(n1267), .Y(mult_x_19_n1177) );
AOI222X1TS U1711 ( .A0(n1410), .A1(n1497), .B0(n1409), .B1(n1495), .C0(n1263), .C1(n2024), .Y(n985) );
XOR2X1TS U1712 ( .A(n986), .B(n1413), .Y(mult_x_19_n1178) );
INVX2TS U1713 ( .A(n988), .Y(n989) );
INVX2TS U1714 ( .A(n991), .Y(n993) );
NAND2X1TS U1715 ( .A(n993), .B(n992), .Y(n994) );
XNOR2X4TS U1716 ( .A(n995), .B(n994), .Y(n1383) );
INVX2TS U1717 ( .A(n400), .Y(n1379) );
AOI222X1TS U1718 ( .A0(n1410), .A1(n1493), .B0(n1409), .B1(n1379), .C0(n1224), .C1(n1377), .Y(n996) );
XOR2X1TS U1719 ( .A(n997), .B(n1413), .Y(mult_x_19_n1180) );
AOI222X1TS U1720 ( .A0(n1410), .A1(n1432), .B0(n1225), .B1(n1986), .C0(n1408), .C1(n1357), .Y(n998) );
OAI21X1TS U1721 ( .A0(n401), .A1(n1412), .B0(n998), .Y(n999) );
XOR2X1TS U1722 ( .A(n999), .B(n1413), .Y(mult_x_19_n1187) );
XNOR2X4TS U1723 ( .A(Op_MX[11]), .B(Op_MX[12]), .Y(n1003) );
XOR2X4TS U1724 ( .A(n1459), .B(Op_MX[13]), .Y(n1004) );
NAND2BX4TS U1725 ( .AN(n1003), .B(n1004), .Y(n1207) );
XNOR2X2TS U1726 ( .A(Op_MX[12]), .B(Op_MX[13]), .Y(n1000) );
AND3X4TS U1727 ( .A(n1004), .B(n1003), .C(n1000), .Y(n1177) );
NOR2BX4TS U1728 ( .AN(n1003), .B(n1000), .Y(n1423) );
AOI21X1TS U1729 ( .A0(n1314), .A1(n1209), .B0(n1403), .Y(n1001) );
INVX2TS U1730 ( .A(n2018), .Y(n1319) );
NOR2X8TS U1731 ( .A(n1004), .B(n1003), .Y(n1420) );
BUFX3TS U1732 ( .A(n1420), .Y(n1404) );
AOI21X1TS U1733 ( .A0(n1314), .A1(n1326), .B0(n1005), .Y(n1006) );
XOR2X1TS U1734 ( .A(n1007), .B(n1319), .Y(mult_x_19_n1197) );
AOI222X1TS U1735 ( .A0(n1426), .A1(n1351), .B0(n1403), .B1(n1350), .C0(n1314), .C1(n1205), .Y(n1008) );
XOR2X1TS U1736 ( .A(n1009), .B(n1319), .Y(mult_x_19_n1198) );
AOI222X1TS U1737 ( .A0(n1426), .A1(n1306), .B0(n1423), .B1(n1310), .C0(n1314), .C1(n1316), .Y(n1010) );
OAI21X1TS U1738 ( .A0(n1308), .A1(n1207), .B0(n1010), .Y(n1011) );
XOR2X1TS U1739 ( .A(n1011), .B(n1319), .Y(mult_x_19_n1199) );
AOI222X1TS U1740 ( .A0(n1426), .A1(n1340), .B0(n1423), .B1(n1338), .C0(n1314), .C1(n1251), .Y(n1012) );
OAI21X1TS U1741 ( .A0(n1342), .A1(n1427), .B0(n1012), .Y(n1013) );
XOR2X1TS U1742 ( .A(n1013), .B(n1319), .Y(mult_x_19_n1202) );
AOI222X1TS U1743 ( .A0(n1404), .A1(n1313), .B0(n1419), .B1(n1298), .C0(n1314), .C1(n1497), .Y(n1014) );
XOR2X1TS U1744 ( .A(n1015), .B(n1319), .Y(mult_x_19_n1203) );
AOI222X1TS U1745 ( .A0(n1426), .A1(n1251), .B0(n1419), .B1(n1292), .C0(n1314), .C1(n1374), .Y(n1016) );
XOR2X1TS U1746 ( .A(n1019), .B(n1428), .Y(mult_x_19_n1205) );
AOI222X1TS U1747 ( .A0(n1420), .A1(n1374), .B0(n1419), .B1(n1380), .C0(n1418), .C1(n1387), .Y(n1020) );
OAI21X1TS U1748 ( .A0(n1376), .A1(n1427), .B0(n1020), .Y(n1021) );
XOR2X1TS U1749 ( .A(n1021), .B(n1428), .Y(mult_x_19_n1206) );
BUFX3TS U1750 ( .A(Op_MY[11]), .Y(n1280) );
AOI222X1TS U1751 ( .A0(n1420), .A1(n1493), .B0(n1419), .B1(n1379), .C0(n1177), .C1(n1280), .Y(n1022) );
XOR2X1TS U1752 ( .A(n1023), .B(n1428), .Y(mult_x_19_n1207) );
AOI222X1TS U1753 ( .A0(n1420), .A1(n1432), .B0(n1403), .B1(n1986), .C0(n1418), .C1(n1481), .Y(n1024) );
OAI21X1TS U1754 ( .A0(n401), .A1(n1406), .B0(n1024), .Y(n1025) );
XOR2X1TS U1755 ( .A(n1025), .B(n1428), .Y(mult_x_19_n1214) );
AOI222X1TS U1756 ( .A0(n1420), .A1(n1439), .B0(n1419), .B1(n1519), .C0(n1418), .C1(n1460), .Y(n1026) );
OAI21X1TS U1757 ( .A0(n1441), .A1(n1406), .B0(n1026), .Y(n1027) );
XOR2X1TS U1758 ( .A(n1027), .B(n1428), .Y(mult_x_19_n1215) );
XNOR2X4TS U1759 ( .A(Op_MX[8]), .B(Op_MX[9]), .Y(n1030) );
XOR2X4TS U1760 ( .A(n1694), .B(Op_MX[10]), .Y(n1031) );
NAND2BX4TS U1761 ( .AN(n1030), .B(n1031), .Y(n1051) );
XNOR2X2TS U1762 ( .A(Op_MX[9]), .B(Op_MX[10]), .Y(n1029) );
AND3X4TS U1763 ( .A(n1031), .B(n1030), .C(n1029), .Y(n1279) );
INVX6TS U1764 ( .A(n1279), .Y(n1048) );
INVX4TS U1765 ( .A(n1048), .Y(n1337) );
NOR2BX4TS U1766 ( .AN(n1030), .B(n1029), .Y(n1041) );
NOR2X8TS U1767 ( .A(n1031), .B(n1030), .Y(n1482) );
AO21X1TS U1768 ( .A0(n1465), .A1(n1324), .B0(n1463), .Y(n1032) );
AOI21X1TS U1769 ( .A0(n1337), .A1(n1326), .B0(n1032), .Y(n1033) );
INVX2TS U1770 ( .A(n1285), .Y(n1343) );
XOR2X1TS U1771 ( .A(n1034), .B(n1343), .Y(mult_x_19_n1224) );
AOI222X1TS U1772 ( .A0(n1463), .A1(n1351), .B0(n1465), .B1(n1350), .C0(n1337), .C1(n2019), .Y(n1035) );
XOR2X1TS U1773 ( .A(n1036), .B(n1343), .Y(mult_x_19_n1225) );
CLKBUFX2TS U1774 ( .A(n1041), .Y(n1339) );
AOI222X1TS U1775 ( .A0(n1463), .A1(n1306), .B0(n1339), .B1(n1310), .C0(n1337), .C1(n2020), .Y(n1037) );
XOR2X1TS U1776 ( .A(n1038), .B(n1343), .Y(mult_x_19_n1226) );
AOI222X1TS U1777 ( .A0(n1463), .A1(n1205), .B0(n1339), .B1(n1309), .C0(n1337), .C1(n2021), .Y(n1039) );
OAI21X1TS U1778 ( .A0(n1312), .A1(n1051), .B0(n1039), .Y(n1040) );
XOR2X1TS U1779 ( .A(n1040), .B(n1343), .Y(mult_x_19_n1227) );
AOI222X1TS U1780 ( .A0(n1060), .A1(n1313), .B0(n1480), .B1(n1298), .C0(n1337), .C1(n1297), .Y(n1042) );
XOR2X1TS U1781 ( .A(n1043), .B(n1343), .Y(mult_x_19_n1230) );
AOI222X1TS U1782 ( .A0(n1463), .A1(n1251), .B0(n1480), .B1(n1292), .C0(n1337), .C1(n2022), .Y(n1044) );
OAI21X1TS U1783 ( .A0(n1291), .A1(n1474), .B0(n1044), .Y(n1045) );
XOR2X1TS U1784 ( .A(n1045), .B(n1343), .Y(mult_x_19_n1231) );
AOI222X1TS U1785 ( .A0(n1060), .A1(n1497), .B0(n1480), .B1(n1495), .C0(n1337), .C1(n2024), .Y(n1046) );
OAI21X1TS U1786 ( .A0(n1501), .A1(n1474), .B0(n1046), .Y(n1047) );
CLKINVX3TS U1787 ( .A(n1285), .Y(n1485) );
XOR2X1TS U1788 ( .A(n1047), .B(n1485), .Y(mult_x_19_n1232) );
AOI222X1TS U1789 ( .A0(n1482), .A1(n1374), .B0(n1480), .B1(n1380), .C0(n1479), .C1(n2025), .Y(n1049) );
XOR2X1TS U1790 ( .A(n1050), .B(n1485), .Y(mult_x_19_n1233) );
AOI222X1TS U1791 ( .A0(n1482), .A1(n1387), .B0(n1465), .B1(n1987), .C0(n1279), .C1(n1368), .Y(n1052) );
OAI21X1TS U1792 ( .A0(n1391), .A1(n1484), .B0(n1052), .Y(n1053) );
XOR2X1TS U1793 ( .A(n1053), .B(n1694), .Y(mult_x_19_n1235) );
BUFX3TS U1794 ( .A(Op_MY[10]), .Y(n1304) );
AOI222X1TS U1795 ( .A0(n1060), .A1(n1304), .B0(n1465), .B1(n1367), .C0(n1479), .C1(n2026), .Y(n1054) );
OAI21X1TS U1796 ( .A0(n1371), .A1(n1484), .B0(n1054), .Y(n1055) );
XOR2X1TS U1797 ( .A(n1055), .B(n1694), .Y(mult_x_19_n1237) );
AOI222X1TS U1798 ( .A0(n1060), .A1(n1198), .B0(n1465), .B1(n1332), .C0(n1479), .C1(n2028), .Y(n1056) );
OAI21X1TS U1799 ( .A0(n392), .A1(n1484), .B0(n1056), .Y(n1057) );
XOR2X1TS U1800 ( .A(n1057), .B(n1694), .Y(mult_x_19_n1238) );
AOI222X1TS U1801 ( .A0(n1060), .A1(n1453), .B0(n1465), .B1(n1451), .C0(n1479), .C1(n2030), .Y(n1058) );
OAI21X1TS U1802 ( .A0(n402), .A1(n1484), .B0(n1058), .Y(n1059) );
AOI222X1TS U1803 ( .A0(n1060), .A1(n1259), .B0(n1480), .B1(n1257), .C0(n1479), .C1(n1283), .Y(n1061) );
XOR2X1TS U1804 ( .A(n1062), .B(n1694), .Y(mult_x_19_n1240) );
AOI222X1TS U1805 ( .A0(n1482), .A1(n1432), .B0(n1465), .B1(n1986), .C0(n1479), .C1(n1357), .Y(n1063) );
XOR2X1TS U1806 ( .A(n1064), .B(n1485), .Y(mult_x_19_n1241) );
AOI21X1TS U1807 ( .A0(n1349), .A1(n1209), .B0(n1433), .Y(n1065) );
OAI21X1TS U1808 ( .A0(n1211), .A1(n1354), .B0(n1065), .Y(n1066) );
INVX2TS U1809 ( .A(n396), .Y(n1355) );
XOR2X1TS U1810 ( .A(n1066), .B(n1355), .Y(mult_x_19_n1250) );
AOI21X1TS U1811 ( .A0(n1349), .A1(n1306), .B0(n1067), .Y(n1068) );
OAI21X1TS U1812 ( .A0(n398), .A1(n1354), .B0(n1068), .Y(n1069) );
XOR2X1TS U1813 ( .A(n1069), .B(n1355), .Y(mult_x_19_n1251) );
CLKBUFX2TS U1814 ( .A(n1070), .Y(n1286) );
AOI222X1TS U1815 ( .A0(n1352), .A1(n1306), .B0(n1286), .B1(n1310), .C0(n1349), .C1(n2020), .Y(n1071) );
XOR2X1TS U1816 ( .A(n1072), .B(n1355), .Y(mult_x_19_n1253) );
AOI222X1TS U1817 ( .A0(n1352), .A1(n1205), .B0(n1286), .B1(n1309), .C0(n1349), .C1(n2021), .Y(n1073) );
OAI21X1TS U1818 ( .A0(n1312), .A1(n1354), .B0(n1073), .Y(n1074) );
XOR2X1TS U1819 ( .A(n1074), .B(n1355), .Y(mult_x_19_n1254) );
AOI222X1TS U1820 ( .A0(n1239), .A1(n1313), .B0(n1258), .B1(n1298), .C0(n1349), .C1(n1297), .Y(n1075) );
OAI21X1TS U1821 ( .A0(n405), .A1(n1288), .B0(n1075), .Y(n1076) );
XOR2X1TS U1822 ( .A(n1076), .B(n1355), .Y(mult_x_19_n1257) );
AOI222X1TS U1823 ( .A0(n1352), .A1(n1251), .B0(n1258), .B1(n1292), .C0(n1349), .C1(n2022), .Y(n1077) );
XOR2X1TS U1824 ( .A(n1078), .B(n1355), .Y(mult_x_19_n1258) );
AOI222X1TS U1825 ( .A0(n1239), .A1(n1497), .B0(n1258), .B1(n1495), .C0(n1349), .C1(n2024), .Y(n1079) );
XOR2X1TS U1826 ( .A(n1080), .B(n431), .Y(mult_x_19_n1259) );
AOI222X1TS U1827 ( .A0(n1239), .A1(n1374), .B0(n1258), .B1(n1380), .C0(n435),
.C1(n2025), .Y(n1081) );
OAI21X1TS U1828 ( .A0(n1376), .A1(n1288), .B0(n1081), .Y(n1082) );
AOI222X1TS U1829 ( .A0(n1434), .A1(n1493), .B0(n1258), .B1(n1379), .C0(n436),
.C1(n1377), .Y(n1083) );
XOR2X1TS U1830 ( .A(n1084), .B(n431), .Y(mult_x_19_n1261) );
AOI222X1TS U1831 ( .A0(n1239), .A1(n1439), .B0(n1258), .B1(n1519), .C0(n436),
.C1(n1438), .Y(n1085) );
XOR2X1TS U1832 ( .A(n1086), .B(n431), .Y(mult_x_19_n1269) );
AOI21X1TS U1833 ( .A0(n1119), .A1(n1324), .B0(n1359), .Y(n1089) );
INVX2TS U1834 ( .A(n1284), .Y(n1117) );
XOR2X1TS U1835 ( .A(n1090), .B(n1117), .Y(mult_x_19_n1277) );
AOI21X1TS U1836 ( .A0(n1119), .A1(n1306), .B0(n1091), .Y(n1092) );
OAI21X1TS U1837 ( .A0(n398), .A1(n1362), .B0(n1092), .Y(n1093) );
XOR2X1TS U1838 ( .A(n1093), .B(n1117), .Y(mult_x_19_n1278) );
AOI222X1TS U1839 ( .A0(n1136), .A1(n1351), .B0(n1359), .B1(n1350), .C0(n1119), .C1(n2019), .Y(n1094) );
OAI21X1TS U1840 ( .A0(n404), .A1(n1362), .B0(n1094), .Y(n1095) );
CLKBUFX2TS U1841 ( .A(n1359), .Y(n1111) );
AOI222X1TS U1842 ( .A0(n1136), .A1(n1306), .B0(n1111), .B1(n1310), .C0(n1119), .C1(n2020), .Y(n1096) );
OAI21X1TS U1843 ( .A0(n1308), .A1(n1362), .B0(n1096), .Y(n1097) );
XOR2X1TS U1844 ( .A(n1097), .B(n1117), .Y(mult_x_19_n1280) );
AOI222X1TS U1845 ( .A0(n1136), .A1(n1205), .B0(n1111), .B1(n1309), .C0(n1119), .C1(n2021), .Y(n1098) );
OAI21X1TS U1846 ( .A0(n1312), .A1(n1362), .B0(n1098), .Y(n1099) );
XOR2X1TS U1847 ( .A(n1099), .B(n1117), .Y(mult_x_19_n1281) );
INVX2TS U1848 ( .A(n1100), .Y(n1101) );
INVX2TS U1849 ( .A(n1104), .Y(n1106) );
NAND2X1TS U1850 ( .A(n1106), .B(n1105), .Y(n1107) );
XNOR2X4TS U1851 ( .A(n1108), .B(n1107), .Y(n1318) );
AOI222X1TS U1852 ( .A0(n1136), .A1(n1316), .B0(n1111), .B1(n1315), .C0(n1119), .C1(n1300), .Y(n1109) );
OAI21X1TS U1853 ( .A0(n1318), .A1(n1347), .B0(n1109), .Y(n1110) );
XOR2X1TS U1854 ( .A(n1110), .B(n1117), .Y(mult_x_19_n1282) );
AOI222X1TS U1855 ( .A0(n1136), .A1(n1340), .B0(n1111), .B1(n1338), .C0(n1119), .C1(n1336), .Y(n1112) );
OAI21X1TS U1856 ( .A0(n1342), .A1(n1347), .B0(n1112), .Y(n1113) );
XOR2X1TS U1857 ( .A(n1113), .B(n1117), .Y(mult_x_19_n1283) );
AOI222X1TS U1858 ( .A0(n1360), .A1(n1313), .B0(n1345), .B1(n1298), .C0(n1119), .C1(n1297), .Y(n1114) );
XOR2X1TS U1859 ( .A(n1115), .B(n1117), .Y(mult_x_19_n1284) );
AOI222X1TS U1860 ( .A0(n1136), .A1(n1251), .B0(n1345), .B1(n1292), .C0(n1119), .C1(n2022), .Y(n1116) );
OAI21X1TS U1861 ( .A0(n1291), .A1(n1347), .B0(n1116), .Y(n1118) );
AOI222X1TS U1862 ( .A0(n1360), .A1(n1497), .B0(n1345), .B1(n1495), .C0(n1119), .C1(n2024), .Y(n1120) );
OAI21X1TS U1863 ( .A0(n1501), .A1(n1347), .B0(n1120), .Y(n1121) );
XOR2X1TS U1864 ( .A(n1121), .B(n1363), .Y(mult_x_19_n1286) );
INVX2TS U1865 ( .A(n1122), .Y(n1276) );
AOI222X1TS U1866 ( .A0(n1360), .A1(n1387), .B0(n1359), .B1(n1987), .C0(n1276), .C1(n1384), .Y(n1123) );
XOR2X1TS U1867 ( .A(n1124), .B(n1695), .Y(mult_x_19_n1289) );
INVX2TS U1868 ( .A(n1125), .Y(n1126) );
NAND2X1TS U1869 ( .A(n1131), .B(n1130), .Y(n1132) );
AOI222X1TS U1870 ( .A0(n1136), .A1(n1280), .B0(n1359), .B1(n1304), .C0(n1276), .C1(n1198), .Y(n1134) );
XOR2X1TS U1871 ( .A(n1135), .B(n1695), .Y(mult_x_19_n1290) );
AOI222X1TS U1872 ( .A0(n1272), .A1(n1368), .B0(n1359), .B1(n1367), .C0(n1358), .C1(n1453), .Y(n1137) );
XOR2X1TS U1873 ( .A(n1138), .B(n1695), .Y(mult_x_19_n1291) );
AOI222X1TS U1874 ( .A0(n1272), .A1(n1198), .B0(n1359), .B1(n1332), .C0(n1358), .C1(n1259), .Y(n1139) );
XOR2X1TS U1875 ( .A(n1140), .B(n1695), .Y(mult_x_19_n1292) );
AOI222X1TS U1876 ( .A0(n1272), .A1(n1259), .B0(n1345), .B1(n1257), .C0(n1358), .C1(n1439), .Y(n1141) );
XOR2X1TS U1877 ( .A(n1142), .B(n1695), .Y(mult_x_19_n1294) );
INVX4TS U1878 ( .A(n480), .Y(n1494) );
AOI21X1TS U1879 ( .A0(n1494), .A1(n1324), .B0(n1386), .Y(n1144) );
XOR2X1TS U1880 ( .A(n1145), .B(n1150), .Y(mult_x_19_n1304) );
AOI21X1TS U1881 ( .A0(n1494), .A1(n1326), .B0(n1146), .Y(n1147) );
XOR2X1TS U1882 ( .A(n1148), .B(n1150), .Y(mult_x_19_n1305) );
AOI222X1TS U1883 ( .A0(n1498), .A1(n1351), .B0(n1386), .B1(n1350), .C0(n1494), .C1(n1205), .Y(n1149) );
XOR2X1TS U1884 ( .A(n1151), .B(n1150), .Y(mult_x_19_n1306) );
CLKBUFX2TS U1885 ( .A(n1152), .Y(n1252) );
AOI222X1TS U1886 ( .A0(n1498), .A1(n1306), .B0(n1252), .B1(n1310), .C0(n1494), .C1(n1316), .Y(n1153) );
OAI21X1TS U1887 ( .A0(n1308), .A1(n1143), .B0(n1153), .Y(n1154) );
XOR2X1TS U1888 ( .A(n1154), .B(n1502), .Y(mult_x_19_n1307) );
AOI222X1TS U1889 ( .A0(n1498), .A1(n1205), .B0(n1252), .B1(n1309), .C0(n1494), .C1(n1340), .Y(n1155) );
OAI21X1TS U1890 ( .A0(n1312), .A1(n1143), .B0(n1155), .Y(n1156) );
AOI222X1TS U1891 ( .A0(n1498), .A1(n1251), .B0(n1496), .B1(n1292), .C0(n1494), .C1(n1374), .Y(n1157) );
XOR2X1TS U1892 ( .A(n1158), .B(n1502), .Y(mult_x_19_n1312) );
INVX2TS U1893 ( .A(n480), .Y(n1385) );
AOI222X1TS U1894 ( .A0(n1498), .A1(n1280), .B0(n1386), .B1(n1304), .C0(n1385), .C1(n1198), .Y(n1159) );
XOR2X1TS U1895 ( .A(n1160), .B(n1392), .Y(mult_x_19_n1317) );
AOI222X1TS U1896 ( .A0(n1369), .A1(n1198), .B0(n1386), .B1(n1332), .C0(n1373), .C1(n1259), .Y(n1161) );
XOR2X1TS U1897 ( .A(n1162), .B(n1392), .Y(mult_x_19_n1319) );
AOI222X1TS U1898 ( .A0(n1217), .A1(n1453), .B0(n1225), .B1(n1451), .C0(n1408), .C1(n2030), .Y(n1163) );
OAI21X1TS U1899 ( .A0(n402), .A1(n1412), .B0(n1163), .Y(n1164) );
XOR2X1TS U1900 ( .A(n1164), .B(n1685), .Y(mult_x_19_n1185) );
AOI222X1TS U1901 ( .A0(n1410), .A1(n1387), .B0(n1225), .B1(n1987), .C0(n1224), .C1(n1368), .Y(n1165) );
OAI21X1TS U1902 ( .A0(n1391), .A1(n1412), .B0(n1165), .Y(n1166) );
XOR2X1TS U1903 ( .A(n1166), .B(n1685), .Y(mult_x_19_n1181) );
AOI222X1TS U1904 ( .A0(n1217), .A1(n1198), .B0(n1225), .B1(n1332), .C0(n1408), .C1(n2028), .Y(n1167) );
OAI21X1TS U1905 ( .A0(n392), .A1(n1412), .B0(n1167), .Y(n1168) );
XOR2X1TS U1906 ( .A(n1168), .B(n1685), .Y(mult_x_19_n1184) );
AOI222X1TS U1907 ( .A0(n1265), .A1(n1259), .B0(n1409), .B1(n1257), .C0(n1408), .C1(n1283), .Y(n1169) );
XOR2X1TS U1908 ( .A(n1170), .B(n1685), .Y(mult_x_19_n1186) );
AOI222X1TS U1909 ( .A0(n1404), .A1(n1259), .B0(n1419), .B1(n1257), .C0(n1418), .C1(n1283), .Y(n1171) );
OAI21X1TS U1910 ( .A0(n1261), .A1(n1406), .B0(n1171), .Y(n1172) );
XOR2X1TS U1911 ( .A(n1172), .B(n1459), .Y(mult_x_19_n1213) );
AOI222X1TS U1912 ( .A0(n1420), .A1(n1387), .B0(n1403), .B1(n1987), .C0(n1177), .C1(n1368), .Y(n1173) );
XOR2X1TS U1913 ( .A(n1174), .B(n1459), .Y(mult_x_19_n1208) );
AOI222X1TS U1914 ( .A0(n1404), .A1(n1198), .B0(n1403), .B1(n1332), .C0(n1418), .C1(n2028), .Y(n1175) );
XOR2X1TS U1915 ( .A(n1176), .B(n1459), .Y(mult_x_19_n1211) );
AOI222X1TS U1916 ( .A0(n1426), .A1(n1280), .B0(n1403), .B1(n1304), .C0(n1177), .C1(n1686), .Y(n1178) );
OAI21X1TS U1917 ( .A0(n403), .A1(n1406), .B0(n1178), .Y(n1179) );
XOR2X1TS U1918 ( .A(n1179), .B(n1459), .Y(mult_x_19_n1209) );
AOI222X1TS U1919 ( .A0(n1404), .A1(n1368), .B0(n1403), .B1(n1367), .C0(n1418), .C1(n2026), .Y(n1180) );
XOR2X1TS U1920 ( .A(n1181), .B(n1459), .Y(mult_x_19_n1210) );
OAI21X1TS U1921 ( .A0(n1196), .A1(n1207), .B0(n1182), .Y(n1183) );
XOR2X1TS U1922 ( .A(n1183), .B(n1459), .Y(mult_x_19_n1195) );
CMPR32X2TS U1923 ( .A(n1184), .B(n1297), .C(n1300), .CO(mult_x_19_n582), .S(
mult_x_19_n583) );
AOI222X1TS U1924 ( .A0(n1520), .A1(n1257), .B0(n1333), .B1(n1986), .C0(n1517), .C1(n1357), .Y(n1185) );
CMPR32X2TS U1925 ( .A(Op_MX[2]), .B(n1438), .C(n1186), .CO(mult_x_19_n702),
.S(mult_x_19_n703) );
AOI222X1TS U1926 ( .A0(n1334), .A1(n1451), .B0(n1518), .B1(n1257), .C0(n1517), .C1(n1439), .Y(n1187) );
CMPR32X2TS U1927 ( .A(Op_MX[2]), .B(n1357), .C(n408), .CO(mult_x_19_n691),
.S(mult_x_19_n692) );
AOI222X1TS U1928 ( .A0(n1369), .A1(n1493), .B0(n1496), .B1(n1379), .C0(n1385), .C1(n1280), .Y(n1189) );
XOR2X1TS U1929 ( .A(n1190), .B(n1150), .Y(mult_x_19_n1315) );
AOI222X1TS U1930 ( .A0(n1434), .A1(n1368), .B0(n1433), .B1(n1367), .C0(n436),
.C1(n1453), .Y(n1191) );
XOR2X1TS U1931 ( .A(n1192), .B(n1997), .Y(mult_x_19_n1264) );
AOI222X1TS U1932 ( .A0(n1434), .A1(n1198), .B0(n1433), .B1(n1332), .C0(n436),
.C1(n1259), .Y(n1193) );
XOR2X1TS U1933 ( .A(n1194), .B(n1997), .Y(mult_x_19_n1265) );
XOR2X1TS U1934 ( .A(n1197), .B(n1997), .Y(mult_x_19_n1249) );
AOI222X1TS U1935 ( .A0(n1352), .A1(n1280), .B0(n1433), .B1(n1304), .C0(n436),
.C1(n1198), .Y(n1199) );
XOR2X1TS U1936 ( .A(n1200), .B(n1997), .Y(mult_x_19_n1263) );
AOI222X1TS U1937 ( .A0(n1498), .A1(n1316), .B0(n1252), .B1(n1315), .C0(n1494), .C1(n1313), .Y(n1201) );
OAI21X1TS U1938 ( .A0(n1318), .A1(n1500), .B0(n1201), .Y(n1202) );
XOR2X1TS U1939 ( .A(n1202), .B(n1502), .Y(mult_x_19_n1309) );
AOI222X1TS U1940 ( .A0(n1410), .A1(n1313), .B0(n1409), .B1(n1298), .C0(n1263), .C1(n1297), .Y(n1203) );
XOR2X1TS U1941 ( .A(n1204), .B(n1267), .Y(mult_x_19_n1176) );
AOI222X1TS U1942 ( .A0(n1426), .A1(n1205), .B0(n1403), .B1(n1309), .C0(n1314), .C1(n1340), .Y(n1206) );
XOR2X1TS U1943 ( .A(n1208), .B(n1319), .Y(mult_x_19_n1200) );
AOI21X1TS U1944 ( .A0(n1337), .A1(n1209), .B0(n1465), .Y(n1210) );
XOR2X1TS U1945 ( .A(n1212), .B(n1343), .Y(mult_x_19_n1223) );
OAI21X1TS U1946 ( .A0(n1513), .A1(n1406), .B0(n1213), .Y(n1214) );
XOR2X1TS U1947 ( .A(n1214), .B(n1428), .Y(mult_x_19_n1217) );
AOI222X1TS U1948 ( .A0(n1239), .A1(n1460), .B0(n1258), .B1(n1984), .C0(n435),
.C1(n1510), .Y(n1215) );
OAI21X1TS U1949 ( .A0(n1513), .A1(n1436), .B0(n1215), .Y(n1216) );
XOR2X1TS U1950 ( .A(n1216), .B(n1997), .Y(mult_x_19_n1271) );
AOI222X1TS U1951 ( .A0(n1217), .A1(n1368), .B0(n1225), .B1(n1367), .C0(n1408), .C1(n2026), .Y(n1218) );
OAI21X1TS U1952 ( .A0(n1371), .A1(n1412), .B0(n1218), .Y(n1219) );
XOR2X1TS U1953 ( .A(n1219), .B(n1685), .Y(mult_x_19_n1183) );
AOI222X1TS U1954 ( .A0(n1397), .A1(n1432), .B0(n1452), .B1(n1986), .C0(n1450), .C1(n1481), .Y(n1220) );
OAI21X1TS U1955 ( .A0(n401), .A1(n1456), .B0(n1220), .Y(n1221) );
XOR2X1TS U1956 ( .A(n1221), .B(Op_MX[20]), .Y(mult_x_19_n1160) );
XOR2X1TS U1957 ( .A(n1223), .B(n1993), .Y(mult_x_19_n1155) );
AOI222X1TS U1958 ( .A0(n1265), .A1(n1280), .B0(n1225), .B1(n1304), .C0(n1224), .C1(n1686), .Y(n1226) );
OAI21X1TS U1959 ( .A0(n403), .A1(n1412), .B0(n1226), .Y(n1227) );
XOR2X1TS U1960 ( .A(n1227), .B(n1685), .Y(mult_x_19_n1182) );
AOI222X1TS U1961 ( .A0(n1520), .A1(n1986), .B0(n1518), .B1(n1519), .C0(n1517), .C1(n1438), .Y(n1228) );
OA21X4TS U1962 ( .A0(n1441), .A1(n1522), .B0(n1228), .Y(n1229) );
CMPR32X2TS U1963 ( .A(Op_MX[2]), .B(n1516), .C(n1229), .CO(mult_x_19_n713),
.S(mult_x_19_n714) );
INVX2TS U1964 ( .A(n1522), .Y(n1232) );
AOI222X1TS U1965 ( .A0(n1520), .A1(n1379), .B0(n1333), .B1(n1987), .C0(n1378), .C1(n1384), .Y(n1230) );
INVX2TS U1966 ( .A(n1230), .Y(n1231) );
CMPR32X2TS U1967 ( .A(n1384), .B(n1505), .C(n1234), .CO(mult_x_19_n630), .S(
mult_x_19_n631) );
AOI222X1TS U1968 ( .A0(n1265), .A1(n1316), .B0(n1264), .B1(n1315), .C0(n1263), .C1(n1300), .Y(n1235) );
OAI21X1TS U1969 ( .A0(n1318), .A1(n1330), .B0(n1235), .Y(n1236) );
XOR2X1TS U1970 ( .A(n1236), .B(n1267), .Y(mult_x_19_n1174) );
AOI222X1TS U1971 ( .A0(n1352), .A1(n1340), .B0(n1286), .B1(n1338), .C0(n1349), .C1(n1336), .Y(n1237) );
OAI21X1TS U1972 ( .A0(n1342), .A1(n1288), .B0(n1237), .Y(n1238) );
XOR2X1TS U1973 ( .A(n1238), .B(n1355), .Y(mult_x_19_n1256) );
AOI222X1TS U1974 ( .A0(n1239), .A1(n1432), .B0(n1433), .B1(n1986), .C0(n436),
.C1(n1357), .Y(n1240) );
XOR2X1TS U1975 ( .A(n1241), .B(n431), .Y(mult_x_19_n1268) );
XOR2X1TS U1976 ( .A(n1244), .B(Op_MX[20]), .Y(mult_x_19_n1153) );
AOI222X1TS U1977 ( .A0(n1369), .A1(n1313), .B0(n1496), .B1(n1298), .C0(n1494), .C1(n1497), .Y(n1245) );
XOR2X1TS U1978 ( .A(n1246), .B(n1502), .Y(mult_x_19_n1311) );
AOI222X1TS U1979 ( .A0(n1463), .A1(n1493), .B0(n1480), .B1(n1379), .C0(n1279), .C1(n1377), .Y(n1247) );
XOR2X1TS U1980 ( .A(n1248), .B(n1485), .Y(mult_x_19_n1234) );
AOI222X1TS U1981 ( .A0(n1434), .A1(n1481), .B0(n1258), .B1(n1985), .C0(n435),
.C1(n1516), .Y(n1249) );
XOR2X1TS U1982 ( .A(n1250), .B(n431), .Y(mult_x_19_n1270) );
AOI222X1TS U1983 ( .A0(n1498), .A1(n1340), .B0(n1252), .B1(n1338), .C0(n1494), .C1(n1251), .Y(n1253) );
OAI21X1TS U1984 ( .A0(n1342), .A1(n1500), .B0(n1253), .Y(n1254) );
XOR2X1TS U1985 ( .A(n1254), .B(n1502), .Y(mult_x_19_n1310) );
AOI222X1TS U1986 ( .A0(n1420), .A1(n1481), .B0(n1419), .B1(n1985), .C0(n1418), .C1(n1472), .Y(n1255) );
XOR2X1TS U1987 ( .A(n1256), .B(n1428), .Y(mult_x_19_n1216) );
AOI222X1TS U1988 ( .A0(n1434), .A1(n1259), .B0(n1258), .B1(n1257), .C0(n436),
.C1(n1283), .Y(n1260) );
XOR2X1TS U1989 ( .A(n1262), .B(n1997), .Y(mult_x_19_n1267) );
AOI222X1TS U1990 ( .A0(n1265), .A1(n1306), .B0(n1264), .B1(n1310), .C0(n1263), .C1(n2020), .Y(n1266) );
AOI222X1TS U1991 ( .A0(n1269), .A1(n1316), .B0(n917), .B1(n1315), .C0(n504),
.C1(n1313), .Y(n1270) );
OAI21X1TS U1992 ( .A0(n1318), .A1(n1399), .B0(n1270), .Y(n1271) );
XOR2X1TS U1993 ( .A(n1271), .B(Op_MX[20]), .Y(mult_x_19_n1147) );
AOI222X1TS U1994 ( .A0(n1272), .A1(n1453), .B0(n1359), .B1(n1451), .C0(n1358), .C1(n1432), .Y(n1273) );
XOR2X1TS U1995 ( .A(n1275), .B(n1695), .Y(mult_x_19_n1293) );
AOI222X1TS U1996 ( .A0(n1360), .A1(n1493), .B0(n1345), .B1(n1379), .C0(n1276), .C1(n1377), .Y(n1277) );
XOR2X1TS U1997 ( .A(n1278), .B(n1363), .Y(mult_x_19_n1288) );
AOI222X1TS U1998 ( .A0(n1463), .A1(n1280), .B0(n1465), .B1(n1304), .C0(n1279), .C1(n1686), .Y(n1281) );
XOR2X1TS U1999 ( .A(n1282), .B(n1694), .Y(mult_x_19_n1236) );
CMPR32X2TS U2000 ( .A(n1284), .B(n485), .C(n1283), .CO(mult_x_19_n680), .S(
mult_x_19_n681) );
CMPR32X2TS U2001 ( .A(n1285), .B(n1686), .C(n1377), .CO(mult_x_19_n622), .S(
mult_x_19_n623) );
AOI222X1TS U2002 ( .A0(n1352), .A1(n1316), .B0(n1286), .B1(n1315), .C0(n1349), .C1(n1300), .Y(n1287) );
XOR2X1TS U2003 ( .A(n1289), .B(n1355), .Y(mult_x_19_n1255) );
AOI222X1TS U2004 ( .A0(n1323), .A1(n1298), .B0(n1518), .B1(n1292), .C0(n1327), .C1(n2022), .Y(n1290) );
AOI222X1TS U2005 ( .A0(n1520), .A1(n1292), .B0(n1518), .B1(n1495), .C0(n1327), .C1(n2024), .Y(n1293) );
AOI222X1TS U2006 ( .A0(n1463), .A1(n1316), .B0(n1339), .B1(n1315), .C0(n1337), .C1(n1300), .Y(n1294) );
XOR2X1TS U2007 ( .A(n1295), .B(n1343), .Y(mult_x_19_n1228) );
AOI222X1TS U2008 ( .A0(n1520), .A1(n1495), .B0(n1518), .B1(n1380), .C0(n1517), .C1(n2025), .Y(n1296) );
AOI222X1TS U2009 ( .A0(n1520), .A1(n1338), .B0(n1518), .B1(n1298), .C0(n1327), .C1(n1297), .Y(n1299) );
AOI222X1TS U2010 ( .A0(n1323), .A1(n1309), .B0(n843), .B1(n1315), .C0(n1327),
.C1(n1300), .Y(n1301) );
AOI222X1TS U2011 ( .A0(n1334), .A1(n1332), .B0(n1333), .B1(n1451), .C0(n1517), .C1(n2030), .Y(n1302) );
AOI222X1TS U2012 ( .A0(n1334), .A1(n1368), .B0(n1333), .B1(n1367), .C0(n1517), .C1(n2026), .Y(n1303) );
AOI222X1TS U2013 ( .A0(n1323), .A1(n1987), .B0(n1333), .B1(n1304), .C0(n1378), .C1(n1686), .Y(n1305) );
AOI222X1TS U2014 ( .A0(n1323), .A1(n1306), .B0(n843), .B1(n1310), .C0(n1327),
.C1(n2020), .Y(n1307) );
AOI222X1TS U2015 ( .A0(n1323), .A1(n1310), .B0(n843), .B1(n1309), .C0(n1327),
.C1(n2021), .Y(n1311) );
AOI222X1TS U2016 ( .A0(n1426), .A1(n1316), .B0(n1423), .B1(n1315), .C0(n1314), .C1(n1313), .Y(n1317) );
OAI21X1TS U2017 ( .A0(n1318), .A1(n1427), .B0(n1317), .Y(n1320) );
XOR2X1TS U2018 ( .A(n1320), .B(n1319), .Y(mult_x_19_n1201) );
ADDHX1TS U2019 ( .A(n1685), .B(n1321), .CO(n846), .S(mult_x_19_n823) );
AOI222X1TS U2020 ( .A0(n1323), .A1(n1351), .B0(n1333), .B1(n1350), .C0(n1327), .C1(n2019), .Y(n1322) );
AOI21X1TS U2021 ( .A0(n1327), .A1(n1326), .B0(n1325), .Y(n1328) );
AOI222X1TS U2022 ( .A0(n1410), .A1(n1374), .B0(n1409), .B1(n1380), .C0(n1408), .C1(n2025), .Y(n1329) );
OAI21X1TS U2023 ( .A0(n1376), .A1(n1330), .B0(n1329), .Y(n1331) );
AOI222X1TS U2024 ( .A0(n1334), .A1(n1367), .B0(n1333), .B1(n1332), .C0(n1517), .C1(n2028), .Y(n1335) );
AOI222X1TS U2025 ( .A0(n1463), .A1(n1340), .B0(n1339), .B1(n1338), .C0(n1337), .C1(n1336), .Y(n1341) );
OAI21X2TS U2026 ( .A0(n1342), .A1(n1474), .B0(n1341), .Y(n1344) );
AOI222X1TS U2027 ( .A0(n1360), .A1(n1374), .B0(n1345), .B1(n1380), .C0(n1358), .C1(n2025), .Y(n1346) );
OAI21X1TS U2028 ( .A0(n1376), .A1(n1347), .B0(n1346), .Y(n1348) );
XOR2X1TS U2029 ( .A(n1348), .B(n1363), .Y(mult_x_19_n1287) );
AOI222X1TS U2030 ( .A0(n1352), .A1(n1351), .B0(n1433), .B1(n1350), .C0(n1349), .C1(n2019), .Y(n1353) );
AOI222X1TS U2031 ( .A0(n1360), .A1(n1432), .B0(n1359), .B1(n1986), .C0(n1358), .C1(n1357), .Y(n1361) );
AOI222X1TS U2032 ( .A0(n1397), .A1(n1460), .B0(n1396), .B1(n1984), .C0(n1450), .C1(n1510), .Y(n1365) );
OAI21X1TS U2033 ( .A0(n1513), .A1(n1456), .B0(n1365), .Y(n1366) );
XOR2X1TS U2034 ( .A(n1372), .B(n1392), .Y(mult_x_19_n1318) );
AOI222X1TS U2035 ( .A0(n1388), .A1(n1374), .B0(n1496), .B1(n1380), .C0(n1373), .C1(n1387), .Y(n1375) );
AOI222X1TS U2036 ( .A0(n1520), .A1(n1380), .B0(n1518), .B1(n1379), .C0(n1378), .C1(n1377), .Y(n1381) );
AOI222X1TS U2037 ( .A0(n1388), .A1(n1387), .B0(n1386), .B1(n1987), .C0(n1385), .C1(n1384), .Y(n1389) );
XOR2X1TS U2038 ( .A(n1393), .B(n1392), .Y(mult_x_19_n1316) );
CMPR22X2TS U2039 ( .A(n1395), .B(n1394), .CO(n1402), .S(n540) );
XOR2X4TS U2040 ( .A(n1400), .B(n430), .Y(n1401) );
CMPR22X2TS U2041 ( .A(n1402), .B(n1401), .CO(mult_x_19_n778), .S(n1417) );
AOI222X1TS U2042 ( .A0(n1404), .A1(n1453), .B0(n1403), .B1(n1451), .C0(n1418), .C1(n2030), .Y(n1405) );
AOI222X1TS U2043 ( .A0(n1410), .A1(n1439), .B0(n1409), .B1(n1519), .C0(n1408), .C1(n1438), .Y(n1411) );
OAI21X1TS U2044 ( .A0(n1441), .A1(n1412), .B0(n1411), .Y(n1414) );
XOR2X1TS U2045 ( .A(n1414), .B(n1413), .Y(n1415) );
ADDFHX2TS U2046 ( .A(n1417), .B(n1416), .CI(n1415), .CO(mult_x_19_n776), .S(
mult_x_19_n777) );
AOI222X1TS U2047 ( .A0(n1420), .A1(n1472), .B0(n1419), .B1(n1471), .C0(n1418), .C1(n1464), .Y(n1421) );
XOR2X1TS U2048 ( .A(n1422), .B(n1428), .Y(n1431) );
AOI22X1TS U2049 ( .A0(n1423), .A1(n1464), .B0(n1426), .B1(n1510), .Y(n1424)
);
XOR2X1TS U2050 ( .A(n1425), .B(n1428), .Y(n1478) );
XOR2X4TS U2051 ( .A(n1429), .B(n1428), .Y(n1458) );
CMPR22X2TS U2052 ( .A(n1431), .B(n1430), .CO(mult_x_19_n829), .S(n1445) );
AOI222X1TS U2053 ( .A0(n1434), .A1(n1453), .B0(n1433), .B1(n1451), .C0(n435),
.C1(n1432), .Y(n1435) );
OAI21X1TS U2054 ( .A0(n402), .A1(n1436), .B0(n1435), .Y(n1437) );
XOR2X1TS U2055 ( .A(n1437), .B(n1997), .Y(n1444) );
AOI222X1TS U2056 ( .A0(n1482), .A1(n1439), .B0(n1480), .B1(n1519), .C0(n1479), .C1(n1438), .Y(n1440) );
OAI21X1TS U2057 ( .A0(n1441), .A1(n1484), .B0(n1440), .Y(n1442) );
XOR2X1TS U2058 ( .A(n1442), .B(n1485), .Y(n1443) );
AOI222X1TS U2059 ( .A0(n1454), .A1(n1453), .B0(n1452), .B1(n1451), .C0(n1450), .C1(n2030), .Y(n1455) );
OAI21X1TS U2060 ( .A0(n402), .A1(n1456), .B0(n1455), .Y(n1457) );
ADDHX1TS U2061 ( .A(n1459), .B(n1458), .CO(n1477), .S(n1489) );
AOI222X1TS U2062 ( .A0(n1482), .A1(n1460), .B0(n1480), .B1(n1984), .C0(n1479), .C1(n1471), .Y(n1461) );
XOR2X2TS U2063 ( .A(n1462), .B(n1485), .Y(n1488) );
AOI22X2TS U2064 ( .A0(n1465), .A1(n1464), .B0(n1463), .B1(n1528), .Y(n1466)
);
XOR2X2TS U2065 ( .A(n1468), .B(n1485), .Y(n1507) );
CMPR22X2TS U2066 ( .A(n1694), .B(n1469), .CO(n1506), .S(mult_x_19_n859) );
AOI222X2TS U2067 ( .A0(n1482), .A1(n1472), .B0(n1480), .B1(n1471), .C0(n1479), .C1(n1470), .Y(n1473) );
XOR2X2TS U2068 ( .A(n1476), .B(n1485), .Y(n1508) );
ADDHX1TS U2069 ( .A(n1478), .B(n1477), .CO(n1430), .S(n1492) );
AOI222X1TS U2070 ( .A0(n1482), .A1(n1481), .B0(n1480), .B1(n1985), .C0(n1479), .C1(n1516), .Y(n1483) );
OAI21X1TS U2071 ( .A0(n1523), .A1(n1484), .B0(n1483), .Y(n1486) );
XOR2X1TS U2072 ( .A(n1486), .B(n1485), .Y(n1491) );
ADDFHX2TS U2073 ( .A(n1489), .B(n1488), .CI(n1487), .CO(n1490), .S(
mult_x_19_n842) );
XOR2X1TS U2074 ( .A(n1503), .B(n1502), .Y(mult_x_19_n1313) );
OA21X4TS U2075 ( .A0(n1513), .A1(n1512), .B0(n1511), .Y(n1525) );
ADDHX4TS U2076 ( .A(n1515), .B(n1514), .CO(n1524), .S(mult_x_19_n747) );
AOI222X1TS U2077 ( .A0(n1520), .A1(n1519), .B0(n1518), .B1(n1985), .C0(n1517), .C1(n1516), .Y(n1521) );
ADDHX4TS U2078 ( .A(n1530), .B(n1529), .CO(n1515), .S(mult_x_19_n758) );
OAI21X4TS U2079 ( .A0(n428), .A1(n1532), .B0(n1531), .Y(n1537) );
INVX2TS U2080 ( .A(n1533), .Y(n1535) );
XOR2X4TS U2081 ( .A(n1537), .B(n1536), .Y(n1538) );
MX2X4TS U2082 ( .A(n1538), .B(P_Sgf[46]), .S0(n1638), .Y(n284) );
INVX4TS U2083 ( .A(n1539), .Y(n1831) );
INVX2TS U2084 ( .A(n1551), .Y(n1540) );
INVX2TS U2085 ( .A(n1550), .Y(n1541) );
AOI21X2TS U2086 ( .A0(n1831), .A1(n1543), .B0(n1542), .Y(n1548) );
INVX2TS U2087 ( .A(n1544), .Y(n1546) );
NAND2X1TS U2088 ( .A(n1546), .B(n1545), .Y(n1547) );
INVX2TS U2089 ( .A(n1552), .Y(n1554) );
NAND2X1TS U2090 ( .A(n1554), .B(n1553), .Y(n1555) );
XOR2X1TS U2091 ( .A(n1556), .B(n1555), .Y(n1557) );
INVX2TS U2092 ( .A(n1558), .Y(n1829) );
INVX2TS U2093 ( .A(n1828), .Y(n1559) );
AOI21X2TS U2094 ( .A0(n1831), .A1(n1829), .B0(n1559), .Y(n1564) );
INVX2TS U2095 ( .A(n1560), .Y(n1562) );
NAND2X1TS U2096 ( .A(n1562), .B(n1561), .Y(n1563) );
XOR2X1TS U2097 ( .A(n1564), .B(n1563), .Y(n1565) );
INVX2TS U2098 ( .A(n1590), .Y(n1568) );
INVX2TS U2099 ( .A(n1594), .Y(n1567) );
INVX2TS U2100 ( .A(n1569), .Y(n1593) );
NAND2X1TS U2101 ( .A(n1593), .B(n1591), .Y(n1570) );
XNOR2X2TS U2102 ( .A(n1571), .B(n1570), .Y(n1572) );
NAND2X1TS U2103 ( .A(n1574), .B(n1573), .Y(n1575) );
XNOR2X2TS U2104 ( .A(n1576), .B(n1575), .Y(n1577) );
INVX2TS U2105 ( .A(n1578), .Y(n1606) );
NAND2X2TS U2106 ( .A(n1579), .B(n1606), .Y(n1583) );
INVX2TS U2107 ( .A(n1605), .Y(n1580) );
AOI21X2TS U2108 ( .A0(n1581), .A1(n1606), .B0(n1580), .Y(n1582) );
INVX2TS U2109 ( .A(n1584), .Y(n1586) );
NAND2X1TS U2110 ( .A(n1586), .B(n1585), .Y(n1587) );
XNOR2X4TS U2111 ( .A(n1588), .B(n1587), .Y(n1589) );
NAND2X1TS U2112 ( .A(n1590), .B(n1593), .Y(n1596) );
INVX2TS U2113 ( .A(n1591), .Y(n1592) );
AOI21X1TS U2114 ( .A0(n1594), .A1(n1593), .B0(n1592), .Y(n1595) );
INVX2TS U2115 ( .A(n1597), .Y(n1599) );
NAND2X1TS U2116 ( .A(n1599), .B(n1598), .Y(n1600) );
OAI21X2TS U2117 ( .A0(n1637), .A1(n1604), .B0(n1603), .Y(n1608) );
NAND2X1TS U2118 ( .A(n1606), .B(n1605), .Y(n1607) );
NAND2X1TS U2119 ( .A(n1611), .B(n1610), .Y(n1612) );
XOR2X2TS U2120 ( .A(n427), .B(n1612), .Y(n1613) );
INVX2TS U2121 ( .A(n1614), .Y(n1617) );
INVX2TS U2122 ( .A(n1615), .Y(n1616) );
OAI21X4TS U2123 ( .A0(n427), .A1(n1617), .B0(n1616), .Y(n1621) );
XOR2X4TS U2124 ( .A(n1621), .B(n1620), .Y(n1622) );
MX2X4TS U2125 ( .A(n1622), .B(n442), .S0(n1974), .Y(n279) );
OAI21X4TS U2126 ( .A0(n428), .A1(n1624), .B0(n1623), .Y(n1630) );
INVX2TS U2127 ( .A(n1626), .Y(n1628) );
XOR2X4TS U2128 ( .A(n1630), .B(n1629), .Y(n1632) );
MX2X4TS U2129 ( .A(n1632), .B(n443), .S0(n461), .Y(n278) );
INVX2TS U2130 ( .A(n1633), .Y(n1635) );
NAND2X1TS U2131 ( .A(n1635), .B(n1634), .Y(n1636) );
NAND2X1TS U2132 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1687) );
NOR3X1TS U2133 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1687), .Y(ready) );
NOR2XLTS U2134 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[1]), .Y(
n1640) );
BUFX3TS U2135 ( .A(n1643), .Y(n2053) );
INVX2TS U2136 ( .A(ready), .Y(n1641) );
AOI32X1TS U2137 ( .A0(FS_Module_state_reg[1]), .A1(n2035), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1681), .Y(
n1642) );
CLKBUFX2TS U2138 ( .A(n1643), .Y(n1644) );
BUFX3TS U2139 ( .A(n2063), .Y(n2061) );
INVX2TS U2140 ( .A(rst), .Y(n167) );
BUFX3TS U2141 ( .A(n167), .Y(n2071) );
BUFX3TS U2142 ( .A(n167), .Y(n2073) );
BUFX3TS U2143 ( .A(n2064), .Y(n2068) );
BUFX3TS U2144 ( .A(n1643), .Y(n2063) );
BUFX3TS U2145 ( .A(n2064), .Y(n2067) );
BUFX3TS U2146 ( .A(n1643), .Y(n2064) );
BUFX3TS U2147 ( .A(n1644), .Y(n2062) );
BUFX3TS U2148 ( .A(n167), .Y(n2070) );
BUFX3TS U2149 ( .A(n167), .Y(n2074) );
BUFX3TS U2150 ( .A(n167), .Y(n2072) );
BUFX3TS U2151 ( .A(n2063), .Y(n2054) );
BUFX3TS U2152 ( .A(n2064), .Y(n2059) );
CLKBUFX2TS U2153 ( .A(n2063), .Y(n2069) );
BUFX3TS U2154 ( .A(n1644), .Y(n2057) );
BUFX3TS U2155 ( .A(n1644), .Y(n2055) );
BUFX3TS U2156 ( .A(n2063), .Y(n2056) );
NOR4X1TS U2157 ( .A(P_Sgf[17]), .B(P_Sgf[15]), .C(P_Sgf[16]), .D(P_Sgf[14]),
.Y(n1651) );
NOR4X1TS U2158 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[19]), .D(P_Sgf[18]),
.Y(n1650) );
NOR3XLTS U2159 ( .A(P_Sgf[22]), .B(P_Sgf[1]), .C(P_Sgf[0]), .Y(n1647) );
AND4X1TS U2160 ( .A(n1648), .B(n1647), .C(n1646), .D(n1645), .Y(n1649) );
XOR2X1TS U2161 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n1673) );
MXI2X1TS U2162 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1673), .Y(n1652)
);
OAI211X1TS U2163 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1653), .C0(
n1652), .Y(n1689) );
INVX2TS U2164 ( .A(n1675), .Y(n1665) );
OAI21X2TS U2165 ( .A0(n1658), .A1(n1657), .B0(FS_Module_state_reg[1]), .Y(
n1704) );
BUFX3TS U2166 ( .A(n1774), .Y(n1766) );
AOI22X1TS U2167 ( .A0(n433), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n1766), .Y(n1662) );
OAI2BB1X1TS U2168 ( .A0N(n460), .A1N(P_Sgf[24]), .B0(n1662), .Y(n1663) );
AOI21X1TS U2169 ( .A0(n456), .A1(Add_result[0]), .B0(n1663), .Y(n1664) );
OAI2BB1X1TS U2170 ( .A0N(P_Sgf[23]), .A1N(n451), .B0(n1664), .Y(n202) );
BUFX3TS U2171 ( .A(n2069), .Y(n2065) );
BUFX3TS U2172 ( .A(n2069), .Y(n2066) );
BUFX3TS U2173 ( .A(n2069), .Y(n2060) );
BUFX3TS U2174 ( .A(n2069), .Y(n2058) );
INVX2TS U2175 ( .A(n1688), .Y(n1676) );
NAND2X2TS U2176 ( .A(n1684), .B(n1667), .Y(n2006) );
NAND2X1TS U2177 ( .A(Add_result[0]), .B(n1754), .Y(n1668) );
INVX2TS U2178 ( .A(n1754), .Y(n1834) );
INVX2TS U2179 ( .A(n1669), .Y(n1670) );
OAI31X1TS U2180 ( .A0(n1806), .A1(n1671), .A2(n2039), .B0(n1670), .Y(n235)
);
NOR2XLTS U2181 ( .A(n1673), .B(underflow_flag), .Y(n1674) );
OAI32X1TS U2182 ( .A0(n2012), .A1(n1674), .A2(overflow_flag), .B0(n2014),
.B1(n2052), .Y(n168) );
NOR2BX1TS U2183 ( .AN(n1680), .B(zero_flag), .Y(n1678) );
NOR3X1TS U2184 ( .A(n1676), .B(P_Sgf[47]), .C(n1675), .Y(n1677) );
AOI211XLTS U2185 ( .A0(n2038), .A1(n2035), .B0(n1678), .C0(n1677), .Y(n1679)
);
AOI22X1TS U2186 ( .A0(n1690), .A1(n1689), .B0(n1688), .B1(n1687), .Y(n1691)
);
OAI2BB1X1TS U2187 ( .A0N(n1692), .A1N(n2038), .B0(n1691), .Y(n378) );
NAND2X1TS U2188 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n1698) );
NAND2X1TS U2189 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n1789) );
NOR2X1TS U2190 ( .A(n2037), .B(n2041), .Y(n1771) );
NAND2X1TS U2191 ( .A(n1771), .B(Sgf_normalized_result[10]), .Y(n1701) );
MXI2X1TS U2192 ( .A(P_Sgf[46]), .B(Add_result[23]), .S0(FSM_selector_C), .Y(
n1703) );
AOI21X1TS U2193 ( .A0(n1704), .A1(n1703), .B0(n1774), .Y(n1705) );
AHHCINX2TS U2194 ( .A(Sgf_normalized_result[22]), .CIN(n1706), .S(n1707),
.CO(n1833) );
AOI22X1TS U2195 ( .A0(n434), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n1774), .Y(n1708) );
OAI2BB1X1TS U2196 ( .A0N(P_Sgf[46]), .A1N(n459), .B0(n1708), .Y(n1709) );
AOI21X1TS U2197 ( .A0(n456), .A1(Add_result[22]), .B0(n1709), .Y(n1710) );
OAI2BB1X1TS U2198 ( .A0N(n449), .A1N(n440), .B0(n1710), .Y(n224) );
AHHCONX2TS U2199 ( .A(Sgf_normalized_result[21]), .CI(n1711), .CON(n1706),
.S(n1712) );
AOI22X1TS U2200 ( .A0(n1713), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n1774), .Y(n1714) );
OAI2BB1X1TS U2201 ( .A0N(n440), .A1N(n458), .B0(n1714), .Y(n1715) );
AOI21X1TS U2202 ( .A0(n457), .A1(Add_result[21]), .B0(n1715), .Y(n1716) );
OAI2BB1X1TS U2203 ( .A0N(n449), .A1N(n453), .B0(n1716), .Y(n223) );
AHHCINX2TS U2204 ( .A(Sgf_normalized_result[20]), .CIN(n1717), .S(n1718),
.CO(n1711) );
AOI22X1TS U2205 ( .A0(n434), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n1774), .Y(n1719) );
OAI2BB1X1TS U2206 ( .A0N(n458), .A1N(n453), .B0(n1719), .Y(n1720) );
AOI21X1TS U2207 ( .A0(n456), .A1(Add_result[20]), .B0(n1720), .Y(n1721) );
OAI2BB1X1TS U2208 ( .A0N(n449), .A1N(n439), .B0(n1721), .Y(n222) );
AHHCONX2TS U2209 ( .A(Sgf_normalized_result[19]), .CI(n1722), .CON(n1717),
.S(n1723) );
AOI22X1TS U2210 ( .A0(n434), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n1766), .Y(n1724) );
OAI2BB1X1TS U2211 ( .A0N(n459), .A1N(n439), .B0(n1724), .Y(n1725) );
AOI21X1TS U2212 ( .A0(n457), .A1(Add_result[19]), .B0(n1725), .Y(n1726) );
OAI2BB1X1TS U2213 ( .A0N(n449), .A1N(n452), .B0(n1726), .Y(n221) );
AHHCINX2TS U2214 ( .A(Sgf_normalized_result[18]), .CIN(n1727), .S(n1728),
.CO(n1722) );
AOI22X1TS U2215 ( .A0(n434), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n1766), .Y(n1729) );
OAI2BB1X1TS U2216 ( .A0N(n460), .A1N(n452), .B0(n1729), .Y(n1730) );
AOI21X1TS U2217 ( .A0(n457), .A1(Add_result[18]), .B0(n1730), .Y(n1731) );
OAI2BB1X1TS U2218 ( .A0N(n449), .A1N(n442), .B0(n1731), .Y(n220) );
AHHCONX2TS U2219 ( .A(Sgf_normalized_result[17]), .CI(n1732), .CON(n1727),
.S(n1733) );
AOI22X1TS U2220 ( .A0(n433), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n1766), .Y(n1734) );
OAI2BB1X1TS U2221 ( .A0N(n460), .A1N(n442), .B0(n1734), .Y(n1735) );
AOI21X1TS U2222 ( .A0(n456), .A1(Add_result[17]), .B0(n1735), .Y(n1736) );
OAI2BB1X1TS U2223 ( .A0N(n449), .A1N(n443), .B0(n1736), .Y(n219) );
AHHCINX2TS U2224 ( .A(Sgf_normalized_result[16]), .CIN(n1737), .S(n1738),
.CO(n1732) );
AOI22X1TS U2225 ( .A0(n433), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n1766), .Y(n1739) );
OAI2BB1X1TS U2226 ( .A0N(n459), .A1N(n443), .B0(n1739), .Y(n1740) );
AOI21X1TS U2227 ( .A0(n456), .A1(Add_result[16]), .B0(n1740), .Y(n1741) );
OAI2BB1X1TS U2228 ( .A0N(n450), .A1N(n454), .B0(n1741), .Y(n218) );
AHHCONX2TS U2229 ( .A(Sgf_normalized_result[15]), .CI(n1742), .CON(n1737),
.S(n1743) );
AOI22X1TS U2230 ( .A0(n433), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n1766), .Y(n1744) );
OAI2BB1X1TS U2231 ( .A0N(n458), .A1N(n454), .B0(n1744), .Y(n1745) );
AOI21X1TS U2232 ( .A0(n457), .A1(Add_result[15]), .B0(n1745), .Y(n1746) );
OAI2BB1X1TS U2233 ( .A0N(n451), .A1N(n441), .B0(n1746), .Y(n217) );
AHHCINX2TS U2234 ( .A(Sgf_normalized_result[14]), .CIN(n1747), .S(n1749),
.CO(n1742) );
AOI22X1TS U2235 ( .A0(n434), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n1766), .Y(n1750) );
OAI2BB1X1TS U2236 ( .A0N(n460), .A1N(n441), .B0(n1750), .Y(n1751) );
AOI21X1TS U2237 ( .A0(n457), .A1(Add_result[14]), .B0(n1751), .Y(n1752) );
OAI2BB1X1TS U2238 ( .A0N(n450), .A1N(n455), .B0(n1752), .Y(n216) );
AHHCONX2TS U2239 ( .A(Sgf_normalized_result[13]), .CI(n1753), .CON(n1747),
.S(n1755) );
AOI22X1TS U2240 ( .A0(n1713), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n1766), .Y(n1756) );
OAI2BB1X1TS U2241 ( .A0N(n459), .A1N(n455), .B0(n1756), .Y(n1757) );
AOI21X1TS U2242 ( .A0(n456), .A1(Add_result[13]), .B0(n1757), .Y(n1758) );
OAI2BB1X1TS U2243 ( .A0N(n451), .A1N(n448), .B0(n1758), .Y(n215) );
AHHCINX2TS U2244 ( .A(Sgf_normalized_result[12]), .CIN(n1759), .S(n1760),
.CO(n1753) );
AOI22X1TS U2245 ( .A0(n433), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n1766), .Y(n1761) );
OAI2BB1X1TS U2246 ( .A0N(n458), .A1N(n448), .B0(n1761), .Y(n1762) );
AOI21X1TS U2247 ( .A0(n456), .A1(Add_result[12]), .B0(n1762), .Y(n1763) );
OAI2BB1X1TS U2248 ( .A0N(n450), .A1N(P_Sgf[35]), .B0(n1763), .Y(n214) );
AHHCONX2TS U2249 ( .A(Sgf_normalized_result[11]), .CI(n1764), .CON(n1759),
.S(n1765) );
AOI22X1TS U2250 ( .A0(n434), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n1766), .Y(n1767) );
OAI2BB1X1TS U2251 ( .A0N(n460), .A1N(P_Sgf[35]), .B0(n1767), .Y(n1768) );
AOI21X1TS U2252 ( .A0(n457), .A1(Add_result[11]), .B0(n1768), .Y(n1769) );
OAI2BB1X1TS U2253 ( .A0N(n451), .A1N(P_Sgf[34]), .B0(n1769), .Y(n213) );
NAND2X1TS U2254 ( .A(n1783), .B(n1771), .Y(n1772) );
XOR2X1TS U2255 ( .A(n1772), .B(n2049), .Y(n1773) );
BUFX3TS U2256 ( .A(n1774), .Y(n1823) );
AOI22X1TS U2257 ( .A0(n433), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n1823), .Y(n1775) );
OAI2BB1X1TS U2258 ( .A0N(n458), .A1N(P_Sgf[34]), .B0(n1775), .Y(n1776) );
AOI21X1TS U2259 ( .A0(n457), .A1(Add_result[10]), .B0(n1776), .Y(n1777) );
OAI2BB1X1TS U2260 ( .A0N(n450), .A1N(P_Sgf[33]), .B0(n1777), .Y(n212) );
NAND2X1TS U2261 ( .A(n1783), .B(Sgf_normalized_result[8]), .Y(n1778) );
XOR2X1TS U2262 ( .A(n1778), .B(n2041), .Y(n1779) );
AOI22X1TS U2263 ( .A0(n1713), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n1823), .Y(n1780) );
OAI2BB1X1TS U2264 ( .A0N(n459), .A1N(P_Sgf[33]), .B0(n1780), .Y(n1781) );
AOI21X1TS U2265 ( .A0(n456), .A1(Add_result[9]), .B0(n1781), .Y(n1782) );
OAI2BB1X1TS U2266 ( .A0N(n451), .A1N(P_Sgf[32]), .B0(n1782), .Y(n211) );
XNOR2X1TS U2267 ( .A(n1783), .B(n2037), .Y(n1784) );
AOI22X1TS U2268 ( .A0(n434), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n1823), .Y(n1785) );
OAI2BB1X1TS U2269 ( .A0N(n460), .A1N(P_Sgf[32]), .B0(n1785), .Y(n1786) );
AOI21X1TS U2270 ( .A0(n457), .A1(Add_result[8]), .B0(n1786), .Y(n1787) );
OAI2BB1X1TS U2271 ( .A0N(n450), .A1N(n447), .B0(n1787), .Y(n210) );
OAI21X1TS U2272 ( .A0(n1805), .A1(n2042), .B0(n1789), .Y(n1795) );
NAND2X1TS U2273 ( .A(n1795), .B(Sgf_normalized_result[6]), .Y(n1790) );
XOR2X1TS U2274 ( .A(n1790), .B(n2050), .Y(n1791) );
AOI22X1TS U2275 ( .A0(n1713), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n1823), .Y(n1792) );
OAI2BB1X1TS U2276 ( .A0N(n458), .A1N(n447), .B0(n1792), .Y(n1793) );
AOI21X1TS U2277 ( .A0(n456), .A1(Add_result[7]), .B0(n1793), .Y(n1794) );
OAI2BB1X1TS U2278 ( .A0N(n451), .A1N(n446), .B0(n1794), .Y(n209) );
XNOR2X1TS U2279 ( .A(n1795), .B(n2047), .Y(n1796) );
AOI22X1TS U2280 ( .A0(n433), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n1823), .Y(n1797) );
OAI2BB1X1TS U2281 ( .A0N(n459), .A1N(n446), .B0(n1797), .Y(n1798) );
AOI21X1TS U2282 ( .A0(n1660), .A1(Add_result[6]), .B0(n1798), .Y(n1799) );
OAI2BB1X1TS U2283 ( .A0N(n450), .A1N(n445), .B0(n1799), .Y(n208) );
NAND2X1TS U2284 ( .A(n1805), .B(n2046), .Y(n1800) );
XNOR2X1TS U2285 ( .A(n1800), .B(n2042), .Y(n1801) );
AOI22X1TS U2286 ( .A0(n433), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n1823), .Y(n1802) );
OAI2BB1X1TS U2287 ( .A0N(n460), .A1N(n445), .B0(n1802), .Y(n1803) );
AOI21X1TS U2288 ( .A0(n1660), .A1(Add_result[5]), .B0(n1803), .Y(n1804) );
OAI2BB1X1TS U2289 ( .A0N(n451), .A1N(n444), .B0(n1804), .Y(n207) );
XOR2X1TS U2290 ( .A(n1805), .B(Sgf_normalized_result[4]), .Y(n1807) );
AOI22X1TS U2291 ( .A0(n434), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n1823), .Y(n1808) );
OAI2BB1X1TS U2292 ( .A0N(n458), .A1N(n444), .B0(n1808), .Y(n1809) );
AOI21X1TS U2293 ( .A0(n1660), .A1(Add_result[4]), .B0(n1809), .Y(n1810) );
OAI2BB1X1TS U2294 ( .A0N(n450), .A1N(P_Sgf[27]), .B0(n1810), .Y(n206) );
XOR2X1TS U2295 ( .A(n1812), .B(n2040), .Y(n1813) );
AOI22X1TS U2296 ( .A0(n1713), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n1823), .Y(n1814) );
OAI2BB1X1TS U2297 ( .A0N(n459), .A1N(P_Sgf[27]), .B0(n1814), .Y(n1815) );
AOI21X1TS U2298 ( .A0(n457), .A1(Add_result[3]), .B0(n1815), .Y(n1816) );
OAI2BB1X1TS U2299 ( .A0N(n451), .A1N(P_Sgf[26]), .B0(n1816), .Y(n205) );
XOR2X1TS U2300 ( .A(n1817), .B(Sgf_normalized_result[2]), .Y(n1818) );
AOI22X1TS U2301 ( .A0(n433), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n1823), .Y(n1819) );
OAI2BB1X1TS U2302 ( .A0N(n458), .A1N(P_Sgf[26]), .B0(n1819), .Y(n1820) );
AOI21X1TS U2303 ( .A0(n457), .A1(Add_result[2]), .B0(n1820), .Y(n1821) );
OAI2BB1X1TS U2304 ( .A0N(n449), .A1N(P_Sgf[25]), .B0(n1821), .Y(n204) );
XNOR2X1TS U2305 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n1822) );
AOI22X1TS U2306 ( .A0(n1713), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n1823), .Y(n1824) );
OAI2BB1X1TS U2307 ( .A0N(n459), .A1N(P_Sgf[25]), .B0(n1824), .Y(n1826) );
AOI21X1TS U2308 ( .A0(n456), .A1(Add_result[1]), .B0(n1826), .Y(n1827) );
OAI2BB1X1TS U2309 ( .A0N(n450), .A1N(P_Sgf[24]), .B0(n1827), .Y(n203) );
NAND2X1TS U2310 ( .A(n1829), .B(n1828), .Y(n1830) );
XNOR2X1TS U2311 ( .A(n1831), .B(n1830), .Y(n1832) );
ADDHXLTS U2312 ( .A(Sgf_normalized_result[23]), .B(n1833), .CO(n1835), .S(
n1702) );
XOR2X1TS U2313 ( .A(n1837), .B(n1836), .Y(n1838) );
NAND2X1TS U2314 ( .A(n1840), .B(n1839), .Y(n1842) );
XNOR2X1TS U2315 ( .A(n1842), .B(n1841), .Y(n1843) );
INVX2TS U2316 ( .A(n1844), .Y(n1846) );
NAND2X1TS U2317 ( .A(n1846), .B(n1845), .Y(n1847) );
XOR2X1TS U2318 ( .A(n1848), .B(n1847), .Y(n1849) );
NAND2X1TS U2319 ( .A(n1850), .B(n1854), .Y(n1852) );
INVX2TS U2320 ( .A(n1851), .Y(n1856) );
XOR2X1TS U2321 ( .A(n1852), .B(n1856), .Y(n1853) );
NAND2X1TS U2322 ( .A(n1859), .B(n1858), .Y(n1860) );
XNOR2X1TS U2323 ( .A(n1861), .B(n1860), .Y(n1862) );
NAND2X1TS U2324 ( .A(n1865), .B(n1864), .Y(n1866) );
XOR2X1TS U2325 ( .A(n1867), .B(n1866), .Y(n1869) );
NAND2X1TS U2326 ( .A(n1871), .B(n1870), .Y(n1872) );
XNOR2X1TS U2327 ( .A(n1873), .B(n1872), .Y(n1874) );
INVX2TS U2328 ( .A(n1875), .Y(n1895) );
NAND2X1TS U2329 ( .A(n481), .B(n1876), .Y(n1877) );
XNOR2X1TS U2330 ( .A(n1895), .B(n1877), .Y(n1878) );
XNOR2X1TS U2331 ( .A(n1882), .B(n1881), .Y(n1883) );
INVX4TS U2332 ( .A(n1885), .Y(n1964) );
OAI21X1TS U2333 ( .A0(n1964), .A1(n1887), .B0(n1886), .Y(n1892) );
INVX2TS U2334 ( .A(n1888), .Y(n1890) );
NAND2X1TS U2335 ( .A(n1890), .B(n1889), .Y(n1891) );
XNOR2X1TS U2336 ( .A(n1892), .B(n1891), .Y(n1893) );
AOI21X1TS U2337 ( .A0(n1895), .A1(n481), .B0(n1894), .Y(n1899) );
NAND2X1TS U2338 ( .A(n1897), .B(n1896), .Y(n1898) );
XOR2X1TS U2339 ( .A(n1899), .B(n1898), .Y(n1900) );
INVX2TS U2340 ( .A(n1901), .Y(n1907) );
INVX2TS U2341 ( .A(n1906), .Y(n1902) );
NAND2X1TS U2342 ( .A(n1902), .B(n1905), .Y(n1903) );
XOR2X1TS U2343 ( .A(n1907), .B(n1903), .Y(n1904) );
INVX2TS U2344 ( .A(n1908), .Y(n1910) );
NAND2X1TS U2345 ( .A(n1910), .B(n1909), .Y(n1911) );
XNOR2X1TS U2346 ( .A(n1912), .B(n1911), .Y(n1913) );
INVX2TS U2347 ( .A(n1914), .Y(n1920) );
NAND2X1TS U2348 ( .A(n1915), .B(n488), .Y(n1916) );
XNOR2X1TS U2349 ( .A(n1920), .B(n1916), .Y(n1918) );
AOI21X1TS U2350 ( .A0(n1920), .A1(n488), .B0(n1919), .Y(n1924) );
NAND2X1TS U2351 ( .A(n1922), .B(n1921), .Y(n1923) );
XOR2X1TS U2352 ( .A(n1924), .B(n1923), .Y(n1925) );
INVX2TS U2353 ( .A(n1926), .Y(n1932) );
INVX2TS U2354 ( .A(n1931), .Y(n1927) );
NAND2X1TS U2355 ( .A(n1927), .B(n1930), .Y(n1928) );
XOR2X1TS U2356 ( .A(n1932), .B(n1928), .Y(n1929) );
INVX2TS U2357 ( .A(n1933), .Y(n1935) );
NAND2X1TS U2358 ( .A(n1935), .B(n1934), .Y(n1936) );
XNOR2X1TS U2359 ( .A(n1937), .B(n1936), .Y(n1938) );
INVX2TS U2360 ( .A(n1940), .Y(n1945) );
NAND2X1TS U2361 ( .A(n1945), .B(n1943), .Y(n1941) );
XNOR2X1TS U2362 ( .A(n1954), .B(n1941), .Y(n1942) );
INVX2TS U2363 ( .A(n1943), .Y(n1944) );
AOI21X1TS U2364 ( .A0(n1954), .A1(n1945), .B0(n1944), .Y(n1950) );
INVX2TS U2365 ( .A(n1946), .Y(n1948) );
NAND2X1TS U2366 ( .A(n1948), .B(n1947), .Y(n1949) );
XOR2X1TS U2367 ( .A(n1950), .B(n1949), .Y(n1951) );
AOI21X1TS U2368 ( .A0(n1954), .A1(n1953), .B0(n1952), .Y(n1957) );
NAND2X1TS U2369 ( .A(n487), .B(n1955), .Y(n1956) );
XOR2X1TS U2370 ( .A(n1957), .B(n1956), .Y(n1958) );
NAND2X1TS U2371 ( .A(n1959), .B(n1962), .Y(n1960) );
XOR2X1TS U2372 ( .A(n1964), .B(n1960), .Y(n1961) );
OAI21X1TS U2373 ( .A0(n1964), .A1(n1963), .B0(n1962), .Y(n1967) );
NAND2X1TS U2374 ( .A(n407), .B(n1965), .Y(n1966) );
XNOR2X1TS U2375 ( .A(n1967), .B(n1966), .Y(n1968) );
NAND2X1TS U2376 ( .A(n2006), .B(n2048), .Y(n376) );
NOR2BX1TS U2377 ( .AN(exp_oper_result[8]), .B(n2048), .Y(S_Oper_A_exp[8]) );
XNOR2X1TS U2378 ( .A(DP_OP_32J1_122_6543_n1), .B(n1683), .Y(n1975) );
AND4X1TS U2379 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n1976) );
AND4X1TS U2380 ( .A(Exp_module_Data_S[6]), .B(Exp_module_Data_S[5]), .C(
Exp_module_Data_S[4]), .D(n1976), .Y(n1977) );
AO22X1TS U2381 ( .A0(n2008), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n2012), .Y(n200) );
AO22X1TS U2382 ( .A0(n2008), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n2012), .Y(n199) );
AO22X1TS U2383 ( .A0(n2008), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n2012), .Y(n198) );
NOR4X1TS U2384 ( .A(Op_MY[27]), .B(Op_MY[26]), .C(Op_MY[25]), .D(Op_MY[24]),
.Y(n1983) );
NOR4X1TS U2385 ( .A(Op_MY[22]), .B(Op_MY[18]), .C(Op_MY[14]), .D(Op_MY[15]),
.Y(n1982) );
NOR4X1TS U2386 ( .A(Op_MY[20]), .B(Op_MY[19]), .C(Op_MY[17]), .D(Op_MY[16]),
.Y(n1981) );
NOR4X1TS U2387 ( .A(Op_MY[21]), .B(Op_MY[30]), .C(Op_MY[29]), .D(Op_MY[28]),
.Y(n1980) );
NOR4X1TS U2388 ( .A(n1987), .B(Op_MY[8]), .C(n1986), .D(Op_MY[4]), .Y(n1989)
);
NOR4X1TS U2389 ( .A(Op_MX[21]), .B(Op_MX[19]), .C(Op_MX[16]), .D(Op_MX[18]),
.Y(n1996) );
NOR4X1TS U2390 ( .A(Op_MX[27]), .B(Op_MX[26]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n1995) );
NOR4X1TS U2391 ( .A(Op_MX[17]), .B(Op_MX[30]), .C(Op_MX[29]), .D(Op_MX[28]),
.Y(n1994) );
NOR4X1TS U2392 ( .A(Op_MX[13]), .B(Op_MX[10]), .C(Op_MX[7]), .D(Op_MX[4]),
.Y(n2000) );
NOR4X1TS U2393 ( .A(Op_MX[12]), .B(Op_MX[9]), .C(Op_MX[6]), .D(Op_MX[3]),
.Y(n1999) );
OA22X1TS U2394 ( .A0(n2004), .A1(n2003), .B0(n2002), .B1(n2001), .Y(n2005)
);
OAI2BB2XLTS U2395 ( .B0(n2006), .B1(n2005), .A0N(n2006), .A1N(zero_flag),
.Y(n311) );
AO22X1TS U2396 ( .A0(Sgf_normalized_result[3]), .A1(n2008), .B0(
final_result_ieee[3]), .B1(n2012), .Y(n197) );
INVX2TS U2397 ( .A(n2016), .Y(n2007) );
AO22X1TS U2398 ( .A0(Sgf_normalized_result[9]), .A1(n2008), .B0(
final_result_ieee[9]), .B1(n2009), .Y(n191) );
AO22X1TS U2399 ( .A0(Sgf_normalized_result[10]), .A1(n2010), .B0(
final_result_ieee[10]), .B1(n2009), .Y(n190) );
AO22X1TS U2400 ( .A0(Sgf_normalized_result[11]), .A1(n2010), .B0(
final_result_ieee[11]), .B1(n2009), .Y(n189) );
AO22X1TS U2401 ( .A0(Sgf_normalized_result[12]), .A1(n2010), .B0(
final_result_ieee[12]), .B1(n2009), .Y(n188) );
AO22X1TS U2402 ( .A0(Sgf_normalized_result[13]), .A1(n2010), .B0(
final_result_ieee[13]), .B1(n2009), .Y(n187) );
AO22X1TS U2403 ( .A0(Sgf_normalized_result[14]), .A1(n2010), .B0(
final_result_ieee[14]), .B1(n2009), .Y(n186) );
AO22X1TS U2404 ( .A0(Sgf_normalized_result[15]), .A1(n2010), .B0(
final_result_ieee[15]), .B1(n2009), .Y(n185) );
AO22X1TS U2405 ( .A0(Sgf_normalized_result[16]), .A1(n2010), .B0(
final_result_ieee[16]), .B1(n2009), .Y(n184) );
AO22X1TS U2406 ( .A0(Sgf_normalized_result[17]), .A1(n2010), .B0(
final_result_ieee[17]), .B1(n2009), .Y(n183) );
AO22X1TS U2407 ( .A0(Sgf_normalized_result[18]), .A1(n2010), .B0(
final_result_ieee[18]), .B1(n2009), .Y(n182) );
AO22X1TS U2408 ( .A0(Sgf_normalized_result[19]), .A1(n2010), .B0(
final_result_ieee[19]), .B1(n2012), .Y(n181) );
INVX2TS U2409 ( .A(n2015), .Y(n2013) );
AO22X1TS U2410 ( .A0(Sgf_normalized_result[20]), .A1(n2013), .B0(
final_result_ieee[20]), .B1(n2012), .Y(n180) );
AO22X1TS U2411 ( .A0(Sgf_normalized_result[21]), .A1(n2013), .B0(
final_result_ieee[21]), .B1(n2012), .Y(n179) );
AO22X1TS U2412 ( .A0(Sgf_normalized_result[22]), .A1(n2013), .B0(
final_result_ieee[22]), .B1(n2012), .Y(n178) );
OA22X1TS U2413 ( .A0(n2016), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n2015), .Y(n177) );
OA22X1TS U2414 ( .A0(n2016), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n2015), .Y(n176) );
OA22X1TS U2415 ( .A0(n2014), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n2015), .Y(n175) );
OA22X1TS U2416 ( .A0(n2014), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n2015), .Y(n174) );
OA22X1TS U2417 ( .A0(n2014), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n2015), .Y(n173) );
OA22X1TS U2418 ( .A0(n2014), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n2015), .Y(n172) );
OA22X1TS U2419 ( .A0(n2014), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n2015), .Y(n171) );
OA22X1TS U2420 ( .A0(n2016), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n2015), .Y(n170) );
CMPR42X1TS U2421 ( .A(n396), .B(n2028), .C(n2026), .D(mult_x_19_n1152),
.ICI(mult_x_19_n657), .S(mult_x_19_n650), .ICO(mult_x_19_n648), .CO(
mult_x_19_n649) );
CMPR42X1TS U2422 ( .A(n479), .B(n2019), .C(n2021), .D(n467), .ICI(
mult_x_19_n571), .S(mult_x_19_n570), .ICO(mult_x_19_n568), .CO(
mult_x_19_n569) );
CMPR42X1TS U2423 ( .A(n397), .B(mult_x_19_n582), .C(mult_x_19_n1142), .D(
n475), .ICI(mult_x_19_n579), .S(mult_x_19_n577), .ICO(mult_x_19_n575),
.CO(mult_x_19_n576) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk10.tcl_DW_1STAGE_syn.sdf");
endmodule
|
module Microfono(clk, reset, rec, play, bclk, lrsel, data_in, data_out, ampSD, rd, wr, emptyLED, fullLED);
input wire clk;
input wire reset;
input wire rec;
input wire play;
output wire bclk;
output wire lrsel;
input wire data_in;
output wire data_out;
output wire ampSD;
output wire rd;
output wire wr;
output wire emptyLED;
output wire fullLED;
wire empty;
wire full;
wire RstN;
wire FClrN;
wire F_LastN;
wire F_SLastN;
wire F_FirstN;
reg [5:0] fifo_counter = 0;
reg fclk = 1'b0;
assign FClrN = 1'b1;
assign emptyLED = ~empty;
assign fullLED = ~full;
always @(posedge bclk) // bclk = 1MHz
begin
if (reset)
begin
fifo_counter = 0;
fclk = 1'b1;
end
else
if (fifo_counter == 2)
begin
fifo_counter = 1;
fclk = ~fclk;
end
else
begin
fifo_counter = fifo_counter + 1;
fclk = fclk;
end
end
assign lrsel = 1'b0; //mic LRSel
assign ampSD = 1'b1;
DivFreq _DivFreq(
.reset(reset),
.clk(clk),
.bclk(bclk) // reloj de 1MHz
);
fifo _fifo(
.Clk(bclk), // reloj de la fifo
.RstN(~reset),
.Data_In(data_in),
.FClrN(FClrN),
.FInN(~wr),
.FOutN(~rd),
.F_Data(data_out),
.F_FullN(full),
.F_LastN(F_LastN),
.F_SLastN(F_SLastN),
.F_FirstN(F_FirstN),
.F_EmptyN(empty)
);
FSM _FSM(
.reset(reset),
.clk(clk),
.full(~full),
.empty(~empty),
.rec(rec),
.play(play),
.wr(wr),
.rd(rd)
);
endmodule
|
Require Import Verdi.Verdi.
Require Import Verdi.LabeledNet.
Require Import Verdi.TotalMapSimulations.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.map.
Require Import InfSeqExt.exteq.
Require Import FunctionalExtensionality.
Local Arguments update {_} {_} _ _ _ _ _ : simpl never.
Require Import Verdi.Ssrexport.
Set Implicit Arguments.
Class LabeledMultiParamsLabelTotalMap
(B0 : BaseParams) (B1 : BaseParams)
(P0 : LabeledMultiParams B0) (P1 : LabeledMultiParams B1) :=
{
tot_map_label : @label B0 P0 -> @label B1 P1
}.
Section LabeledTotalMapDefs.
Context {base_fst : BaseParams}.
Context {base_snd : BaseParams}.
Context {labeled_multi_fst : LabeledMultiParams base_fst}.
Context {labeled_multi_snd : LabeledMultiParams base_snd}.
Context {label_map : LabeledMultiParamsLabelTotalMap labeled_multi_fst labeled_multi_snd}.
Definition tot_mapped_lb_net_handlers_label me src m st :=
let '(lb, out, st', ps) := lb_net_handlers me src m st in tot_map_label lb.
Definition tot_mapped_lb_input_handlers_label me inp st :=
let '(lb, out, st', ps) := lb_input_handlers me inp st in tot_map_label lb.
End LabeledTotalMapDefs.
Class LabeledMultiParamsTotalMapCongruency
(B0 : BaseParams) (B1 : BaseParams)
(P0 : LabeledMultiParams B0) (P1 : LabeledMultiParams B1)
(B : BaseParamsTotalMap B0 B1)
(N : MultiParamsNameTotalMap (@unlabeled_multi_params _ P0) (@unlabeled_multi_params _ P1))
(P : MultiParamsMsgTotalMap (@unlabeled_multi_params _ P0) (@unlabeled_multi_params _ P1))
(L : LabeledMultiParamsLabelTotalMap P0 P1) : Prop :=
{
tot_lb_net_handlers_eq : forall me src m st out st' ps lb,
lb_net_handlers (tot_map_name me) (tot_map_name src) (tot_map_msg m) (tot_map_data st) = (lb, out, st', ps) ->
tot_mapped_lb_net_handlers_label me src m st = lb ;
tot_lb_input_handlers_eq : forall me inp st out st' ps lb,
lb_input_handlers (tot_map_name me) (tot_map_input inp) (tot_map_data st) = (lb, out, st', ps) ->
tot_mapped_lb_input_handlers_label me inp st = lb ;
tot_lb_label_silent_fst_snd : tot_map_label label_silent = label_silent
}.
Section TotalMapExecutionSimulations.
Context {base_fst : BaseParams}.
Context {base_snd : BaseParams}.
Context {labeled_multi_fst : LabeledMultiParams base_fst}.
Context {labeled_multi_snd : LabeledMultiParams base_snd}.
Context {base_map : BaseParamsTotalMap base_fst base_snd}.
Context {name_map : MultiParamsNameTotalMap (@unlabeled_multi_params _ labeled_multi_fst) (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {msg_map : MultiParamsMsgTotalMap (@unlabeled_multi_params _ labeled_multi_fst) (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {label_map : LabeledMultiParamsLabelTotalMap labeled_multi_fst labeled_multi_snd}.
Context {name_map_bijective : MultiParamsNameTotalMapBijective name_map}.
Context {multi_map_congr : MultiParamsTotalMapCongruency base_map name_map msg_map}.
Context {multi_map_lb_congr : LabeledMultiParamsTotalMapCongruency base_map name_map msg_map label_map}.
Hypothesis tot_map_label_injective :
forall l l', tot_map_label l = tot_map_label l' -> l = l'.
(* lb_step_failure *)
Theorem lb_step_failure_tot_mapped_simulation_1 :
forall net net' failed failed' lb tr,
@lb_step_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_failure _ labeled_multi_snd (List.map tot_map_name failed, tot_map_net net) (tot_map_label lb) (List.map tot_map_name failed', tot_map_net net') (List.map tot_map_trace_occ tr).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_step.
invcs H_step => //=.
- have ->: tot_map_name (pDst p) = pDst (tot_map_packet p) by destruct p.
apply: (@LabeledStepFailure_deliver _ _ _ _ _ _ (List.map tot_map_packet xs) (List.map tot_map_packet ys) (List.map tot_map_output out) (tot_map_data d) (@tot_map_name_msgs _ _ _ _ _ msg_map l)).
* rewrite /tot_map_net /=.
find_rewrite.
by rewrite map_app.
* destruct p.
simpl in *.
exact: not_in_failed_not_in.
* destruct p.
simpl in *.
rewrite tot_map_name_inv_inverse.
have H_q := @tot_net_handlers_eq _ _ _ _ _ _ _ multi_map_congr pDst pSrc pBody (nwState net pDst).
rewrite /tot_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @tot_lb_net_handlers_eq _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ Heqp1.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
by repeat tuple_inversion.
* rewrite /tot_map_net /= 2!map_app -(@tot_map_update_packet_eq _ _ _ _ _ _ _ name_map_bijective).
destruct p.
by rewrite tot_map_packet_map_eq.
- apply: (@LabeledStepFailure_input _ _ _ _ _ _ _ _ (tot_map_data d) (tot_map_name_msgs l)).
* exact: not_in_failed_not_in.
* rewrite /tot_map_net /= tot_map_name_inv_inverse.
have H_q := @tot_input_handlers_eq _ _ _ _ _ _ _ multi_map_congr h inp (nwState net h).
rewrite /tot_mapped_input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @tot_lb_input_handlers_eq _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ Heqp1.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
by repeat tuple_inversion.
* by rewrite /tot_map_net /= map_app tot_map_packet_map_eq -(@tot_map_update_eq _ _ _ _ _ _ name_map_bijective).
- rewrite tot_lb_label_silent_fst_snd.
exact: LabeledStepFailure_stutter.
Qed.
Definition tot_map_net_event e :=
{| evt_a := (List.map tot_map_name (fst e.(evt_a)), tot_map_net (snd e.(evt_a))) ;
evt_l := tot_map_label e.(evt_l) ;
evt_trace := List.map tot_map_trace_occ e.(evt_trace) |}.
Lemma tot_map_net_event_map_unfold : forall s,
Cons (tot_map_net_event (hd s)) (map tot_map_net_event (tl s)) = map tot_map_net_event s.
Proof using.
by move => s; rewrite -map_Cons /= -{3}(recons s).
Qed.
Lemma lb_step_trace_execution_lb_step_failure_tot_map_net_infseq : forall s,
lb_step_execution lb_step_failure s ->
lb_step_execution lb_step_failure (map tot_map_net_event s).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
cofix c.
move => s H_exec.
rewrite -tot_map_net_event_map_unfold {1}/tot_map_net_event /=.
inversion H_exec; subst => /=.
rewrite -tot_map_net_event_map_unfold /= /tot_map_net_event /=.
apply: (@Cons_lb_step_exec _ _ _ _ _ _ (List.map tot_map_trace_occ tr)) => /=.
- apply: lb_step_failure_tot_mapped_simulation_1.
have <-: evt_a e = (fst (evt_a e), snd (evt_a e)) by destruct e, evt_a.
by have <-: evt_a e' = (fst (evt_a e'), snd (evt_a e')) by destruct e', evt_a.
- simpl in *.
find_rewrite.
by rewrite map_app.
- set e0 := {| evt_a := _ ; evt_l := _ ; evt_trace := _ |}.
have ->: e0 = tot_map_net_event e' by [].
pose s' := Cons e' s0.
rewrite (tot_map_net_event_map_unfold s').
exact: c.
Qed.
Lemma tot_map_net_label_event_inf_often_occurred :
forall l s,
inf_often (now (occurred l)) s ->
inf_often (now (occurred (tot_map_label l))) (map tot_map_net_event s).
Proof using.
move => l.
apply: always_map.
apply: eventually_map.
case => e s.
rewrite /= /occurred /=.
move => H_eq.
by rewrite H_eq.
Qed.
Lemma tot_map_net_label_event_inf_often_occurred_conv :
forall l s,
inf_often (now (occurred (tot_map_label l))) (map tot_map_net_event s) ->
inf_often (now (occurred l)) s.
Proof using tot_map_label_injective.
move => l.
apply: always_map_conv.
apply: eventually_map_conv => //.
- rewrite /extensional /=.
case => e s1.
case => e' s2.
move => H_eq.
by inversion H_eq; subst_max.
- rewrite /extensional /=.
case => e s1.
case => e' s2.
move => H_eq.
by inversion H_eq; subst_max.
- case => e s.
rewrite /= /occurred /=.
move => H_eq.
exact: tot_map_label_injective.
Qed.
Context {fail_fst : FailureParams (@unlabeled_multi_params _ labeled_multi_fst)}.
Context {fail_snd : FailureParams (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {fail_map_congr : FailureParamsTotalMapCongruency fail_fst fail_snd base_map}.
Lemma tot_map_net_hd_step_failure_star_always :
forall s, event_step_star step_failure step_failure_init (hd s) ->
lb_step_execution lb_step_failure s ->
always (now (event_step_star step_failure step_failure_init)) (map tot_map_net_event s).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr fail_map_congr.
case => e s H_star H_exec.
apply: step_failure_star_lb_step_execution.
rewrite /=.
rewrite /tot_map_net_event /= /event_step_star /=.
apply: step_failure_tot_mapped_simulation_star_1.
by have <-: evt_a e = (fst (evt_a e), snd (evt_a e)) by destruct e, evt_a.
exact: lb_step_trace_execution_lb_step_failure_tot_map_net_infseq.
Qed.
(* lb_step_ordered_failure *)
Theorem lb_step_ordered_failure_tot_mapped_simulation_1 :
forall net net' failed failed' lb tr,
@lb_step_ordered_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_ordered_failure _ labeled_multi_snd (List.map tot_map_name failed, tot_map_onet net) (tot_map_label lb) (List.map tot_map_name failed', tot_map_onet net') (List.map tot_map_trace tr).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_step.
invcs H_step => //=.
- apply (@LabeledStepOrderedFailure_deliver _ _ _ _ _ _ (@tot_map_msg _ _ _ _ msg_map m) (List.map (@tot_map_msg _ _ _ _ msg_map) ms) (List.map tot_map_output out) (tot_map_data d) (@tot_map_name_msgs _ _ _ _ _ msg_map l) (@tot_map_name _ _ _ _ name_map from) (@tot_map_name _ _ _ _ name_map to)) => //=.
* rewrite /tot_map_onet /=.
rewrite 2!tot_map_name_inv_inverse.
by find_rewrite.
* exact: not_in_failed_not_in.
* rewrite /tot_map_onet /= tot_map_name_inv_inverse.
have H_q := @tot_net_handlers_eq _ _ _ _ _ _ _ multi_map_congr to from m (onwState net to).
rewrite /tot_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @tot_lb_net_handlers_eq _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ Heqp1.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
by repeat tuple_inversion.
* rewrite /tot_map_onet /=.
rewrite (@collate_tot_map_update2_eq _ _ _ _ _ _ name_map_bijective).
set f1 := fun _ => tot_map_data _.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2.
apply functional_extensionality => n.
rewrite /update.
break_if; break_if => //; first by rewrite -e tot_map_name_inverse_inv in n0.
by rewrite e tot_map_name_inv_inverse in n0.
by rewrite H_eq_f.
* by rewrite (@map_tot_map_trace_eq _ _ _ _ _ name_map).
- rewrite /tot_map_onet /=.
apply (@LabeledStepOrderedFailure_input _ _ (@tot_map_name _ _ _ _ name_map h) _ _ _ _ (List.map tot_map_output out) (tot_map_input inp) (tot_map_data d) (@tot_map_name_msgs _ _ _ _ _ msg_map l)).
* exact: not_in_failed_not_in.
* rewrite /tot_map_onet /= tot_map_name_inv_inverse.
have H_q := @tot_input_handlers_eq _ _ _ _ _ _ _ multi_map_congr h inp (onwState net h).
rewrite /tot_mapped_input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @tot_lb_input_handlers_eq _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ Heqp1.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
by repeat tuple_inversion.
* rewrite /tot_map_onet /=.
rewrite (@collate_tot_map_eq _ _ _ _ _ _ name_map_bijective).
set f1 := fun _ => tot_map_data _.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2.
apply functional_extensionality => n.
rewrite /update.
break_if; break_if => //; first by rewrite -e tot_map_name_inverse_inv in n0.
by rewrite e tot_map_name_inv_inverse in n0.
by rewrite H_eq_f.
* by rewrite (@map_tot_map_trace_eq _ _ _ _ _ name_map).
- rewrite tot_lb_label_silent_fst_snd.
exact: LabeledStepOrderedFailure_stutter.
Qed.
Definition tot_map_onet_event e :=
{| evt_a := (List.map tot_map_name (fst e.(evt_a)), tot_map_onet (snd e.(evt_a))) ;
evt_l := tot_map_label e.(evt_l) ;
evt_trace := List.map tot_map_trace e.(evt_trace) |}.
Lemma tot_map_onet_event_map_unfold : forall s,
Cons (tot_map_onet_event (hd s)) (map tot_map_onet_event (tl s)) = map tot_map_onet_event s.
Proof using.
by move => s; rewrite -map_Cons /= -{3}(recons s).
Qed.
Lemma lb_step_execution_lb_step_ordered_failure_tot_map_onet_infseq : forall s,
lb_step_execution lb_step_ordered_failure s ->
lb_step_execution lb_step_ordered_failure (map tot_map_onet_event s).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
cofix c.
move => s H_exec.
rewrite -tot_map_onet_event_map_unfold {1}/tot_map_onet_event /=.
inversion H_exec; subst => /=.
rewrite -tot_map_onet_event_map_unfold /= /tot_map_onet_event /=.
apply: (@Cons_lb_step_exec _ _ _ _ _ _ (List.map tot_map_trace tr)) => /=.
- apply: lb_step_ordered_failure_tot_mapped_simulation_1.
have <-: evt_a e = (fst (evt_a e), snd (evt_a e)) by destruct e, evt_a.
by have <-: evt_a e' = (fst (evt_a e'), snd (evt_a e')) by destruct e', evt_a.
- simpl in *.
find_rewrite.
by rewrite map_app.
- set e0 := {| evt_a := _ ; evt_l := _ ; evt_trace := _ |}.
have ->: e0 = tot_map_onet_event e' by [].
pose s' := Cons e' s0.
rewrite (tot_map_onet_event_map_unfold s').
exact: c.
Qed.
Lemma tot_map_onet_label_event_inf_often_occurred :
forall l s,
inf_often (now (occurred l)) s ->
inf_often (now (occurred (tot_map_label l))) (map tot_map_onet_event s).
Proof using.
move => l.
apply: always_map.
apply: eventually_map.
case => e s.
rewrite /= /occurred /=.
move => H_eq.
by rewrite H_eq.
Qed.
Lemma tot_map_onet_label_event_inf_often_occurred_conv :
forall l s,
inf_often (now (occurred (tot_map_label l))) (map tot_map_onet_event s) ->
inf_often (now (occurred l)) s.
Proof using tot_map_label_injective.
move => l.
apply: always_map_conv.
apply: eventually_map_conv => //.
- rewrite /extensional /=.
case => e s1.
case => e' s2.
move => H_eq.
by inversion H_eq; subst_max.
- rewrite /extensional /=.
case => e s1.
case => e' s2.
move => H_eq.
by inversion H_eq; subst_max.
- case => e s.
rewrite /= /occurred /=.
move => H_eq.
exact: tot_map_label_injective.
Qed.
Context {overlay_fst : NameOverlayParams (@unlabeled_multi_params _ labeled_multi_fst)}.
Context {overlay_snd : NameOverlayParams (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {overlay_map_congr : NameOverlayParamsTotalMapCongruency overlay_fst overlay_snd name_map}.
Context {fail_msg_fst : FailMsgParams (@unlabeled_multi_params _ labeled_multi_fst)}.
Context {fail_msg_snd : FailMsgParams (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {fail_msg_map_congr : FailMsgParamsTotalMapCongruency fail_msg_fst fail_msg_snd msg_map}.
Lemma tot_map_onet_hd_step_ordered_failure_star_always :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
always (now (event_step_star step_ordered_failure step_ordered_failure_init)) (map tot_map_onet_event s).
Proof using overlay_map_congr name_map_bijective multi_map_lb_congr multi_map_congr fail_msg_map_congr.
case => e s H_star H_exec.
apply: step_ordered_failure_star_lb_step_execution; last exact: lb_step_execution_lb_step_ordered_failure_tot_map_onet_infseq.
rewrite /= /tot_map_onet_event /= /event_step_star /=.
apply: step_ordered_failure_tot_mapped_simulation_star_1.
by have <-: evt_a e = (fst (evt_a e), snd (evt_a e)) by destruct e, evt_a.
Qed.
(* lb_step_ordered_dynamic_failure *)
Theorem lb_step_ordered_dynamic_failure_tot_mapped_simulation_1 :
forall net net' failed failed' lb tr,
@lb_step_ordered_dynamic_failure _ labeled_multi_fst (failed, net) lb (failed', net') tr ->
@lb_step_ordered_dynamic_failure _ labeled_multi_snd (List.map tot_map_name failed, tot_map_odnet net) (tot_map_label lb) (List.map tot_map_name failed', tot_map_odnet net') (List.map tot_map_trace tr).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
move => net net' failed failed' lb tr H_step.
invcs H_step => //=.
- rewrite /tot_map_odnet /=.
apply (@LabeledStepOrderedDynamicFailure_deliver _ _ _ _ _ _ (@tot_map_msg _ _ _ _ msg_map m) (List.map (@tot_map_msg _ _ _ _ msg_map) ms) (List.map tot_map_output out) (tot_map_data d) (tot_map_data d') (@tot_map_name_msgs _ _ _ _ _ msg_map l) (@tot_map_name _ _ _ _ name_map from) (@tot_map_name _ _ _ _ name_map to)) => //=.
* exact: not_in_failed_not_in.
* exact: in_failed_in.
* rewrite tot_map_name_inv_inverse.
by find_rewrite.
* rewrite 2!tot_map_name_inv_inverse.
by find_rewrite.
* have H_q := @tot_net_handlers_eq _ _ _ _ _ _ _ multi_map_congr to from m d.
rewrite /tot_mapped_net_handlers /net_handlers /= /unlabeled_net_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @tot_lb_net_handlers_eq _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ _ Heqp1.
rewrite /tot_mapped_lb_net_handlers_label in H_q'.
repeat break_let.
by repeat tuple_inversion.
* rewrite (@collate_tot_map_update2_eq _ _ _ _ _ _ name_map_bijective).
set f1 := fun _ => match _ with _ => _ end.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2 /update.
apply functional_extensionality => dst.
repeat break_if => //=; first by rewrite -e tot_map_name_inverse_inv in n.
by rewrite e tot_map_name_inv_inverse in n.
by rewrite H_eq_f.
* by rewrite (@map_tot_map_trace_eq _ _ _ _ _ name_map).
- rewrite /tot_map_odnet /=.
apply (@LabeledStepOrderedDynamicFailure_input _ _ (@tot_map_name _ _ _ _ name_map h) _ _ _ _ (List.map tot_map_output out) (tot_map_input inp) (tot_map_data d) (tot_map_data d') (@tot_map_name_msgs _ _ _ _ _ msg_map l)) => //=.
* exact: not_in_failed_not_in.
* exact: in_failed_in.
* rewrite tot_map_name_inv_inverse.
by find_rewrite.
* have H_q := @tot_input_handlers_eq _ _ _ _ _ _ _ multi_map_congr h inp d.
rewrite /tot_mapped_input_handlers /= /unlabeled_input_handlers in H_q.
repeat break_let.
repeat tuple_inversion.
have H_q' := @tot_lb_input_handlers_eq _ _ _ _ _ _ _ _ multi_map_lb_congr _ _ _ _ _ _ _ Heqp1.
rewrite /tot_mapped_lb_input_handlers_label in H_q'.
repeat break_let.
by repeat tuple_inversion.
* rewrite (@collate_tot_map_eq _ _ _ _ _ _ name_map_bijective).
set f1 := fun _ => match _ with _ => _ end.
set f2 := update _ _ _ _.
have H_eq_f: f1 = f2.
rewrite /f1 /f2 /update.
apply functional_extensionality => n.
repeat break_match; try by congruence.
* by rewrite e tot_map_name_inv_inverse in n0.
* by rewrite -e tot_map_name_inverse_inv in n0.
* by rewrite e tot_map_name_inv_inverse in n0.
by rewrite H_eq_f.
* by rewrite (@map_tot_map_trace_eq _ _ _ _ _ name_map).
- rewrite tot_lb_label_silent_fst_snd.
exact: LabeledStepOrderedDynamicFailure_stutter.
Qed.
Definition tot_map_odnet_event e :=
{| evt_a := (List.map tot_map_name (fst e.(evt_a)), tot_map_odnet (snd e.(evt_a))) ;
evt_l := tot_map_label e.(evt_l) ;
evt_trace := List.map tot_map_trace e.(evt_trace) |}.
Lemma tot_map_odnet_event_map_unfold : forall s,
Cons (tot_map_odnet_event (hd s)) (map tot_map_odnet_event (tl s)) = map tot_map_odnet_event s.
Proof using.
by move => s; rewrite -map_Cons /= -{3}(recons s).
Qed.
Lemma lb_step_execution_lb_step_ordered_dynamic_failure_tot_map_odnet_infseq : forall s,
lb_step_execution lb_step_ordered_dynamic_failure s ->
lb_step_execution lb_step_ordered_dynamic_failure (map tot_map_odnet_event s).
Proof using name_map_bijective multi_map_lb_congr multi_map_congr.
cofix c.
move => s H_exec.
rewrite -tot_map_odnet_event_map_unfold {1}/tot_map_odnet_event /=.
inversion H_exec; subst => /=.
rewrite -tot_map_odnet_event_map_unfold /= /tot_map_odnet_event /=.
apply: (@Cons_lb_step_exec _ _ _ _ _ _ (List.map tot_map_trace tr)) => /=.
- apply: lb_step_ordered_dynamic_failure_tot_mapped_simulation_1.
have <-: evt_a e = (fst (evt_a e), snd (evt_a e)) by destruct e, evt_a.
by have <-: evt_a e' = (fst (evt_a e'), snd (evt_a e')) by destruct e', evt_a.
- simpl in *.
find_rewrite.
by rewrite map_app.
- set e0 := {| evt_a := _ ; evt_l := _ ; evt_trace := _ |}.
have ->: e0 = tot_map_odnet_event e' by [].
pose s' := Cons e' s0.
rewrite (tot_map_odnet_event_map_unfold s').
exact: c.
Qed.
Lemma tot_map_odnet_label_event_inf_often_occurred :
forall l s,
inf_often (now (occurred l)) s ->
inf_often (now (occurred (tot_map_label l))) (map tot_map_odnet_event s).
Proof using.
move => l.
apply: always_map.
apply: eventually_map.
case => e s.
rewrite /= /occurred /=.
move => H_eq.
by rewrite H_eq.
Qed.
Lemma tot_map_odnet_label_event_inf_often_occurred_conv :
forall l s,
inf_often (now (occurred (tot_map_label l))) (map tot_map_odnet_event s) ->
inf_often (now (occurred l)) s.
Proof using tot_map_label_injective.
move => l.
apply: always_map_conv.
apply: eventually_map_conv => //.
- rewrite /extensional /=.
case => e s1.
case => e' s2.
move => H_eq.
by inversion H_eq; subst_max.
- rewrite /extensional /=.
case => e s1.
case => e' s2.
move => H_eq.
by inversion H_eq; subst_max.
- case => e s.
rewrite /= /occurred /=.
move => H_eq.
exact: tot_map_label_injective.
Qed.
Context {new_msg_fst : NewMsgParams (@unlabeled_multi_params _ labeled_multi_fst)}.
Context {new_msg_snd : NewMsgParams (@unlabeled_multi_params _ labeled_multi_snd)}.
Context {new_msg_map_congr : NewMsgParamsTotalMapCongruency new_msg_fst new_msg_snd msg_map}.
Lemma tot_map_odnet_hd_step_ordered_dynamic_failure_star_always :
forall s, event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init (hd s) ->
lb_step_execution lb_step_ordered_dynamic_failure s ->
always (now (event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init)) (map tot_map_odnet_event s).
Proof using overlay_map_congr new_msg_map_congr name_map_bijective multi_map_lb_congr multi_map_congr fail_msg_map_congr.
case => e s H_star H_exec.
apply: step_ordered_dynamic_failure_star_lb_step_execution; last exact: lb_step_execution_lb_step_ordered_dynamic_failure_tot_map_odnet_infseq.
rewrite /= /tot_map_odnet_event /= /event_step_star /=.
apply: step_ordered_dynamic_failure_tot_mapped_simulation_star_1.
by have <-: evt_a e = (fst (evt_a e), snd (evt_a e)) by destruct e, evt_a.
Qed.
End TotalMapExecutionSimulations.
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// mv_sie_read O 64
// mav_sie_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// mav_sie_write_misa I 28
// mav_sie_write_wordxl I 64
// EN_reset I 1
// EN_mav_write I 1
// EN_mav_sie_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
// (mav_sie_write_misa, mav_sie_write_wordxl) -> mav_sie_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIE(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
mv_sie_read,
mav_sie_write_misa,
mav_sie_write_wordxl,
EN_mav_sie_write,
mav_sie_write);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// value method mv_sie_read
output [63 : 0] mv_sie_read;
// actionvalue method mav_sie_write
input [27 : 0] mav_sie_write_misa;
input [63 : 0] mav_sie_write_wordxl;
input EN_mav_sie_write;
output [63 : 0] mav_sie_write;
// signals for module outputs
wire [63 : 0] mav_sie_write, mav_write, mv_read, mv_sie_read;
// register rg_mie
reg [11 : 0] rg_mie;
reg [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_sie_write,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_sie_write,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// inputs to muxes for submodule ports
wire [11 : 0] MUX_rg_mie$write_1__VAL_3;
// remaining internal signals
wire [11 : 0] mie__h92, x__h467, x__h901;
wire seie__h132,
seie__h562,
ssie__h126,
ssie__h556,
stie__h129,
stie__h559,
ueie__h131,
ueie__h561,
usie__h125,
usie__h555,
utie__h128,
utie__h558;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, mie__h92 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// value method mv_sie_read
assign mv_sie_read = { 52'd0, x__h467 } ;
// actionvalue method mav_sie_write
assign mav_sie_write = { 52'd0, x__h901 } ;
assign CAN_FIRE_mav_sie_write = 1'd1 ;
assign WILL_FIRE_mav_sie_write = EN_mav_sie_write ;
// inputs to muxes for submodule ports
assign MUX_rg_mie$write_1__VAL_3 =
{ rg_mie[11],
1'b0,
seie__h562,
ueie__h561,
rg_mie[7],
1'b0,
stie__h559,
utie__h558,
rg_mie[3],
1'b0,
ssie__h556,
usie__h555 } ;
// register rg_mie
always@(EN_mav_write or
mie__h92 or
EN_reset or EN_mav_sie_write or MUX_rg_mie$write_1__VAL_3)
case (1'b1)
EN_mav_write: rg_mie$D_IN = mie__h92;
EN_reset: rg_mie$D_IN = 12'd0;
EN_mav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3;
default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ;
endcase
assign rg_mie$EN = EN_mav_write || EN_mav_sie_write || EN_reset ;
// remaining internal signals
assign mie__h92 =
{ mav_write_wordxl[11],
1'b0,
seie__h132,
ueie__h131,
mav_write_wordxl[7],
1'b0,
stie__h129,
utie__h128,
mav_write_wordxl[3],
1'b0,
ssie__h126,
usie__h125 } ;
assign seie__h132 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign seie__h562 = mav_sie_write_misa[18] && mav_sie_write_wordxl[9] ;
assign ssie__h126 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign ssie__h556 = mav_sie_write_misa[18] && mav_sie_write_wordxl[1] ;
assign stie__h129 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign stie__h559 = mav_sie_write_misa[18] && mav_sie_write_wordxl[5] ;
assign ueie__h131 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign ueie__h561 = mav_sie_write_misa[13] && mav_sie_write_wordxl[8] ;
assign usie__h125 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign usie__h555 = mav_sie_write_misa[13] && mav_sie_write_wordxl[0] ;
assign utie__h128 = mav_write_misa[13] && mav_write_wordxl[4] ;
assign utie__h558 = mav_sie_write_misa[13] && mav_sie_write_wordxl[4] ;
assign x__h467 =
{ 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ;
assign x__h901 =
{ 2'd0,
seie__h562,
ueie__h561,
2'd0,
stie__h559,
utie__h558,
2'd0,
ssie__h556,
usie__h555 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIE
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
`include "config.vh"
/* Chien search, determines roots of a polynomial defined over a finite field */
module bch_chien_reg #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter REG = 1,
parameter SKIP = 0,
parameter STRIDE = 1
) (
input clk,
input start,
input [`BCH_M(P)-1:0] in,
output reg [`BCH_M(P)-1:0] out = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
wire [M-1:0] mul_out;
wire [M-1:0] mul_out_start;
if (!SKIP)
assign mul_out_start = in;
else begin
/* Initialize with coefficients of the error location polynomial */
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const2 #(M, lpow(M, REG * SKIP)) u_mult_start(
.standard_in(in),
.standard_out(mul_out_start)
);
else
parallel_standard_multiplier #(M) u_mult_start(
.standard_in1(in),
.standard_in2(lpow(M, REG * SKIP)),
.standard_out(mul_out_start)
);
end
/* Multiply by alpha^P */
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const1 #(M, lpow(M, REG * STRIDE)) u_mult(
.standard_in(out),
.standard_out(mul_out)
);
else
parallel_standard_multiplier #(M) u_mult(
.standard_in1(lpow(M, REG * STRIDE)),
.standard_in2(out),
.standard_out(mul_out)
);
always @(posedge clk)
out <= #TCQ start ? mul_out_start : mul_out;
endmodule
module bch_chien_expand #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter REG = 1,
parameter SKIP = 1
) (
input [`BCH_M(P)-1:0] in,
output [`BCH_M(P)-1:0] out
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
parallel_standard_multiplier_const1 #(M, lpow(M, REG * SKIP)) u_mult(
.standard_in(in),
.standard_out(out)
);
endmodule
/*
* Each register is loaded with the associated syndrome
* and multiplied by alpha^i each cycle.
*/
module bch_chien #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
/*
* For multi-bit output, Only implement every Nth register. Use async
* logic to fill in the remaining values.
*/
parameter REG_RATIO = BITS > 8 ? 8 : BITS
) (
input clk,
input start,
input [`BCH_SIGMA_SZ(P)-1:0] sigma,
output first, /* First valid output data */
output [`BCH_CHIEN_SZ(P)*BITS-1:0] chien
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam T = `BCH_T(P);
localparam SKIP = `BCH_K(P) - `BCH_DATA_BITS(P);
if (REG_RATIO > BITS)
chien_reg_ratio_must_be_less_than_or_equal_to_bits u_crrmbltoeqb();
genvar i, b;
generate
for (b = 0; b < BITS; b = b + 1) begin : BIT
for (i = 0; i <= T; i = i + 1) begin : REG
if (!(b % REG_RATIO)) begin : ORIG
bch_chien_reg #(M, i + 1, SKIP + b - BITS + 1 + `BCH_N(P), BITS) u_chien_reg(
.clk(clk),
.start(start),
.in(sigma[i*M+:M]),
.out(chien[((BITS-b-1)*(T+1)+i)*M+:M])
);
end else begin : EXPAND
bch_chien_expand #(M, i + 1, b % REG_RATIO) u_chien_expand(
.in(chien[((BITS-b+(b%REG_RATIO)-1)*(T+1)+i)*M+:M]),
.out(chien[((BITS-b-1)*(T+1)+i)*M+:M])
);
end
end
end
endgenerate
pipeline #(2) u_first_pipeline (
.clk(clk),
.i(start),
.o(first)
);
endmodule
module bch_chien_counter #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1
) (
input clk,
input first, /* First valid output data */
output last, /* Last valid output cycle */
output valid /* Outputting data */
);
`include "bch.vh"
localparam TCQ = 1;
localparam CYCLES = (`BCH_DATA_BITS(P) + BITS - 1) / BITS;
localparam M = `BCH_M(P);
if (CYCLES == 1) begin
assign last = first;
assign valid = first;
end else begin
reg _valid = 0;
reg _last = 0;
wire penult;
if (CYCLES == 2)
assign penult = first;
else if (CYCLES == 3)
assign penult = valid && !last;
else begin
wire [M-1:0] count;
lfsr_counter #(M) u_counter(
.clk(clk),
.reset(first),
.ce(valid),
.count(count)
);
assign penult = count == lfsr_count(M, CYCLES - 3);
end
always @(posedge clk) begin
if (first)
_valid <= #TCQ 1;
else if (last)
_valid <= #TCQ 0;
_last <= #TCQ penult;
end
assign last = _last;
assign valid = _valid;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ext_de1_sram.v
//
// *Module Description:
// openMSP430 interface with altera DE1's external async SRAM (256kwords x 16bits)
//
// *Author(s):
// - Vadim Akimov, [email protected]
module ext_de1_sram(
input clk,
// ram interface with openmsp430 core
input [ADDR_WIDTH-1:0] ram_addr,
input ram_cen,
input [1:0] ram_wen,
input [15:0] ram_din,
output reg [15:0] ram_dout,
// DE1's sram signals
inout [15:0] SRAM_DQ,
output reg [17:0] SRAM_ADDR,
output reg SRAM_UB_N,
output reg SRAM_LB_N,
output reg SRAM_WE_N,
output reg SRAM_CE_N,
output reg SRAM_OE_N
);
parameter ADDR_WIDTH = 9; // [8:0] - 512 words of 16 bits (1 kB) are only addressed by default
// we assume SRAM is fast enough to accomodate 1-cycle access rate of openmsp430. Also it must be fast
// enough to provide read data half cycle after read access begins. It is highly recommended to
// set all SRAM_ signals as "Fast Output Register" in quartus. Also set Fast Enable Register for SRAM_DQ.
// SRAM used in DE1 has zero setup and hold times for address and data in write cycle, so we can write data
// in one clock cycle.
//
// we emulate ram_cen behavior by not changing read data when ram_cen=1 (last read data remain on ram_dout)
reg [15:0] sram_dout;
reg rnw; // =1 - read, =0 - write (Read-Not_Write)
reg ena; // enable
// address is always loaded from core
always @(negedge clk)
begin
SRAM_ADDR <= { {18-ADDR_WIDTH{1'b0}}, ram_addr[ADDR_WIDTH-1:0] };
end
// some control signals
always @(negedge clk)
begin
if( !ram_cen && !(&ram_wen) )
rnw <= 1'b0;
else
rnw <= 1'b1;
ena <= ~ram_cen;
end
// store data for write cycle
always @(negedge clk)
sram_dout <= ram_din;
// bus control
assign SRAM_DQ = rnw ? {16{1'bZ}} : sram_dout;
// read cycle - data latching
always @(posedge clk)
begin
if( ena && rnw )
ram_dout <= SRAM_DQ;
end
// SRAM access signals
always @(negedge clk)
begin
if( !ram_cen )
begin
if( &ram_wen[1:0] ) // read access
begin
SRAM_CE_N <= 1'b0;
SRAM_OE_N <= 1'b0;
SRAM_WE_N <= 1'b1;
SRAM_UB_N <= 1'b0;
SRAM_LB_N <= 1'b0;
end
else // !(&ram_wen[1:0]) - write access
begin
SRAM_CE_N <= 1'b0;
SRAM_OE_N <= 1'b1;
SRAM_WE_N <= 1'b0;
SRAM_UB_N <= ram_wen[1];
SRAM_LB_N <= ram_wen[0];
end
end
else // ram_cen - idle
begin
SRAM_CE_N <= 1'b1;
SRAM_OE_N <= 1'b1;
SRAM_WE_N <= 1'b1;
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
end
end
endmodule
|
`default_nettype none
module thinpad_top(/*autoport*/
//inout
base_ram_data,
ext_ram_data,
flash_data,
sl811_data,
dm9k_data,
//output
base_ram_addr,
base_ram_be_n,
base_ram_ce_n,
base_ram_oe_n,
base_ram_we_n,
ext_ram_addr,
ext_ram_be_n,
ext_ram_ce_n,
ext_ram_oe_n,
ext_ram_we_n,
txd,
flash_address,
flash_rp_n,
flash_vpen,
flash_oe_n,
flash_ce,
flash_byte_n,
flash_we_n,
sl811_a0,
sl811_we_n,
sl811_rd_n,
sl811_cs_n,
sl811_rst_n,
sl811_drq,
dm9k_cmd,
dm9k_we_n,
dm9k_rd_n,
dm9k_cs_n,
dm9k_rst_n,
leds,
vga_pixel,
vga_hsync,
vga_vsync,
vga_clk,
vga_de,
//input
clk_in,
clk_uart_in,
rxd,
sl811_dack,
sl811_int,
dm9k_int,
dip_sw,
touch_btn);
input wire clk_in; //50MHz main clock input
input wire clk_uart_in; //11.0592MHz clock for UART
//Base memory signals
inout wire[31:0] base_ram_data;
output wire[19:0] base_ram_addr;
output wire[3:0] base_ram_be_n;
output wire base_ram_ce_n;
output wire base_ram_oe_n;
output wire base_ram_we_n;
assign base_ram_be_n=4'b0; //leave ByteEnable zero if you don't know what it is
//Extension memory signals
inout wire[31:0] ext_ram_data;
output wire[19:0] ext_ram_addr;
output wire[3:0] ext_ram_be_n;
output wire ext_ram_ce_n;
output wire ext_ram_oe_n;
output wire ext_ram_we_n;
assign ext_ram_be_n=4'b0;
//Serial port signals
output wire txd;
input wire rxd;
//Flash memory, JS28F640
output wire [21:0]flash_address;
output wire flash_rp_n;
output wire flash_vpen;
output wire flash_oe_n;
inout wire [15:0]flash_data;
output wire flash_ce;
output wire flash_byte_n;
output wire flash_we_n;
//SL811 USB controller signals
output wire sl811_a0;
inout wire[7:0] sl811_data;
output wire sl811_we_n;
output wire sl811_rd_n;
output wire sl811_cs_n;
output wire sl811_rst_n;
input wire sl811_dack;
input wire sl811_int;
output wire sl811_drq;
//DM9000 Ethernet controller signals
output wire dm9k_cmd;
inout wire[15:0] dm9k_data;
output wire dm9k_we_n;
output wire dm9k_rd_n;
output wire dm9k_cs_n;
output wire dm9k_rst_n;
input wire dm9k_int;
//LED, SegDisp, DIP SW, and BTN1~6
output wire[31:0] leds;
input wire[31:0] dip_sw;
input wire[5:0] touch_btn;
//Video output
output wire[7:0] vga_pixel;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_clk;
output wire vga_de;
//flash
wire [22:0] flash_addr;
wire [7:0] number;
assign flash_ce = 1'b0;
assign flash_address = flash_addr[22:1];
//wire sram_sramEnable;
//wire sram_writeEnable;
//wire sram_readEnable;
//assign base_ram_we_n = sram_writeEnable;
//assign ext_ram_we_n = sram_writeEnable;
//assign base_ram_ce_n = sram_sramEnable;
//assign ext_ram_ce_n = sram_sramEnable;
//assign base_ram_oe_n = sram_readEnable;
//assign ext_ram_oe_n = sram_readEnable;
//LED & DIP switches test
reg[23:0] counter;
reg[15:0] led_bits;
always@(posedge clk_in) begin
if(touch_btn[5])begin //reset
counter<=0;
led_bits[15:0] <= dip_sw[15:0]^dip_sw[31:16];
end
else begin
counter<= counter+1;
if(&counter)
led_bits[15:0] <= {led_bits[14:0],led_bits[15]};
end
end
assign leds[15:0] = led_bits;
//Serial port receive and transmit, 115200 baudrate, no parity
//wire [7:0] RxD_data;
//wire RxD_data_ready;
//async_receiver #(.ClkFrequency(11059200),.Baud(115200))
// uart_r(.clk(clk_uart_in),.RxD(rxd),.RxD_data_ready(RxD_data_ready),.RxD_data(RxD_data));
//async_transmitter #(.ClkFrequency(11059200),.Baud(115200))
// uart_t(.clk(clk_uart_in),.TxD(txd),.TxD_start(RxD_data_ready),.TxD_data(RxD_data)); //transmit data back
//// 7-Segment display decoder
SEG7_LUT segL(.oSEG1({leds[23:22],leds[19:17],leds[20],leds[21],leds[16]}), .iDIG(number[3:0]));
SEG7_LUT segH(.oSEG1({leds[31:30],leds[27:25],leds[28],leds[29],leds[24]}), .iDIG(number[7:4]));
//always @(posedge clk_uart_in) begin
// if(RxD_data_ready)
// number <= RxD_data; //show received data on segment display
//end
//VGA display pattern generation
wire [2:0] red,green;
wire [1:0] blue;
assign vga_pixel = {red,green,blue};
assign vga_clk = clk_in;
vga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 (
.clk(clk_in),
.hdata(red),
.vdata({blue,green}),
.hsync(vga_hsync),
.vsync(vga_vsync),
.data_enable(vga_de)
);
cpu top(
// .clk50(touch_btn[4]),
.clk50(clk_in),
.rst(!touch_btn[5]),
.sram_sramEnable_o(base_ram_ce_n),
.sram_writeEnable_o(base_ram_we_n),
.sram_readEnable_o(base_ram_oe_n),
.sram_addr_o(base_ram_addr),
.sram_data_io(base_ram_data),
.flash_flashByte_o(flash_byte_n),
.flash_flashVpen_o(flash_vpen),
.flash_flashRP_o(flash_rp_n),
.flash_flashSTS_o(1'b1),
.flash_flashEnable_o(),
.flash_flashCE1_o(),
.flash_flashCE2_o(),
.flash_readEnable_o(flash_oe_n),
.flash_writeEnable_o(flash_we_n),
.flash_addr_o(flash_addr),
.flash_data_io(flash_data),
.pc_output(number),
.led_o(),
.RxD(rxd),
.TxD(txd)
);
sram SRAM(
.addr_i(base_ram_addr),
//Enable
.en_i(base_ram_ce_n),
//Write
.we_i(base_ram_we_n),
//Output
.oe_i(base_ram_oe_n),
//Data
.data_io(base_ram_data)
);
endmodule
|
/*********************************************************************
* SYNOPSYS CONFIDENTIAL *
* *
* This is an unpublished, proprietary work of Synopsys, Inc., and *
* is fully protected under copyright and trade secret laws. You may *
* not view, use, disclose, copy, or distribute this file or any *
* information contained herein except pursuant to a valid written *
* license from Synopsys. *
*********************************************************************/
// Description: Wallace Tree for 32 x 32 Multiplier
//
// Wallace Carry Save Adder Tree
//
// Uses 4 levels of 4 to 2 Carry Save adders to sum the 16 partial products.
// The final sum is generated using a Carry Look-Ahead adder.
//
// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// | | | | | | | | | | | | | | | |
// +-+---+---+---+-+ +-+---+---+---+-+ +-+---+---+---+-+ +-+---+---+---+-+
// | CSA13 | | CSA12 | | CSA11 | | CSA10 |
// +---+-------+---+ +---+-------+---+ +---+-------+---+ +---+-------+---+
// | +------+ | +---+ +---+ | +------+ |
// +----------+ | | | | | | +----------+
// +-+---+---+---+-+ +-+---+---+---+-+
// | CSA21 | | CSA20 |
// +---+-------+---+ +---+-------+---+
// | +--------+ +---------+ |
// +------------+ | | +-------------+
// +-+---+---+---+-+
// | CSA30 |
// +---+-------+---+
// | +-+ Z Y[31]
// +-----+ | | |
// +-+---+---+---+-+
// | CSA40 |
// +---+-------+---+
// | |
// +---+-------+---+
// | CLA0 |
// +-------+-------+
// | Sum
//
module PP_Add_32Bits(Ovfl,Sum,PP15,PP14,PP13,PP12,PP11,PP10,PP9,PP8,
PP7,PP6,PP5,PP4,PP3,PP2,PP1,PP0,Y,Z);
output Ovfl; // CLA Overflow
output [31:0] Sum; // Sum of Partial Products
input [32:0] PP15; // Partial Product 15
input [32:0] PP14; // Partial Product 14
input [32:0] PP13; // Partial Product 13
input [32:0] PP12; // Partial Product 12
input [32:0] PP11; // Partial Product 11
input [32:0] PP10; // Partial Product 10
input [32:0] PP9; // Partial Product 9
input [32:0] PP8; // Partial Product 8
input [32:0] PP7; // Partial Product 7
input [32:0] PP6; // Partial Product 6
input [32:0] PP5; // Partial Product 5
input [32:0] PP4; // Partial Product 4
input [32:0] PP3; // Partial Product 3
input [32:0] PP2; // Partial Product 2
input [32:0] PP1; // Partial Product 1
input [32:0] PP0; // Partial Product 0
input [31:0] Y; // Mulitiplier, Y
input [31:0] Z; // Adder Z
wire Cin = 1'b0; // Carry In
wire Zero = 1'b0; // Carry In
// Partial Product Alignment and Wallace Tree Addition
//
// Note: Y[x] terms are included to complete Booth encoding. They are
// used for completing 2's complement when substacting the segment
// is required.
//
// First Level of Wallace Tree
//
wire [9:0] aPP15= { PP15[1:0], 1'b0, Y[29], 6'h00 };
wire [9:0] aPP14= { PP14[3:0], 1'b0, Y[27], 4'h0 };
wire [9:0] aPP13= { PP13[5:0], 1'b0, Y[25], 2'h0 };
wire [9:0] aPP12= { PP12[7:0], 1'b0, Y[23] };
wire [9:0] S13; // CSA Sum PP15:PP12
wire [9:0] C13; // CSA Carry PP15:PP12
wire Ovf13; // CSA Overflow
CSA_nBits #(10) CSA13(C13,S13,Ovf13,aPP15,aPP14,aPP13,aPP12,Zero);
wire [17:0] aPP11= { PP11[9:0], 1'b0, Y[21], 6'h00 };
wire [17:0] aPP10= { PP10[11:0], 1'b0, Y[19], 4'h0 };
wire [17:0] aPP9 = { PP9[13:0], 1'b0, Y[17], 2'h0 };
wire [17:0] aPP8 = { PP8[15:0], 1'b0, Y[15] };
wire [17:0] S12; // CSA Sum PP11:PP8
wire [17:0] C12; // CSA Carry PP11:PP8
wire Ovf12; // CSA Overflow
CSA_nBits #(18) CSA12(C12,S12,Ovf12,aPP11,aPP10,aPP9,aPP8,Zero);
wire [25:0] aPP7 = { PP7[17:0], 1'b0, Y[13], 6'h00 };
wire [25:0] aPP6 = { PP6[19:0], 1'b0, Y[11], 4'h0 };
wire [25:0] aPP5 = { PP5[21:0], 1'b0, Y[9], 2'h0 };
wire [25:0] aPP4 = { PP4[23:0], 1'b0, Y[7] };
wire [25:0] S11; // CSA Sum PP7:PP4
wire [25:0] C11; // CSA Carry PP7:PP4
wire Ovf11; // CSA Overflow
CSA_nBits #(26) CSA11(C11,S11,Ovf11,aPP7,aPP6,aPP5,aPP4,Zero);
wire [31:0] aPP3 = { PP3[25:0], 1'b0, Y[5], 4'h0 };
wire [31:0] aPP2 = { PP2[27:0], 1'b0, Y[3], 2'h0 };
wire [31:0] aPP1 = { PP1[29:0], 1'b0, Y[1] };
wire [31:0] aPP0 = { PP0[31:0] };
wire [31:0] S10; // CSA Sum PP3:PP0
wire [31:0] C10; // CSA Carry PP3:PP0
wire Ovf10; // CSA Overflow
CSA_nBits #(32) CSA10(C10,S10,Ovf10,aPP3,aPP2,aPP1,aPP0,Zero);
// Second Level of Wallace Tree
//
wire [17:0] S21; // CSA Sum PP15:PP8
wire [17:0] C21; // CSA Carry PP15:PP8
wire Ovf21; // CSA Overflow
CSA_nBits #(18) CSA21(C21,S21,Ovf21,C12,S12,{C13,8'h00},{S13,8'h00},Zero);
wire [31:0] S20; // CSA Sum PP7:PP0
wire [31:0] C20; // CSA Carry PP7:PP0
wire Ovf20; // CSA Overflow
CSA_nBits #(32) CSA20(C20,S20,Ovf20,C10,S10,{C11,6'h00},{S11,6'h00},Zero);
// Third Level of Wallace Tree
//
wire [31:0] S30; // CSA Sum PP15:PP0
wire [31:0] C30; // CSA Carry PP15:PP0
wire Ovf30; // CSA Overflow
CSA_nBits #(32) CSA30(C30,S30,Ovf30,C20,S20,{C21,14'h0000},{S21,14'h0000},Zero);
// Forth Level of Wallace Tree
//
wire [31:0] S40; // CSA Sum Z & Final Subtraction Fix
wire [31:0] C40; // CSA Carry Z & Final Sub Fix
wire Ovf40; // CSA Overflow Z & Final Sub Fix
CSA_nBits #(32) CSA40(C40,S40,Ovf40,C30,S30,Z,{1'b0,Y[31],30'h00000000},Zero);
// Final Carry Propagating Stage
//
wire ClaOvfl; // CLA Overflow
CLA_32Bit_Adder CLA1(ClaOvfl,Sum,C40,S40,Cin);
// Overflow Detection
//
assign Ovfl = Ovf13 | Ovf12 | Ovf11 | Ovf10 | Ovf21 | Ovf20 | Ovf30 | Ovf40 ;
// always #10 $display ($time,,,"Overflow %h %h %h %h %h %h %h %h %h",
// Ovf13,Ovf12,Ovf11,Ovf10,Ovf21,Ovf20,Ovf30,Ovf40,ClaOvfl);
endmodule
|
module check_command_fifo(
reset,
clk,
init_dram_done,
all_controller_command_fifo_empty,
finish_command_fifo0_empty_or_not,
finish_command_fifo1_empty_or_not,
finish_command_fifo2_empty_or_not,
finish_command_fifo3_empty_or_not,
finish_command_fifo4_empty_or_not,
finish_command_fifo5_empty_or_not,
finish_command_fifo6_empty_or_not,
finish_command_fifo7_empty_or_not,
finish_command_fifo8_empty_or_not,
finish_command_fifo0_out,
finish_command_fifo1_out,
finish_command_fifo2_out,
finish_command_fifo3_out,
finish_command_fifo4_out,
finish_command_fifo5_out,
finish_command_fifo6_out,
finish_command_fifo7_out,
finish_command_fifo8_out,
read_data_fifo0_out,
read_data_fifo1_out,
read_data_fifo2_out,
read_data_fifo3_out,
read_data_fifo4_out,
read_data_fifo5_out,
read_data_fifo6_out,
read_data_fifo7_out,
data_from_dram,
dram_ready,
rd_data_valid,
dram_permit,
pcie_data_send_fifo_out_prog_full,
pcie_command_send_fifo_full_or_not, //pcie_command_send_fifopcie_data_send_fifoǶԳƵģֻһfifoǷ
//output
finish_command_fifo0_out_en,
finish_command_fifo1_out_en,
finish_command_fifo2_out_en,
finish_command_fifo3_out_en,
finish_command_fifo4_out_en,
finish_command_fifo5_out_en,
finish_command_fifo6_out_en,
finish_command_fifo7_out_en,
finish_command_fifo8_out_en,
read_data_fifo0_out_en,
read_data_fifo1_out_en,
read_data_fifo2_out_en,
read_data_fifo3_out_en,
read_data_fifo4_out_en,
read_data_fifo5_out_en,
read_data_fifo6_out_en,
read_data_fifo7_out_en,
dram_request,
release_dram,
addr_to_dram_o,
data_to_dram,
dram_data_mask,
dram_en_o,
dram_read_or_write,
data_to_dram_en,
data_to_dram_end,
data_to_dram_ready,
pcie_data_send_fifo_in,
pcie_data_send_fifo_in_en,
pcie_command_send_fifo_in,
pcie_command_send_fifo_in_en,
left_capacity_final,//512GB flash有2的17次方个块
free_block_fifo_tails,
free_block_fifo_heads,
register_ready,
initial_dram_done,
state
);
`include"ftl_define.v"
input reset;
input clk;
input init_dram_done;
input all_controller_command_fifo_empty;
input finish_command_fifo0_empty_or_not;
input finish_command_fifo1_empty_or_not ;
input finish_command_fifo2_empty_or_not ;
input finish_command_fifo3_empty_or_not;
input finish_command_fifo4_empty_or_not ;
input finish_command_fifo5_empty_or_not;
input finish_command_fifo6_empty_or_not ;
input finish_command_fifo7_empty_or_not;
input finish_command_fifo8_empty_or_not;
input [COMMAND_WIDTH-1:0]finish_command_fifo0_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo1_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo2_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo3_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo4_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo5_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo6_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo7_out;
input [COMMAND_WIDTH-1:0]finish_command_fifo8_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo0_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo1_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo2_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo3_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo4_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo5_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo6_out;
input [DRAM_IO_WIDTH-1:0]read_data_fifo7_out;
input [DRAM_IO_WIDTH-1:0]data_from_dram;
input dram_ready;
input rd_data_valid;
input dram_permit;
input pcie_data_send_fifo_out_prog_full;
input pcie_command_send_fifo_full_or_not; //pcie_command_send_fifopcie_data_send_fifoǶԳƵģֻһfifoǷ
//output
input data_to_dram_ready;
output data_to_dram_en;
output data_to_dram_end;
output finish_command_fifo0_out_en;
output finish_command_fifo1_out_en;
output finish_command_fifo2_out_en;
output finish_command_fifo3_out_en;
output finish_command_fifo4_out_en;
output finish_command_fifo5_out_en;
output finish_command_fifo6_out_en;
output finish_command_fifo7_out_en;
output finish_command_fifo8_out_en;
output read_data_fifo0_out_en;
output read_data_fifo1_out_en;
output read_data_fifo2_out_en;
output read_data_fifo3_out_en;
output read_data_fifo4_out_en;
output read_data_fifo5_out_en;
output read_data_fifo6_out_en;
output read_data_fifo7_out_en;
output dram_request;
output release_dram;
output [DRAM_ADDR_WIDTH-1:0]addr_to_dram_o;
output [DRAM_IO_WIDTH-1:0]data_to_dram;
output [DRAM_MASK_WIDTH-1:0]dram_data_mask;
output dram_en_o;
output dram_read_or_write;
output [DRAM_IO_WIDTH-1:0]pcie_data_send_fifo_in;
output pcie_data_send_fifo_in_en;
output [COMMAND_WIDTH-1:0]pcie_command_send_fifo_in;
output pcie_command_send_fifo_in_en;
output [18:0]left_capacity_final;//512GB flash有2的17次方个块
output [127:0] free_block_fifo_tails;
output [127:0] free_block_fifo_heads;
output register_ready;
output initial_dram_done;
output [5:0] state;
reg finish_command_fifo0_out_en;
reg finish_command_fifo1_out_en;
reg finish_command_fifo2_out_en;
reg finish_command_fifo3_out_en;
reg finish_command_fifo4_out_en;
reg finish_command_fifo5_out_en;
reg finish_command_fifo6_out_en;
reg finish_command_fifo7_out_en;
reg finish_command_fifo8_out_en;
reg read_data_fifo0_out_en;
reg read_data_fifo1_out_en;
reg read_data_fifo2_out_en;
reg read_data_fifo3_out_en;
reg read_data_fifo4_out_en;
reg read_data_fifo5_out_en;
reg read_data_fifo6_out_en;
reg read_data_fifo7_out_en;
reg dram_request;
reg release_dram;
reg [DRAM_ADDR_WIDTH-1:0]addr_to_dram;
reg [DRAM_IO_WIDTH-1:0]data_to_dram;
reg [DRAM_MASK_WIDTH-1:0]dram_data_mask;
reg dram_en;
reg dram_read_or_write;
reg [DRAM_IO_WIDTH-1:0]pcie_data_send_fifo_in;
reg pcie_data_send_fifo_in_en;
reg [COMMAND_WIDTH-1:0]pcie_command_send_fifo_in;
reg pcie_command_send_fifo_in_en;
reg [DRAM_IO_WIDTH-1:0]data_tmp;
reg [18:0]left_capacity_final;//512GB flash有2的17次方个块
reg [127:0] free_block_fifo_tails;
reg [127:0] free_block_fifo_heads;
wire finish_command_fifo_empty_or_not;
assign finish_command_fifo_empty_or_not=finish_command_fifo0_empty_or_not & finish_command_fifo1_empty_or_not & finish_command_fifo2_empty_or_not & finish_command_fifo3_empty_or_not & finish_command_fifo4_empty_or_not & finish_command_fifo5_empty_or_not & finish_command_fifo6_empty_or_not & finish_command_fifo7_empty_or_not ;
parameter CHECK_COMMAND_FIFO0 =6'b000000;
parameter CHECK_COMMAND_FIFO1 =6'b000001;
parameter CHECK_COMMAND_FIFO2 =6'b000010;
parameter CHECK_COMMAND_FIFO3 =6'b000011;
parameter CHECK_COMMAND_FIFO4 =6'b000100;
parameter CHECK_COMMAND_FIFO5 =6'b000101;
parameter CHECK_COMMAND_FIFO6 =6'b000110;
parameter CHECK_COMMAND_FIFO7 =6'b000111;
parameter CHECK_COMMAND_FIFO8 =6'b001000;
parameter COMMAND_INTERPRET =6'b001001;
parameter INITIAL_DRAM_READ_COMMAND =6'b001010;
parameter REGISTER_READ_COMMAND =6'b001011;
parameter WAIT_DRAM =6'b001100;
parameter DATA_FIFO0_WRITE0 =6'b001101;
parameter DATA_FIFO0_WRITE1 =6'b001110;
parameter DATA_FIFO0_WRITE2 =6'b001111;
parameter DATA_FIFO0_WRITE3 =6'b010000;
parameter DATA_FIFO1_WRITE0 =6'b010001;
parameter DATA_FIFO1_WRITE1 =6'b010010;
parameter DATA_FIFO1_WRITE2 =6'b010011;
parameter DATA_FIFO1_WRITE3 =6'b010100;
parameter DATA_FIFO2_WRITE0 =6'b010101;
parameter DATA_FIFO2_WRITE1 =6'b010110;
parameter DATA_FIFO2_WRITE2 =6'b010111;
parameter DATA_FIFO2_WRITE3 =6'b011000;
parameter DATA_FIFO3_WRITE0 =6'b011001;
parameter DATA_FIFO3_WRITE1 =6'b011010;
parameter DATA_FIFO3_WRITE2 =6'b011011;
parameter DATA_FIFO3_WRITE3 =6'b011100;
parameter DATA_FIFO4_WRITE0 =6'b011101;
parameter DATA_FIFO4_WRITE1 =6'b011110;
parameter DATA_FIFO4_WRITE2 =6'b011111;
parameter DATA_FIFO4_WRITE3 =6'b100000;
parameter DATA_FIFO5_WRITE0 =6'b100001;
parameter DATA_FIFO5_WRITE1 =6'b100010;
parameter DATA_FIFO5_WRITE2 =6'b100011;
parameter DATA_FIFO5_WRITE3 =6'b100100;
parameter DATA_FIFO6_WRITE0 =6'b100101;
parameter DATA_FIFO6_WRITE1 =6'b100110;
parameter DATA_FIFO6_WRITE2 =6'b100111;
parameter DATA_FIFO6_WRITE3 =6'b101000;
parameter DATA_FIFO7_WRITE0 =6'b101001;
parameter DATA_FIFO7_WRITE1 =6'b101010;
parameter DATA_FIFO7_WRITE2 =6'b101011;
parameter DATA_FIFO7_WRITE3 =6'b101100;
parameter READ_FROM_CACHE0 =6'b101101;
parameter READ_FROM_CACHE1 =6'b101110;
parameter READ_FROM_CACHE2 =6'b101111;
parameter READ_FROM_CACHE3 =6'b110000;
parameter PCIE_COMMAND_SEND =6'b110001;
parameter GET_ENTRY0 =6'b110010;
parameter GET_ENTRY1 =6'b110011;
parameter RECEIVE_ENTRY0 =6'b110100;
parameter RECEIVE_ENTRY1 =6'b110101;
parameter RECEIVE_ENTRY2 =6'b110110;
parameter READY_FOR_CHECK_HIT =6'b110111;
parameter CHECK_HIT =6'b111000;
parameter WAIT_FOR_TWO_CYCLE =6'b111001;
parameter WRITE_ENTRY_BACK0 =6'b111010;
parameter WRITE_ENTRY_BACK1 =6'b111011;
parameter UNLOCK_DRAM =6'b111100;
parameter FINISH =6'b111101;
parameter CHECK_INIT_DRAM_DONE =6'b111110;
reg [COMMAND_WIDTH-1:0]controller_command;
reg [DRAM_ADDR_WIDTH-1:0] dram_addr;
reg [5:0] state;
reg [5:0] state_buf; //0~8 command fifoת
reg [5:0] state_buf1; //read:8read_data_fifo_out write:ֱӳlockλ
reg [9:0]count;
reg [9:0]count_read;
reg [511:0]data_from_dram_buf;
reg [63:0]dram_data_mask_buf;
reg [7:0]hit_flag;
reg [DRAM_IO_WIDTH-1:0] entries;
reg register_ready;
reg initial_dram_done;
reg read_or_initial;
parameter COMMANDS_ISSUE0 =2'b00;
parameter COMMANDS_ISSUE1 =2'b01;
parameter COMMANDS_ISSUE2 =2'b10;
parameter COMMANDS_ISSUE3 =2'b11;
reg data_to_dram_en;
reg data_to_dram_end;
reg ci_en;
reg [DRAM_ADDR_WIDTH-1:0] ci_addr;
reg [31:0] ci_num;
reg [9:0] ci_cmd_cnt;
reg [9:0] ci_data_cnt;
reg ci_done;
reg [1:0] ci_state;
reg flag;
reg dram_en_ci;
reg [DRAM_ADDR_WIDTH-1:0] addr_to_dram_ci;
assign dram_en_o=dram_en_ci|dram_en;
assign addr_to_dram_o=(dram_en_ci)? addr_to_dram_ci:addr_to_dram;
always@ (posedge clk or negedge reset)
begin
if(!reset)
begin
finish_command_fifo0_out_en<= 0;
finish_command_fifo1_out_en<= 0;
finish_command_fifo2_out_en<= 0;
finish_command_fifo3_out_en<= 0;
finish_command_fifo4_out_en<= 0;
finish_command_fifo5_out_en<= 0;
finish_command_fifo6_out_en<= 0;
finish_command_fifo7_out_en<= 0;
finish_command_fifo8_out_en<= 0;
read_data_fifo0_out_en <= 0;
read_data_fifo1_out_en <= 0;
read_data_fifo2_out_en <= 0;
read_data_fifo3_out_en <= 0;
read_data_fifo4_out_en <= 0;
read_data_fifo5_out_en <= 0;
read_data_fifo6_out_en <= 0;
read_data_fifo7_out_en <= 0;
dram_request <= 0;
release_dram <= 0;
addr_to_dram <= 0;
data_to_dram <= 0;
dram_data_mask <= 0;
dram_en <= 0;
dram_read_or_write <= 0;
pcie_data_send_fifo_in <= 0;
pcie_data_send_fifo_in_en <= 0;
pcie_command_send_fifo_in <= 0;
pcie_command_send_fifo_in_en<= 0;
dram_addr <= 0;
state <= CHECK_COMMAND_FIFO0;//CHECK_INIT_DRAM_DONE
state_buf <= 0;
state_buf1 <= 0;
count <= 0;
count_read <= 0;
data_from_dram_buf <= 0;
dram_data_mask_buf <= 0;
hit_flag <= 0;
entries <= 0;
left_capacity_final <= 0; //512GB flash有2的19次方个块
free_block_fifo_tails <= 0;
free_block_fifo_heads <= 0;
register_ready <= 0;
read_or_initial <= 0;
initial_dram_done <= 0; //debug: ignore initial dram
ci_en <= 0;
ci_addr <= 0;
ci_num <= 0;
ci_data_cnt <= 0;
data_to_dram_en <= 0;
data_to_dram_end <= 0;
flag <= 0;
end
else
begin
case (state)
/*CHECK_INIT_DRAM_DONE:
begin
if(init_dram_done && all_controller_command_fifo_empty == 1'b1)
begin
//register_ready <= 1'b1;
initial_dram_done <=1'b1;
left_capacity_final <= 19'b111_11111000_00000000;
free_block_fifo_heads <= 0;
free_block_fifo_tails <= 128'b0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001;
state <= CHECK_COMMAND_FIFO0;
end
else
state <= CHECK_INIT_DRAM_DONE;
end*/
CHECK_COMMAND_FIFO0://00
begin
if(register_ready == 1'b1 && all_controller_command_fifo_empty == 1'b1)
begin
initial_dram_done <=1'b1;
end
if(finish_command_fifo0_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo0_out_en <= 1;
controller_command<=finish_command_fifo0_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO1; //ָһfifoת
state_buf1<=DATA_FIFO0_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO1;
end
end
CHECK_COMMAND_FIFO1://01
begin
if(finish_command_fifo1_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo1_out_en <= 1;
controller_command<=finish_command_fifo1_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO2; //ָһfifoת
state_buf1<=DATA_FIFO1_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO2;
end
end
CHECK_COMMAND_FIFO2://02
begin
if(finish_command_fifo2_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo2_out_en <= 1;
controller_command<=finish_command_fifo2_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO3; //ָһfifoת
state_buf1<=DATA_FIFO2_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO3;
end
end
CHECK_COMMAND_FIFO3://03
begin
if(finish_command_fifo3_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo3_out_en <= 1;
controller_command<=finish_command_fifo3_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO4; //ָһfifoת
state_buf1<=DATA_FIFO3_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO4;
end
end
CHECK_COMMAND_FIFO4://04
begin
if(finish_command_fifo4_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo4_out_en <= 1;
controller_command<=finish_command_fifo4_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO5; //ָһfifoת
state_buf1<=DATA_FIFO4_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO5;
end
end
CHECK_COMMAND_FIFO5://05
begin
if(finish_command_fifo5_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo5_out_en <= 1;
controller_command<=finish_command_fifo5_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO6; //ָһfifoת
state_buf1<=DATA_FIFO5_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO6;
end
end
CHECK_COMMAND_FIFO6://06
begin
if(finish_command_fifo6_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo6_out_en <= 1;
controller_command<=finish_command_fifo6_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO7; //ָһfifoת
state_buf1<=DATA_FIFO6_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO7;
end
end
CHECK_COMMAND_FIFO7://07
begin
if(finish_command_fifo7_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo7_out_en <= 1;
controller_command<=finish_command_fifo7_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO8; //ָһfifoת
state_buf1<=DATA_FIFO7_WRITE0;
end
else
begin
state <= CHECK_COMMAND_FIFO8;
end
end
CHECK_COMMAND_FIFO8://08
begin
if(finish_command_fifo8_empty_or_not==0)//finish_command_fifo0
begin
finish_command_fifo8_out_en <= 1;
controller_command<=finish_command_fifo8_out;
state <= COMMAND_INTERPRET;
state_buf <= CHECK_COMMAND_FIFO0; //ָһfifoת
state_buf1<=READ_FROM_CACHE0; //cache
end
else
begin
state <= CHECK_COMMAND_FIFO0;
end
end
COMMAND_INTERPRET://09
begin
finish_command_fifo0_out_en <= 0;//λ
finish_command_fifo1_out_en <= 0;//λ
finish_command_fifo2_out_en <= 0;//λ
finish_command_fifo3_out_en <= 0;//λ
finish_command_fifo4_out_en <= 0;//λ
finish_command_fifo5_out_en <= 0;//λ
finish_command_fifo6_out_en <= 0;//λ
finish_command_fifo7_out_en <= 0;//λ
finish_command_fifo8_out_en <= 0;//λ
case(controller_command[127:126]) //125位标识flush与否
READ:
begin
case(controller_command[124:123])
2'b00:
begin
read_or_initial <= 1;
// dram_addr<=CACHE_BASE+{controller_command[49:32], 11'b0};
dram_addr<=CACHE_BASE+{controller_command[50:32], 9'b0}; //cache_address 19+9=28
if(pcie_data_send_fifo_out_prog_full==1'b0)
state<=WAIT_DRAM;//8 read_data_fifo_out
else
state<=COMMAND_INTERPRET;//wait until pcie_command_send_fifo not full
end
2'b10:
begin
state <= INITIAL_DRAM_READ_COMMAND;
read_or_initial <= 0;
end
2'b01:
begin
count<=0;
state <= REGISTER_READ_COMMAND;
end
default:state <= CHECK_COMMAND_FIFO0;
endcase
end
WRITE:
begin
state <= WAIT_DRAM;
count<=0;
state_buf1<=GET_ENTRY0;//дcache滻ֱӳ
end
default: state <= CHECK_COMMAND_FIFO0;
endcase
end
INITIAL_DRAM_READ_COMMAND: //001010
begin
// dram_addr<={controller_command[49:32],11'b0};
dram_addr<={controller_command[51:32],9'b0};
state<=WAIT_DRAM;//8read_data_fifo_out
end
WAIT_DRAM: //001100
begin
if(dram_permit)
begin
dram_request <= 0;
state <= state_buf1;
end
else
begin
dram_request<=1;//dram
state<=WAIT_DRAM;
end
end
REGISTER_READ_COMMAND: //001011
begin
if(count==0)
begin
register_ready <=1;
read_data_fifo0_out_en<=1;
//left_capacity_final<=read_data_fifo0_out[255:239];
//free_block_fifo_heads <=read_data_fifo0_out[238:127];
//free_block_fifo_tails <=read_data_fifo0_out[126:15];
left_capacity_final <= 19'b111_11111000_00000000;
free_block_fifo_heads <= 0;
free_block_fifo_tails <= 128'b0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001_0000000000000001;
count <=count+1;
end
else if(count<DRAM_COUNT*2)
begin
read_data_fifo0_out_en<=1;
count <=count+1;
end
else
begin
count <=0;
read_data_fifo0_out_en<=0;
state <=FINISH;
end
end
///////////////00000000000000000000000///////////////
DATA_FIFO0_WRITE0://001101
begin
read_data_fifo0_out_en<=1;
state<=DATA_FIFO0_WRITE1;
end
DATA_FIFO0_WRITE1://001110
begin
read_data_fifo0_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo0_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo0_out;
read_data_fifo0_out_en<=1;
state <= DATA_FIFO0_WRITE2;
end
else
begin
state<=DATA_FIFO0_WRITE1;
end
end
DATA_FIFO0_WRITE2://001111
begin
ci_en <=0;
read_data_fifo0_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo0_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo0_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo0_out_en<=1;
state <= DATA_FIFO0_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo0_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo0_out_en<=1;
flag <=0;
state <= DATA_FIFO0_WRITE3;
end
else
state <= DATA_FIFO0_WRITE2;
end
DATA_FIFO0_WRITE3://010000
begin
read_data_fifo0_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo0_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo0_out;
read_data_fifo0_out_en <= 1;
state <= DATA_FIFO0_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo0_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo0_out_en <= 1;
flag <=0;
state <= DATA_FIFO0_WRITE2;
end
else
state <= DATA_FIFO0_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo0_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo0_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo0_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO0_WRITE3;
end
end
////////////////////11111111111111111111111111///////////
DATA_FIFO1_WRITE0://010010
begin
read_data_fifo1_out_en<=1;
state<=DATA_FIFO1_WRITE1;
end
DATA_FIFO1_WRITE1://010011
begin
read_data_fifo1_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo1_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo1_out;
read_data_fifo1_out_en<=1;
state <= DATA_FIFO1_WRITE2;
end
else
begin
state<=DATA_FIFO1_WRITE1;
end
end
DATA_FIFO1_WRITE2://010011
begin
ci_en <=0;
read_data_fifo1_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo1_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo1_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo1_out_en<=1;
state <= DATA_FIFO1_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo1_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo1_out_en<=1;
flag <=0;
state <= DATA_FIFO1_WRITE3;
end
else
state <= DATA_FIFO1_WRITE2;
end
DATA_FIFO1_WRITE3://010100
begin
read_data_fifo1_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo1_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo1_out;
read_data_fifo1_out_en <= 1;
state <= DATA_FIFO1_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo1_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo1_out_en <= 1;
flag <=0;
state <= DATA_FIFO1_WRITE2;
end
else
state <= DATA_FIFO1_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo1_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo1_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo1_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO1_WRITE3;
end
end
///////////////////22222222222222222222222222222222222222/////////////
DATA_FIFO2_WRITE0://0c read_data_fifo2
begin
read_data_fifo2_out_en<=1;
state<=DATA_FIFO2_WRITE1;
end
DATA_FIFO2_WRITE1://0d
begin
read_data_fifo2_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo2_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo2_out;
read_data_fifo2_out_en<=1;
state <= DATA_FIFO2_WRITE2;
end
else
begin
state<=DATA_FIFO2_WRITE1;
end
end
DATA_FIFO2_WRITE2://0e
begin
ci_en <=0;
read_data_fifo2_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo2_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo2_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo2_out_en<=1;
state <= DATA_FIFO2_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo2_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo2_out_en<=1;
flag <=0;
state <= DATA_FIFO2_WRITE3;
end
else
state <= DATA_FIFO2_WRITE2;
end
DATA_FIFO2_WRITE3://0f
begin
read_data_fifo2_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo2_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo2_out;
read_data_fifo2_out_en <= 1;
state <= DATA_FIFO2_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo2_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo2_out_en <= 1;
flag <=0;
state <= DATA_FIFO2_WRITE2;
end
else
state <= DATA_FIFO2_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo2_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo2_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo2_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO2_WRITE3;
end
end
///////////33333333333333333333333333333/////////
DATA_FIFO3_WRITE0://0c read_data_fifo3
begin
read_data_fifo3_out_en<=1;
state<=DATA_FIFO3_WRITE1;
end
DATA_FIFO3_WRITE1://0d
begin
read_data_fifo3_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo3_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo3_out;
read_data_fifo3_out_en<=1;
state <= DATA_FIFO3_WRITE2;
end
else
begin
state<=DATA_FIFO3_WRITE1;
end
end
DATA_FIFO3_WRITE2://0e
begin
ci_en <=0;
read_data_fifo3_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo3_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo3_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo3_out_en<=1;
state <= DATA_FIFO3_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo3_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo3_out_en<=1;
flag <=0;
state <= DATA_FIFO3_WRITE3;
end
else
state <= DATA_FIFO3_WRITE2;
end
DATA_FIFO3_WRITE3://0f
begin
read_data_fifo3_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo3_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo3_out;
read_data_fifo3_out_en <= 1;
state <= DATA_FIFO3_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo3_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo3_out_en <= 1;
flag <=0;
state <= DATA_FIFO3_WRITE2;
end
else
state <= DATA_FIFO3_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo3_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo3_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo3_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO3_WRITE3;
end
end
////////////////444444444444444444//////////////////
DATA_FIFO4_WRITE0://0c read_data_fifo4
begin
read_data_fifo4_out_en<=1;
state<=DATA_FIFO4_WRITE1;
end
DATA_FIFO4_WRITE1://0d
begin
read_data_fifo4_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo4_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo4_out;
read_data_fifo4_out_en<=1;
state <= DATA_FIFO4_WRITE2;
end
else
begin
state<=DATA_FIFO4_WRITE1;
end
end
DATA_FIFO4_WRITE2://0e
begin
ci_en <=0;
read_data_fifo4_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo4_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo4_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo4_out_en<=1;
state <= DATA_FIFO4_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo4_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo4_out_en<=1;
flag <=0;
state <= DATA_FIFO4_WRITE3;
end
else
state <= DATA_FIFO4_WRITE2;
end
DATA_FIFO4_WRITE3://0f
begin
read_data_fifo4_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo4_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo4_out;
read_data_fifo4_out_en <= 1;
state <= DATA_FIFO4_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo4_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo4_out_en <= 1;
flag <=0;
state <= DATA_FIFO4_WRITE2;
end
else
state <= DATA_FIFO4_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo4_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo4_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo4_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO4_WRITE3;
end
end
//////55555555555555555////////////
DATA_FIFO5_WRITE0://0c read_data_fifo5
begin
read_data_fifo5_out_en<=1;
state<=DATA_FIFO5_WRITE1;
end
DATA_FIFO5_WRITE1://0d
begin
read_data_fifo5_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo5_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo5_out;
read_data_fifo5_out_en<=1;
state <= DATA_FIFO5_WRITE2;
end
else
begin
state<=DATA_FIFO5_WRITE1;
end
end
DATA_FIFO5_WRITE2://0e
begin
ci_en <=0;
read_data_fifo5_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo5_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo5_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo5_out_en<=1;
state <= DATA_FIFO5_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo5_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo5_out_en<=1;
flag <=0;
state <= DATA_FIFO5_WRITE3;
end
else
state <= DATA_FIFO5_WRITE2;
end
DATA_FIFO5_WRITE3://0f
begin
read_data_fifo5_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo5_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo5_out;
read_data_fifo5_out_en <= 1;
state <= DATA_FIFO5_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo5_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo5_out_en <= 1;
flag <=0;
state <= DATA_FIFO5_WRITE2;
end
else
state <= DATA_FIFO5_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo5_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo5_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo5_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO5_WRITE3;
end
end
/////////6666666666666666/////////////////
DATA_FIFO6_WRITE0://0c read_data_fifo6
begin
read_data_fifo6_out_en<=1;
state<=DATA_FIFO6_WRITE1;
end
DATA_FIFO6_WRITE1://0d
begin
read_data_fifo6_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo6_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo6_out;
read_data_fifo6_out_en<=1;
state <= DATA_FIFO6_WRITE2;
end
else
begin
state<=DATA_FIFO6_WRITE1;
end
end
DATA_FIFO6_WRITE2://0e
begin
ci_en <=0;
read_data_fifo6_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo6_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo6_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo6_out_en<=1;
state <= DATA_FIFO6_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo6_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo6_out_en<=1;
flag <=0;
state <= DATA_FIFO6_WRITE3;
end
else
state <= DATA_FIFO6_WRITE2;
end
DATA_FIFO6_WRITE3://0f
begin
read_data_fifo6_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo6_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo6_out;
read_data_fifo6_out_en <= 1;
state <= DATA_FIFO6_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo6_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo6_out_en <= 1;
flag <=0;
state <= DATA_FIFO6_WRITE2;
end
else
state <= DATA_FIFO6_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo6_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo6_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo6_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO6_WRITE3;
end
end
////////////7777777777777777777/////////////
DATA_FIFO7_WRITE0://0c read_data_fifo7
begin
read_data_fifo7_out_en<=1;
state<=DATA_FIFO7_WRITE1;
end
DATA_FIFO7_WRITE1://0d
begin
read_data_fifo7_out_en<=0;
if(ci_done)
begin
ci_en <=1;
dram_read_or_write <= 0;//write
ci_addr <=dram_addr;
ci_num<=DRAM_COUNT; //256*512b=16KB
data_to_dram_en <= 1'b1;
data_to_dram <= read_data_fifo7_out;
dram_data_mask<=32'h0;//no mask
ci_data_cnt <= 0;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo7_out;
read_data_fifo7_out_en<=1;
state <= DATA_FIFO7_WRITE2;
end
else
begin
state<=DATA_FIFO7_WRITE1;
end
end
DATA_FIFO7_WRITE2://0e
begin
ci_en <=0;
read_data_fifo7_out_en<=0;//
pcie_data_send_fifo_in_en<=0;
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo7_out;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo7_out;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo7_out_en<=1;
state <= DATA_FIFO7_WRITE3;
end
else if (!flag) //if !data_to_dram_ready, pcie_data_rec_fifo_i needs to be stored.
begin
data_tmp <= read_data_fifo7_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
ci_data_cnt <= ci_data_cnt+1;
if(ci_data_cnt<ci_num-1)
read_data_fifo7_out_en<=1;
flag <=0;
state <= DATA_FIFO7_WRITE3;
end
else
state <= DATA_FIFO7_WRITE2;
end
DATA_FIFO7_WRITE3://0f
begin
read_data_fifo7_out_en<=0;
pcie_data_send_fifo_in_en<=0;
if(ci_data_cnt<ci_num)
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <=read_data_fifo7_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=read_data_fifo7_out;
read_data_fifo7_out_en <= 1;
state <= DATA_FIFO7_WRITE2;
end
else if (!flag)
begin
data_tmp <= read_data_fifo7_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b1;
pcie_data_send_fifo_in_en<=read_or_initial;
pcie_data_send_fifo_in<=data_tmp;
read_data_fifo7_out_en <= 1;
flag <=0;
state <= DATA_FIFO7_WRITE2;
end
else
state <= DATA_FIFO7_WRITE3;
end
else
begin
if (data_to_dram_ready & !flag)
begin
dram_data_mask<=32'h0;
data_to_dram <= read_data_fifo7_out;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=read_data_fifo7_out;
state <= PCIE_COMMAND_SEND;
end
else if (!flag)
begin
data_tmp <= read_data_fifo7_out;
flag <=1;
end
else if(data_to_dram_ready)
begin
dram_data_mask<=32'h0;
data_to_dram <= data_tmp;
data_to_dram_end <= 1'b0;
data_to_dram_en <= 1'b0;
//pcie_data_send_fifo_in_en<=read_or_initial;
//pcie_data_send_fifo_in<=data_tmp;
flag <=0;
state <= PCIE_COMMAND_SEND;
end
else
state <= DATA_FIFO7_WRITE3;
end
end
READ_FROM_CACHE0://101101
begin
pcie_data_send_fifo_in_en<=0;//Ĭϲpcie_data_send_fifo
if(rd_data_valid)
begin
pcie_data_send_fifo_in_en<=1;
pcie_data_send_fifo_in<=data_from_dram;
count_read<=count_read+1;//նٸ
end
dram_en <= 1;
dram_read_or_write <= 1;//read
addr_to_dram <=dram_addr;
state<=READ_FROM_CACHE1;
end
READ_FROM_CACHE1://101110
begin
pcie_data_send_fifo_in_en<=0;//Ĭϲpcie_data_send_fifo
if(rd_data_valid)
begin
pcie_data_send_fifo_in_en<=1;
pcie_data_send_fifo_in<=data_from_dram;
count_read<=count_read+1;//նٸ
end
if(dram_ready)
begin
dram_en <=0;
count <= count + 1;
dram_addr<=dram_addr+8;
state <= READ_FROM_CACHE2;
end
end
READ_FROM_CACHE2://101111
begin
pcie_data_send_fifo_in_en<=0;//Ĭϲpcie_data_send_fifo
if(rd_data_valid)
begin
pcie_data_send_fifo_in_en<=1;
pcie_data_send_fifo_in<=data_from_dram;
count_read<=count_read+1;//նٸ
end
if(count>=DRAM_COUNT)//256ζ256*512b=16KBΪһҳС
begin
state <= READ_FROM_CACHE3;
count<=0;
end
else
begin
state <= READ_FROM_CACHE1;
dram_en <= 1;
dram_read_or_write <= 1;//read
addr_to_dram <=dram_addr;
end
end
READ_FROM_CACHE3: //110000
begin
pcie_data_send_fifo_in_en<=0;//Ĭϲpcie_data_send_fifo
if(rd_data_valid)
begin
pcie_data_send_fifo_in_en<=1;
pcie_data_send_fifo_in<=data_from_dram;
count_read<=count_read+1;//նٸ
end
if(count_read>=DRAM_COUNT*2)//512256b
begin
state <= PCIE_COMMAND_SEND;//ӳ
count_read<=0;
end
else
begin
state<=READ_FROM_CACHE3;
end
end
PCIE_COMMAND_SEND://110001
begin
pcie_data_send_fifo_in_en<=0;
if(read_or_initial==1'b1)
begin
if(pcie_command_send_fifo_full_or_not==1'b0)
begin
pcie_command_send_fifo_in_en<=read_or_initial;//pcie_command_send_fifo
pcie_command_send_fifo_in<=controller_command;
state<=GET_ENTRY0;//8read_data_fifo_out
end
end
else
if(ci_done == 1'b1)
begin
release_dram <= 1;
state<=FINISH;
end
end
GET_ENTRY0://110010
begin
pcie_command_send_fifo_in_en<=1'b0;
if(ci_done == 1'b1)
begin
dram_en <= 1;
dram_read_or_write <= 1;//read
// addr_to_dram <= {controller_command[13:1], 3'b000} + CACHE_ENTRY_BASE;
addr_to_dram <= {controller_command[15:1], 3'b000} + CACHE_ENTRY_BASE;
state<=GET_ENTRY1;
end
end
GET_ENTRY1://110011
begin
if(dram_ready)
begin
dram_en <= 0;
state <= RECEIVE_ENTRY0;
end
else
begin
state<=GET_ENTRY1;
end
end
RECEIVE_ENTRY0: //110100
begin
if(rd_data_valid)
begin
state <= RECEIVE_ENTRY1;
data_from_dram_buf[255:0]<=data_from_dram;
end
else
state<=RECEIVE_ENTRY0;
end
RECEIVE_ENTRY1: //110101
begin
if(rd_data_valid)
begin
state <= RECEIVE_ENTRY2;
data_from_dram_buf[511:256]<=data_from_dram;
end
else
state<=RECEIVE_ENTRY1;
end
RECEIVE_ENTRY2://110110
begin
if(controller_command[0]==0)
begin
entries<=data_from_dram_buf[255:0];
dram_data_mask_buf<=64'hffffffff_00000000;
end
else
begin
entries<=data_from_dram_buf[511:256];
dram_data_mask_buf<=64'h00000000_ffffffff;
end
state <= READY_FOR_CHECK_HIT;
end
READY_FOR_CHECK_HIT://110111
begin
hit_flag[0] <= |(entries[28:0] ^ {1'b1, controller_command[27:0]});
hit_flag[1] <= |(entries[60:32] ^ {1'b1, controller_command[27:0]});
hit_flag[2] <= |(entries[92:64] ^ {1'b1, controller_command[27:0]});
hit_flag[3] <= |(entries[124:96] ^ {1'b1, controller_command[27:0]});
hit_flag[4] <= |(entries[156:128] ^ {1'b1, controller_command[27:0]});
hit_flag[5] <= |(entries[188:160] ^ {1'b1, controller_command[27:0]});
hit_flag[6] <= |(entries[220:192] ^ {1'b1, controller_command[27:0]});
hit_flag[7] <= |(entries[252:224] ^ {1'b1, controller_command[27:0]});
state <= CHECK_HIT;
end
CHECK_HIT://111000
begin
casex(hit_flag)// synthesis parallel_case
8'bxxxxxxx0:
begin
entries[29] <= 0; //unlock
end
8'bxxxxxx0x:
begin
entries[61] <= 0; //unlock
end
8'bxxxxx0xx:
begin
entries[93] <= 0; //unlock
end
8'bxxxx0xxx:
begin
entries[125] <= 0; //unlock
end
8'bxxx0xxxx:
begin
entries[157] <= 0; //unlock
end
8'bxx0xxxxx:
begin
entries[189] <= 0; //unlock
end
8'bx0xxxxxx:
begin
entries[221] <= 0; //unlock
end
8'b0xxxxxxx:
begin
entries[253] <= 0; //unlock
end
endcase
state<=WAIT_FOR_TWO_CYCLE;
end
WAIT_FOR_TWO_CYCLE://111001
begin
if(count>=8)
begin
count<=0;
state<=WRITE_ENTRY_BACK0;
data_to_dram_en <= 1'b1;
dram_data_mask<=dram_data_mask_buf[31:0];//mask
data_to_dram <= entries;
end
else
count<=count+1;
end
WRITE_ENTRY_BACK0://111010
begin
if(data_to_dram_ready)
begin
dram_en <= 1;
dram_read_or_write <= 0;//write
addr_to_dram <= {controller_command[15:1], 3'b000} + CACHE_ENTRY_BASE;
data_to_dram_end<= 1'b1;
data_to_dram <= entries;
dram_data_mask<=dram_data_mask_buf[63:32];
state <= WRITE_ENTRY_BACK1;
end
end
WRITE_ENTRY_BACK1: //111011
begin
if(dram_ready & data_to_dram_ready )
begin
dram_en <= 0;
data_to_dram_en <= 1'b0;
data_to_dram_end<= 1'b0;
state <= UNLOCK_DRAM;
end
else if (dram_ready)
begin
dram_en <= 0;
end
else if (data_to_dram_ready)
begin
data_to_dram_en <= 1'b0;
data_to_dram_end<= 1'b0;
end
else
state <= WRITE_ENTRY_BACK1;
end
UNLOCK_DRAM://111100
begin
release_dram <= 1;
state <= FINISH;
end
FINISH: //111101
begin
release_dram <= 0;
state <= state_buf;
end
default:
state <= CHECK_COMMAND_FIFO0;
endcase
end
end
always@(posedge clk or negedge reset) // issue ci_num dram write commands
begin
if(!reset)
begin
ci_done <= 1; //done==1, not busy
ci_state <= COMMANDS_ISSUE0;
ci_cmd_cnt <= 0;
dram_en_ci <= 0;
addr_to_dram_ci <= 0;
end
else
begin
case(ci_state)
COMMANDS_ISSUE0: //0
begin
if(ci_en)
begin
ci_done <= 0;
ci_cmd_cnt <= 0;
ci_state <= COMMANDS_ISSUE1;
end
end
COMMANDS_ISSUE1: //1
begin
if (ci_cmd_cnt < ci_data_cnt)
begin
dram_en_ci <= 1;
addr_to_dram_ci <= ci_addr+{ci_cmd_cnt[9:0],3'b000};
ci_state <= COMMANDS_ISSUE2;
end
end
COMMANDS_ISSUE2: //2
begin
if(dram_ready)
begin
dram_en_ci <= 0;
ci_cmd_cnt<=ci_cmd_cnt+1; //successive command number +1
ci_state <= COMMANDS_ISSUE1;
if(ci_cmd_cnt == (ci_num-1))
ci_state <= COMMANDS_ISSUE3;
end
end
COMMANDS_ISSUE3: //3
begin
ci_done <= 1;
ci_state<=COMMANDS_ISSUE0;
end
endcase
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: mul_int19_int20_int39.v
// /___/ /\ Timestamp: Thu Oct 1 16:53:08 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int19_int20_int39.ngc /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int19_int20_int39.v
// Device : 7z020clg484-1
// Input file : /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int19_int20_int39.ngc
// Output file : /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int19_int20_int39.v
// # of Modules : 1
// Design Name : mul_int19_int20_int39
// Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
module mul_int19_int20_int39 (
// clk, ce, a, b, p
CLK, ce, inp, out
);
parameter INSTANCE_NAME="INST";
/* input clk;
input ce;
input [18 : 0] a;
input [19 : 0] b;
output [38 : 0] p;*/
input wire CLK;
input wire ce;
input [38:0] inp;
output [38:0] out;
wire [18:0] a;
wire [19:0] b;
wire [38:0] p;
assign a = inp[18:0];
assign b = inp[38:19];
assign out = p;
wire clk;
assign clk = CLK;
wire \blk00000001/sig000007aa ;
wire \blk00000001/sig000007a9 ;
wire \blk00000001/sig000007a8 ;
wire \blk00000001/sig000007a7 ;
wire \blk00000001/sig000007a6 ;
wire \blk00000001/sig000007a5 ;
wire \blk00000001/sig000007a4 ;
wire \blk00000001/sig000007a3 ;
wire \blk00000001/sig000007a2 ;
wire \blk00000001/sig000007a1 ;
wire \blk00000001/sig000007a0 ;
wire \blk00000001/sig0000079f ;
wire \blk00000001/sig0000079e ;
wire \blk00000001/sig0000079d ;
wire \blk00000001/sig0000079c ;
wire \blk00000001/sig0000079b ;
wire \blk00000001/sig0000079a ;
wire \blk00000001/sig00000799 ;
wire \blk00000001/sig00000798 ;
wire \blk00000001/sig00000797 ;
wire \blk00000001/sig00000796 ;
wire \blk00000001/sig00000795 ;
wire \blk00000001/sig00000794 ;
wire \blk00000001/sig00000793 ;
wire \blk00000001/sig00000792 ;
wire \blk00000001/sig00000791 ;
wire \blk00000001/sig00000790 ;
wire \blk00000001/sig0000078f ;
wire \blk00000001/sig0000078e ;
wire \blk00000001/sig0000078d ;
wire \blk00000001/sig0000078c ;
wire \blk00000001/sig0000078b ;
wire \blk00000001/sig0000078a ;
wire \blk00000001/sig00000789 ;
wire \blk00000001/sig00000788 ;
wire \blk00000001/sig00000787 ;
wire \blk00000001/sig00000786 ;
wire \blk00000001/sig00000785 ;
wire \blk00000001/sig00000784 ;
wire \blk00000001/sig00000783 ;
wire \blk00000001/sig00000782 ;
wire \blk00000001/sig00000781 ;
wire \blk00000001/sig00000780 ;
wire \blk00000001/sig0000077f ;
wire \blk00000001/sig0000077e ;
wire \blk00000001/sig0000077d ;
wire \blk00000001/sig0000077c ;
wire \blk00000001/sig0000077b ;
wire \blk00000001/sig0000077a ;
wire \blk00000001/sig00000779 ;
wire \blk00000001/sig00000778 ;
wire \blk00000001/sig00000777 ;
wire \blk00000001/sig00000776 ;
wire \blk00000001/sig00000775 ;
wire \blk00000001/sig00000774 ;
wire \blk00000001/sig00000773 ;
wire \blk00000001/sig00000772 ;
wire \blk00000001/sig00000771 ;
wire \blk00000001/sig00000770 ;
wire \blk00000001/sig0000076f ;
wire \blk00000001/sig0000076e ;
wire \blk00000001/sig0000076d ;
wire \blk00000001/sig0000076c ;
wire \blk00000001/sig0000076b ;
wire \blk00000001/sig0000076a ;
wire \blk00000001/sig00000769 ;
wire \blk00000001/sig00000768 ;
wire \blk00000001/sig00000767 ;
wire \blk00000001/sig00000766 ;
wire \blk00000001/sig00000765 ;
wire \blk00000001/sig00000764 ;
wire \blk00000001/sig00000763 ;
wire \blk00000001/sig00000762 ;
wire \blk00000001/sig00000761 ;
wire \blk00000001/sig00000760 ;
wire \blk00000001/sig0000075f ;
wire \blk00000001/sig0000075e ;
wire \blk00000001/sig0000075d ;
wire \blk00000001/sig0000075c ;
wire \blk00000001/sig0000075b ;
wire \blk00000001/sig0000075a ;
wire \blk00000001/sig00000759 ;
wire \blk00000001/sig00000758 ;
wire \blk00000001/sig00000757 ;
wire \blk00000001/sig00000756 ;
wire \blk00000001/sig00000755 ;
wire \blk00000001/sig00000754 ;
wire \blk00000001/sig00000753 ;
wire \blk00000001/sig00000752 ;
wire \blk00000001/sig00000751 ;
wire \blk00000001/sig00000750 ;
wire \blk00000001/sig0000074f ;
wire \blk00000001/sig0000074e ;
wire \blk00000001/sig0000074d ;
wire \blk00000001/sig0000074c ;
wire \blk00000001/sig0000074b ;
wire \blk00000001/sig0000074a ;
wire \blk00000001/sig00000749 ;
wire \blk00000001/sig00000748 ;
wire \blk00000001/sig00000747 ;
wire \blk00000001/sig00000746 ;
wire \blk00000001/sig00000745 ;
wire \blk00000001/sig00000744 ;
wire \blk00000001/sig00000743 ;
wire \blk00000001/sig00000742 ;
wire \blk00000001/sig00000741 ;
wire \blk00000001/sig00000740 ;
wire \blk00000001/sig0000073f ;
wire \blk00000001/sig0000073e ;
wire \blk00000001/sig0000073d ;
wire \blk00000001/sig0000073c ;
wire \blk00000001/sig0000073b ;
wire \blk00000001/sig0000073a ;
wire \blk00000001/sig00000739 ;
wire \blk00000001/sig00000738 ;
wire \blk00000001/sig00000737 ;
wire \blk00000001/sig00000736 ;
wire \blk00000001/sig00000735 ;
wire \blk00000001/sig00000734 ;
wire \blk00000001/sig00000733 ;
wire \blk00000001/sig00000732 ;
wire \blk00000001/sig00000731 ;
wire \blk00000001/sig00000730 ;
wire \blk00000001/sig0000072f ;
wire \blk00000001/sig0000072e ;
wire \blk00000001/sig0000072d ;
wire \blk00000001/sig0000072c ;
wire \blk00000001/sig0000072b ;
wire \blk00000001/sig0000072a ;
wire \blk00000001/sig00000729 ;
wire \blk00000001/sig00000728 ;
wire \blk00000001/sig00000727 ;
wire \blk00000001/sig00000726 ;
wire \blk00000001/sig00000725 ;
wire \blk00000001/sig00000724 ;
wire \blk00000001/sig00000723 ;
wire \blk00000001/sig00000722 ;
wire \blk00000001/sig00000721 ;
wire \blk00000001/sig00000720 ;
wire \blk00000001/sig0000071f ;
wire \blk00000001/sig0000071e ;
wire \blk00000001/sig0000071d ;
wire \blk00000001/sig0000071c ;
wire \blk00000001/sig0000071b ;
wire \blk00000001/sig0000071a ;
wire \blk00000001/sig00000719 ;
wire \blk00000001/sig00000718 ;
wire \blk00000001/sig00000717 ;
wire \blk00000001/sig00000716 ;
wire \blk00000001/sig00000715 ;
wire \blk00000001/sig00000714 ;
wire \blk00000001/sig00000713 ;
wire \blk00000001/sig00000712 ;
wire \blk00000001/sig00000711 ;
wire \blk00000001/sig00000710 ;
wire \blk00000001/sig0000070f ;
wire \blk00000001/sig0000070e ;
wire \blk00000001/sig0000070d ;
wire \blk00000001/sig0000070c ;
wire \blk00000001/sig0000070b ;
wire \blk00000001/sig0000070a ;
wire \blk00000001/sig00000709 ;
wire \blk00000001/sig00000708 ;
wire \blk00000001/sig00000707 ;
wire \blk00000001/sig00000706 ;
wire \blk00000001/sig00000705 ;
wire \blk00000001/sig00000704 ;
wire \blk00000001/sig00000703 ;
wire \blk00000001/sig00000702 ;
wire \blk00000001/sig00000701 ;
wire \blk00000001/sig00000700 ;
wire \blk00000001/sig000006ff ;
wire \blk00000001/sig000006fe ;
wire \blk00000001/sig000006fd ;
wire \blk00000001/sig000006fc ;
wire \blk00000001/sig000006fb ;
wire \blk00000001/sig000006fa ;
wire \blk00000001/sig000006f9 ;
wire \blk00000001/sig000006f8 ;
wire \blk00000001/sig000006f7 ;
wire \blk00000001/sig000006f6 ;
wire \blk00000001/sig000006f5 ;
wire \blk00000001/sig000006f4 ;
wire \blk00000001/sig000006f3 ;
wire \blk00000001/sig000006f2 ;
wire \blk00000001/sig000006f1 ;
wire \blk00000001/sig000006f0 ;
wire \blk00000001/sig000006ef ;
wire \blk00000001/sig000006ee ;
wire \blk00000001/sig000006ed ;
wire \blk00000001/sig000006ec ;
wire \blk00000001/sig000006eb ;
wire \blk00000001/sig000006ea ;
wire \blk00000001/sig000006e9 ;
wire \blk00000001/sig000006e8 ;
wire \blk00000001/sig000006e7 ;
wire \blk00000001/sig000006e6 ;
wire \blk00000001/sig000006e5 ;
wire \blk00000001/sig000006e4 ;
wire \blk00000001/sig000006e3 ;
wire \blk00000001/sig000006e2 ;
wire \blk00000001/sig000006e1 ;
wire \blk00000001/sig000006e0 ;
wire \blk00000001/sig000006df ;
wire \blk00000001/sig000006de ;
wire \blk00000001/sig000006dd ;
wire \blk00000001/sig000006dc ;
wire \blk00000001/sig000006db ;
wire \blk00000001/sig000006da ;
wire \blk00000001/sig000006d9 ;
wire \blk00000001/sig000006d8 ;
wire \blk00000001/sig000006d7 ;
wire \blk00000001/sig000006d6 ;
wire \blk00000001/sig000006d5 ;
wire \blk00000001/sig000006d4 ;
wire \blk00000001/sig000006d3 ;
wire \blk00000001/sig000006d2 ;
wire \blk00000001/sig000006d1 ;
wire \blk00000001/sig000006d0 ;
wire \blk00000001/sig000006cf ;
wire \blk00000001/sig000006ce ;
wire \blk00000001/sig000006cd ;
wire \blk00000001/sig000006cc ;
wire \blk00000001/sig000006cb ;
wire \blk00000001/sig000006ca ;
wire \blk00000001/sig000006c9 ;
wire \blk00000001/sig000006c8 ;
wire \blk00000001/sig000006c7 ;
wire \blk00000001/sig000006c6 ;
wire \blk00000001/sig000006c5 ;
wire \blk00000001/sig000006c4 ;
wire \blk00000001/sig000006c3 ;
wire \blk00000001/sig000006c2 ;
wire \blk00000001/sig000006c1 ;
wire \blk00000001/sig000006c0 ;
wire \blk00000001/sig000006bf ;
wire \blk00000001/sig000006be ;
wire \blk00000001/sig000006bd ;
wire \blk00000001/sig000006bc ;
wire \blk00000001/sig000006bb ;
wire \blk00000001/sig000006ba ;
wire \blk00000001/sig000006b9 ;
wire \blk00000001/sig000006b8 ;
wire \blk00000001/sig000006b7 ;
wire \blk00000001/sig000006b6 ;
wire \blk00000001/sig000006b5 ;
wire \blk00000001/sig000006b4 ;
wire \blk00000001/sig000006b3 ;
wire \blk00000001/sig000006b2 ;
wire \blk00000001/sig000006b1 ;
wire \blk00000001/sig000006b0 ;
wire \blk00000001/sig000006af ;
wire \blk00000001/sig000006ae ;
wire \blk00000001/sig000006ad ;
wire \blk00000001/sig000006ac ;
wire \blk00000001/sig000006ab ;
wire \blk00000001/sig000006aa ;
wire \blk00000001/sig000006a9 ;
wire \blk00000001/sig000006a8 ;
wire \blk00000001/sig000006a7 ;
wire \blk00000001/sig000006a6 ;
wire \blk00000001/sig000006a5 ;
wire \blk00000001/sig000006a4 ;
wire \blk00000001/sig000006a3 ;
wire \blk00000001/sig000006a2 ;
wire \blk00000001/sig000006a1 ;
wire \blk00000001/sig000006a0 ;
wire \blk00000001/sig0000069f ;
wire \blk00000001/sig0000069e ;
wire \blk00000001/sig0000069d ;
wire \blk00000001/sig0000069c ;
wire \blk00000001/sig0000069b ;
wire \blk00000001/sig0000069a ;
wire \blk00000001/sig00000699 ;
wire \blk00000001/sig00000698 ;
wire \blk00000001/sig00000697 ;
wire \blk00000001/sig00000696 ;
wire \blk00000001/sig00000695 ;
wire \blk00000001/sig00000694 ;
wire \blk00000001/sig00000693 ;
wire \blk00000001/sig00000692 ;
wire \blk00000001/sig00000691 ;
wire \blk00000001/sig00000690 ;
wire \blk00000001/sig0000068f ;
wire \blk00000001/sig0000068e ;
wire \blk00000001/sig0000068d ;
wire \blk00000001/sig0000068c ;
wire \blk00000001/sig0000068b ;
wire \blk00000001/sig0000068a ;
wire \blk00000001/sig00000689 ;
wire \blk00000001/sig00000688 ;
wire \blk00000001/sig00000687 ;
wire \blk00000001/sig00000686 ;
wire \blk00000001/sig00000685 ;
wire \blk00000001/sig00000684 ;
wire \blk00000001/sig00000683 ;
wire \blk00000001/sig00000682 ;
wire \blk00000001/sig00000681 ;
wire \blk00000001/sig00000680 ;
wire \blk00000001/sig0000067f ;
wire \blk00000001/sig0000067e ;
wire \blk00000001/sig0000067d ;
wire \blk00000001/sig0000067c ;
wire \blk00000001/sig0000067b ;
wire \blk00000001/sig0000067a ;
wire \blk00000001/sig00000679 ;
wire \blk00000001/sig00000678 ;
wire \blk00000001/sig00000677 ;
wire \blk00000001/sig00000676 ;
wire \blk00000001/sig00000675 ;
wire \blk00000001/sig00000674 ;
wire \blk00000001/sig00000673 ;
wire \blk00000001/sig00000672 ;
wire \blk00000001/sig00000671 ;
wire \blk00000001/sig00000670 ;
wire \blk00000001/sig0000066f ;
wire \blk00000001/sig0000066e ;
wire \blk00000001/sig0000066d ;
wire \blk00000001/sig0000066c ;
wire \blk00000001/sig0000066b ;
wire \blk00000001/sig0000066a ;
wire \blk00000001/sig00000669 ;
wire \blk00000001/sig00000668 ;
wire \blk00000001/sig00000667 ;
wire \blk00000001/sig00000666 ;
wire \blk00000001/sig00000665 ;
wire \blk00000001/sig00000664 ;
wire \blk00000001/sig00000663 ;
wire \blk00000001/sig00000662 ;
wire \blk00000001/sig00000661 ;
wire \blk00000001/sig00000660 ;
wire \blk00000001/sig0000065f ;
wire \blk00000001/sig0000065e ;
wire \blk00000001/sig0000065d ;
wire \blk00000001/sig0000065c ;
wire \blk00000001/sig0000065b ;
wire \blk00000001/sig0000065a ;
wire \blk00000001/sig00000659 ;
wire \blk00000001/sig00000658 ;
wire \blk00000001/sig00000657 ;
wire \blk00000001/sig00000656 ;
wire \blk00000001/sig00000655 ;
wire \blk00000001/sig00000654 ;
wire \blk00000001/sig00000653 ;
wire \blk00000001/sig00000652 ;
wire \blk00000001/sig00000651 ;
wire \blk00000001/sig00000650 ;
wire \blk00000001/sig0000064f ;
wire \blk00000001/sig0000064e ;
wire \blk00000001/sig0000064d ;
wire \blk00000001/sig0000064c ;
wire \blk00000001/sig0000064b ;
wire \blk00000001/sig0000064a ;
wire \blk00000001/sig00000649 ;
wire \blk00000001/sig00000648 ;
wire \blk00000001/sig00000647 ;
wire \blk00000001/sig00000646 ;
wire \blk00000001/sig00000645 ;
wire \blk00000001/sig00000644 ;
wire \blk00000001/sig00000643 ;
wire \blk00000001/sig00000642 ;
wire \blk00000001/sig00000641 ;
wire \blk00000001/sig00000640 ;
wire \blk00000001/sig0000063f ;
wire \blk00000001/sig0000063e ;
wire \blk00000001/sig0000063d ;
wire \blk00000001/sig0000063c ;
wire \blk00000001/sig0000063b ;
wire \blk00000001/sig0000063a ;
wire \blk00000001/sig00000639 ;
wire \blk00000001/sig00000638 ;
wire \blk00000001/sig00000637 ;
wire \blk00000001/sig00000636 ;
wire \blk00000001/sig00000635 ;
wire \blk00000001/sig00000634 ;
wire \blk00000001/sig00000633 ;
wire \blk00000001/sig00000632 ;
wire \blk00000001/sig00000631 ;
wire \blk00000001/sig00000630 ;
wire \blk00000001/sig0000062f ;
wire \blk00000001/sig0000062e ;
wire \blk00000001/sig0000062d ;
wire \blk00000001/sig0000062c ;
wire \blk00000001/sig0000062b ;
wire \blk00000001/sig0000062a ;
wire \blk00000001/sig00000629 ;
wire \blk00000001/sig00000628 ;
wire \blk00000001/sig00000627 ;
wire \blk00000001/sig00000626 ;
wire \blk00000001/sig00000625 ;
wire \blk00000001/sig00000624 ;
wire \blk00000001/sig00000623 ;
wire \blk00000001/sig00000622 ;
wire \blk00000001/sig00000621 ;
wire \blk00000001/sig00000620 ;
wire \blk00000001/sig0000061f ;
wire \blk00000001/sig0000061e ;
wire \blk00000001/sig0000061d ;
wire \blk00000001/sig0000061c ;
wire \blk00000001/sig0000061b ;
wire \blk00000001/sig0000061a ;
wire \blk00000001/sig00000619 ;
wire \blk00000001/sig00000618 ;
wire \blk00000001/sig00000617 ;
wire \blk00000001/sig00000616 ;
wire \blk00000001/sig00000615 ;
wire \blk00000001/sig00000614 ;
wire \blk00000001/sig00000613 ;
wire \blk00000001/sig00000612 ;
wire \blk00000001/sig00000611 ;
wire \blk00000001/sig00000610 ;
wire \blk00000001/sig0000060f ;
wire \blk00000001/sig0000060e ;
wire \blk00000001/sig0000060d ;
wire \blk00000001/sig0000060c ;
wire \blk00000001/sig0000060b ;
wire \blk00000001/sig0000060a ;
wire \blk00000001/sig00000609 ;
wire \blk00000001/sig00000608 ;
wire \blk00000001/sig00000607 ;
wire \blk00000001/sig00000606 ;
wire \blk00000001/sig00000605 ;
wire \blk00000001/sig00000604 ;
wire \blk00000001/sig00000603 ;
wire \blk00000001/sig00000602 ;
wire \blk00000001/sig00000601 ;
wire \blk00000001/sig00000600 ;
wire \blk00000001/sig000005ff ;
wire \blk00000001/sig000005fe ;
wire \blk00000001/sig000005fd ;
wire \blk00000001/sig000005fc ;
wire \blk00000001/sig000005fb ;
wire \blk00000001/sig000005fa ;
wire \blk00000001/sig000005f9 ;
wire \blk00000001/sig000005f8 ;
wire \blk00000001/sig000005f7 ;
wire \blk00000001/sig000005f6 ;
wire \blk00000001/sig000005f5 ;
wire \blk00000001/sig000005f4 ;
wire \blk00000001/sig000005f3 ;
wire \blk00000001/sig000005f2 ;
wire \blk00000001/sig000005f1 ;
wire \blk00000001/sig000005f0 ;
wire \blk00000001/sig000005ef ;
wire \blk00000001/sig000005ee ;
wire \blk00000001/sig000005ed ;
wire \blk00000001/sig000005ec ;
wire \blk00000001/sig000005eb ;
wire \blk00000001/sig000005ea ;
wire \blk00000001/sig000005e9 ;
wire \blk00000001/sig000005e8 ;
wire \blk00000001/sig000005e7 ;
wire \blk00000001/sig000005e6 ;
wire \blk00000001/sig000005e5 ;
wire \blk00000001/sig000005e4 ;
wire \blk00000001/sig000005e3 ;
wire \blk00000001/sig000005e2 ;
wire \blk00000001/sig000005e1 ;
wire \blk00000001/sig000005e0 ;
wire \blk00000001/sig000005df ;
wire \blk00000001/sig000005de ;
wire \blk00000001/sig000005dd ;
wire \blk00000001/sig000005dc ;
wire \blk00000001/sig000005db ;
wire \blk00000001/sig000005da ;
wire \blk00000001/sig000005d9 ;
wire \blk00000001/sig000005d8 ;
wire \blk00000001/sig000005d7 ;
wire \blk00000001/sig000005d6 ;
wire \blk00000001/sig000005d5 ;
wire \blk00000001/sig000005d4 ;
wire \blk00000001/sig000005d3 ;
wire \blk00000001/sig000005d2 ;
wire \blk00000001/sig000005d1 ;
wire \blk00000001/sig000005d0 ;
wire \blk00000001/sig000005cf ;
wire \blk00000001/sig000005ce ;
wire \blk00000001/sig000005cd ;
wire \blk00000001/sig000005cc ;
wire \blk00000001/sig000005cb ;
wire \blk00000001/sig000005ca ;
wire \blk00000001/sig000005c9 ;
wire \blk00000001/sig000005c8 ;
wire \blk00000001/sig000005c7 ;
wire \blk00000001/sig000005c6 ;
wire \blk00000001/sig000005c5 ;
wire \blk00000001/sig000005c4 ;
wire \blk00000001/sig000005c3 ;
wire \blk00000001/sig000005c2 ;
wire \blk00000001/sig000005c1 ;
wire \blk00000001/sig000005c0 ;
wire \blk00000001/sig000005bf ;
wire \blk00000001/sig000005be ;
wire \blk00000001/sig000005bd ;
wire \blk00000001/sig000005bc ;
wire \blk00000001/sig000005bb ;
wire \blk00000001/sig000005ba ;
wire \blk00000001/sig000005b9 ;
wire \blk00000001/sig000005b8 ;
wire \blk00000001/sig000005b7 ;
wire \blk00000001/sig000005b6 ;
wire \blk00000001/sig000005b5 ;
wire \blk00000001/sig000005b4 ;
wire \blk00000001/sig000005b3 ;
wire \blk00000001/sig000005b2 ;
wire \blk00000001/sig000005b1 ;
wire \blk00000001/sig000005b0 ;
wire \blk00000001/sig000005af ;
wire \blk00000001/sig000005ae ;
wire \blk00000001/sig000005ad ;
wire \blk00000001/sig000005ac ;
wire \blk00000001/sig000005ab ;
wire \blk00000001/sig000005aa ;
wire \blk00000001/sig000005a9 ;
wire \blk00000001/sig000005a8 ;
wire \blk00000001/sig000005a7 ;
wire \blk00000001/sig000005a6 ;
wire \blk00000001/sig000005a5 ;
wire \blk00000001/sig000005a4 ;
wire \blk00000001/sig000005a3 ;
wire \blk00000001/sig000005a2 ;
wire \blk00000001/sig000005a1 ;
wire \blk00000001/sig000005a0 ;
wire \blk00000001/sig0000059f ;
wire \blk00000001/sig0000059e ;
wire \blk00000001/sig0000059d ;
wire \blk00000001/sig0000059c ;
wire \blk00000001/sig0000059b ;
wire \blk00000001/sig0000059a ;
wire \blk00000001/sig00000599 ;
wire \blk00000001/sig00000598 ;
wire \blk00000001/sig00000597 ;
wire \blk00000001/sig00000596 ;
wire \blk00000001/sig00000595 ;
wire \blk00000001/sig00000594 ;
wire \blk00000001/sig00000593 ;
wire \blk00000001/sig00000592 ;
wire \blk00000001/sig00000591 ;
wire \blk00000001/sig00000590 ;
wire \blk00000001/sig0000058f ;
wire \blk00000001/sig0000058e ;
wire \blk00000001/sig0000058d ;
wire \blk00000001/sig0000058c ;
wire \blk00000001/sig0000058b ;
wire \blk00000001/sig0000058a ;
wire \blk00000001/sig00000589 ;
wire \blk00000001/sig00000588 ;
wire \blk00000001/sig00000587 ;
wire \blk00000001/sig00000586 ;
wire \blk00000001/sig00000585 ;
wire \blk00000001/sig00000584 ;
wire \blk00000001/sig00000583 ;
wire \blk00000001/sig00000582 ;
wire \blk00000001/sig00000581 ;
wire \blk00000001/sig00000580 ;
wire \blk00000001/sig0000057f ;
wire \blk00000001/sig0000057e ;
wire \blk00000001/sig0000057d ;
wire \blk00000001/sig0000057c ;
wire \blk00000001/sig0000057b ;
wire \blk00000001/sig0000057a ;
wire \blk00000001/sig00000579 ;
wire \blk00000001/sig00000578 ;
wire \blk00000001/sig00000577 ;
wire \blk00000001/sig00000576 ;
wire \blk00000001/sig00000575 ;
wire \blk00000001/sig00000574 ;
wire \blk00000001/sig00000573 ;
wire \blk00000001/sig00000572 ;
wire \blk00000001/sig00000571 ;
wire \blk00000001/sig00000570 ;
wire \blk00000001/sig0000056f ;
wire \blk00000001/sig0000056e ;
wire \blk00000001/sig0000056d ;
wire \blk00000001/sig0000056c ;
wire \blk00000001/sig0000056b ;
wire \blk00000001/sig0000056a ;
wire \blk00000001/sig00000569 ;
wire \blk00000001/sig00000568 ;
wire \blk00000001/sig00000567 ;
wire \blk00000001/sig00000566 ;
wire \blk00000001/sig00000565 ;
wire \blk00000001/sig00000564 ;
wire \blk00000001/sig00000563 ;
wire \blk00000001/sig00000562 ;
wire \blk00000001/sig00000561 ;
wire \blk00000001/sig00000560 ;
wire \blk00000001/sig0000055f ;
wire \blk00000001/sig0000055e ;
wire \blk00000001/sig0000055d ;
wire \blk00000001/sig0000055c ;
wire \blk00000001/sig0000055b ;
wire \blk00000001/sig0000055a ;
wire \blk00000001/sig00000559 ;
wire \blk00000001/sig00000558 ;
wire \blk00000001/sig00000557 ;
wire \blk00000001/sig00000556 ;
wire \blk00000001/sig00000555 ;
wire \blk00000001/sig00000554 ;
wire \blk00000001/sig00000553 ;
wire \blk00000001/sig00000552 ;
wire \blk00000001/sig00000551 ;
wire \blk00000001/sig00000550 ;
wire \blk00000001/sig0000054f ;
wire \blk00000001/sig0000054e ;
wire \blk00000001/sig0000054d ;
wire \blk00000001/sig0000054c ;
wire \blk00000001/sig0000054b ;
wire \blk00000001/sig0000054a ;
wire \blk00000001/sig00000549 ;
wire \blk00000001/sig00000548 ;
wire \blk00000001/sig00000547 ;
wire \blk00000001/sig00000546 ;
wire \blk00000001/sig00000545 ;
wire \blk00000001/sig00000544 ;
wire \blk00000001/sig00000543 ;
wire \blk00000001/sig00000542 ;
wire \blk00000001/sig00000541 ;
wire \blk00000001/sig00000540 ;
wire \blk00000001/sig0000053f ;
wire \blk00000001/sig0000053e ;
wire \blk00000001/sig0000053d ;
wire \blk00000001/sig0000053c ;
wire \blk00000001/sig0000053b ;
wire \blk00000001/sig0000053a ;
wire \blk00000001/sig00000539 ;
wire \blk00000001/sig00000538 ;
wire \blk00000001/sig00000537 ;
wire \blk00000001/sig00000536 ;
wire \blk00000001/sig00000535 ;
wire \blk00000001/sig00000534 ;
wire \blk00000001/sig00000533 ;
wire \blk00000001/sig00000532 ;
wire \blk00000001/sig00000531 ;
wire \blk00000001/sig00000530 ;
wire \blk00000001/sig0000052f ;
wire \blk00000001/sig0000052e ;
wire \blk00000001/sig0000052d ;
wire \blk00000001/sig0000052c ;
wire \blk00000001/sig0000052b ;
wire \blk00000001/sig0000052a ;
wire \blk00000001/sig00000529 ;
wire \blk00000001/sig00000528 ;
wire \blk00000001/sig00000527 ;
wire \blk00000001/sig00000526 ;
wire \blk00000001/sig00000525 ;
wire \blk00000001/sig00000524 ;
wire \blk00000001/sig00000523 ;
wire \blk00000001/sig00000522 ;
wire \blk00000001/sig00000521 ;
wire \blk00000001/sig00000520 ;
wire \blk00000001/sig0000051f ;
wire \blk00000001/sig0000051e ;
wire \blk00000001/sig0000051d ;
wire \blk00000001/sig0000051c ;
wire \blk00000001/sig0000051b ;
wire \blk00000001/sig0000051a ;
wire \blk00000001/sig00000519 ;
wire \blk00000001/sig00000518 ;
wire \blk00000001/sig00000517 ;
wire \blk00000001/sig00000516 ;
wire \blk00000001/sig00000515 ;
wire \blk00000001/sig00000514 ;
wire \blk00000001/sig00000513 ;
wire \blk00000001/sig00000512 ;
wire \blk00000001/sig00000511 ;
wire \blk00000001/sig00000510 ;
wire \blk00000001/sig0000050f ;
wire \blk00000001/sig0000050e ;
wire \blk00000001/sig0000050d ;
wire \blk00000001/sig0000050c ;
wire \blk00000001/sig0000050b ;
wire \blk00000001/sig0000050a ;
wire \blk00000001/sig00000509 ;
wire \blk00000001/sig00000508 ;
wire \blk00000001/sig00000507 ;
wire \blk00000001/sig00000506 ;
wire \blk00000001/sig00000505 ;
wire \blk00000001/sig00000504 ;
wire \blk00000001/sig00000503 ;
wire \blk00000001/sig00000502 ;
wire \blk00000001/sig00000501 ;
wire \blk00000001/sig00000500 ;
wire \blk00000001/sig000004ff ;
wire \blk00000001/sig000004fe ;
wire \blk00000001/sig000004fd ;
wire \blk00000001/sig000004fc ;
wire \blk00000001/sig000004fb ;
wire \blk00000001/sig000004fa ;
wire \blk00000001/sig000004f9 ;
wire \blk00000001/sig000004f8 ;
wire \blk00000001/sig000004f7 ;
wire \blk00000001/sig000004f6 ;
wire \blk00000001/sig000004f5 ;
wire \blk00000001/sig000004f4 ;
wire \blk00000001/sig000004f3 ;
wire \blk00000001/sig000004f2 ;
wire \blk00000001/sig000004f1 ;
wire \blk00000001/sig000004f0 ;
wire \blk00000001/sig000004ef ;
wire \blk00000001/sig000004ee ;
wire \blk00000001/sig000004ed ;
wire \blk00000001/sig000004ec ;
wire \blk00000001/sig000004eb ;
wire \blk00000001/sig000004ea ;
wire \blk00000001/sig000004e9 ;
wire \blk00000001/sig000004e8 ;
wire \blk00000001/sig000004e7 ;
wire \blk00000001/sig000004e6 ;
wire \blk00000001/sig000004e5 ;
wire \blk00000001/sig000004e4 ;
wire \blk00000001/sig000004e3 ;
wire \blk00000001/sig000004e2 ;
wire \blk00000001/sig000004e1 ;
wire \blk00000001/sig000004e0 ;
wire \blk00000001/sig000004df ;
wire \blk00000001/sig000004de ;
wire \blk00000001/sig000004dd ;
wire \blk00000001/sig000004dc ;
wire \blk00000001/sig000004db ;
wire \blk00000001/sig000004da ;
wire \blk00000001/sig000004d9 ;
wire \blk00000001/sig000004d8 ;
wire \blk00000001/sig000004d7 ;
wire \blk00000001/sig000004d6 ;
wire \blk00000001/sig000004d5 ;
wire \blk00000001/sig000004d4 ;
wire \blk00000001/sig000004d3 ;
wire \blk00000001/sig000004d2 ;
wire \blk00000001/sig000004d1 ;
wire \blk00000001/sig000004d0 ;
wire \blk00000001/sig000004cf ;
wire \blk00000001/sig000004ce ;
wire \blk00000001/sig000004cd ;
wire \blk00000001/sig000004cc ;
wire \blk00000001/sig000004cb ;
wire \blk00000001/sig000004ca ;
wire \blk00000001/sig000004c9 ;
wire \blk00000001/sig000004c8 ;
wire \blk00000001/sig000004c7 ;
wire \blk00000001/sig000004c6 ;
wire \blk00000001/sig000004c5 ;
wire \blk00000001/sig000004c4 ;
wire \blk00000001/sig000004c3 ;
wire \blk00000001/sig000004c2 ;
wire \blk00000001/sig000004c1 ;
wire \blk00000001/sig000004c0 ;
wire \blk00000001/sig000004bf ;
wire \blk00000001/sig000004be ;
wire \blk00000001/sig000004bd ;
wire \blk00000001/sig000004bc ;
wire \blk00000001/sig000004bb ;
wire \blk00000001/sig000004ba ;
wire \blk00000001/sig000004b9 ;
wire \blk00000001/sig000004b8 ;
wire \blk00000001/sig000004b7 ;
wire \blk00000001/sig000004b6 ;
wire \blk00000001/sig000004b5 ;
wire \blk00000001/sig000004b4 ;
wire \blk00000001/sig000004b3 ;
wire \blk00000001/sig000004b2 ;
wire \blk00000001/sig000004b1 ;
wire \blk00000001/sig000004b0 ;
wire \blk00000001/sig000004af ;
wire \blk00000001/sig000004ae ;
wire \blk00000001/sig000004ad ;
wire \blk00000001/sig000004ac ;
wire \blk00000001/sig000004ab ;
wire \blk00000001/sig000004aa ;
wire \blk00000001/sig000004a9 ;
wire \blk00000001/sig000004a8 ;
wire \blk00000001/sig000004a7 ;
wire \blk00000001/sig000004a6 ;
wire \blk00000001/sig000004a5 ;
wire \blk00000001/sig000004a4 ;
wire \blk00000001/sig000004a3 ;
wire \blk00000001/sig000004a2 ;
wire \blk00000001/sig000004a1 ;
wire \blk00000001/sig000004a0 ;
wire \blk00000001/sig0000049f ;
wire \blk00000001/sig0000049e ;
wire \blk00000001/sig0000049d ;
wire \blk00000001/sig0000049c ;
wire \blk00000001/sig0000049b ;
wire \blk00000001/sig0000049a ;
wire \blk00000001/sig00000499 ;
wire \blk00000001/sig00000498 ;
wire \blk00000001/sig00000497 ;
wire \blk00000001/sig00000496 ;
wire \blk00000001/sig00000495 ;
wire \blk00000001/sig00000494 ;
wire \blk00000001/sig00000493 ;
wire \blk00000001/sig00000492 ;
wire \blk00000001/sig00000491 ;
wire \blk00000001/sig00000490 ;
wire \blk00000001/sig0000048f ;
wire \blk00000001/sig0000048e ;
wire \blk00000001/sig0000048d ;
wire \blk00000001/sig0000048c ;
wire \blk00000001/sig0000048b ;
wire \blk00000001/sig0000048a ;
wire \blk00000001/sig00000489 ;
wire \blk00000001/sig00000488 ;
wire \blk00000001/sig00000487 ;
wire \blk00000001/sig00000486 ;
wire \blk00000001/sig00000485 ;
wire \blk00000001/sig00000484 ;
wire \blk00000001/sig00000483 ;
wire \blk00000001/sig00000482 ;
wire \blk00000001/sig00000481 ;
wire \blk00000001/sig00000480 ;
wire \blk00000001/sig0000047f ;
wire \blk00000001/sig0000047e ;
wire \blk00000001/sig0000047d ;
wire \blk00000001/sig0000047c ;
wire \blk00000001/sig0000047b ;
wire \blk00000001/sig0000047a ;
wire \blk00000001/sig00000479 ;
wire \blk00000001/sig00000478 ;
wire \blk00000001/sig00000477 ;
wire \blk00000001/sig00000476 ;
wire \blk00000001/sig00000475 ;
wire \blk00000001/sig00000474 ;
wire \blk00000001/sig00000473 ;
wire \blk00000001/sig00000472 ;
wire \blk00000001/sig00000471 ;
wire \blk00000001/sig00000470 ;
wire \blk00000001/sig0000046f ;
wire \blk00000001/sig0000046e ;
wire \blk00000001/sig0000046d ;
wire \blk00000001/sig0000046c ;
wire \blk00000001/sig0000046b ;
wire \blk00000001/sig0000046a ;
wire \blk00000001/sig00000469 ;
wire \blk00000001/sig00000468 ;
wire \blk00000001/sig00000467 ;
wire \blk00000001/sig00000466 ;
wire \blk00000001/sig00000465 ;
wire \blk00000001/sig00000464 ;
wire \blk00000001/sig00000463 ;
wire \blk00000001/sig00000462 ;
wire \blk00000001/sig00000461 ;
wire \blk00000001/sig00000460 ;
wire \blk00000001/sig0000045f ;
wire \blk00000001/sig0000045e ;
wire \blk00000001/sig0000045d ;
wire \blk00000001/sig0000045c ;
wire \blk00000001/sig0000045b ;
wire \blk00000001/sig0000045a ;
wire \blk00000001/sig00000459 ;
wire \blk00000001/sig00000458 ;
wire \blk00000001/sig00000457 ;
wire \blk00000001/sig00000456 ;
wire \blk00000001/sig00000455 ;
wire \blk00000001/sig00000454 ;
wire \blk00000001/sig00000453 ;
wire \blk00000001/sig00000452 ;
wire \blk00000001/sig00000451 ;
wire \blk00000001/sig00000450 ;
wire \blk00000001/sig0000044f ;
wire \blk00000001/sig0000044e ;
wire \blk00000001/sig0000044d ;
wire \blk00000001/sig0000044c ;
wire \blk00000001/sig0000044b ;
wire \blk00000001/sig0000044a ;
wire \blk00000001/sig00000449 ;
wire \blk00000001/sig00000448 ;
wire \blk00000001/sig00000447 ;
wire \blk00000001/sig00000446 ;
wire \blk00000001/sig00000445 ;
wire \blk00000001/sig00000444 ;
wire \blk00000001/sig00000443 ;
wire \blk00000001/sig00000442 ;
wire \blk00000001/sig00000441 ;
wire \blk00000001/sig00000440 ;
wire \blk00000001/sig0000043f ;
wire \blk00000001/sig0000043e ;
wire \blk00000001/sig0000043d ;
wire \blk00000001/sig0000043c ;
wire \blk00000001/sig0000043b ;
wire \blk00000001/sig0000043a ;
wire \blk00000001/sig00000439 ;
wire \blk00000001/sig00000438 ;
wire \blk00000001/sig00000437 ;
wire \blk00000001/sig00000436 ;
wire \blk00000001/sig00000435 ;
wire \blk00000001/sig00000434 ;
wire \blk00000001/sig00000433 ;
wire \blk00000001/sig00000432 ;
wire \blk00000001/sig00000431 ;
wire \blk00000001/sig00000430 ;
wire \blk00000001/sig0000042f ;
wire \blk00000001/sig0000042e ;
wire \blk00000001/sig0000042d ;
wire \blk00000001/sig0000042c ;
wire \blk00000001/sig0000042b ;
wire \blk00000001/sig0000042a ;
wire \blk00000001/sig00000429 ;
wire \blk00000001/sig00000428 ;
wire \blk00000001/sig00000427 ;
wire \blk00000001/sig00000426 ;
wire \blk00000001/sig00000425 ;
wire \blk00000001/sig00000424 ;
wire \blk00000001/sig00000423 ;
wire \blk00000001/sig00000422 ;
wire \blk00000001/sig00000421 ;
wire \blk00000001/sig00000420 ;
wire \blk00000001/sig0000041f ;
wire \blk00000001/sig0000041e ;
wire \blk00000001/sig0000041d ;
wire \blk00000001/sig0000041c ;
wire \blk00000001/sig0000041b ;
wire \blk00000001/sig0000041a ;
wire \blk00000001/sig00000419 ;
wire \blk00000001/sig00000418 ;
wire \blk00000001/sig00000417 ;
wire \blk00000001/sig00000416 ;
wire \blk00000001/sig00000415 ;
wire \blk00000001/sig00000414 ;
wire \blk00000001/sig00000413 ;
wire \blk00000001/sig00000412 ;
wire \blk00000001/sig00000411 ;
wire \blk00000001/sig00000410 ;
wire \blk00000001/sig0000040f ;
wire \blk00000001/sig0000040e ;
wire \blk00000001/sig0000040d ;
wire \blk00000001/sig0000040c ;
wire \blk00000001/sig0000040b ;
wire \blk00000001/sig0000040a ;
wire \blk00000001/sig00000409 ;
wire \blk00000001/sig00000408 ;
wire \blk00000001/sig00000407 ;
wire \blk00000001/sig00000406 ;
wire \blk00000001/sig00000405 ;
wire \blk00000001/sig00000404 ;
wire \blk00000001/sig00000403 ;
wire \blk00000001/sig00000402 ;
wire \blk00000001/sig00000401 ;
wire \blk00000001/sig00000400 ;
wire \blk00000001/sig000003ff ;
wire \blk00000001/sig000003fe ;
wire \blk00000001/sig000003fd ;
wire \blk00000001/sig000003fc ;
wire \blk00000001/sig000003fb ;
wire \blk00000001/sig000003fa ;
wire \blk00000001/sig000003f9 ;
wire \blk00000001/sig000003f8 ;
wire \blk00000001/sig000003f7 ;
wire \blk00000001/sig000003f6 ;
wire \blk00000001/sig000003f5 ;
wire \blk00000001/sig000003f4 ;
wire \blk00000001/sig000003f3 ;
wire \blk00000001/sig000003f2 ;
wire \blk00000001/sig000003f1 ;
wire \blk00000001/sig000003f0 ;
wire \blk00000001/sig000003ef ;
wire \blk00000001/sig000003ee ;
wire \blk00000001/sig000003ed ;
wire \blk00000001/sig000003ec ;
wire \blk00000001/sig000003eb ;
wire \blk00000001/sig000003ea ;
wire \blk00000001/sig000003e9 ;
wire \blk00000001/sig000003e8 ;
wire \blk00000001/sig000003e7 ;
wire \blk00000001/sig000003e6 ;
wire \blk00000001/sig000003e5 ;
wire \blk00000001/sig000003e4 ;
wire \blk00000001/sig000003e3 ;
wire \blk00000001/sig000003e2 ;
wire \blk00000001/sig000003e1 ;
wire \blk00000001/sig000003e0 ;
wire \blk00000001/sig000003df ;
wire \blk00000001/sig000003de ;
wire \blk00000001/sig000003dd ;
wire \blk00000001/sig000003dc ;
wire \blk00000001/sig000003db ;
wire \blk00000001/sig000003da ;
wire \blk00000001/sig000003d9 ;
wire \blk00000001/sig000003d8 ;
wire \blk00000001/sig000003d7 ;
wire \blk00000001/sig000003d6 ;
wire \blk00000001/sig000003d5 ;
wire \blk00000001/sig000003d4 ;
wire \blk00000001/sig000003d3 ;
wire \blk00000001/sig000003d2 ;
wire \blk00000001/sig000003d1 ;
wire \blk00000001/sig000003d0 ;
wire \blk00000001/sig000003cf ;
wire \blk00000001/sig000003ce ;
wire \blk00000001/sig000003cd ;
wire \blk00000001/sig000003cc ;
wire \blk00000001/sig000003cb ;
wire \blk00000001/sig000003ca ;
wire \blk00000001/sig000003c9 ;
wire \blk00000001/sig000003c8 ;
wire \blk00000001/sig000003c7 ;
wire \blk00000001/sig000003c6 ;
wire \blk00000001/sig000003c5 ;
wire \blk00000001/sig000003c4 ;
wire \blk00000001/sig000003c3 ;
wire \blk00000001/sig000003c2 ;
wire \blk00000001/sig000003c1 ;
wire \blk00000001/sig000003c0 ;
wire \blk00000001/sig000003bf ;
wire \blk00000001/sig000003be ;
wire \blk00000001/sig000003bd ;
wire \blk00000001/sig000003bc ;
wire \blk00000001/sig000003bb ;
wire \blk00000001/sig000003ba ;
wire \blk00000001/sig000003b9 ;
wire \blk00000001/sig000003b8 ;
wire \blk00000001/sig000003b7 ;
wire \blk00000001/sig000003b6 ;
wire \blk00000001/sig000003b5 ;
wire \blk00000001/sig000003b4 ;
wire \blk00000001/sig000003b3 ;
wire \blk00000001/sig000003b2 ;
wire \blk00000001/sig000003b1 ;
wire \blk00000001/sig000003b0 ;
wire \blk00000001/sig000003af ;
wire \blk00000001/sig000003ae ;
wire \blk00000001/sig000003ad ;
wire \blk00000001/sig000003ac ;
wire \blk00000001/sig000003ab ;
wire \blk00000001/sig000003aa ;
wire \blk00000001/sig000003a9 ;
wire \blk00000001/sig000003a8 ;
wire \blk00000001/sig000003a7 ;
wire \blk00000001/sig000003a6 ;
wire \blk00000001/sig000003a5 ;
wire \blk00000001/sig000003a4 ;
wire \blk00000001/sig000003a3 ;
wire \blk00000001/sig000003a2 ;
wire \blk00000001/sig000003a1 ;
wire \blk00000001/sig000003a0 ;
wire \blk00000001/sig0000039f ;
wire \blk00000001/sig0000039e ;
wire \blk00000001/sig0000039d ;
wire \blk00000001/sig0000039c ;
wire \blk00000001/sig0000039b ;
wire \blk00000001/sig0000039a ;
wire \blk00000001/sig00000399 ;
wire \blk00000001/sig00000398 ;
wire \blk00000001/sig00000397 ;
wire \blk00000001/sig00000396 ;
wire \blk00000001/sig00000395 ;
wire \blk00000001/sig00000394 ;
wire \blk00000001/sig00000393 ;
wire \blk00000001/sig00000392 ;
wire \blk00000001/sig00000391 ;
wire \blk00000001/sig00000390 ;
wire \blk00000001/sig0000038f ;
wire \blk00000001/sig0000038e ;
wire \blk00000001/sig0000038d ;
wire \blk00000001/sig0000038c ;
wire \blk00000001/sig0000038b ;
wire \blk00000001/sig0000038a ;
wire \blk00000001/sig00000389 ;
wire \blk00000001/sig00000388 ;
wire \blk00000001/sig00000387 ;
wire \blk00000001/sig00000386 ;
wire \blk00000001/sig00000385 ;
wire \blk00000001/sig00000384 ;
wire \blk00000001/sig00000383 ;
wire \blk00000001/sig00000382 ;
wire \blk00000001/sig00000381 ;
wire \blk00000001/sig00000380 ;
wire \blk00000001/sig0000037f ;
wire \blk00000001/sig0000037e ;
wire \blk00000001/sig0000037d ;
wire \blk00000001/sig0000037c ;
wire \blk00000001/sig0000037b ;
wire \blk00000001/sig0000037a ;
wire \blk00000001/sig00000379 ;
wire \blk00000001/sig00000378 ;
wire \blk00000001/sig00000377 ;
wire \blk00000001/sig00000376 ;
wire \blk00000001/sig00000375 ;
wire \blk00000001/sig00000374 ;
wire \blk00000001/sig00000373 ;
wire \blk00000001/sig00000372 ;
wire \blk00000001/sig00000371 ;
wire \blk00000001/sig00000370 ;
wire \blk00000001/sig0000036f ;
wire \blk00000001/sig0000036e ;
wire \blk00000001/sig0000036d ;
wire \blk00000001/sig0000036c ;
wire \blk00000001/sig0000036b ;
wire \blk00000001/sig0000036a ;
wire \blk00000001/sig00000369 ;
wire \blk00000001/sig00000368 ;
wire \blk00000001/sig00000367 ;
wire \blk00000001/sig00000366 ;
wire \blk00000001/sig00000365 ;
wire \blk00000001/sig00000364 ;
wire \blk00000001/sig00000363 ;
wire \blk00000001/sig00000362 ;
wire \blk00000001/sig00000361 ;
wire \blk00000001/sig00000360 ;
wire \blk00000001/sig0000035f ;
wire \blk00000001/sig0000035e ;
wire \blk00000001/sig0000035d ;
wire \blk00000001/sig0000035c ;
wire \blk00000001/sig0000035b ;
wire \blk00000001/sig0000035a ;
wire \blk00000001/sig00000359 ;
wire \blk00000001/sig00000358 ;
wire \blk00000001/sig00000357 ;
wire \blk00000001/sig00000356 ;
wire \blk00000001/sig00000355 ;
wire \blk00000001/sig00000354 ;
wire \blk00000001/sig00000353 ;
wire \blk00000001/sig00000352 ;
wire \blk00000001/sig00000351 ;
wire \blk00000001/sig00000350 ;
wire \blk00000001/sig0000034f ;
wire \blk00000001/sig0000034e ;
wire \blk00000001/sig0000034d ;
wire \blk00000001/sig0000034c ;
wire \blk00000001/sig0000034b ;
wire \blk00000001/sig0000034a ;
wire \blk00000001/sig00000349 ;
wire \blk00000001/sig00000348 ;
wire \blk00000001/sig00000347 ;
wire \blk00000001/sig00000346 ;
wire \blk00000001/sig00000345 ;
wire \blk00000001/sig00000344 ;
wire \blk00000001/sig00000343 ;
wire \blk00000001/sig00000342 ;
wire \blk00000001/sig00000341 ;
wire \blk00000001/sig00000340 ;
wire \blk00000001/sig0000033f ;
wire \blk00000001/sig0000033e ;
wire \blk00000001/sig0000033d ;
wire \blk00000001/sig0000033c ;
wire \blk00000001/sig0000033b ;
wire \blk00000001/sig0000033a ;
wire \blk00000001/sig00000339 ;
wire \blk00000001/sig00000338 ;
wire \blk00000001/sig00000337 ;
wire \blk00000001/sig00000336 ;
wire \blk00000001/sig00000335 ;
wire \blk00000001/sig00000334 ;
wire \blk00000001/sig00000333 ;
wire \blk00000001/sig00000332 ;
wire \blk00000001/sig00000331 ;
wire \blk00000001/sig00000330 ;
wire \blk00000001/sig0000032f ;
wire \blk00000001/sig0000032e ;
wire \blk00000001/sig0000032d ;
wire \blk00000001/sig0000032c ;
wire \blk00000001/sig0000032b ;
wire \blk00000001/sig0000032a ;
wire \blk00000001/sig00000329 ;
wire \blk00000001/sig00000328 ;
wire \blk00000001/sig00000327 ;
wire \blk00000001/sig00000326 ;
wire \blk00000001/sig00000325 ;
wire \blk00000001/sig00000324 ;
wire \blk00000001/sig00000323 ;
wire \blk00000001/sig00000322 ;
wire \blk00000001/sig00000321 ;
wire \blk00000001/sig00000320 ;
wire \blk00000001/sig0000031f ;
wire \blk00000001/sig0000031e ;
wire \blk00000001/sig0000031d ;
wire \blk00000001/sig0000031c ;
wire \blk00000001/sig0000031b ;
wire \blk00000001/sig0000031a ;
wire \blk00000001/sig00000319 ;
wire \blk00000001/sig00000318 ;
wire \blk00000001/sig00000317 ;
wire \blk00000001/sig00000316 ;
wire \blk00000001/sig00000315 ;
wire \blk00000001/sig00000314 ;
wire \blk00000001/sig00000313 ;
wire \blk00000001/sig00000312 ;
wire \blk00000001/sig00000311 ;
wire \blk00000001/sig00000310 ;
wire \blk00000001/sig0000030f ;
wire \blk00000001/sig0000030e ;
wire \blk00000001/sig0000030d ;
wire \blk00000001/sig0000030c ;
wire \blk00000001/sig0000030b ;
wire \blk00000001/sig0000030a ;
wire \blk00000001/sig00000309 ;
wire \blk00000001/sig00000308 ;
wire \blk00000001/sig00000307 ;
wire \blk00000001/sig00000306 ;
wire \blk00000001/sig00000305 ;
wire \blk00000001/sig00000304 ;
wire \blk00000001/sig00000303 ;
wire \blk00000001/sig00000302 ;
wire \blk00000001/sig00000301 ;
wire \blk00000001/sig00000300 ;
wire \blk00000001/sig000002ff ;
wire \blk00000001/sig000002fe ;
wire \blk00000001/sig000002fd ;
wire \blk00000001/sig000002fc ;
wire \blk00000001/sig000002fb ;
wire \blk00000001/sig000002fa ;
wire \blk00000001/sig000002f9 ;
wire \blk00000001/sig000002f8 ;
wire \blk00000001/sig000002f7 ;
wire \blk00000001/sig000002f6 ;
wire \blk00000001/sig000002f5 ;
wire \blk00000001/sig000002f4 ;
wire \blk00000001/sig000002f3 ;
wire \blk00000001/sig000002f2 ;
wire \blk00000001/sig000002f1 ;
wire \blk00000001/sig000002f0 ;
wire \blk00000001/sig000002ef ;
wire \blk00000001/sig000002ee ;
wire \blk00000001/sig000002ed ;
wire \blk00000001/sig000002ec ;
wire \blk00000001/sig000002eb ;
wire \blk00000001/sig000002ea ;
wire \blk00000001/sig000002e9 ;
wire \blk00000001/sig000002e8 ;
wire \blk00000001/sig000002e7 ;
wire \blk00000001/sig000002e6 ;
wire \blk00000001/sig000002e5 ;
wire \blk00000001/sig000002e4 ;
wire \blk00000001/sig000002e3 ;
wire \blk00000001/sig000002e2 ;
wire \blk00000001/sig000002e1 ;
wire \blk00000001/sig000002e0 ;
wire \blk00000001/sig000002df ;
wire \blk00000001/sig000002de ;
wire \blk00000001/sig000002dd ;
wire \blk00000001/sig000002dc ;
wire \blk00000001/sig000002db ;
wire \blk00000001/sig000002da ;
wire \blk00000001/sig000002d9 ;
wire \blk00000001/sig000002d8 ;
wire \blk00000001/sig000002d7 ;
wire \blk00000001/sig000002d6 ;
wire \blk00000001/sig000002d5 ;
wire \blk00000001/sig000002d4 ;
wire \blk00000001/sig000002d3 ;
wire \blk00000001/sig000002d2 ;
wire \blk00000001/sig000002d1 ;
wire \blk00000001/sig000002d0 ;
wire \blk00000001/sig000002cf ;
wire \blk00000001/sig000002ce ;
wire \blk00000001/sig000002cd ;
wire \blk00000001/sig000002cc ;
wire \blk00000001/sig000002cb ;
wire \blk00000001/sig000002ca ;
wire \blk00000001/sig000002c9 ;
wire \blk00000001/sig000002c8 ;
wire \blk00000001/sig000002c7 ;
wire \blk00000001/sig000002c6 ;
wire \blk00000001/sig000002c5 ;
wire \blk00000001/sig000002c4 ;
wire \blk00000001/sig000002c3 ;
wire \blk00000001/sig000002c2 ;
wire \blk00000001/sig000002c1 ;
wire \blk00000001/sig000002c0 ;
wire \blk00000001/sig000002bf ;
wire \blk00000001/sig000002be ;
wire \blk00000001/sig000002bd ;
wire \blk00000001/sig000002bc ;
wire \blk00000001/sig000002bb ;
wire \blk00000001/sig000002ba ;
wire \blk00000001/sig000002b9 ;
wire \blk00000001/sig000002b8 ;
wire \blk00000001/sig000002b7 ;
wire \blk00000001/sig000002b6 ;
wire \blk00000001/sig000002b5 ;
wire \blk00000001/sig000002b4 ;
wire \blk00000001/sig000002b3 ;
wire \blk00000001/sig000002b2 ;
wire \blk00000001/sig000002b1 ;
wire \blk00000001/sig000002b0 ;
wire \blk00000001/sig000002af ;
wire \blk00000001/sig000002ae ;
wire \blk00000001/sig000002ad ;
wire \blk00000001/sig000002ac ;
wire \blk00000001/sig000002ab ;
wire \blk00000001/sig000002aa ;
wire \blk00000001/sig000002a9 ;
wire \blk00000001/sig000002a8 ;
wire \blk00000001/sig000002a7 ;
wire \blk00000001/sig000002a6 ;
wire \blk00000001/sig000002a5 ;
wire \blk00000001/sig000002a4 ;
wire \blk00000001/sig000002a3 ;
wire \blk00000001/sig000002a2 ;
wire \blk00000001/sig000002a1 ;
wire \blk00000001/sig000002a0 ;
wire \blk00000001/sig0000029f ;
wire \blk00000001/sig0000029e ;
wire \blk00000001/sig0000029d ;
wire \blk00000001/sig0000029c ;
wire \blk00000001/sig0000029b ;
wire \blk00000001/sig0000029a ;
wire \blk00000001/sig00000299 ;
wire \blk00000001/sig00000298 ;
wire \blk00000001/sig00000297 ;
wire \blk00000001/sig00000296 ;
wire \blk00000001/sig00000295 ;
wire \blk00000001/sig00000294 ;
wire \blk00000001/sig00000293 ;
wire \blk00000001/sig00000292 ;
wire \blk00000001/sig00000291 ;
wire \blk00000001/sig00000290 ;
wire \blk00000001/sig0000028f ;
wire \blk00000001/sig0000028e ;
wire \blk00000001/sig0000028d ;
wire \blk00000001/sig0000028c ;
wire \blk00000001/sig0000028b ;
wire \blk00000001/sig0000028a ;
wire \blk00000001/sig00000289 ;
wire \blk00000001/sig00000288 ;
wire \blk00000001/sig00000287 ;
wire \blk00000001/sig00000286 ;
wire \blk00000001/sig00000285 ;
wire \blk00000001/sig00000284 ;
wire \blk00000001/sig00000283 ;
wire \blk00000001/sig00000282 ;
wire \blk00000001/sig00000281 ;
wire \blk00000001/sig00000280 ;
wire \blk00000001/sig0000027f ;
wire \blk00000001/sig0000027e ;
wire \blk00000001/sig0000027d ;
wire \blk00000001/sig0000027c ;
wire \blk00000001/sig0000027b ;
wire \blk00000001/sig0000027a ;
wire \blk00000001/sig00000279 ;
wire \blk00000001/sig00000278 ;
wire \blk00000001/sig00000277 ;
wire \blk00000001/sig00000276 ;
wire \blk00000001/sig00000275 ;
wire \blk00000001/sig00000274 ;
wire \blk00000001/sig00000273 ;
wire \blk00000001/sig00000272 ;
wire \blk00000001/sig00000271 ;
wire \blk00000001/sig00000270 ;
wire \blk00000001/sig0000026f ;
wire \blk00000001/sig0000026e ;
wire \blk00000001/sig0000026d ;
wire \blk00000001/sig0000026c ;
wire \blk00000001/sig0000026b ;
wire \blk00000001/sig0000026a ;
wire \blk00000001/sig00000269 ;
wire \blk00000001/sig00000268 ;
wire \blk00000001/sig00000267 ;
wire \blk00000001/sig00000266 ;
wire \blk00000001/sig00000265 ;
wire \blk00000001/sig00000264 ;
wire \blk00000001/sig00000263 ;
wire \blk00000001/sig00000262 ;
wire \blk00000001/sig00000261 ;
wire \blk00000001/sig00000260 ;
wire \blk00000001/sig0000025f ;
wire \blk00000001/sig0000025e ;
wire \blk00000001/sig0000025d ;
wire \blk00000001/sig0000025c ;
wire \blk00000001/sig0000025b ;
wire \blk00000001/sig0000025a ;
wire \blk00000001/sig00000259 ;
wire \blk00000001/sig00000258 ;
wire \blk00000001/sig00000257 ;
wire \blk00000001/sig00000256 ;
wire \blk00000001/sig00000255 ;
wire \blk00000001/sig00000254 ;
wire \blk00000001/sig00000253 ;
wire \blk00000001/sig00000252 ;
wire \blk00000001/sig00000251 ;
wire \blk00000001/sig00000250 ;
wire \blk00000001/sig0000024f ;
wire \blk00000001/sig0000024e ;
wire \blk00000001/sig0000024d ;
wire \blk00000001/sig0000024c ;
wire \blk00000001/sig0000024b ;
wire \blk00000001/sig0000024a ;
wire \blk00000001/sig00000249 ;
wire \blk00000001/sig00000248 ;
wire \blk00000001/sig00000247 ;
wire \blk00000001/sig00000246 ;
wire \blk00000001/sig00000245 ;
wire \blk00000001/sig00000244 ;
wire \blk00000001/sig00000243 ;
wire \blk00000001/sig00000242 ;
wire \blk00000001/sig00000241 ;
wire \blk00000001/sig00000240 ;
wire \blk00000001/sig0000023f ;
wire \blk00000001/sig0000023e ;
wire \blk00000001/sig0000023d ;
wire \blk00000001/sig0000023c ;
wire \blk00000001/sig0000023b ;
wire \blk00000001/sig0000023a ;
wire \blk00000001/sig00000239 ;
wire \blk00000001/sig00000238 ;
wire \blk00000001/sig00000237 ;
wire \blk00000001/sig00000236 ;
wire \blk00000001/sig00000235 ;
wire \blk00000001/sig00000234 ;
wire \blk00000001/sig00000233 ;
wire \blk00000001/sig00000232 ;
wire \blk00000001/sig00000231 ;
wire \blk00000001/sig00000230 ;
wire \blk00000001/sig0000022f ;
wire \blk00000001/sig0000022e ;
wire \blk00000001/sig0000022d ;
wire \blk00000001/sig0000022c ;
wire \blk00000001/sig0000022b ;
wire \blk00000001/sig0000022a ;
wire \blk00000001/sig00000229 ;
wire \blk00000001/sig00000228 ;
wire \blk00000001/sig00000227 ;
wire \blk00000001/sig00000226 ;
wire \blk00000001/sig00000225 ;
wire \blk00000001/sig00000224 ;
wire \blk00000001/sig00000223 ;
wire \blk00000001/sig00000222 ;
wire \blk00000001/sig00000221 ;
wire \blk00000001/sig00000220 ;
wire \blk00000001/sig0000021f ;
wire \blk00000001/sig0000021e ;
wire \blk00000001/sig0000021d ;
wire \blk00000001/sig0000021c ;
wire \blk00000001/sig0000021b ;
wire \blk00000001/sig0000021a ;
wire \blk00000001/sig00000219 ;
wire \blk00000001/sig00000218 ;
wire \blk00000001/sig00000217 ;
wire \blk00000001/sig00000216 ;
wire \blk00000001/sig00000215 ;
wire \blk00000001/sig00000214 ;
wire \blk00000001/sig00000213 ;
wire \blk00000001/sig00000212 ;
wire \blk00000001/sig00000211 ;
wire \blk00000001/sig00000210 ;
wire \blk00000001/sig0000020f ;
wire \blk00000001/sig0000020e ;
wire \blk00000001/sig0000020d ;
wire \blk00000001/sig0000020c ;
wire \blk00000001/sig0000020b ;
wire \blk00000001/sig0000020a ;
wire \blk00000001/sig00000209 ;
wire \blk00000001/sig00000208 ;
wire \blk00000001/sig00000207 ;
wire \blk00000001/sig00000206 ;
wire \blk00000001/sig00000205 ;
wire \blk00000001/sig00000204 ;
wire \blk00000001/sig00000203 ;
wire \blk00000001/sig00000202 ;
wire \blk00000001/sig00000201 ;
wire \blk00000001/sig00000200 ;
wire \blk00000001/sig000001ff ;
wire \blk00000001/sig000001fe ;
wire \blk00000001/sig000001fd ;
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \NLW_blk00000001/blk00000781_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000077f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000077d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000077b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000779_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000777_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000775_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000773_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000771_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000076f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000076d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000076b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000769_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000767_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000765_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000763_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000761_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000075f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000075d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000075b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000759_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000757_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000755_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000753_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000751_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000074f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000074d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000074b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000749_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000747_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000745_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000743_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000741_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000073f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000073d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000073b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000739_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000737_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000735_Q15_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000782 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007aa ),
.Q(\blk00000001/sig00000681 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000781 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000499 ),
.Q(\blk00000001/sig000007aa ),
.Q15(\NLW_blk00000001/blk00000781_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000780 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a9 ),
.Q(\blk00000001/sig00000682 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000077f (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000036e ),
.Q(\blk00000001/sig000007a9 ),
.Q15(\NLW_blk00000001/blk0000077f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000077e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a8 ),
.Q(\blk00000001/sig00000654 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000077d (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000048d ),
.Q(\blk00000001/sig000007a8 ),
.Q15(\NLW_blk00000001/blk0000077d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000077c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a7 ),
.Q(\blk00000001/sig00000655 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000077b (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000362 ),
.Q(\blk00000001/sig000007a7 ),
.Q15(\NLW_blk00000001/blk0000077b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000077a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a6 ),
.Q(\blk00000001/sig0000060a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000779 (
.A0(\blk00000001/sig00000051 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000493 ),
.Q(\blk00000001/sig000007a6 ),
.Q15(\NLW_blk00000001/blk00000779_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000778 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a5 ),
.Q(\blk00000001/sig0000060b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000777 (
.A0(\blk00000001/sig00000051 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000368 ),
.Q(\blk00000001/sig000007a5 ),
.Q15(\NLW_blk00000001/blk00000777_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000776 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a4 ),
.Q(\blk00000001/sig000005d5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000775 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000051 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000487 ),
.Q(\blk00000001/sig000007a4 ),
.Q15(\NLW_blk00000001/blk00000775_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000774 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a3 ),
.Q(\blk00000001/sig000005d6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000773 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000051 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000035c ),
.Q(\blk00000001/sig000007a3 ),
.Q15(\NLW_blk00000001/blk00000773_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000772 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a2 ),
.Q(\blk00000001/sig0000060c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000771 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000005a8 ),
.Q(\blk00000001/sig000007a2 ),
.Q15(\NLW_blk00000001/blk00000771_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000770 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a1 ),
.Q(\blk00000001/sig000005d7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000076f (
.A0(\blk00000001/sig00000051 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000057c ),
.Q(\blk00000001/sig000007a1 ),
.Q15(\NLW_blk00000001/blk0000076f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000076e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007a0 ),
.Q(\blk00000001/sig000005d8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000076d (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000063f ),
.Q(\blk00000001/sig000007a0 ),
.Q15(\NLW_blk00000001/blk0000076d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000076c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000079f ),
.Q(\blk00000001/sig000005da )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000076b (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000641 ),
.Q(\blk00000001/sig0000079f ),
.Q15(\NLW_blk00000001/blk0000076b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000076a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000079e ),
.Q(\blk00000001/sig000005db )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000769 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000642 ),
.Q(\blk00000001/sig0000079e ),
.Q15(\NLW_blk00000001/blk00000769_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000768 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000079d ),
.Q(\blk00000001/sig000005d9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000767 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000640 ),
.Q(\blk00000001/sig0000079d ),
.Q15(\NLW_blk00000001/blk00000767_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000766 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000079c ),
.Q(\blk00000001/sig000005dc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000765 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000643 ),
.Q(\blk00000001/sig0000079c ),
.Q15(\NLW_blk00000001/blk00000765_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000764 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000079b ),
.Q(\blk00000001/sig000005dd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000763 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000644 ),
.Q(\blk00000001/sig0000079b ),
.Q15(\NLW_blk00000001/blk00000763_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000762 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000079a ),
.Q(\blk00000001/sig000005df )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000761 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000646 ),
.Q(\blk00000001/sig0000079a ),
.Q15(\NLW_blk00000001/blk00000761_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000760 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000799 ),
.Q(\blk00000001/sig000005e0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000075f (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000647 ),
.Q(\blk00000001/sig00000799 ),
.Q15(\NLW_blk00000001/blk0000075f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000075e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000798 ),
.Q(\blk00000001/sig000005de )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000075d (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000645 ),
.Q(\blk00000001/sig00000798 ),
.Q15(\NLW_blk00000001/blk0000075d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000075c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000797 ),
.Q(\blk00000001/sig000005e1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000075b (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000648 ),
.Q(\blk00000001/sig00000797 ),
.Q15(\NLW_blk00000001/blk0000075b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000075a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000796 ),
.Q(\blk00000001/sig000005e2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000759 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000649 ),
.Q(\blk00000001/sig00000796 ),
.Q15(\NLW_blk00000001/blk00000759_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000758 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000795 ),
.Q(\blk00000001/sig000005e4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000757 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000064b ),
.Q(\blk00000001/sig00000795 ),
.Q15(\NLW_blk00000001/blk00000757_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000756 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000794 ),
.Q(\blk00000001/sig000005e5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000755 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000064c ),
.Q(\blk00000001/sig00000794 ),
.Q15(\NLW_blk00000001/blk00000755_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000754 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000793 ),
.Q(\blk00000001/sig000005e3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000753 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000064a ),
.Q(\blk00000001/sig00000793 ),
.Q15(\NLW_blk00000001/blk00000753_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000752 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000792 ),
.Q(\blk00000001/sig000005e6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000751 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000064d ),
.Q(\blk00000001/sig00000792 ),
.Q15(\NLW_blk00000001/blk00000751_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000750 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000791 ),
.Q(\blk00000001/sig000005e7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000074f (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000064e ),
.Q(\blk00000001/sig00000791 ),
.Q15(\NLW_blk00000001/blk0000074f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000074e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000790 ),
.Q(\blk00000001/sig000005e9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000074d (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000650 ),
.Q(\blk00000001/sig00000790 ),
.Q15(\NLW_blk00000001/blk0000074d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000074c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000078f ),
.Q(\blk00000001/sig000005ea )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000074b (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000651 ),
.Q(\blk00000001/sig0000078f ),
.Q15(\NLW_blk00000001/blk0000074b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000074a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000078e ),
.Q(\blk00000001/sig000005e8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000749 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000064f ),
.Q(\blk00000001/sig0000078e ),
.Q15(\NLW_blk00000001/blk00000749_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000748 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000078d ),
.Q(\blk00000001/sig000005eb )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000747 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000652 ),
.Q(\blk00000001/sig0000078d ),
.Q15(\NLW_blk00000001/blk00000747_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000746 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000078c ),
.Q(\blk00000001/sig000005ec )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000745 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000653 ),
.Q(\blk00000001/sig0000078c ),
.Q15(\NLW_blk00000001/blk00000745_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000744 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000078b ),
.Q(p[1])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000743 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000051 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000003c1 ),
.Q(\blk00000001/sig0000078b ),
.Q15(\NLW_blk00000001/blk00000743_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000742 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000078a ),
.Q(p[2])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000741 (
.A0(\blk00000001/sig00000051 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000069a ),
.Q(\blk00000001/sig0000078a ),
.Q15(\NLW_blk00000001/blk00000741_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000740 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000789 ),
.Q(p[0])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000073f (
.A0(\blk00000001/sig00000051 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000699 ),
.Q(\blk00000001/sig00000789 ),
.Q15(\NLW_blk00000001/blk0000073f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000073e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000788 ),
.Q(p[3])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000073d (
.A0(\blk00000001/sig00000051 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000003a8 ),
.Q(\blk00000001/sig00000788 ),
.Q15(\NLW_blk00000001/blk0000073d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000073c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000787 ),
.Q(p[4])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000073b (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000627 ),
.Q(\blk00000001/sig00000787 ),
.Q15(\NLW_blk00000001/blk0000073b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000073a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000786 ),
.Q(p[6])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000739 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000629 ),
.Q(\blk00000001/sig00000786 ),
.Q15(\NLW_blk00000001/blk00000739_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000738 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000785 ),
.Q(p[7])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000737 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000038a ),
.Q(\blk00000001/sig00000785 ),
.Q15(\NLW_blk00000001/blk00000737_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000736 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000784 ),
.Q(p[5])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000735 (
.A0(\blk00000001/sig00000052 ),
.A1(\blk00000001/sig00000052 ),
.A2(\blk00000001/sig00000052 ),
.A3(\blk00000001/sig00000052 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000628 ),
.Q(\blk00000001/sig00000784 ),
.Q15(\NLW_blk00000001/blk00000735_Q15_UNCONNECTED )
);
LUT3 #(
.INIT ( 8'h78 ))
\blk00000001/blk00000734 (
.I0(\blk00000001/sig00000782 ),
.I1(\blk00000001/sig0000076e ),
.I2(\blk00000001/sig0000076d ),
.O(\blk00000001/sig000000b3 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000733 (
.I0(\blk00000001/sig0000076d ),
.I1(\blk00000001/sig00000782 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000b5 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000732 (
.I0(\blk00000001/sig0000076c ),
.I1(\blk00000001/sig00000782 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000b7 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000731 (
.I0(\blk00000001/sig0000076b ),
.I1(\blk00000001/sig00000782 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000b9 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000730 (
.I0(\blk00000001/sig0000076a ),
.I1(\blk00000001/sig00000782 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000bb )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000072f (
.I0(\blk00000001/sig00000769 ),
.I1(\blk00000001/sig00000781 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000bd )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000072e (
.I0(\blk00000001/sig00000768 ),
.I1(\blk00000001/sig00000780 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000bf )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000072d (
.I0(\blk00000001/sig00000767 ),
.I1(\blk00000001/sig0000077f ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000c1 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000072c (
.I0(\blk00000001/sig00000766 ),
.I1(\blk00000001/sig0000077e ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000c3 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000072b (
.I0(\blk00000001/sig00000765 ),
.I1(\blk00000001/sig0000077d ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000c5 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000072a (
.I0(\blk00000001/sig00000764 ),
.I1(\blk00000001/sig0000077c ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000c7 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000729 (
.I0(\blk00000001/sig00000763 ),
.I1(\blk00000001/sig0000077b ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000c9 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000728 (
.I0(\blk00000001/sig00000762 ),
.I1(\blk00000001/sig0000077a ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000cb )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000727 (
.I0(\blk00000001/sig00000761 ),
.I1(\blk00000001/sig00000779 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000cd )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000726 (
.I0(\blk00000001/sig00000760 ),
.I1(\blk00000001/sig00000778 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000cf )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000725 (
.I0(\blk00000001/sig0000075f ),
.I1(\blk00000001/sig00000777 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000d1 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000724 (
.I0(\blk00000001/sig0000075e ),
.I1(\blk00000001/sig00000776 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000d3 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000723 (
.I0(\blk00000001/sig0000075d ),
.I1(\blk00000001/sig00000775 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000d5 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000722 (
.I0(\blk00000001/sig0000075c ),
.I1(\blk00000001/sig00000774 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000d7 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000721 (
.I0(\blk00000001/sig0000075b ),
.I1(\blk00000001/sig00000773 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000d9 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000720 (
.I0(\blk00000001/sig0000075a ),
.I1(\blk00000001/sig00000772 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000db )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000071f (
.I0(\blk00000001/sig00000759 ),
.I1(\blk00000001/sig00000771 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000dd )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk0000071e (
.I0(\blk00000001/sig00000758 ),
.I1(\blk00000001/sig00000770 ),
.I2(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000000df )
);
LUT3 #(
.INIT ( 8'hD7 ))
\blk00000001/blk0000071d (
.I0(b[19]),
.I1(a[18]),
.I2(a[17]),
.O(\blk00000001/sig00000783 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000071c (
.I0(\blk00000001/sig0000076f ),
.I1(\blk00000001/sig0000076e ),
.O(\blk00000001/sig000005d4 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000071b (
.I0(b[0]),
.I1(a[1]),
.O(\blk00000001/sig00000562 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000071a (
.I0(b[0]),
.I1(a[3]),
.O(\blk00000001/sig0000055f )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000719 (
.I0(b[0]),
.I1(a[5]),
.O(\blk00000001/sig0000055c )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000718 (
.I0(b[0]),
.I1(a[7]),
.O(\blk00000001/sig00000559 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000717 (
.I0(b[0]),
.I1(a[9]),
.O(\blk00000001/sig00000556 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000716 (
.I0(b[0]),
.I1(a[11]),
.O(\blk00000001/sig00000553 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000715 (
.I0(b[0]),
.I1(a[13]),
.O(\blk00000001/sig00000550 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000714 (
.I0(b[0]),
.I1(a[15]),
.O(\blk00000001/sig0000054d )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk00000713 (
.I0(b[0]),
.I1(a[17]),
.O(\blk00000001/sig00000485 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000712 (
.I0(b[10]),
.I1(a[1]),
.I2(b[9]),
.I3(a[2]),
.O(\blk00000001/sig000002cf )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000711 (
.I0(b[10]),
.I1(a[2]),
.I2(b[11]),
.I3(a[1]),
.O(\blk00000001/sig000002be )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000710 (
.I0(b[11]),
.I1(a[2]),
.I2(b[12]),
.I3(a[1]),
.O(\blk00000001/sig000002ad )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070f (
.I0(b[12]),
.I1(a[2]),
.I2(b[13]),
.I3(a[1]),
.O(\blk00000001/sig0000029c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070e (
.I0(b[13]),
.I1(a[2]),
.I2(b[14]),
.I3(a[1]),
.O(\blk00000001/sig0000028b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070d (
.I0(b[14]),
.I1(a[2]),
.I2(b[15]),
.I3(a[1]),
.O(\blk00000001/sig0000027a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070c (
.I0(b[15]),
.I1(a[2]),
.I2(b[16]),
.I3(a[1]),
.O(\blk00000001/sig00000269 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070b (
.I0(b[16]),
.I1(a[2]),
.I2(b[17]),
.I3(a[1]),
.O(\blk00000001/sig00000258 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070a (
.I0(b[17]),
.I1(a[2]),
.I2(b[18]),
.I3(a[1]),
.O(\blk00000001/sig00000247 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000709 (
.I0(b[18]),
.I1(a[2]),
.I2(b[19]),
.I3(a[1]),
.O(\blk00000001/sig00000236 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000708 (
.I0(b[0]),
.I1(a[2]),
.I2(b[1]),
.I3(a[1]),
.O(\blk00000001/sig00000370 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000707 (
.I0(b[19]),
.I1(a[2]),
.I2(a[1]),
.O(\blk00000001/sig00000225 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000706 (
.I0(b[19]),
.I1(a[2]),
.I2(a[1]),
.O(\blk00000001/sig00000214 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000705 (
.I0(b[1]),
.I1(a[2]),
.I2(b[2]),
.I3(a[1]),
.O(\blk00000001/sig00000357 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000704 (
.I0(b[2]),
.I1(a[2]),
.I2(b[3]),
.I3(a[1]),
.O(\blk00000001/sig00000346 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000703 (
.I0(b[3]),
.I1(a[2]),
.I2(b[4]),
.I3(a[1]),
.O(\blk00000001/sig00000335 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000702 (
.I0(b[4]),
.I1(a[2]),
.I2(b[5]),
.I3(a[1]),
.O(\blk00000001/sig00000324 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000701 (
.I0(b[5]),
.I1(a[2]),
.I2(b[6]),
.I3(a[1]),
.O(\blk00000001/sig00000313 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000700 (
.I0(b[6]),
.I1(a[2]),
.I2(b[7]),
.I3(a[1]),
.O(\blk00000001/sig00000302 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ff (
.I0(b[7]),
.I1(a[2]),
.I2(b[8]),
.I3(a[1]),
.O(\blk00000001/sig000002f1 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fe (
.I0(b[8]),
.I1(a[2]),
.I2(b[9]),
.I3(a[1]),
.O(\blk00000001/sig000002e0 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fd (
.I0(b[10]),
.I1(a[3]),
.I2(b[9]),
.I3(a[4]),
.O(\blk00000001/sig000002cd )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fc (
.I0(b[10]),
.I1(a[4]),
.I2(b[11]),
.I3(a[3]),
.O(\blk00000001/sig000002bc )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fb (
.I0(b[11]),
.I1(a[4]),
.I2(b[12]),
.I3(a[3]),
.O(\blk00000001/sig000002ab )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fa (
.I0(b[12]),
.I1(a[4]),
.I2(b[13]),
.I3(a[3]),
.O(\blk00000001/sig0000029a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f9 (
.I0(b[13]),
.I1(a[4]),
.I2(b[14]),
.I3(a[3]),
.O(\blk00000001/sig00000289 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f8 (
.I0(b[14]),
.I1(a[4]),
.I2(b[15]),
.I3(a[3]),
.O(\blk00000001/sig00000278 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f7 (
.I0(b[15]),
.I1(a[4]),
.I2(b[16]),
.I3(a[3]),
.O(\blk00000001/sig00000267 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f6 (
.I0(b[16]),
.I1(a[4]),
.I2(b[17]),
.I3(a[3]),
.O(\blk00000001/sig00000256 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f5 (
.I0(b[17]),
.I1(a[4]),
.I2(b[18]),
.I3(a[3]),
.O(\blk00000001/sig00000245 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f4 (
.I0(b[18]),
.I1(a[4]),
.I2(b[19]),
.I3(a[3]),
.O(\blk00000001/sig00000234 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f3 (
.I0(b[0]),
.I1(a[4]),
.I2(b[1]),
.I3(a[3]),
.O(\blk00000001/sig0000036d )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006f2 (
.I0(b[19]),
.I1(a[4]),
.I2(a[3]),
.O(\blk00000001/sig00000223 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006f1 (
.I0(b[19]),
.I1(a[4]),
.I2(a[3]),
.O(\blk00000001/sig00000213 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f0 (
.I0(b[1]),
.I1(a[4]),
.I2(b[2]),
.I3(a[3]),
.O(\blk00000001/sig00000355 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ef (
.I0(b[2]),
.I1(a[4]),
.I2(b[3]),
.I3(a[3]),
.O(\blk00000001/sig00000344 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ee (
.I0(b[3]),
.I1(a[4]),
.I2(b[4]),
.I3(a[3]),
.O(\blk00000001/sig00000333 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ed (
.I0(b[4]),
.I1(a[4]),
.I2(b[5]),
.I3(a[3]),
.O(\blk00000001/sig00000322 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ec (
.I0(b[5]),
.I1(a[4]),
.I2(b[6]),
.I3(a[3]),
.O(\blk00000001/sig00000311 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006eb (
.I0(b[6]),
.I1(a[4]),
.I2(b[7]),
.I3(a[3]),
.O(\blk00000001/sig00000300 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ea (
.I0(b[7]),
.I1(a[4]),
.I2(b[8]),
.I3(a[3]),
.O(\blk00000001/sig000002ef )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e9 (
.I0(b[8]),
.I1(a[4]),
.I2(b[9]),
.I3(a[3]),
.O(\blk00000001/sig000002de )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e8 (
.I0(b[10]),
.I1(a[5]),
.I2(b[9]),
.I3(a[6]),
.O(\blk00000001/sig000002cb )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e7 (
.I0(b[10]),
.I1(a[6]),
.I2(b[11]),
.I3(a[5]),
.O(\blk00000001/sig000002ba )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e6 (
.I0(b[11]),
.I1(a[6]),
.I2(b[12]),
.I3(a[5]),
.O(\blk00000001/sig000002a9 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e5 (
.I0(b[12]),
.I1(a[6]),
.I2(b[13]),
.I3(a[5]),
.O(\blk00000001/sig00000298 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e4 (
.I0(b[13]),
.I1(a[6]),
.I2(b[14]),
.I3(a[5]),
.O(\blk00000001/sig00000287 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e3 (
.I0(b[14]),
.I1(a[6]),
.I2(b[15]),
.I3(a[5]),
.O(\blk00000001/sig00000276 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e2 (
.I0(b[15]),
.I1(a[6]),
.I2(b[16]),
.I3(a[5]),
.O(\blk00000001/sig00000265 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e1 (
.I0(b[16]),
.I1(a[6]),
.I2(b[17]),
.I3(a[5]),
.O(\blk00000001/sig00000254 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e0 (
.I0(b[17]),
.I1(a[6]),
.I2(b[18]),
.I3(a[5]),
.O(\blk00000001/sig00000243 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006df (
.I0(b[18]),
.I1(a[6]),
.I2(b[19]),
.I3(a[5]),
.O(\blk00000001/sig00000232 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006de (
.I0(b[0]),
.I1(a[6]),
.I2(b[1]),
.I3(a[5]),
.O(\blk00000001/sig0000036a )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006dd (
.I0(b[19]),
.I1(a[6]),
.I2(a[5]),
.O(\blk00000001/sig00000221 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006dc (
.I0(b[19]),
.I1(a[6]),
.I2(a[5]),
.O(\blk00000001/sig00000212 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006db (
.I0(b[1]),
.I1(a[6]),
.I2(b[2]),
.I3(a[5]),
.O(\blk00000001/sig00000353 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006da (
.I0(b[2]),
.I1(a[6]),
.I2(b[3]),
.I3(a[5]),
.O(\blk00000001/sig00000342 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d9 (
.I0(b[3]),
.I1(a[6]),
.I2(b[4]),
.I3(a[5]),
.O(\blk00000001/sig00000331 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d8 (
.I0(b[4]),
.I1(a[6]),
.I2(b[5]),
.I3(a[5]),
.O(\blk00000001/sig00000320 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d7 (
.I0(b[5]),
.I1(a[6]),
.I2(b[6]),
.I3(a[5]),
.O(\blk00000001/sig0000030f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d6 (
.I0(b[6]),
.I1(a[6]),
.I2(b[7]),
.I3(a[5]),
.O(\blk00000001/sig000002fe )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d5 (
.I0(b[7]),
.I1(a[6]),
.I2(b[8]),
.I3(a[5]),
.O(\blk00000001/sig000002ed )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d4 (
.I0(b[8]),
.I1(a[6]),
.I2(b[9]),
.I3(a[5]),
.O(\blk00000001/sig000002dc )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d3 (
.I0(b[10]),
.I1(a[7]),
.I2(b[9]),
.I3(a[8]),
.O(\blk00000001/sig000002c9 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d2 (
.I0(b[10]),
.I1(a[8]),
.I2(b[11]),
.I3(a[7]),
.O(\blk00000001/sig000002b8 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d1 (
.I0(b[11]),
.I1(a[8]),
.I2(b[12]),
.I3(a[7]),
.O(\blk00000001/sig000002a7 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d0 (
.I0(b[12]),
.I1(a[8]),
.I2(b[13]),
.I3(a[7]),
.O(\blk00000001/sig00000296 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cf (
.I0(b[13]),
.I1(a[8]),
.I2(b[14]),
.I3(a[7]),
.O(\blk00000001/sig00000285 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ce (
.I0(b[14]),
.I1(a[8]),
.I2(b[15]),
.I3(a[7]),
.O(\blk00000001/sig00000274 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cd (
.I0(b[15]),
.I1(a[8]),
.I2(b[16]),
.I3(a[7]),
.O(\blk00000001/sig00000263 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cc (
.I0(b[16]),
.I1(a[8]),
.I2(b[17]),
.I3(a[7]),
.O(\blk00000001/sig00000252 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cb (
.I0(b[17]),
.I1(a[8]),
.I2(b[18]),
.I3(a[7]),
.O(\blk00000001/sig00000241 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ca (
.I0(b[18]),
.I1(a[8]),
.I2(b[19]),
.I3(a[7]),
.O(\blk00000001/sig00000230 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c9 (
.I0(b[0]),
.I1(a[8]),
.I2(b[1]),
.I3(a[7]),
.O(\blk00000001/sig00000367 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006c8 (
.I0(b[19]),
.I1(a[8]),
.I2(a[7]),
.O(\blk00000001/sig0000021f )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006c7 (
.I0(b[19]),
.I1(a[8]),
.I2(a[7]),
.O(\blk00000001/sig00000211 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c6 (
.I0(b[1]),
.I1(a[8]),
.I2(b[2]),
.I3(a[7]),
.O(\blk00000001/sig00000351 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c5 (
.I0(b[2]),
.I1(a[8]),
.I2(b[3]),
.I3(a[7]),
.O(\blk00000001/sig00000340 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c4 (
.I0(b[3]),
.I1(a[8]),
.I2(b[4]),
.I3(a[7]),
.O(\blk00000001/sig0000032f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c3 (
.I0(b[4]),
.I1(a[8]),
.I2(b[5]),
.I3(a[7]),
.O(\blk00000001/sig0000031e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c2 (
.I0(b[5]),
.I1(a[8]),
.I2(b[6]),
.I3(a[7]),
.O(\blk00000001/sig0000030d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c1 (
.I0(b[6]),
.I1(a[8]),
.I2(b[7]),
.I3(a[7]),
.O(\blk00000001/sig000002fc )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c0 (
.I0(b[7]),
.I1(a[8]),
.I2(b[8]),
.I3(a[7]),
.O(\blk00000001/sig000002eb )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006bf (
.I0(b[8]),
.I1(a[8]),
.I2(b[9]),
.I3(a[7]),
.O(\blk00000001/sig000002da )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006be (
.I0(b[10]),
.I1(a[9]),
.I2(b[9]),
.I3(a[10]),
.O(\blk00000001/sig000002c7 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006bd (
.I0(b[10]),
.I1(a[10]),
.I2(b[11]),
.I3(a[9]),
.O(\blk00000001/sig000002b6 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006bc (
.I0(b[11]),
.I1(a[10]),
.I2(b[12]),
.I3(a[9]),
.O(\blk00000001/sig000002a5 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006bb (
.I0(b[12]),
.I1(a[10]),
.I2(b[13]),
.I3(a[9]),
.O(\blk00000001/sig00000294 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ba (
.I0(b[13]),
.I1(a[10]),
.I2(b[14]),
.I3(a[9]),
.O(\blk00000001/sig00000283 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b9 (
.I0(b[14]),
.I1(a[10]),
.I2(b[15]),
.I3(a[9]),
.O(\blk00000001/sig00000272 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b8 (
.I0(b[15]),
.I1(a[10]),
.I2(b[16]),
.I3(a[9]),
.O(\blk00000001/sig00000261 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b7 (
.I0(b[16]),
.I1(a[10]),
.I2(b[17]),
.I3(a[9]),
.O(\blk00000001/sig00000250 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b6 (
.I0(b[17]),
.I1(a[10]),
.I2(b[18]),
.I3(a[9]),
.O(\blk00000001/sig0000023f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b5 (
.I0(b[18]),
.I1(a[10]),
.I2(b[19]),
.I3(a[9]),
.O(\blk00000001/sig0000022e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b4 (
.I0(b[0]),
.I1(a[10]),
.I2(b[1]),
.I3(a[9]),
.O(\blk00000001/sig00000364 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006b3 (
.I0(b[19]),
.I1(a[10]),
.I2(a[9]),
.O(\blk00000001/sig0000021d )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006b2 (
.I0(b[19]),
.I1(a[10]),
.I2(a[9]),
.O(\blk00000001/sig00000210 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b1 (
.I0(b[1]),
.I1(a[10]),
.I2(b[2]),
.I3(a[9]),
.O(\blk00000001/sig0000034f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006b0 (
.I0(b[2]),
.I1(a[10]),
.I2(b[3]),
.I3(a[9]),
.O(\blk00000001/sig0000033e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006af (
.I0(b[3]),
.I1(a[10]),
.I2(b[4]),
.I3(a[9]),
.O(\blk00000001/sig0000032d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ae (
.I0(b[4]),
.I1(a[10]),
.I2(b[5]),
.I3(a[9]),
.O(\blk00000001/sig0000031c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ad (
.I0(b[5]),
.I1(a[10]),
.I2(b[6]),
.I3(a[9]),
.O(\blk00000001/sig0000030b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ac (
.I0(b[6]),
.I1(a[10]),
.I2(b[7]),
.I3(a[9]),
.O(\blk00000001/sig000002fa )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ab (
.I0(b[7]),
.I1(a[10]),
.I2(b[8]),
.I3(a[9]),
.O(\blk00000001/sig000002e9 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006aa (
.I0(b[8]),
.I1(a[10]),
.I2(b[9]),
.I3(a[9]),
.O(\blk00000001/sig000002d8 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a9 (
.I0(b[10]),
.I1(a[11]),
.I2(b[9]),
.I3(a[12]),
.O(\blk00000001/sig000002c5 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a8 (
.I0(b[10]),
.I1(a[12]),
.I2(b[11]),
.I3(a[11]),
.O(\blk00000001/sig000002b4 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a7 (
.I0(b[11]),
.I1(a[12]),
.I2(b[12]),
.I3(a[11]),
.O(\blk00000001/sig000002a3 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a6 (
.I0(b[12]),
.I1(a[12]),
.I2(b[13]),
.I3(a[11]),
.O(\blk00000001/sig00000292 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a5 (
.I0(b[13]),
.I1(a[12]),
.I2(b[14]),
.I3(a[11]),
.O(\blk00000001/sig00000281 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a4 (
.I0(b[14]),
.I1(a[12]),
.I2(b[15]),
.I3(a[11]),
.O(\blk00000001/sig00000270 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a3 (
.I0(b[15]),
.I1(a[12]),
.I2(b[16]),
.I3(a[11]),
.O(\blk00000001/sig0000025f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a2 (
.I0(b[16]),
.I1(a[12]),
.I2(b[17]),
.I3(a[11]),
.O(\blk00000001/sig0000024e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a1 (
.I0(b[17]),
.I1(a[12]),
.I2(b[18]),
.I3(a[11]),
.O(\blk00000001/sig0000023d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006a0 (
.I0(b[18]),
.I1(a[12]),
.I2(b[19]),
.I3(a[11]),
.O(\blk00000001/sig0000022c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000069f (
.I0(b[0]),
.I1(a[12]),
.I2(b[1]),
.I3(a[11]),
.O(\blk00000001/sig00000361 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk0000069e (
.I0(b[19]),
.I1(a[12]),
.I2(a[11]),
.O(\blk00000001/sig0000021b )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk0000069d (
.I0(b[19]),
.I1(a[12]),
.I2(a[11]),
.O(\blk00000001/sig0000020f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000069c (
.I0(b[1]),
.I1(a[12]),
.I2(b[2]),
.I3(a[11]),
.O(\blk00000001/sig0000034d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000069b (
.I0(b[2]),
.I1(a[12]),
.I2(b[3]),
.I3(a[11]),
.O(\blk00000001/sig0000033c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000069a (
.I0(b[3]),
.I1(a[12]),
.I2(b[4]),
.I3(a[11]),
.O(\blk00000001/sig0000032b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000699 (
.I0(b[4]),
.I1(a[12]),
.I2(b[5]),
.I3(a[11]),
.O(\blk00000001/sig0000031a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000698 (
.I0(b[5]),
.I1(a[12]),
.I2(b[6]),
.I3(a[11]),
.O(\blk00000001/sig00000309 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000697 (
.I0(b[6]),
.I1(a[12]),
.I2(b[7]),
.I3(a[11]),
.O(\blk00000001/sig000002f8 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000696 (
.I0(b[7]),
.I1(a[12]),
.I2(b[8]),
.I3(a[11]),
.O(\blk00000001/sig000002e7 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000695 (
.I0(b[8]),
.I1(a[12]),
.I2(b[9]),
.I3(a[11]),
.O(\blk00000001/sig000002d6 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000694 (
.I0(b[10]),
.I1(a[13]),
.I2(b[9]),
.I3(a[14]),
.O(\blk00000001/sig000002c3 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000693 (
.I0(b[10]),
.I1(a[14]),
.I2(b[11]),
.I3(a[13]),
.O(\blk00000001/sig000002b2 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000692 (
.I0(b[11]),
.I1(a[14]),
.I2(b[12]),
.I3(a[13]),
.O(\blk00000001/sig000002a1 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000691 (
.I0(b[12]),
.I1(a[14]),
.I2(b[13]),
.I3(a[13]),
.O(\blk00000001/sig00000290 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000690 (
.I0(b[13]),
.I1(a[14]),
.I2(b[14]),
.I3(a[13]),
.O(\blk00000001/sig0000027f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000068f (
.I0(b[14]),
.I1(a[14]),
.I2(b[15]),
.I3(a[13]),
.O(\blk00000001/sig0000026e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000068e (
.I0(b[15]),
.I1(a[14]),
.I2(b[16]),
.I3(a[13]),
.O(\blk00000001/sig0000025d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000068d (
.I0(b[16]),
.I1(a[14]),
.I2(b[17]),
.I3(a[13]),
.O(\blk00000001/sig0000024c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000068c (
.I0(b[17]),
.I1(a[14]),
.I2(b[18]),
.I3(a[13]),
.O(\blk00000001/sig0000023b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000068b (
.I0(b[18]),
.I1(a[14]),
.I2(b[19]),
.I3(a[13]),
.O(\blk00000001/sig0000022a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000068a (
.I0(b[0]),
.I1(a[14]),
.I2(b[1]),
.I3(a[13]),
.O(\blk00000001/sig0000035e )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000689 (
.I0(b[19]),
.I1(a[14]),
.I2(a[13]),
.O(\blk00000001/sig00000219 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000688 (
.I0(b[19]),
.I1(a[14]),
.I2(a[13]),
.O(\blk00000001/sig0000020e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000687 (
.I0(b[1]),
.I1(a[14]),
.I2(b[2]),
.I3(a[13]),
.O(\blk00000001/sig0000034b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000686 (
.I0(b[2]),
.I1(a[14]),
.I2(b[3]),
.I3(a[13]),
.O(\blk00000001/sig0000033a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000685 (
.I0(b[3]),
.I1(a[14]),
.I2(b[4]),
.I3(a[13]),
.O(\blk00000001/sig00000329 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000684 (
.I0(b[4]),
.I1(a[14]),
.I2(b[5]),
.I3(a[13]),
.O(\blk00000001/sig00000318 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000683 (
.I0(b[5]),
.I1(a[14]),
.I2(b[6]),
.I3(a[13]),
.O(\blk00000001/sig00000307 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000682 (
.I0(b[6]),
.I1(a[14]),
.I2(b[7]),
.I3(a[13]),
.O(\blk00000001/sig000002f6 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000681 (
.I0(b[7]),
.I1(a[14]),
.I2(b[8]),
.I3(a[13]),
.O(\blk00000001/sig000002e5 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000680 (
.I0(b[8]),
.I1(a[14]),
.I2(b[9]),
.I3(a[13]),
.O(\blk00000001/sig000002d4 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000067f (
.I0(b[10]),
.I1(a[15]),
.I2(b[9]),
.I3(a[16]),
.O(\blk00000001/sig000002c1 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000067e (
.I0(b[10]),
.I1(a[16]),
.I2(b[11]),
.I3(a[15]),
.O(\blk00000001/sig000002b0 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000067d (
.I0(b[11]),
.I1(a[16]),
.I2(b[12]),
.I3(a[15]),
.O(\blk00000001/sig0000029f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000067c (
.I0(b[12]),
.I1(a[16]),
.I2(b[13]),
.I3(a[15]),
.O(\blk00000001/sig0000028e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000067b (
.I0(b[13]),
.I1(a[16]),
.I2(b[14]),
.I3(a[15]),
.O(\blk00000001/sig0000027d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000067a (
.I0(b[14]),
.I1(a[16]),
.I2(b[15]),
.I3(a[15]),
.O(\blk00000001/sig0000026c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000679 (
.I0(b[15]),
.I1(a[16]),
.I2(b[16]),
.I3(a[15]),
.O(\blk00000001/sig0000025b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000678 (
.I0(b[16]),
.I1(a[16]),
.I2(b[17]),
.I3(a[15]),
.O(\blk00000001/sig0000024a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000677 (
.I0(b[17]),
.I1(a[16]),
.I2(b[18]),
.I3(a[15]),
.O(\blk00000001/sig00000239 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000676 (
.I0(b[18]),
.I1(a[16]),
.I2(b[19]),
.I3(a[15]),
.O(\blk00000001/sig00000228 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000675 (
.I0(b[0]),
.I1(a[16]),
.I2(b[1]),
.I3(a[15]),
.O(\blk00000001/sig0000035b )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000674 (
.I0(b[19]),
.I1(a[16]),
.I2(a[15]),
.O(\blk00000001/sig00000217 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000673 (
.I0(b[19]),
.I1(a[16]),
.I2(a[15]),
.O(\blk00000001/sig0000020d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000672 (
.I0(b[1]),
.I1(a[16]),
.I2(b[2]),
.I3(a[15]),
.O(\blk00000001/sig00000349 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000671 (
.I0(b[2]),
.I1(a[16]),
.I2(b[3]),
.I3(a[15]),
.O(\blk00000001/sig00000338 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000670 (
.I0(b[3]),
.I1(a[16]),
.I2(b[4]),
.I3(a[15]),
.O(\blk00000001/sig00000327 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000066f (
.I0(b[4]),
.I1(a[16]),
.I2(b[5]),
.I3(a[15]),
.O(\blk00000001/sig00000316 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000066e (
.I0(b[5]),
.I1(a[16]),
.I2(b[6]),
.I3(a[15]),
.O(\blk00000001/sig00000305 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000066d (
.I0(b[6]),
.I1(a[16]),
.I2(b[7]),
.I3(a[15]),
.O(\blk00000001/sig000002f4 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000066c (
.I0(b[7]),
.I1(a[16]),
.I2(b[8]),
.I3(a[15]),
.O(\blk00000001/sig000002e3 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000066b (
.I0(b[8]),
.I1(a[16]),
.I2(b[9]),
.I3(a[15]),
.O(\blk00000001/sig000002d2 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk0000066a (
.I0(b[10]),
.I1(b[11]),
.I2(a[18]),
.I3(a[17]),
.O(\blk00000001/sig00000201 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000669 (
.I0(b[17]),
.I1(b[18]),
.I2(a[18]),
.I3(a[17]),
.O(\blk00000001/sig000001fa )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000668 (
.I0(b[0]),
.I1(a[17]),
.I2(a[18]),
.I3(b[1]),
.O(\blk00000001/sig0000020b )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000667 (
.I0(b[1]),
.I1(a[17]),
.I2(a[18]),
.I3(b[2]),
.O(\blk00000001/sig0000020a )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000666 (
.I0(b[2]),
.I1(a[17]),
.I2(a[18]),
.I3(b[3]),
.O(\blk00000001/sig00000209 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000665 (
.I0(b[3]),
.I1(a[17]),
.I2(a[18]),
.I3(b[4]),
.O(\blk00000001/sig00000208 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000664 (
.I0(b[4]),
.I1(a[17]),
.I2(a[18]),
.I3(b[5]),
.O(\blk00000001/sig00000207 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000663 (
.I0(b[5]),
.I1(a[17]),
.I2(a[18]),
.I3(b[6]),
.O(\blk00000001/sig00000206 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000662 (
.I0(b[6]),
.I1(b[7]),
.I2(a[18]),
.I3(a[17]),
.O(\blk00000001/sig00000205 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000661 (
.I0(a[17]),
.I1(b[7]),
.I2(b[8]),
.I3(a[18]),
.O(\blk00000001/sig00000204 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000660 (
.I0(a[17]),
.I1(a[18]),
.I2(b[9]),
.I3(b[8]),
.O(\blk00000001/sig00000203 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk0000065f (
.I0(a[17]),
.I1(a[18]),
.I2(b[10]),
.I3(b[9]),
.O(\blk00000001/sig00000202 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk0000065e (
.I0(b[11]),
.I1(a[17]),
.I2(a[18]),
.I3(b[12]),
.O(\blk00000001/sig00000200 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk0000065d (
.I0(b[12]),
.I1(a[17]),
.I2(a[18]),
.I3(b[13]),
.O(\blk00000001/sig000001ff )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk0000065c (
.I0(b[13]),
.I1(a[17]),
.I2(a[18]),
.I3(b[14]),
.O(\blk00000001/sig000001fe )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk0000065b (
.I0(b[14]),
.I1(a[17]),
.I2(a[18]),
.I3(b[15]),
.O(\blk00000001/sig000001fd )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk0000065a (
.I0(b[15]),
.I1(a[17]),
.I2(a[18]),
.I3(b[16]),
.O(\blk00000001/sig000001fc )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000659 (
.I0(b[16]),
.I1(a[17]),
.I2(a[18]),
.I3(b[17]),
.O(\blk00000001/sig000001fb )
);
LUT3 #(
.INIT ( 8'hD7 ))
\blk00000001/blk00000658 (
.I0(b[19]),
.I1(a[18]),
.I2(a[17]),
.O(\blk00000001/sig000001f8 )
);
LUT4 #(
.INIT ( 16'h935F ))
\blk00000001/blk00000657 (
.I0(a[17]),
.I1(a[18]),
.I2(b[19]),
.I3(b[18]),
.O(\blk00000001/sig000001f9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000656 (
.C(clk),
.CE(ce),
.D(b[19]),
.Q(\blk00000001/sig00000782 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000655 (
.C(clk),
.CE(ce),
.D(b[16]),
.Q(\blk00000001/sig0000077f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000654 (
.C(clk),
.CE(ce),
.D(b[18]),
.Q(\blk00000001/sig00000781 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000653 (
.C(clk),
.CE(ce),
.D(b[17]),
.Q(\blk00000001/sig00000780 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000652 (
.C(clk),
.CE(ce),
.D(b[13]),
.Q(\blk00000001/sig0000077c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000651 (
.C(clk),
.CE(ce),
.D(b[15]),
.Q(\blk00000001/sig0000077e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000650 (
.C(clk),
.CE(ce),
.D(b[14]),
.Q(\blk00000001/sig0000077d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064f (
.C(clk),
.CE(ce),
.D(b[10]),
.Q(\blk00000001/sig00000779 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064e (
.C(clk),
.CE(ce),
.D(b[12]),
.Q(\blk00000001/sig0000077b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064d (
.C(clk),
.CE(ce),
.D(b[11]),
.Q(\blk00000001/sig0000077a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064c (
.C(clk),
.CE(ce),
.D(b[9]),
.Q(\blk00000001/sig00000778 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064b (
.C(clk),
.CE(ce),
.D(b[8]),
.Q(\blk00000001/sig00000777 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064a (
.C(clk),
.CE(ce),
.D(b[7]),
.Q(\blk00000001/sig00000776 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000649 (
.C(clk),
.CE(ce),
.D(b[6]),
.Q(\blk00000001/sig00000775 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000648 (
.C(clk),
.CE(ce),
.D(b[3]),
.Q(\blk00000001/sig00000772 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000647 (
.C(clk),
.CE(ce),
.D(b[5]),
.Q(\blk00000001/sig00000774 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000646 (
.C(clk),
.CE(ce),
.D(b[4]),
.Q(\blk00000001/sig00000773 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000645 (
.C(clk),
.CE(ce),
.D(b[0]),
.Q(\blk00000001/sig0000076f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000644 (
.C(clk),
.CE(ce),
.D(b[2]),
.Q(\blk00000001/sig00000771 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000643 (
.C(clk),
.CE(ce),
.D(b[1]),
.Q(\blk00000001/sig00000770 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000642 (
.C(clk),
.CE(ce),
.D(a[0]),
.Q(\blk00000001/sig0000076e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000641 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000036c ),
.Q(\blk00000001/sig00000744 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000640 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000354 ),
.Q(\blk00000001/sig00000745 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000343 ),
.Q(\blk00000001/sig00000746 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000332 ),
.Q(\blk00000001/sig00000747 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000321 ),
.Q(\blk00000001/sig00000748 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000310 ),
.Q(\blk00000001/sig00000749 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ff ),
.Q(\blk00000001/sig0000074a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ee ),
.Q(\blk00000001/sig0000074b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000639 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002dd ),
.Q(\blk00000001/sig0000074c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000638 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002cc ),
.Q(\blk00000001/sig0000074d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000637 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002bb ),
.Q(\blk00000001/sig0000074e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000636 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002aa ),
.Q(\blk00000001/sig0000074f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000635 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000299 ),
.Q(\blk00000001/sig00000750 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000634 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000288 ),
.Q(\blk00000001/sig00000751 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000633 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000277 ),
.Q(\blk00000001/sig00000752 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000632 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000266 ),
.Q(\blk00000001/sig00000753 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000631 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000255 ),
.Q(\blk00000001/sig00000754 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000630 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000244 ),
.Q(\blk00000001/sig00000755 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000233 ),
.Q(\blk00000001/sig00000756 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000222 ),
.Q(\blk00000001/sig00000757 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000049c ),
.Q(\blk00000001/sig00000758 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000371 ),
.Q(\blk00000001/sig00000759 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000036f ),
.Q(\blk00000001/sig0000075a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000356 ),
.Q(\blk00000001/sig0000075b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000629 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000345 ),
.Q(\blk00000001/sig0000075c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000628 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000334 ),
.Q(\blk00000001/sig0000075d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000627 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000323 ),
.Q(\blk00000001/sig0000075e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000626 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000312 ),
.Q(\blk00000001/sig0000075f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000625 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000301 ),
.Q(\blk00000001/sig00000760 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000624 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f0 ),
.Q(\blk00000001/sig00000761 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000623 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002df ),
.Q(\blk00000001/sig00000762 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000622 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ce ),
.Q(\blk00000001/sig00000763 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000621 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002bd ),
.Q(\blk00000001/sig00000764 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000620 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ac ),
.Q(\blk00000001/sig00000765 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000029b ),
.Q(\blk00000001/sig00000766 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000028a ),
.Q(\blk00000001/sig00000767 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000279 ),
.Q(\blk00000001/sig00000768 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000268 ),
.Q(\blk00000001/sig00000769 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000257 ),
.Q(\blk00000001/sig0000076a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000246 ),
.Q(\blk00000001/sig0000076b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000619 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000235 ),
.Q(\blk00000001/sig0000076c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000618 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000224 ),
.Q(\blk00000001/sig0000076d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000617 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000496 ),
.Q(\blk00000001/sig0000072e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000616 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000036b ),
.Q(\blk00000001/sig0000072f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000615 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000369 ),
.Q(\blk00000001/sig00000730 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000614 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000352 ),
.Q(\blk00000001/sig00000731 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000613 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000341 ),
.Q(\blk00000001/sig00000732 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000612 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000330 ),
.Q(\blk00000001/sig00000733 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000611 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000031f ),
.Q(\blk00000001/sig00000734 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000610 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000030e ),
.Q(\blk00000001/sig00000735 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002fd ),
.Q(\blk00000001/sig00000736 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ec ),
.Q(\blk00000001/sig00000737 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002db ),
.Q(\blk00000001/sig00000738 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ca ),
.Q(\blk00000001/sig00000739 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b9 ),
.Q(\blk00000001/sig0000073a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a8 ),
.Q(\blk00000001/sig0000073b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000609 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000297 ),
.Q(\blk00000001/sig0000073c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000608 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000286 ),
.Q(\blk00000001/sig0000073d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000607 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000275 ),
.Q(\blk00000001/sig0000073e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000606 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000264 ),
.Q(\blk00000001/sig0000073f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000605 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000253 ),
.Q(\blk00000001/sig00000740 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000604 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000242 ),
.Q(\blk00000001/sig00000741 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000603 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000231 ),
.Q(\blk00000001/sig00000742 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000602 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000220 ),
.Q(\blk00000001/sig00000743 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000601 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000366 ),
.Q(\blk00000001/sig0000071a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000600 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000350 ),
.Q(\blk00000001/sig0000071b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ff (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000033f ),
.Q(\blk00000001/sig0000071c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fe (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000032e ),
.Q(\blk00000001/sig0000071d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000031d ),
.Q(\blk00000001/sig0000071e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000030c ),
.Q(\blk00000001/sig0000071f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002fb ),
.Q(\blk00000001/sig00000720 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fa (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ea ),
.Q(\blk00000001/sig00000721 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d9 ),
.Q(\blk00000001/sig00000722 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c8 ),
.Q(\blk00000001/sig00000723 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b7 ),
.Q(\blk00000001/sig00000724 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a6 ),
.Q(\blk00000001/sig00000725 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000295 ),
.Q(\blk00000001/sig00000726 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig00000727 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000273 ),
.Q(\blk00000001/sig00000728 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000262 ),
.Q(\blk00000001/sig00000729 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000251 ),
.Q(\blk00000001/sig0000072a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000240 ),
.Q(\blk00000001/sig0000072b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ef (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000022f ),
.Q(\blk00000001/sig0000072c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ee (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000021e ),
.Q(\blk00000001/sig0000072d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ed (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000490 ),
.Q(\blk00000001/sig00000704 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ec (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000365 ),
.Q(\blk00000001/sig00000705 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005eb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000363 ),
.Q(\blk00000001/sig00000706 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ea (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000034e ),
.Q(\blk00000001/sig00000707 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000033d ),
.Q(\blk00000001/sig00000708 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000032c ),
.Q(\blk00000001/sig00000709 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000031b ),
.Q(\blk00000001/sig0000070a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000030a ),
.Q(\blk00000001/sig0000070b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f9 ),
.Q(\blk00000001/sig0000070c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e8 ),
.Q(\blk00000001/sig0000070d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d7 ),
.Q(\blk00000001/sig0000070e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c6 ),
.Q(\blk00000001/sig0000070f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b5 ),
.Q(\blk00000001/sig00000710 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a4 ),
.Q(\blk00000001/sig00000711 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005df (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000293 ),
.Q(\blk00000001/sig00000712 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005de (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000282 ),
.Q(\blk00000001/sig00000713 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005dd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000271 ),
.Q(\blk00000001/sig00000714 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005dc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000260 ),
.Q(\blk00000001/sig00000715 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005db (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000024f ),
.Q(\blk00000001/sig00000716 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005da (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000023e ),
.Q(\blk00000001/sig00000717 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000022d ),
.Q(\blk00000001/sig00000718 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000021c ),
.Q(\blk00000001/sig00000719 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000360 ),
.Q(\blk00000001/sig000006f0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000034c ),
.Q(\blk00000001/sig000006f1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000033b ),
.Q(\blk00000001/sig000006f2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000032a ),
.Q(\blk00000001/sig000006f3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000319 ),
.Q(\blk00000001/sig000006f4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000308 ),
.Q(\blk00000001/sig000006f5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f7 ),
.Q(\blk00000001/sig000006f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e6 ),
.Q(\blk00000001/sig000006f7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d5 ),
.Q(\blk00000001/sig000006f8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ce (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c4 ),
.Q(\blk00000001/sig000006f9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b3 ),
.Q(\blk00000001/sig000006fa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a2 ),
.Q(\blk00000001/sig000006fb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000291 ),
.Q(\blk00000001/sig000006fc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ca (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000280 ),
.Q(\blk00000001/sig000006fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000026f ),
.Q(\blk00000001/sig000006fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000025e ),
.Q(\blk00000001/sig000006ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000024d ),
.Q(\blk00000001/sig00000700 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000023c ),
.Q(\blk00000001/sig00000701 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000022b ),
.Q(\blk00000001/sig00000702 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000021a ),
.Q(\blk00000001/sig00000703 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000359 ),
.Q(\blk00000001/sig000006b0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000358 ),
.Q(\blk00000001/sig000006b1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000347 ),
.Q(\blk00000001/sig000006b2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000336 ),
.Q(\blk00000001/sig000006b3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000325 ),
.Q(\blk00000001/sig000006b4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005be (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000314 ),
.Q(\blk00000001/sig000006b5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000303 ),
.Q(\blk00000001/sig000006b6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f2 ),
.Q(\blk00000001/sig000006b7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e1 ),
.Q(\blk00000001/sig000006b8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ba (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d0 ),
.Q(\blk00000001/sig000006b9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002bf ),
.Q(\blk00000001/sig000006ba )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ae ),
.Q(\blk00000001/sig000006bb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000029d ),
.Q(\blk00000001/sig000006bc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000028c ),
.Q(\blk00000001/sig000006bd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000027b ),
.Q(\blk00000001/sig000006be )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000026a ),
.Q(\blk00000001/sig000006bf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000259 ),
.Q(\blk00000001/sig000006c0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000248 ),
.Q(\blk00000001/sig000006c1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000237 ),
.Q(\blk00000001/sig000006c2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000226 ),
.Q(\blk00000001/sig000006c3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005af (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000215 ),
.Q(\blk00000001/sig000006c4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ae (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000020c ),
.Q(\blk00000001/sig000006c5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ad (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000048a ),
.Q(\blk00000001/sig000006da )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ac (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000035f ),
.Q(\blk00000001/sig000006db )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ab (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000035d ),
.Q(\blk00000001/sig000006dc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005aa (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000034a ),
.Q(\blk00000001/sig000006dd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000339 ),
.Q(\blk00000001/sig000006de )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000328 ),
.Q(\blk00000001/sig000006df )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000317 ),
.Q(\blk00000001/sig000006e0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000306 ),
.Q(\blk00000001/sig000006e1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f5 ),
.Q(\blk00000001/sig000006e2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e4 ),
.Q(\blk00000001/sig000006e3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d3 ),
.Q(\blk00000001/sig000006e4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c2 ),
.Q(\blk00000001/sig000006e5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b1 ),
.Q(\blk00000001/sig000006e6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a0 ),
.Q(\blk00000001/sig000006e7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000028f ),
.Q(\blk00000001/sig000006e8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000027e ),
.Q(\blk00000001/sig000006e9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000026d ),
.Q(\blk00000001/sig000006ea )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000025c ),
.Q(\blk00000001/sig000006eb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000024b ),
.Q(\blk00000001/sig000006ec )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000023a ),
.Q(\blk00000001/sig000006ed )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000599 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000229 ),
.Q(\blk00000001/sig000006ee )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000598 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000218 ),
.Q(\blk00000001/sig000006ef )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000597 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000035a ),
.Q(\blk00000001/sig000006c6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000596 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000348 ),
.Q(\blk00000001/sig000006c7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000595 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000337 ),
.Q(\blk00000001/sig000006c8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000594 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000326 ),
.Q(\blk00000001/sig000006c9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000593 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000315 ),
.Q(\blk00000001/sig000006ca )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000592 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000304 ),
.Q(\blk00000001/sig000006cb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000591 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f3 ),
.Q(\blk00000001/sig000006cc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000590 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e2 ),
.Q(\blk00000001/sig000006cd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d1 ),
.Q(\blk00000001/sig000006ce )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c0 ),
.Q(\blk00000001/sig000006cf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002af ),
.Q(\blk00000001/sig000006d0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000029e ),
.Q(\blk00000001/sig000006d1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000028d ),
.Q(\blk00000001/sig000006d2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000027c ),
.Q(\blk00000001/sig000006d3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000589 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000026b ),
.Q(\blk00000001/sig000006d4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000588 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000025a ),
.Q(\blk00000001/sig000006d5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000587 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000249 ),
.Q(\blk00000001/sig000006d6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000586 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000238 ),
.Q(\blk00000001/sig000006d7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000585 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000227 ),
.Q(\blk00000001/sig000006d8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000584 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000216 ),
.Q(\blk00000001/sig000006d9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000583 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a9 ),
.Q(\blk00000001/sig0000066c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000582 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005aa ),
.Q(\blk00000001/sig0000066d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000581 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ab ),
.Q(\blk00000001/sig0000066e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000580 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ac ),
.Q(\blk00000001/sig0000066f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ad ),
.Q(\blk00000001/sig00000670 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ae ),
.Q(\blk00000001/sig00000671 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005af ),
.Q(\blk00000001/sig00000672 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b0 ),
.Q(\blk00000001/sig00000673 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b1 ),
.Q(\blk00000001/sig00000674 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b2 ),
.Q(\blk00000001/sig00000675 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000579 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b3 ),
.Q(\blk00000001/sig00000676 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000578 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b4 ),
.Q(\blk00000001/sig00000677 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000577 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b5 ),
.Q(\blk00000001/sig00000678 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000576 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b6 ),
.Q(\blk00000001/sig00000679 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000575 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b7 ),
.Q(\blk00000001/sig0000067a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000574 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b8 ),
.Q(\blk00000001/sig0000067b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000573 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b9 ),
.Q(\blk00000001/sig0000067c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000572 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ba ),
.Q(\blk00000001/sig0000067d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000571 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005bb ),
.Q(\blk00000001/sig0000067e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000570 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005bc ),
.Q(\blk00000001/sig0000067f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005bd ),
.Q(\blk00000001/sig00000680 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d4 ),
.Q(\blk00000001/sig00000699 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c2 ),
.Q(\blk00000001/sig0000069a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c3 ),
.Q(\blk00000001/sig0000069b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c4 ),
.Q(\blk00000001/sig0000069c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c5 ),
.Q(\blk00000001/sig0000069d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000569 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c6 ),
.Q(\blk00000001/sig0000069e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000568 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c7 ),
.Q(\blk00000001/sig0000069f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000567 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c8 ),
.Q(\blk00000001/sig000006a0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000566 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c9 ),
.Q(\blk00000001/sig000006a1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000565 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003ca ),
.Q(\blk00000001/sig000006a2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000564 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003cb ),
.Q(\blk00000001/sig000006a3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000563 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003cc ),
.Q(\blk00000001/sig000006a4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000562 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003cd ),
.Q(\blk00000001/sig000006a5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000561 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003ce ),
.Q(\blk00000001/sig000006a6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000560 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003cf ),
.Q(\blk00000001/sig000006a7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d0 ),
.Q(\blk00000001/sig000006a8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d1 ),
.Q(\blk00000001/sig000006a9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d2 ),
.Q(\blk00000001/sig000006aa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d3 ),
.Q(\blk00000001/sig000006ab )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d4 ),
.Q(\blk00000001/sig000006ac )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d5 ),
.Q(\blk00000001/sig000006ad )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000559 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d6 ),
.Q(\blk00000001/sig000006ae )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000558 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003d7 ),
.Q(\blk00000001/sig000006af )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000557 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005be ),
.Q(\blk00000001/sig00000683 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000556 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005bf ),
.Q(\blk00000001/sig00000684 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000555 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c0 ),
.Q(\blk00000001/sig00000685 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000554 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c1 ),
.Q(\blk00000001/sig00000686 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000553 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c2 ),
.Q(\blk00000001/sig00000687 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000552 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c3 ),
.Q(\blk00000001/sig00000688 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000551 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c4 ),
.Q(\blk00000001/sig00000689 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000550 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c5 ),
.Q(\blk00000001/sig0000068a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c6 ),
.Q(\blk00000001/sig0000068b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c7 ),
.Q(\blk00000001/sig0000068c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c8 ),
.Q(\blk00000001/sig0000068d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c9 ),
.Q(\blk00000001/sig0000068e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ca ),
.Q(\blk00000001/sig0000068f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cb ),
.Q(\blk00000001/sig00000690 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000549 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cc ),
.Q(\blk00000001/sig00000691 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000548 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cd ),
.Q(\blk00000001/sig00000692 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000547 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ce ),
.Q(\blk00000001/sig00000693 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000546 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cf ),
.Q(\blk00000001/sig00000694 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000545 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d0 ),
.Q(\blk00000001/sig00000695 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000544 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d1 ),
.Q(\blk00000001/sig00000696 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000543 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d2 ),
.Q(\blk00000001/sig00000697 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000542 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d3 ),
.Q(\blk00000001/sig00000698 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000541 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000592 ),
.Q(\blk00000001/sig00000656 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000540 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000593 ),
.Q(\blk00000001/sig00000657 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000594 ),
.Q(\blk00000001/sig00000658 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000595 ),
.Q(\blk00000001/sig00000659 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000596 ),
.Q(\blk00000001/sig0000065a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000597 ),
.Q(\blk00000001/sig0000065b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000598 ),
.Q(\blk00000001/sig0000065c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000599 ),
.Q(\blk00000001/sig0000065d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000539 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059a ),
.Q(\blk00000001/sig0000065e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000538 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059b ),
.Q(\blk00000001/sig0000065f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000537 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059c ),
.Q(\blk00000001/sig00000660 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000536 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059d ),
.Q(\blk00000001/sig00000661 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000535 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059e ),
.Q(\blk00000001/sig00000662 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000534 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059f ),
.Q(\blk00000001/sig00000663 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000533 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a0 ),
.Q(\blk00000001/sig00000664 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000532 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a1 ),
.Q(\blk00000001/sig00000665 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000531 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a2 ),
.Q(\blk00000001/sig00000666 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000530 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a3 ),
.Q(\blk00000001/sig00000667 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a4 ),
.Q(\blk00000001/sig00000668 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a5 ),
.Q(\blk00000001/sig00000669 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a6 ),
.Q(\blk00000001/sig0000066a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a7 ),
.Q(\blk00000001/sig0000066b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057d ),
.Q(\blk00000001/sig0000063f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057e ),
.Q(\blk00000001/sig00000640 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000529 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057f ),
.Q(\blk00000001/sig00000641 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000528 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000580 ),
.Q(\blk00000001/sig00000642 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000527 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000581 ),
.Q(\blk00000001/sig00000643 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000526 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000582 ),
.Q(\blk00000001/sig00000644 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000525 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000583 ),
.Q(\blk00000001/sig00000645 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000524 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000584 ),
.Q(\blk00000001/sig00000646 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000523 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000585 ),
.Q(\blk00000001/sig00000647 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000522 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000586 ),
.Q(\blk00000001/sig00000648 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000521 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000587 ),
.Q(\blk00000001/sig00000649 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000520 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000588 ),
.Q(\blk00000001/sig0000064a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000589 ),
.Q(\blk00000001/sig0000064b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058a ),
.Q(\blk00000001/sig0000064c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058b ),
.Q(\blk00000001/sig0000064d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058c ),
.Q(\blk00000001/sig0000064e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058d ),
.Q(\blk00000001/sig0000064f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058e ),
.Q(\blk00000001/sig00000650 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000519 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058f ),
.Q(\blk00000001/sig00000651 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000518 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000590 ),
.Q(\blk00000001/sig00000652 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000517 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000591 ),
.Q(\blk00000001/sig00000653 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000516 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a9 ),
.Q(\blk00000001/sig00000627 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000515 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003aa ),
.Q(\blk00000001/sig00000628 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000514 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003ab ),
.Q(\blk00000001/sig00000629 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000513 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003ac ),
.Q(\blk00000001/sig0000062a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000512 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003ad ),
.Q(\blk00000001/sig0000062b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000511 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003ae ),
.Q(\blk00000001/sig0000062c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000510 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003af ),
.Q(\blk00000001/sig0000062d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b0 ),
.Q(\blk00000001/sig0000062e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b1 ),
.Q(\blk00000001/sig0000062f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b2 ),
.Q(\blk00000001/sig00000630 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b3 ),
.Q(\blk00000001/sig00000631 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b4 ),
.Q(\blk00000001/sig00000632 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b5 ),
.Q(\blk00000001/sig00000633 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000509 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b6 ),
.Q(\blk00000001/sig00000634 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000508 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b7 ),
.Q(\blk00000001/sig00000635 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000507 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b8 ),
.Q(\blk00000001/sig00000636 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000506 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003b9 ),
.Q(\blk00000001/sig00000637 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000505 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003ba ),
.Q(\blk00000001/sig00000638 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000504 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003bb ),
.Q(\blk00000001/sig00000639 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000503 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003bc ),
.Q(\blk00000001/sig0000063a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000502 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003bd ),
.Q(\blk00000001/sig0000063b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000501 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003be ),
.Q(\blk00000001/sig0000063c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000500 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003bf ),
.Q(\blk00000001/sig0000063d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ff (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003c0 ),
.Q(\blk00000001/sig0000063e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004fe (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000066c ),
.Q(\blk00000001/sig0000060d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004fd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000563 ),
.Q(\blk00000001/sig0000060e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004fc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000564 ),
.Q(\blk00000001/sig0000060f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004fb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000565 ),
.Q(\blk00000001/sig00000610 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004fa (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000566 ),
.Q(\blk00000001/sig00000611 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000567 ),
.Q(\blk00000001/sig00000612 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000568 ),
.Q(\blk00000001/sig00000613 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000569 ),
.Q(\blk00000001/sig00000614 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056a ),
.Q(\blk00000001/sig00000615 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056b ),
.Q(\blk00000001/sig00000616 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056c ),
.Q(\blk00000001/sig00000617 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056d ),
.Q(\blk00000001/sig00000618 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056e ),
.Q(\blk00000001/sig00000619 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056f ),
.Q(\blk00000001/sig0000061a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004f0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000570 ),
.Q(\blk00000001/sig0000061b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ef (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000571 ),
.Q(\blk00000001/sig0000061c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ee (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000572 ),
.Q(\blk00000001/sig0000061d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ed (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000573 ),
.Q(\blk00000001/sig0000061e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ec (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000574 ),
.Q(\blk00000001/sig0000061f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004eb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000575 ),
.Q(\blk00000001/sig00000620 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ea (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000576 ),
.Q(\blk00000001/sig00000621 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000577 ),
.Q(\blk00000001/sig00000622 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000578 ),
.Q(\blk00000001/sig00000623 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000579 ),
.Q(\blk00000001/sig00000624 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057a ),
.Q(\blk00000001/sig00000625 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057b ),
.Q(\blk00000001/sig00000626 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038b ),
.Q(\blk00000001/sig000005ed )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038c ),
.Q(\blk00000001/sig000005ee )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038d ),
.Q(\blk00000001/sig000005ef )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038e ),
.Q(\blk00000001/sig000005f0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004e0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038f ),
.Q(\blk00000001/sig000005f1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004df (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000390 ),
.Q(\blk00000001/sig000005f2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004de (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000391 ),
.Q(\blk00000001/sig000005f3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004dd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000392 ),
.Q(\blk00000001/sig000005f4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004dc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000393 ),
.Q(\blk00000001/sig000005f5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004db (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000394 ),
.Q(\blk00000001/sig000005f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004da (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000395 ),
.Q(\blk00000001/sig000005f7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000396 ),
.Q(\blk00000001/sig000005f8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000397 ),
.Q(\blk00000001/sig000005f9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000398 ),
.Q(\blk00000001/sig000005fa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000399 ),
.Q(\blk00000001/sig000005fb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000039a ),
.Q(\blk00000001/sig000005fc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000039b ),
.Q(\blk00000001/sig000005fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000039c ),
.Q(\blk00000001/sig000005fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000039d ),
.Q(\blk00000001/sig000005ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000039e ),
.Q(\blk00000001/sig00000600 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004d0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000039f ),
.Q(\blk00000001/sig00000601 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004cf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a0 ),
.Q(\blk00000001/sig00000602 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ce (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a1 ),
.Q(\blk00000001/sig00000603 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004cd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a2 ),
.Q(\blk00000001/sig00000604 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004cc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a3 ),
.Q(\blk00000001/sig00000605 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004cb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a4 ),
.Q(\blk00000001/sig00000606 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ca (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a5 ),
.Q(\blk00000001/sig00000607 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a6 ),
.Q(\blk00000001/sig00000608 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000003a7 ),
.Q(\blk00000001/sig00000609 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ed ),
.Q(p[8])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ee ),
.Q(p[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ef ),
.Q(p[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f0 ),
.Q(p[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f1 ),
.Q(p[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f2 ),
.Q(p[13])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f3 ),
.Q(p[14])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004c0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000372 ),
.Q(p[15])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004bf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000373 ),
.Q(p[16])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004be (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000374 ),
.Q(p[17])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004bd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000375 ),
.Q(p[18])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004bc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000376 ),
.Q(p[19])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004bb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000377 ),
.Q(p[20])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ba (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000378 ),
.Q(p[21])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000379 ),
.Q(p[22])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037a ),
.Q(p[23])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037b ),
.Q(p[24])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037c ),
.Q(p[25])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037d ),
.Q(p[26])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037e ),
.Q(p[27])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037f ),
.Q(p[28])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000380 ),
.Q(p[29])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000381 ),
.Q(p[30])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004b0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000382 ),
.Q(p[31])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004af (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000383 ),
.Q(p[32])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ae (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000384 ),
.Q(p[33])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ad (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000385 ),
.Q(p[34])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ac (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000386 ),
.Q(p[35])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ab (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000387 ),
.Q(p[36])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004aa (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000388 ),
.Q(p[37])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004a9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000389 ),
.Q(p[38])
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004a8 (
.I0(\blk00000001/sig00000744 ),
.I1(\blk00000001/sig0000072e ),
.O(\blk00000001/sig000001f7 )
);
MUXCY \blk00000001/blk000004a7 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig00000744 ),
.S(\blk00000001/sig000001f7 ),
.O(\blk00000001/sig000001f6 )
);
XORCY \blk00000001/blk000004a6 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig000001f7 ),
.O(\blk00000001/sig000005be )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004a5 (
.I0(\blk00000001/sig00000745 ),
.I1(\blk00000001/sig0000072f ),
.O(\blk00000001/sig000001f5 )
);
MUXCY \blk00000001/blk000004a4 (
.CI(\blk00000001/sig000001f6 ),
.DI(\blk00000001/sig00000745 ),
.S(\blk00000001/sig000001f5 ),
.O(\blk00000001/sig000001f4 )
);
XORCY \blk00000001/blk000004a3 (
.CI(\blk00000001/sig000001f6 ),
.LI(\blk00000001/sig000001f5 ),
.O(\blk00000001/sig000005bf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004a2 (
.I0(\blk00000001/sig00000746 ),
.I1(\blk00000001/sig00000730 ),
.O(\blk00000001/sig000001f3 )
);
MUXCY \blk00000001/blk000004a1 (
.CI(\blk00000001/sig000001f4 ),
.DI(\blk00000001/sig00000746 ),
.S(\blk00000001/sig000001f3 ),
.O(\blk00000001/sig000001f2 )
);
XORCY \blk00000001/blk000004a0 (
.CI(\blk00000001/sig000001f4 ),
.LI(\blk00000001/sig000001f3 ),
.O(\blk00000001/sig000005c0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000049f (
.I0(\blk00000001/sig00000747 ),
.I1(\blk00000001/sig00000731 ),
.O(\blk00000001/sig000001f1 )
);
MUXCY \blk00000001/blk0000049e (
.CI(\blk00000001/sig000001f2 ),
.DI(\blk00000001/sig00000747 ),
.S(\blk00000001/sig000001f1 ),
.O(\blk00000001/sig000001f0 )
);
XORCY \blk00000001/blk0000049d (
.CI(\blk00000001/sig000001f2 ),
.LI(\blk00000001/sig000001f1 ),
.O(\blk00000001/sig000005c1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000049c (
.I0(\blk00000001/sig00000748 ),
.I1(\blk00000001/sig00000732 ),
.O(\blk00000001/sig000001ef )
);
MUXCY \blk00000001/blk0000049b (
.CI(\blk00000001/sig000001f0 ),
.DI(\blk00000001/sig00000748 ),
.S(\blk00000001/sig000001ef ),
.O(\blk00000001/sig000001ee )
);
XORCY \blk00000001/blk0000049a (
.CI(\blk00000001/sig000001f0 ),
.LI(\blk00000001/sig000001ef ),
.O(\blk00000001/sig000005c2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000499 (
.I0(\blk00000001/sig00000749 ),
.I1(\blk00000001/sig00000733 ),
.O(\blk00000001/sig000001ed )
);
MUXCY \blk00000001/blk00000498 (
.CI(\blk00000001/sig000001ee ),
.DI(\blk00000001/sig00000749 ),
.S(\blk00000001/sig000001ed ),
.O(\blk00000001/sig000001ec )
);
XORCY \blk00000001/blk00000497 (
.CI(\blk00000001/sig000001ee ),
.LI(\blk00000001/sig000001ed ),
.O(\blk00000001/sig000005c3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000496 (
.I0(\blk00000001/sig0000074a ),
.I1(\blk00000001/sig00000734 ),
.O(\blk00000001/sig000001eb )
);
MUXCY \blk00000001/blk00000495 (
.CI(\blk00000001/sig000001ec ),
.DI(\blk00000001/sig0000074a ),
.S(\blk00000001/sig000001eb ),
.O(\blk00000001/sig000001ea )
);
XORCY \blk00000001/blk00000494 (
.CI(\blk00000001/sig000001ec ),
.LI(\blk00000001/sig000001eb ),
.O(\blk00000001/sig000005c4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000493 (
.I0(\blk00000001/sig0000074b ),
.I1(\blk00000001/sig00000735 ),
.O(\blk00000001/sig000001e9 )
);
MUXCY \blk00000001/blk00000492 (
.CI(\blk00000001/sig000001ea ),
.DI(\blk00000001/sig0000074b ),
.S(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig000001e8 )
);
XORCY \blk00000001/blk00000491 (
.CI(\blk00000001/sig000001ea ),
.LI(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig000005c5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000490 (
.I0(\blk00000001/sig0000074c ),
.I1(\blk00000001/sig00000736 ),
.O(\blk00000001/sig000001e7 )
);
MUXCY \blk00000001/blk0000048f (
.CI(\blk00000001/sig000001e8 ),
.DI(\blk00000001/sig0000074c ),
.S(\blk00000001/sig000001e7 ),
.O(\blk00000001/sig000001e6 )
);
XORCY \blk00000001/blk0000048e (
.CI(\blk00000001/sig000001e8 ),
.LI(\blk00000001/sig000001e7 ),
.O(\blk00000001/sig000005c6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000048d (
.I0(\blk00000001/sig0000074d ),
.I1(\blk00000001/sig00000737 ),
.O(\blk00000001/sig000001e5 )
);
MUXCY \blk00000001/blk0000048c (
.CI(\blk00000001/sig000001e6 ),
.DI(\blk00000001/sig0000074d ),
.S(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig000001e4 )
);
XORCY \blk00000001/blk0000048b (
.CI(\blk00000001/sig000001e6 ),
.LI(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig000005c7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000048a (
.I0(\blk00000001/sig0000074e ),
.I1(\blk00000001/sig00000738 ),
.O(\blk00000001/sig000001e3 )
);
MUXCY \blk00000001/blk00000489 (
.CI(\blk00000001/sig000001e4 ),
.DI(\blk00000001/sig0000074e ),
.S(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig000001e2 )
);
XORCY \blk00000001/blk00000488 (
.CI(\blk00000001/sig000001e4 ),
.LI(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig000005c8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000487 (
.I0(\blk00000001/sig0000074f ),
.I1(\blk00000001/sig00000739 ),
.O(\blk00000001/sig000001e1 )
);
MUXCY \blk00000001/blk00000486 (
.CI(\blk00000001/sig000001e2 ),
.DI(\blk00000001/sig0000074f ),
.S(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig000001e0 )
);
XORCY \blk00000001/blk00000485 (
.CI(\blk00000001/sig000001e2 ),
.LI(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig000005c9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000484 (
.I0(\blk00000001/sig00000750 ),
.I1(\blk00000001/sig0000073a ),
.O(\blk00000001/sig000001df )
);
MUXCY \blk00000001/blk00000483 (
.CI(\blk00000001/sig000001e0 ),
.DI(\blk00000001/sig00000750 ),
.S(\blk00000001/sig000001df ),
.O(\blk00000001/sig000001de )
);
XORCY \blk00000001/blk00000482 (
.CI(\blk00000001/sig000001e0 ),
.LI(\blk00000001/sig000001df ),
.O(\blk00000001/sig000005ca )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000481 (
.I0(\blk00000001/sig00000751 ),
.I1(\blk00000001/sig0000073b ),
.O(\blk00000001/sig000001dd )
);
MUXCY \blk00000001/blk00000480 (
.CI(\blk00000001/sig000001de ),
.DI(\blk00000001/sig00000751 ),
.S(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000001dc )
);
XORCY \blk00000001/blk0000047f (
.CI(\blk00000001/sig000001de ),
.LI(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000005cb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000047e (
.I0(\blk00000001/sig00000752 ),
.I1(\blk00000001/sig0000073c ),
.O(\blk00000001/sig000001db )
);
MUXCY \blk00000001/blk0000047d (
.CI(\blk00000001/sig000001dc ),
.DI(\blk00000001/sig00000752 ),
.S(\blk00000001/sig000001db ),
.O(\blk00000001/sig000001da )
);
XORCY \blk00000001/blk0000047c (
.CI(\blk00000001/sig000001dc ),
.LI(\blk00000001/sig000001db ),
.O(\blk00000001/sig000005cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000047b (
.I0(\blk00000001/sig00000753 ),
.I1(\blk00000001/sig0000073d ),
.O(\blk00000001/sig000001d9 )
);
MUXCY \blk00000001/blk0000047a (
.CI(\blk00000001/sig000001da ),
.DI(\blk00000001/sig00000753 ),
.S(\blk00000001/sig000001d9 ),
.O(\blk00000001/sig000001d8 )
);
XORCY \blk00000001/blk00000479 (
.CI(\blk00000001/sig000001da ),
.LI(\blk00000001/sig000001d9 ),
.O(\blk00000001/sig000005cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000478 (
.I0(\blk00000001/sig00000754 ),
.I1(\blk00000001/sig0000073e ),
.O(\blk00000001/sig000001d7 )
);
MUXCY \blk00000001/blk00000477 (
.CI(\blk00000001/sig000001d8 ),
.DI(\blk00000001/sig00000754 ),
.S(\blk00000001/sig000001d7 ),
.O(\blk00000001/sig000001d6 )
);
XORCY \blk00000001/blk00000476 (
.CI(\blk00000001/sig000001d8 ),
.LI(\blk00000001/sig000001d7 ),
.O(\blk00000001/sig000005ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000475 (
.I0(\blk00000001/sig00000755 ),
.I1(\blk00000001/sig0000073f ),
.O(\blk00000001/sig000001d5 )
);
MUXCY \blk00000001/blk00000474 (
.CI(\blk00000001/sig000001d6 ),
.DI(\blk00000001/sig00000755 ),
.S(\blk00000001/sig000001d5 ),
.O(\blk00000001/sig000001d4 )
);
XORCY \blk00000001/blk00000473 (
.CI(\blk00000001/sig000001d6 ),
.LI(\blk00000001/sig000001d5 ),
.O(\blk00000001/sig000005cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000472 (
.I0(\blk00000001/sig00000756 ),
.I1(\blk00000001/sig00000740 ),
.O(\blk00000001/sig000001d3 )
);
MUXCY \blk00000001/blk00000471 (
.CI(\blk00000001/sig000001d4 ),
.DI(\blk00000001/sig00000756 ),
.S(\blk00000001/sig000001d3 ),
.O(\blk00000001/sig000001d2 )
);
XORCY \blk00000001/blk00000470 (
.CI(\blk00000001/sig000001d4 ),
.LI(\blk00000001/sig000001d3 ),
.O(\blk00000001/sig000005d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000046f (
.I0(\blk00000001/sig00000757 ),
.I1(\blk00000001/sig00000741 ),
.O(\blk00000001/sig000001d1 )
);
MUXCY \blk00000001/blk0000046e (
.CI(\blk00000001/sig000001d2 ),
.DI(\blk00000001/sig00000757 ),
.S(\blk00000001/sig000001d1 ),
.O(\blk00000001/sig000001d0 )
);
XORCY \blk00000001/blk0000046d (
.CI(\blk00000001/sig000001d2 ),
.LI(\blk00000001/sig000001d1 ),
.O(\blk00000001/sig000005d1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000046c (
.I0(\blk00000001/sig00000757 ),
.I1(\blk00000001/sig00000742 ),
.O(\blk00000001/sig000001cf )
);
MUXCY \blk00000001/blk0000046b (
.CI(\blk00000001/sig000001d0 ),
.DI(\blk00000001/sig00000757 ),
.S(\blk00000001/sig000001cf ),
.O(\blk00000001/sig000001ce )
);
XORCY \blk00000001/blk0000046a (
.CI(\blk00000001/sig000001d0 ),
.LI(\blk00000001/sig000001cf ),
.O(\blk00000001/sig000005d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000469 (
.I0(\blk00000001/sig00000757 ),
.I1(\blk00000001/sig00000743 ),
.O(\blk00000001/sig000001cd )
);
XORCY \blk00000001/blk00000468 (
.CI(\blk00000001/sig000001ce ),
.LI(\blk00000001/sig000001cd ),
.O(\blk00000001/sig000005d3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000467 (
.I0(\blk00000001/sig0000071a ),
.I1(\blk00000001/sig00000704 ),
.O(\blk00000001/sig000001cc )
);
MUXCY \blk00000001/blk00000466 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig0000071a ),
.S(\blk00000001/sig000001cc ),
.O(\blk00000001/sig000001cb )
);
XORCY \blk00000001/blk00000465 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig000001cc ),
.O(\blk00000001/sig000005a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000464 (
.I0(\blk00000001/sig0000071b ),
.I1(\blk00000001/sig00000705 ),
.O(\blk00000001/sig000001ca )
);
MUXCY \blk00000001/blk00000463 (
.CI(\blk00000001/sig000001cb ),
.DI(\blk00000001/sig0000071b ),
.S(\blk00000001/sig000001ca ),
.O(\blk00000001/sig000001c9 )
);
XORCY \blk00000001/blk00000462 (
.CI(\blk00000001/sig000001cb ),
.LI(\blk00000001/sig000001ca ),
.O(\blk00000001/sig000005a9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000461 (
.I0(\blk00000001/sig0000071c ),
.I1(\blk00000001/sig00000706 ),
.O(\blk00000001/sig000001c8 )
);
MUXCY \blk00000001/blk00000460 (
.CI(\blk00000001/sig000001c9 ),
.DI(\blk00000001/sig0000071c ),
.S(\blk00000001/sig000001c8 ),
.O(\blk00000001/sig000001c7 )
);
XORCY \blk00000001/blk0000045f (
.CI(\blk00000001/sig000001c9 ),
.LI(\blk00000001/sig000001c8 ),
.O(\blk00000001/sig000005aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000045e (
.I0(\blk00000001/sig0000071d ),
.I1(\blk00000001/sig00000707 ),
.O(\blk00000001/sig000001c6 )
);
MUXCY \blk00000001/blk0000045d (
.CI(\blk00000001/sig000001c7 ),
.DI(\blk00000001/sig0000071d ),
.S(\blk00000001/sig000001c6 ),
.O(\blk00000001/sig000001c5 )
);
XORCY \blk00000001/blk0000045c (
.CI(\blk00000001/sig000001c7 ),
.LI(\blk00000001/sig000001c6 ),
.O(\blk00000001/sig000005ab )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000045b (
.I0(\blk00000001/sig0000071e ),
.I1(\blk00000001/sig00000708 ),
.O(\blk00000001/sig000001c4 )
);
MUXCY \blk00000001/blk0000045a (
.CI(\blk00000001/sig000001c5 ),
.DI(\blk00000001/sig0000071e ),
.S(\blk00000001/sig000001c4 ),
.O(\blk00000001/sig000001c3 )
);
XORCY \blk00000001/blk00000459 (
.CI(\blk00000001/sig000001c5 ),
.LI(\blk00000001/sig000001c4 ),
.O(\blk00000001/sig000005ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000458 (
.I0(\blk00000001/sig0000071f ),
.I1(\blk00000001/sig00000709 ),
.O(\blk00000001/sig000001c2 )
);
MUXCY \blk00000001/blk00000457 (
.CI(\blk00000001/sig000001c3 ),
.DI(\blk00000001/sig0000071f ),
.S(\blk00000001/sig000001c2 ),
.O(\blk00000001/sig000001c1 )
);
XORCY \blk00000001/blk00000456 (
.CI(\blk00000001/sig000001c3 ),
.LI(\blk00000001/sig000001c2 ),
.O(\blk00000001/sig000005ad )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000455 (
.I0(\blk00000001/sig00000720 ),
.I1(\blk00000001/sig0000070a ),
.O(\blk00000001/sig000001c0 )
);
MUXCY \blk00000001/blk00000454 (
.CI(\blk00000001/sig000001c1 ),
.DI(\blk00000001/sig00000720 ),
.S(\blk00000001/sig000001c0 ),
.O(\blk00000001/sig000001bf )
);
XORCY \blk00000001/blk00000453 (
.CI(\blk00000001/sig000001c1 ),
.LI(\blk00000001/sig000001c0 ),
.O(\blk00000001/sig000005ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000452 (
.I0(\blk00000001/sig00000721 ),
.I1(\blk00000001/sig0000070b ),
.O(\blk00000001/sig000001be )
);
MUXCY \blk00000001/blk00000451 (
.CI(\blk00000001/sig000001bf ),
.DI(\blk00000001/sig00000721 ),
.S(\blk00000001/sig000001be ),
.O(\blk00000001/sig000001bd )
);
XORCY \blk00000001/blk00000450 (
.CI(\blk00000001/sig000001bf ),
.LI(\blk00000001/sig000001be ),
.O(\blk00000001/sig000005af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000044f (
.I0(\blk00000001/sig00000722 ),
.I1(\blk00000001/sig0000070c ),
.O(\blk00000001/sig000001bc )
);
MUXCY \blk00000001/blk0000044e (
.CI(\blk00000001/sig000001bd ),
.DI(\blk00000001/sig00000722 ),
.S(\blk00000001/sig000001bc ),
.O(\blk00000001/sig000001bb )
);
XORCY \blk00000001/blk0000044d (
.CI(\blk00000001/sig000001bd ),
.LI(\blk00000001/sig000001bc ),
.O(\blk00000001/sig000005b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000044c (
.I0(\blk00000001/sig00000723 ),
.I1(\blk00000001/sig0000070d ),
.O(\blk00000001/sig000001ba )
);
MUXCY \blk00000001/blk0000044b (
.CI(\blk00000001/sig000001bb ),
.DI(\blk00000001/sig00000723 ),
.S(\blk00000001/sig000001ba ),
.O(\blk00000001/sig000001b9 )
);
XORCY \blk00000001/blk0000044a (
.CI(\blk00000001/sig000001bb ),
.LI(\blk00000001/sig000001ba ),
.O(\blk00000001/sig000005b1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000449 (
.I0(\blk00000001/sig00000724 ),
.I1(\blk00000001/sig0000070e ),
.O(\blk00000001/sig000001b8 )
);
MUXCY \blk00000001/blk00000448 (
.CI(\blk00000001/sig000001b9 ),
.DI(\blk00000001/sig00000724 ),
.S(\blk00000001/sig000001b8 ),
.O(\blk00000001/sig000001b7 )
);
XORCY \blk00000001/blk00000447 (
.CI(\blk00000001/sig000001b9 ),
.LI(\blk00000001/sig000001b8 ),
.O(\blk00000001/sig000005b2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000446 (
.I0(\blk00000001/sig00000725 ),
.I1(\blk00000001/sig0000070f ),
.O(\blk00000001/sig000001b6 )
);
MUXCY \blk00000001/blk00000445 (
.CI(\blk00000001/sig000001b7 ),
.DI(\blk00000001/sig00000725 ),
.S(\blk00000001/sig000001b6 ),
.O(\blk00000001/sig000001b5 )
);
XORCY \blk00000001/blk00000444 (
.CI(\blk00000001/sig000001b7 ),
.LI(\blk00000001/sig000001b6 ),
.O(\blk00000001/sig000005b3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000443 (
.I0(\blk00000001/sig00000726 ),
.I1(\blk00000001/sig00000710 ),
.O(\blk00000001/sig000001b4 )
);
MUXCY \blk00000001/blk00000442 (
.CI(\blk00000001/sig000001b5 ),
.DI(\blk00000001/sig00000726 ),
.S(\blk00000001/sig000001b4 ),
.O(\blk00000001/sig000001b3 )
);
XORCY \blk00000001/blk00000441 (
.CI(\blk00000001/sig000001b5 ),
.LI(\blk00000001/sig000001b4 ),
.O(\blk00000001/sig000005b4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000440 (
.I0(\blk00000001/sig00000727 ),
.I1(\blk00000001/sig00000711 ),
.O(\blk00000001/sig000001b2 )
);
MUXCY \blk00000001/blk0000043f (
.CI(\blk00000001/sig000001b3 ),
.DI(\blk00000001/sig00000727 ),
.S(\blk00000001/sig000001b2 ),
.O(\blk00000001/sig000001b1 )
);
XORCY \blk00000001/blk0000043e (
.CI(\blk00000001/sig000001b3 ),
.LI(\blk00000001/sig000001b2 ),
.O(\blk00000001/sig000005b5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000043d (
.I0(\blk00000001/sig00000728 ),
.I1(\blk00000001/sig00000712 ),
.O(\blk00000001/sig000001b0 )
);
MUXCY \blk00000001/blk0000043c (
.CI(\blk00000001/sig000001b1 ),
.DI(\blk00000001/sig00000728 ),
.S(\blk00000001/sig000001b0 ),
.O(\blk00000001/sig000001af )
);
XORCY \blk00000001/blk0000043b (
.CI(\blk00000001/sig000001b1 ),
.LI(\blk00000001/sig000001b0 ),
.O(\blk00000001/sig000005b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000043a (
.I0(\blk00000001/sig00000729 ),
.I1(\blk00000001/sig00000713 ),
.O(\blk00000001/sig000001ae )
);
MUXCY \blk00000001/blk00000439 (
.CI(\blk00000001/sig000001af ),
.DI(\blk00000001/sig00000729 ),
.S(\blk00000001/sig000001ae ),
.O(\blk00000001/sig000001ad )
);
XORCY \blk00000001/blk00000438 (
.CI(\blk00000001/sig000001af ),
.LI(\blk00000001/sig000001ae ),
.O(\blk00000001/sig000005b7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000437 (
.I0(\blk00000001/sig0000072a ),
.I1(\blk00000001/sig00000714 ),
.O(\blk00000001/sig000001ac )
);
MUXCY \blk00000001/blk00000436 (
.CI(\blk00000001/sig000001ad ),
.DI(\blk00000001/sig0000072a ),
.S(\blk00000001/sig000001ac ),
.O(\blk00000001/sig000001ab )
);
XORCY \blk00000001/blk00000435 (
.CI(\blk00000001/sig000001ad ),
.LI(\blk00000001/sig000001ac ),
.O(\blk00000001/sig000005b8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000434 (
.I0(\blk00000001/sig0000072b ),
.I1(\blk00000001/sig00000715 ),
.O(\blk00000001/sig000001aa )
);
MUXCY \blk00000001/blk00000433 (
.CI(\blk00000001/sig000001ab ),
.DI(\blk00000001/sig0000072b ),
.S(\blk00000001/sig000001aa ),
.O(\blk00000001/sig000001a9 )
);
XORCY \blk00000001/blk00000432 (
.CI(\blk00000001/sig000001ab ),
.LI(\blk00000001/sig000001aa ),
.O(\blk00000001/sig000005b9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000431 (
.I0(\blk00000001/sig0000072c ),
.I1(\blk00000001/sig00000716 ),
.O(\blk00000001/sig000001a8 )
);
MUXCY \blk00000001/blk00000430 (
.CI(\blk00000001/sig000001a9 ),
.DI(\blk00000001/sig0000072c ),
.S(\blk00000001/sig000001a8 ),
.O(\blk00000001/sig000001a7 )
);
XORCY \blk00000001/blk0000042f (
.CI(\blk00000001/sig000001a9 ),
.LI(\blk00000001/sig000001a8 ),
.O(\blk00000001/sig000005ba )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000042e (
.I0(\blk00000001/sig0000072d ),
.I1(\blk00000001/sig00000717 ),
.O(\blk00000001/sig000001a6 )
);
MUXCY \blk00000001/blk0000042d (
.CI(\blk00000001/sig000001a7 ),
.DI(\blk00000001/sig0000072d ),
.S(\blk00000001/sig000001a6 ),
.O(\blk00000001/sig000001a5 )
);
XORCY \blk00000001/blk0000042c (
.CI(\blk00000001/sig000001a7 ),
.LI(\blk00000001/sig000001a6 ),
.O(\blk00000001/sig000005bb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000042b (
.I0(\blk00000001/sig0000072d ),
.I1(\blk00000001/sig00000718 ),
.O(\blk00000001/sig000001a4 )
);
MUXCY \blk00000001/blk0000042a (
.CI(\blk00000001/sig000001a5 ),
.DI(\blk00000001/sig0000072d ),
.S(\blk00000001/sig000001a4 ),
.O(\blk00000001/sig000001a3 )
);
XORCY \blk00000001/blk00000429 (
.CI(\blk00000001/sig000001a5 ),
.LI(\blk00000001/sig000001a4 ),
.O(\blk00000001/sig000005bc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000428 (
.I0(\blk00000001/sig0000072d ),
.I1(\blk00000001/sig00000719 ),
.O(\blk00000001/sig000001a2 )
);
XORCY \blk00000001/blk00000427 (
.CI(\blk00000001/sig000001a3 ),
.LI(\blk00000001/sig000001a2 ),
.O(\blk00000001/sig000005bd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000426 (
.I0(\blk00000001/sig000006f0 ),
.I1(\blk00000001/sig000006da ),
.O(\blk00000001/sig000001a1 )
);
MUXCY \blk00000001/blk00000425 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig000006f0 ),
.S(\blk00000001/sig000001a1 ),
.O(\blk00000001/sig000001a0 )
);
XORCY \blk00000001/blk00000424 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig000001a1 ),
.O(\blk00000001/sig00000592 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000423 (
.I0(\blk00000001/sig000006f1 ),
.I1(\blk00000001/sig000006db ),
.O(\blk00000001/sig0000019f )
);
MUXCY \blk00000001/blk00000422 (
.CI(\blk00000001/sig000001a0 ),
.DI(\blk00000001/sig000006f1 ),
.S(\blk00000001/sig0000019f ),
.O(\blk00000001/sig0000019e )
);
XORCY \blk00000001/blk00000421 (
.CI(\blk00000001/sig000001a0 ),
.LI(\blk00000001/sig0000019f ),
.O(\blk00000001/sig00000593 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000420 (
.I0(\blk00000001/sig000006f2 ),
.I1(\blk00000001/sig000006dc ),
.O(\blk00000001/sig0000019d )
);
MUXCY \blk00000001/blk0000041f (
.CI(\blk00000001/sig0000019e ),
.DI(\blk00000001/sig000006f2 ),
.S(\blk00000001/sig0000019d ),
.O(\blk00000001/sig0000019c )
);
XORCY \blk00000001/blk0000041e (
.CI(\blk00000001/sig0000019e ),
.LI(\blk00000001/sig0000019d ),
.O(\blk00000001/sig00000594 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000041d (
.I0(\blk00000001/sig000006f3 ),
.I1(\blk00000001/sig000006dd ),
.O(\blk00000001/sig0000019b )
);
MUXCY \blk00000001/blk0000041c (
.CI(\blk00000001/sig0000019c ),
.DI(\blk00000001/sig000006f3 ),
.S(\blk00000001/sig0000019b ),
.O(\blk00000001/sig0000019a )
);
XORCY \blk00000001/blk0000041b (
.CI(\blk00000001/sig0000019c ),
.LI(\blk00000001/sig0000019b ),
.O(\blk00000001/sig00000595 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000041a (
.I0(\blk00000001/sig000006f4 ),
.I1(\blk00000001/sig000006de ),
.O(\blk00000001/sig00000199 )
);
MUXCY \blk00000001/blk00000419 (
.CI(\blk00000001/sig0000019a ),
.DI(\blk00000001/sig000006f4 ),
.S(\blk00000001/sig00000199 ),
.O(\blk00000001/sig00000198 )
);
XORCY \blk00000001/blk00000418 (
.CI(\blk00000001/sig0000019a ),
.LI(\blk00000001/sig00000199 ),
.O(\blk00000001/sig00000596 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000417 (
.I0(\blk00000001/sig000006f5 ),
.I1(\blk00000001/sig000006df ),
.O(\blk00000001/sig00000197 )
);
MUXCY \blk00000001/blk00000416 (
.CI(\blk00000001/sig00000198 ),
.DI(\blk00000001/sig000006f5 ),
.S(\blk00000001/sig00000197 ),
.O(\blk00000001/sig00000196 )
);
XORCY \blk00000001/blk00000415 (
.CI(\blk00000001/sig00000198 ),
.LI(\blk00000001/sig00000197 ),
.O(\blk00000001/sig00000597 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000414 (
.I0(\blk00000001/sig000006f6 ),
.I1(\blk00000001/sig000006e0 ),
.O(\blk00000001/sig00000195 )
);
MUXCY \blk00000001/blk00000413 (
.CI(\blk00000001/sig00000196 ),
.DI(\blk00000001/sig000006f6 ),
.S(\blk00000001/sig00000195 ),
.O(\blk00000001/sig00000194 )
);
XORCY \blk00000001/blk00000412 (
.CI(\blk00000001/sig00000196 ),
.LI(\blk00000001/sig00000195 ),
.O(\blk00000001/sig00000598 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000411 (
.I0(\blk00000001/sig000006f7 ),
.I1(\blk00000001/sig000006e1 ),
.O(\blk00000001/sig00000193 )
);
MUXCY \blk00000001/blk00000410 (
.CI(\blk00000001/sig00000194 ),
.DI(\blk00000001/sig000006f7 ),
.S(\blk00000001/sig00000193 ),
.O(\blk00000001/sig00000192 )
);
XORCY \blk00000001/blk0000040f (
.CI(\blk00000001/sig00000194 ),
.LI(\blk00000001/sig00000193 ),
.O(\blk00000001/sig00000599 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000040e (
.I0(\blk00000001/sig000006f8 ),
.I1(\blk00000001/sig000006e2 ),
.O(\blk00000001/sig00000191 )
);
MUXCY \blk00000001/blk0000040d (
.CI(\blk00000001/sig00000192 ),
.DI(\blk00000001/sig000006f8 ),
.S(\blk00000001/sig00000191 ),
.O(\blk00000001/sig00000190 )
);
XORCY \blk00000001/blk0000040c (
.CI(\blk00000001/sig00000192 ),
.LI(\blk00000001/sig00000191 ),
.O(\blk00000001/sig0000059a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000040b (
.I0(\blk00000001/sig000006f9 ),
.I1(\blk00000001/sig000006e3 ),
.O(\blk00000001/sig0000018f )
);
MUXCY \blk00000001/blk0000040a (
.CI(\blk00000001/sig00000190 ),
.DI(\blk00000001/sig000006f9 ),
.S(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000018e )
);
XORCY \blk00000001/blk00000409 (
.CI(\blk00000001/sig00000190 ),
.LI(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000059b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000408 (
.I0(\blk00000001/sig000006fa ),
.I1(\blk00000001/sig000006e4 ),
.O(\blk00000001/sig0000018d )
);
MUXCY \blk00000001/blk00000407 (
.CI(\blk00000001/sig0000018e ),
.DI(\blk00000001/sig000006fa ),
.S(\blk00000001/sig0000018d ),
.O(\blk00000001/sig0000018c )
);
XORCY \blk00000001/blk00000406 (
.CI(\blk00000001/sig0000018e ),
.LI(\blk00000001/sig0000018d ),
.O(\blk00000001/sig0000059c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000405 (
.I0(\blk00000001/sig000006fb ),
.I1(\blk00000001/sig000006e5 ),
.O(\blk00000001/sig0000018b )
);
MUXCY \blk00000001/blk00000404 (
.CI(\blk00000001/sig0000018c ),
.DI(\blk00000001/sig000006fb ),
.S(\blk00000001/sig0000018b ),
.O(\blk00000001/sig0000018a )
);
XORCY \blk00000001/blk00000403 (
.CI(\blk00000001/sig0000018c ),
.LI(\blk00000001/sig0000018b ),
.O(\blk00000001/sig0000059d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000402 (
.I0(\blk00000001/sig000006fc ),
.I1(\blk00000001/sig000006e6 ),
.O(\blk00000001/sig00000189 )
);
MUXCY \blk00000001/blk00000401 (
.CI(\blk00000001/sig0000018a ),
.DI(\blk00000001/sig000006fc ),
.S(\blk00000001/sig00000189 ),
.O(\blk00000001/sig00000188 )
);
XORCY \blk00000001/blk00000400 (
.CI(\blk00000001/sig0000018a ),
.LI(\blk00000001/sig00000189 ),
.O(\blk00000001/sig0000059e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ff (
.I0(\blk00000001/sig000006fd ),
.I1(\blk00000001/sig000006e7 ),
.O(\blk00000001/sig00000187 )
);
MUXCY \blk00000001/blk000003fe (
.CI(\blk00000001/sig00000188 ),
.DI(\blk00000001/sig000006fd ),
.S(\blk00000001/sig00000187 ),
.O(\blk00000001/sig00000186 )
);
XORCY \blk00000001/blk000003fd (
.CI(\blk00000001/sig00000188 ),
.LI(\blk00000001/sig00000187 ),
.O(\blk00000001/sig0000059f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003fc (
.I0(\blk00000001/sig000006fe ),
.I1(\blk00000001/sig000006e8 ),
.O(\blk00000001/sig00000185 )
);
MUXCY \blk00000001/blk000003fb (
.CI(\blk00000001/sig00000186 ),
.DI(\blk00000001/sig000006fe ),
.S(\blk00000001/sig00000185 ),
.O(\blk00000001/sig00000184 )
);
XORCY \blk00000001/blk000003fa (
.CI(\blk00000001/sig00000186 ),
.LI(\blk00000001/sig00000185 ),
.O(\blk00000001/sig000005a0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003f9 (
.I0(\blk00000001/sig000006ff ),
.I1(\blk00000001/sig000006e9 ),
.O(\blk00000001/sig00000183 )
);
MUXCY \blk00000001/blk000003f8 (
.CI(\blk00000001/sig00000184 ),
.DI(\blk00000001/sig000006ff ),
.S(\blk00000001/sig00000183 ),
.O(\blk00000001/sig00000182 )
);
XORCY \blk00000001/blk000003f7 (
.CI(\blk00000001/sig00000184 ),
.LI(\blk00000001/sig00000183 ),
.O(\blk00000001/sig000005a1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003f6 (
.I0(\blk00000001/sig00000700 ),
.I1(\blk00000001/sig000006ea ),
.O(\blk00000001/sig00000181 )
);
MUXCY \blk00000001/blk000003f5 (
.CI(\blk00000001/sig00000182 ),
.DI(\blk00000001/sig00000700 ),
.S(\blk00000001/sig00000181 ),
.O(\blk00000001/sig00000180 )
);
XORCY \blk00000001/blk000003f4 (
.CI(\blk00000001/sig00000182 ),
.LI(\blk00000001/sig00000181 ),
.O(\blk00000001/sig000005a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003f3 (
.I0(\blk00000001/sig00000701 ),
.I1(\blk00000001/sig000006eb ),
.O(\blk00000001/sig0000017f )
);
MUXCY \blk00000001/blk000003f2 (
.CI(\blk00000001/sig00000180 ),
.DI(\blk00000001/sig00000701 ),
.S(\blk00000001/sig0000017f ),
.O(\blk00000001/sig0000017e )
);
XORCY \blk00000001/blk000003f1 (
.CI(\blk00000001/sig00000180 ),
.LI(\blk00000001/sig0000017f ),
.O(\blk00000001/sig000005a3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003f0 (
.I0(\blk00000001/sig00000702 ),
.I1(\blk00000001/sig000006ec ),
.O(\blk00000001/sig0000017d )
);
MUXCY \blk00000001/blk000003ef (
.CI(\blk00000001/sig0000017e ),
.DI(\blk00000001/sig00000702 ),
.S(\blk00000001/sig0000017d ),
.O(\blk00000001/sig0000017c )
);
XORCY \blk00000001/blk000003ee (
.CI(\blk00000001/sig0000017e ),
.LI(\blk00000001/sig0000017d ),
.O(\blk00000001/sig000005a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ed (
.I0(\blk00000001/sig00000703 ),
.I1(\blk00000001/sig000006ed ),
.O(\blk00000001/sig0000017b )
);
MUXCY \blk00000001/blk000003ec (
.CI(\blk00000001/sig0000017c ),
.DI(\blk00000001/sig00000703 ),
.S(\blk00000001/sig0000017b ),
.O(\blk00000001/sig0000017a )
);
XORCY \blk00000001/blk000003eb (
.CI(\blk00000001/sig0000017c ),
.LI(\blk00000001/sig0000017b ),
.O(\blk00000001/sig000005a5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ea (
.I0(\blk00000001/sig00000703 ),
.I1(\blk00000001/sig000006ee ),
.O(\blk00000001/sig00000179 )
);
MUXCY \blk00000001/blk000003e9 (
.CI(\blk00000001/sig0000017a ),
.DI(\blk00000001/sig00000703 ),
.S(\blk00000001/sig00000179 ),
.O(\blk00000001/sig00000178 )
);
XORCY \blk00000001/blk000003e8 (
.CI(\blk00000001/sig0000017a ),
.LI(\blk00000001/sig00000179 ),
.O(\blk00000001/sig000005a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003e7 (
.I0(\blk00000001/sig00000703 ),
.I1(\blk00000001/sig000006ef ),
.O(\blk00000001/sig00000177 )
);
XORCY \blk00000001/blk000003e6 (
.CI(\blk00000001/sig00000178 ),
.LI(\blk00000001/sig00000177 ),
.O(\blk00000001/sig000005a7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003e5 (
.I0(\blk00000001/sig000006c6 ),
.I1(\blk00000001/sig000006b0 ),
.O(\blk00000001/sig00000176 )
);
MUXCY \blk00000001/blk000003e4 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig000006c6 ),
.S(\blk00000001/sig00000176 ),
.O(\blk00000001/sig00000175 )
);
XORCY \blk00000001/blk000003e3 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig00000176 ),
.O(\blk00000001/sig0000057c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003e2 (
.I0(\blk00000001/sig000006c7 ),
.I1(\blk00000001/sig000006b1 ),
.O(\blk00000001/sig00000174 )
);
MUXCY \blk00000001/blk000003e1 (
.CI(\blk00000001/sig00000175 ),
.DI(\blk00000001/sig000006c7 ),
.S(\blk00000001/sig00000174 ),
.O(\blk00000001/sig00000173 )
);
XORCY \blk00000001/blk000003e0 (
.CI(\blk00000001/sig00000175 ),
.LI(\blk00000001/sig00000174 ),
.O(\blk00000001/sig0000057d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003df (
.I0(\blk00000001/sig000006c8 ),
.I1(\blk00000001/sig000006b2 ),
.O(\blk00000001/sig00000172 )
);
MUXCY \blk00000001/blk000003de (
.CI(\blk00000001/sig00000173 ),
.DI(\blk00000001/sig000006c8 ),
.S(\blk00000001/sig00000172 ),
.O(\blk00000001/sig00000171 )
);
XORCY \blk00000001/blk000003dd (
.CI(\blk00000001/sig00000173 ),
.LI(\blk00000001/sig00000172 ),
.O(\blk00000001/sig0000057e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003dc (
.I0(\blk00000001/sig000006c9 ),
.I1(\blk00000001/sig000006b3 ),
.O(\blk00000001/sig00000170 )
);
MUXCY \blk00000001/blk000003db (
.CI(\blk00000001/sig00000171 ),
.DI(\blk00000001/sig000006c9 ),
.S(\blk00000001/sig00000170 ),
.O(\blk00000001/sig0000016f )
);
XORCY \blk00000001/blk000003da (
.CI(\blk00000001/sig00000171 ),
.LI(\blk00000001/sig00000170 ),
.O(\blk00000001/sig0000057f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003d9 (
.I0(\blk00000001/sig000006ca ),
.I1(\blk00000001/sig000006b4 ),
.O(\blk00000001/sig0000016e )
);
MUXCY \blk00000001/blk000003d8 (
.CI(\blk00000001/sig0000016f ),
.DI(\blk00000001/sig000006ca ),
.S(\blk00000001/sig0000016e ),
.O(\blk00000001/sig0000016d )
);
XORCY \blk00000001/blk000003d7 (
.CI(\blk00000001/sig0000016f ),
.LI(\blk00000001/sig0000016e ),
.O(\blk00000001/sig00000580 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003d6 (
.I0(\blk00000001/sig000006cb ),
.I1(\blk00000001/sig000006b5 ),
.O(\blk00000001/sig0000016c )
);
MUXCY \blk00000001/blk000003d5 (
.CI(\blk00000001/sig0000016d ),
.DI(\blk00000001/sig000006cb ),
.S(\blk00000001/sig0000016c ),
.O(\blk00000001/sig0000016b )
);
XORCY \blk00000001/blk000003d4 (
.CI(\blk00000001/sig0000016d ),
.LI(\blk00000001/sig0000016c ),
.O(\blk00000001/sig00000581 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003d3 (
.I0(\blk00000001/sig000006cc ),
.I1(\blk00000001/sig000006b6 ),
.O(\blk00000001/sig0000016a )
);
MUXCY \blk00000001/blk000003d2 (
.CI(\blk00000001/sig0000016b ),
.DI(\blk00000001/sig000006cc ),
.S(\blk00000001/sig0000016a ),
.O(\blk00000001/sig00000169 )
);
XORCY \blk00000001/blk000003d1 (
.CI(\blk00000001/sig0000016b ),
.LI(\blk00000001/sig0000016a ),
.O(\blk00000001/sig00000582 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003d0 (
.I0(\blk00000001/sig000006cd ),
.I1(\blk00000001/sig000006b7 ),
.O(\blk00000001/sig00000168 )
);
MUXCY \blk00000001/blk000003cf (
.CI(\blk00000001/sig00000169 ),
.DI(\blk00000001/sig000006cd ),
.S(\blk00000001/sig00000168 ),
.O(\blk00000001/sig00000167 )
);
XORCY \blk00000001/blk000003ce (
.CI(\blk00000001/sig00000169 ),
.LI(\blk00000001/sig00000168 ),
.O(\blk00000001/sig00000583 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003cd (
.I0(\blk00000001/sig000006ce ),
.I1(\blk00000001/sig000006b8 ),
.O(\blk00000001/sig00000166 )
);
MUXCY \blk00000001/blk000003cc (
.CI(\blk00000001/sig00000167 ),
.DI(\blk00000001/sig000006ce ),
.S(\blk00000001/sig00000166 ),
.O(\blk00000001/sig00000165 )
);
XORCY \blk00000001/blk000003cb (
.CI(\blk00000001/sig00000167 ),
.LI(\blk00000001/sig00000166 ),
.O(\blk00000001/sig00000584 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ca (
.I0(\blk00000001/sig000006cf ),
.I1(\blk00000001/sig000006b9 ),
.O(\blk00000001/sig00000164 )
);
MUXCY \blk00000001/blk000003c9 (
.CI(\blk00000001/sig00000165 ),
.DI(\blk00000001/sig000006cf ),
.S(\blk00000001/sig00000164 ),
.O(\blk00000001/sig00000163 )
);
XORCY \blk00000001/blk000003c8 (
.CI(\blk00000001/sig00000165 ),
.LI(\blk00000001/sig00000164 ),
.O(\blk00000001/sig00000585 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003c7 (
.I0(\blk00000001/sig000006d0 ),
.I1(\blk00000001/sig000006ba ),
.O(\blk00000001/sig00000162 )
);
MUXCY \blk00000001/blk000003c6 (
.CI(\blk00000001/sig00000163 ),
.DI(\blk00000001/sig000006d0 ),
.S(\blk00000001/sig00000162 ),
.O(\blk00000001/sig00000161 )
);
XORCY \blk00000001/blk000003c5 (
.CI(\blk00000001/sig00000163 ),
.LI(\blk00000001/sig00000162 ),
.O(\blk00000001/sig00000586 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003c4 (
.I0(\blk00000001/sig000006d1 ),
.I1(\blk00000001/sig000006bb ),
.O(\blk00000001/sig00000160 )
);
MUXCY \blk00000001/blk000003c3 (
.CI(\blk00000001/sig00000161 ),
.DI(\blk00000001/sig000006d1 ),
.S(\blk00000001/sig00000160 ),
.O(\blk00000001/sig0000015f )
);
XORCY \blk00000001/blk000003c2 (
.CI(\blk00000001/sig00000161 ),
.LI(\blk00000001/sig00000160 ),
.O(\blk00000001/sig00000587 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003c1 (
.I0(\blk00000001/sig000006d2 ),
.I1(\blk00000001/sig000006bc ),
.O(\blk00000001/sig0000015e )
);
MUXCY \blk00000001/blk000003c0 (
.CI(\blk00000001/sig0000015f ),
.DI(\blk00000001/sig000006d2 ),
.S(\blk00000001/sig0000015e ),
.O(\blk00000001/sig0000015d )
);
XORCY \blk00000001/blk000003bf (
.CI(\blk00000001/sig0000015f ),
.LI(\blk00000001/sig0000015e ),
.O(\blk00000001/sig00000588 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003be (
.I0(\blk00000001/sig000006d3 ),
.I1(\blk00000001/sig000006bd ),
.O(\blk00000001/sig0000015c )
);
MUXCY \blk00000001/blk000003bd (
.CI(\blk00000001/sig0000015d ),
.DI(\blk00000001/sig000006d3 ),
.S(\blk00000001/sig0000015c ),
.O(\blk00000001/sig0000015b )
);
XORCY \blk00000001/blk000003bc (
.CI(\blk00000001/sig0000015d ),
.LI(\blk00000001/sig0000015c ),
.O(\blk00000001/sig00000589 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003bb (
.I0(\blk00000001/sig000006d4 ),
.I1(\blk00000001/sig000006be ),
.O(\blk00000001/sig0000015a )
);
MUXCY \blk00000001/blk000003ba (
.CI(\blk00000001/sig0000015b ),
.DI(\blk00000001/sig000006d4 ),
.S(\blk00000001/sig0000015a ),
.O(\blk00000001/sig00000159 )
);
XORCY \blk00000001/blk000003b9 (
.CI(\blk00000001/sig0000015b ),
.LI(\blk00000001/sig0000015a ),
.O(\blk00000001/sig0000058a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003b8 (
.I0(\blk00000001/sig000006d5 ),
.I1(\blk00000001/sig000006bf ),
.O(\blk00000001/sig00000158 )
);
MUXCY \blk00000001/blk000003b7 (
.CI(\blk00000001/sig00000159 ),
.DI(\blk00000001/sig000006d5 ),
.S(\blk00000001/sig00000158 ),
.O(\blk00000001/sig00000157 )
);
XORCY \blk00000001/blk000003b6 (
.CI(\blk00000001/sig00000159 ),
.LI(\blk00000001/sig00000158 ),
.O(\blk00000001/sig0000058b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003b5 (
.I0(\blk00000001/sig000006d6 ),
.I1(\blk00000001/sig000006c0 ),
.O(\blk00000001/sig00000156 )
);
MUXCY \blk00000001/blk000003b4 (
.CI(\blk00000001/sig00000157 ),
.DI(\blk00000001/sig000006d6 ),
.S(\blk00000001/sig00000156 ),
.O(\blk00000001/sig00000155 )
);
XORCY \blk00000001/blk000003b3 (
.CI(\blk00000001/sig00000157 ),
.LI(\blk00000001/sig00000156 ),
.O(\blk00000001/sig0000058c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003b2 (
.I0(\blk00000001/sig000006d7 ),
.I1(\blk00000001/sig000006c1 ),
.O(\blk00000001/sig00000154 )
);
MUXCY \blk00000001/blk000003b1 (
.CI(\blk00000001/sig00000155 ),
.DI(\blk00000001/sig000006d7 ),
.S(\blk00000001/sig00000154 ),
.O(\blk00000001/sig00000153 )
);
XORCY \blk00000001/blk000003b0 (
.CI(\blk00000001/sig00000155 ),
.LI(\blk00000001/sig00000154 ),
.O(\blk00000001/sig0000058d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003af (
.I0(\blk00000001/sig000006d8 ),
.I1(\blk00000001/sig000006c2 ),
.O(\blk00000001/sig00000152 )
);
MUXCY \blk00000001/blk000003ae (
.CI(\blk00000001/sig00000153 ),
.DI(\blk00000001/sig000006d8 ),
.S(\blk00000001/sig00000152 ),
.O(\blk00000001/sig00000151 )
);
XORCY \blk00000001/blk000003ad (
.CI(\blk00000001/sig00000153 ),
.LI(\blk00000001/sig00000152 ),
.O(\blk00000001/sig0000058e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ac (
.I0(\blk00000001/sig000006d9 ),
.I1(\blk00000001/sig000006c3 ),
.O(\blk00000001/sig00000150 )
);
MUXCY \blk00000001/blk000003ab (
.CI(\blk00000001/sig00000151 ),
.DI(\blk00000001/sig000006d9 ),
.S(\blk00000001/sig00000150 ),
.O(\blk00000001/sig0000014f )
);
XORCY \blk00000001/blk000003aa (
.CI(\blk00000001/sig00000151 ),
.LI(\blk00000001/sig00000150 ),
.O(\blk00000001/sig0000058f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003a9 (
.I0(\blk00000001/sig000006d9 ),
.I1(\blk00000001/sig000006c4 ),
.O(\blk00000001/sig0000014e )
);
MUXCY \blk00000001/blk000003a8 (
.CI(\blk00000001/sig0000014f ),
.DI(\blk00000001/sig000006d9 ),
.S(\blk00000001/sig0000014e ),
.O(\blk00000001/sig0000014d )
);
XORCY \blk00000001/blk000003a7 (
.CI(\blk00000001/sig0000014f ),
.LI(\blk00000001/sig0000014e ),
.O(\blk00000001/sig00000590 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003a6 (
.I0(\blk00000001/sig000006d9 ),
.I1(\blk00000001/sig000006c5 ),
.O(\blk00000001/sig0000014c )
);
XORCY \blk00000001/blk000003a5 (
.CI(\blk00000001/sig0000014d ),
.LI(\blk00000001/sig0000014c ),
.O(\blk00000001/sig00000591 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003a4 (
.I0(\blk00000001/sig0000066d ),
.I1(\blk00000001/sig00000654 ),
.O(\blk00000001/sig0000014b )
);
MUXCY \blk00000001/blk000003a3 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig0000066d ),
.S(\blk00000001/sig0000014b ),
.O(\blk00000001/sig0000014a )
);
XORCY \blk00000001/blk000003a2 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig0000014b ),
.O(\blk00000001/sig00000563 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003a1 (
.I0(\blk00000001/sig0000066e ),
.I1(\blk00000001/sig00000655 ),
.O(\blk00000001/sig00000149 )
);
MUXCY \blk00000001/blk000003a0 (
.CI(\blk00000001/sig0000014a ),
.DI(\blk00000001/sig0000066e ),
.S(\blk00000001/sig00000149 ),
.O(\blk00000001/sig00000148 )
);
XORCY \blk00000001/blk0000039f (
.CI(\blk00000001/sig0000014a ),
.LI(\blk00000001/sig00000149 ),
.O(\blk00000001/sig00000564 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000039e (
.I0(\blk00000001/sig0000066f ),
.I1(\blk00000001/sig00000656 ),
.O(\blk00000001/sig00000147 )
);
MUXCY \blk00000001/blk0000039d (
.CI(\blk00000001/sig00000148 ),
.DI(\blk00000001/sig0000066f ),
.S(\blk00000001/sig00000147 ),
.O(\blk00000001/sig00000146 )
);
XORCY \blk00000001/blk0000039c (
.CI(\blk00000001/sig00000148 ),
.LI(\blk00000001/sig00000147 ),
.O(\blk00000001/sig00000565 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000039b (
.I0(\blk00000001/sig00000670 ),
.I1(\blk00000001/sig00000657 ),
.O(\blk00000001/sig00000145 )
);
MUXCY \blk00000001/blk0000039a (
.CI(\blk00000001/sig00000146 ),
.DI(\blk00000001/sig00000670 ),
.S(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000144 )
);
XORCY \blk00000001/blk00000399 (
.CI(\blk00000001/sig00000146 ),
.LI(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000566 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000398 (
.I0(\blk00000001/sig00000671 ),
.I1(\blk00000001/sig00000658 ),
.O(\blk00000001/sig00000143 )
);
MUXCY \blk00000001/blk00000397 (
.CI(\blk00000001/sig00000144 ),
.DI(\blk00000001/sig00000671 ),
.S(\blk00000001/sig00000143 ),
.O(\blk00000001/sig00000142 )
);
XORCY \blk00000001/blk00000396 (
.CI(\blk00000001/sig00000144 ),
.LI(\blk00000001/sig00000143 ),
.O(\blk00000001/sig00000567 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000395 (
.I0(\blk00000001/sig00000672 ),
.I1(\blk00000001/sig00000659 ),
.O(\blk00000001/sig00000141 )
);
MUXCY \blk00000001/blk00000394 (
.CI(\blk00000001/sig00000142 ),
.DI(\blk00000001/sig00000672 ),
.S(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000140 )
);
XORCY \blk00000001/blk00000393 (
.CI(\blk00000001/sig00000142 ),
.LI(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000568 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000392 (
.I0(\blk00000001/sig00000673 ),
.I1(\blk00000001/sig0000065a ),
.O(\blk00000001/sig0000013f )
);
MUXCY \blk00000001/blk00000391 (
.CI(\blk00000001/sig00000140 ),
.DI(\blk00000001/sig00000673 ),
.S(\blk00000001/sig0000013f ),
.O(\blk00000001/sig0000013e )
);
XORCY \blk00000001/blk00000390 (
.CI(\blk00000001/sig00000140 ),
.LI(\blk00000001/sig0000013f ),
.O(\blk00000001/sig00000569 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000038f (
.I0(\blk00000001/sig00000674 ),
.I1(\blk00000001/sig0000065b ),
.O(\blk00000001/sig0000013d )
);
MUXCY \blk00000001/blk0000038e (
.CI(\blk00000001/sig0000013e ),
.DI(\blk00000001/sig00000674 ),
.S(\blk00000001/sig0000013d ),
.O(\blk00000001/sig0000013c )
);
XORCY \blk00000001/blk0000038d (
.CI(\blk00000001/sig0000013e ),
.LI(\blk00000001/sig0000013d ),
.O(\blk00000001/sig0000056a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000038c (
.I0(\blk00000001/sig00000675 ),
.I1(\blk00000001/sig0000065c ),
.O(\blk00000001/sig0000013b )
);
MUXCY \blk00000001/blk0000038b (
.CI(\blk00000001/sig0000013c ),
.DI(\blk00000001/sig00000675 ),
.S(\blk00000001/sig0000013b ),
.O(\blk00000001/sig0000013a )
);
XORCY \blk00000001/blk0000038a (
.CI(\blk00000001/sig0000013c ),
.LI(\blk00000001/sig0000013b ),
.O(\blk00000001/sig0000056b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000389 (
.I0(\blk00000001/sig00000676 ),
.I1(\blk00000001/sig0000065d ),
.O(\blk00000001/sig00000139 )
);
MUXCY \blk00000001/blk00000388 (
.CI(\blk00000001/sig0000013a ),
.DI(\blk00000001/sig00000676 ),
.S(\blk00000001/sig00000139 ),
.O(\blk00000001/sig00000138 )
);
XORCY \blk00000001/blk00000387 (
.CI(\blk00000001/sig0000013a ),
.LI(\blk00000001/sig00000139 ),
.O(\blk00000001/sig0000056c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000386 (
.I0(\blk00000001/sig00000677 ),
.I1(\blk00000001/sig0000065e ),
.O(\blk00000001/sig00000137 )
);
MUXCY \blk00000001/blk00000385 (
.CI(\blk00000001/sig00000138 ),
.DI(\blk00000001/sig00000677 ),
.S(\blk00000001/sig00000137 ),
.O(\blk00000001/sig00000136 )
);
XORCY \blk00000001/blk00000384 (
.CI(\blk00000001/sig00000138 ),
.LI(\blk00000001/sig00000137 ),
.O(\blk00000001/sig0000056d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000383 (
.I0(\blk00000001/sig00000678 ),
.I1(\blk00000001/sig0000065f ),
.O(\blk00000001/sig00000135 )
);
MUXCY \blk00000001/blk00000382 (
.CI(\blk00000001/sig00000136 ),
.DI(\blk00000001/sig00000678 ),
.S(\blk00000001/sig00000135 ),
.O(\blk00000001/sig00000134 )
);
XORCY \blk00000001/blk00000381 (
.CI(\blk00000001/sig00000136 ),
.LI(\blk00000001/sig00000135 ),
.O(\blk00000001/sig0000056e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000380 (
.I0(\blk00000001/sig00000679 ),
.I1(\blk00000001/sig00000660 ),
.O(\blk00000001/sig00000133 )
);
MUXCY \blk00000001/blk0000037f (
.CI(\blk00000001/sig00000134 ),
.DI(\blk00000001/sig00000679 ),
.S(\blk00000001/sig00000133 ),
.O(\blk00000001/sig00000132 )
);
XORCY \blk00000001/blk0000037e (
.CI(\blk00000001/sig00000134 ),
.LI(\blk00000001/sig00000133 ),
.O(\blk00000001/sig0000056f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000037d (
.I0(\blk00000001/sig0000067a ),
.I1(\blk00000001/sig00000661 ),
.O(\blk00000001/sig00000131 )
);
MUXCY \blk00000001/blk0000037c (
.CI(\blk00000001/sig00000132 ),
.DI(\blk00000001/sig0000067a ),
.S(\blk00000001/sig00000131 ),
.O(\blk00000001/sig00000130 )
);
XORCY \blk00000001/blk0000037b (
.CI(\blk00000001/sig00000132 ),
.LI(\blk00000001/sig00000131 ),
.O(\blk00000001/sig00000570 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000037a (
.I0(\blk00000001/sig0000067b ),
.I1(\blk00000001/sig00000662 ),
.O(\blk00000001/sig0000012f )
);
MUXCY \blk00000001/blk00000379 (
.CI(\blk00000001/sig00000130 ),
.DI(\blk00000001/sig0000067b ),
.S(\blk00000001/sig0000012f ),
.O(\blk00000001/sig0000012e )
);
XORCY \blk00000001/blk00000378 (
.CI(\blk00000001/sig00000130 ),
.LI(\blk00000001/sig0000012f ),
.O(\blk00000001/sig00000571 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000377 (
.I0(\blk00000001/sig0000067c ),
.I1(\blk00000001/sig00000663 ),
.O(\blk00000001/sig0000012d )
);
MUXCY \blk00000001/blk00000376 (
.CI(\blk00000001/sig0000012e ),
.DI(\blk00000001/sig0000067c ),
.S(\blk00000001/sig0000012d ),
.O(\blk00000001/sig0000012c )
);
XORCY \blk00000001/blk00000375 (
.CI(\blk00000001/sig0000012e ),
.LI(\blk00000001/sig0000012d ),
.O(\blk00000001/sig00000572 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000374 (
.I0(\blk00000001/sig0000067d ),
.I1(\blk00000001/sig00000664 ),
.O(\blk00000001/sig0000012b )
);
MUXCY \blk00000001/blk00000373 (
.CI(\blk00000001/sig0000012c ),
.DI(\blk00000001/sig0000067d ),
.S(\blk00000001/sig0000012b ),
.O(\blk00000001/sig0000012a )
);
XORCY \blk00000001/blk00000372 (
.CI(\blk00000001/sig0000012c ),
.LI(\blk00000001/sig0000012b ),
.O(\blk00000001/sig00000573 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000371 (
.I0(\blk00000001/sig0000067e ),
.I1(\blk00000001/sig00000665 ),
.O(\blk00000001/sig00000129 )
);
MUXCY \blk00000001/blk00000370 (
.CI(\blk00000001/sig0000012a ),
.DI(\blk00000001/sig0000067e ),
.S(\blk00000001/sig00000129 ),
.O(\blk00000001/sig00000128 )
);
XORCY \blk00000001/blk0000036f (
.CI(\blk00000001/sig0000012a ),
.LI(\blk00000001/sig00000129 ),
.O(\blk00000001/sig00000574 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000036e (
.I0(\blk00000001/sig0000067f ),
.I1(\blk00000001/sig00000666 ),
.O(\blk00000001/sig00000127 )
);
MUXCY \blk00000001/blk0000036d (
.CI(\blk00000001/sig00000128 ),
.DI(\blk00000001/sig0000067f ),
.S(\blk00000001/sig00000127 ),
.O(\blk00000001/sig00000126 )
);
XORCY \blk00000001/blk0000036c (
.CI(\blk00000001/sig00000128 ),
.LI(\blk00000001/sig00000127 ),
.O(\blk00000001/sig00000575 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000036b (
.I0(\blk00000001/sig00000667 ),
.I1(\blk00000001/sig00000680 ),
.O(\blk00000001/sig00000125 )
);
MUXCY \blk00000001/blk0000036a (
.CI(\blk00000001/sig00000126 ),
.DI(\blk00000001/sig00000680 ),
.S(\blk00000001/sig00000125 ),
.O(\blk00000001/sig00000124 )
);
XORCY \blk00000001/blk00000369 (
.CI(\blk00000001/sig00000126 ),
.LI(\blk00000001/sig00000125 ),
.O(\blk00000001/sig00000576 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000368 (
.I0(\blk00000001/sig00000668 ),
.I1(\blk00000001/sig00000680 ),
.O(\blk00000001/sig00000123 )
);
MUXCY \blk00000001/blk00000367 (
.CI(\blk00000001/sig00000124 ),
.DI(\blk00000001/sig00000680 ),
.S(\blk00000001/sig00000123 ),
.O(\blk00000001/sig00000122 )
);
XORCY \blk00000001/blk00000366 (
.CI(\blk00000001/sig00000124 ),
.LI(\blk00000001/sig00000123 ),
.O(\blk00000001/sig00000577 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000365 (
.I0(\blk00000001/sig00000669 ),
.I1(\blk00000001/sig00000680 ),
.O(\blk00000001/sig00000121 )
);
MUXCY \blk00000001/blk00000364 (
.CI(\blk00000001/sig00000122 ),
.DI(\blk00000001/sig00000680 ),
.S(\blk00000001/sig00000121 ),
.O(\blk00000001/sig00000120 )
);
XORCY \blk00000001/blk00000363 (
.CI(\blk00000001/sig00000122 ),
.LI(\blk00000001/sig00000121 ),
.O(\blk00000001/sig00000578 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000362 (
.I0(\blk00000001/sig00000680 ),
.I1(\blk00000001/sig0000066a ),
.O(\blk00000001/sig0000011f )
);
MUXCY \blk00000001/blk00000361 (
.CI(\blk00000001/sig00000120 ),
.DI(\blk00000001/sig00000680 ),
.S(\blk00000001/sig0000011f ),
.O(\blk00000001/sig0000011e )
);
XORCY \blk00000001/blk00000360 (
.CI(\blk00000001/sig00000120 ),
.LI(\blk00000001/sig0000011f ),
.O(\blk00000001/sig00000579 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000035f (
.I0(\blk00000001/sig00000680 ),
.I1(\blk00000001/sig0000066b ),
.O(\blk00000001/sig0000011d )
);
MUXCY \blk00000001/blk0000035e (
.CI(\blk00000001/sig0000011e ),
.DI(\blk00000001/sig00000680 ),
.S(\blk00000001/sig0000011d ),
.O(\blk00000001/sig0000011c )
);
XORCY \blk00000001/blk0000035d (
.CI(\blk00000001/sig0000011e ),
.LI(\blk00000001/sig0000011d ),
.O(\blk00000001/sig0000057a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000035c (
.I0(\blk00000001/sig00000680 ),
.I1(\blk00000001/sig0000066b ),
.O(\blk00000001/sig0000011b )
);
XORCY \blk00000001/blk0000035b (
.CI(\blk00000001/sig0000011c ),
.LI(\blk00000001/sig0000011b ),
.O(\blk00000001/sig0000057b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000035a (
.I0(\blk00000001/sig0000062a ),
.I1(\blk00000001/sig0000060a ),
.O(\blk00000001/sig0000011a )
);
MUXCY \blk00000001/blk00000359 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig0000062a ),
.S(\blk00000001/sig0000011a ),
.O(\blk00000001/sig00000119 )
);
XORCY \blk00000001/blk00000358 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig0000011a ),
.O(\blk00000001/sig0000038a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000357 (
.I0(\blk00000001/sig0000062b ),
.I1(\blk00000001/sig0000060b ),
.O(\blk00000001/sig00000118 )
);
MUXCY \blk00000001/blk00000356 (
.CI(\blk00000001/sig00000119 ),
.DI(\blk00000001/sig0000062b ),
.S(\blk00000001/sig00000118 ),
.O(\blk00000001/sig00000117 )
);
XORCY \blk00000001/blk00000355 (
.CI(\blk00000001/sig00000119 ),
.LI(\blk00000001/sig00000118 ),
.O(\blk00000001/sig0000038b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000354 (
.I0(\blk00000001/sig0000062c ),
.I1(\blk00000001/sig0000060c ),
.O(\blk00000001/sig00000116 )
);
MUXCY \blk00000001/blk00000353 (
.CI(\blk00000001/sig00000117 ),
.DI(\blk00000001/sig0000062c ),
.S(\blk00000001/sig00000116 ),
.O(\blk00000001/sig00000115 )
);
XORCY \blk00000001/blk00000352 (
.CI(\blk00000001/sig00000117 ),
.LI(\blk00000001/sig00000116 ),
.O(\blk00000001/sig0000038c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000351 (
.I0(\blk00000001/sig0000062d ),
.I1(\blk00000001/sig0000060d ),
.O(\blk00000001/sig00000114 )
);
MUXCY \blk00000001/blk00000350 (
.CI(\blk00000001/sig00000115 ),
.DI(\blk00000001/sig0000062d ),
.S(\blk00000001/sig00000114 ),
.O(\blk00000001/sig00000113 )
);
XORCY \blk00000001/blk0000034f (
.CI(\blk00000001/sig00000115 ),
.LI(\blk00000001/sig00000114 ),
.O(\blk00000001/sig0000038d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000034e (
.I0(\blk00000001/sig0000062e ),
.I1(\blk00000001/sig0000060e ),
.O(\blk00000001/sig00000112 )
);
MUXCY \blk00000001/blk0000034d (
.CI(\blk00000001/sig00000113 ),
.DI(\blk00000001/sig0000062e ),
.S(\blk00000001/sig00000112 ),
.O(\blk00000001/sig00000111 )
);
XORCY \blk00000001/blk0000034c (
.CI(\blk00000001/sig00000113 ),
.LI(\blk00000001/sig00000112 ),
.O(\blk00000001/sig0000038e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000034b (
.I0(\blk00000001/sig0000062f ),
.I1(\blk00000001/sig0000060f ),
.O(\blk00000001/sig00000110 )
);
MUXCY \blk00000001/blk0000034a (
.CI(\blk00000001/sig00000111 ),
.DI(\blk00000001/sig0000062f ),
.S(\blk00000001/sig00000110 ),
.O(\blk00000001/sig0000010f )
);
XORCY \blk00000001/blk00000349 (
.CI(\blk00000001/sig00000111 ),
.LI(\blk00000001/sig00000110 ),
.O(\blk00000001/sig0000038f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000348 (
.I0(\blk00000001/sig00000630 ),
.I1(\blk00000001/sig00000610 ),
.O(\blk00000001/sig0000010e )
);
MUXCY \blk00000001/blk00000347 (
.CI(\blk00000001/sig0000010f ),
.DI(\blk00000001/sig00000630 ),
.S(\blk00000001/sig0000010e ),
.O(\blk00000001/sig0000010d )
);
XORCY \blk00000001/blk00000346 (
.CI(\blk00000001/sig0000010f ),
.LI(\blk00000001/sig0000010e ),
.O(\blk00000001/sig00000390 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000345 (
.I0(\blk00000001/sig00000631 ),
.I1(\blk00000001/sig00000611 ),
.O(\blk00000001/sig0000010c )
);
MUXCY \blk00000001/blk00000344 (
.CI(\blk00000001/sig0000010d ),
.DI(\blk00000001/sig00000631 ),
.S(\blk00000001/sig0000010c ),
.O(\blk00000001/sig0000010b )
);
XORCY \blk00000001/blk00000343 (
.CI(\blk00000001/sig0000010d ),
.LI(\blk00000001/sig0000010c ),
.O(\blk00000001/sig00000391 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000342 (
.I0(\blk00000001/sig00000632 ),
.I1(\blk00000001/sig00000612 ),
.O(\blk00000001/sig0000010a )
);
MUXCY \blk00000001/blk00000341 (
.CI(\blk00000001/sig0000010b ),
.DI(\blk00000001/sig00000632 ),
.S(\blk00000001/sig0000010a ),
.O(\blk00000001/sig00000109 )
);
XORCY \blk00000001/blk00000340 (
.CI(\blk00000001/sig0000010b ),
.LI(\blk00000001/sig0000010a ),
.O(\blk00000001/sig00000392 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000033f (
.I0(\blk00000001/sig00000633 ),
.I1(\blk00000001/sig00000613 ),
.O(\blk00000001/sig00000108 )
);
MUXCY \blk00000001/blk0000033e (
.CI(\blk00000001/sig00000109 ),
.DI(\blk00000001/sig00000633 ),
.S(\blk00000001/sig00000108 ),
.O(\blk00000001/sig00000107 )
);
XORCY \blk00000001/blk0000033d (
.CI(\blk00000001/sig00000109 ),
.LI(\blk00000001/sig00000108 ),
.O(\blk00000001/sig00000393 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000033c (
.I0(\blk00000001/sig00000634 ),
.I1(\blk00000001/sig00000614 ),
.O(\blk00000001/sig00000106 )
);
MUXCY \blk00000001/blk0000033b (
.CI(\blk00000001/sig00000107 ),
.DI(\blk00000001/sig00000634 ),
.S(\blk00000001/sig00000106 ),
.O(\blk00000001/sig00000105 )
);
XORCY \blk00000001/blk0000033a (
.CI(\blk00000001/sig00000107 ),
.LI(\blk00000001/sig00000106 ),
.O(\blk00000001/sig00000394 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000339 (
.I0(\blk00000001/sig00000635 ),
.I1(\blk00000001/sig00000615 ),
.O(\blk00000001/sig00000104 )
);
MUXCY \blk00000001/blk00000338 (
.CI(\blk00000001/sig00000105 ),
.DI(\blk00000001/sig00000635 ),
.S(\blk00000001/sig00000104 ),
.O(\blk00000001/sig00000103 )
);
XORCY \blk00000001/blk00000337 (
.CI(\blk00000001/sig00000105 ),
.LI(\blk00000001/sig00000104 ),
.O(\blk00000001/sig00000395 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000336 (
.I0(\blk00000001/sig00000636 ),
.I1(\blk00000001/sig00000616 ),
.O(\blk00000001/sig00000102 )
);
MUXCY \blk00000001/blk00000335 (
.CI(\blk00000001/sig00000103 ),
.DI(\blk00000001/sig00000636 ),
.S(\blk00000001/sig00000102 ),
.O(\blk00000001/sig00000101 )
);
XORCY \blk00000001/blk00000334 (
.CI(\blk00000001/sig00000103 ),
.LI(\blk00000001/sig00000102 ),
.O(\blk00000001/sig00000396 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000333 (
.I0(\blk00000001/sig00000637 ),
.I1(\blk00000001/sig00000617 ),
.O(\blk00000001/sig00000100 )
);
MUXCY \blk00000001/blk00000332 (
.CI(\blk00000001/sig00000101 ),
.DI(\blk00000001/sig00000637 ),
.S(\blk00000001/sig00000100 ),
.O(\blk00000001/sig000000ff )
);
XORCY \blk00000001/blk00000331 (
.CI(\blk00000001/sig00000101 ),
.LI(\blk00000001/sig00000100 ),
.O(\blk00000001/sig00000397 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000330 (
.I0(\blk00000001/sig00000638 ),
.I1(\blk00000001/sig00000618 ),
.O(\blk00000001/sig000000fe )
);
MUXCY \blk00000001/blk0000032f (
.CI(\blk00000001/sig000000ff ),
.DI(\blk00000001/sig00000638 ),
.S(\blk00000001/sig000000fe ),
.O(\blk00000001/sig000000fd )
);
XORCY \blk00000001/blk0000032e (
.CI(\blk00000001/sig000000ff ),
.LI(\blk00000001/sig000000fe ),
.O(\blk00000001/sig00000398 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000032d (
.I0(\blk00000001/sig00000639 ),
.I1(\blk00000001/sig00000619 ),
.O(\blk00000001/sig000000fc )
);
MUXCY \blk00000001/blk0000032c (
.CI(\blk00000001/sig000000fd ),
.DI(\blk00000001/sig00000639 ),
.S(\blk00000001/sig000000fc ),
.O(\blk00000001/sig000000fb )
);
XORCY \blk00000001/blk0000032b (
.CI(\blk00000001/sig000000fd ),
.LI(\blk00000001/sig000000fc ),
.O(\blk00000001/sig00000399 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000032a (
.I0(\blk00000001/sig0000063a ),
.I1(\blk00000001/sig0000061a ),
.O(\blk00000001/sig000000fa )
);
MUXCY \blk00000001/blk00000329 (
.CI(\blk00000001/sig000000fb ),
.DI(\blk00000001/sig0000063a ),
.S(\blk00000001/sig000000fa ),
.O(\blk00000001/sig000000f9 )
);
XORCY \blk00000001/blk00000328 (
.CI(\blk00000001/sig000000fb ),
.LI(\blk00000001/sig000000fa ),
.O(\blk00000001/sig0000039a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000327 (
.I0(\blk00000001/sig0000063b ),
.I1(\blk00000001/sig0000061b ),
.O(\blk00000001/sig000000f8 )
);
MUXCY \blk00000001/blk00000326 (
.CI(\blk00000001/sig000000f9 ),
.DI(\blk00000001/sig0000063b ),
.S(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000000f7 )
);
XORCY \blk00000001/blk00000325 (
.CI(\blk00000001/sig000000f9 ),
.LI(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig0000039b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000324 (
.I0(\blk00000001/sig0000063c ),
.I1(\blk00000001/sig0000061c ),
.O(\blk00000001/sig000000f6 )
);
MUXCY \blk00000001/blk00000323 (
.CI(\blk00000001/sig000000f7 ),
.DI(\blk00000001/sig0000063c ),
.S(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig000000f5 )
);
XORCY \blk00000001/blk00000322 (
.CI(\blk00000001/sig000000f7 ),
.LI(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig0000039c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000321 (
.I0(\blk00000001/sig0000063d ),
.I1(\blk00000001/sig0000061d ),
.O(\blk00000001/sig000000f4 )
);
MUXCY \blk00000001/blk00000320 (
.CI(\blk00000001/sig000000f5 ),
.DI(\blk00000001/sig0000063d ),
.S(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig000000f3 )
);
XORCY \blk00000001/blk0000031f (
.CI(\blk00000001/sig000000f5 ),
.LI(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig0000039d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000031e (
.I0(\blk00000001/sig0000061e ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000f2 )
);
MUXCY \blk00000001/blk0000031d (
.CI(\blk00000001/sig000000f3 ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig000000f1 )
);
XORCY \blk00000001/blk0000031c (
.CI(\blk00000001/sig000000f3 ),
.LI(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig0000039e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000031b (
.I0(\blk00000001/sig0000061f ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000f0 )
);
MUXCY \blk00000001/blk0000031a (
.CI(\blk00000001/sig000000f1 ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig000000ef )
);
XORCY \blk00000001/blk00000319 (
.CI(\blk00000001/sig000000f1 ),
.LI(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig0000039f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000318 (
.I0(\blk00000001/sig00000620 ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000ee )
);
MUXCY \blk00000001/blk00000317 (
.CI(\blk00000001/sig000000ef ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000ee ),
.O(\blk00000001/sig000000ed )
);
XORCY \blk00000001/blk00000316 (
.CI(\blk00000001/sig000000ef ),
.LI(\blk00000001/sig000000ee ),
.O(\blk00000001/sig000003a0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000315 (
.I0(\blk00000001/sig00000621 ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000ec )
);
MUXCY \blk00000001/blk00000314 (
.CI(\blk00000001/sig000000ed ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000ec ),
.O(\blk00000001/sig000000eb )
);
XORCY \blk00000001/blk00000313 (
.CI(\blk00000001/sig000000ed ),
.LI(\blk00000001/sig000000ec ),
.O(\blk00000001/sig000003a1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000312 (
.I0(\blk00000001/sig00000622 ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000ea )
);
MUXCY \blk00000001/blk00000311 (
.CI(\blk00000001/sig000000eb ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000ea ),
.O(\blk00000001/sig000000e9 )
);
XORCY \blk00000001/blk00000310 (
.CI(\blk00000001/sig000000eb ),
.LI(\blk00000001/sig000000ea ),
.O(\blk00000001/sig000003a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000030f (
.I0(\blk00000001/sig00000623 ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000e8 )
);
MUXCY \blk00000001/blk0000030e (
.CI(\blk00000001/sig000000e9 ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000e8 ),
.O(\blk00000001/sig000000e7 )
);
XORCY \blk00000001/blk0000030d (
.CI(\blk00000001/sig000000e9 ),
.LI(\blk00000001/sig000000e8 ),
.O(\blk00000001/sig000003a3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000030c (
.I0(\blk00000001/sig00000624 ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000e6 )
);
MUXCY \blk00000001/blk0000030b (
.CI(\blk00000001/sig000000e7 ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000e6 ),
.O(\blk00000001/sig000000e5 )
);
XORCY \blk00000001/blk0000030a (
.CI(\blk00000001/sig000000e7 ),
.LI(\blk00000001/sig000000e6 ),
.O(\blk00000001/sig000003a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000309 (
.I0(\blk00000001/sig00000625 ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000e4 )
);
MUXCY \blk00000001/blk00000308 (
.CI(\blk00000001/sig000000e5 ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000e4 ),
.O(\blk00000001/sig000000e3 )
);
XORCY \blk00000001/blk00000307 (
.CI(\blk00000001/sig000000e5 ),
.LI(\blk00000001/sig000000e4 ),
.O(\blk00000001/sig000003a5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000306 (
.I0(\blk00000001/sig00000626 ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig000000e2 )
);
MUXCY \blk00000001/blk00000305 (
.CI(\blk00000001/sig000000e3 ),
.DI(\blk00000001/sig0000063e ),
.S(\blk00000001/sig000000e2 ),
.O(\blk00000001/sig000000e1 )
);
XORCY \blk00000001/blk00000304 (
.CI(\blk00000001/sig000000e3 ),
.LI(\blk00000001/sig000000e2 ),
.O(\blk00000001/sig000003a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000303 (
.I0(\blk00000001/sig0000063e ),
.I1(\blk00000001/sig00000626 ),
.O(\blk00000001/sig000000e0 )
);
XORCY \blk00000001/blk00000302 (
.CI(\blk00000001/sig000000e1 ),
.LI(\blk00000001/sig000000e0 ),
.O(\blk00000001/sig000003a7 )
);
MUXCY \blk00000001/blk00000301 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig00000758 ),
.S(\blk00000001/sig000000df ),
.O(\blk00000001/sig000000de )
);
XORCY \blk00000001/blk00000300 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig000000df ),
.O(\blk00000001/sig000003c1 )
);
MUXCY \blk00000001/blk000002ff (
.CI(\blk00000001/sig000000de ),
.DI(\blk00000001/sig00000759 ),
.S(\blk00000001/sig000000dd ),
.O(\blk00000001/sig000000dc )
);
XORCY \blk00000001/blk000002fe (
.CI(\blk00000001/sig000000de ),
.LI(\blk00000001/sig000000dd ),
.O(\blk00000001/sig000003c2 )
);
MUXCY \blk00000001/blk000002fd (
.CI(\blk00000001/sig000000dc ),
.DI(\blk00000001/sig0000075a ),
.S(\blk00000001/sig000000db ),
.O(\blk00000001/sig000000da )
);
XORCY \blk00000001/blk000002fc (
.CI(\blk00000001/sig000000dc ),
.LI(\blk00000001/sig000000db ),
.O(\blk00000001/sig000003c3 )
);
MUXCY \blk00000001/blk000002fb (
.CI(\blk00000001/sig000000da ),
.DI(\blk00000001/sig0000075b ),
.S(\blk00000001/sig000000d9 ),
.O(\blk00000001/sig000000d8 )
);
XORCY \blk00000001/blk000002fa (
.CI(\blk00000001/sig000000da ),
.LI(\blk00000001/sig000000d9 ),
.O(\blk00000001/sig000003c4 )
);
MUXCY \blk00000001/blk000002f9 (
.CI(\blk00000001/sig000000d8 ),
.DI(\blk00000001/sig0000075c ),
.S(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig000000d6 )
);
XORCY \blk00000001/blk000002f8 (
.CI(\blk00000001/sig000000d8 ),
.LI(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig000003c5 )
);
MUXCY \blk00000001/blk000002f7 (
.CI(\blk00000001/sig000000d6 ),
.DI(\blk00000001/sig0000075d ),
.S(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig000000d4 )
);
XORCY \blk00000001/blk000002f6 (
.CI(\blk00000001/sig000000d6 ),
.LI(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig000003c6 )
);
MUXCY \blk00000001/blk000002f5 (
.CI(\blk00000001/sig000000d4 ),
.DI(\blk00000001/sig0000075e ),
.S(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig000000d2 )
);
XORCY \blk00000001/blk000002f4 (
.CI(\blk00000001/sig000000d4 ),
.LI(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig000003c7 )
);
MUXCY \blk00000001/blk000002f3 (
.CI(\blk00000001/sig000000d2 ),
.DI(\blk00000001/sig0000075f ),
.S(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig000000d0 )
);
XORCY \blk00000001/blk000002f2 (
.CI(\blk00000001/sig000000d2 ),
.LI(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig000003c8 )
);
MUXCY \blk00000001/blk000002f1 (
.CI(\blk00000001/sig000000d0 ),
.DI(\blk00000001/sig00000760 ),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000ce )
);
XORCY \blk00000001/blk000002f0 (
.CI(\blk00000001/sig000000d0 ),
.LI(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000003c9 )
);
MUXCY \blk00000001/blk000002ef (
.CI(\blk00000001/sig000000ce ),
.DI(\blk00000001/sig00000761 ),
.S(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000cc )
);
XORCY \blk00000001/blk000002ee (
.CI(\blk00000001/sig000000ce ),
.LI(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000003ca )
);
MUXCY \blk00000001/blk000002ed (
.CI(\blk00000001/sig000000cc ),
.DI(\blk00000001/sig00000762 ),
.S(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000ca )
);
XORCY \blk00000001/blk000002ec (
.CI(\blk00000001/sig000000cc ),
.LI(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000003cb )
);
MUXCY \blk00000001/blk000002eb (
.CI(\blk00000001/sig000000ca ),
.DI(\blk00000001/sig00000763 ),
.S(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000000c8 )
);
XORCY \blk00000001/blk000002ea (
.CI(\blk00000001/sig000000ca ),
.LI(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000003cc )
);
MUXCY \blk00000001/blk000002e9 (
.CI(\blk00000001/sig000000c8 ),
.DI(\blk00000001/sig00000764 ),
.S(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000000c6 )
);
XORCY \blk00000001/blk000002e8 (
.CI(\blk00000001/sig000000c8 ),
.LI(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000003cd )
);
MUXCY \blk00000001/blk000002e7 (
.CI(\blk00000001/sig000000c6 ),
.DI(\blk00000001/sig00000765 ),
.S(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000000c4 )
);
XORCY \blk00000001/blk000002e6 (
.CI(\blk00000001/sig000000c6 ),
.LI(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000003ce )
);
MUXCY \blk00000001/blk000002e5 (
.CI(\blk00000001/sig000000c4 ),
.DI(\blk00000001/sig00000766 ),
.S(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000000c2 )
);
XORCY \blk00000001/blk000002e4 (
.CI(\blk00000001/sig000000c4 ),
.LI(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000003cf )
);
MUXCY \blk00000001/blk000002e3 (
.CI(\blk00000001/sig000000c2 ),
.DI(\blk00000001/sig00000767 ),
.S(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000000c0 )
);
XORCY \blk00000001/blk000002e2 (
.CI(\blk00000001/sig000000c2 ),
.LI(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000003d0 )
);
MUXCY \blk00000001/blk000002e1 (
.CI(\blk00000001/sig000000c0 ),
.DI(\blk00000001/sig00000768 ),
.S(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000000be )
);
XORCY \blk00000001/blk000002e0 (
.CI(\blk00000001/sig000000c0 ),
.LI(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000003d1 )
);
MUXCY \blk00000001/blk000002df (
.CI(\blk00000001/sig000000be ),
.DI(\blk00000001/sig00000769 ),
.S(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000000bc )
);
XORCY \blk00000001/blk000002de (
.CI(\blk00000001/sig000000be ),
.LI(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000003d2 )
);
MUXCY \blk00000001/blk000002dd (
.CI(\blk00000001/sig000000bc ),
.DI(\blk00000001/sig0000076a ),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000ba )
);
XORCY \blk00000001/blk000002dc (
.CI(\blk00000001/sig000000bc ),
.LI(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000003d3 )
);
MUXCY \blk00000001/blk000002db (
.CI(\blk00000001/sig000000ba ),
.DI(\blk00000001/sig0000076b ),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000b8 )
);
XORCY \blk00000001/blk000002da (
.CI(\blk00000001/sig000000ba ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000003d4 )
);
MUXCY \blk00000001/blk000002d9 (
.CI(\blk00000001/sig000000b8 ),
.DI(\blk00000001/sig0000076c ),
.S(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000b6 )
);
XORCY \blk00000001/blk000002d8 (
.CI(\blk00000001/sig000000b8 ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000003d5 )
);
MUXCY \blk00000001/blk000002d7 (
.CI(\blk00000001/sig000000b6 ),
.DI(\blk00000001/sig0000076d ),
.S(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000b4 )
);
XORCY \blk00000001/blk000002d6 (
.CI(\blk00000001/sig000000b6 ),
.LI(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000003d6 )
);
XORCY \blk00000001/blk000002d5 (
.CI(\blk00000001/sig000000b4 ),
.LI(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig000003d7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002d4 (
.I0(\blk00000001/sig0000069b ),
.I1(\blk00000001/sig00000681 ),
.O(\blk00000001/sig000000b2 )
);
MUXCY \blk00000001/blk000002d3 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig0000069b ),
.S(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig000000b1 )
);
XORCY \blk00000001/blk000002d2 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig000003a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002d1 (
.I0(\blk00000001/sig0000069c ),
.I1(\blk00000001/sig00000682 ),
.O(\blk00000001/sig000000b0 )
);
MUXCY \blk00000001/blk000002d0 (
.CI(\blk00000001/sig000000b1 ),
.DI(\blk00000001/sig0000069c ),
.S(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig000000af )
);
XORCY \blk00000001/blk000002cf (
.CI(\blk00000001/sig000000b1 ),
.LI(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig000003a9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002ce (
.I0(\blk00000001/sig0000069d ),
.I1(\blk00000001/sig00000683 ),
.O(\blk00000001/sig000000ae )
);
MUXCY \blk00000001/blk000002cd (
.CI(\blk00000001/sig000000af ),
.DI(\blk00000001/sig0000069d ),
.S(\blk00000001/sig000000ae ),
.O(\blk00000001/sig000000ad )
);
XORCY \blk00000001/blk000002cc (
.CI(\blk00000001/sig000000af ),
.LI(\blk00000001/sig000000ae ),
.O(\blk00000001/sig000003aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002cb (
.I0(\blk00000001/sig0000069e ),
.I1(\blk00000001/sig00000684 ),
.O(\blk00000001/sig000000ac )
);
MUXCY \blk00000001/blk000002ca (
.CI(\blk00000001/sig000000ad ),
.DI(\blk00000001/sig0000069e ),
.S(\blk00000001/sig000000ac ),
.O(\blk00000001/sig000000ab )
);
XORCY \blk00000001/blk000002c9 (
.CI(\blk00000001/sig000000ad ),
.LI(\blk00000001/sig000000ac ),
.O(\blk00000001/sig000003ab )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002c8 (
.I0(\blk00000001/sig0000069f ),
.I1(\blk00000001/sig00000685 ),
.O(\blk00000001/sig000000aa )
);
MUXCY \blk00000001/blk000002c7 (
.CI(\blk00000001/sig000000ab ),
.DI(\blk00000001/sig0000069f ),
.S(\blk00000001/sig000000aa ),
.O(\blk00000001/sig000000a9 )
);
XORCY \blk00000001/blk000002c6 (
.CI(\blk00000001/sig000000ab ),
.LI(\blk00000001/sig000000aa ),
.O(\blk00000001/sig000003ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002c5 (
.I0(\blk00000001/sig000006a0 ),
.I1(\blk00000001/sig00000686 ),
.O(\blk00000001/sig000000a8 )
);
MUXCY \blk00000001/blk000002c4 (
.CI(\blk00000001/sig000000a9 ),
.DI(\blk00000001/sig000006a0 ),
.S(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig000000a7 )
);
XORCY \blk00000001/blk000002c3 (
.CI(\blk00000001/sig000000a9 ),
.LI(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig000003ad )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002c2 (
.I0(\blk00000001/sig000006a1 ),
.I1(\blk00000001/sig00000687 ),
.O(\blk00000001/sig000000a6 )
);
MUXCY \blk00000001/blk000002c1 (
.CI(\blk00000001/sig000000a7 ),
.DI(\blk00000001/sig000006a1 ),
.S(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig000000a5 )
);
XORCY \blk00000001/blk000002c0 (
.CI(\blk00000001/sig000000a7 ),
.LI(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig000003ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002bf (
.I0(\blk00000001/sig000006a2 ),
.I1(\blk00000001/sig00000688 ),
.O(\blk00000001/sig000000a4 )
);
MUXCY \blk00000001/blk000002be (
.CI(\blk00000001/sig000000a5 ),
.DI(\blk00000001/sig000006a2 ),
.S(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig000000a3 )
);
XORCY \blk00000001/blk000002bd (
.CI(\blk00000001/sig000000a5 ),
.LI(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig000003af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002bc (
.I0(\blk00000001/sig000006a3 ),
.I1(\blk00000001/sig00000689 ),
.O(\blk00000001/sig000000a2 )
);
MUXCY \blk00000001/blk000002bb (
.CI(\blk00000001/sig000000a3 ),
.DI(\blk00000001/sig000006a3 ),
.S(\blk00000001/sig000000a2 ),
.O(\blk00000001/sig000000a1 )
);
XORCY \blk00000001/blk000002ba (
.CI(\blk00000001/sig000000a3 ),
.LI(\blk00000001/sig000000a2 ),
.O(\blk00000001/sig000003b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002b9 (
.I0(\blk00000001/sig000006a4 ),
.I1(\blk00000001/sig0000068a ),
.O(\blk00000001/sig000000a0 )
);
MUXCY \blk00000001/blk000002b8 (
.CI(\blk00000001/sig000000a1 ),
.DI(\blk00000001/sig000006a4 ),
.S(\blk00000001/sig000000a0 ),
.O(\blk00000001/sig0000009f )
);
XORCY \blk00000001/blk000002b7 (
.CI(\blk00000001/sig000000a1 ),
.LI(\blk00000001/sig000000a0 ),
.O(\blk00000001/sig000003b1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002b6 (
.I0(\blk00000001/sig000006a5 ),
.I1(\blk00000001/sig0000068b ),
.O(\blk00000001/sig0000009e )
);
MUXCY \blk00000001/blk000002b5 (
.CI(\blk00000001/sig0000009f ),
.DI(\blk00000001/sig000006a5 ),
.S(\blk00000001/sig0000009e ),
.O(\blk00000001/sig0000009d )
);
XORCY \blk00000001/blk000002b4 (
.CI(\blk00000001/sig0000009f ),
.LI(\blk00000001/sig0000009e ),
.O(\blk00000001/sig000003b2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002b3 (
.I0(\blk00000001/sig000006a6 ),
.I1(\blk00000001/sig0000068c ),
.O(\blk00000001/sig0000009c )
);
MUXCY \blk00000001/blk000002b2 (
.CI(\blk00000001/sig0000009d ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig0000009c ),
.O(\blk00000001/sig0000009b )
);
XORCY \blk00000001/blk000002b1 (
.CI(\blk00000001/sig0000009d ),
.LI(\blk00000001/sig0000009c ),
.O(\blk00000001/sig000003b3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002b0 (
.I0(\blk00000001/sig000006a7 ),
.I1(\blk00000001/sig0000068d ),
.O(\blk00000001/sig0000009a )
);
MUXCY \blk00000001/blk000002af (
.CI(\blk00000001/sig0000009b ),
.DI(\blk00000001/sig000006a7 ),
.S(\blk00000001/sig0000009a ),
.O(\blk00000001/sig00000099 )
);
XORCY \blk00000001/blk000002ae (
.CI(\blk00000001/sig0000009b ),
.LI(\blk00000001/sig0000009a ),
.O(\blk00000001/sig000003b4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002ad (
.I0(\blk00000001/sig000006a8 ),
.I1(\blk00000001/sig0000068e ),
.O(\blk00000001/sig00000098 )
);
MUXCY \blk00000001/blk000002ac (
.CI(\blk00000001/sig00000099 ),
.DI(\blk00000001/sig000006a8 ),
.S(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000097 )
);
XORCY \blk00000001/blk000002ab (
.CI(\blk00000001/sig00000099 ),
.LI(\blk00000001/sig00000098 ),
.O(\blk00000001/sig000003b5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002aa (
.I0(\blk00000001/sig000006a9 ),
.I1(\blk00000001/sig0000068f ),
.O(\blk00000001/sig00000096 )
);
MUXCY \blk00000001/blk000002a9 (
.CI(\blk00000001/sig00000097 ),
.DI(\blk00000001/sig000006a9 ),
.S(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000095 )
);
XORCY \blk00000001/blk000002a8 (
.CI(\blk00000001/sig00000097 ),
.LI(\blk00000001/sig00000096 ),
.O(\blk00000001/sig000003b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002a7 (
.I0(\blk00000001/sig000006aa ),
.I1(\blk00000001/sig00000690 ),
.O(\blk00000001/sig00000094 )
);
MUXCY \blk00000001/blk000002a6 (
.CI(\blk00000001/sig00000095 ),
.DI(\blk00000001/sig000006aa ),
.S(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000093 )
);
XORCY \blk00000001/blk000002a5 (
.CI(\blk00000001/sig00000095 ),
.LI(\blk00000001/sig00000094 ),
.O(\blk00000001/sig000003b7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002a4 (
.I0(\blk00000001/sig000006ab ),
.I1(\blk00000001/sig00000691 ),
.O(\blk00000001/sig00000092 )
);
MUXCY \blk00000001/blk000002a3 (
.CI(\blk00000001/sig00000093 ),
.DI(\blk00000001/sig000006ab ),
.S(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000091 )
);
XORCY \blk00000001/blk000002a2 (
.CI(\blk00000001/sig00000093 ),
.LI(\blk00000001/sig00000092 ),
.O(\blk00000001/sig000003b8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002a1 (
.I0(\blk00000001/sig000006ac ),
.I1(\blk00000001/sig00000692 ),
.O(\blk00000001/sig00000090 )
);
MUXCY \blk00000001/blk000002a0 (
.CI(\blk00000001/sig00000091 ),
.DI(\blk00000001/sig000006ac ),
.S(\blk00000001/sig00000090 ),
.O(\blk00000001/sig0000008f )
);
XORCY \blk00000001/blk0000029f (
.CI(\blk00000001/sig00000091 ),
.LI(\blk00000001/sig00000090 ),
.O(\blk00000001/sig000003b9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000029e (
.I0(\blk00000001/sig000006ad ),
.I1(\blk00000001/sig00000693 ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk0000029d (
.CI(\blk00000001/sig0000008f ),
.DI(\blk00000001/sig000006ad ),
.S(\blk00000001/sig0000008e ),
.O(\blk00000001/sig0000008d )
);
XORCY \blk00000001/blk0000029c (
.CI(\blk00000001/sig0000008f ),
.LI(\blk00000001/sig0000008e ),
.O(\blk00000001/sig000003ba )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000029b (
.I0(\blk00000001/sig000006ae ),
.I1(\blk00000001/sig00000694 ),
.O(\blk00000001/sig0000008c )
);
MUXCY \blk00000001/blk0000029a (
.CI(\blk00000001/sig0000008d ),
.DI(\blk00000001/sig000006ae ),
.S(\blk00000001/sig0000008c ),
.O(\blk00000001/sig0000008b )
);
XORCY \blk00000001/blk00000299 (
.CI(\blk00000001/sig0000008d ),
.LI(\blk00000001/sig0000008c ),
.O(\blk00000001/sig000003bb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000298 (
.I0(\blk00000001/sig00000695 ),
.I1(\blk00000001/sig000006af ),
.O(\blk00000001/sig0000008a )
);
MUXCY \blk00000001/blk00000297 (
.CI(\blk00000001/sig0000008b ),
.DI(\blk00000001/sig000006af ),
.S(\blk00000001/sig0000008a ),
.O(\blk00000001/sig00000089 )
);
XORCY \blk00000001/blk00000296 (
.CI(\blk00000001/sig0000008b ),
.LI(\blk00000001/sig0000008a ),
.O(\blk00000001/sig000003bc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000295 (
.I0(\blk00000001/sig000006af ),
.I1(\blk00000001/sig00000696 ),
.O(\blk00000001/sig00000088 )
);
MUXCY \blk00000001/blk00000294 (
.CI(\blk00000001/sig00000089 ),
.DI(\blk00000001/sig000006af ),
.S(\blk00000001/sig00000088 ),
.O(\blk00000001/sig00000087 )
);
XORCY \blk00000001/blk00000293 (
.CI(\blk00000001/sig00000089 ),
.LI(\blk00000001/sig00000088 ),
.O(\blk00000001/sig000003bd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000292 (
.I0(\blk00000001/sig000006af ),
.I1(\blk00000001/sig00000697 ),
.O(\blk00000001/sig00000086 )
);
MUXCY \blk00000001/blk00000291 (
.CI(\blk00000001/sig00000087 ),
.DI(\blk00000001/sig000006af ),
.S(\blk00000001/sig00000086 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk00000290 (
.CI(\blk00000001/sig00000087 ),
.LI(\blk00000001/sig00000086 ),
.O(\blk00000001/sig000003be )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000028f (
.I0(\blk00000001/sig000006af ),
.I1(\blk00000001/sig00000698 ),
.O(\blk00000001/sig00000084 )
);
MUXCY \blk00000001/blk0000028e (
.CI(\blk00000001/sig00000085 ),
.DI(\blk00000001/sig000006af ),
.S(\blk00000001/sig00000084 ),
.O(\blk00000001/sig00000083 )
);
XORCY \blk00000001/blk0000028d (
.CI(\blk00000001/sig00000085 ),
.LI(\blk00000001/sig00000084 ),
.O(\blk00000001/sig000003bf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000028c (
.I0(\blk00000001/sig000006af ),
.I1(\blk00000001/sig00000698 ),
.O(\blk00000001/sig00000082 )
);
XORCY \blk00000001/blk0000028b (
.CI(\blk00000001/sig00000083 ),
.LI(\blk00000001/sig00000082 ),
.O(\blk00000001/sig000003c0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000028a (
.I0(\blk00000001/sig000005f4 ),
.I1(\blk00000001/sig000005d5 ),
.O(\blk00000001/sig00000081 )
);
MUXCY \blk00000001/blk00000289 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig000005f4 ),
.S(\blk00000001/sig00000081 ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk00000288 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig00000081 ),
.O(\blk00000001/sig00000372 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000287 (
.I0(\blk00000001/sig000005f5 ),
.I1(\blk00000001/sig000005d6 ),
.O(\blk00000001/sig0000007f )
);
MUXCY \blk00000001/blk00000286 (
.CI(\blk00000001/sig00000080 ),
.DI(\blk00000001/sig000005f5 ),
.S(\blk00000001/sig0000007f ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk00000285 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig0000007f ),
.O(\blk00000001/sig00000373 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000284 (
.I0(\blk00000001/sig000005f6 ),
.I1(\blk00000001/sig000005d7 ),
.O(\blk00000001/sig0000007d )
);
MUXCY \blk00000001/blk00000283 (
.CI(\blk00000001/sig0000007e ),
.DI(\blk00000001/sig000005f6 ),
.S(\blk00000001/sig0000007d ),
.O(\blk00000001/sig0000007c )
);
XORCY \blk00000001/blk00000282 (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig0000007d ),
.O(\blk00000001/sig00000374 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000281 (
.I0(\blk00000001/sig000005f7 ),
.I1(\blk00000001/sig000005d8 ),
.O(\blk00000001/sig0000007b )
);
MUXCY \blk00000001/blk00000280 (
.CI(\blk00000001/sig0000007c ),
.DI(\blk00000001/sig000005f7 ),
.S(\blk00000001/sig0000007b ),
.O(\blk00000001/sig0000007a )
);
XORCY \blk00000001/blk0000027f (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig0000007b ),
.O(\blk00000001/sig00000375 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000027e (
.I0(\blk00000001/sig000005f8 ),
.I1(\blk00000001/sig000005d9 ),
.O(\blk00000001/sig00000079 )
);
MUXCY \blk00000001/blk0000027d (
.CI(\blk00000001/sig0000007a ),
.DI(\blk00000001/sig000005f8 ),
.S(\blk00000001/sig00000079 ),
.O(\blk00000001/sig00000078 )
);
XORCY \blk00000001/blk0000027c (
.CI(\blk00000001/sig0000007a ),
.LI(\blk00000001/sig00000079 ),
.O(\blk00000001/sig00000376 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000027b (
.I0(\blk00000001/sig000005f9 ),
.I1(\blk00000001/sig000005da ),
.O(\blk00000001/sig00000077 )
);
MUXCY \blk00000001/blk0000027a (
.CI(\blk00000001/sig00000078 ),
.DI(\blk00000001/sig000005f9 ),
.S(\blk00000001/sig00000077 ),
.O(\blk00000001/sig00000076 )
);
XORCY \blk00000001/blk00000279 (
.CI(\blk00000001/sig00000078 ),
.LI(\blk00000001/sig00000077 ),
.O(\blk00000001/sig00000377 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000278 (
.I0(\blk00000001/sig000005fa ),
.I1(\blk00000001/sig000005db ),
.O(\blk00000001/sig00000075 )
);
MUXCY \blk00000001/blk00000277 (
.CI(\blk00000001/sig00000076 ),
.DI(\blk00000001/sig000005fa ),
.S(\blk00000001/sig00000075 ),
.O(\blk00000001/sig00000074 )
);
XORCY \blk00000001/blk00000276 (
.CI(\blk00000001/sig00000076 ),
.LI(\blk00000001/sig00000075 ),
.O(\blk00000001/sig00000378 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000275 (
.I0(\blk00000001/sig000005fb ),
.I1(\blk00000001/sig000005dc ),
.O(\blk00000001/sig00000073 )
);
MUXCY \blk00000001/blk00000274 (
.CI(\blk00000001/sig00000074 ),
.DI(\blk00000001/sig000005fb ),
.S(\blk00000001/sig00000073 ),
.O(\blk00000001/sig00000072 )
);
XORCY \blk00000001/blk00000273 (
.CI(\blk00000001/sig00000074 ),
.LI(\blk00000001/sig00000073 ),
.O(\blk00000001/sig00000379 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000272 (
.I0(\blk00000001/sig000005fc ),
.I1(\blk00000001/sig000005dd ),
.O(\blk00000001/sig00000071 )
);
MUXCY \blk00000001/blk00000271 (
.CI(\blk00000001/sig00000072 ),
.DI(\blk00000001/sig000005fc ),
.S(\blk00000001/sig00000071 ),
.O(\blk00000001/sig00000070 )
);
XORCY \blk00000001/blk00000270 (
.CI(\blk00000001/sig00000072 ),
.LI(\blk00000001/sig00000071 ),
.O(\blk00000001/sig0000037a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000026f (
.I0(\blk00000001/sig000005fd ),
.I1(\blk00000001/sig000005de ),
.O(\blk00000001/sig0000006f )
);
MUXCY \blk00000001/blk0000026e (
.CI(\blk00000001/sig00000070 ),
.DI(\blk00000001/sig000005fd ),
.S(\blk00000001/sig0000006f ),
.O(\blk00000001/sig0000006e )
);
XORCY \blk00000001/blk0000026d (
.CI(\blk00000001/sig00000070 ),
.LI(\blk00000001/sig0000006f ),
.O(\blk00000001/sig0000037b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000026c (
.I0(\blk00000001/sig000005fe ),
.I1(\blk00000001/sig000005df ),
.O(\blk00000001/sig0000006d )
);
MUXCY \blk00000001/blk0000026b (
.CI(\blk00000001/sig0000006e ),
.DI(\blk00000001/sig000005fe ),
.S(\blk00000001/sig0000006d ),
.O(\blk00000001/sig0000006c )
);
XORCY \blk00000001/blk0000026a (
.CI(\blk00000001/sig0000006e ),
.LI(\blk00000001/sig0000006d ),
.O(\blk00000001/sig0000037c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000269 (
.I0(\blk00000001/sig000005ff ),
.I1(\blk00000001/sig000005e0 ),
.O(\blk00000001/sig0000006b )
);
MUXCY \blk00000001/blk00000268 (
.CI(\blk00000001/sig0000006c ),
.DI(\blk00000001/sig000005ff ),
.S(\blk00000001/sig0000006b ),
.O(\blk00000001/sig0000006a )
);
XORCY \blk00000001/blk00000267 (
.CI(\blk00000001/sig0000006c ),
.LI(\blk00000001/sig0000006b ),
.O(\blk00000001/sig0000037d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000266 (
.I0(\blk00000001/sig00000600 ),
.I1(\blk00000001/sig000005e1 ),
.O(\blk00000001/sig00000069 )
);
MUXCY \blk00000001/blk00000265 (
.CI(\blk00000001/sig0000006a ),
.DI(\blk00000001/sig00000600 ),
.S(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000068 )
);
XORCY \blk00000001/blk00000264 (
.CI(\blk00000001/sig0000006a ),
.LI(\blk00000001/sig00000069 ),
.O(\blk00000001/sig0000037e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000263 (
.I0(\blk00000001/sig00000601 ),
.I1(\blk00000001/sig000005e2 ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk00000262 (
.CI(\blk00000001/sig00000068 ),
.DI(\blk00000001/sig00000601 ),
.S(\blk00000001/sig00000067 ),
.O(\blk00000001/sig00000066 )
);
XORCY \blk00000001/blk00000261 (
.CI(\blk00000001/sig00000068 ),
.LI(\blk00000001/sig00000067 ),
.O(\blk00000001/sig0000037f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000260 (
.I0(\blk00000001/sig00000602 ),
.I1(\blk00000001/sig000005e3 ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk0000025f (
.CI(\blk00000001/sig00000066 ),
.DI(\blk00000001/sig00000602 ),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000064 )
);
XORCY \blk00000001/blk0000025e (
.CI(\blk00000001/sig00000066 ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000380 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000025d (
.I0(\blk00000001/sig00000603 ),
.I1(\blk00000001/sig000005e4 ),
.O(\blk00000001/sig00000063 )
);
MUXCY \blk00000001/blk0000025c (
.CI(\blk00000001/sig00000064 ),
.DI(\blk00000001/sig00000603 ),
.S(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000062 )
);
XORCY \blk00000001/blk0000025b (
.CI(\blk00000001/sig00000064 ),
.LI(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000381 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000025a (
.I0(\blk00000001/sig00000604 ),
.I1(\blk00000001/sig000005e5 ),
.O(\blk00000001/sig00000061 )
);
MUXCY \blk00000001/blk00000259 (
.CI(\blk00000001/sig00000062 ),
.DI(\blk00000001/sig00000604 ),
.S(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000060 )
);
XORCY \blk00000001/blk00000258 (
.CI(\blk00000001/sig00000062 ),
.LI(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000382 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000257 (
.I0(\blk00000001/sig00000605 ),
.I1(\blk00000001/sig000005e6 ),
.O(\blk00000001/sig0000005f )
);
MUXCY \blk00000001/blk00000256 (
.CI(\blk00000001/sig00000060 ),
.DI(\blk00000001/sig00000605 ),
.S(\blk00000001/sig0000005f ),
.O(\blk00000001/sig0000005e )
);
XORCY \blk00000001/blk00000255 (
.CI(\blk00000001/sig00000060 ),
.LI(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000383 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000254 (
.I0(\blk00000001/sig00000606 ),
.I1(\blk00000001/sig000005e7 ),
.O(\blk00000001/sig0000005d )
);
MUXCY \blk00000001/blk00000253 (
.CI(\blk00000001/sig0000005e ),
.DI(\blk00000001/sig00000606 ),
.S(\blk00000001/sig0000005d ),
.O(\blk00000001/sig0000005c )
);
XORCY \blk00000001/blk00000252 (
.CI(\blk00000001/sig0000005e ),
.LI(\blk00000001/sig0000005d ),
.O(\blk00000001/sig00000384 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000251 (
.I0(\blk00000001/sig00000607 ),
.I1(\blk00000001/sig000005e8 ),
.O(\blk00000001/sig0000005b )
);
MUXCY \blk00000001/blk00000250 (
.CI(\blk00000001/sig0000005c ),
.DI(\blk00000001/sig00000607 ),
.S(\blk00000001/sig0000005b ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk0000024f (
.CI(\blk00000001/sig0000005c ),
.LI(\blk00000001/sig0000005b ),
.O(\blk00000001/sig00000385 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000024e (
.I0(\blk00000001/sig00000608 ),
.I1(\blk00000001/sig000005e9 ),
.O(\blk00000001/sig00000059 )
);
MUXCY \blk00000001/blk0000024d (
.CI(\blk00000001/sig0000005a ),
.DI(\blk00000001/sig00000608 ),
.S(\blk00000001/sig00000059 ),
.O(\blk00000001/sig00000058 )
);
XORCY \blk00000001/blk0000024c (
.CI(\blk00000001/sig0000005a ),
.LI(\blk00000001/sig00000059 ),
.O(\blk00000001/sig00000386 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000024b (
.I0(\blk00000001/sig00000609 ),
.I1(\blk00000001/sig000005ea ),
.O(\blk00000001/sig00000057 )
);
MUXCY \blk00000001/blk0000024a (
.CI(\blk00000001/sig00000058 ),
.DI(\blk00000001/sig00000609 ),
.S(\blk00000001/sig00000057 ),
.O(\blk00000001/sig00000056 )
);
XORCY \blk00000001/blk00000249 (
.CI(\blk00000001/sig00000058 ),
.LI(\blk00000001/sig00000057 ),
.O(\blk00000001/sig00000387 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000248 (
.I0(\blk00000001/sig00000609 ),
.I1(\blk00000001/sig000005eb ),
.O(\blk00000001/sig00000055 )
);
MUXCY \blk00000001/blk00000247 (
.CI(\blk00000001/sig00000056 ),
.DI(\blk00000001/sig00000609 ),
.S(\blk00000001/sig00000055 ),
.O(\blk00000001/sig00000054 )
);
XORCY \blk00000001/blk00000246 (
.CI(\blk00000001/sig00000056 ),
.LI(\blk00000001/sig00000055 ),
.O(\blk00000001/sig00000388 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000245 (
.I0(\blk00000001/sig00000609 ),
.I1(\blk00000001/sig000005ec ),
.O(\blk00000001/sig00000053 )
);
XORCY \blk00000001/blk00000244 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig00000053 ),
.O(\blk00000001/sig00000389 )
);
MULT_AND \blk00000001/blk00000243 (
.I0(a[1]),
.I1(b[0]),
.LO(\blk00000001/sig00000561 )
);
MULT_AND \blk00000001/blk00000242 (
.I0(a[2]),
.I1(b[0]),
.LO(\blk00000001/sig00000560 )
);
MULT_AND \blk00000001/blk00000241 (
.I0(a[3]),
.I1(b[0]),
.LO(\blk00000001/sig0000055e )
);
MULT_AND \blk00000001/blk00000240 (
.I0(a[4]),
.I1(b[0]),
.LO(\blk00000001/sig0000055d )
);
MULT_AND \blk00000001/blk0000023f (
.I0(a[5]),
.I1(b[0]),
.LO(\blk00000001/sig0000055b )
);
MULT_AND \blk00000001/blk0000023e (
.I0(a[6]),
.I1(b[0]),
.LO(\blk00000001/sig0000055a )
);
MULT_AND \blk00000001/blk0000023d (
.I0(a[7]),
.I1(b[0]),
.LO(\blk00000001/sig00000558 )
);
MULT_AND \blk00000001/blk0000023c (
.I0(a[8]),
.I1(b[0]),
.LO(\blk00000001/sig00000557 )
);
MULT_AND \blk00000001/blk0000023b (
.I0(a[9]),
.I1(b[0]),
.LO(\blk00000001/sig00000555 )
);
MULT_AND \blk00000001/blk0000023a (
.I0(a[10]),
.I1(b[0]),
.LO(\blk00000001/sig00000554 )
);
MULT_AND \blk00000001/blk00000239 (
.I0(a[11]),
.I1(b[0]),
.LO(\blk00000001/sig00000552 )
);
MULT_AND \blk00000001/blk00000238 (
.I0(a[12]),
.I1(b[0]),
.LO(\blk00000001/sig00000551 )
);
MULT_AND \blk00000001/blk00000237 (
.I0(a[13]),
.I1(b[0]),
.LO(\blk00000001/sig0000054f )
);
MULT_AND \blk00000001/blk00000236 (
.I0(a[14]),
.I1(b[0]),
.LO(\blk00000001/sig0000054e )
);
MULT_AND \blk00000001/blk00000235 (
.I0(a[15]),
.I1(b[0]),
.LO(\blk00000001/sig0000054c )
);
MULT_AND \blk00000001/blk00000234 (
.I0(a[16]),
.I1(b[0]),
.LO(\blk00000001/sig0000054b )
);
MULT_AND \blk00000001/blk00000233 (
.I0(a[17]),
.I1(b[0]),
.LO(\blk00000001/sig0000054a )
);
MULT_AND \blk00000001/blk00000232 (
.I0(a[2]),
.I1(b[1]),
.LO(\blk00000001/sig00000549 )
);
MULT_AND \blk00000001/blk00000231 (
.I0(a[4]),
.I1(b[1]),
.LO(\blk00000001/sig00000548 )
);
MULT_AND \blk00000001/blk00000230 (
.I0(a[6]),
.I1(b[1]),
.LO(\blk00000001/sig00000547 )
);
MULT_AND \blk00000001/blk0000022f (
.I0(a[8]),
.I1(b[1]),
.LO(\blk00000001/sig00000546 )
);
MULT_AND \blk00000001/blk0000022e (
.I0(a[10]),
.I1(b[1]),
.LO(\blk00000001/sig00000545 )
);
MULT_AND \blk00000001/blk0000022d (
.I0(a[12]),
.I1(b[1]),
.LO(\blk00000001/sig00000544 )
);
MULT_AND \blk00000001/blk0000022c (
.I0(a[14]),
.I1(b[1]),
.LO(\blk00000001/sig00000543 )
);
MULT_AND \blk00000001/blk0000022b (
.I0(a[16]),
.I1(b[1]),
.LO(\blk00000001/sig00000542 )
);
MULT_AND \blk00000001/blk0000022a (
.I0(a[17]),
.I1(b[1]),
.LO(\blk00000001/sig00000541 )
);
MULT_AND \blk00000001/blk00000229 (
.I0(a[2]),
.I1(b[2]),
.LO(\blk00000001/sig00000540 )
);
MULT_AND \blk00000001/blk00000228 (
.I0(a[4]),
.I1(b[2]),
.LO(\blk00000001/sig0000053f )
);
MULT_AND \blk00000001/blk00000227 (
.I0(a[6]),
.I1(b[2]),
.LO(\blk00000001/sig0000053e )
);
MULT_AND \blk00000001/blk00000226 (
.I0(a[8]),
.I1(b[2]),
.LO(\blk00000001/sig0000053d )
);
MULT_AND \blk00000001/blk00000225 (
.I0(a[10]),
.I1(b[2]),
.LO(\blk00000001/sig0000053c )
);
MULT_AND \blk00000001/blk00000224 (
.I0(a[12]),
.I1(b[2]),
.LO(\blk00000001/sig0000053b )
);
MULT_AND \blk00000001/blk00000223 (
.I0(a[14]),
.I1(b[2]),
.LO(\blk00000001/sig0000053a )
);
MULT_AND \blk00000001/blk00000222 (
.I0(a[16]),
.I1(b[2]),
.LO(\blk00000001/sig00000539 )
);
MULT_AND \blk00000001/blk00000221 (
.I0(a[17]),
.I1(b[2]),
.LO(\blk00000001/sig00000538 )
);
MULT_AND \blk00000001/blk00000220 (
.I0(a[2]),
.I1(b[3]),
.LO(\blk00000001/sig00000537 )
);
MULT_AND \blk00000001/blk0000021f (
.I0(a[4]),
.I1(b[3]),
.LO(\blk00000001/sig00000536 )
);
MULT_AND \blk00000001/blk0000021e (
.I0(a[6]),
.I1(b[3]),
.LO(\blk00000001/sig00000535 )
);
MULT_AND \blk00000001/blk0000021d (
.I0(a[8]),
.I1(b[3]),
.LO(\blk00000001/sig00000534 )
);
MULT_AND \blk00000001/blk0000021c (
.I0(a[10]),
.I1(b[3]),
.LO(\blk00000001/sig00000533 )
);
MULT_AND \blk00000001/blk0000021b (
.I0(a[12]),
.I1(b[3]),
.LO(\blk00000001/sig00000532 )
);
MULT_AND \blk00000001/blk0000021a (
.I0(a[14]),
.I1(b[3]),
.LO(\blk00000001/sig00000531 )
);
MULT_AND \blk00000001/blk00000219 (
.I0(a[16]),
.I1(b[3]),
.LO(\blk00000001/sig00000530 )
);
MULT_AND \blk00000001/blk00000218 (
.I0(a[17]),
.I1(b[3]),
.LO(\blk00000001/sig0000052f )
);
MULT_AND \blk00000001/blk00000217 (
.I0(a[2]),
.I1(b[4]),
.LO(\blk00000001/sig0000052e )
);
MULT_AND \blk00000001/blk00000216 (
.I0(a[4]),
.I1(b[4]),
.LO(\blk00000001/sig0000052d )
);
MULT_AND \blk00000001/blk00000215 (
.I0(a[6]),
.I1(b[4]),
.LO(\blk00000001/sig0000052c )
);
MULT_AND \blk00000001/blk00000214 (
.I0(a[8]),
.I1(b[4]),
.LO(\blk00000001/sig0000052b )
);
MULT_AND \blk00000001/blk00000213 (
.I0(a[10]),
.I1(b[4]),
.LO(\blk00000001/sig0000052a )
);
MULT_AND \blk00000001/blk00000212 (
.I0(a[12]),
.I1(b[4]),
.LO(\blk00000001/sig00000529 )
);
MULT_AND \blk00000001/blk00000211 (
.I0(a[14]),
.I1(b[4]),
.LO(\blk00000001/sig00000528 )
);
MULT_AND \blk00000001/blk00000210 (
.I0(a[16]),
.I1(b[4]),
.LO(\blk00000001/sig00000527 )
);
MULT_AND \blk00000001/blk0000020f (
.I0(a[17]),
.I1(b[4]),
.LO(\blk00000001/sig00000526 )
);
MULT_AND \blk00000001/blk0000020e (
.I0(a[2]),
.I1(b[5]),
.LO(\blk00000001/sig00000525 )
);
MULT_AND \blk00000001/blk0000020d (
.I0(a[4]),
.I1(b[5]),
.LO(\blk00000001/sig00000524 )
);
MULT_AND \blk00000001/blk0000020c (
.I0(a[6]),
.I1(b[5]),
.LO(\blk00000001/sig00000523 )
);
MULT_AND \blk00000001/blk0000020b (
.I0(a[8]),
.I1(b[5]),
.LO(\blk00000001/sig00000522 )
);
MULT_AND \blk00000001/blk0000020a (
.I0(a[10]),
.I1(b[5]),
.LO(\blk00000001/sig00000521 )
);
MULT_AND \blk00000001/blk00000209 (
.I0(a[12]),
.I1(b[5]),
.LO(\blk00000001/sig00000520 )
);
MULT_AND \blk00000001/blk00000208 (
.I0(a[14]),
.I1(b[5]),
.LO(\blk00000001/sig0000051f )
);
MULT_AND \blk00000001/blk00000207 (
.I0(a[16]),
.I1(b[5]),
.LO(\blk00000001/sig0000051e )
);
MULT_AND \blk00000001/blk00000206 (
.I0(a[17]),
.I1(b[5]),
.LO(\blk00000001/sig0000051d )
);
MULT_AND \blk00000001/blk00000205 (
.I0(a[2]),
.I1(b[6]),
.LO(\blk00000001/sig0000051c )
);
MULT_AND \blk00000001/blk00000204 (
.I0(a[4]),
.I1(b[6]),
.LO(\blk00000001/sig0000051b )
);
MULT_AND \blk00000001/blk00000203 (
.I0(a[6]),
.I1(b[6]),
.LO(\blk00000001/sig0000051a )
);
MULT_AND \blk00000001/blk00000202 (
.I0(a[8]),
.I1(b[6]),
.LO(\blk00000001/sig00000519 )
);
MULT_AND \blk00000001/blk00000201 (
.I0(a[10]),
.I1(b[6]),
.LO(\blk00000001/sig00000518 )
);
MULT_AND \blk00000001/blk00000200 (
.I0(a[12]),
.I1(b[6]),
.LO(\blk00000001/sig00000517 )
);
MULT_AND \blk00000001/blk000001ff (
.I0(a[14]),
.I1(b[6]),
.LO(\blk00000001/sig00000516 )
);
MULT_AND \blk00000001/blk000001fe (
.I0(a[16]),
.I1(b[6]),
.LO(\blk00000001/sig00000515 )
);
MULT_AND \blk00000001/blk000001fd (
.I0(a[17]),
.I1(b[6]),
.LO(\blk00000001/sig00000514 )
);
MULT_AND \blk00000001/blk000001fc (
.I0(a[2]),
.I1(b[7]),
.LO(\blk00000001/sig00000513 )
);
MULT_AND \blk00000001/blk000001fb (
.I0(a[4]),
.I1(b[7]),
.LO(\blk00000001/sig00000512 )
);
MULT_AND \blk00000001/blk000001fa (
.I0(a[6]),
.I1(b[7]),
.LO(\blk00000001/sig00000511 )
);
MULT_AND \blk00000001/blk000001f9 (
.I0(a[8]),
.I1(b[7]),
.LO(\blk00000001/sig00000510 )
);
MULT_AND \blk00000001/blk000001f8 (
.I0(a[10]),
.I1(b[7]),
.LO(\blk00000001/sig0000050f )
);
MULT_AND \blk00000001/blk000001f7 (
.I0(a[12]),
.I1(b[7]),
.LO(\blk00000001/sig0000050e )
);
MULT_AND \blk00000001/blk000001f6 (
.I0(a[14]),
.I1(b[7]),
.LO(\blk00000001/sig0000050d )
);
MULT_AND \blk00000001/blk000001f5 (
.I0(a[16]),
.I1(b[7]),
.LO(\blk00000001/sig0000050c )
);
MULT_AND \blk00000001/blk000001f4 (
.I0(a[17]),
.I1(b[7]),
.LO(\blk00000001/sig0000050b )
);
MULT_AND \blk00000001/blk000001f3 (
.I0(a[2]),
.I1(b[8]),
.LO(\blk00000001/sig0000050a )
);
MULT_AND \blk00000001/blk000001f2 (
.I0(a[4]),
.I1(b[8]),
.LO(\blk00000001/sig00000509 )
);
MULT_AND \blk00000001/blk000001f1 (
.I0(a[6]),
.I1(b[8]),
.LO(\blk00000001/sig00000508 )
);
MULT_AND \blk00000001/blk000001f0 (
.I0(a[8]),
.I1(b[8]),
.LO(\blk00000001/sig00000507 )
);
MULT_AND \blk00000001/blk000001ef (
.I0(a[10]),
.I1(b[8]),
.LO(\blk00000001/sig00000506 )
);
MULT_AND \blk00000001/blk000001ee (
.I0(a[12]),
.I1(b[8]),
.LO(\blk00000001/sig00000505 )
);
MULT_AND \blk00000001/blk000001ed (
.I0(a[14]),
.I1(b[8]),
.LO(\blk00000001/sig00000504 )
);
MULT_AND \blk00000001/blk000001ec (
.I0(a[16]),
.I1(b[8]),
.LO(\blk00000001/sig00000503 )
);
MULT_AND \blk00000001/blk000001eb (
.I0(a[17]),
.I1(b[8]),
.LO(\blk00000001/sig00000502 )
);
MULT_AND \blk00000001/blk000001ea (
.I0(a[2]),
.I1(b[9]),
.LO(\blk00000001/sig00000501 )
);
MULT_AND \blk00000001/blk000001e9 (
.I0(a[4]),
.I1(b[9]),
.LO(\blk00000001/sig00000500 )
);
MULT_AND \blk00000001/blk000001e8 (
.I0(a[6]),
.I1(b[9]),
.LO(\blk00000001/sig000004ff )
);
MULT_AND \blk00000001/blk000001e7 (
.I0(a[8]),
.I1(b[9]),
.LO(\blk00000001/sig000004fe )
);
MULT_AND \blk00000001/blk000001e6 (
.I0(a[10]),
.I1(b[9]),
.LO(\blk00000001/sig000004fd )
);
MULT_AND \blk00000001/blk000001e5 (
.I0(a[12]),
.I1(b[9]),
.LO(\blk00000001/sig000004fc )
);
MULT_AND \blk00000001/blk000001e4 (
.I0(a[14]),
.I1(b[9]),
.LO(\blk00000001/sig000004fb )
);
MULT_AND \blk00000001/blk000001e3 (
.I0(a[16]),
.I1(b[9]),
.LO(\blk00000001/sig000004fa )
);
MULT_AND \blk00000001/blk000001e2 (
.I0(a[17]),
.I1(b[9]),
.LO(\blk00000001/sig000004f9 )
);
MULT_AND \blk00000001/blk000001e1 (
.I0(a[2]),
.I1(b[10]),
.LO(\blk00000001/sig000004f8 )
);
MULT_AND \blk00000001/blk000001e0 (
.I0(a[4]),
.I1(b[10]),
.LO(\blk00000001/sig000004f7 )
);
MULT_AND \blk00000001/blk000001df (
.I0(a[6]),
.I1(b[10]),
.LO(\blk00000001/sig000004f6 )
);
MULT_AND \blk00000001/blk000001de (
.I0(a[8]),
.I1(b[10]),
.LO(\blk00000001/sig000004f5 )
);
MULT_AND \blk00000001/blk000001dd (
.I0(a[10]),
.I1(b[10]),
.LO(\blk00000001/sig000004f4 )
);
MULT_AND \blk00000001/blk000001dc (
.I0(a[12]),
.I1(b[10]),
.LO(\blk00000001/sig000004f3 )
);
MULT_AND \blk00000001/blk000001db (
.I0(a[14]),
.I1(b[10]),
.LO(\blk00000001/sig000004f2 )
);
MULT_AND \blk00000001/blk000001da (
.I0(a[16]),
.I1(b[10]),
.LO(\blk00000001/sig000004f1 )
);
MULT_AND \blk00000001/blk000001d9 (
.I0(a[17]),
.I1(b[10]),
.LO(\blk00000001/sig000004f0 )
);
MULT_AND \blk00000001/blk000001d8 (
.I0(a[2]),
.I1(b[11]),
.LO(\blk00000001/sig000004ef )
);
MULT_AND \blk00000001/blk000001d7 (
.I0(a[4]),
.I1(b[11]),
.LO(\blk00000001/sig000004ee )
);
MULT_AND \blk00000001/blk000001d6 (
.I0(a[6]),
.I1(b[11]),
.LO(\blk00000001/sig000004ed )
);
MULT_AND \blk00000001/blk000001d5 (
.I0(a[8]),
.I1(b[11]),
.LO(\blk00000001/sig000004ec )
);
MULT_AND \blk00000001/blk000001d4 (
.I0(a[10]),
.I1(b[11]),
.LO(\blk00000001/sig000004eb )
);
MULT_AND \blk00000001/blk000001d3 (
.I0(a[12]),
.I1(b[11]),
.LO(\blk00000001/sig000004ea )
);
MULT_AND \blk00000001/blk000001d2 (
.I0(a[14]),
.I1(b[11]),
.LO(\blk00000001/sig000004e9 )
);
MULT_AND \blk00000001/blk000001d1 (
.I0(a[16]),
.I1(b[11]),
.LO(\blk00000001/sig000004e8 )
);
MULT_AND \blk00000001/blk000001d0 (
.I0(a[17]),
.I1(b[11]),
.LO(\blk00000001/sig000004e7 )
);
MULT_AND \blk00000001/blk000001cf (
.I0(a[2]),
.I1(b[12]),
.LO(\blk00000001/sig000004e6 )
);
MULT_AND \blk00000001/blk000001ce (
.I0(a[4]),
.I1(b[12]),
.LO(\blk00000001/sig000004e5 )
);
MULT_AND \blk00000001/blk000001cd (
.I0(a[6]),
.I1(b[12]),
.LO(\blk00000001/sig000004e4 )
);
MULT_AND \blk00000001/blk000001cc (
.I0(a[8]),
.I1(b[12]),
.LO(\blk00000001/sig000004e3 )
);
MULT_AND \blk00000001/blk000001cb (
.I0(a[10]),
.I1(b[12]),
.LO(\blk00000001/sig000004e2 )
);
MULT_AND \blk00000001/blk000001ca (
.I0(a[12]),
.I1(b[12]),
.LO(\blk00000001/sig000004e1 )
);
MULT_AND \blk00000001/blk000001c9 (
.I0(a[14]),
.I1(b[12]),
.LO(\blk00000001/sig000004e0 )
);
MULT_AND \blk00000001/blk000001c8 (
.I0(a[16]),
.I1(b[12]),
.LO(\blk00000001/sig000004df )
);
MULT_AND \blk00000001/blk000001c7 (
.I0(a[17]),
.I1(b[12]),
.LO(\blk00000001/sig000004de )
);
MULT_AND \blk00000001/blk000001c6 (
.I0(a[2]),
.I1(b[13]),
.LO(\blk00000001/sig000004dd )
);
MULT_AND \blk00000001/blk000001c5 (
.I0(a[4]),
.I1(b[13]),
.LO(\blk00000001/sig000004dc )
);
MULT_AND \blk00000001/blk000001c4 (
.I0(a[6]),
.I1(b[13]),
.LO(\blk00000001/sig000004db )
);
MULT_AND \blk00000001/blk000001c3 (
.I0(a[8]),
.I1(b[13]),
.LO(\blk00000001/sig000004da )
);
MULT_AND \blk00000001/blk000001c2 (
.I0(a[10]),
.I1(b[13]),
.LO(\blk00000001/sig000004d9 )
);
MULT_AND \blk00000001/blk000001c1 (
.I0(a[12]),
.I1(b[13]),
.LO(\blk00000001/sig000004d8 )
);
MULT_AND \blk00000001/blk000001c0 (
.I0(a[14]),
.I1(b[13]),
.LO(\blk00000001/sig000004d7 )
);
MULT_AND \blk00000001/blk000001bf (
.I0(a[16]),
.I1(b[13]),
.LO(\blk00000001/sig000004d6 )
);
MULT_AND \blk00000001/blk000001be (
.I0(a[17]),
.I1(b[13]),
.LO(\blk00000001/sig000004d5 )
);
MULT_AND \blk00000001/blk000001bd (
.I0(a[2]),
.I1(b[14]),
.LO(\blk00000001/sig000004d4 )
);
MULT_AND \blk00000001/blk000001bc (
.I0(a[4]),
.I1(b[14]),
.LO(\blk00000001/sig000004d3 )
);
MULT_AND \blk00000001/blk000001bb (
.I0(a[6]),
.I1(b[14]),
.LO(\blk00000001/sig000004d2 )
);
MULT_AND \blk00000001/blk000001ba (
.I0(a[8]),
.I1(b[14]),
.LO(\blk00000001/sig000004d1 )
);
MULT_AND \blk00000001/blk000001b9 (
.I0(a[10]),
.I1(b[14]),
.LO(\blk00000001/sig000004d0 )
);
MULT_AND \blk00000001/blk000001b8 (
.I0(a[12]),
.I1(b[14]),
.LO(\blk00000001/sig000004cf )
);
MULT_AND \blk00000001/blk000001b7 (
.I0(a[14]),
.I1(b[14]),
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MULT_AND \blk00000001/blk000001b6 (
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MULT_AND \blk00000001/blk000001b5 (
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MULT_AND \blk00000001/blk000001b4 (
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MULT_AND \blk00000001/blk000001b3 (
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MULT_AND \blk00000001/blk000001b2 (
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MULT_AND \blk00000001/blk000001b1 (
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MULT_AND \blk00000001/blk000001b0 (
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MULT_AND \blk00000001/blk000001af (
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MULT_AND \blk00000001/blk000001ae (
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MULT_AND \blk00000001/blk000001ad (
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MULT_AND \blk00000001/blk000001ac (
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MULT_AND \blk00000001/blk000001ab (
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MULT_AND \blk00000001/blk000001aa (
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MULT_AND \blk00000001/blk000001a9 (
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MULT_AND \blk00000001/blk000001a8 (
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MULT_AND \blk00000001/blk000001a7 (
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MULT_AND \blk00000001/blk000001a6 (
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MULT_AND \blk00000001/blk000001a5 (
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MULT_AND \blk00000001/blk000001a4 (
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MULT_AND \blk00000001/blk000001a3 (
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MULT_AND \blk00000001/blk000001a2 (
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MULT_AND \blk00000001/blk000001a1 (
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MULT_AND \blk00000001/blk000001a0 (
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MULT_AND \blk00000001/blk0000019f (
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MULT_AND \blk00000001/blk0000019e (
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MULT_AND \blk00000001/blk0000019d (
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MULT_AND \blk00000001/blk0000019c (
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MULT_AND \blk00000001/blk0000019b (
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MULT_AND \blk00000001/blk0000019a (
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MULT_AND \blk00000001/blk00000199 (
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MULT_AND \blk00000001/blk00000198 (
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MULT_AND \blk00000001/blk00000197 (
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MULT_AND \blk00000001/blk00000196 (
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MULT_AND \blk00000001/blk00000195 (
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MULT_AND \blk00000001/blk00000194 (
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MULT_AND \blk00000001/blk00000193 (
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MULT_AND \blk00000001/blk00000192 (
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MULT_AND \blk00000001/blk00000191 (
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MULT_AND \blk00000001/blk00000190 (
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MULT_AND \blk00000001/blk0000018f (
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MULT_AND \blk00000001/blk0000018e (
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MULT_AND \blk00000001/blk0000018d (
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MULT_AND \blk00000001/blk0000018c (
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MULT_AND \blk00000001/blk0000018b (
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MULT_AND \blk00000001/blk0000018a (
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MULT_AND \blk00000001/blk00000189 (
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MULT_AND \blk00000001/blk00000188 (
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MULT_AND \blk00000001/blk00000187 (
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MUXCY \blk00000001/blk00000186 (
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XORCY \blk00000001/blk00000185 (
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MUXCY \blk00000001/blk00000184 (
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MUXCY \blk00000001/blk00000183 (
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XORCY \blk00000001/blk00000182 (
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MUXCY \blk00000001/blk00000181 (
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MUXCY \blk00000001/blk00000180 (
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XORCY \blk00000001/blk0000017f (
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MUXCY \blk00000001/blk0000017e (
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MUXCY \blk00000001/blk0000017d (
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XORCY \blk00000001/blk0000017c (
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MUXCY \blk00000001/blk0000017b (
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MUXCY \blk00000001/blk0000017a (
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XORCY \blk00000001/blk00000179 (
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MUXCY \blk00000001/blk00000178 (
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MUXCY \blk00000001/blk00000177 (
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XORCY \blk00000001/blk00000176 (
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MUXCY \blk00000001/blk00000175 (
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MUXCY \blk00000001/blk00000174 (
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XORCY \blk00000001/blk00000173 (
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MUXCY \blk00000001/blk00000172 (
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MUXCY \blk00000001/blk00000171 (
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XORCY \blk00000001/blk00000170 (
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MUXCY \blk00000001/blk0000016f (
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MUXCY \blk00000001/blk0000016e (
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MUXCY \blk00000001/blk0000016d (
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MUXCY \blk00000001/blk0000016c (
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MUXCY \blk00000001/blk0000016b (
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MUXCY \blk00000001/blk0000016a (
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MUXCY \blk00000001/blk00000169 (
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MUXCY \blk00000001/blk00000168 (
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MUXCY \blk00000001/blk00000167 (
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MUXCY \blk00000001/blk00000166 (
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MUXCY \blk00000001/blk00000165 (
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MUXCY \blk00000001/blk00000164 (
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MUXCY \blk00000001/blk00000163 (
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MUXCY \blk00000001/blk00000162 (
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MUXCY \blk00000001/blk00000161 (
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MUXCY \blk00000001/blk00000160 (
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MUXCY \blk00000001/blk0000015f (
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MUXCY \blk00000001/blk0000015e (
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MUXCY \blk00000001/blk0000015d (
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MUXCY \blk00000001/blk0000015c (
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MUXCY \blk00000001/blk0000015b (
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MUXCY \blk00000001/blk0000015a (
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MUXCY \blk00000001/blk00000159 (
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MUXCY \blk00000001/blk00000158 (
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MUXCY \blk00000001/blk00000157 (
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MUXCY \blk00000001/blk00000156 (
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MUXCY \blk00000001/blk00000155 (
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MUXCY \blk00000001/blk00000154 (
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MUXCY \blk00000001/blk00000153 (
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MUXCY \blk00000001/blk00000152 (
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MUXCY \blk00000001/blk00000151 (
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MUXCY \blk00000001/blk00000150 (
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MUXCY \blk00000001/blk0000014f (
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MUXCY \blk00000001/blk0000014e (
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MUXCY \blk00000001/blk0000014d (
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MUXCY \blk00000001/blk0000014c (
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MUXCY \blk00000001/blk0000014b (
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MUXCY \blk00000001/blk0000014a (
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MUXCY \blk00000001/blk00000149 (
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MUXCY \blk00000001/blk00000148 (
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MUXCY \blk00000001/blk00000147 (
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MUXCY \blk00000001/blk00000146 (
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MUXCY \blk00000001/blk00000145 (
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MUXCY \blk00000001/blk00000144 (
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MUXCY \blk00000001/blk00000143 (
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MUXCY \blk00000001/blk00000142 (
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MUXCY \blk00000001/blk00000141 (
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MUXCY \blk00000001/blk00000140 (
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MUXCY \blk00000001/blk0000013f (
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MUXCY \blk00000001/blk0000013e (
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MUXCY \blk00000001/blk0000013d (
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MUXCY \blk00000001/blk0000013c (
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MUXCY \blk00000001/blk0000013b (
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MUXCY \blk00000001/blk0000013a (
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MUXCY \blk00000001/blk00000139 (
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MUXCY \blk00000001/blk00000138 (
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MUXCY \blk00000001/blk00000137 (
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MUXCY \blk00000001/blk00000136 (
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MUXCY \blk00000001/blk00000135 (
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MUXCY \blk00000001/blk00000134 (
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MUXCY \blk00000001/blk00000133 (
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MUXCY \blk00000001/blk00000132 (
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MUXCY \blk00000001/blk00000131 (
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MUXCY \blk00000001/blk00000130 (
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MUXCY \blk00000001/blk0000012f (
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MUXCY \blk00000001/blk0000012e (
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MUXCY \blk00000001/blk0000012d (
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MUXCY \blk00000001/blk0000012c (
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MUXCY \blk00000001/blk0000012b (
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MUXCY \blk00000001/blk0000012a (
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MUXCY \blk00000001/blk00000129 (
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MUXCY \blk00000001/blk00000128 (
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MUXCY \blk00000001/blk00000127 (
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MUXCY \blk00000001/blk00000126 (
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MUXCY \blk00000001/blk00000125 (
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MUXCY \blk00000001/blk00000124 (
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MUXCY \blk00000001/blk00000123 (
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MUXCY \blk00000001/blk00000122 (
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MUXCY \blk00000001/blk00000121 (
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MUXCY \blk00000001/blk00000120 (
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MUXCY \blk00000001/blk0000011f (
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MUXCY \blk00000001/blk0000011e (
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MUXCY \blk00000001/blk0000011d (
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MUXCY \blk00000001/blk0000011c (
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MUXCY \blk00000001/blk0000011b (
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MUXCY \blk00000001/blk0000011a (
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MUXCY \blk00000001/blk00000119 (
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MUXCY \blk00000001/blk00000118 (
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MUXCY \blk00000001/blk00000117 (
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MUXCY \blk00000001/blk00000116 (
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MUXCY \blk00000001/blk00000115 (
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MUXCY \blk00000001/blk00000114 (
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MUXCY \blk00000001/blk00000113 (
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MUXCY \blk00000001/blk00000112 (
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MUXCY \blk00000001/blk00000111 (
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MUXCY \blk00000001/blk00000110 (
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MUXCY \blk00000001/blk0000010f (
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MUXCY \blk00000001/blk0000010e (
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MUXCY \blk00000001/blk0000010d (
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MUXCY \blk00000001/blk0000010c (
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MUXCY \blk00000001/blk0000010b (
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MUXCY \blk00000001/blk0000010a (
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MUXCY \blk00000001/blk00000109 (
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MUXCY \blk00000001/blk00000108 (
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MUXCY \blk00000001/blk00000107 (
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MUXCY \blk00000001/blk00000106 (
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MUXCY \blk00000001/blk00000105 (
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MUXCY \blk00000001/blk00000104 (
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MUXCY \blk00000001/blk00000103 (
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MUXCY \blk00000001/blk00000102 (
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MUXCY \blk00000001/blk00000101 (
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MUXCY \blk00000001/blk00000100 (
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MUXCY \blk00000001/blk000000ff (
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MUXCY \blk00000001/blk000000fe (
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MUXCY \blk00000001/blk000000fd (
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MUXCY \blk00000001/blk000000fc (
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MUXCY \blk00000001/blk000000fb (
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MUXCY \blk00000001/blk000000fa (
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MUXCY \blk00000001/blk000000f9 (
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MUXCY \blk00000001/blk000000f8 (
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MUXCY \blk00000001/blk000000f7 (
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MUXCY \blk00000001/blk000000f6 (
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MUXCY \blk00000001/blk000000f5 (
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MUXCY \blk00000001/blk000000f4 (
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MUXCY \blk00000001/blk000000f3 (
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MUXCY \blk00000001/blk000000f2 (
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MUXCY \blk00000001/blk000000f1 (
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MUXCY \blk00000001/blk000000f0 (
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MUXCY \blk00000001/blk000000ef (
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MUXCY \blk00000001/blk000000ee (
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MUXCY \blk00000001/blk000000ed (
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MUXCY \blk00000001/blk000000ec (
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MUXCY \blk00000001/blk000000eb (
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MUXCY \blk00000001/blk000000ea (
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MUXCY \blk00000001/blk000000e9 (
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MUXCY \blk00000001/blk000000e8 (
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MUXCY \blk00000001/blk000000e7 (
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MUXCY \blk00000001/blk000000e6 (
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MUXCY \blk00000001/blk000000e5 (
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MUXCY \blk00000001/blk000000e4 (
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MUXCY \blk00000001/blk000000e3 (
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MUXCY \blk00000001/blk000000e2 (
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MUXCY \blk00000001/blk000000e1 (
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MUXCY \blk00000001/blk000000e0 (
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MUXCY \blk00000001/blk000000df (
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MUXCY \blk00000001/blk000000de (
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MUXCY \blk00000001/blk000000dd (
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MUXCY \blk00000001/blk000000dc (
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MUXCY \blk00000001/blk000000db (
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MUXCY \blk00000001/blk000000da (
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MUXCY \blk00000001/blk000000d9 (
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MUXCY \blk00000001/blk000000d8 (
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MUXCY \blk00000001/blk000000d7 (
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MUXCY \blk00000001/blk000000d6 (
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MUXCY \blk00000001/blk000000d5 (
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MUXCY \blk00000001/blk000000d4 (
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MUXCY \blk00000001/blk000000d3 (
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MUXCY \blk00000001/blk000000d2 (
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MUXCY \blk00000001/blk000000d1 (
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MUXCY \blk00000001/blk000000d0 (
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MUXCY \blk00000001/blk000000cf (
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MUXCY \blk00000001/blk000000ce (
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MUXCY \blk00000001/blk000000cd (
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MUXCY \blk00000001/blk000000cc (
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MUXCY \blk00000001/blk000000cb (
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MUXCY \blk00000001/blk000000ca (
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MUXCY \blk00000001/blk000000c9 (
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MUXCY \blk00000001/blk000000c8 (
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MUXCY \blk00000001/blk000000c7 (
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MUXCY \blk00000001/blk000000c6 (
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MUXCY \blk00000001/blk000000c5 (
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MUXCY \blk00000001/blk000000c4 (
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MUXCY \blk00000001/blk000000c3 (
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XORCY \blk00000001/blk000000bf (
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XORCY \blk00000001/blk000000be (
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XORCY \blk00000001/blk000000bd (
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XORCY \blk00000001/blk000000bc (
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XORCY \blk00000001/blk000000bb (
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XORCY \blk00000001/blk000000ba (
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XORCY \blk00000001/blk000000b9 (
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XORCY \blk00000001/blk000000b8 (
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XORCY \blk00000001/blk000000b6 (
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.O(\blk00000001/sig00000244 )
);
XORCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig000003f1 ),
.LI(\blk00000001/sig00000232 ),
.O(\blk00000001/sig00000242 )
);
XORCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig000003f0 ),
.LI(\blk00000001/sig00000230 ),
.O(\blk00000001/sig00000240 )
);
XORCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig000003ef ),
.LI(\blk00000001/sig0000022e ),
.O(\blk00000001/sig0000023e )
);
XORCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig000003ee ),
.LI(\blk00000001/sig0000022c ),
.O(\blk00000001/sig0000023c )
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig000003ed ),
.LI(\blk00000001/sig0000022a ),
.O(\blk00000001/sig0000023a )
);
XORCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig000003ec ),
.LI(\blk00000001/sig00000228 ),
.O(\blk00000001/sig00000238 )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig000003eb ),
.LI(\blk00000001/sig000001fa ),
.O(\blk00000001/sig00000237 )
);
XORCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig000003ea ),
.LI(\blk00000001/sig00000225 ),
.O(\blk00000001/sig00000235 )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig000003e9 ),
.LI(\blk00000001/sig00000223 ),
.O(\blk00000001/sig00000233 )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig000003e8 ),
.LI(\blk00000001/sig00000221 ),
.O(\blk00000001/sig00000231 )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig000003e7 ),
.LI(\blk00000001/sig0000021f ),
.O(\blk00000001/sig0000022f )
);
XORCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig000003e6 ),
.LI(\blk00000001/sig0000021d ),
.O(\blk00000001/sig0000022d )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig000003e5 ),
.LI(\blk00000001/sig0000021b ),
.O(\blk00000001/sig0000022b )
);
XORCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig000003e4 ),
.LI(\blk00000001/sig00000219 ),
.O(\blk00000001/sig00000229 )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig000003e3 ),
.LI(\blk00000001/sig00000217 ),
.O(\blk00000001/sig00000227 )
);
XORCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig000003e2 ),
.LI(\blk00000001/sig000001f9 ),
.O(\blk00000001/sig00000226 )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig000003e1 ),
.LI(\blk00000001/sig00000214 ),
.O(\blk00000001/sig00000224 )
);
XORCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig000003e0 ),
.LI(\blk00000001/sig00000213 ),
.O(\blk00000001/sig00000222 )
);
XORCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig000003df ),
.LI(\blk00000001/sig00000212 ),
.O(\blk00000001/sig00000220 )
);
XORCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig000003de ),
.LI(\blk00000001/sig00000211 ),
.O(\blk00000001/sig0000021e )
);
XORCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig000003dd ),
.LI(\blk00000001/sig00000210 ),
.O(\blk00000001/sig0000021c )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig000003dc ),
.LI(\blk00000001/sig0000020f ),
.O(\blk00000001/sig0000021a )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig000003db ),
.LI(\blk00000001/sig0000020e ),
.O(\blk00000001/sig00000218 )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig000003da ),
.LI(\blk00000001/sig0000020d ),
.O(\blk00000001/sig00000216 )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig000003d9 ),
.LI(\blk00000001/sig00000783 ),
.O(\blk00000001/sig00000215 )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig000003d8 ),
.LI(\blk00000001/sig000001f8 ),
.O(\blk00000001/sig0000020c )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig00000052 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig00000051 )
);
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous DDR input
*/
module ssio_ddr_in_diff #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk_p,
input wire input_clk_n,
input wire [WIDTH-1:0] input_d_p,
input wire [WIDTH-1:0] input_d_n,
output wire output_clk,
output wire [WIDTH-1:0] output_q1,
output wire [WIDTH-1:0] output_q2
);
wire input_clk;
wire [WIDTH-1:0] input_d;
genvar n;
generate
if (TARGET == "XILINX") begin
IBUFDS
clk_ibufds_inst (
.I(input_clk_p),
.IB(input_clk_n),
.O(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
IBUFDS
data_ibufds_inst (
.I(input_d_p[n]),
.IB(input_d_n[n]),
.O(input_d[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_INBUF_DIFF
clk_inbuf_diff_inst (
.i(input_clk_p),
.ibar(input_clk_n),
.o(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_INBUF_DIFF
data_inbuf_diff_inst (
.i(input_d_p[n]),
.ibar(input_d_n[n]),
.o(input_d[n])
);
end
end else begin
assign input_clk = input_clk_p;
assign input_d = input_d_p;
end
endgenerate
ssio_ddr_in #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(WIDTH)
)
ssio_ddr_in_inst(
.input_clk(input_clk),
.input_d(input_d),
.output_clk(output_clk),
.output_q1(output_q1),
.output_q2(output_q2)
);
endmodule
|
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