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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DFRTP_PP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTP_PP_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire [3:0] sw,
input wire [3:0] btn,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* Ethernet: 100BASE-T MII
*/
output wire phy_ref_clk,
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
input wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_en,
input wire phy_col,
input wire phy_crs,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
// Internal 125 MHz clock
wire clk_mmcm_out;
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
wire clk_25mhz_mmcm_out;
wire clk_25mhz_int;
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// Divide by 40 to get output frequency of 25 MHz
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(40),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk_25mhz_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
BUFG
clk_25mhz_bufg_inst (
.I(clk_25mhz_mmcm_out),
.O(clk_25mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btn,
sw}),
.out({btn_int,
sw_int})
);
wire uart_rxd_int;
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
assign phy_ref_clk = clk_25mhz_int;
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led0_r(led0_r),
.led0_g(led0_g),
.led0_b(led0_b),
.led1_r(led1_r),
.led1_g(led1_g),
.led1_b(led1_b),
.led2_r(led2_r),
.led2_g(led2_g),
.led2_b(led2_b),
.led3_r(led3_r),
.led3_g(led3_g),
.led3_b(led3_b),
.led4(led4),
.led5(led5),
.led6(led6),
.led7(led7),
/*
* Ethernet: 100BASE-T MII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_col(phy_col),
.phy_crs(phy_crs),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
`resetall
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
//
/* verilator lint_off LITENDIAN */
module some_module (
input wrclk
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge wrclk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (wrclk)
some_other_state <= 0;
end
endmodule
`define BROKEN
module t1(
input [-12:-9] i_clks,
input i_clk0,
input i_clk1
);
some_module
some_module
(
`ifdef BROKEN
.wrclk (i_clks[-12])
`else
.wrclk (i_clk1)
`endif
);
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [-12:-9] the_clks;
logic data_q;
assign the_clks[-12] = i_clk1;
assign the_clks[-11] = i_clk2;
assign the_clks[-10] = i_clk1;
assign the_clks[-9] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk1),
.i_clk2 (clk2),
.i_data (data_in)
);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fifo_1k_x_8_dual_port (
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count,
wr_rst_busy,
rd_rst_busy
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 core_clk CLK" *)
input wire clk;
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [7 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [7 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire [10 : 0] data_count;
output wire wr_rst_busy;
output wire rd_rst_busy;
fifo_generator_v13_2_4 #(
.C_COMMON_CLOCK(1),
.C_SELECT_XPM(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(11),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(8),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_FAMILY("zynq"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(11),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(11),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_EN_SAFETY_CKT(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(1),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(clk),
.rst(rst),
.srst(1'D0),
.wr_clk(1'D0),
.wr_rst(1'D0),
.rd_clk(1'D0),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(10'B0),
.prog_empty_thresh_assert(10'B0),
.prog_empty_thresh_negate(10'B0),
.prog_full_thresh(10'B0),
.prog_full_thresh_assert(10'B0),
.prog_full_thresh_negate(10'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(data_count),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(wr_rst_busy),
.rd_rst_busy(rd_rst_busy),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
module asl(value1, value2, shift_hex, value_out, EN);
input [31:0] value1, value2;
input [3:0] shift_hex;
output [31:0] value_out;
input EN;
wire or_unary = |value2[31:5];
wire value2_shrink = value2[4:0];
wire [4:0] shift_amt = (value2_shrink== 32'b0) ?
( {1'b0, shift_hex} + 5'b1) : (value2_shrink + {1'b0, shift_hex});
assign value_out = (or_unary==1'b1) ? 32'b0 : (
(shift_amt == 5'b00000) ? value1[31:0] :
(shift_amt == 5'b00001) ? {value1[30:0], 01'b0 } :
(shift_amt == 5'b00010) ? {value1[29:0], 02'b0 } :
(shift_amt == 5'b00011) ? {value1[28:0], 03'b0 } :
(shift_amt == 5'b00100) ? {value1[27:0], 04'b0 } :
(shift_amt == 5'b00101) ? {value1[26:0], 05'b0 } :
(shift_amt == 5'b00110) ? {value1[25:0], 06'b0 } :
(shift_amt == 5'b00111) ? {value1[24:0], 07'b0 } :
(shift_amt == 5'b01000) ? {value1[23:0], 08'b0 } :
(shift_amt == 5'b01001) ? {value1[22:0], 09'b0 } :
(shift_amt == 5'b01010) ? {value1[21:0], 10'b0 } :
(shift_amt == 5'b01011) ? {value1[20:0], 11'b0 } :
(shift_amt == 5'b01100) ? {value1[19:0], 12'b0 } :
(shift_amt == 5'b01101) ? {value1[18:0], 13'b0 } :
(shift_amt == 5'b01110) ? {value1[17:0], 14'b0 } :
(shift_amt == 5'b01111) ? {value1[16:0], 15'b0 } :
(shift_amt == 5'b10000) ? {value1[15:0], 16'b0 } :
(shift_amt == 5'b10001) ? {value1[14:0], 17'b0 } :
(shift_amt == 5'b10010) ? {value1[13:0], 18'b0 } :
(shift_amt == 5'b10011) ? {value1[12:0], 19'b0 } :
(shift_amt == 5'b10100) ? {value1[11:0], 20'b0 } :
(shift_amt == 5'b10101) ? {value1[10:0], 21'b0 } :
(shift_amt == 5'b10110) ? {value1[09:0], 22'b0 } :
(shift_amt == 5'b10111) ? {value1[08:0], 23'b0 } :
(shift_amt == 5'b11000) ? {value1[07:0], 24'b0 } :
(shift_amt == 5'b11001) ? {value1[06:0], 25'b0 } :
(shift_amt == 5'b11010) ? {value1[05:0], 26'b0 } :
(shift_amt == 5'b11011) ? {value1[04:0], 27'b0 } :
(shift_amt == 5'b11100) ? {value1[03:0], 28'b0 } :
(shift_amt == 5'b11101) ? {value1[02:0], 29'b0 } :
(shift_amt == 5'b11110) ? {value1[01:0], 30'b0 } :
(shift_amt == 5'b11111) ? {value1[00:0], 31'b0 } : 32'b0);
endmodule |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_16x8k.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_16x8k (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [12:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.clocken0 (clken),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x8k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x8k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x8k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x8k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x8k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x8k_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
(** * Hoare: Hoare Logic, Part I *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Imp.
Require Import Maps.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than of particular programs in the language. These
included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g., functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (sometimes also subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the book when we discuss _types_ and _type
soundness_. In this chapter, though, we turn to a different set
of issues.
Our goal is to carry out some simple examples of _program
verification_ -- i.e., to use the precise definition of Imp to
prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning
system called _Floyd-Hoare Logic_ -- often shortened to just
_Hoare Logic_ -- in which each of the syntactic constructs of Imp
is equipped with a generic "proof rule" that can be used to reason
compositionally about the correctness of programs involving this
construct.
Hoare Logic originated in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems.
Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(** This chapter:
- A systematic method for reasoning about the correctness of
particular programs in Imp
Goals:
- a natural notation for _program specifications_ and
- a _compositional_ proof technique for program correctness
Plan:
- assertions (Hoare Triples)
- proof rules
- decorated programs
- loop invariants
- examples *)
(* ################################################################# *)
(** * Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when execution reaches that
point. Formally, an assertion is just a family of propositions
indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
(** Paraphrase the following assertions in English (or your favorite
natural language). *)
Module ExAssertions.
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables in assertions (we
will never need to talk about two different memory states at the
same time). For discussing examples informally, we'll adopt some
simplifying conventions: we'll drop the initial [fun st =>], and
we'll write just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** This example also illustrates a convention that we'll use
throughout the Hoare Logic chapters: in informal assertions,
capital letters like {X], [Y], and [Z] are Imp variables, while
lowercase letters like [x], [y], [m], and [n] are ordinary Coq
variables (of type [nat]). This is why, when translating from
informal to formal, we replace [X] with [st X] but leave [m]
alone. *)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" := (assert_implies P Q)
(at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** We'll also want the "iff" variant of implication between
assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ################################################################# *)
(** * Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** In general, the behavior of a command is to transform one state to
another, so it is natural to express claims about commands in
terms of assertions that are true before and after the command
executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st \\ st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.)
To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ################################################################# *)
(** * Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of specific Hoare triples. That
is, we want the structure of a program's correctness proof to
mirror the structure of the program itself. To this end, in the
sections below, we'll introduce a rule for reasoning about each of
the different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules for gluing things together. We
will then be able to prove programs correct using these proof
rules, without ever unfolding the definition of [hoare_triple]. *)
(* ================================================================= *)
(** ** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this valid Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1].
That is, the property of being equal to [1] gets transferred
from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment. *)
(** More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple. *)
(** This can be made even more general. To conclude that an
arbitrary property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]". *)
(** For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the same effect by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (t_update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] stands for an assertion -- let's call it [P'] --
that is just like [P] except that, wherever [P] looks up the
variable [X] in the current state, [P'] instead uses the value
of the expression [a]. *)
(** To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(t_update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(t_update st X 3)
and further simplifies to
fun st =>
((t_update st X 3) X) <= 5)
and finally to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected). *)
(** For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(t_update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((t_update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now, using the concept of substitution, we can give the precise
proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_asgn. Qed.
(** **** Exercise: 2 starsM (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements (use the names [assn_sub_ex1]
and [assn_sub_ex2]) and use [hoare_asgn] to prove them. *)
Example assn_sub_ex1 :
{{ (fun st => st X <= 5) [X |-> APlus (AId X) (ANum 1)] }}
(X ::= APlus (AId X) (ANum 1))
{{ fun st => st X <= 5 }}.
Proof. apply hoare_asgn. Qed.
Example assn_sub_ex2 :
{{ (fun st => 0 <= (st X) /\ st X <= 5) [X |-> (ANum 3)] }}
(X ::= ANum 3)
{{ fun st => 0 <= st X /\ st X <= 5 }}.
Proof. apply hoare_asgn. Qed.
(** [] *)
(** **** Exercise: 2 stars, recommendedM (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems puzzling, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect and
argue informally that it is really a counterexample. (Hint:
The rule universally quantifies over the arithmetic expression
[a], and your counterexample needs to exhibit an [a] for which
the rule doesn't work.) *)
(**
Let a = X + 1. We can choose this expression because arithmetic expressions
quantify over variable names as well as numbers in IMP. To show that hoare_asgn_wrong
is incorrect, we simply apply it. Since the precondition is trivially try, we enter the
commant block and assign X + 1 to X. In the postcondition, we have X = X + 1, which is
absurd.
*)
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, by using a _parameter_ [m] (a Coq number) to remember the
original value of [X] we can define a Hoare rule for assignment
that does, intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = t_update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct. (Also note that this rule is more complicated than
[hoare_asgn].)
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (t_update st X m)
/\ st X = aeval (t_update st X m) a }}.
Proof.
intros F m a P. unfold hoare_triple. intros st st' H0 H1.
destruct H1. inversion H0; subst.
assert (t_update (t_update st X (aeval st a)) X (st X) = st).
{ apply F. intros x. rewrite -> t_update_shadow.
rewrite t_update_same. reflexivity. }
rewrite -> H1. rewrite -> t_update_eq.
split. assumption. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (t_update st X m) /\
st X = aeval (t_update st X m) a }}
*)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (t_update st X m) /\
st X = aeval (t_update st X m) a }}.
Proof.
intros F a P. unfold hoare_triple. intros. exists (st X).
apply hoare_asgn_fwd with (m := (st X)) (a := a) (P := P) in F.
unfold hoare_triple in F. apply F with st.
assumption. split. assumption. reflexivity.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
_equivalent_, so if one triple is valid, then the other must
certainly be as well. We can capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
*)
(** Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we can use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally... *)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, t_update. simpl. reflexivity.
Qed.
(** Finally, for convenience in proofs, we can state a combined
rule of consequence that allows us to vary both the precondition
and the postcondition at the same time.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ================================================================= *)
(** ** Digression: The [eapply] Tactic *)
(** This is a good moment to take another look at the [eapply] tactic,
which we introduced briefly in the [Auto] chapter.
We had to write "[with (P' := ...)]" explicitly in the proof of
[hoare_asgn_example1] and [hoare_consequence] above, to make sure
that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is annoying, both because the assertion is a bit long and
also because, in [hoare_asgn_example1], the very next thing we are
going to do -- applying the [hoare_asgn] rule -- will tell us
exactly what it should be! We can use [eapply] instead of [apply]
to tell Coq, essentially, "Be patient: The missing part is going
to be filled in later in the proof." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with _existential variables_ (written [?nnn]), which
function as placeholders for expressions that will be
determined (by further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]. (The warnings look
different between Coq 8.4 and Coq 8.5. In 8.4, the warning says
"No more subgoals but non-instantiated existential variables." In
8.5, it says "All the remaining goals are on the shelf," meaning
that we've finished all our top-level proof obligations but along
the way we've put some aside to be done later, and we have not
finished those.) Trying to close the proof with [Qed] gives an
error. *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing ordinary variables that did not
exist at the time the existential variable was created. (The
reason for this technical restriction is that allowing such
instantiation would lead to inconsistency of Coq's logic.) *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix: doing [destruct HP] _before_
doing [eapply HQ]. *)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** The [apply HP'] in the last step unifies the existential variable
in the goal with the variable [y].
Note that the [assumption] tactic doesn't work in this case, since
it cannot handle existential variables. However, Coq also
provides an [eassumption] tactic that solves the goal if one of
the premises matches the goal up to instantiations of existential
variables. We can use it instead of [apply HP'] if we like. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 starsM (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements (name them [assn_sub_ex1'] and
[assn_sub_ex2']) and use [hoare_asgn] and [hoare_consequence_pre]
to prove them. *)
Theorem assn_sub_ex1' :
{{ fun st => st X + 1 <= 5 }}
( X ::= APlus (AId X) (ANum 1))
{{ fun st => st X <= 5 }}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn. unfold assert_implies.
intros st H0. unfold assn_sub. rewrite t_update_eq.
simpl. assumption.
Qed.
Theorem assn_sub_ex1'' :
{{ fun st => st X + 1 <= 5 }}
( X ::= APlus (AId X) (ANum 1))
{{ fun st => st X <= 5 }}.
Proof.
remember (fun st : state => st X + 1 <= 5) as P.
remember (fun st : state => st X <= 5) as P'.
remember P' as Q.
assert(H0 : forall st : state, st X <= st X + 1).
{ intros. omega. }
assert(H1 : P ->> P').
{ intros st HP. admit. }
apply hoare_consequence_pre with (P' := P').
unfold hoare_triple. intros st st' H HP'. rewrite <- HeqQ in HP'.
rewrite -> HeqP' in HP'.
Abort.
Theorem assn_sub_ex2' :
{{ fun st => 0 <= 3 /\ 3 <= 5 }}
( X ::= ANum 3)
{{ fun st => 0 <= st X /\ st X <= 5 }}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn. unfold assert_implies.
intros st H035. unfold assn_sub. rewrite -> t_update_eq.
simpl. assumption.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property [P]:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ================================================================= *)
(** ** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in backwards order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule, since the natural way to construct a Hoare-logic
proof is to begin at the end of the program (with the final
postcondition) and push postconditions backwards through commands
until we reach the beginning. *)
(** Informally, a nice way of displaying a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
(** Here's an example of a program involving both assignment and
sequencing. *)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
- (* right part of seq *)
apply hoare_skip.
- (* left part of seq *)
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity.
Qed.
(** We typically use [hoare_seq] in conjunction with
[hoare_consequence_pre] and the [eapply] tactic, as in this
example. *)
(** **** Exercise: 2 stars, recommended (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
(Note the use of "[->>]" decorations, each marking a use of
[hoare_consequence_pre].) *)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
eapply hoare_seq. apply hoare_asgn.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold assert_implies.
intros st H. unfold assn_sub.
split; simpl; reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y] and
show that it satisfies the following specification:
{{X <= Y}} c {{Y <= X}}
Your proof should not need to use [unfold hoare_triple]. *)
Definition swap_program : com :=
Z ::= AId Y;;
Y ::= AId X;;
X ::= AId Z.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
eapply hoare_seq.
eapply hoare_seq.
apply hoare_asgn.
apply hoare_asgn.
intros st st' H HstXY.
inversion H; subst.
unfold assn_sub. simpl.
remember (t_update st Z (st Y)) as mz.
rewrite -> t_update_eq. rewrite -> t_update_neq.
rewrite -> t_update_eq.
subst.
rewrite -> t_update_neq. rewrite -> t_update_neq. rewrite -> t_update_eq.
assumption.
unfold not. intros. inversion H0.
unfold not. intros. inversion H0.
unfold not. intros. inversion H0.
Qed.
(** [] *)
(** **** Exercise: 3 starsM (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(*
Let a = AId X.
Then aeval st a = aeval st (AId X) = X, so that when n <> 3,
st X = n <> 3.
For example, if we introduct n = 4 above, with aeval st X = 4,
then we cannot apply rule hoare_asgn since st X = 4 <> 3.
*)
(** [] *)
(* ================================================================= *)
(** ** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands?
Certainly, if the same assertion [Q] holds after executing
either of the branches, then it holds after the whole conditional.
So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
*)
(** However, this is rather weak. For example, using this rule,
we cannot show
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** Fortunately, we can say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
- (* b is true *)
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
- (* b is false *)
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ----------------------------------------------------------------- *)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
- (* Then *)
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, t_update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
- (* Else *)
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, t_update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]. Do not
use [unfold hoare_triple]. *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
apply hoare_if.
- eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, t_update, assert_implies.
simpl. intros st [_ H]. apply le_plus_minus.
apply leb_complete. assumption.
- eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, t_update, assert_implies.
simpl. intros st [_ H]. reflexivity.
Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 starsM (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '\\' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st \\ st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st \\ t_update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st \\ st' -> c2 / st' \\ st'' -> (c1 ;; c2) / st \\ st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st \\ st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(WHILE b1 DO c1 END) / st' \\ st'' ->
(WHILE b1 DO c1 END) / st \\ st''
| E_If1True : forall st st' b c,
beval st b = true ->
c / st \\ st' ->
(IF1 b THEN c FI) / st \\ st'
| E_If1False : forall st b c,
beval st b = false ->
(IF1 b THEN c FI) / st \\ st
where "c1 '/' st '\\' st'" := (ceval c1 st st').
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st \\ st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
Theorem hoare_if1 :
forall (P Q : Assertion) (b : bexp) (c : com),
{{ fun st => P st /\ bassn b st }} c {{ Q }} ->
{{ fun st => P st /\ ~ (bassn b st) }} SKIP {{ Q }} ->
{{ P }} (IF1 b THEN c FI) {{ Q }}.
Proof.
intros P Q b c H0 H1. unfold hoare_triple.
intros st st' Hbc. inversion Hbc; subst.
- intros HPst. apply (H0 st st'). assumption.
split. assumption. unfold bassn. assumption.
- intros HPst'. apply (H1 st' st'). apply E_Skip.
split. assumption. apply bexp_eval_false. assumption.
Qed.
(** For full credit, prove formally [hoare_if1_good] that your rule is
precise enough to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof.
eapply hoare_if1.
- intros st st' H H'. inversion H; subst; simpl.
rewrite -> t_update_eq. rewrite -> t_update_neq.
destruct H'. assumption. unfold not.
intros HXZ. inversion HXZ.
- intros st st' H H'. inversion H; subst. destruct H'.
unfold bassn in H1. simpl in H1.
destruct (beq_nat (st' Y) 0) eqn : HeqY.
+ simpl in H1. apply beq_nat_true in HeqY. omega.
+ destruct H1. simpl. reflexivity.
Qed.
End If1.
(** [] *)
(* ================================================================= *)
(** ** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(** But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little: *)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(** What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule: *)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(** This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the
rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn : Heqwcom.
induction He;
try (inversion Heqwcom); subst; clear Heqwcom.
- (* E_WhileEnd *)
split. assumption. apply bexp_eval_false. assumption.
- (* E_WhileLoop *)
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(** One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop. *)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, t_update. simpl.
intros st [H1 H2]. apply leb_complete in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (leb (st X) 2) eqn : Heqle.
exfalso. apply Hb; reflexivity.
apply leb_iff_conv in Heqle. omega.
Qed.
(** We can use the WHILE rule to prove the following Hoare triple... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
- (* Loop body preserves invariant *)
apply hoare_post_true. intros st. apply I.
- (* Loop invariant and negated guard imply postcondition *)
simpl. intros st [Hinv Hguard].
exfalso. apply Hguard. reflexivity.
- (* Precondition implies invariant *)
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ----------------------------------------------------------------- *)
(** *** Exercise: [REPEAT] *)
(** **** Exercise: 4 stars, advancedM (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to the
language for programs involving it. (You may recall that the
evaluation rule is given in an example in the [Auto] chapter.
Try to figure it out yourself here rather than peeking.) *)
Module RepeatExercise.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (t_update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_Repeat : forall st st' st'' b c,
ceval st c st' ->
ceval st' (WHILE (BNot b) DO c END) st'' ->
ceval st (REPEAT c UNTIL b END) st''
.
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '\\' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st \\ st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat] evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state \\
t_update (t_update empty_state X 1) Y 1.
Proof.
eapply E_Repeat.
eapply E_Seq. constructor. reflexivity.
constructor. reflexivity.
apply E_WhileEnd. reflexivity.
Qed.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
Theorem hoare_repeat : forall (P : Assertion) (b : bexp) (c : com),
{{ fun st => P st /\ ~ (bassn b st)}} c {{ P }} ->
{{ P }} (WHILE (BNot b) DO c END) {{ fun st => P st /\ bassn b st }} ->
{{ P }} (REPEAT c UNTIL b END) {{ fun st => P st /\ bassn b st }}.
Proof.
intros P b c HhoarePQ HhoareQR.
intros st st' Hr Hp.
remember (REPEAT c UNTIL b END) as rcom eqn : Heqrcom.
inversion Hr; subst.
- inversion H0.
- inversion H1.
- inversion H2.
- inversion H2.
- inversion H2.
- inversion H1.
- inversion H3.
- apply (HhoareQR st'0 st'). inversion H2. subst. assumption.
apply (HhoarePQ st st'0). inversion H2. subst. assumption.
inversion H0; subst.
Abort.
Theorem hoare_repeat' : forall (P Q R : Assertion) (b : bexp) (c : com),
{{ P }} c {{ Q }} ->
{{ Q }} WHILE BNot b DO c END {{ R }} ->
{{ P }} REPEAT c UNTIL b END {{ R }}.
Proof.
intros P Q R b c HhoarePQ HhoareQR.
intros st st' H1 H2.
inversion H1; subst.
apply (HhoareQR st'0 st'). assumption.
apply (HhoarePQ st st'0). assumption. assumption.
Qed.
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ################################################################# *)
(** * Summary *)
(** So far, we've introduced Hoare Logic as a tool for reasoning about
Imp programs. In the reminder of this chapter we'll explore a
systematic way to use Hoare Logic to prove properties about
programs. The rules of Hoare Logic are:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior. *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC]
command, which we studied in the last chapter.
First, we enclose this work in a separate module, and recall the
syntax and big-step semantics of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '\\' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st \\ st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st \\ t_update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st \\ st' -> c2 / st' \\ st'' -> (c1 ;; c2) / st \\ st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st \\ st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(WHILE b1 DO c1 END) / st' \\ st'' ->
(WHILE b1 DO c1 END) / st \\ st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st \\ t_update st X n
where "c1 '/' st '\\' st'" := (ceval c1 st st').
(** The definition of Hoare triples is exactly as before. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st \\ st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
fun st => forall n, Q (t_update st X n).
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
unfold hoare_triple. intros Q X st st' H Hhav.
inversion H; subst. unfold havoc_pre in Hhav.
apply Hhav.
Qed.
End Himp.
(** [] *)
(** $Date: 2017-02-02 10:32:28 -0500 (Thu, 02 Feb 2017) $ *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:01:47 09/18/2015
// Design Name:
// Module Name: boardSynchroniser
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module boardSynchroniser(
input clk,
input synch_en,
input toggle_en,
input [1:0] cnt_n,
input [1:0] cnt_m,
input opMode,
output reg synchroStatus = 1'b0,
inout syncInOut
);
// Synchroniser module for providing n-high-in-m-pulses syncronisation signal to external device, e.g. DC-coupled digitiser.
// For synchronising two FONT5 boards, the module will work in master or slave mode for receiving or transmitting data.
// Eg opMode = 0 (slave), opMode = 1 (master) - eg default to fail-safe (zero) - if need default to master, need to initialise this with the CRs.
reg tog_a = 1'b0, tog_b = 1'b0, toggle = 1'b0;
reg [1:0] ctr = 2'b00;
reg synch = 1'b0;
always @(posedge clk) begin
tog_a <= toggle_en;
tog_b <= tog_a;
toggle <= tog_a & ~tog_b;
if (toggle) begin
ctr <= (ctr == cnt_m) ? 2'b00 : ctr + 1'b1;
if (synch_en) begin
if (ctr == cnt_m) synch <= 1'b1;
else if (ctr == cnt_n) synch <= 1'b0;
else synch <= synch;
end else synch <= 1'b0;
end
synchroStatus <= (opMode) ? synch : syncInOut;
end
assign syncInOut = (opMode) ? synch : 1'bz;
endmodule
|
`define DROP_SFD
module gmii2fifo9 # (
parameter Gap = 4'h2
) (
input sys_rst,
input gmii_rx_clk,
input gmii_rx_dv,
input [7:0] gmii_rxd,
// FIFO
output [8:0] din,
input full,
output reg wr_en,
output wr_clk
);
assign wr_clk = gmii_rx_clk;
parameter STATE_IDLE = 1'b0;
parameter STATE_DATA = 1'b1;
//-----------------------------------
// logic
//-----------------------------------
`ifndef DROP_SFD
reg [7:0] rxd = 8'h00;
reg rxc = 1'b0;
reg [3:0] gap_count = 4'h0;
always @(posedge gmii_rx_clk) begin
if (sys_rst) begin
gap_count <= 4'h0;
wr_en <= 1'b0;
end else begin
wr_en <= 1'b0;
if (gmii_rx_dv == 1'b1) begin
gap_count <= Gap;
rxd[7:0] <= gmii_rxd[7:0];
rxc <= 1'b1;
wr_en <= 1'b1;
end else begin
if (gap_count != 4'h0) begin
rxd[7:0] <= 8'h0;
rxc <= 1'b0;
wr_en <= 1'b1;
gap_count <= gap_count - 4'h1;
end
end
end
end
`else
reg [7:0] rxd = 8'h00;
reg rxc = 1'b0;
reg [3:0] gap_count = 4'h0;
reg [1:0] state;
always @(posedge gmii_rx_clk) begin
if (sys_rst) begin
state <= STATE_IDLE;
gap_count <= 4'h0;
wr_en <= 1'b0;
end else begin
wr_en <= 1'b0;
if (gmii_rx_dv == 1'b1) begin
case (state)
STATE_IDLE: begin
if (gmii_rxd[7:0] == 8'hd5)
state <= STATE_DATA;
end
STATE_DATA: begin
gap_count <= Gap;
rxd[7:0] <= gmii_rxd[7:0];
rxc <= 1'b1;
wr_en <= 1'b1;
end
endcase
end else begin
state <= STATE_IDLE;
if (gap_count != 4'h0) begin
rxd[7:0] <= 8'h0;
rxc <= 1'b0;
wr_en <= 1'b1;
gap_count <= gap_count - 4'h1;
end
end
end
end
`endif
assign din[8:0] = {rxc, rxd[7:0]};
endmodule
|
// system_acl_iface.v
// Generated using ACDS version 14.0 200 at 2015.04.28.12:23:01
`timescale 1 ps / 1 ps
module system_acl_iface (
input wire config_clk_clk, // config_clk.clk
input wire reset_n, // global_reset.reset_n
input wire kernel_pll_refclk_clk, // kernel_pll_refclk.clk
output wire kernel_clk_clk, // kernel_clk.clk
output wire kernel_reset_reset_n, // kernel_reset.reset_n
output wire kernel_clk2x_clk, // kernel_clk2x.clk
output wire kernel_mem0_waitrequest, // kernel_mem0.waitrequest
output wire [255:0] kernel_mem0_readdata, // .readdata
output wire kernel_mem0_readdatavalid, // .readdatavalid
input wire [4:0] kernel_mem0_burstcount, // .burstcount
input wire [255:0] kernel_mem0_writedata, // .writedata
input wire [29:0] kernel_mem0_address, // .address
input wire kernel_mem0_write, // .write
input wire kernel_mem0_read, // .read
input wire [31:0] kernel_mem0_byteenable, // .byteenable
input wire kernel_mem0_debugaccess, // .debugaccess
output wire acl_kernel_clk_kernel_pll_locked_export, // acl_kernel_clk_kernel_pll_locked.export
output wire kernel_clk_snoop_clk, // kernel_clk_snoop.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire peripheral_hps_io_emac1_inst_TX_CLK, // peripheral.hps_io_emac1_inst_TX_CLK
output wire peripheral_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire peripheral_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire peripheral_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire peripheral_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire peripheral_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire peripheral_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire peripheral_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire peripheral_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire peripheral_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire peripheral_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire peripheral_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire peripheral_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire peripheral_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire peripheral_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire peripheral_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire peripheral_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire peripheral_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire peripheral_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire peripheral_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire peripheral_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire peripheral_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire peripheral_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire peripheral_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire peripheral_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
output wire [1:0] acl_internal_memorg_kernel_mode, // acl_internal_memorg_kernel.mode
input wire [0:0] kernel_irq_irq, // kernel_irq.irq
input wire kernel_cra_waitrequest, // kernel_cra.waitrequest
input wire [63:0] kernel_cra_readdata, // .readdata
input wire kernel_cra_readdatavalid, // .readdatavalid
output wire [0:0] kernel_cra_burstcount, // .burstcount
output wire [63:0] kernel_cra_writedata, // .writedata
output wire [29:0] kernel_cra_address, // .address
output wire kernel_cra_write, // .write
output wire kernel_cra_read, // .read
output wire [7:0] kernel_cra_byteenable, // .byteenable
output wire kernel_cra_debugaccess, // .debugaccess
output wire [1:0] kernel_interface_acl_bsp_memorg_host_mode // kernel_interface_acl_bsp_memorg_host.mode
);
wire pll_outclk0_clk; // pll:outclk_0 -> [address_span_extender_kernel:clk, clock_cross_kernel_mem1:m0_clk, hps:f2h_sdram0_clk, mm_interconnect_1:pll_outclk0_clk, mm_interconnect_2:pll_outclk0_clk, rst_controller_001:clk, rst_controller_003:clk]
wire hps_h2f_lw_axi_master_awvalid; // hps:h2f_lw_AWVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_awvalid
wire [2:0] hps_h2f_lw_axi_master_arsize; // hps:h2f_lw_ARSIZE -> mm_interconnect_0:hps_h2f_lw_axi_master_arsize
wire [1:0] hps_h2f_lw_axi_master_arlock; // hps:h2f_lw_ARLOCK -> mm_interconnect_0:hps_h2f_lw_axi_master_arlock
wire [3:0] hps_h2f_lw_axi_master_awcache; // hps:h2f_lw_AWCACHE -> mm_interconnect_0:hps_h2f_lw_axi_master_awcache
wire hps_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_h2f_lw_axi_master_arready -> hps:h2f_lw_ARREADY
wire [11:0] hps_h2f_lw_axi_master_arid; // hps:h2f_lw_ARID -> mm_interconnect_0:hps_h2f_lw_axi_master_arid
wire hps_h2f_lw_axi_master_rready; // hps:h2f_lw_RREADY -> mm_interconnect_0:hps_h2f_lw_axi_master_rready
wire hps_h2f_lw_axi_master_bready; // hps:h2f_lw_BREADY -> mm_interconnect_0:hps_h2f_lw_axi_master_bready
wire [2:0] hps_h2f_lw_axi_master_awsize; // hps:h2f_lw_AWSIZE -> mm_interconnect_0:hps_h2f_lw_axi_master_awsize
wire [2:0] hps_h2f_lw_axi_master_awprot; // hps:h2f_lw_AWPROT -> mm_interconnect_0:hps_h2f_lw_axi_master_awprot
wire hps_h2f_lw_axi_master_arvalid; // hps:h2f_lw_ARVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_arvalid
wire [2:0] hps_h2f_lw_axi_master_arprot; // hps:h2f_lw_ARPROT -> mm_interconnect_0:hps_h2f_lw_axi_master_arprot
wire [11:0] hps_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_h2f_lw_axi_master_bid -> hps:h2f_lw_BID
wire [3:0] hps_h2f_lw_axi_master_arlen; // hps:h2f_lw_ARLEN -> mm_interconnect_0:hps_h2f_lw_axi_master_arlen
wire hps_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_h2f_lw_axi_master_awready -> hps:h2f_lw_AWREADY
wire [11:0] hps_h2f_lw_axi_master_awid; // hps:h2f_lw_AWID -> mm_interconnect_0:hps_h2f_lw_axi_master_awid
wire hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_h2f_lw_axi_master_bvalid -> hps:h2f_lw_BVALID
wire [11:0] hps_h2f_lw_axi_master_wid; // hps:h2f_lw_WID -> mm_interconnect_0:hps_h2f_lw_axi_master_wid
wire [1:0] hps_h2f_lw_axi_master_awlock; // hps:h2f_lw_AWLOCK -> mm_interconnect_0:hps_h2f_lw_axi_master_awlock
wire [1:0] hps_h2f_lw_axi_master_awburst; // hps:h2f_lw_AWBURST -> mm_interconnect_0:hps_h2f_lw_axi_master_awburst
wire [1:0] hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_h2f_lw_axi_master_bresp -> hps:h2f_lw_BRESP
wire [3:0] hps_h2f_lw_axi_master_wstrb; // hps:h2f_lw_WSTRB -> mm_interconnect_0:hps_h2f_lw_axi_master_wstrb
wire hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_h2f_lw_axi_master_rvalid -> hps:h2f_lw_RVALID
wire [31:0] hps_h2f_lw_axi_master_wdata; // hps:h2f_lw_WDATA -> mm_interconnect_0:hps_h2f_lw_axi_master_wdata
wire hps_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_h2f_lw_axi_master_wready -> hps:h2f_lw_WREADY
wire [1:0] hps_h2f_lw_axi_master_arburst; // hps:h2f_lw_ARBURST -> mm_interconnect_0:hps_h2f_lw_axi_master_arburst
wire [31:0] hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_h2f_lw_axi_master_rdata -> hps:h2f_lw_RDATA
wire [20:0] hps_h2f_lw_axi_master_araddr; // hps:h2f_lw_ARADDR -> mm_interconnect_0:hps_h2f_lw_axi_master_araddr
wire [3:0] hps_h2f_lw_axi_master_arcache; // hps:h2f_lw_ARCACHE -> mm_interconnect_0:hps_h2f_lw_axi_master_arcache
wire [3:0] hps_h2f_lw_axi_master_awlen; // hps:h2f_lw_AWLEN -> mm_interconnect_0:hps_h2f_lw_axi_master_awlen
wire [20:0] hps_h2f_lw_axi_master_awaddr; // hps:h2f_lw_AWADDR -> mm_interconnect_0:hps_h2f_lw_axi_master_awaddr
wire [11:0] hps_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_h2f_lw_axi_master_rid -> hps:h2f_lw_RID
wire hps_h2f_lw_axi_master_wvalid; // hps:h2f_lw_WVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_wvalid
wire [1:0] hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_h2f_lw_axi_master_rresp -> hps:h2f_lw_RRESP
wire hps_h2f_lw_axi_master_wlast; // hps:h2f_lw_WLAST -> mm_interconnect_0:hps_h2f_lw_axi_master_wlast
wire hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_h2f_lw_axi_master_rlast -> hps:h2f_lw_RLAST
wire mm_interconnect_0_version_id_s_read; // mm_interconnect_0:version_id_s_read -> version_id:slave_read
wire [31:0] mm_interconnect_0_version_id_s_readdata; // version_id:slave_readdata -> mm_interconnect_0:version_id_s_readdata
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest; // acl_kernel_interface:kernel_cntrl_waitrequest -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_waitrequest
wire [0:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_burstcount -> acl_kernel_interface:kernel_cntrl_burstcount
wire [31:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_writedata -> acl_kernel_interface:kernel_cntrl_writedata
wire [13:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_address -> acl_kernel_interface:kernel_cntrl_address
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_write -> acl_kernel_interface:kernel_cntrl_write
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_read -> acl_kernel_interface:kernel_cntrl_read
wire [31:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata; // acl_kernel_interface:kernel_cntrl_readdata -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_readdata
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_debugaccess -> acl_kernel_interface:kernel_cntrl_debugaccess
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid; // acl_kernel_interface:kernel_cntrl_readdatavalid -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_readdatavalid
wire [3:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_byteenable -> acl_kernel_interface:kernel_cntrl_byteenable
wire mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest; // acl_kernel_clk:ctrl_waitrequest -> mm_interconnect_0:acl_kernel_clk_ctrl_waitrequest
wire [0:0] mm_interconnect_0_acl_kernel_clk_ctrl_burstcount; // mm_interconnect_0:acl_kernel_clk_ctrl_burstcount -> acl_kernel_clk:ctrl_burstcount
wire [31:0] mm_interconnect_0_acl_kernel_clk_ctrl_writedata; // mm_interconnect_0:acl_kernel_clk_ctrl_writedata -> acl_kernel_clk:ctrl_writedata
wire [10:0] mm_interconnect_0_acl_kernel_clk_ctrl_address; // mm_interconnect_0:acl_kernel_clk_ctrl_address -> acl_kernel_clk:ctrl_address
wire mm_interconnect_0_acl_kernel_clk_ctrl_write; // mm_interconnect_0:acl_kernel_clk_ctrl_write -> acl_kernel_clk:ctrl_write
wire mm_interconnect_0_acl_kernel_clk_ctrl_read; // mm_interconnect_0:acl_kernel_clk_ctrl_read -> acl_kernel_clk:ctrl_read
wire [31:0] mm_interconnect_0_acl_kernel_clk_ctrl_readdata; // acl_kernel_clk:ctrl_readdata -> mm_interconnect_0:acl_kernel_clk_ctrl_readdata
wire mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess; // mm_interconnect_0:acl_kernel_clk_ctrl_debugaccess -> acl_kernel_clk:ctrl_debugaccess
wire mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid; // acl_kernel_clk:ctrl_readdatavalid -> mm_interconnect_0:acl_kernel_clk_ctrl_readdatavalid
wire [3:0] mm_interconnect_0_acl_kernel_clk_ctrl_byteenable; // mm_interconnect_0:acl_kernel_clk_ctrl_byteenable -> acl_kernel_clk:ctrl_byteenable
wire [4:0] clock_cross_kernel_mem1_m0_burstcount; // clock_cross_kernel_mem1:m0_burstcount -> mm_interconnect_1:clock_cross_kernel_mem1_m0_burstcount
wire clock_cross_kernel_mem1_m0_waitrequest; // mm_interconnect_1:clock_cross_kernel_mem1_m0_waitrequest -> clock_cross_kernel_mem1:m0_waitrequest
wire [29:0] clock_cross_kernel_mem1_m0_address; // clock_cross_kernel_mem1:m0_address -> mm_interconnect_1:clock_cross_kernel_mem1_m0_address
wire [255:0] clock_cross_kernel_mem1_m0_writedata; // clock_cross_kernel_mem1:m0_writedata -> mm_interconnect_1:clock_cross_kernel_mem1_m0_writedata
wire clock_cross_kernel_mem1_m0_write; // clock_cross_kernel_mem1:m0_write -> mm_interconnect_1:clock_cross_kernel_mem1_m0_write
wire clock_cross_kernel_mem1_m0_read; // clock_cross_kernel_mem1:m0_read -> mm_interconnect_1:clock_cross_kernel_mem1_m0_read
wire [255:0] clock_cross_kernel_mem1_m0_readdata; // mm_interconnect_1:clock_cross_kernel_mem1_m0_readdata -> clock_cross_kernel_mem1:m0_readdata
wire clock_cross_kernel_mem1_m0_debugaccess; // clock_cross_kernel_mem1:m0_debugaccess -> mm_interconnect_1:clock_cross_kernel_mem1_m0_debugaccess
wire [31:0] clock_cross_kernel_mem1_m0_byteenable; // clock_cross_kernel_mem1:m0_byteenable -> mm_interconnect_1:clock_cross_kernel_mem1_m0_byteenable
wire clock_cross_kernel_mem1_m0_readdatavalid; // mm_interconnect_1:clock_cross_kernel_mem1_m0_readdatavalid -> clock_cross_kernel_mem1:m0_readdatavalid
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest; // address_span_extender_kernel:avs_s0_waitrequest -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_waitrequest
wire [4:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_burstcount -> address_span_extender_kernel:avs_s0_burstcount
wire [255:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_writedata -> address_span_extender_kernel:avs_s0_writedata
wire [24:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_address; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_address -> address_span_extender_kernel:avs_s0_address
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_write; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_write -> address_span_extender_kernel:avs_s0_write
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_read; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_read -> address_span_extender_kernel:avs_s0_read
wire [255:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata; // address_span_extender_kernel:avs_s0_readdata -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_readdata
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid; // address_span_extender_kernel:avs_s0_readdatavalid -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_readdatavalid
wire [31:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_byteenable -> address_span_extender_kernel:avs_s0_byteenable
wire [4:0] address_span_extender_kernel_expanded_master_burstcount; // address_span_extender_kernel:avm_m0_burstcount -> mm_interconnect_2:address_span_extender_kernel_expanded_master_burstcount
wire address_span_extender_kernel_expanded_master_waitrequest; // mm_interconnect_2:address_span_extender_kernel_expanded_master_waitrequest -> address_span_extender_kernel:avm_m0_waitrequest
wire [255:0] address_span_extender_kernel_expanded_master_writedata; // address_span_extender_kernel:avm_m0_writedata -> mm_interconnect_2:address_span_extender_kernel_expanded_master_writedata
wire [31:0] address_span_extender_kernel_expanded_master_address; // address_span_extender_kernel:avm_m0_address -> mm_interconnect_2:address_span_extender_kernel_expanded_master_address
wire address_span_extender_kernel_expanded_master_write; // address_span_extender_kernel:avm_m0_write -> mm_interconnect_2:address_span_extender_kernel_expanded_master_write
wire address_span_extender_kernel_expanded_master_read; // address_span_extender_kernel:avm_m0_read -> mm_interconnect_2:address_span_extender_kernel_expanded_master_read
wire [255:0] address_span_extender_kernel_expanded_master_readdata; // mm_interconnect_2:address_span_extender_kernel_expanded_master_readdata -> address_span_extender_kernel:avm_m0_readdata
wire [31:0] address_span_extender_kernel_expanded_master_byteenable; // address_span_extender_kernel:avm_m0_byteenable -> mm_interconnect_2:address_span_extender_kernel_expanded_master_byteenable
wire address_span_extender_kernel_expanded_master_readdatavalid; // mm_interconnect_2:address_span_extender_kernel_expanded_master_readdatavalid -> address_span_extender_kernel:avm_m0_readdatavalid
wire mm_interconnect_2_hps_f2h_sdram0_data_waitrequest; // hps:f2h_sdram0_WAITREQUEST -> mm_interconnect_2:hps_f2h_sdram0_data_waitrequest
wire [7:0] mm_interconnect_2_hps_f2h_sdram0_data_burstcount; // mm_interconnect_2:hps_f2h_sdram0_data_burstcount -> hps:f2h_sdram0_BURSTCOUNT
wire [255:0] mm_interconnect_2_hps_f2h_sdram0_data_writedata; // mm_interconnect_2:hps_f2h_sdram0_data_writedata -> hps:f2h_sdram0_WRITEDATA
wire [26:0] mm_interconnect_2_hps_f2h_sdram0_data_address; // mm_interconnect_2:hps_f2h_sdram0_data_address -> hps:f2h_sdram0_ADDRESS
wire mm_interconnect_2_hps_f2h_sdram0_data_write; // mm_interconnect_2:hps_f2h_sdram0_data_write -> hps:f2h_sdram0_WRITE
wire mm_interconnect_2_hps_f2h_sdram0_data_read; // mm_interconnect_2:hps_f2h_sdram0_data_read -> hps:f2h_sdram0_READ
wire [255:0] mm_interconnect_2_hps_f2h_sdram0_data_readdata; // hps:f2h_sdram0_READDATA -> mm_interconnect_2:hps_f2h_sdram0_data_readdata
wire mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid; // hps:f2h_sdram0_READDATAVALID -> mm_interconnect_2:hps_f2h_sdram0_data_readdatavalid
wire [31:0] mm_interconnect_2_hps_f2h_sdram0_data_byteenable; // mm_interconnect_2:hps_f2h_sdram0_data_byteenable -> hps:f2h_sdram0_BYTEENABLE
wire irq_mapper_receiver0_irq; // acl_kernel_interface:kernel_irq_to_host_irq -> irq_mapper:receiver0_irq
wire [31:0] hps_f2h_irq0_irq; // irq_mapper:sender_irq -> hps:f2h_irq_p0
wire [31:0] hps_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps:f2h_irq_p1
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [acl_kernel_clk:reset_reset_n, acl_kernel_interface:reset_reset_n, acl_kernel_interface:sw_reset_in_reset, mm_interconnect_0:version_id_clk_reset_reset_bridge_in_reset_reset, pll:rst, version_id:resetn]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [address_span_extender_kernel:reset, clock_cross_kernel_mem1:m0_reset, mm_interconnect_1:clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset, mm_interconnect_2:address_span_extender_kernel_reset_reset_bridge_in_reset_reset]
wire acl_kernel_interface_sw_reset_export_reset; // acl_kernel_interface:sw_reset_export_reset_n -> rst_controller_001:reset_in0
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> mm_interconnect_0:hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
wire hps_h2f_reset_reset; // hps:h2f_rst_n -> [rst_controller_002:reset_in0, rst_controller_003:reset_in0]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> mm_interconnect_2:hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset
system_acl_iface_acl_kernel_clk acl_kernel_clk (
.kernel_clk2x_clk (kernel_clk2x_clk), // kernel_clk2x.clk
.pll_refclk_clk (kernel_pll_refclk_clk), // pll_refclk.clk
.ctrl_waitrequest (mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest), // ctrl.waitrequest
.ctrl_readdata (mm_interconnect_0_acl_kernel_clk_ctrl_readdata), // .readdata
.ctrl_readdatavalid (mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.ctrl_burstcount (mm_interconnect_0_acl_kernel_clk_ctrl_burstcount), // .burstcount
.ctrl_writedata (mm_interconnect_0_acl_kernel_clk_ctrl_writedata), // .writedata
.ctrl_address (mm_interconnect_0_acl_kernel_clk_ctrl_address), // .address
.ctrl_write (mm_interconnect_0_acl_kernel_clk_ctrl_write), // .write
.ctrl_read (mm_interconnect_0_acl_kernel_clk_ctrl_read), // .read
.ctrl_byteenable (mm_interconnect_0_acl_kernel_clk_ctrl_byteenable), // .byteenable
.ctrl_debugaccess (mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.kernel_clk_clk (kernel_clk_clk), // kernel_clk.clk
.kernel_pll_locked_export (acl_kernel_clk_kernel_pll_locked_export), // kernel_pll_locked.export
.clk_clk (config_clk_clk), // clk.clk
.reset_reset_n (~rst_controller_reset_out_reset) // reset.reset_n
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (256),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (30),
.BURSTCOUNT_WIDTH (5),
.COMMAND_FIFO_DEPTH (64),
.RESPONSE_FIFO_DEPTH (64),
.MASTER_SYNC_DEPTH (2),
.SLAVE_SYNC_DEPTH (2)
) clock_cross_kernel_mem1 (
.m0_clk (pll_outclk0_clk), // m0_clk.clk
.m0_reset (rst_controller_001_reset_out_reset), // m0_reset.reset
.s0_clk (kernel_clk_clk), // s0_clk.clk
.s0_reset (~kernel_reset_reset_n), // s0_reset.reset
.s0_waitrequest (kernel_mem0_waitrequest), // s0.waitrequest
.s0_readdata (kernel_mem0_readdata), // .readdata
.s0_readdatavalid (kernel_mem0_readdatavalid), // .readdatavalid
.s0_burstcount (kernel_mem0_burstcount), // .burstcount
.s0_writedata (kernel_mem0_writedata), // .writedata
.s0_address (kernel_mem0_address), // .address
.s0_write (kernel_mem0_write), // .write
.s0_read (kernel_mem0_read), // .read
.s0_byteenable (kernel_mem0_byteenable), // .byteenable
.s0_debugaccess (kernel_mem0_debugaccess), // .debugaccess
.m0_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.m0_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.m0_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.m0_address (clock_cross_kernel_mem1_m0_address), // .address
.m0_write (clock_cross_kernel_mem1_m0_write), // .write
.m0_read (clock_cross_kernel_mem1_m0_read), // .read
.m0_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.m0_debugaccess (clock_cross_kernel_mem1_m0_debugaccess) // .debugaccess
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1597521440)
) version_id (
.clk (config_clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_0_version_id_s_read), // s.read
.slave_readdata (mm_interconnect_0_version_id_s_readdata) // .readdata
);
system_acl_iface_hps #(
.F2S_Width (0),
.S2F_Width (0)
) hps (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (peripheral_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (peripheral_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (peripheral_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (peripheral_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (peripheral_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (peripheral_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (peripheral_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (peripheral_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (peripheral_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (peripheral_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (peripheral_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (peripheral_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (peripheral_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (peripheral_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (peripheral_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (peripheral_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (peripheral_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (peripheral_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (peripheral_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (peripheral_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_uart0_inst_RX (peripheral_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (peripheral_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (peripheral_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (peripheral_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO53 (peripheral_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (pll_outclk0_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (mm_interconnect_2_hps_f2h_sdram0_data_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (mm_interconnect_2_hps_f2h_sdram0_data_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (mm_interconnect_2_hps_f2h_sdram0_data_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (mm_interconnect_2_hps_f2h_sdram0_data_readdata), // .readdata
.f2h_sdram0_READDATAVALID (mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (mm_interconnect_2_hps_f2h_sdram0_data_read), // .read
.f2h_sdram0_WRITEDATA (mm_interconnect_2_hps_f2h_sdram0_data_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (mm_interconnect_2_hps_f2h_sdram0_data_byteenable), // .byteenable
.f2h_sdram0_WRITE (mm_interconnect_2_hps_f2h_sdram0_data_write), // .write
.h2f_lw_axi_clk (config_clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_f2h_irq1_irq) // f2h_irq1.irq
);
system_acl_iface_acl_kernel_interface acl_kernel_interface (
.clk_clk (config_clk_clk), // clk.clk
.reset_reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.kernel_cntrl_waitrequest (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest), // kernel_cntrl.waitrequest
.kernel_cntrl_readdata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.kernel_cntrl_readdatavalid (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.kernel_cntrl_burstcount (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.kernel_cntrl_writedata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.kernel_cntrl_address (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address), // .address
.kernel_cntrl_write (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write), // .write
.kernel_cntrl_read (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read), // .read
.kernel_cntrl_byteenable (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.kernel_cntrl_debugaccess (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.kernel_cra_waitrequest (kernel_cra_waitrequest), // kernel_cra.waitrequest
.kernel_cra_readdata (kernel_cra_readdata), // .readdata
.kernel_cra_readdatavalid (kernel_cra_readdatavalid), // .readdatavalid
.kernel_cra_burstcount (kernel_cra_burstcount), // .burstcount
.kernel_cra_writedata (kernel_cra_writedata), // .writedata
.kernel_cra_address (kernel_cra_address), // .address
.kernel_cra_write (kernel_cra_write), // .write
.kernel_cra_read (kernel_cra_read), // .read
.kernel_cra_byteenable (kernel_cra_byteenable), // .byteenable
.kernel_cra_debugaccess (kernel_cra_debugaccess), // .debugaccess
.kernel_irq_from_kernel_irq (kernel_irq_irq), // kernel_irq_from_kernel.irq
.acl_bsp_memorg_kernel_mode (acl_internal_memorg_kernel_mode), // acl_bsp_memorg_kernel.mode
.acl_bsp_memorg_host_mode (kernel_interface_acl_bsp_memorg_host_mode), // acl_bsp_memorg_host.mode
.sw_reset_in_reset (rst_controller_reset_out_reset), // sw_reset_in.reset
.kernel_clk_clk (kernel_clk_clk), // kernel_clk.clk
.sw_reset_export_reset_n (acl_kernel_interface_sw_reset_export_reset), // sw_reset_export.reset_n
.kernel_reset_reset_n (kernel_reset_reset_n), // kernel_reset.reset_n
.kernel_irq_to_host_irq (irq_mapper_receiver0_irq) // kernel_irq_to_host.irq
);
system_acl_iface_pll pll (
.refclk (config_clk_clk), // refclk.clk
.rst (rst_controller_reset_out_reset), // reset.reset
.outclk_0 (pll_outclk0_clk), // outclk0.clk
.locked () // (terminated)
);
altera_address_span_extender #(
.DATA_WIDTH (256),
.BYTEENABLE_WIDTH (32),
.MASTER_ADDRESS_WIDTH (32),
.SLAVE_ADDRESS_WIDTH (25),
.SLAVE_ADDRESS_SHIFT (5),
.BURSTCOUNT_WIDTH (5),
.CNTL_ADDRESS_WIDTH (1),
.SUB_WINDOW_COUNT (1),
.MASTER_ADDRESS_DEF (64'b0000000000000000000000000000000000000000000000000000000000000000)
) address_span_extender_kernel (
.clk (pll_outclk0_clk), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_1_address_span_extender_kernel_windowed_slave_address), // windowed_slave.address
.avs_s0_read (mm_interconnect_1_address_span_extender_kernel_windowed_slave_read), // .read
.avs_s0_readdata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata), // .readdata
.avs_s0_write (mm_interconnect_1_address_span_extender_kernel_windowed_slave_write), // .write
.avs_s0_writedata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata), // .writedata
.avs_s0_readdatavalid (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.avs_s0_waitrequest (mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest), // .waitrequest
.avs_s0_byteenable (mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.avs_s0_burstcount (mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.avm_m0_address (address_span_extender_kernel_expanded_master_address), // expanded_master.address
.avm_m0_read (address_span_extender_kernel_expanded_master_read), // .read
.avm_m0_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.avm_m0_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.avm_m0_write (address_span_extender_kernel_expanded_master_write), // .write
.avm_m0_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.avm_m0_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.avm_m0_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.avm_m0_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.avs_cntl_address (1'b0), // (terminated)
.avs_cntl_read (1'b0), // (terminated)
.avs_cntl_readdata (), // (terminated)
.avs_cntl_write (1'b0), // (terminated)
.avs_cntl_writedata (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.avs_cntl_byteenable (8'b00000000) // (terminated)
);
system_acl_iface_mm_interconnect_0 mm_interconnect_0 (
.hps_h2f_lw_axi_master_awid (hps_h2f_lw_axi_master_awid), // hps_h2f_lw_axi_master.awid
.hps_h2f_lw_axi_master_awaddr (hps_h2f_lw_axi_master_awaddr), // .awaddr
.hps_h2f_lw_axi_master_awlen (hps_h2f_lw_axi_master_awlen), // .awlen
.hps_h2f_lw_axi_master_awsize (hps_h2f_lw_axi_master_awsize), // .awsize
.hps_h2f_lw_axi_master_awburst (hps_h2f_lw_axi_master_awburst), // .awburst
.hps_h2f_lw_axi_master_awlock (hps_h2f_lw_axi_master_awlock), // .awlock
.hps_h2f_lw_axi_master_awcache (hps_h2f_lw_axi_master_awcache), // .awcache
.hps_h2f_lw_axi_master_awprot (hps_h2f_lw_axi_master_awprot), // .awprot
.hps_h2f_lw_axi_master_awvalid (hps_h2f_lw_axi_master_awvalid), // .awvalid
.hps_h2f_lw_axi_master_awready (hps_h2f_lw_axi_master_awready), // .awready
.hps_h2f_lw_axi_master_wid (hps_h2f_lw_axi_master_wid), // .wid
.hps_h2f_lw_axi_master_wdata (hps_h2f_lw_axi_master_wdata), // .wdata
.hps_h2f_lw_axi_master_wstrb (hps_h2f_lw_axi_master_wstrb), // .wstrb
.hps_h2f_lw_axi_master_wlast (hps_h2f_lw_axi_master_wlast), // .wlast
.hps_h2f_lw_axi_master_wvalid (hps_h2f_lw_axi_master_wvalid), // .wvalid
.hps_h2f_lw_axi_master_wready (hps_h2f_lw_axi_master_wready), // .wready
.hps_h2f_lw_axi_master_bid (hps_h2f_lw_axi_master_bid), // .bid
.hps_h2f_lw_axi_master_bresp (hps_h2f_lw_axi_master_bresp), // .bresp
.hps_h2f_lw_axi_master_bvalid (hps_h2f_lw_axi_master_bvalid), // .bvalid
.hps_h2f_lw_axi_master_bready (hps_h2f_lw_axi_master_bready), // .bready
.hps_h2f_lw_axi_master_arid (hps_h2f_lw_axi_master_arid), // .arid
.hps_h2f_lw_axi_master_araddr (hps_h2f_lw_axi_master_araddr), // .araddr
.hps_h2f_lw_axi_master_arlen (hps_h2f_lw_axi_master_arlen), // .arlen
.hps_h2f_lw_axi_master_arsize (hps_h2f_lw_axi_master_arsize), // .arsize
.hps_h2f_lw_axi_master_arburst (hps_h2f_lw_axi_master_arburst), // .arburst
.hps_h2f_lw_axi_master_arlock (hps_h2f_lw_axi_master_arlock), // .arlock
.hps_h2f_lw_axi_master_arcache (hps_h2f_lw_axi_master_arcache), // .arcache
.hps_h2f_lw_axi_master_arprot (hps_h2f_lw_axi_master_arprot), // .arprot
.hps_h2f_lw_axi_master_arvalid (hps_h2f_lw_axi_master_arvalid), // .arvalid
.hps_h2f_lw_axi_master_arready (hps_h2f_lw_axi_master_arready), // .arready
.hps_h2f_lw_axi_master_rid (hps_h2f_lw_axi_master_rid), // .rid
.hps_h2f_lw_axi_master_rdata (hps_h2f_lw_axi_master_rdata), // .rdata
.hps_h2f_lw_axi_master_rresp (hps_h2f_lw_axi_master_rresp), // .rresp
.hps_h2f_lw_axi_master_rlast (hps_h2f_lw_axi_master_rlast), // .rlast
.hps_h2f_lw_axi_master_rvalid (hps_h2f_lw_axi_master_rvalid), // .rvalid
.hps_h2f_lw_axi_master_rready (hps_h2f_lw_axi_master_rready), // .rready
.config_clk_out_clk_clk (config_clk_clk), // config_clk_out_clk.clk
.hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.version_id_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // version_id_clk_reset_reset_bridge_in_reset.reset
.acl_kernel_clk_ctrl_address (mm_interconnect_0_acl_kernel_clk_ctrl_address), // acl_kernel_clk_ctrl.address
.acl_kernel_clk_ctrl_write (mm_interconnect_0_acl_kernel_clk_ctrl_write), // .write
.acl_kernel_clk_ctrl_read (mm_interconnect_0_acl_kernel_clk_ctrl_read), // .read
.acl_kernel_clk_ctrl_readdata (mm_interconnect_0_acl_kernel_clk_ctrl_readdata), // .readdata
.acl_kernel_clk_ctrl_writedata (mm_interconnect_0_acl_kernel_clk_ctrl_writedata), // .writedata
.acl_kernel_clk_ctrl_burstcount (mm_interconnect_0_acl_kernel_clk_ctrl_burstcount), // .burstcount
.acl_kernel_clk_ctrl_byteenable (mm_interconnect_0_acl_kernel_clk_ctrl_byteenable), // .byteenable
.acl_kernel_clk_ctrl_readdatavalid (mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.acl_kernel_clk_ctrl_waitrequest (mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest), // .waitrequest
.acl_kernel_clk_ctrl_debugaccess (mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.acl_kernel_interface_kernel_cntrl_address (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address), // acl_kernel_interface_kernel_cntrl.address
.acl_kernel_interface_kernel_cntrl_write (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write), // .write
.acl_kernel_interface_kernel_cntrl_read (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read), // .read
.acl_kernel_interface_kernel_cntrl_readdata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.acl_kernel_interface_kernel_cntrl_writedata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.acl_kernel_interface_kernel_cntrl_burstcount (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.acl_kernel_interface_kernel_cntrl_byteenable (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.acl_kernel_interface_kernel_cntrl_readdatavalid (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.acl_kernel_interface_kernel_cntrl_waitrequest (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest), // .waitrequest
.acl_kernel_interface_kernel_cntrl_debugaccess (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.version_id_s_read (mm_interconnect_0_version_id_s_read), // version_id_s.read
.version_id_s_readdata (mm_interconnect_0_version_id_s_readdata) // .readdata
);
system_acl_iface_mm_interconnect_1 mm_interconnect_1 (
.pll_outclk0_clk (pll_outclk0_clk), // pll_outclk0.clk
.clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset.reset
.clock_cross_kernel_mem1_m0_address (clock_cross_kernel_mem1_m0_address), // clock_cross_kernel_mem1_m0.address
.clock_cross_kernel_mem1_m0_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // .waitrequest
.clock_cross_kernel_mem1_m0_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.clock_cross_kernel_mem1_m0_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.clock_cross_kernel_mem1_m0_read (clock_cross_kernel_mem1_m0_read), // .read
.clock_cross_kernel_mem1_m0_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.clock_cross_kernel_mem1_m0_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.clock_cross_kernel_mem1_m0_write (clock_cross_kernel_mem1_m0_write), // .write
.clock_cross_kernel_mem1_m0_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.clock_cross_kernel_mem1_m0_debugaccess (clock_cross_kernel_mem1_m0_debugaccess), // .debugaccess
.address_span_extender_kernel_windowed_slave_address (mm_interconnect_1_address_span_extender_kernel_windowed_slave_address), // address_span_extender_kernel_windowed_slave.address
.address_span_extender_kernel_windowed_slave_write (mm_interconnect_1_address_span_extender_kernel_windowed_slave_write), // .write
.address_span_extender_kernel_windowed_slave_read (mm_interconnect_1_address_span_extender_kernel_windowed_slave_read), // .read
.address_span_extender_kernel_windowed_slave_readdata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata), // .readdata
.address_span_extender_kernel_windowed_slave_writedata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata), // .writedata
.address_span_extender_kernel_windowed_slave_burstcount (mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.address_span_extender_kernel_windowed_slave_byteenable (mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.address_span_extender_kernel_windowed_slave_readdatavalid (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.address_span_extender_kernel_windowed_slave_waitrequest (mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest) // .waitrequest
);
system_acl_iface_mm_interconnect_2 mm_interconnect_2 (
.pll_outclk0_clk (pll_outclk0_clk), // pll_outclk0.clk
.address_span_extender_kernel_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_kernel_reset_reset_bridge_in_reset.reset
.hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
.address_span_extender_kernel_expanded_master_address (address_span_extender_kernel_expanded_master_address), // address_span_extender_kernel_expanded_master.address
.address_span_extender_kernel_expanded_master_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.address_span_extender_kernel_expanded_master_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.address_span_extender_kernel_expanded_master_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.address_span_extender_kernel_expanded_master_read (address_span_extender_kernel_expanded_master_read), // .read
.address_span_extender_kernel_expanded_master_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.address_span_extender_kernel_expanded_master_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.address_span_extender_kernel_expanded_master_write (address_span_extender_kernel_expanded_master_write), // .write
.address_span_extender_kernel_expanded_master_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.hps_f2h_sdram0_data_address (mm_interconnect_2_hps_f2h_sdram0_data_address), // hps_f2h_sdram0_data.address
.hps_f2h_sdram0_data_write (mm_interconnect_2_hps_f2h_sdram0_data_write), // .write
.hps_f2h_sdram0_data_read (mm_interconnect_2_hps_f2h_sdram0_data_read), // .read
.hps_f2h_sdram0_data_readdata (mm_interconnect_2_hps_f2h_sdram0_data_readdata), // .readdata
.hps_f2h_sdram0_data_writedata (mm_interconnect_2_hps_f2h_sdram0_data_writedata), // .writedata
.hps_f2h_sdram0_data_burstcount (mm_interconnect_2_hps_f2h_sdram0_data_burstcount), // .burstcount
.hps_f2h_sdram0_data_byteenable (mm_interconnect_2_hps_f2h_sdram0_data_byteenable), // .byteenable
.hps_f2h_sdram0_data_readdatavalid (mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.hps_f2h_sdram0_data_waitrequest (mm_interconnect_2_hps_f2h_sdram0_data_waitrequest) // .waitrequest
);
system_acl_iface_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (hps_f2h_irq0_irq) // sender.irq
);
system_acl_iface_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_f2h_irq1_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_n), // reset_in0.reset
.clk (config_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~acl_kernel_interface_sw_reset_export_reset), // reset_in0.reset
.clk (pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~hps_h2f_reset_reset), // reset_in0.reset
.clk (config_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
assign kernel_clk_snoop_clk = kernel_clk_clk;
endmodule
|
// ECE 429
module memory(clock, address, data_in, access_size, rw, enable, busy, data_out);
parameter data_width = 32;
parameter address_width = 32;
parameter depth = 1048576;
// -1 for 0 based indexed
parameter bytes_in_word = 4-1;
parameter bits_in_bytes = 8-1;
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
input clock;
input [address_width-1:0] address;
input [data_width-1:0] data_in;
input [1:0] access_size;
input rw;
input enable;
// Output Ports
//FIXME: change to output port.
output reg busy;
output reg [data_width-1:0] data_out;
// Create a 1MB deep memory of 8-bits (1 byte) width
reg [7:0] mem[0:depth]; // should be [7:0] since its byte addressible memory
reg [7:0] data;
reg [7:0] byte[3:0];
reg [31:0] global_cur_addr;
reg [31:0] global_cur_addr_write;
reg [31:0] global_cur_addr_read;
integer cyc_ctr = 0;
integer cyc_ctr_write = 0;
integer i = 0;
integer words_written = 0;
integer words_read = 0;
integer write_total_words = 0;
integer read_total_words = 0;
integer fd;
integer status_read, status_write;
reg [31:0] fd_in;
reg [31:0] str;
always @(posedge clock, data_in, rw)
begin : WRITE
// rw = 1
if ((!rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(write_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
mem[address-start_addr+3] <= data_in[7:0];
mem[address-start_addr+2] <= data_in[15:8];
mem[address-start_addr+1] <= data_in[23:16];
mem[address-start_addr] <= data_in[31:24];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
write_total_words = 4;
// skip over the already written bytes
global_cur_addr_write = address-start_addr;
if (words_written < 4) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_written = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
write_total_words = 8;
global_cur_addr_write = address-start_addr;
if (words_written < 8) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
// 11: 16 words
else if (access_size == 2'b1_1) begin
write_total_words = 16;
global_cur_addr_write = address-start_addr;
if (words_written < 16) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
end
end
/*
00: 1 word (4-bytes)
01: 4 words (16-bytes)
10: 8 words (32-bytes)
11: 16 words (64-bytes)
*/
always @(posedge clock, address, rw)
begin : READ
if ((rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(read_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
// read 4 bytes at max in 1 clock cycle.
//assign data_out = {mem[address-start_addr], mem[address-start_addr+1], mem[address-start_addr+2], mem[address-start_addr+3]};
data_out[7:0] <= mem[address-start_addr+3];
data_out[15:8] <= mem[address-start_addr+2];
data_out[23:16] <= mem[address-start_addr+1];
data_out[31:24] <= mem[address-start_addr];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
read_total_words = 4;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 4) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
read_total_words = 8;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 8) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
// 11: 16 words
end else if (access_size == 2'b1_1) begin
read_total_words = 16;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 16) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
end
end
endmodule
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code for ZTEX USB-FPGA Module 1.15b (one double hash pipe)
Copyright (C) 2012 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
compilation warnings:
WARNING:Timing:3159 - The DCM, dcm0, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be constrained using FROM/TO constraints.
(answer)
This warning is valid and is intended to deliver more information that a user may not be aware of. The warning serves to alert the user that when the DCM is in the Free Running Oscillator mode (DCM_CLKGEN) there is NO phase relationship between the CLKIN and CLKOUT ports of the DCM.
The warning message also lists the following attributes that are not documented.
DFS_OSCILLATOR_MODE / PHASE_FREQ_LOCK
These settings are automatically enabled when the DCM is in the Free Running Oscillator mode so they are not accessible by the user but are controlled by the implementation tools.
The warning and added settings can be ignored as long as the design is able to handle the lack of phase relationship on between the input clock and output clock of the DCM in Free Running Oscillator mode. For more information, please visit the Spartan-6 FPGA Clocking Resources User Guide (UG382):
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf
WARNING:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
(command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1
# try 46MHz for TIMESPEC in ucf
WARNING:Xst:647 - Input <data3<127:124>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
!*/
module ztex_ufm1_15y1 (fxclk_in, reset, select, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, select, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
// Configure cores here since using `ifdef rather than generate (lazy)
//`define PROTOCOL80 // Select 80 or 76 byte protocol (NB use 76 for current cgminer)
localparam LOCAL_MINERS = 1; // One or two cores (configures ADDRBITS automatically)
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS); // Automatically selects largest RAM that will fit LX150
localparam SBITS = 8; // Shift data path width
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1 = 0, reset_buf = 0, reset_buf_d = 0, clk_reset_buf = 1, pll_stop_buf = 1, select_buf = 0;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [3:0] wr_delay;
reg [127:0] outbuf;
reg [7:0] read_buf, write_buf;
reg [31:0] golden_nonce_a = 32'd0, golden_nonce_b = 32'd0;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce_1, hash_1;
wire [31:0] golden_nonce_2, hash_2;
wire [31:0] golden_nonce, nonce_a, hash_a;
wire gn_match_1, gn_match_2;
BUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
DCM_CLKGEN #(
.CLKFX_DIVIDE(4), /* 1mhz */
.CLKFX_MULTIPLY(8), /* 150mhz 166mhz */
.CLKFXDV_DIVIDE(2), /* n/a */
.CLKIN_PERIOD(26.8)
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset_buf)
);
PLL_BASE #(
.BANDWIDTH("LOW"),
// 6.7ns
// .CLKFBOUT_MULT(8),
// .CLKOUT0_DIVIDE(2),
// ~ 400mhz
.CLKFBOUT_MULT(16),
.CLKOUT0_DIVIDE(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.CLKIN_PERIOD(26.8),
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
assign write = select ? write_buf : 8'bz; // This actually does tristate the outputs
assign pll_reset = pll_stop_buf | ~dcm_locked | clk_reset_buf | dcm_status[2];
`ifdef SIM
// Test hash - final hash at 672,780ns
`ifdef PROTOCOL80
// 80 byte protocol includes nonce
reg [639:0] inbuf_tmp = {
128'h0000318f7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`else
// 76 byte protocol excludes nonce
reg [607:0] inbuf_tmp = {
96'h7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`endif
`else // SIM
`ifdef PROTOCOL80
reg [639:0] inbuf_tmp;
`else
reg [639:0] inbuf_tmp;
`endif
`endif // SIM
`ifdef PROTOCOL80
reg [639:0] inbuf; // 80 byte protocol
`else
reg [607:0] inbuf; // 76 byte protocol
`endif
wire [31:0] mod_target = 32'h000007ff; // Hard coded for diff=32
wire [255:0] data1 = inbuf[255:0];
wire [255:0] data2 = inbuf[511:256];
`ifdef PROTOCOL80
wire [127:0] data3 = inbuf[639:512];
`else
`ifdef SIM
wire [127:0] data3 = { 32'h0000318f, inbuf[607:512] };
`else
wire [127:0] data3 = { 32'd0, inbuf[607:512] };
`endif
`endif
// Generate loadnonce strobe for new work (NB this initiates a full engine reset)
reg loadnonce = 1'b0; // Strobe generated loading work
reg loadnonce_d = 1'b0; // Delay by one since extra register stage inbuf
// NB For now using same clk for both P and S
wire [31:0] nonce_out_1;
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
// Single core
assign nonce_a = nonce_out_1;
assign hash_a = hash_1;
assign gn_match = gn_match_1;
assign golden_nonce = golden_nonce_1;
always @ (posedge clk)
begin
loadnonce <= 1'b0; // For pbkdfengine
loadnonce_d <= loadnonce; // Delay by one since extra register stage inbuf
// KRAMBLE not sure I understand this, it does not seem to be conventional clock-crossing as the comparison is the wrong
// end of the shift register, so perhaps its a de-bounce on the rd_clk (which is sort of clock-crossing too) ??
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) && select_buf )
begin
`ifdef PROTOCOL80
inbuf_tmp[639:632] <= read_buf;
inbuf_tmp[631:0] <= inbuf_tmp[639:8];
`else
inbuf_tmp[607:600] <= read_buf;
inbuf_tmp[599:0] <= inbuf_tmp[607:8];
`endif
// Nonce will be loaded (or reset to 0 in 76 byte protocol) every byte since there is no signal
// that indicates when work is completely loaded (this means hashes generated during loading
// are invalid, so we also reset golden_nonce_a/b below)
loadnonce <= 1'b1; // For pbkdfengine (single clock cycle strobe)
end
inbuf <= inbuf_tmp; // due to TIG's
if ( wr_start_b1 )
begin
wr_delay <= 4'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[3:1] <= wr_delay[2:0];
end
if ( ! wr_delay[3] )
begin
outbuf <= { golden_nonce_b, hash_a, nonce_a, golden_nonce_a };
end else
begin
// KRAMBLE see note above for rd_clk
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[119:0] <= outbuf[127:8];
end
if ( reset_buf | loadnonce ) // Also reset on loadnonce since hashes are invalid
begin
golden_nonce_a <= 32'd0;
golden_nonce_b <= 32'd0;
end else if ( gn_match )
begin
golden_nonce_b <= golden_nonce_a;
golden_nonce_a <= golden_nonce;
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
select_buf <= select;
if ( select )
begin
reset_buf <= reset;
end
reset_buf_d <= reset_buf;
if (reset_buf_d & ~reset_buf) // Executes on trailing edge of reset
begin
end
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen & select;
if ( select )
begin
clk_reset_buf <= clk_reset;
pll_stop_buf <= pll_stop;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Pixel Cache Top Level
// File : ded_pix_cache.v
// Author : Frank Bruno
// Created : 08-Jul-2008
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// ded_pix_cache is used to handle all memory requests for the 2D/3D pipeline
// Requests from Lines and triangles as well as BLTs all pass through this
// Block.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_pix_cache
#(parameter BYTES = 4)
(
input de_clk, // Drawing engine clock
input mc_clk, // memory controller clock
input de_rstn, // reset input bit_t
input [27:0] dorg_2, // Destination origin.
input [27:0] sorg_2, // Source origin.
input [27:0] zorg_2, // Z origin.
input [11:0] dptch_2, // destination pitch.
input [11:0] sptch_2, // source pitch.
input [11:0] zptch_2, // Z pitch.
input ld_wcnt,
input [3:0] fx_1, // lower nibble of the alu fx
input rmw,
// Needed by Pixel cache
input ps8_2, // pixel size equals eight
input ps16_2, // pixel size equals sixteen
input ps32_2, // pixel size equals sixteen
input [31:0] fore_2, // Foreground Color
input [31:0] back_2, // Background Color
input solid_2, // Solid indicator
input dr_trnsp_2, // Transparent indicator
input dx_pc_ld, // Load a pixel from execution
input dx_clip, // Line is being clipped
input [15:0] dx_real_dstx, // X destination
input [15:0] dx_real_dsty, // Y destination
input dx_pc_msk_last,// Don;t display last pixel
input dx_fg_bgn, // Foreground or background color
input dx_last_pixel, // We are receiving the last pix
// 3D Interface.
input valid_3d, // Valid pixel from the 3D engine.
input fg_bgn_3d, // Forground background from 3D engine.
input [15:0] x_out_3d, // X destination
input [15:0] y_out_3d, // Y destination
input pc_msk_last_3d,// Don;t display last pixel
input pc_last_3d, // Last pixel from the 3D engine.
input [31:0] pixel_3d, // 3D Pixel.
input [31:0] z_3d, // 3D Pixel.
input [7:0] alpha_3d, // 3D Alpha.
input [2:0] z_op, // Z operation
input z_en, // Z enabled
input z_ro, // Do not update Z
input active_3d_2,// #D is active.
// Needed by BLT
input de_pc_pop, // Pop from PC
input mc_popen, // increment from MC
input [15:0] srcx, // Source X address.
input [15:0] srcy, // Source Y address.
input [15:0] dstx, // Destination X address.
input [15:0] dsty, // Destination Y address.
input imem_rd, // Internal Memory read.
input dx_mem_req, // Internal Memory request.
input [3:0] mask_2,
input [1:0] stpl_2,
input [1:0] dr_apat_2,
input [1:0] dr_clp_2,
input rad_flg_2,
input [2:0] strt_wrd_2,
input [3:0] strt_byt_2,
input [2:0] strt_bit_2,
input [1:0] ps_2,
input [3:0] bsrcr_2, // Source blending function.
input [2:0] bdstr_2, // Destination blending fx
input blend_en_2, // Blending enable.
input [1:0] blend_reg_en_2,// Blending register enable.
input [7:0] bsrc_alpha_2, // Source alpha data.
input [7:0] bdst_alpha_2, // Destination alpha data.
input [3:0] rop_2, // Raster operation.
input [31:0] kcol_2, // Key Color.
input [2:0] key_ctrl_2, // Key control.
input [6:0] lft_enc_2,
input [6:0] rht_enc_2,
input [11:0] clp_min_2, // left clipping pointer
input [11:0] clp_max_2, // right clipping pointer
input [3:0] cmin_enc_2,
input [3:0] cmax_enc_2,
input y_clip_2,
input sol_2,
input eol_2,
input rst_wad_flg_2,
input [2:0] frst8_2,
output reg mc_acken,
output reg [(BYTES*8)-1:0] px_col, // pixel color select
output reg [BYTES-1:0] px_msk_color, // pixel mask
output reg [(BYTES*4)-1:0] px_a, // alpha out
output reg [31:0] de_mc_address,
output reg de_mc_read,
output reg de_mc_rmw,
output reg [3:0] de_mc_wcnt,
output reg pc_dirty, // data left in the pixel cache.
output reg pc_pending, // Pixel cache access pending
output reg pc_busy, // Pixel cache is busy
output reg pc_busy_3d, // Pixel cache is busy
output de_pc_empty,
output reg [31:0] fore_4, // foreground register output
output reg [31:0] back_4, // foreground register output.
output reg blt_actv_4,
output reg trnsp_4, solid_4,
output reg ps8_4,
output reg ps16_4,
output reg ps32_4,
output reg [1:0] stpl_4,
output reg [1:0] clp_4,
output reg line_actv_4,
output reg [1:0] apat_4,
output reg [3:0] mask_4,
output rad_flg_3,
output [2:0] strt_wrd_3,
output [3:0] strt_byt_3,
output [2:0] strt_bit_3,
output reg [2:0] strt_wrd_4,
output reg [3:0] strt_byt_4,
output reg [2:0] strt_bit_4,
output reg [1:0] ps_4,
output reg [3:0] bsrcr_4, // Source blending function.
output reg [2:0] bdstr_4, // Destination blending function.
output reg blend_en_4, // Blending enable.
output reg [1:0] blend_reg_en_4, // Blending enable.
output reg [7:0] bsrc_alpha_4, // Source alpha data.
output reg [7:0] bdst_alpha_4, // Destination alpha data.
output reg [3:0] rop_4, // Raster operation
output reg [31:0] kcol_4, // Key Color.
output reg [2:0] key_ctrl_4, // Key control.
output reg [6:0] lft_enc_4,
output reg [6:0] rht_enc_4,
output reg [11:0] clp_min_4, // left clipping pointer
output reg [11:0] clp_max_4, // right clipping pointer
output reg [3:0] cmin_enc_4,
output reg [3:0] cmax_enc_4,
output reg [13:0] x_bus_4, // bus from execution X dest counter
output reg y_clip_4,
output sol_4,
output reg eol_4,
output rst_wad_flg_3,
output mc_read_3,
output sol_3,
output reg [2:0] frst8_4,
output reg pc_empty,
output reg pc_last,
output reg [2:0] z_op_4, // Z operation
output reg z_en_4, // Z enabled
output reg z_ro_4, // Do not update Z
output reg [31:0] z_address_4, // Z Address.
output reg [(BYTES*8)-1:0] z_out // Z value to framebuffer
);
reg push_last;
reg [2:0] sol_4_int;
reg [31:0] pix_color; // Color into output fifo
reg [31:0] pix_z; // Color into output fifo
reg [7:0] pix_a; // Color into output fifo
reg push; // push into output fifo
reg [15:0] in_x, in_y; // X,Y into the output fifo
reg [1:0] depth; // encoded depth into fifo
reg [127:0] int_col;
reg [15:0] int_mask;
reg [3:0] wcnt;
reg [15:0] y_pos;
reg [13:0] x_pos;
reg [27:0] org_2;
reg [11:0] ptch_2;
reg same_page; // we are writing to the same mask
reg startup;
reg push_previous;
reg pipe_push_last;
reg fifo_rmw;
reg fifo_cmd;
reg [15:0] fifo_mask;
reg [127:0] fifo_color;
reg dx_delayed;
reg [31:0] fifo_kcol;
reg [1:0] fifo_ps;
reg [3:0] fifo_bsrcr;
reg [2:0] fifo_bdstr;
reg fifo_blend_en;
reg [1:0] fifo_blend_reg_en;
reg [7:0] fifo_bsrc_alpha;
reg [7:0] fifo_bdst_alpha;
reg [3:0] fifo_rop;
reg [2:0] fifo_key_ctrl;
reg [27:0] fifo_junk;
reg data_pending;
reg [31:0] p_mult, int_add;
reg [31:0] z_mult, int_zadd;
reg fifo_push;
reg [270:0] fifo_data; // Muxed data into fifo
reg [128:0] fifo_adata; // Muxed data into fifo
reg push_d;
reg [1:0] last_pixel_pipe;
reg [31:0] fifo_address;
reg [31:0] z_address;
reg [127:0] z_buffer, int_z;
reg [63:0] a_buffer;
reg [165:0] fifo_z;
reg hold_push_last;
reg hold_3d;
reg active_3d_del;
wire [6:0] wrusedw;
wire fifo_empty;
wire [270:0] fifo_dout; // Muxed data into fifo
wire [165:0] fifo_zout; // Muxed data into fifo
wire fifo_dout_extra;
wire [127:0] a_dout;
// always @(posedge de_clk) begin
// if(valid_3d && (x_out_3d == 16'd181) && (y_out_3d == 16'd111)) begin
// #1000 $stop;
// end
// end
// Combine 2D and 3D signals (jmacleod).
wire pc_ld = dx_pc_ld | valid_3d; // Valid pixel
wire fg_bgn = (~valid_3d & dx_fg_bgn) | (valid_3d & fg_bgn_3d); // Forground background Select.
wire last_pixel = (~valid_3d & dx_last_pixel) | (valid_3d & pc_last_3d); // Last pixel
wire [15:0] real_dstx = ({16{~valid_3d}} & dx_real_dstx) | ({16{valid_3d}} & x_out_3d); // X destination
wire [15:0] real_dsty = ({16{~valid_3d}} & dx_real_dsty) | ({16{valid_3d}} & y_out_3d); // Y destination
wire pc_msk_last = (~valid_3d & dx_pc_msk_last) | (valid_3d & pc_msk_last_3d); // Last pixel mask.
wire clip = (~valid_3d) ? dx_clip : 1'b0;
// create org and pitch multiplexers
always @* begin
casex({push,imem_rd})
/* synopsys full_case parallel_case */
2'b1x:begin // Pixel Cache Color write to memory.
org_2 = dorg_2;
ptch_2 = dptch_2;
if (BYTES == 16) x_pos = {{2{in_x[15]}}, in_x[15:4]};
else if (BYTES == 8) x_pos = {in_x[15], in_x[15:3]};
else x_pos = in_x[15:2];
y_pos = in_y;
end
2'b01:begin // 2 D read from memory.
org_2 = sorg_2;
ptch_2 = sptch_2;
//if (BYTES == 16) x_pos = {{2{srcx[15]}}, srcx[15:6], 2'b0};
//else if (BYTES == 8) x_pos = {srcx[15], srcx[15:5], 2'b0};
//else x_pos = {srcx[15:4], 2'b0};
if (BYTES == 16) x_pos = {{2{srcx[15]}}, srcx[15:4]};
else if (BYTES == 8) x_pos = {srcx[15], srcx[15:4], 1'b0};
else x_pos = {srcx[15:4], 2'b0};
y_pos = srcy;
end
2'b00:begin // 2 D write to memory.
org_2 = dorg_2;
ptch_2 = dptch_2;
//if (BYTES == 16) x_pos = {{2{dstx[15]}}, dstx[15:6], 2'b0};
//else if (BYTES == 8) x_pos = {dstx[15], dstx[15:5], 2'b0};
//else x_pos = {dstx[15:4], 2'b0};
if (BYTES == 16) x_pos = {{2{dstx[15]}}, dstx[15:4]};
else if (BYTES == 8) x_pos = {dstx[15], dstx[15:4], 1'b0};
else x_pos = {dstx[15:4], 2'b0};
y_pos = dsty;
end
endcase
end
always @*
if (BYTES == 16) fifo_address = p_mult + int_add;
else if (BYTES == 8) fifo_address = {p_mult, 1'b0} + int_add;
else fifo_address = {p_mult, 2'b0} + int_add;
always @*
if (BYTES == 16) z_address = z_mult + int_zadd;
else if (BYTES == 8) z_address = {z_mult, 1'b0} + int_zadd;
else z_address = {z_mult, 2'b0} + int_zadd;
always @ (posedge de_clk) begin
if (push || dx_mem_req) begin
// Pitch conversion
p_mult <= (y_pos * {{4{ptch_2[11]}}, ptch_2});
z_mult <= (y_pos * {{4{zptch_2[11]}}, zptch_2});
`ifdef BYTE16 int_add <= (org_2 + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE8 int_add <= ({org_2, 1'b0} + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE4 int_add <= ({org_2, 2'b0} + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE16 int_zadd <= (zorg_2 + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE8 int_zadd <= ({zorg_2, 1'b0} + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE4 int_zadd <= ({zorg_2, 2'b0} + {{14{x_pos[13]}}, x_pos}); `endif
fifo_rmw <= (rmw | blend_en_2);
fifo_kcol <= kcol_2;
fifo_ps <= ps_2;
fifo_bsrcr <= bsrcr_2;
fifo_bdstr <= bdstr_2;
fifo_blend_en <= blend_en_2;
fifo_blend_reg_en <= blend_reg_en_2;
fifo_bsrc_alpha <= bsrc_alpha_2;
fifo_bdst_alpha <= bdst_alpha_2;
fifo_rop <= rop_2;
fifo_key_ctrl <= key_ctrl_2;
fifo_junk[6:0] <= lft_enc_2;
fifo_junk[13:7] <= rht_enc_2;
fifo_junk[25:14] <= dstx[15:4];
fifo_junk[26] <= rst_wad_flg_2;
end
if (push) begin
fifo_color[7:0] <= ~int_mask[0] ? int_col[7:0] : fifo_color[7:0];
fifo_color[15:8] <= ~int_mask[1] ? int_col[15:8] : fifo_color[15:8];
fifo_color[23:16] <= ~int_mask[2] ? int_col[23:16] : fifo_color[23:16];
fifo_color[31:24] <= ~int_mask[3] ? int_col[31:24] : fifo_color[31:24];
fifo_color[39:32] <= ~int_mask[4] ? int_col[39:32] : fifo_color[39:32];
fifo_color[47:40] <= ~int_mask[5] ? int_col[47:40] : fifo_color[47:40];
fifo_color[55:48] <= ~int_mask[6] ? int_col[55:48] : fifo_color[55:48];
fifo_color[63:56] <= ~int_mask[7] ? int_col[63:56] : fifo_color[63:56];
fifo_color[71:64] <= ~int_mask[8] ? int_col[71:64] : fifo_color[71:64];
fifo_color[79:72] <= ~int_mask[9] ? int_col[79:72] : fifo_color[79:72];
fifo_color[87:80] <= ~int_mask[10] ? int_col[87:80] : fifo_color[87:80];
fifo_color[95:88] <= ~int_mask[11] ? int_col[95:88] : fifo_color[95:88];
fifo_color[103:96] <= ~int_mask[12] ? int_col[103:96] : fifo_color[103:96];
fifo_color[111:104] <= ~int_mask[13] ? int_col[111:104] : fifo_color[111:104];
fifo_color[119:112] <= ~int_mask[14] ? int_col[119:112] : fifo_color[119:112];
fifo_color[127:120] <= ~int_mask[15] ? int_col[127:120] : fifo_color[127:120];
z_buffer[7:0] <= ~int_mask[0] ? int_z[7:0] : z_buffer[7:0];
z_buffer[15:8] <= ~int_mask[1] ? int_z[15:8] : z_buffer[15:8];
z_buffer[23:16] <= ~int_mask[2] ? int_z[23:16] : z_buffer[23:16];
z_buffer[31:24] <= ~int_mask[3] ? int_z[31:24] : z_buffer[31:24];
z_buffer[39:32] <= ~int_mask[4] ? int_z[39:32] : z_buffer[39:32];
z_buffer[47:40] <= ~int_mask[5] ? int_z[47:40] : z_buffer[47:40];
z_buffer[55:48] <= ~int_mask[6] ? int_z[55:48] : z_buffer[55:48];
z_buffer[63:56] <= ~int_mask[7] ? int_z[63:56] : z_buffer[63:56];
z_buffer[71:64] <= ~int_mask[8] ? int_z[71:64] : z_buffer[71:64];
z_buffer[79:72] <= ~int_mask[9] ? int_z[79:72] : z_buffer[79:72];
z_buffer[87:80] <= ~int_mask[10] ? int_z[87:80] : z_buffer[87:80];
z_buffer[95:88] <= ~int_mask[11] ? int_z[95:88] : z_buffer[95:88];
z_buffer[103:96] <= ~int_mask[12] ? int_z[103:96] : z_buffer[103:96];
z_buffer[111:104] <= ~int_mask[13] ? int_z[111:104] : z_buffer[111:104];
z_buffer[119:112] <= ~int_mask[14] ? int_z[119:112] : z_buffer[119:112];
z_buffer[127:120] <= ~int_mask[15] ? int_z[127:120] : z_buffer[127:120];
a_buffer[7:0] <= ~int_mask[0] ? pix_a : a_buffer[7:0];
a_buffer[15:8] <= ~int_mask[2] ? pix_a : a_buffer[15:8];
a_buffer[23:16] <= ~int_mask[4] ? pix_a : a_buffer[23:16];
a_buffer[31:24] <= ~int_mask[6] ? pix_a : a_buffer[31:24];
a_buffer[39:32] <= ~int_mask[8] ? pix_a : a_buffer[39:32];
a_buffer[47:40] <= ~int_mask[10] ? pix_a : a_buffer[47:40];
a_buffer[55:48] <= ~int_mask[12] ? pix_a : a_buffer[55:48];
a_buffer[63:56] <= ~int_mask[14] ? pix_a : a_buffer[63:56];
fifo_mask <= ~same_page ? int_mask : int_mask & fifo_mask;
fifo_cmd <= 1'b0; // Line/ Triangle write
fifo_junk[27] <= sol_2;
end else if (dx_mem_req) begin
fifo_junk[27] <= ~imem_rd ? sol_2 : fifo_junk[27];
fifo_color[31:0] <= fore_2;
fifo_color[63:32] <= back_2;
fifo_color[67:64] <= mask_2;
fifo_color[68] <= ps8_2;
fifo_color[69] <= ps16_2;
fifo_color[70] <= ps32_2;
fifo_color[72:71] <= stpl_2;
fifo_color[73] <= dr_trnsp_2;
fifo_color[75:74] <= dr_clp_2;
fifo_color[77:76] <= dr_apat_2;
fifo_color[78] <= solid_2;
fifo_color[79] <= imem_rd;
fifo_color[80] <= rad_flg_2;
fifo_color[83:81] <= strt_wrd_2;
fifo_color[87:84] <= strt_byt_2;
fifo_color[90:88] <= strt_bit_2;
fifo_color[93:91] <= frst8_2;
fifo_color[105:94] <= clp_min_2;
fifo_color[117:106] <= clp_max_2;
fifo_color[121:118] <= cmin_enc_2;
fifo_color[125:122] <= cmax_enc_2;
fifo_color[126] <= y_clip_2;
fifo_color[127] <= eol_2;
fifo_mask <= {12'b0, wcnt};
fifo_cmd <= 1'b1; // BLT operation
end
end
always @(posedge de_clk or negedge de_rstn)
if (!de_rstn) begin
pix_color <= 32'b0;
pix_z <= 32'b0;
pix_a <= 8'b0;
push <= 1'b0;
pc_dirty <= 1'b0;
pc_pending <= 1'b0;
in_x <= 16'h0;
in_y <= 16'h0;
depth <= 2'b0;
pc_busy <= 1'b0;
pc_busy_3d <= 1'b0;
wcnt <= 4'b0;
startup <= 1'b1;
same_page <= 1'b0;
push_previous <= 1'b0;
push_last <= 1'b0;
pipe_push_last <= 1'b0;
dx_delayed <= 1'b0;
data_pending <= 1'b0;
fifo_data <= 271'b0;
fifo_adata <= 128'b0;
fifo_z <= 166'h0;
fifo_push <= 1'b0;
push_d <= 1'b0;
last_pixel_pipe<= 2'b0;
pc_empty <= 1'b0;
hold_push_last <= 1'b0;
hold_3d <= 1'b0;
active_3d_del <= 1'b0;
end else begin
active_3d_del <= active_3d_2;
pc_empty <= fifo_empty;
push_d <= push;
last_pixel_pipe <= {last_pixel_pipe[0], last_pixel};
fifo_push <= dx_delayed | push_previous | pipe_push_last;
fifo_adata <= {fifo_blend_reg_en, a_buffer};
fifo_data <= {
fifo_junk, // [270:243]
fifo_ps, // [242:241]
fifo_key_ctrl, // [240:238]
fifo_blend_en, // [237]
fifo_bsrcr, // [236:233]
fifo_bdstr, // [232:230]
fifo_rop, // [229:226]
fifo_bsrc_alpha, // [225:218]
fifo_bdst_alpha, // [217:210]
fifo_kcol, // [209:178]
fifo_rmw, // [177]
fifo_cmd, // [176]
fifo_address, // [175:144]
fifo_mask, // [143:128]
fifo_color // [127:0]
};
fifo_z <= {
active_3d_del | hold_3d, // [165]
z_en, // [164]
z_ro, // [163]
z_op, // [162:160]
z_address, // [159:128]
z_buffer // [127:0]
};
if (push_d && ~push_previous) data_pending <= 1'b1;
else if (push_d && push_previous || push_last) data_pending <= 1'b0;
push_previous <= 1'b0;
push_last <= 1'b0;
pipe_push_last <= push_last;
dx_delayed <= dx_mem_req;
if (ld_wcnt) wcnt <= fx_1[3:0] - 1'b1;
// pc_busy_3d <= (wrusedw > 64);
pc_busy_3d <= (wrusedw > 96);
pc_busy <= (wrusedw > 120);
// pc_busy <= ~fifo_empty;
push <= 1'b0;
// create the dirty flag
if (pc_ld && ~clip && ~pc_busy) pc_dirty <= 1'b1;
else if (fifo_empty) pc_dirty <= 1'b0;
// Ceate the busy flag
if (last_pixel) pc_pending <= 1'b0;
else if (pc_ld && ~pc_busy) pc_pending <= 1'b1;
//push_last <= (data_pending & last_pixel_pipe[1] & ~pc_busy) |
push_last <= ~hold_push_last & (data_pending & last_pixel_pipe[1] & ~last_pixel_pipe[0]) |
pc_ld & ~pc_busy & last_pixel & ~pc_msk_last & ~(dr_trnsp_2 & ~fg_bgn);
// pc_last <= ~hold_push_last & (data_pending & last_pixel_pipe[1] & ~last_pixel_pipe[0]) |
// pc_ld & ~pc_busy & last_pixel;
pc_last <= (last_pixel_pipe[1] & ~last_pixel_pipe[0]);
if (pc_ld && ~last_pixel) hold_push_last <= 1'b0;
else if (push_last) hold_push_last <= 1'b1;
if (pc_ld && ~last_pixel) hold_3d <= active_3d_2;
if (pc_ld && ~clip && ~pc_busy) begin
//startup <= last_pixel; // each new line
if (last_pixel) startup <= 1'b1;
else if ((~dr_trnsp_2 | dr_trnsp_2 & fg_bgn | solid_2) &
~(last_pixel & pc_msk_last)) startup <= 1'b0;
if (last_pixel) startup <= 1'b1; // each new line
// Added 3D data input (Jim MacLeod)
pix_color <= (solid_2) ? fore_2 :
(valid_3d & fg_bgn_3d) ? pixel_3d :
(fg_bgn) ? fore_2 : back_2;
pix_z <= z_3d;
pix_a <= alpha_3d;
// push if solid, not transparent or transparent + foreground
if ((~dr_trnsp_2 | dr_trnsp_2 & fg_bgn | solid_2) &
~(last_pixel & pc_msk_last)) begin
push <= 1'b1;
// X miss
if (BYTES == 16) begin
push_previous <= ~startup & ((in_x[15:4] != real_dstx[15:4]) |
(in_y != real_dsty));
// make sure to push if really last
same_page <= ~(startup | in_x[15:4] != real_dstx[15:4] |
in_y != real_dsty);
end else if (BYTES == 8) begin
push_previous <= ~startup & ((in_x[15:3] != real_dstx[15:3]) |
(in_y != real_dsty));
// make sure to push if really last
same_page <= ~(startup | in_x[15:3] != real_dstx[15:3] |
in_y != real_dsty);
end else begin
push_previous <= ~startup & ((in_x[15:2] != real_dstx[15:2]) |
(in_y != real_dsty));
// make sure to push if really last
same_page <= ~(startup | in_x[15:2] != real_dstx[15:2] |
in_y != real_dsty);
end
end
// don't push if masking last pix.
in_x <= real_dstx;
in_y <= real_dsty;
depth <= {ps32_2, ps16_2};
end
end
always @*
case (depth)
2'b00: int_col = {16{pix_color[7:0]}};
2'b01: int_col = {8{pix_color[15:0]}};
default: int_col = {4{pix_color}};
endcase // casex({solid_2, fg_bgn_2, ps32_2, ps16_2})
always @*
case (depth)
2'b00: int_z = {16{pix_z[7:0]}};
2'b01: int_z = {8{pix_z[15:0]}};
default: int_z = {4{pix_z}};
endcase // casex({solid_2, fg_bgn_2, ps32_2, ps16_2})
always @*
if (BYTES == 16)
casex ({depth, in_x[3:0]})
// synopsys parallel_case
6'b00_0000: int_mask = 16'hFFFE;
6'b00_0001: int_mask = 16'hFFFD;
6'b00_0010: int_mask = 16'hFFFB;
6'b00_0011: int_mask = 16'hFFF7;
6'b00_0100: int_mask = 16'hFFEF;
6'b00_0101: int_mask = 16'hFFDF;
6'b00_0110: int_mask = 16'hFFBF;
6'b00_0111: int_mask = 16'hFF7F;
6'b00_1000: int_mask = 16'hFEFF;
6'b00_1001: int_mask = 16'hFDFF;
6'b00_1010: int_mask = 16'hFBFF;
6'b00_1011: int_mask = 16'hF7FF;
6'b00_1100: int_mask = 16'hEFFF;
6'b00_1101: int_mask = 16'hDFFF;
6'b00_1110: int_mask = 16'hBFFF;
6'b00_1111: int_mask = 16'h7FFF;
6'b01_000x: int_mask = 16'hFFFC;
6'b01_001x: int_mask = 16'hFFF3;
6'b01_010x: int_mask = 16'hFFCF;
6'b01_011x: int_mask = 16'hFF3F;
6'b01_100x: int_mask = 16'hFCFF;
6'b01_101x: int_mask = 16'hF3FF;
6'b01_110x: int_mask = 16'hCFFF;
6'b01_111x: int_mask = 16'h3FFF;
6'b10_00xx: int_mask = 16'hFFF0;
6'b10_01xx: int_mask = 16'hFF0F;
6'b10_10xx: int_mask = 16'hF0FF;
default: int_mask = 16'h0FFF;
endcase // casex({depth, in_x[3:0]})
else if (BYTES == 8)
casex ({depth, in_x[3:0]})
// synopsys parallel_case
6'b00_x000: int_mask = 16'hFFFE;
6'b00_x001: int_mask = 16'hFFFD;
6'b00_x010: int_mask = 16'hFFFB;
6'b00_x011: int_mask = 16'hFFF7;
6'b00_x100: int_mask = 16'hFFEF;
6'b00_x101: int_mask = 16'hFFDF;
6'b00_x110: int_mask = 16'hFFBF;
6'b00_x111: int_mask = 16'hFF7F;
6'b01_x00x: int_mask = 16'hFFFC;
6'b01_x01x: int_mask = 16'hFFF3;
6'b01_x10x: int_mask = 16'hFFCF;
6'b01_x11x: int_mask = 16'hFF3F;
6'b10_x0xx: int_mask = 16'hFFF0;
default: int_mask = 16'hFF0F;
endcase // casex({depth, in_x[3:0]})
else
casex ({depth, in_x[3:0]})
// synopsys parallel_case
6'b00_xx00: int_mask = 16'hFFFE;
6'b00_xx01: int_mask = 16'hFFFD;
6'b00_xx10: int_mask = 16'hFFFB;
6'b00_xx11: int_mask = 16'hFFF7;
6'b01_xx0x: int_mask = 16'hFFFC;
6'b01_xx1x: int_mask = 16'hFFF3;
default: int_mask = 16'hFFF0;
endcase // casex({depth, in_x[3:0]})
`ifdef RAM_FIFO_271x128
async_fifo
#
(
.WIDTH (271),
.DEPTH (128),
.DLOG2 (7)
) u_fifo_271x128a
(
.aclr (de_rstn),
.wrclk (de_clk),
.wrreq (fifo_push),
.data (fifo_data),
.wr_empty (fifo_empty),
.wrusedw (wrusedw),
.rdclk (mc_clk),
.rdreq (de_pc_pop),
.q (fifo_dout),
.rd_empty (de_pc_empty)
);
async_fifo
#
(
.WIDTH (166),
.DEPTH (128),
.DLOG2 (7)
) u_fifo_181x128a
(
.aclr (de_rstn),
.wrclk (de_clk),
.wrreq (fifo_push),
.data (fifo_z),
.wr_empty (),
.wrusedw (),
.rdclk (mc_clk),
.rdreq (de_pc_pop),
.q (fifo_zout),
.rd_empty ()
);
`else
fifo_128x128a u0_fifo
(
.aclr (~de_rstn),
.data (fifo_data[127:0]),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q (fifo_dout[127:0]),
.rdempty (de_pc_empty),
.wrempty (fifo_empty),
.wrusedw (wrusedw)
);
fifo_144x128a u1_fifo
(
.aclr (~de_rstn),
.data ({1'b0, fifo_data[270:128]}),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q ({fifo_dout_extra, fifo_dout[270:128]})
);
fifo_181x128a u2_fifo
(
.aclr (~de_rstn),
.data (fifo_z),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q (fifo_zout)
);
fifo_128x128a u3_fifo
(
.aclr (~de_rstn),
.data (fifo_adata),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q (a_dout[127:0])
);
`endif // !`ifdef RAM_FIFO_267x128
always @(posedge mc_clk or negedge de_rstn)
if (!de_rstn) mc_acken <= 1'b0;
else mc_acken <= de_pc_pop;
always @(posedge mc_clk or negedge de_rstn)
if (!de_rstn) begin
px_col <= 128'b0;
px_a <= 64'b0;
px_msk_color <= 16'b0;
de_mc_address<= 32'b0;
de_mc_rmw <= 1'b0;
de_mc_read <= 1'b0;
de_mc_wcnt <= 4'b0;
blt_actv_4 <= 1'b0;
line_actv_4 <= 1'b0;
kcol_4 <= 32'b0;
bdst_alpha_4 <= 8'b0;
bsrc_alpha_4 <= 8'b0;
rop_4 <= 4'b0;
bdstr_4 <= 3'b0;
bsrcr_4 <= 4'b0;
blend_en_4 <= 1'b0;
key_ctrl_4 <= 3'b0;
ps_4 <= 2'b0;
lft_enc_4 <= 7'b0;
rht_enc_4 <= 7'b0;
clp_min_4 <= 12'b0;
clp_max_4 <= 12'b0;
cmin_enc_4 <= 4'b0;
cmax_enc_4 <= 4'b0;
y_clip_4 <= 1'b0;
eol_4 <= 1'b0;
fore_4 <= 32'b0;
back_4 <= 32'b0;
mask_4 <= 4'b0;
ps8_4 <= 1'b0;
ps16_4 <= 1'b0;
ps32_4 <= 1'b0;
stpl_4 <= 2'b0;
trnsp_4 <= 1'b0;
clp_4 <= 2'b0;
apat_4 <= 2'b0;
solid_4 <= 1'b0;
strt_wrd_4 <= 3'b0;
strt_byt_4 <= 4'b0;
strt_bit_4 <= 3'b0;
frst8_4 <= 3'b0;
z_en_4 <= 1'b0;
z_ro_4 <= 1'b0;
z_op_4 <= 3'b0;
z_address_4 <= 32'b0;
z_out <= 128'b0;
end else begin
if (mc_acken) begin
// Z stuff
z_en_4 <= (&fifo_zout[165:164]);
z_ro_4 <= fifo_zout[163];
z_op_4 <= fifo_zout[162:160];
z_address_4 <= fifo_zout[159:128];
z_out <= fifo_zout[127:0];
// Color stuff
px_a <= a_dout[63:0];
blend_reg_en_4<= a_dout[65:64];
px_col <= fifo_dout[127:0];
px_msk_color <= fifo_dout[143:128];
de_mc_address<= fifo_dout[175:144];
de_mc_rmw <= fifo_dout[177];
de_mc_read <= fifo_dout[176] & fifo_dout[79];
de_mc_wcnt <= ~fifo_dout[176] ? 4'b0 : fifo_dout[131:128];
blt_actv_4 <= fifo_dout[176];
line_actv_4 <= ~fifo_dout[176];
kcol_4 <= fifo_dout[209:178];
bdst_alpha_4 <= fifo_dout[217:210];
bsrc_alpha_4 <= fifo_dout[225:218];
rop_4 <= fifo_dout[229:226];
bdstr_4 <= fifo_dout[232:230];
bsrcr_4 <= fifo_dout[236:233];
blend_en_4 <= fifo_dout[237];
key_ctrl_4 <= fifo_dout[240:238];
ps_4 <= fifo_dout[242:241];
lft_enc_4 <= fifo_dout[249:243];
rht_enc_4 <= fifo_dout[256:250];
clp_min_4 <= fifo_dout[105:94];
clp_max_4 <= fifo_dout[117:106];
cmin_enc_4 <= fifo_dout[121:118];
cmax_enc_4 <= fifo_dout[125:122];
y_clip_4 <= fifo_dout[126];
eol_4 <= fifo_dout[127];
// BLT only flags
if (fifo_dout[176]) begin
fore_4 <= fifo_dout[31:0];
back_4 <= fifo_dout[63:32];
mask_4 <= fifo_dout[67:64];
ps8_4 <= fifo_dout[68];
ps16_4 <= fifo_dout[69];
ps32_4 <= fifo_dout[70];
stpl_4 <= fifo_dout[72:71];
trnsp_4 <= fifo_dout[73];
clp_4 <= fifo_dout[75:74];
apat_4 <= fifo_dout[77:76];
solid_4 <= fifo_dout[78];
if (fifo_dout[80]) begin
strt_wrd_4 <= fifo_dout[83:81];
strt_byt_4 <= fifo_dout[87:84];
strt_bit_4 <= fifo_dout[90:88];
end
frst8_4 <= fifo_dout[93:91];
end else begin // if (fifo_dout[172])
mask_4 <= 4'hF; // set mask to 1111 for line
end
end
end // else: !if(!de_rstn)
// page coordinate counter, used to track X during page cycles and produce
// the correct clipping mask
always @(posedge mc_clk)
if (mc_acken && (BYTES == 16)) x_bus_4 <= {2'b00, fifo_dout[268:257]};
else if (mc_acken && (BYTES == 8)) x_bus_4 <= {1'b0, fifo_dout[268:257], 1'b0};
else if (mc_acken) x_bus_4 <= {fifo_dout[268:257], 2'b00};
else if (mc_popen) x_bus_4 <= x_bus_4 + 14'h1;
`ifdef BYTE16
always @(posedge mc_clk)
if (mc_acken) sol_4_int <= fifo_dout[270];
else if (mc_popen) sol_4_int <= 1'b0;
assign sol_4 = sol_4_int[0];
`elsif BYTE8
always @(posedge mc_clk)
if (mc_acken) sol_4_int <= {1'b0, fifo_dout[270], 1'b0};
else if (mc_popen) sol_4_int <= sol_4_int - |sol_4_int;
assign sol_4 = |sol_4_int;
`else
always @(posedge mc_clk)
if (mc_acken) sol_4_int <= {fifo_dout[270], 2'b0};
else if (mc_popen) sol_4_int <= sol_4_int - |sol_4_int;
assign sol_4 = |sol_4_int;
`endif
assign rst_wad_flg_3 = fifo_dout[269];
assign rad_flg_3 = fifo_dout[80];
assign sol_3 = fifo_dout[270];
assign mc_read_3 = fifo_dout[172] & fifo_dout[79];
assign strt_wrd_3 = fifo_dout[80] ? fifo_dout[83:81] : strt_wrd_4;
assign strt_byt_3 = fifo_dout[80] ? fifo_dout[87:84] : strt_byt_4;
assign strt_bit_3 = fifo_dout[80] ? fifo_dout[90:88] : strt_bit_4;
endmodule
|
// megafunction wizard: %ALTIOBUF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altiobuf_in
// ============================================================
// File Name: in_buf.v
// Megafunction Name(s):
// altiobuf_in
//
// Simulation Library Files(s):
// cyclonev
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altiobuf_in CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" datain dataout
//VERSION_BEGIN 15.0 cbx_altiobuf_in 2015:04:15:19:11:38:SJ cbx_mgl 2015:04:15:20:18:26:SJ cbx_stratixiii 2015:04:15:19:11:39:SJ cbx_stratixv 2015:04:15:19:11:39:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = cyclonev_io_ibuf 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module in_buf_iobuf_in_v0i
(
datain,
dataout) ;
input [0:0] datain;
output [0:0] dataout;
wire [0:0] wire_ibufa_o;
cyclonev_io_ibuf ibufa_0
(
.i(datain),
.o(wire_ibufa_o[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_0.bus_hold = "false",
ibufa_0.differential_mode = "false",
ibufa_0.lpm_type = "cyclonev_io_ibuf";
assign
dataout = wire_ibufa_o;
endmodule //in_buf_iobuf_in_v0i
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module in_buf (
datain,
dataout);
input [0:0] datain;
output [0:0] dataout;
wire [0:0] sub_wire0;
wire [0:0] dataout = sub_wire0[0:0];
in_buf_iobuf_in_v0i in_buf_iobuf_in_v0i_component (
.datain (datain),
.dataout (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
// Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
// Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
// Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
// Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf_bb.v FALSE
// Retrieval info: LIB_FILE: cyclonev
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/09/2015 03:36:22 PM
// Design Name:
// Module Name: quad_encoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module quad_encoder(
input clk,
input reset,
input a,
input b,
output [31:0] count
);
reg [2:0] a_prev;
reg [2:0] b_prev;
reg dir = 1'b0;
reg [31:0] count = 32'b0;
reg count_enable = 1'b0;
always @(posedge clk)
begin
a_prev <= {a_prev[1:0],a};
b_prev <= {b_prev[1:0],b};
end
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1)
begin
dir <= 1'b0;
count <= 32'b0;
count_enable <= 0'b0;
end
else
count_enable <= a_prev[2] ^ b_prev[2] ^ a_prev[1] ^ b_prev[1];
dir <= b_prev[2] ^ a_prev[1] ;
if(count_enable)
begin
if(dir)
begin
count <= count + 32'b1;
end
else
begin
count <= count - 32'b1;
end
end
end
endmodule
|
`default_nettype none
`timescale 1ns/1ns
module tb_sys_level;
`include "../task/task_disp_inst_issue.v"
`include "../task/task_disp_pcr.v"
`include "../task/task_disp_tag_info.v"
`include "../task/task_disp_branch.v"
`include "../task/task_disp_loadstore.v"
`include "../task/task_disp_logic_register.v"
localparam PL_CORE_CYCLE = 20; //It's necessary "Core Clock == Bus Clock". This restriction is removed near future.
localparam PL_BUS_CYCLE = 20; //
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
localparam PL_GCI_SIZE = 32'h0001_0000;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
wire iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire [3:0] oMEMORY_MASK;
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
wire iMEMORY_VALID;
wire oMEMORY_BUSY;
wire [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
mist1032sa TARGET(
/****************************************
System
****************************************/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iBUS_CLOCK),
.iDPS_CLOCK(iDPS_CLOCK),
.inRESET(inRESET),
/****************************************
SCI
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(oMEMORY_REQ),
.iMEMORY_LOCK(iMEMORY_LOCK),
.oMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.oMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.oMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.iMEMORY_VALID(iMEMORY_VALID),
.oMEMORY_BUSY(oMEMORY_BUSY),
.iMEMORY_DATA(iMEMORY_DATA),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(oGCI_REQ), //Input
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ), //Output
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
.oDEBUG_PC(oDEBUG_PC),
.oDEBUG0(oDEBUG0),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
$display("Check Start");
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
//GCI Init
#(PL_BUS_CYCLE*32);
while(oGCI_BUSY) #(PL_BUS_CYCLE);
iGCI_REQ = 1'b1;
iGCI_DATA = PL_GCI_SIZE;
#(PL_BUS_CYCLE);
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
#1500000000 begin
$finish;
end
end
/******************************************************
Memory Model
******************************************************/
sim_memory_model #(1, "tb_sys_test.hex") MEMORY_MODEL(
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//Req
.iMEMORY_REQ(oMEMORY_REQ),
.oMEMORY_LOCK(iMEMORY_LOCK),
.iMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iMEMORY_MASK(oMEMORY_MASK),
.iMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.iMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.iMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.oMEMORY_VALID(iMEMORY_VALID),
.iMEMORY_LOCK(oMEMORY_BUSY),
.oMEMORY_DATA(iMEMORY_DATA)
);
/******************************************************
Display Dump
******************************************************/
always@(posedge iCORE_CLOCK)begin
if(inRESET)begin
//task_disp_inst_issue();
//task_disp_pcr();
//task_disp_tag_info();
//task_disp_branch();
task_disp_loadstore();
//task_disp_logic_register_all();
//task_disp_logic_register_single(5'h2);
end
end
/******************************************************
Assertion
******************************************************/
/*
reg assert_check_flag;
reg [31:0] assert_wrong_number;
reg [31:0] assert_wrong_type;
reg [31:0] assert_result;
reg [31:0] assert_expect;
always@(posedge iCORE_CLOCK)begin
if(inRESET && oMEMORY_REQ && !iMEMORY_LOCK && oMEMORY_ORDER == 2'h2 && oMEMORY_RW)begin
//Finish Check
if(oMEMORY_ADDR == 32'h0002_0004)begin
if(!assert_check_flag)begin
$display("[SIM-ERR]Wrong Data.");
$display("[SIM-ERR]Wrong Type : %d", assert_wrong_type);
$display("[SIM-ERR]Index:%d, Expect:%x, Result:%x", assert_wrong_number, assert_expect, assert_result);
$display("[SIM-ERR]Simulation Finished.");
$finish;
end
else begin
$display("[SIM-OK]Simulation Finished.");
$finish;
end
end
//Check Log
else if(oMEMORY_ADDR == 32'h0002_0008)begin
$display("[SIM-LOG]#d", {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]});
end
//Check Flag
else if(oMEMORY_ADDR == 32'h0002_0000)begin
assert_check_flag = oMEMORY_DATA[24];
end
//Error Number
else if(oMEMORY_ADDR == 32'h0002_0010)begin
assert_wrong_number = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Type
else if(oMEMORY_ADDR == 32'h0002_000c)begin
assert_wrong_type = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Result
else if(oMEMORY_ADDR == 32'h0002_0014)begin
assert_result = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Expect
else if(oMEMORY_ADDR == 32'h0002_0018)begin
assert_expect = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
end
end
*/
endmodule
`default_nettype wire
|
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 10.12.2015 13:03:05
// Design Name:
// Module Name: red_pitaya_iir_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// Design considerations
// Try: Filter coefficients are represented as 100 bit numbers in IQ module
// Upon a custom command, all coefficients are updated
// Data for multiplication are always 18 bit numbers
// Must properly treat overflow conditions
// Arbitrary (max 16) sequential execution of parallel modules
// Choice over ZOH or averaging of input during the 16 sequences
// maximum specs: 16 biquad iir filters, each with 4 coefficients with 128 bits
//-> 128*4 = 512 * 16 = 8092 bits! for representing such a large number, we need already
// 12 address bits! where does this fit into the address space of the pid module?
//address: 0x20000 or 0x30000-> treated by iq module
//set address bit 16: goes into fgen module -> 0x2zzzz is free
//0x2n000 for IQ-module number n
//diret form:
//
// sum_k^M ( b_k * z^-k ) b_0 + b_1/z
// H(z) = --------------------------- = ------------------------
// 1 - sum_k^N ( a_k * z^-k) 1 - a_1/z - a_2/z^2
//
// can be transformed into a difference equation:
// y[n] = a_1 * y_(n-1) + a_2 * y_(n-2) + b_0 * x(n) + b_1 * x(n-1)
//
// we thus have to compute 4 products
//////////////////////////////////////////////////////////////////////////////////
module red_pitaya_iir_block
#( parameter IIRBITS = 32, //46 // iir coefficients represented with IIRBITS bits
parameter IIRSHIFT = 29, //30 // iir coefficients FIXED POINT at bit IIRSHIFT
parameter IIRSTAGES = 14, //20 // maximum number of parallel biquads
parameter IIRSIGNALBITS= 32, //40 //32 // internally represent calculated results with IIRSIGNALBITS bits (32 is really necessary)
parameter SIGNALBITS = 14, // in- and output signal bitwidth
parameter SIGNALSHIFT = 3, //5, // over-represent input by SIGNALSHIFT bits (e.g. once input averaging is implemented)
parameter LOOPBITS = 10, //8
//parameters for input pre-filter
parameter FILTERSTAGES = 1,
parameter FILTERSHIFTBITS = 3,
parameter FILTERMINBW = 1000
)
(
// data
input clk_i , // clock
input rstn_i , // reset - active low
input [ 14-1: 0] dat_i , // input data
output reg [ 14-1: 0] dat_o , // output data
// communication with PS
input [ 16-1: 0] addr,
input wen,
input ren,
output reg ack,
output reg [ 32-1: 0] rdata,
input [ 32-1: 0] wdata
);
reg [LOOPBITS-1:0] loops;
reg on;
reg shortcut;
//reg copydata;
reg [32-1:0] overflow; // accumulated overflows
wire [7-1:0] overflow_i; // instantaneous overflows
reg [32-1:0] iir_coefficients [0:IIRSTAGES*4*2-1];
reg [ 32-1: 0] set_filter; // input filter setting
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
loops <= {LOOPBITS{1'b0}};
on <= 1'b0;
shortcut <= 1'b0;
//copydata <= 1'b1;
set_filter <= 32'd0;
end
else begin
if (wen) begin
if (addr==16'h100) loops <= wdata[LOOPBITS-1:0];
//if (addr==16'h104) {copydata,shortcut,on} <= wdata[3-1:0];
if (addr==16'h104) {shortcut,on} <= wdata[2-1:0];
if (addr==16'h120) set_filter <= wdata;
if (addr[16-1]==1'b1) iir_coefficients[addr[12-1:2]] <= wdata;
end
casez (addr)
16'h100 : begin ack <= wen|ren; rdata <= {{32-LOOPBITS{1'b0}},loops}; end
//16'h104 : begin ack <= wen|ren; rdata <= {{32-3{1'b0}},copydata,shortcut,on}; end
16'h104 : begin ack <= wen|ren; rdata <= {{32-3{1'b0}},shortcut,on}; end
16'h108 : begin ack <= wen|ren; rdata <= overflow; end
16'h120 : begin ack <= wen|ren; rdata <= set_filter; end
16'h200 : begin ack <= wen|ren; rdata <= IIRBITS; end
16'h204 : begin ack <= wen|ren; rdata <= IIRSHIFT; end
16'h208 : begin ack <= wen|ren; rdata <= IIRSTAGES; end
16'h220 : begin ack <= wen|ren; rdata <= FILTERSTAGES; end
16'h224 : begin ack <= wen|ren; rdata <= FILTERSHIFTBITS; end
16'h228 : begin ack <= wen|ren; rdata <= FILTERMINBW; end
// disable read-back of coefficients to save resources
// this makes a big difference since it will allow the implementation of
// the coefficients as RAM and not as registers
// 16'b1zzzzzzzzzzzzzzz: begin ack <= wen|ren; rdata <= iir_coefficients[addr[12-1:2]]; end
default: begin ack <= wen|ren; rdata <= 32'h0; end
endcase
end
end
//-----------------------------
// cascaded set of FILTERSTAGES low- or high-pass filters
wire signed [SIGNALBITS+SIGNALSHIFT-1:0] dat_i_filtered;
red_pitaya_filter_block #(
.STAGES(FILTERSTAGES),
.SHIFTBITS(FILTERSHIFTBITS),
.SIGNALBITS(SIGNALBITS+SIGNALSHIFT),
.MINBW(FILTERMINBW)
)
iir_inputfilter
(
.clk_i(clk_i),
.rstn_i(rstn_i),
.set_filter(set_filter),
.dat_i({dat_i,{SIGNALSHIFT{1'b0}}}),
.dat_o(dat_i_filtered)
);
/*
//coefficient management - update coefficients when requested by copydata high transition
reg signed [IIRBITS-1:0] b0_i [0:IIRSTAGES-1];
reg signed [IIRBITS-1:0] b1_i [0:IIRSTAGES-1];
reg signed [IIRBITS-1:0] a1_i [0:IIRSTAGES-1];
reg signed [IIRBITS-1:0] a2_i [0:IIRSTAGES-1];
integer i;
always @(posedge clk_i) begin
if (copydata == 1'b1) begin
for (i=0;i<IIRSTAGES;i=i+1) begin
b0_i[i] <= {iir_coefficients[8*i+1],iir_coefficients[8*i+0]};//{iir_coefficients[16*i+3],iir_coefficients[16*i+2],iir_coefficients[16*i+1],iir_coefficients[16*i+0]};
b1_i[i] <= {iir_coefficients[8*i+3],iir_coefficients[8*i+2]};//{iir_coefficients[16*i+7],iir_coefficients[16*i+6],iir_coefficients[16*i+5],iir_coefficients[16*i+4]};
a1_i[i] <= {iir_coefficients[8*i+5],iir_coefficients[8*i+4]};//{iir_coefficients[16*i+11],iir_coefficients[16*i+10],iir_coefficients[16*i+9],iir_coefficients[16*i+8]};
a2_i[i] <= {iir_coefficients[8*i+7],iir_coefficients[8*i+6]};//{iir_coefficients[16*i+15],iir_coefficients[16*i+14],iir_coefficients[16*i+13],iir_coefficients[16*i+12]};
end
end
end
*/
// coefficient management more resource-friendly - only one memory for
// coefficients, update immediately -> requires reset after coefficient write
wire signed [IIRBITS-1:0] b0_i [0:IIRSTAGES-1];
wire signed [IIRBITS-1:0] b1_i [0:IIRSTAGES-1];
wire signed [IIRBITS-1:0] a1_i [0:IIRSTAGES-1];
wire signed [IIRBITS-1:0] a2_i [0:IIRSTAGES-1];
integer i; // for later use
genvar j;
generate for (j=0; j<IIRSTAGES; j=j+1) begin
assign b0_i[j] = {iir_coefficients[8*j+1],iir_coefficients[8*j+0]};
assign b1_i[j] = {iir_coefficients[8*j+3],iir_coefficients[8*j+2]};
assign a1_i[j] = {iir_coefficients[8*j+5],iir_coefficients[8*j+4]};
assign a2_i[j] = {iir_coefficients[8*j+7],iir_coefficients[8*j+6]};
end
endgenerate
// loop management - let stage0 repeatedly run from loops-1 to 0
// stage_n contains the number stage0 with n cycles of delay
reg [LOOPBITS-1:0] stage0;
reg [LOOPBITS-1:0] stage1;
reg [LOOPBITS-1:0] stage2;
reg [LOOPBITS-1:0] stage3;
reg [LOOPBITS-1:0] stage4;
reg [LOOPBITS-1:0] stage5;
reg [LOOPBITS-1:0] stage6;
always @(posedge clk_i) begin
if (on==1'b0) begin
overflow <= 32'h00000000;
stage0 <= loops;
stage1 <= {LOOPBITS{1'b0}};
stage2 <= {LOOPBITS{1'b0}};
stage3 <= {LOOPBITS{1'b0}};
stage4 <= {LOOPBITS{1'b0}};
stage5 <= {LOOPBITS{1'b0}};
stage6 <= {LOOPBITS{1'b0}};
end
else begin
overflow <= overflow | overflow_i;
if (stage0 == 8'h00)
stage0 <= loops - {{LOOPBITS-1{1'b0}},1'b1};
else
stage0 <= stage0 - {{LOOPBITS-1{1'b0}},1'b1};
end
stage1 <= stage0;
stage2 <= stage1;
stage3 <= stage2;
stage4 <= stage3;
stage5 <= stage4;
stage6 <= stage5;
end
//actual signal treatment
reg signed [IIRBITS-1:0] a1;
reg signed [IIRBITS-1:0] a2;
reg signed [IIRBITS-1:0] b0;
reg signed [IIRBITS-1:0] b1;
//wire signed [IIRSIGNALBITS-1:0] x0;
reg signed [IIRSIGNALBITS-1:0] x0;
//assign x0 = {{IIRSIGNALBITS-SIGNALSHIFT-SIGNALBITS+1{dat_i[SIGNALBITS-1]}},dat_i[SIGNALBITS-2:0],{SIGNALSHIFT{1'b0}}};
//assign x0 = $signed(dat_i_filtered);
//averaging in x0_sum below
//reg signed [IIRSIGNALBITS-1:0] x0_sum;
//reg signed [IIRSIGNALBITS-1:0] x0;
reg signed [IIRSIGNALBITS-1:0] y0;
reg signed [IIRSIGNALBITS-1:0] y1a;
reg signed [IIRSIGNALBITS-1:0] y2a;
reg signed [IIRSIGNALBITS-1:0] y1b;
reg signed [IIRSIGNALBITS-1:0] y1_i [0:IIRSTAGES-1];
reg signed [IIRSIGNALBITS-1:0] y2_i [0:IIRSTAGES-1];
//reg signed [IIRSIGNALBITS-1:0] z1_i [0:IIRSTAGES-1];
wire signed [IIRSIGNALBITS-1:0] p_ay1_full;
wire signed [IIRSIGNALBITS-1:0] p_ay2_full;
red_pitaya_product_sat #( .BITS_IN1(IIRSIGNALBITS), .BITS_IN2(IIRBITS), .SHIFT(IIRSHIFT), .BITS_OUT(IIRSIGNALBITS))
p_ay1_module (
.factor1_i(y1a),
.factor2_i(a1),
.product_o(p_ay1_full),
.overflow (overflow_i[0])
);
red_pitaya_product_sat #( .BITS_IN1(IIRSIGNALBITS), .BITS_IN2(IIRBITS), .SHIFT(IIRSHIFT), .BITS_OUT(IIRSIGNALBITS))
p_ay2_module (
.factor1_i(y2a),
.factor2_i(a2),
.product_o(p_ay2_full),
.overflow (overflow_i[1])
);
reg signed [IIRSIGNALBITS-1:0] p_ay1;
reg signed [IIRSIGNALBITS-1:0] p_ay2;
wire signed [IIRSIGNALBITS+2-1:0] y0_sum;
assign y0_sum = x0 + p_ay1 + p_ay2;
wire signed [IIRSIGNALBITS-1:0] y0_full;
red_pitaya_saturate #( .BITS_IN (IIRSIGNALBITS+2), .SHIFT(0), .BITS_OUT(IIRSIGNALBITS))
s_y0_module (
.input_i(y0_sum),
.output_o(y0_full),
.overflow (overflow_i[2])
);
wire signed [IIRSIGNALBITS-1:0] p_by0_full;
wire signed [IIRSIGNALBITS-1:0] p_by1_full;
red_pitaya_product_sat #( .BITS_IN1(IIRSIGNALBITS), .BITS_IN2(IIRBITS), .SHIFT(IIRSHIFT), .BITS_OUT(IIRSIGNALBITS))
p_by0_module (
.factor1_i(y0),
.factor2_i(b0),
.product_o(p_by0_full),
.overflow (overflow_i[3])
);
red_pitaya_product_sat #( .BITS_IN1(IIRSIGNALBITS), .BITS_IN2(IIRBITS), .SHIFT(IIRSHIFT), .BITS_OUT(IIRSIGNALBITS))
p_by1_module (
.factor1_i(y1b),
.factor2_i(b1),
.product_o(p_by1_full),
.overflow (overflow_i[4])
);
reg signed [IIRSIGNALBITS-1:0] p_by0;
reg signed [IIRSIGNALBITS-1:0] p_by1;
wire signed [IIRSIGNALBITS+2-1:0] z0_sum;
assign z0_sum = p_by0 + p_by1;
wire signed [IIRSIGNALBITS-1:0] z0_full;
red_pitaya_saturate #(
.BITS_IN (IIRSIGNALBITS+2),
.SHIFT(0),
.BITS_OUT(IIRSIGNALBITS)
)
s_z0_module (
.input_i(z0_sum),
.output_o(z0_full),
.overflow (overflow_i[5])
);
reg signed [IIRSIGNALBITS-1:0] z0;
//reg signed [IIRSIGNALBITS-1:0] z1;
/* //former solution - adder tree (resource intensive)
reg signed [IIRSIGNALBITS+4-1:0] dat_o_sum;
always @(*) begin
dat_o_sum = z1_i[0];
for (i=1;i<IIRSTAGES;i=i+1)
dat_o_sum = dat_o_sum + z1_i[i];
end
wire [SIGNALBITS-1:0] dat_o_full;
red_pitaya_saturate #( .BITS_IN (IIRSIGNALBITS+4), .SHIFT(SIGNALSHIFT), .BITS_OUT(SIGNALBITS))
s_dat_o_module (
.input_i(dat_o_sum),
.output_o(dat_o_full),
.overflow (overflow_i[6])
);
*/
// better solution - incremental adding - see below, here only saturator
reg signed [IIRSIGNALBITS+4-1:0] dat_o_sum;
wire [SIGNALBITS-1:0] dat_o_full;
red_pitaya_saturate #( .BITS_IN (IIRSIGNALBITS+4), .SHIFT(SIGNALSHIFT), .BITS_OUT(SIGNALBITS))
s_dat_o_module (
.input_i(dat_o_sum),
.output_o(dat_o_full),
.overflow (overflow_i[6])
);
reg signed [SIGNALBITS-1:0] signal_o;
always @(posedge clk_i) begin
// minimum delay implementation samples continuously new data
x0 <= dat_i_filtered;
if (on==1'b0) begin
for (i=0;i<IIRSTAGES;i=i+1) begin
y1_i[i] <= {IIRSIGNALBITS{1'b0}};
y2_i[i] <= {IIRSIGNALBITS{1'b0}};
end
y0 <= {IIRSIGNALBITS{1'b0}};
y1a <= {IIRSIGNALBITS{1'b0}};
y2a <= {IIRSIGNALBITS{1'b0}};
y1b <= {IIRSIGNALBITS{1'b0}};
z0 <= {IIRSIGNALBITS{1'b0}};
a1 <= {IIRBITS{1'b0}};
a2 <= {IIRBITS{1'b0}};
b0 <= {IIRBITS{1'b0}};
b1 <= {IIRBITS{1'b0}};
p_ay1 <= {IIRSIGNALBITS{1'b0}};
p_ay2 <= {IIRSIGNALBITS{1'b0}};
p_by0 <= {IIRSIGNALBITS{1'b0}};
p_by1 <= {IIRSIGNALBITS{1'b0}};
signal_o <= {SIGNALBITS{1'b0}};
//x0 <= {IIRSIGNALBITS{1'b0}};
end
else begin
// the computation will stretch over several cycles. while each computation is performed once per cycle, we will
// follow the signal of one particular biquad element as its signals go through the different phases of computation
// over subsequent cycles
//cycle n
if (stage0<IIRSTAGES) begin
y1a <= y1_i[stage0];
a1 <= a1_i[stage0];
y2a <= y2_i[stage0];
a2 <= a2_i[stage0];
y2_i[stage0] <= y1_i[stage0]; //update y2 memory
end
//cycle n+1
if (stage1<IIRSTAGES) begin
p_ay1 <= p_ay1_full;
p_ay2 <= p_ay2_full;
end
// do this for zero-order hold
//if (stage1 == (loops-1) || stage1 == (IIRSTAGES-1))
// x0 <= dat_i_filtered;
//cycle n+2
if (stage2<IIRSTAGES) begin
y0 <= y0_full;//no saturation here, because y0 is two bits longer than other signals
b0 <= b0_i[stage2];
y1b <= y1_i[stage2];
b1 <= b1_i[stage2];
y1_i[stage2] <= y0_full; //update y1 memory
end
//cycle n+3
if (stage3<IIRSTAGES) begin
p_by0 <= p_by0_full;
p_by1 <= p_by1_full;
end
//cycle n+4
if (stage4<IIRSTAGES) begin
z0 <= z0_full;
end
// from step IIRSTAGES-1 to 0 (IIRSTAGES steps), increment the sum
//cycle n+5
// start with a reset when the highest stage corresponding to an iir
// filter being executed
if (stage5 == (loops-1) || stage5 == (IIRSTAGES-1)) begin
dat_o_sum <= z0;
end
// then increment
else begin
dat_o_sum <= dat_o_sum + z0;
end
// once cycle of 5 is complete, output the fresh sum (after saturation)
if (stage6 == 0) begin
signal_o <= dat_o_full;
end
end
dat_o <= (shortcut==1'b1) ? dat_i_filtered[SIGNALSHIFT+SIGNALBITS-1:SIGNALSHIFT] : signal_o;
end
endmodule
|
module c432 ( N1, N4, N8, N11, N14, N17, N21, N24, N27, N30, N34, N37, N40,
N43, N47, N50, N53, N56, N60, N63, N66, N69, N73, N76, N79, N82, N86,
N89, N92, N95, N99, N102, N105, N108, N112, N115, N223, N329, N370,
N421, N430, N431, N432 );
input N1, N4, N8, N11, N14, N17, N21, N24, N27, N30, N34, N37, N40, N43, N47,
N50, N53, N56, N60, N63, N66, N69, N73, N76, N79, N82, N86, N89, N92,
N95, N99, N102, N105, N108, N112, N115;
output N223, N329, N370, N421, N430, N431, N432;
wire n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120,
n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131,
n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142,
n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164,
n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186,
n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204;
AO21X1 U111 ( .IN1(n110), .IN2(n111), .IN3(n112), .Q(N432) );
INVX0 U112 ( .INP(n113), .ZN(n112) );
AO221X1 U113 ( .IN1(n114), .IN2(n115), .IN3(n116), .IN4(n117), .IN5(n118),
.Q(n110) );
INVX0 U114 ( .INP(n119), .ZN(n118) );
INVX0 U115 ( .INP(n120), .ZN(n116) );
NAND3X0 U116 ( .IN1(n113), .IN2(n111), .IN3(n121), .QN(N431) );
NAND3X0 U117 ( .IN1(n119), .IN2(n117), .IN3(n122), .QN(n121) );
NOR2X0 U118 ( .IN1(n123), .IN2(n124), .QN(N421) );
OA221X1 U119 ( .IN1(n125), .IN2(n126), .IN3(n127), .IN4(n128), .IN5(n129),
.Q(n124) );
INVX0 U120 ( .INP(N370), .ZN(n125) );
NOR4X0 U121 ( .IN1(N108), .IN2(N430), .IN3(n114), .IN4(n122), .QN(n123) );
NAND2X0 U122 ( .IN1(n120), .IN2(n115), .QN(n122) );
AO222X1 U123 ( .IN1(N86), .IN2(N329), .IN3(n130), .IN4(n131), .IN5(N92),
.IN6(N370), .Q(n115) );
NAND2X0 U124 ( .IN1(N82), .IN2(n132), .QN(n130) );
AO221X1 U125 ( .IN1(N73), .IN2(N329), .IN3(N79), .IN4(N370), .IN5(n133), .Q(
n120) );
AOI222X1 U126 ( .IN1(n134), .IN2(n135), .IN3(N99), .IN4(N329), .IN5(N105),
.IN6(N370), .QN(n114) );
NAND2X0 U127 ( .IN1(N95), .IN2(n132), .QN(n135) );
NAND4X0 U128 ( .IN1(n119), .IN2(n117), .IN3(n113), .IN4(n111), .QN(N430) );
AO221X1 U129 ( .IN1(N34), .IN2(N329), .IN3(N40), .IN4(N370), .IN5(n136), .Q(
n111) );
AO222X1 U130 ( .IN1(N21), .IN2(N329), .IN3(n137), .IN4(n138), .IN5(N27),
.IN6(N370), .Q(n113) );
NAND2X0 U131 ( .IN1(N17), .IN2(n132), .QN(n137) );
AO221X1 U132 ( .IN1(N60), .IN2(N329), .IN3(N66), .IN4(N370), .IN5(n139), .Q(
n117) );
AO222X1 U133 ( .IN1(N47), .IN2(N329), .IN3(n140), .IN4(n141), .IN5(N53),
.IN6(N370), .Q(n119) );
NAND2X0 U134 ( .IN1(N43), .IN2(n132), .QN(n140) );
NAND4X0 U135 ( .IN1(n142), .IN2(n143), .IN3(n144), .IN4(n145), .QN(N370) );
AND4X1 U136 ( .IN1(n146), .IN2(n147), .IN3(n148), .IN4(n149), .Q(n145) );
OR4X1 U137 ( .IN1(n150), .IN2(n151), .IN3(N115), .IN4(n152), .Q(n149) );
INVX0 U138 ( .INP(n153), .ZN(n152) );
NOR2X0 U139 ( .IN1(n127), .IN2(n154), .QN(n150) );
NAND3X0 U140 ( .IN1(n155), .IN2(n156), .IN3(n157), .QN(n148) );
INVX0 U141 ( .INP(N105), .ZN(n156) );
NAND2X0 U142 ( .IN1(N329), .IN2(n158), .QN(n155) );
NAND3X0 U143 ( .IN1(n159), .IN2(n160), .IN3(n161), .QN(n147) );
INVX0 U144 ( .INP(N92), .ZN(n160) );
NAND2X0 U145 ( .IN1(N329), .IN2(n162), .QN(n159) );
OR3X1 U146 ( .IN1(n163), .IN2(N40), .IN3(n136), .Q(n146) );
NOR2X0 U147 ( .IN1(n127), .IN2(n164), .QN(n163) );
AOI222X1 U148 ( .IN1(n165), .IN2(n166), .IN3(n167), .IN4(n168), .IN5(n169),
.IN6(n170), .QN(n144) );
INVX0 U149 ( .INP(n139), .ZN(n170) );
OA21X1 U150 ( .IN1(n171), .IN2(n127), .IN3(n172), .Q(n169) );
INVX0 U151 ( .INP(N66), .ZN(n172) );
INVX0 U152 ( .INP(n133), .ZN(n168) );
AOI21X1 U153 ( .IN1(n173), .IN2(N329), .IN3(N79), .QN(n167) );
OA21X1 U154 ( .IN1(n174), .IN2(n127), .IN3(n175), .Q(n165) );
INVX0 U155 ( .INP(N27), .ZN(n175) );
NAND3X0 U156 ( .IN1(n176), .IN2(n177), .IN3(n178), .QN(n143) );
INVX0 U157 ( .INP(N53), .ZN(n177) );
OR2X1 U158 ( .IN1(n127), .IN2(n179), .Q(n176) );
NAND3X0 U159 ( .IN1(n180), .IN2(n126), .IN3(n129), .QN(n142) );
INVX0 U160 ( .INP(N14), .ZN(n126) );
NAND2X0 U161 ( .IN1(N329), .IN2(n181), .QN(n180) );
INVX0 U162 ( .INP(n127), .ZN(N329) );
NOR4X0 U163 ( .IN1(n182), .IN2(n164), .IN3(n183), .IN4(n184), .QN(n127) );
NAND4X0 U164 ( .IN1(n185), .IN2(n173), .IN3(n162), .IN4(n158), .QN(n184) );
NAND2X0 U165 ( .IN1(n157), .IN2(n186), .QN(n158) );
INVX0 U166 ( .INP(N99), .ZN(n186) );
OA21X1 U167 ( .IN1(n132), .IN2(n187), .IN3(N95), .Q(n157) );
NAND2X0 U168 ( .IN1(n161), .IN2(n188), .QN(n162) );
INVX0 U169 ( .INP(N86), .ZN(n188) );
AOI21X1 U170 ( .IN1(N223), .IN2(n131), .IN3(n189), .QN(n161) );
OR2X1 U171 ( .IN1(n133), .IN2(N73), .Q(n173) );
AO21X1 U172 ( .IN1(N63), .IN2(N223), .IN3(n190), .Q(n133) );
NAND3X0 U173 ( .IN1(n153), .IN2(n154), .IN3(N108), .QN(n185) );
INVX0 U174 ( .INP(N112), .ZN(n154) );
NAND2X0 U175 ( .IN1(N102), .IN2(N223), .QN(n153) );
OR3X1 U176 ( .IN1(n171), .IN2(n179), .IN3(n174), .Q(n183) );
NOR2X0 U177 ( .IN1(n191), .IN2(N21), .QN(n174) );
INVX0 U178 ( .INP(n166), .ZN(n191) );
OA21X1 U179 ( .IN1(n132), .IN2(n192), .IN3(N17), .Q(n166) );
NOR2X0 U180 ( .IN1(n193), .IN2(N47), .QN(n179) );
INVX0 U181 ( .INP(n178), .ZN(n193) );
OA21X1 U182 ( .IN1(n132), .IN2(n194), .IN3(N43), .Q(n178) );
INVX0 U183 ( .INP(N223), .ZN(n132) );
NOR2X0 U184 ( .IN1(n139), .IN2(N60), .QN(n171) );
AO21X1 U185 ( .IN1(N50), .IN2(N223), .IN3(n195), .Q(n139) );
NOR2X0 U186 ( .IN1(n136), .IN2(N34), .QN(n164) );
AO21X1 U187 ( .IN1(N24), .IN2(N223), .IN3(n196), .Q(n136) );
INVX0 U188 ( .INP(n181), .ZN(n182) );
NAND2X0 U189 ( .IN1(n129), .IN2(n128), .QN(n181) );
INVX0 U190 ( .INP(N8), .ZN(n128) );
AOI21X1 U191 ( .IN1(N1), .IN2(N223), .IN3(n197), .QN(n129) );
NAND4X0 U192 ( .IN1(n198), .IN2(n131), .IN3(n199), .IN4(n200), .QN(N223) );
OA221X1 U193 ( .IN1(N24), .IN2(n196), .IN3(N102), .IN4(n151), .IN5(n201),
.Q(n200) );
OA22X1 U194 ( .IN1(N50), .IN2(n195), .IN3(N63), .IN4(n190), .Q(n201) );
INVX0 U195 ( .INP(N69), .ZN(n190) );
INVX0 U196 ( .INP(N56), .ZN(n195) );
INVX0 U197 ( .INP(N108), .ZN(n151) );
INVX0 U198 ( .INP(N30), .ZN(n196) );
NOR3X0 U199 ( .IN1(n187), .IN2(n192), .IN3(n194), .QN(n199) );
INVX0 U200 ( .INP(n141), .ZN(n194) );
NAND2X0 U201 ( .IN1(n202), .IN2(N43), .QN(n141) );
INVX0 U202 ( .INP(N37), .ZN(n202) );
INVX0 U203 ( .INP(n138), .ZN(n192) );
NAND2X0 U204 ( .IN1(n203), .IN2(N17), .QN(n138) );
INVX0 U205 ( .INP(N11), .ZN(n203) );
INVX0 U206 ( .INP(n134), .ZN(n187) );
NAND2X0 U207 ( .IN1(n204), .IN2(N95), .QN(n134) );
INVX0 U208 ( .INP(N89), .ZN(n204) );
OR2X1 U209 ( .IN1(N76), .IN2(n189), .Q(n131) );
INVX0 U210 ( .INP(N82), .ZN(n189) );
OR2X1 U211 ( .IN1(n197), .IN2(N1), .Q(n198) );
INVX0 U212 ( .INP(N4), .ZN(n197) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_4_V
`define SKY130_FD_SC_HS__SEDFXTP_4_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_4 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_4 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_4_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module up_busif (
// bus interface
up_rstn,
up_clk,
upif_sel,
upif_rwn,
upif_addr,
upif_wdata,
upif_wack,
upif_rdata,
upif_rack,
// block interface
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack,
// pcore identifier
pid);
// parameters
parameter PCORE_VERSION = 32'h00040061;
parameter PCORE_ID = 0;
// bus interface
input up_rstn;
input up_clk;
input upif_sel;
input upif_rwn;
input [31:0] upif_addr;
input [31:0] upif_wdata;
output upif_wack;
output [31:0] upif_rdata;
output upif_rack;
// block interface
output up_sel;
output up_wr;
output [13:0] up_addr;
output [31:0] up_wdata;
input [31:0] up_rdata;
input up_ack;
// pcore identifier
output [31:0] pid;
// internal registers
reg upif_wack = 'd0;
reg upif_rack = 'd0;
reg [31:0] upif_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel = 'd0;
reg up_wr = 'd0;
reg [13:0] up_addr = 'd0;
reg [31:0] up_wdata = 'd0;
reg up_access = 'd0;
reg [ 2:0] up_access_count = 'd0;
reg up_access_ack = 'd0;
reg [31:0] up_access_rdata = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_int_ack = 'd0;
reg [31:0] up_int_rdata = 'd0;
// internal signals
wire [31:0] up_rdata_s;
wire up_ack_s;
wire up_sel_s;
wire up_wr_s;
// pcore identifier
assign pid = PCORE_ID;
// bus interface read and ack registers
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
upif_wack <= 'd0;
upif_rack <= 'd0;
upif_rdata <= 'd0;
end else begin
upif_wack <= (up_ack_s | up_access_ack) & ~upif_rwn;
upif_rack <= (up_ack_s | up_access_ack) & upif_rwn;
upif_rdata <= up_rdata_s | up_access_rdata;
end
end
// usuable format from the bus interface signals
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_sel_d <= 'd0;
up_sel <= 'd0;
up_wr <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel_d <= upif_sel;
up_sel <= upif_sel & ~up_sel_d;
up_wr <= ~upif_rwn;
up_addr <= upif_addr[15:2];
up_wdata <= upif_wdata;
end
end
// combine up read and ack from all the blocks
assign up_rdata_s = up_rdata | up_int_rdata;
assign up_ack_s = up_ack | up_int_ack;
// 8 clock cycles access time out to release bus
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_access <= 'd0;
up_access_count <= 'd0;
up_access_ack <= 'd0;
up_access_rdata <= 'd0;
end else begin
if (up_sel == 1'b1) begin
up_access <= 1'b1;
end else if (up_ack_s == 1'b1) begin
up_access <= 1'b0;
end
if (up_access == 1'b1) begin
up_access_count <= up_access_count + 1'b1;
end else begin
up_access_count <= 3'd0;
end
if ((up_access_count == 3'h7) && (up_ack_s == 1'b0)) begin
up_access_ack <= 1'b1;
up_access_rdata <= {2{16'hdead}};
end else begin
up_access_ack <= 1'b0;
up_access_rdata <= 32'd0;
end
end
end
// decode block select
assign up_sel_s = (up_addr[13:4] == 10'd0) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
// write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_scratch <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h2)) begin
up_scratch <= up_wdata;
end
end
end
// read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_int_ack <= 'd0;
up_int_rdata <= 'd0;
end else begin
up_int_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[3:0])
4'h0: up_int_rdata <= PCORE_VERSION;
4'h1: up_int_rdata <= PCORE_ID;
4'h2: up_int_rdata <= up_scratch;
default: up_int_rdata <= 32'd0;
endcase
end else begin
up_int_rdata <= 32'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NOR2B_FUNCTIONAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2b (
VPWR,
VGND,
Y ,
A ,
B_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B_N ;
// Local signals
wire Y not0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_FUNCTIONAL_V |
// MBT 9-7-2014
//
// two element fifo
//
// helpful interface on both input and output
//
// input : ready/valid flow control (rv->&)
// output: valid->yumi flow control ( v->r)
//
// see https://github.com/bespoke-silicon-group/basejump_stl/blob/master/docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf
// to understand the flow control standards in BaseJump STL.
//
// INPUTS: although this module's inputs adheres to
// ready/valid protocol where both sender and receiver
// AND the two signals together to determine
// if transaction happened; in some cases, we
// know that the sender takes into account the
// ready signal before sending out valid, and the
// check is unnecessary. We use ready_THEN_valid_p
// to remove the check if it is unnecessary.
//
//
// note: ~v_o == fifo is empty.
//
`include "bsg_defines.v"
module bsg_two_fifo #(parameter `BSG_INV_PARAM(width_p)
, parameter verbose_p=0
// whether we should allow simultaneous enque and deque on full
, parameter allow_enq_deq_on_full_p=0
// necessarily, if we allow enq on ready low, then
// we are not using a ready/valid protocol
, parameter ready_THEN_valid_p=allow_enq_deq_on_full_p
)
(input clk_i
, input reset_i
// input side
, output ready_o // early
, input [width_p-1:0] data_i // late
, input v_i // late
// output side
, output v_o // early
, output[width_p-1:0] data_o // early
, input yumi_i // late
);
wire deq_i = yumi_i;
wire enq_i;
logic head_r, tail_r;
logic empty_r, full_r;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(2)
,.read_write_same_addr_p(allow_enq_deq_on_full_p)
) mem_1r1w
(.w_clk_i (clk_i )
,.w_reset_i(reset_i)
,.w_v_i (enq_i )
,.w_addr_i (tail_r )
,.w_data_i (data_i )
,.r_v_i (~empty_r)
,.r_addr_i (head_r )
,.r_data_o (data_o )
);
assign v_o = ~empty_r;
assign ready_o = ~full_r;
if (ready_THEN_valid_p)
assign enq_i = v_i;
else
assign enq_i = v_i & ~full_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
tail_r <= 1'b0;
head_r <= 1'b0;
empty_r <= 1'b1;
full_r <= 1'b0;
end
else
begin
if (enq_i)
tail_r <= ~tail_r;
if (deq_i)
head_r <= ~head_r;
// logic simplifies nicely for 2 element case
empty_r <= ( empty_r & ~enq_i)
| (~full_r & deq_i & ~enq_i);
if (allow_enq_deq_on_full_p)
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~(deq_i^enq_i));
else
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~deq_i);
end // else: !if(reset_i)
end // always_ff @
// synopsys translate_off
always_ff @(posedge clk_i)
begin
if (~reset_i)
begin
assert ({empty_r, deq_i} !== 2'b11)
else $error("invalid deque on empty fifo ", empty_r, deq_i);
if (allow_enq_deq_on_full_p)
begin
assert ({full_r,enq_i,deq_i} !== 3'b110)
else $error("invalid enque on full fifo ", full_r, enq_i);
end
else
assert ({full_r,enq_i} !== 2'b11)
else $error("invalid enque on full fifo ", full_r, enq_i);
assert ({full_r,empty_r} !== 2'b11)
else $error ("fifo full and empty at same time ", full_r, empty_r);
end // if (~reset_i)
end // always_ff @
always_ff @(posedge clk_i)
if (verbose_p)
begin
if (enq_i)
$display("### %m enq %x onto fifo",data_i);
if (deq_i)
$display("### %m deq %x from fifo",data_o);
end
// for debugging
wire [31:0] num_elements_debug = full_r + (empty_r==0);
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_two_fifo)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A311OI_PP_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_PP_SYMBOL_V
|
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, writeR7, inR7, in, reset); // Modify to include R7 effects
output [15:0] out1, out2;
input [15:0] in, inR7;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset, writeR7;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [6:0] writeLines;
wire [7:0] writeLinesInit;
decode8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, inR7, writeR7, reset);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the advanced register file
// Import the modules that will be tested for in this testbench
`include "regfileww.v"
// IMPORTANT: To run this, try: ncverilog -f regfileww.f +gui
module tb_regfileww();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the advanced register file
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// rd1data or rd2data output signals
wire [127:0] rd1_d,rd2_d;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, wren,rd1en,rd2en;
reg clock,wr_en,r1_en,r2_en;
// wrdata
reg [127:0] wr_d;
// wraddr, rd1addr, rd2addr
reg [4:0] w_addr,r1_addr,r2_addr;
// wrbyteen
reg [15:0] wrbytn;
// 32 Words of 128-bits
reg r[0:31];
reg [127:0] r_row;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#2.5 clock = 0;
#2.5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
RegFileWW rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
rd1_d,rd2_d,wr_d,r1_addr,r2_addr,w_addr,r1_en,r2_en,
wr_en,wrbytn,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/*
for(count=0;count<=size_of_input;count=count+1)
begin
#10
//$display("Next");
r_row=r[count];
$display("Next",r_row);
end
*/
// Write to 8 data locations
#20
wr_d=128'h787897ea12fec60cae787897eac22354;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd0;
wrbytn=16'hff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h72348973465465465464645664654666;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd1;
wrbytn=16'h7f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48545618548486131875531264684565;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd2;
wrbytn=16'h3f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48646517897894613514684987984614;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd3;
wrbytn=16'h1f;
r1_en=0;
r2_en=0;
wr_en=1;
// ===================================
#20
wr_d=128'hcaacecce09c4ae54864c6ae464ca3544;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd4;
wrbytn=16'hfff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hceac45564c1ae151c53ae15c153ae1c4;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd5;
wrbytn=16'h7ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hdc46da456c1ad561c65ad1c6ad61c455;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd6;
wrbytn=16'h3ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
//wr_d=128'h18342cad864c65da4654cad646c5d4a564cd56ca552;
wr_d=128'hc65da4654cad646c5d4a564cd56ca552;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd7;
wrbytn=16'h1ff;
r1_en=0;
r2_en=0;
wr_en=1;
// Read the data from the aforementioned locations
#20
wr_d=128'd12345;
r1_addr=5'd0;
r2_addr=5'd7;
w_addr=5'd20;
wrbytn=16'hffff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd1;
r2_addr=5'd6;
w_addr=5'd20;
wrbytn=16'h7fff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd2;
r2_addr=5'd5;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd3;
r2_addr=5'd4;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// ====================================================
#20
wr_d=128'd12345;
r1_addr=5'd4;
r2_addr=5'd3;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd5;
r2_addr=5'd2;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd6;
r2_addr=5'd1;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd7;
r2_addr=5'd0;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
// CREATED "Wed Nov 06 13:53:27 2013"
module PPgen_9bits(
Single,
Double,
Negate,
Y,
Sign,
PP
);
input wire Single;
input wire Double;
input wire Negate;
input wire [7:0] Y;
output wire Sign;
output wire [8:0] PP;
wire [8:0] PP_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_19;
assign SYNTHESIZED_WIRE_19 = 0;
PPgen b2v_inst1(
.Single(Single),
.Yi(Y[7]),
.Double(Double),
.Yi_m1(Y[7]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_14));
HalfAdder b2v_inst11(
.A(SYNTHESIZED_WIRE_0),
.Cin(SYNTHESIZED_WIRE_1),
.Cout(SYNTHESIZED_WIRE_3),
.Sum(PP_ALTERA_SYNTHESIZED[1]));
HalfAdder b2v_inst12(
.A(SYNTHESIZED_WIRE_2),
.Cin(SYNTHESIZED_WIRE_3),
.Cout(SYNTHESIZED_WIRE_5),
.Sum(PP_ALTERA_SYNTHESIZED[2]));
HalfAdder b2v_inst13(
.A(SYNTHESIZED_WIRE_4),
.Cin(SYNTHESIZED_WIRE_5),
.Cout(SYNTHESIZED_WIRE_7),
.Sum(PP_ALTERA_SYNTHESIZED[3]));
HalfAdder b2v_inst14(
.A(SYNTHESIZED_WIRE_6),
.Cin(SYNTHESIZED_WIRE_7),
.Cout(SYNTHESIZED_WIRE_9),
.Sum(PP_ALTERA_SYNTHESIZED[4]));
HalfAdder b2v_inst15(
.A(SYNTHESIZED_WIRE_8),
.Cin(SYNTHESIZED_WIRE_9),
.Cout(SYNTHESIZED_WIRE_11),
.Sum(PP_ALTERA_SYNTHESIZED[5]));
HalfAdder b2v_inst16(
.A(SYNTHESIZED_WIRE_10),
.Cin(SYNTHESIZED_WIRE_11),
.Cout(SYNTHESIZED_WIRE_13),
.Sum(PP_ALTERA_SYNTHESIZED[6]));
HalfAdder b2v_inst17(
.A(SYNTHESIZED_WIRE_12),
.Cin(SYNTHESIZED_WIRE_13),
.Cout(SYNTHESIZED_WIRE_15),
.Sum(PP_ALTERA_SYNTHESIZED[7]));
HalfAdder b2v_inst18(
.A(SYNTHESIZED_WIRE_14),
.Cin(SYNTHESIZED_WIRE_15),
.Sum(PP_ALTERA_SYNTHESIZED[8]));
PPgen b2v_inst2(
.Single(Single),
.Yi(Y[7]),
.Double(Double),
.Yi_m1(Y[6]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_12));
HalfAdder b2v_inst20(
.A(SYNTHESIZED_WIRE_16),
.Cin(Negate),
.Cout(SYNTHESIZED_WIRE_1),
.Sum(PP_ALTERA_SYNTHESIZED[0]));
PPgen b2v_inst3(
.Single(Single),
.Yi(Y[5]),
.Double(Double),
.Yi_m1(Y[4]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_8));
NAND8_reducer b2v_inst36(
.InY(Y),
.Reduced_NAND(SYNTHESIZED_WIRE_17));
assign SYNTHESIZED_WIRE_18 = ~(Negate & Double & SYNTHESIZED_WIRE_17);
PPgen b2v_inst4(
.Single(Single),
.Yi(Y[6]),
.Double(Double),
.Yi_m1(Y[5]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_10));
assign Sign = SYNTHESIZED_WIRE_18 & PP_ALTERA_SYNTHESIZED[8];
PPgen b2v_inst5(
.Single(Single),
.Yi(Y[4]),
.Double(Double),
.Yi_m1(Y[3]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_6));
PPgen b2v_inst6(
.Single(Single),
.Yi(Y[3]),
.Double(Double),
.Yi_m1(Y[2]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_4));
PPgen b2v_inst7(
.Single(Single),
.Yi(Y[2]),
.Double(Double),
.Yi_m1(Y[1]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_2));
PPgen b2v_inst8(
.Single(Single),
.Yi(Y[1]),
.Double(Double),
.Yi_m1(Y[0]),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_0));
PPgen b2v_inst9(
.Single(Single),
.Yi(Y[0]),
.Double(Double),
.Yi_m1(SYNTHESIZED_WIRE_19),
.Negate(Negate),
.PPi(SYNTHESIZED_WIRE_16));
assign PP = PP_ALTERA_SYNTHESIZED;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O41AI_BEHAVIORAL_PP_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_BEHAVIORAL_PP_V |
module StepDecoder(output [15:0] TimeSteps, input [3:0]StepCounter);
and and1(TimeSteps[0], ~StepCounter[3], ~StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and2(TimeSteps[1], ~StepCounter[3], ~StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and3(TimeSteps[2], ~StepCounter[3], ~StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and4(TimeSteps[3], ~StepCounter[3], ~StepCounter[2], StepCounter[1], StepCounter[0]);
and and5(TimeSteps[4], ~StepCounter[3], StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and6(TimeSteps[5], ~StepCounter[3], StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and7(TimeSteps[6], ~StepCounter[3], StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and8(TimeSteps[7], ~StepCounter[3], StepCounter[2], StepCounter[1], StepCounter[0]);
and and9(TimeSteps[8], StepCounter[3], ~StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and10(TimeSteps[9], StepCounter[3], ~StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and11(TimeSteps[10], StepCounter[3], ~StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and12(TimeSteps[11], StepCounter[3], ~StepCounter[2], StepCounter[1], StepCounter[0]);
and and13(TimeSteps[12], StepCounter[3], StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and14(TimeSteps[13], StepCounter[3], StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and15(TimeSteps[14], StepCounter[3], StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and16(TimeSteps[15], StepCounter[3], StepCounter[2], StepCounter[1], StepCounter[0]);
endmodule
|
module edge_detect(
input clk_50M, //系统时钟
input rst_n, //复位信号，低电平有效
input rx_int, //需要检测的输入信号
output pos_rx_int, //检测到上升沿信号
output neg_rx_int, //检测到下降沿信号
output doub_rx_int //双边检测信号
);
reg clk_r=1'b0;
reg [21:0] cnt;
always @(posedge clk_50M or negedge rst_n) //将50MHz时钟分频，留作后面信号clk使用
if(!rst_n)
cnt <= 22'b0;
else
if(cnt == 22'd4194303)
cnt <= 22'b0;
else
cnt <= cnt +1'b1;
//用来寄存分频时钟信号
always @(posedge clk_50M or negedge rst_n)
if(!rst_n)
clk_r <= 1'b0;
else
if(cnt == 22'd4194300)
clk_r <= ~clk_r;
else
clk_r <= clk_r;
assign clk = clk_r ; //获取分频时钟50000000/4191304=11.9209Hz（人眼能分辨）
/************************************************************************
9~30行代码为优化时钟代码，烧写程序后通过引脚分配来检验程序的正确性
故将50M时钟分频到10Hz左右，能够明显判断。若只需掌握边沿检测原理可
直接使用系统时钟clk。代码可删去，并在输入输出端口进行修改
************************************************************************/
reg rx_int0,rx_int1,rx_int2; //在内部新建寄存器，用来暂存数据信号
//若这里只用到两个寄存器变量，那么边沿检测信号是实时输出的
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rx_int0 <= 1'b0;
rx_int1 <= 1'b0;
rx_int2 <= 1'b0;
end
else
begin
rx_int0 <= rx_int; //初始值信号赋值给0
rx_int1 <= rx_int0; //0的前一个周期的信号赋给1
rx_int2 <= rx_int1; //1的前一个周期的信号赋给2
end
end
assign pos_rx_int = rx_int1 & ~rx_int2; //前一个周期的信号为0，当前周期信号为1，则上升沿检测信号为1（有效），即检测到一个上升沿信号
assign neg_rx_int = ~rx_int1 & rx_int2; //前一个周期的信号为1，当前周期信号为0，则下降沿检测信号为1（有效），即检测到一个下降沿信号
assign doub_rx_int = rx_int1 ^ rx_int2; //两次变量发生变化时，双边检测信号为1（有效），即检测到上升沿、和下降沿信号
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr36(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [35:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 36'hF0F0AA55;
end
else if(ena) begin
word[35] <= word[0];
word[34] <= word[35];
word[33] <= word[34];
word[32] <= word[33];
word[31] <= word[32];
word[30] <= word[31];
word[29] <= word[30];
word[28] <= word[29];
word[27] <= word[28];
word[26] <= word[27];
word[25] <= word[26];
word[24] <= word[25] ^ word[0];
word[23] <= word[24];
word[22] <= word[23];
word[21] <= word[22];
word[20] <= word[21];
word[19] <= word[20];
word[18] <= word[19];
word[17] <= word[18];
word[16] <= word[17];
word[15] <= word[16];
word[14] <= word[15];
word[13] <= word[14];
word[12] <= word[13];
word[11] <= word[12];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6];
word[4] <= word[5];
word[3] <= word[4];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_SYMBOL_V
`define SKY130_FD_SC_MS__NAND2B_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_SYMBOL_V
|
/*
* Copyright 2013-2021 Robert Newgard
*
* This file is part of fcs.
*
* fcs is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fcs is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with fcs. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "fcs32_1.v"
`include "fcs32_brev.v"
module uut_1_bitp
(
output wire [31:0] res_o,
output wire [31:0] exp_o,
output wire [31:0] obs_o,
output wire val_o,
input wire [31:0] data_i,
input wire sof_i,
input wire eof_i,
input wire bstb_i,
input wire bclk_i
);
/* -----------------------------------------------------------
parameters
------------------------------------------------------------*/
localparam LO = 1'b0;
localparam HI = 1'b1;
localparam [31:0] ZEROS = {32{LO}};
localparam [31:0] ONES = {32{HI}};
localparam FIRST = 4;
localparam LAST = 34;
/* -----------------------------------------------------------
net declarations
------------------------------------------------------------*/
reg dat_z1;
reg bgn_z1;
reg end_z1;
reg [31:0] exp_z2;
reg [31:0] fcs_z2;
reg end_z2;
reg [31:0] exp_z3;
reg [31:0] fcs_z3;
reg val_z3;
reg [31:0] exp[FIRST:LAST];
reg [31:0] crc[FIRST:LAST];
reg val[FIRST:LAST];
integer bit_cnt;
/* -----------------------------------------------------------
input assignments
------------------------------------------------------------*/
/* -----------------------------------------------------------
Pipeline
------------------------------------------------------------*/
always @ (posedge bclk_i) begin
if (bstb_i == HI) begin
bit_cnt <= 0;
end else begin
bit_cnt <= bit_cnt + 1;
end
bgn_z1 <= LO;
end_z1 <= LO;
dat_z1 <= data_i[bit_cnt + 24];
if (bit_cnt == 7) begin
end_z1 <= eof_i;
end else if (bit_cnt == 0) begin
bgn_z1 <= sof_i;
end
end_z2 <= end_z1;
if (end_z1 == HI) begin
exp_z2[31:0] <= data_i[31:0];
end
if (bgn_z1 == HI) begin
fcs_z2[31:0] <= fcs32_1(dat_z1, ONES[31:0]);
end else begin
fcs_z2[31:0] <= fcs32_1(dat_z1, fcs_z2[31:0]);
end
val_z3 <= end_z2;
exp_z3[31:0] <= exp_z2[31:0];
if (end_z2 == HI) begin
fcs_z3[31:0] <= fcs32_brev(fcs_z2[31:0]);
end
end
generate
genvar i;
for (i = FIRST ; i <= LAST ; i = i + 1) begin : ppln_delay
always @ (posedge bclk_i) begin
if (i == FIRST) begin
exp[i][31:0] <= exp_z3[31:0];
crc[i][31:0] <= fcs_z3[31:0];
val[i] <= val_z3;
end else begin
exp[i][31:0] <= exp[i - 1][31:0];
crc[i][31:0] <= crc[i - 1][31:0];
val[i] <= val[i - 1];
end
end
end
endgenerate
/* -----------------------------------------------------------
output assignments
------------------------------------------------------------*/
always @ (*) begin
res_o[31:0] = fcs_z2[31:0];
exp_o[31:0] = exp[LAST][31:0];
obs_o[31:0] = crc[LAST][31:0];
val_o = val[LAST];
end
endmodule
|
module artemis_ddr3 (
input clk_333mhz,
input board_rst,
output calibration_done,
output usr_clk,
output rst,
//Memory Interface
inout [7:0] ddr3_dram_dq,
output [13:0] ddr3_dram_a,
output [2:0] ddr3_dram_ba,
output ddr3_dram_ras_n,
output ddr3_dram_cas_n,
output ddr3_dram_we_n,
output ddr3_dram_odt,
output ddr3_dram_reset_n,
output ddr3_dram_cke,
output ddr3_dram_dm,
inout ddr3_rzq,
inout ddr3_zio,
inout ddr3_dram_dqs,
inout ddr3_dram_dqs_n,
output ddr3_dram_ck,
output ddr3_dram_ck_n,
//Port Interfaces
input p0_cmd_clk,
input p0_cmd_en,
input [2:0] p0_cmd_instr,
input [5:0] p0_cmd_bl,
input [29:0] p0_cmd_byte_addr,
output p0_cmd_empty,
output p0_cmd_full,
input p0_wr_clk,
input p0_wr_en,
input [3:0] p0_wr_mask,
input [31:0] p0_wr_data,
output p0_wr_full,
output p0_wr_empty,
output [6:0] p0_wr_count,
output p0_wr_underrun,
output p0_wr_error,
input p0_rd_clk,
input p0_rd_en,
output [31:0] p0_rd_data,
output p0_rd_full,
output p0_rd_empty,
output [6:0] p0_rd_count,
output p0_rd_overflow,
output p0_rd_error,
input p1_cmd_clk,
input p1_cmd_en,
input [2:0] p1_cmd_instr,
input [5:0] p1_cmd_bl,
input [29:0] p1_cmd_byte_addr,
output p1_cmd_empty,
output p1_cmd_full,
input p1_wr_clk,
input p1_wr_en,
input [3:0] p1_wr_mask,
input [31:0] p1_wr_data,
output p1_wr_full,
output p1_wr_empty,
output [6:0] p1_wr_count,
output p1_wr_underrun,
output p1_wr_error,
input p1_rd_clk,
input p1_rd_en,
output [31:0] p1_rd_data,
output p1_rd_full,
output p1_rd_empty,
output [6:0] p1_rd_count,
output p1_rd_overflow,
output p1_rd_error,
input p2_cmd_clk,
input p2_cmd_en,
input [2:0] p2_cmd_instr,
input [5:0] p2_cmd_bl,
input [29:0] p2_cmd_byte_addr,
output p2_cmd_empty,
output p2_cmd_full,
input p2_wr_clk,
input p2_wr_en,
input [3:0] p2_wr_mask,
input [31:0] p2_wr_data,
output p2_wr_full,
output p2_wr_empty,
output [6:0] p2_wr_count,
output p2_wr_underrun,
output p2_wr_error,
input p3_cmd_clk,
input p3_cmd_en,
input [2:0] p3_cmd_instr,
input [5:0] p3_cmd_bl,
input [29:0] p3_cmd_byte_addr,
output p3_cmd_empty,
output p3_cmd_full,
input p3_wr_clk,
input p3_wr_en,
input [3:0] p3_wr_mask,
input [31:0] p3_wr_data,
output p3_wr_full,
output p3_wr_empty,
output [6:0] p3_wr_count,
output p3_wr_underrun,
output p3_wr_error,
input p4_cmd_clk,
input p4_cmd_en,
input [2:0] p4_cmd_instr,
input [5:0] p4_cmd_bl,
input [29:0] p4_cmd_byte_addr,
output p4_cmd_empty,
output p4_cmd_full,
input p4_rd_clk,
input p4_rd_en,
output [31:0] p4_rd_data,
output p4_rd_full,
output p4_rd_empty,
output [6:0] p4_rd_count,
output p4_rd_overflow,
output p4_rd_error,
input p5_cmd_clk,
input p5_cmd_en,
input [2:0] p5_cmd_instr,
input [5:0] p5_cmd_bl,
input [29:0] p5_cmd_byte_addr,
output p5_cmd_empty,
output p5_cmd_full,
input p5_rd_clk,
input p5_rd_en,
output [31:0] p5_rd_data,
output p5_rd_full,
output p5_rd_empty,
output [6:0] p5_rd_count,
output p5_rd_overflow,
output p5_rd_error
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_ae.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No `defines in this module
module ent_ae
//
// Generated module inst_ae
//
(
input wire [4:0] port_ae_2, // Use internally test2, no port generated
input wire [3:0] port_ae_5, // Bus, single bits go to outside
input wire [3:0] port_ae_6, // Conflicting definition
input wire [5:0] sig_07, // Conflicting definition, IN false!
input wire [8:2] sig_08, // VHDL intermediate needed (port name)
input wire [6:0] sig_i_ae, // Input Bus
output wire [7:0] sig_o_ae // Output Bus
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// hps_design_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_mm_interconnect_0 (
input wire [11:0] SMP_CORE_h2f_lw_axi_master_awid, // SMP_CORE_h2f_lw_axi_master.awid
input wire [20:0] SMP_CORE_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] SMP_CORE_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] SMP_CORE_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] SMP_CORE_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] SMP_CORE_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] SMP_CORE_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] SMP_CORE_h2f_lw_axi_master_awprot, // .awprot
input wire SMP_CORE_h2f_lw_axi_master_awvalid, // .awvalid
output wire SMP_CORE_h2f_lw_axi_master_awready, // .awready
input wire [11:0] SMP_CORE_h2f_lw_axi_master_wid, // .wid
input wire [31:0] SMP_CORE_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] SMP_CORE_h2f_lw_axi_master_wstrb, // .wstrb
input wire SMP_CORE_h2f_lw_axi_master_wlast, // .wlast
input wire SMP_CORE_h2f_lw_axi_master_wvalid, // .wvalid
output wire SMP_CORE_h2f_lw_axi_master_wready, // .wready
output wire [11:0] SMP_CORE_h2f_lw_axi_master_bid, // .bid
output wire [1:0] SMP_CORE_h2f_lw_axi_master_bresp, // .bresp
output wire SMP_CORE_h2f_lw_axi_master_bvalid, // .bvalid
input wire SMP_CORE_h2f_lw_axi_master_bready, // .bready
input wire [11:0] SMP_CORE_h2f_lw_axi_master_arid, // .arid
input wire [20:0] SMP_CORE_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] SMP_CORE_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] SMP_CORE_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] SMP_CORE_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] SMP_CORE_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] SMP_CORE_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] SMP_CORE_h2f_lw_axi_master_arprot, // .arprot
input wire SMP_CORE_h2f_lw_axi_master_arvalid, // .arvalid
output wire SMP_CORE_h2f_lw_axi_master_arready, // .arready
output wire [11:0] SMP_CORE_h2f_lw_axi_master_rid, // .rid
output wire [31:0] SMP_CORE_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] SMP_CORE_h2f_lw_axi_master_rresp, // .rresp
output wire SMP_CORE_h2f_lw_axi_master_rlast, // .rlast
output wire SMP_CORE_h2f_lw_axi_master_rvalid, // .rvalid
input wire SMP_CORE_h2f_lw_axi_master_rready, // .rready
input wire clk_clk_clk, // clk_clk.clk
input wire PIO_reset_reset_bridge_in_reset_reset, // PIO_reset_reset_bridge_in_reset.reset
input wire SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
output wire [1:0] PIO_s1_address, // PIO_s1.address
output wire PIO_s1_write, // .write
input wire [31:0] PIO_s1_readdata, // .readdata
output wire [31:0] PIO_s1_writedata, // .writedata
output wire PIO_s1_chipselect // .chipselect
);
wire rsp_mux_src_valid; // rsp_mux:src_valid -> SMP_CORE_h2f_lw_axi_master_agent:write_rp_valid
wire [111:0] rsp_mux_src_data; // rsp_mux:src_data -> SMP_CORE_h2f_lw_axi_master_agent:write_rp_data
wire rsp_mux_src_ready; // SMP_CORE_h2f_lw_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> SMP_CORE_h2f_lw_axi_master_agent:write_rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> SMP_CORE_h2f_lw_axi_master_agent:write_rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> SMP_CORE_h2f_lw_axi_master_agent:write_rp_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> SMP_CORE_h2f_lw_axi_master_agent:read_rp_valid
wire [111:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> SMP_CORE_h2f_lw_axi_master_agent:read_rp_data
wire rsp_mux_001_src_ready; // SMP_CORE_h2f_lw_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> SMP_CORE_h2f_lw_axi_master_agent:read_rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> SMP_CORE_h2f_lw_axi_master_agent:read_rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> SMP_CORE_h2f_lw_axi_master_agent:read_rp_endofpacket
wire [31:0] pio_s1_agent_m0_readdata; // PIO_s1_translator:uav_readdata -> PIO_s1_agent:m0_readdata
wire pio_s1_agent_m0_waitrequest; // PIO_s1_translator:uav_waitrequest -> PIO_s1_agent:m0_waitrequest
wire pio_s1_agent_m0_debugaccess; // PIO_s1_agent:m0_debugaccess -> PIO_s1_translator:uav_debugaccess
wire [20:0] pio_s1_agent_m0_address; // PIO_s1_agent:m0_address -> PIO_s1_translator:uav_address
wire [3:0] pio_s1_agent_m0_byteenable; // PIO_s1_agent:m0_byteenable -> PIO_s1_translator:uav_byteenable
wire pio_s1_agent_m0_read; // PIO_s1_agent:m0_read -> PIO_s1_translator:uav_read
wire pio_s1_agent_m0_readdatavalid; // PIO_s1_translator:uav_readdatavalid -> PIO_s1_agent:m0_readdatavalid
wire pio_s1_agent_m0_lock; // PIO_s1_agent:m0_lock -> PIO_s1_translator:uav_lock
wire [31:0] pio_s1_agent_m0_writedata; // PIO_s1_agent:m0_writedata -> PIO_s1_translator:uav_writedata
wire pio_s1_agent_m0_write; // PIO_s1_agent:m0_write -> PIO_s1_translator:uav_write
wire [2:0] pio_s1_agent_m0_burstcount; // PIO_s1_agent:m0_burstcount -> PIO_s1_translator:uav_burstcount
wire pio_s1_agent_rf_source_valid; // PIO_s1_agent:rf_source_valid -> PIO_s1_agent_rsp_fifo:in_valid
wire [112:0] pio_s1_agent_rf_source_data; // PIO_s1_agent:rf_source_data -> PIO_s1_agent_rsp_fifo:in_data
wire pio_s1_agent_rf_source_ready; // PIO_s1_agent_rsp_fifo:in_ready -> PIO_s1_agent:rf_source_ready
wire pio_s1_agent_rf_source_startofpacket; // PIO_s1_agent:rf_source_startofpacket -> PIO_s1_agent_rsp_fifo:in_startofpacket
wire pio_s1_agent_rf_source_endofpacket; // PIO_s1_agent:rf_source_endofpacket -> PIO_s1_agent_rsp_fifo:in_endofpacket
wire pio_s1_agent_rsp_fifo_out_valid; // PIO_s1_agent_rsp_fifo:out_valid -> PIO_s1_agent:rf_sink_valid
wire [112:0] pio_s1_agent_rsp_fifo_out_data; // PIO_s1_agent_rsp_fifo:out_data -> PIO_s1_agent:rf_sink_data
wire pio_s1_agent_rsp_fifo_out_ready; // PIO_s1_agent:rf_sink_ready -> PIO_s1_agent_rsp_fifo:out_ready
wire pio_s1_agent_rsp_fifo_out_startofpacket; // PIO_s1_agent_rsp_fifo:out_startofpacket -> PIO_s1_agent:rf_sink_startofpacket
wire pio_s1_agent_rsp_fifo_out_endofpacket; // PIO_s1_agent_rsp_fifo:out_endofpacket -> PIO_s1_agent:rf_sink_endofpacket
wire pio_s1_agent_rdata_fifo_src_valid; // PIO_s1_agent:rdata_fifo_src_valid -> PIO_s1_agent_rdata_fifo:in_valid
wire [33:0] pio_s1_agent_rdata_fifo_src_data; // PIO_s1_agent:rdata_fifo_src_data -> PIO_s1_agent_rdata_fifo:in_data
wire pio_s1_agent_rdata_fifo_src_ready; // PIO_s1_agent_rdata_fifo:in_ready -> PIO_s1_agent:rdata_fifo_src_ready
wire smp_core_h2f_lw_axi_master_agent_write_cp_valid; // SMP_CORE_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
wire [111:0] smp_core_h2f_lw_axi_master_agent_write_cp_data; // SMP_CORE_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
wire smp_core_h2f_lw_axi_master_agent_write_cp_ready; // router:sink_ready -> SMP_CORE_h2f_lw_axi_master_agent:write_cp_ready
wire smp_core_h2f_lw_axi_master_agent_write_cp_startofpacket; // SMP_CORE_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire smp_core_h2f_lw_axi_master_agent_write_cp_endofpacket; // SMP_CORE_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [111:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire smp_core_h2f_lw_axi_master_agent_read_cp_valid; // SMP_CORE_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire [111:0] smp_core_h2f_lw_axi_master_agent_read_cp_data; // SMP_CORE_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
wire smp_core_h2f_lw_axi_master_agent_read_cp_ready; // router_001:sink_ready -> SMP_CORE_h2f_lw_axi_master_agent:read_cp_ready
wire smp_core_h2f_lw_axi_master_agent_read_cp_startofpacket; // SMP_CORE_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire smp_core_h2f_lw_axi_master_agent_read_cp_endofpacket; // SMP_CORE_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [111:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire pio_s1_agent_rp_valid; // PIO_s1_agent:rp_valid -> router_002:sink_valid
wire [111:0] pio_s1_agent_rp_data; // PIO_s1_agent:rp_data -> router_002:sink_data
wire pio_s1_agent_rp_ready; // router_002:sink_ready -> PIO_s1_agent:rp_ready
wire pio_s1_agent_rp_startofpacket; // PIO_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire pio_s1_agent_rp_endofpacket; // PIO_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [111:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> PIO_s1_burst_adapter:sink0_valid
wire [111:0] cmd_mux_src_data; // cmd_mux:src_data -> PIO_s1_burst_adapter:sink0_data
wire cmd_mux_src_ready; // PIO_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> PIO_s1_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> PIO_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> PIO_s1_burst_adapter:sink0_endofpacket
wire pio_s1_burst_adapter_source0_valid; // PIO_s1_burst_adapter:source0_valid -> PIO_s1_agent:cp_valid
wire [111:0] pio_s1_burst_adapter_source0_data; // PIO_s1_burst_adapter:source0_data -> PIO_s1_agent:cp_data
wire pio_s1_burst_adapter_source0_ready; // PIO_s1_agent:cp_ready -> PIO_s1_burst_adapter:source0_ready
wire [1:0] pio_s1_burst_adapter_source0_channel; // PIO_s1_burst_adapter:source0_channel -> PIO_s1_agent:cp_channel
wire pio_s1_burst_adapter_source0_startofpacket; // PIO_s1_burst_adapter:source0_startofpacket -> PIO_s1_agent:cp_startofpacket
wire pio_s1_burst_adapter_source0_endofpacket; // PIO_s1_burst_adapter:source0_endofpacket -> PIO_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [111:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [111:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [111:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [111:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire pio_s1_agent_rdata_fifo_out_valid; // PIO_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [33:0] pio_s1_agent_rdata_fifo_out_data; // PIO_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire pio_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> PIO_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> PIO_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> PIO_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // PIO_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> PIO_s1_agent:rdata_fifo_sink_error
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pio_s1_translator (
.clk (clk_clk_clk), // clk.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pio_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pio_s1_agent_m0_burstcount), // .burstcount
.uav_read (pio_s1_agent_m0_read), // .read
.uav_write (pio_s1_agent_m0_write), // .write
.uav_waitrequest (pio_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pio_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pio_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pio_s1_agent_m0_readdata), // .readdata
.uav_writedata (pio_s1_agent_m0_writedata), // .writedata
.uav_lock (pio_s1_agent_m0_lock), // .lock
.uav_debugaccess (pio_s1_agent_m0_debugaccess), // .debugaccess
.av_address (PIO_s1_address), // avalon_anti_slave_0.address
.av_write (PIO_s1_write), // .write
.av_readdata (PIO_s1_readdata), // .readdata
.av_writedata (PIO_s1_writedata), // .writedata
.av_chipselect (PIO_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (106),
.PKT_CACHE_L (103),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (107),
.PKT_RESPONSE_STATUS_H (108),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (99),
.PKT_THREAD_ID_L (88),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.ID (0)
) smp_core_h2f_lw_axi_master_agent (
.aclk (clk_clk_clk), // clk.clk
.aresetn (~SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (smp_core_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (smp_core_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (smp_core_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (smp_core_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (smp_core_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (rsp_mux_src_valid), // write_rp.valid
.write_rp_data (rsp_mux_src_data), // .data
.write_rp_channel (rsp_mux_src_channel), // .channel
.write_rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.write_rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.write_rp_ready (rsp_mux_src_ready), // .ready
.read_cp_valid (smp_core_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (smp_core_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (smp_core_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (smp_core_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (smp_core_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (rsp_mux_001_src_valid), // read_rp.valid
.read_rp_data (rsp_mux_001_src_data), // .data
.read_rp_channel (rsp_mux_001_src_channel), // .channel
.read_rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.read_rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.read_rp_ready (rsp_mux_001_src_ready), // .ready
.awid (SMP_CORE_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (SMP_CORE_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (SMP_CORE_h2f_lw_axi_master_awlen), // .awlen
.awsize (SMP_CORE_h2f_lw_axi_master_awsize), // .awsize
.awburst (SMP_CORE_h2f_lw_axi_master_awburst), // .awburst
.awlock (SMP_CORE_h2f_lw_axi_master_awlock), // .awlock
.awcache (SMP_CORE_h2f_lw_axi_master_awcache), // .awcache
.awprot (SMP_CORE_h2f_lw_axi_master_awprot), // .awprot
.awvalid (SMP_CORE_h2f_lw_axi_master_awvalid), // .awvalid
.awready (SMP_CORE_h2f_lw_axi_master_awready), // .awready
.wid (SMP_CORE_h2f_lw_axi_master_wid), // .wid
.wdata (SMP_CORE_h2f_lw_axi_master_wdata), // .wdata
.wstrb (SMP_CORE_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (SMP_CORE_h2f_lw_axi_master_wlast), // .wlast
.wvalid (SMP_CORE_h2f_lw_axi_master_wvalid), // .wvalid
.wready (SMP_CORE_h2f_lw_axi_master_wready), // .wready
.bid (SMP_CORE_h2f_lw_axi_master_bid), // .bid
.bresp (SMP_CORE_h2f_lw_axi_master_bresp), // .bresp
.bvalid (SMP_CORE_h2f_lw_axi_master_bvalid), // .bvalid
.bready (SMP_CORE_h2f_lw_axi_master_bready), // .bready
.arid (SMP_CORE_h2f_lw_axi_master_arid), // .arid
.araddr (SMP_CORE_h2f_lw_axi_master_araddr), // .araddr
.arlen (SMP_CORE_h2f_lw_axi_master_arlen), // .arlen
.arsize (SMP_CORE_h2f_lw_axi_master_arsize), // .arsize
.arburst (SMP_CORE_h2f_lw_axi_master_arburst), // .arburst
.arlock (SMP_CORE_h2f_lw_axi_master_arlock), // .arlock
.arcache (SMP_CORE_h2f_lw_axi_master_arcache), // .arcache
.arprot (SMP_CORE_h2f_lw_axi_master_arprot), // .arprot
.arvalid (SMP_CORE_h2f_lw_axi_master_arvalid), // .arvalid
.arready (SMP_CORE_h2f_lw_axi_master_arready), // .arready
.rid (SMP_CORE_h2f_lw_axi_master_rid), // .rid
.rdata (SMP_CORE_h2f_lw_axi_master_rdata), // .rdata
.rresp (SMP_CORE_h2f_lw_axi_master_rresp), // .rresp
.rlast (SMP_CORE_h2f_lw_axi_master_rlast), // .rlast
.rvalid (SMP_CORE_h2f_lw_axi_master_rvalid), // .rvalid
.rready (SMP_CORE_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (111),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_RESPONSE_STATUS_H (108),
.PKT_RESPONSE_STATUS_L (107),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (61),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (112),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) pio_s1_agent (
.clk (clk_clk_clk), // clk.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pio_s1_agent_m0_address), // m0.address
.m0_burstcount (pio_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pio_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pio_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pio_s1_agent_m0_lock), // .lock
.m0_readdata (pio_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pio_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pio_s1_agent_m0_read), // .read
.m0_waitrequest (pio_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pio_s1_agent_m0_writedata), // .writedata
.m0_write (pio_s1_agent_m0_write), // .write
.rp_endofpacket (pio_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pio_s1_agent_rp_ready), // .ready
.rp_valid (pio_s1_agent_rp_valid), // .valid
.rp_data (pio_s1_agent_rp_data), // .data
.rp_startofpacket (pio_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (pio_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (pio_s1_burst_adapter_source0_valid), // .valid
.cp_data (pio_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (pio_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (pio_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pio_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pio_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pio_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pio_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pio_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pio_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pio_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (pio_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pio_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pio_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (113),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pio_s1_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pio_s1_agent_rf_source_data), // in.data
.in_valid (pio_s1_agent_rf_source_valid), // .valid
.in_ready (pio_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pio_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pio_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pio_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pio_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pio_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pio_s1_agent_rdata_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pio_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (pio_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (pio_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (pio_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (pio_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (pio_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
hps_design_mm_interconnect_0_router router (
.sink_ready (smp_core_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (smp_core_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (smp_core_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (smp_core_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (smp_core_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_router router_001 (
.sink_ready (smp_core_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (smp_core_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (smp_core_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (smp_core_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (smp_core_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_router_002 router_002 (
.sink_ready (pio_s1_agent_rp_ready), // sink.ready
.sink_valid (pio_s1_agent_rp_valid), // .valid
.sink_data (pio_s1_agent_rp_data), // .data
.sink_startofpacket (pio_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pio_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) pio_s1_burst_adapter (
.clk (clk_clk_clk), // cr0.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (pio_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (pio_s1_burst_adapter_source0_data), // .data
.source0_channel (pio_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (pio_s1_burst_adapter_source0_ready) // .ready
);
hps_design_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_clk_clk), // clk.clk
.reset (SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_clk_clk), // clk.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_clk_clk), // clk.clk
.reset (PIO_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_clk_clk), // clk.clk
.reset (SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (SMP_CORE_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (clk_clk_clk), // in_clk_0.clk
.in_rst_0_reset (PIO_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (pio_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (pio_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (pio_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
// Local signals
wire DN not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_TB_V
`define SKY130_FD_SC_HDLL__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hdll__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_TB_V
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// DVB-S encoding pipeline.
//
//------------------------------------------------------------------------------
`ifndef _ZL_DVB_S_CORE_V_
`define _ZL_DVB_S_CORE_V_
`include "zl_fifo_sc.v"
`include "zl_sync_invert_randomizer.v"
`include "zl_fifo_2.v"
`include "zl_rs_encoder.v"
`include "zl_interleaver.v"
`include "zl_conv_encoder.v"
module zl_dvb_s_core
(
input clk,
input rst_n,
//
input [7:0] data_in,
input data_in_req,
output data_in_ack,
//
output data_out_i,
output data_out_q,
output data_out_req,
input data_out_ack
);
wire input_buffer_req;
wire input_buffer_ack;
wire [7:0] input_buffer_data;
zl_fifo_sc #
(
.Data_width(8),
.Addr_width(8) // 256 bytes
)
input_buffer
(
.clk(clk),
.rst_n(rst_n),
//
.in_req(data_in_req),
.in_ack(data_in_ack),
.in_data(data_in),
//
.out_req(input_buffer_req),
.out_ack(input_buffer_ack),
.out_data(input_buffer_data),
//
.full(),
.empty(),
.used()
);
wire randomizer_req;
wire randomizer_ack;
wire [7:0] randomizer_data;
zl_sync_invert_randomizer sync_invert_randomizer
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(input_buffer_req),
.data_in_ack(input_buffer_ack),
.data_in(input_buffer_data),
//
.data_out_req(randomizer_req),
.data_out_ack(randomizer_ack),
.data_out(randomizer_data)
);
wire randomizer_fifo_req;
wire randomizer_fifo_ack;
wire [7:0] randomizer_fifo_data;
zl_fifo_2 #
(
.Width(8)
)
randomizer_fifo
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(randomizer_req),
.data_in_ack(randomizer_ack),
.data_in(randomizer_data),
//
.data_out_req(randomizer_fifo_req),
.data_out_ack(randomizer_fifo_ack),
.data_out(randomizer_fifo_data)
);
wire rs_encoder_req;
wire rs_encoder_ack;
wire [7:0] rs_encoder_data;
zl_rs_encoder #
(
.N(204),
.K(188),
.M(8),
.G_x({
8'd59,
8'd13,
8'd104,
8'd189,
8'd68,
8'd209,
8'd30,
8'd8,
8'd163,
8'd65,
8'd41,
8'd229,
8'd98,
8'd50,
8'd36,
8'd59
}),
.Gf_poly(9'd285)
)
rs_encoder
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(randomizer_fifo_req),
.data_in_ack(randomizer_fifo_ack),
.data_in(randomizer_fifo_data),
//
.data_out_req(rs_encoder_req),
.data_out_ack(rs_encoder_ack),
.data_out(rs_encoder_data)
);
wire rs_encoder_fifo_req;
wire rs_encoder_fifo_ack;
wire [7:0] rs_encoder_fifo_data;
zl_fifo_2 #
(
.Width(8)
)
rs_encoder_fifo
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(rs_encoder_req),
.data_in_ack(rs_encoder_ack),
.data_in(rs_encoder_data),
//
.data_out_req(rs_encoder_fifo_req),
.data_out_ack(rs_encoder_fifo_ack),
.data_out(rs_encoder_fifo_data)
);
wire interleaver_req;
wire interleaver_ack;
wire [7:0] interleaver_data;
zl_interleaver interleaver
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(rs_encoder_fifo_req),
.data_in_ack(rs_encoder_fifo_ack),
.data_in(rs_encoder_fifo_data),
//
.data_out_req(interleaver_req),
.data_out_ack(interleaver_ack),
.data_out(interleaver_data)
);
wire interleaver_fifo_req;
wire interleaver_fifo_ack;
wire [7:0] interleaver_fifo_data;
zl_fifo_2 #
(
.Width(8)
)
interleaver_fifo
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(interleaver_req),
.data_in_ack(interleaver_ack),
.data_in(interleaver_data),
//
.data_out_req(interleaver_fifo_req),
.data_out_ack(interleaver_fifo_ack),
.data_out(interleaver_fifo_data)
);
wire conv_encoder_req;
wire conv_encoder_ack;
wire conv_encoder_data_i;
wire conv_encoder_data_q;
zl_conv_encoder #
(
.I_poly(7'o171),
.Q_poly(7'o133),
.K(7)
)
conv_encoder
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(interleaver_fifo_req),
.data_in_ack(interleaver_fifo_ack),
.data_in(interleaver_fifo_data),
//
.data_out_req(conv_encoder_req),
.data_out_ack(conv_encoder_ack),
.data_out_i(conv_encoder_data_i),
.data_out_q(conv_encoder_data_q)
);
zl_fifo_2 #
(
.Width(2)
)
conv_encoder_fifo
(
.clk(clk),
.rst_n(rst_n),
//
.data_in_req(conv_encoder_req),
.data_in_ack(conv_encoder_ack),
.data_in({conv_encoder_data_i,
conv_encoder_data_q}),
//
.data_out_req(data_out_req),
.data_out_ack(data_out_ack),
.data_out({data_out_i,
data_out_q})
);
endmodule // zl_dvb_s_core
`endif // _ZL_DVB_S_CORE_V_
|
`timescale 1ns/10ps
module RegBankS8Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] out;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`RegBankS8_LD0,8'hAE};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx000};
inst_en = 1;
#4 inst = {`RegBankS8_LD1,8'hAB};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx001};
inst_en = 1;
#4 inst = {`RegBankS8_LD2,8'hEF};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx010};
inst_en = 1;
#4 inst = {`RegBankS8_LD3,8'h2F};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx011};
inst_en = 1;
#4 inst = {`RegBankS8_LD4,8'h72};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx100};
inst_en = 1;
#4 inst = {`RegBankS8_LD5,8'h3E};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx101};
inst_en = 1;
#4 inst = {`RegBankS8_LD6,8'h92};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx110};
inst_en = 1;
#4 inst = {`RegBankS8_LD7,8'h61};
inst_en = 1;
#4 inst = {`RegBankS8_RDO,8'bxxxxx111};
inst_en = 1;
#4 inst = {`RegBankS8_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`RegBankS8_LD1,8'h87};
inst_en = 0;
#4 inst = {`RegBankS8_LD0,8'hAE};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAB};
inst_en = 1;
#4 inst = {`RegBankS8_LD1,8'h27};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`RegBankS8_LD0,8'h1A};
inst_en = 1;
#4 inst = {`RegBankS8_NOP,8'bxxxxxxxx};
inst_en = 1;
end
RegBankS8
rbs8 (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.out(out));
endmodule // RegBankS8Sim
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
reg r_change;
reg [width-1:0] r_test_expr;
reg r_state;
parameter WIN_CHANGE_START = 1'b0;
parameter WIN_CHANGE_CHECK = 1'b1;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
wire valid_end_event;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
assign valid_end_event = ~(end_event^end_event);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=WIN_CHANGE_START;
r_change=1'b0;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
case (r_state)
WIN_CHANGE_START: begin
if (start_event == 1'b1) begin
r_change <= 1'b0;
r_state <= WIN_CHANGE_CHECK;
r_test_expr <= test_expr;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_start_event == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
WIN_CHANGE_CHECK: begin
if (r_test_expr != test_expr) begin
r_change <= 1'b1;
end
// go to start state on last check
if (end_event == 1'b1) begin
r_state <= WIN_CHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window covered");
end
end
`endif // OVL_COVER_ON
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_change != 1'b1) && (r_test_expr == test_expr)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression has not changed value before window is closed");
end
`endif // OVL_ASSERT_ON
end
r_test_expr <= test_expr;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (valid_end_event == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"end_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
endcase
end
else begin
r_state<=WIN_CHANGE_START;
r_change<=1'b0;
r_test_expr <= {width{1'b0}};
end
end // always
`endif // OVL_SHARED_CODE
|
`timescale 1ns/10ps
// 输入/输出控制
module dio_if(oe, dio, din, dout);
parameter width = 1;
input oe;
inout [width-1:0] dio;
input [width-1:0] din;
output [width-1:0] dout;
assign dout = dio;
assign dio = oe ? din : {width{1'bz}};
endmodule
// 8分频，可旁路（不分频）
module fdiv8(nrst, clkin, bypass, clkout);
input nrst;
input clkin;
input bypass;
output clkout;
reg [2:0] cnt;
always @(posedge clkin or negedge nrst) begin
if (~nrst) begin
cnt <= 0;
end else begin
cnt <= cnt + 1'b1;
end
end
assign clkout = bypass ? clkin : cnt[2];
endmodule
/*
功能：DSO
输入：nrst-复位
clk-时钟
spi_cs-SPI片选
spi_sck-SPI时钟
spi_si-SPI数据输入
fx_in-待测时钟
la_in-逻辑分析仪输入
adc_in-ADC数据输入
输出：spi_so-SPI数据输出
spi_nirq-SPI中断输出
adc_clk-ADC时钟输出
adc_pd-ADC低功耗信号
fx_out-待测时钟输出
led-LED信号输出
*/
module dso(nrst, clk,
spi_cs, spi_sck, spi_si, spi_so, spi_nirq,
sram_addr, sram_dio, sram_nce, sram_noe, sram_nwe, sram_nlb, sram_nub,
adc_in, adc_clk, adc_pd, la_in, fx_in, fx_out, trig_in, trig_out, led);
// 全局信号
input nrst;
input clk;
// SPI
input spi_cs;
input spi_sck;
input spi_si;
output spi_so;
output spi_nirq;
// SRAM
output [17:0] sram_addr;
inout [15:0] sram_dio;
output sram_nce;
output sram_noe;
output sram_nwe;
output sram_nlb;
output sram_nub;
// ADC
input [7:0] adc_in;
output adc_clk;
output adc_pd;
// 其它外设
input [7:0] la_in;
input fx_in;
output fx_out;
input trig_in;
output trig_out;
output led;
// SPI读写接口
wire [6:0] s_addr;
wire [7:0] s_din;
wire [7:0] s_dout;
wire spi_so_z;
wire s_rd;
wire s_we;
// 公共接口
wire [7:0] com_ctrl;
wire [7:0] com_stat;
// 采样抽取接口
wire [15:0] deci_cnt;
wire smpl_en;
// 逻辑分析仪接口
wire la_trig_out;
wire [7:0] la_in_r;
// 示波器接口
wire wave_trig_out;
wire [7:0] adc_in_r;
// 触发器接口
wire [7:0] trig_ctrl0;
wire [7:0] trig_ctrl1;
wire [7:0] trig_ctrl2;
// SRAM接口
wire [15:0] sram_din;
wire [7:0] sram_dat_rd;
wire [17:0] sram_addr_rd;
wire [17:0] sram_addr_wr;
wire [7:0] sram_rd_step;
wire sram_wr_req;
wire sram_wr_sta;
wire sram_rd_sta;
wire sram_addr_rd_load;
// DSO启动/停止
wire dso_run;
// 读取模拟或数字数据
wire rd_sel;
// 写SRAM完成标志
wire dso_wr_end;
// 触发状态
wire trig_sta;
// 输入通道选择
wire adc_in_sel;
wire la_in_sel;
// 输入频率8分频
wire fx_div8;
// 公共状态
assign com_stat = {dso_wr_end, trig_sta};
// 公共控制
assign {fx_div8, la_in_sel, adc_in_sel, rd_sel, dso_run} = com_ctrl[4:0];
assign adc_clk = clk;
assign adc_pd = ~dso_run;
assign spi_nirq = |com_stat[1:0] ? 1'b0 : 1'bz;
assign trig_out = trig_sta;
// SPI从接口
sspi u_spi(.nrst(nrst), .clk(clk),
.cs(spi_cs), .sck(spi_sck), .si(spi_si), .so(spi_so_z),
.addr(s_addr), .din(s_din), .dout(s_dout), .rd(s_rd), .we(s_we));
assign spi_so = spi_cs ? 1'bz : spi_so_z;
// 地址写译码
dso_regw u_regw(.nrst(nrst), .clk(clk),
.addr(s_addr[2:0]), .din(s_dout), .we(s_we),
.reg0(com_ctrl), .reg1(sram_rd_step),
.reg2(trig_ctrl0), .reg3(trig_ctrl1), .reg4(trig_ctrl2),
.reg5(deci_cnt[7:0]), .reg6(deci_cnt[15:8]));
// 地址读译码
dso_regr u_regr(.addr({2'b0, s_addr[0]}), .dout(s_din),
.reg0(com_stat), .reg1(sram_dat_rd));
// 采样抽取
smpl_deci u_deci(.nrst(nrst), .clk(clk),
.en(dso_run), .div2(adc_in_sel ^ la_in_sel), .num(deci_cnt), .out(smpl_en), .out2(sram_wr_req));
// 同步输入数据
mux21nr #(8) u_muxadc(.nrst(nrst), .clk(clk), .en(smpl_en), .sel(adc_in_sel),
.din0(adc_in), .din1(la_in_r), .dout(adc_in_r));
mux21nr #(8) u_muxla(.nrst(nrst), .clk(clk), .en(smpl_en), .sel(la_in_sel),
.din0(la_in), .din1(adc_in_r), .dout(la_in_r));
// 逻辑触发
la_trig u_lat(.nrst(nrst), .clk(clk),
.din(la_in_r), .trig_out(la_trig_out),
.level_sel(trig_ctrl1), .level_mask(trig_ctrl2),
.edge_sel(trig_ctrl0[2:0]), .edge_mask(trig_ctrl0[3]));
// 波形触发
wave_trig u_wavt(.nrst(nrst), .clk(clk),
.din(adc_in_r), .level(trig_ctrl1), .edge_sel(trig_ctrl0[4]), .trig_out(wave_trig_out));
// 触发器
dso_trig u_trig(.nrst(nrst), .clk(clk),
.wave_trig(wave_trig_out), .wave_bypass(trig_ctrl0[5]), .la_trig(la_trig_out),
.ext_trig(trig_in), .ext_bypass(trig_ctrl0[6]),
.trig_clr(trig_ctrl0[7]), .trig_sta(trig_sta), .trig_pluse(sram_addr_rd_load));
// 读写地址生成
addr_gen u_addr(.nrst(nrst), .clk(clk),
.wr_en(dso_run), .wr_inc(sram_wr_req), .load_w2r(sram_addr_rd_load), .rd_inc(s_rd), .rd_step(sram_rd_step),
.addr_wr(sram_addr_wr), .addr_rd(sram_addr_rd), .wr_end(dso_wr_end));
// 读写状态控制
rw_ctrl u_rwc(.nrst(nrst), .clk(clk),
.wr_req(sram_wr_req), .rd_req(s_rd), .wr_sta(sram_wr_sta), .rd_sta(sram_rd_sta));
// 读写地址选择
mux21n #(18) u_muxaddr(.sel(sram_wr_sta), .din0(sram_addr_rd), .din1(sram_addr_wr), .dout(sram_addr));
// 读取数据选择
mux21nr #(8) u_muxdat(.nrst(nrst), .clk(clk), .en(sram_rd_sta), .sel(rd_sel),
.din0(sram_din[7:0]), .din1(sram_din[15:8]), .dout(sram_dat_rd));
// SRAM数据io
dio_if #(16) u_dio(.oe(sram_wr_sta), .dio(sram_dio), .din({la_in_r, adc_in_r}), .dout(sram_din));
// SRAM控制信号
assign sram_nwe = ~sram_wr_sta;
assign sram_noe = ~sram_rd_sta;
assign sram_nce = ~(sram_wr_sta | sram_rd_sta);
assign sram_nlb = 1'b0;
assign sram_nub = 1'b0;
// 频率计分频
fdiv8 u_fxdiv(.nrst(nrst), .clkin(fx_in), .bypass(~fx_div8), .clkout(fx_out));
assign led = dso_run; //'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__OR3B_PP_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A311OI_PP_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_PP_BLACKBOX_V
|
module cmd_gen_submodule (
//input
input clk ,
input reset_n ,
//output
output [7:0] Line_Num,
output [1:0] Focus_Num,
output Pr_Gate ,
output RX_Gate ,
output Sample_Gate,
output Envelop ,
output End_Gate
);
//wire
wire [7:0] Line_Num_buf ;
wire [1:0] Focus_Num_buf ;
wire Pr_Gate_buf ;
wire RX_Gate_buf ;
wire Sample_Gate_buf ;
wire End_Gate_buf ;
wire Envelop_buf ;
//reg
//combination
//seq
//initiation
transmit_test_model transmit_test_rev (
//input
.clk_100M (clk),
.reset_n (reset_n) ,
//output
.Line_Num (Line_Num_buf),
.Focus_Num (Focus_Num_buf),
.Pr_Gate (Pr_Gate_buf) ,
.RX_Gate (RX_Gate_buf) ,
.End_Gate (End_Gate_buf),
.Envelop (Envelop_buf)
);
Transmit Transmit_rev (
//input
.Transmit_CLK (clk), //100MHz
.Line_Num (Line_Num_buf), //Line Num,256 Lines totally,0~255
.Focus_Num (Focus_Num_buf), //Focus_num ,3 totally
.Pr_Gate (Pr_Gate_buf), //prepare for everythings
.RX_Gate (RX_Gate_buf), // Start Transmit
//output
.Sample_Gate (Sample_Gate_buf), //
.P (),
.N (),
.HV_SW_CLR (),
.HV_SW_LE (),
.HV_SW_CLK (),
.HV_SW_DOUT (),
.AX (),
.AY (),
.MT_CS (),
.MT_Strobe (),
.MT_Data ()
);
assign Line_Num = Line_Num_buf ;
assign Focus_Num = Focus_Num_buf ;
assign Pr_Gate = Pr_Gate_buf ;
assign RX_Gate = RX_Gate_buf ;
assign End_Gate = End_Gate_buf ;
assign Sample_Gate = Sample_Gate_buf;
assign Envelop = Envelop_buf ;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__OR2B_FUNCTIONAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or2b (
X ,
A ,
B_N
);
// Module ports
output X ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_FUNCTIONAL_V |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : mc_top.v
// Author : Yufeng Bai
// Email : [email protected]
// Created On : 2015-01-19
//
//-------------------------------------------------------------------
//
// Modified : 2015-08-31 by HLL
// Description : mvd added
// Modified : 2015-09-02 by HLL
// Description : mvd if connected out
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module mc_top (
clk ,
rstn ,
mb_x_total_i ,
mb_y_total_i ,
sysif_cmb_x_i ,
sysif_cmb_y_i ,
sysif_qp_i ,
sysif_start_i ,
sysif_done_o ,
fetchif_rden_o ,
fetchif_idx_x_o ,
fetchif_idx_y_o ,
fetchif_sel_o ,
fetchif_pel_i ,
fmeif_partition_i ,
fmeif_mv_i ,
fmeif_mv_rden_o ,
fmeif_mv_rdaddr_o ,
pred_wrdata_o ,
pred_wren_o ,
pred_wraddr_o ,
pred_ren_o ,
pred_size_o ,
pred_4x4_x_o ,
pred_4x4_y_o ,
pred_4x4_idx_o ,
pred_rdata_i ,
mvd_wen_o ,
mvd_waddr_o ,
mvd_wdata_o ,
pre_start_o ,
pre_en_o ,
pre_sel_o ,
pre_size_o ,
pre_4x4_x_o ,
pre_4x4_y_o ,
pre_data_o ,
rec_val_i ,
rec_idx_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [(`PIC_X_WIDTH)-1 : 0] mb_x_total_i ; // mb_x_total_i
input [(`PIC_Y_WIDTH)-1 : 0] mb_y_total_i ; // mb_y_total_i
input [`PIC_X_WIDTH-1:0] sysif_cmb_x_i ; // x position of the current LCU in the frame
input [`PIC_Y_WIDTH-1:0] sysif_cmb_y_i ; // y position of the current LCU in the frame
input [6-1:0] sysif_qp_i ; // qp of the current LCU
input [1-1:0] sysif_start_i ; // C-ime start trigger signal
output [1-1:0] sysif_done_o ; // C-ime done ack signal
output [1-1:0] fetchif_rden_o ; // fetch u/v ref pixels enable
output [6-1:0] fetchif_idx_x_o ; // "x position of ref LCU in the search window; (-12
output [6-1:0] fetchif_idx_y_o ; // "y position of ref LCU in the search window; (-12
output [1-1:0] fetchif_sel_o ; // fetch u/v ref pixels
input [8*`PIXEL_WIDTH-1:0] fetchif_pel_i ; // ref LCU pixel data
input [42-1:0] fmeif_partition_i ; // CU partition info ( 16 + 4 + 1) * 2
input [`FMV_WIDTH*2-1:0] fmeif_mv_i ; // 8 x 8 PU MVs
output [1-1:0] fmeif_mv_rden_o ; // mv read enable siganl
output [6-1:0] fmeif_mv_rdaddr_o; // mv address
//pred buf reuse
output [32*`PIXEL_WIDTH-1:0] pred_wrdata_o ; // chroma predicted pixel output
output [4-1:0] pred_wren_o ; // chroma predicted pixel write enable
output [7-1:0] pred_wraddr_o ; // chroma predicted pixel write address
output [1-1:0] pred_ren_o ; // predicted pixel read request
output [2-1:0] pred_size_o ; // predicted pixel read mode
output [4-1:0] pred_4x4_x_o ; // predicted data 4x4 block x in LCU
output [4-1:0] pred_4x4_y_o ; // predicted data 4x4 block y in LCU
output [5-1:0] pred_4x4_idx_o ; // predicted data index
input [32*`PIXEL_WIDTH-1:0] pred_rdata_i ; // predicted pixel
output mvd_wen_o ;
output [6-1 : 0] mvd_waddr_o ;
output [2*`MVD_WIDTH : 0] mvd_wdata_o ;
output [1-1:0] pre_start_o ; // pre start (pulse)
output [1-1:0] pre_en_o ; // pre enbale
output [2-1:0] pre_sel_o ; // luma:0x,u:10,v:11
output [2-1:0] pre_size_o ; // pre size info
output [4-1:0] pre_4x4_x_o ; // tq 4x4 block index x in LCU
output [4-1:0] pre_4x4_y_o ; // tq 4x4 block index y in LCU
output [16*`PIXEL_WIDTH-1:0] pre_data_o ; // tq 4x4 data
input [1-1:0] rec_val_i ; // reconstruced info valid
input [5-1:0] rec_idx_i ; // reconstruced idx
wire [2-1:0] tq_sel ;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
wire [1-1 : 0] fmeif_mv_rden_mvd_w ;
wire [6-1 : 0] fmeif_mv_rdaddr_mvd_w ;
wire [1-1 : 0] fmeif_mv_rden_mc_w ;
wire [6-1 : 0] fmeif_mv_rdaddr_mc_w ;
wire mvd_access_w ;
wire mvd_wen_w ;
// ********************************************
//
// Sub-modules Logic
//
// ********************************************
mc_chroma_top u_mc_chroma(
.clk (clk ),
.rstn (rstn ),
.ctrl_launch_i (chroma_start ),
.ctrl_launch_sel_i (chroma_sel ),
.ctrl_done_o (chroma_done ),
.mv_rden_o (fmeif_mv_rden_mc_w ),
.mv_rdaddr_o (fmeif_mv_rdaddr_mc_w ),
.mv_data_i (fmeif_mv_i ),
.ref_rden_o (fetchif_rden_o ),
.ref_idx_x_o (fetchif_idx_x_o ),
.ref_idx_y_o (fetchif_idx_y_o ),
.ref_sel_o (fetchif_sel_o ),
.ref_pel_i (fetchif_pel_i ),
.pred_pixel_o (pred_wrdata_o ),
.pred_wren_o (pred_wren_o ),
.pred_addr_o (pred_wraddr_o )
);
mc_ctrl u_ctrl (
.clk (clk ),
.rstn (rstn ),
.mc_start_i (sysif_start_i ),
.mc_done_o (sysif_done_o ),
.mvd_access_o ( mvd_access_w ),
.chroma_start_o (chroma_start ),
.chroma_sel_o (chroma_sel ),
.chroma_done_i (chroma_done ),
.tq_start_o (tq_start ),
.tq_sel_o (tq_sel ),
.tq_done_i (tq_done )
);
mc_tq u_tq(
.clk (clk ),
.rstn (rstn ),
.tq_start_i (tq_start ),
.tq_sel_i (tq_sel ),
.tq_done_o (tq_done ),
.partition_i (fmeif_partition_i),
.ipre_start_o (pre_start_o ),
.ipre_en_o (pre_en_o ),
.ipre_sel_o (pre_sel_o ),
.ipre_size_o (pre_size_o ),
.ipre_4x4_x_o (pre_4x4_x_o ),
.ipre_4x4_y_o (pre_4x4_y_o ),
.ipre_data_o (pre_data_o ),
.rec_val_i (rec_val_i ),
.rec_idx_i (rec_idx_i ),
.pred_ren_o (pred_ren_o ),
.pred_size_o (pred_size_o ),
.pred_4x4_x_o (pred_4x4_x_o ),
.pred_4x4_y_o (pred_4x4_y_o ),
.pred_4x4_idx_o (pred_4x4_idx_o ),
.pred_rdata_i (pred_rdata_i )
);
// mvd
mvd_top u_mvd_top(
// global
.clk ( clk ),
.rst_n ( rstn ),
.mb_x_total_i ( mb_x_total_i ),
.mb_y_total_i ( mb_y_total_i ),
// control
.mvd_start_i ( sysif_start_i ),
.mb_x_i ( sysif_cmb_x_i ),
.mb_y_i ( sysif_cmb_y_i ),
.inter_cu_part_size_i ( fmeif_partition_i ),
.mvd_done_o ( ),
// mv_i
.mv_rden_o ( fmeif_mv_rden_mvd_w ),
.mv_rdaddr_o ( fmeif_mv_rdaddr_mvd_w ),
.mv_data_i ( fmeif_mv_i ),
// mvd_o
.mvd_wen_o ( mvd_wen_w ),
.mvd_addr_o ( mvd_waddr_o ),
.mvd_and_mvp_idx_o ( mvd_wdata_o )
);
assign fmeif_mv_rden_o = mvd_access_w ? (!fmeif_mv_rden_mvd_w ) : fmeif_mv_rden_mc_w ;
assign fmeif_mv_rdaddr_o = mvd_access_w ? fmeif_mv_rdaddr_mvd_w : fmeif_mv_rdaddr_mc_w ;
assign mvd_wen_o = !mvd_wen_w ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V |
module cross_bar_tb;
reg rst, clk;
reg [0:7] wr_en;
reg [63:0] d;
wire [0:7] full;
wire [0:7] valid;
wire [63:0] q;
reg [0:7] stall;
wire [0:7] almost_full;
cross_bar #(8, 8)dut(rst, clk, wr_en, d, full, valid, q, stall, almost_full);
wire [7:0] internal_q [0:7];
initial begin
clk = 0;
forever #5 clk = ~clk;
end
integer i, j, tmp;
integer i2;
initial begin
rst = 1;
wr_en = 0;
d = 0;
stall = 0;
#31 rst = 0;
#10 for(i = 0; i < 1; i = i + 1) begin
wr_en = 0;
d = d + 1;
for(j = 0; j < 1; j = j + 1) begin
if(!full[j])
wr_en[j] = 1;
end
#10 ;
end
wr_en = 0;
d = 0;
stall = 0;
#200 $finish;
end
always @(posedge clk) begin
for(i2 = 0; i2 < 8; i2 = i2 + 1) begin
if(valid[i2])
$display("valid: port:%d, time:%d, data:%b", i2, $time, q);
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
// Device : Spartan-6
// Design Name : DDR/DDR2/DDR3/LPDDR
// Purpose : This is the simulation testbench which is used to verify the
// design. The basic clocks and resets to the interface are
// generated here. This also connects the memory interface to the
// memory model.
//*****************************************************************************
`timescale 1ps/1ps
module sim_tb_top;
// ========================================================================== //
// Parameters //
// ========================================================================== //
parameter DEBUG_EN = 0;
localparam DBG_WR_STS_WIDTH = 32;
localparam DBG_RD_STS_WIDTH = 32;
localparam C1_P0_PORT_MODE = "BI_MODE";
localparam C1_P1_PORT_MODE = "BI_MODE";
localparam C1_P2_PORT_MODE = "BI_MODE";
localparam C1_P3_PORT_MODE = "BI_MODE";
localparam C1_P4_PORT_MODE = "NONE";
localparam C1_P5_PORT_MODE = "NONE";
localparam C1_PORT_ENABLE = 6'b001111;
localparam C1_PORT_CONFIG = "B32_B32_B32_B32";
parameter C1_MEMCLK_PERIOD = 3000;
parameter C1_RST_ACT_LOW = 0;
parameter C1_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C1_NUM_DQ_PINS = 16;
parameter C1_MEM_ADDR_WIDTH = 13;
parameter C1_MEM_BANKADDR_WIDTH = 3;
parameter C1_MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
parameter C1_P0_MASK_SIZE = 4;
parameter C1_P0_DATA_PORT_SIZE = 32;
parameter C1_P1_MASK_SIZE = 4;
parameter C1_P1_DATA_PORT_SIZE = 32;
parameter C1_MEM_BURST_LEN = 8;
parameter C1_MEM_NUM_COL_BITS = 10;
parameter C1_CALIB_SOFT_IP = "TRUE";
parameter C1_SIMULATION = "TRUE";
parameter C1_HW_TESTING = "FALSE";
parameter C1_SMALL_DEVICE = "FALSE";
localparam C3_P0_PORT_MODE = "BI_MODE";
localparam C3_P1_PORT_MODE = "BI_MODE";
localparam C3_P2_PORT_MODE = "BI_MODE";
localparam C3_P3_PORT_MODE = "BI_MODE";
localparam C3_P4_PORT_MODE = "NONE";
localparam C3_P5_PORT_MODE = "NONE";
localparam C3_PORT_ENABLE = 6'b001111;
localparam C3_PORT_CONFIG = "B32_B32_B32_B32";
parameter C3_MEMCLK_PERIOD = 3000;
parameter C3_RST_ACT_LOW = 0;
parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C3_NUM_DQ_PINS = 16;
parameter C3_MEM_ADDR_WIDTH = 13;
parameter C3_MEM_BANKADDR_WIDTH = 3;
parameter C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
parameter C3_P0_MASK_SIZE = 4;
parameter C3_P0_DATA_PORT_SIZE = 32;
parameter C3_P1_MASK_SIZE = 4;
parameter C3_P1_DATA_PORT_SIZE = 32;
parameter C3_MEM_BURST_LEN = 8;
parameter C3_MEM_NUM_COL_BITS = 10;
parameter C3_CALIB_SOFT_IP = "TRUE";
parameter C3_SIMULATION = "TRUE";
parameter C3_HW_TESTING = "FALSE";
parameter C3_SMALL_DEVICE = "FALSE";
localparam C1_p0_BEGIN_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
localparam C1_p0_DATA_MODE = 4'b0010;
localparam C1_p0_END_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000002ff;
localparam C1_p0_PRBS_EADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffffc00;
localparam C1_p0_PRBS_SADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
localparam C1_p1_BEGIN_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000300;
localparam C1_p1_DATA_MODE = 4'b0010;
localparam C1_p1_END_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h04ffffff:32'h000004ff;
localparam C1_p1_PRBS_EADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C1_p1_PRBS_SADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000300;
localparam C1_p2_BEGIN_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C1_p2_DATA_MODE = 4'b0010;
localparam C1_p2_END_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h06ffffff:32'h000006ff;
localparam C1_p2_PRBS_EADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C1_p2_PRBS_SADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C1_p3_BEGIN_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000700;
localparam C1_p3_DATA_MODE = 4'b0010;
localparam C1_p3_END_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000008ff;
localparam C1_p3_PRBS_EADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffff000;
localparam C1_p3_PRBS_SADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000700;
localparam C1_p4_BEGIN_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C1_p4_DATA_MODE = 4'b0010;
localparam C1_p4_END_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h06ffffff:32'h000006ff;
localparam C1_p4_PRBS_EADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C1_p4_PRBS_SADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C1_p5_BEGIN_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C1_p5_DATA_MODE = 4'b0010;
localparam C1_p5_END_ADDRESS = (C1_HW_TESTING == "TRUE") ? 32'h06ffffff:32'h000006ff;
localparam C1_p5_PRBS_EADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C1_p5_PRBS_SADDR_MASK_POS = (C1_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C3_p0_BEGIN_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
localparam C3_p0_DATA_MODE = 4'b0010;
localparam C3_p0_END_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000002ff;
localparam C3_p0_PRBS_EADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffffc00;
localparam C3_p0_PRBS_SADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
localparam C3_p1_BEGIN_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000300;
localparam C3_p1_DATA_MODE = 4'b0010;
localparam C3_p1_END_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h04ffffff:32'h000004ff;
localparam C3_p1_PRBS_EADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C3_p1_PRBS_SADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000300;
localparam C3_p2_BEGIN_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C3_p2_DATA_MODE = 4'b0010;
localparam C3_p2_END_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h06ffffff:32'h000006ff;
localparam C3_p2_PRBS_EADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C3_p2_PRBS_SADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C3_p3_BEGIN_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000700;
localparam C3_p3_DATA_MODE = 4'b0010;
localparam C3_p3_END_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000008ff;
localparam C3_p3_PRBS_EADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffff000;
localparam C3_p3_PRBS_SADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000700;
localparam C3_p4_BEGIN_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C3_p4_DATA_MODE = 4'b0010;
localparam C3_p4_END_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h06ffffff:32'h000006ff;
localparam C3_p4_PRBS_EADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C3_p4_PRBS_SADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C3_p5_BEGIN_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
localparam C3_p5_DATA_MODE = 4'b0010;
localparam C3_p5_END_ADDRESS = (C3_HW_TESTING == "TRUE") ? 32'h06ffffff:32'h000006ff;
localparam C3_p5_PRBS_EADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff800;
localparam C3_p5_PRBS_SADDR_MASK_POS = (C3_HW_TESTING == "TRUE") ? 32'h05000000:32'h00000500;
// ========================================================================== //
// Signal Declarations //
// ========================================================================== //
// Clocks
// Clocks
reg c1_sys_clk;
wire c1_sys_clk_p;
wire c1_sys_clk_n;
// System Reset
reg c1_sys_rst;
wire c1_sys_rst_i;
// Design-Top Port Map
wire c1_error;
wire c1_calib_done;
wire [31:0] c1_cmp_data;
wire c1_cmp_error;
wire [C1_MEM_ADDR_WIDTH-1:0] mcb1_dram_a;
wire [C1_MEM_BANKADDR_WIDTH-1:0] mcb1_dram_ba;
wire mcb1_dram_ck;
wire mcb1_dram_ck_n;
wire [C1_NUM_DQ_PINS-1:0] mcb1_dram_dq;
wire mcb1_dram_dqs;
wire mcb1_dram_dqs_n;
wire mcb1_dram_dm;
wire mcb1_dram_ras_n;
wire mcb1_dram_cas_n;
wire mcb1_dram_we_n;
wire mcb1_dram_cke;
wire mcb1_dram_odt;
wire mcb1_dram_reset_n;
wire [64 + (2*C1_P0_DATA_PORT_SIZE - 1):0] c1_p0_error_status;
wire [64 + (2*C1_P1_DATA_PORT_SIZE - 1):0] c1_p1_error_status;
wire [127 : 0] c1_p2_error_status;
wire [127 : 0] c1_p3_error_status;
wire [127 : 0] c1_p4_error_status;
wire [127 : 0] c1_p5_error_status;
wire mcb1_dram_udqs; // for X16 parts
wire mcb1_dram_udqs_n; // for X16 parts
wire mcb1_dram_udm; // for X16 parts
wire c1_vio_modify_enable = 1'b1;
wire [2:0] c1_vio_data_mode_value = 3'b010;
wire [2:0] c1_vio_addr_mode_value = 3'b011;
// User design Sim
wire c1_clk0;
wire c1_rst0;
reg c1_aresetn;
wire c1_wrap_en;
wire c1_cmd_err;
wire c1_data_msmatch_err;
wire c1_write_err;
wire c1_read_err;
wire c1_test_cmptd;
wire c1_dbg_wr_sts_vld;
wire c1_dbg_rd_sts_vld;
wire [DBG_WR_STS_WIDTH-1:0] c1_dbg_wr_sts;
wire [DBG_WR_STS_WIDTH-1:0] c1_dbg_rd_sts;
wire c1_p0_cmd_en;
wire [2:0] c1_p0_cmd_instr;
wire [5:0] c1_p0_cmd_bl;
wire [29:0] c1_p0_cmd_byte_addr;
wire c1_p0_cmd_empty;
wire c1_p0_cmd_full;
wire c1_p0_wr_en;
wire [C1_P0_MASK_SIZE - 1:0] c1_p0_wr_mask;
wire [C1_P0_DATA_PORT_SIZE - 1:0] c1_p0_wr_data;
wire c1_p0_wr_full;
wire c1_p0_wr_empty;
wire [6:0] c1_p0_wr_count;
wire c1_p0_wr_underrun;
wire c1_p0_wr_error;
wire c1_p0_rd_en;
wire [C1_P0_DATA_PORT_SIZE - 1:0] c1_p0_rd_data;
wire c1_p0_rd_full;
wire c1_p0_rd_empty;
wire [6:0] c1_p0_rd_count;
wire c1_p0_rd_overflow;
wire c1_p0_rd_error;
wire c1_p1_cmd_en;
wire [2:0] c1_p1_cmd_instr;
wire [5:0] c1_p1_cmd_bl;
wire [29:0] c1_p1_cmd_byte_addr;
wire c1_p1_cmd_empty;
wire c1_p1_cmd_full;
wire c1_p1_wr_en;
wire [C1_P1_MASK_SIZE - 1:0] c1_p1_wr_mask;
wire [C1_P1_DATA_PORT_SIZE - 1:0] c1_p1_wr_data;
wire c1_p1_wr_full;
wire c1_p1_wr_empty;
wire [6:0] c1_p1_wr_count;
wire c1_p1_wr_underrun;
wire c1_p1_wr_error;
wire c1_p1_rd_en;
wire [C1_P1_DATA_PORT_SIZE - 1:0] c1_p1_rd_data;
wire c1_p1_rd_full;
wire c1_p1_rd_empty;
wire [6:0] c1_p1_rd_count;
wire c1_p1_rd_overflow;
wire c1_p1_rd_error;
wire c1_p2_cmd_en;
wire [2:0] c1_p2_cmd_instr;
wire [5:0] c1_p2_cmd_bl;
wire [29:0] c1_p2_cmd_byte_addr;
wire c1_p2_cmd_empty;
wire c1_p2_cmd_full;
wire c1_p2_wr_en;
wire [3:0] c1_p2_wr_mask;
wire [31:0] c1_p2_wr_data;
wire c1_p2_wr_full;
wire c1_p2_wr_empty;
wire [6:0] c1_p2_wr_count;
wire c1_p2_wr_underrun;
wire c1_p2_wr_error;
wire c1_p2_rd_en;
wire [31:0] c1_p2_rd_data;
wire c1_p2_rd_full;
wire c1_p2_rd_empty;
wire [6:0] c1_p2_rd_count;
wire c1_p2_rd_overflow;
wire c1_p2_rd_error;
wire c1_p3_cmd_en;
wire [2:0] c1_p3_cmd_instr;
wire [5:0] c1_p3_cmd_bl;
wire [29:0] c1_p3_cmd_byte_addr;
wire c1_p3_cmd_empty;
wire c1_p3_cmd_full;
wire c1_p3_wr_en;
wire [3:0] c1_p3_wr_mask;
wire [31:0] c1_p3_wr_data;
wire c1_p3_wr_full;
wire c1_p3_wr_empty;
wire [6:0] c1_p3_wr_count;
wire c1_p3_wr_underrun;
wire c1_p3_wr_error;
wire c1_p3_rd_en;
wire [31:0] c1_p3_rd_data;
wire c1_p3_rd_full;
wire c1_p3_rd_empty;
wire [6:0] c1_p3_rd_count;
wire c1_p3_rd_overflow;
wire c1_p3_rd_error;
// Clocks
// Clocks
reg c3_sys_clk;
wire c3_sys_clk_p;
wire c3_sys_clk_n;
// System Reset
reg c3_sys_rst;
wire c3_sys_rst_i;
// Design-Top Port Map
wire c3_error;
wire c3_calib_done;
wire [31:0] c3_cmp_data;
wire c3_cmp_error;
wire [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a;
wire [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba;
wire mcb3_dram_ck;
wire mcb3_dram_ck_n;
wire [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq;
wire mcb3_dram_dqs;
wire mcb3_dram_dqs_n;
wire mcb3_dram_dm;
wire mcb3_dram_ras_n;
wire mcb3_dram_cas_n;
wire mcb3_dram_we_n;
wire mcb3_dram_cke;
wire mcb3_dram_odt;
wire mcb3_dram_reset_n;
wire [64 + (2*C3_P0_DATA_PORT_SIZE - 1):0] c3_p0_error_status;
wire [64 + (2*C3_P1_DATA_PORT_SIZE - 1):0] c3_p1_error_status;
wire [127 : 0] c3_p2_error_status;
wire [127 : 0] c3_p3_error_status;
wire [127 : 0] c3_p4_error_status;
wire [127 : 0] c3_p5_error_status;
wire mcb3_dram_udqs; // for X16 parts
wire mcb3_dram_udqs_n; // for X16 parts
wire mcb3_dram_udm; // for X16 parts
wire c3_vio_modify_enable = 1'b1;
wire [2:0] c3_vio_data_mode_value = 3'b010;
wire [2:0] c3_vio_addr_mode_value = 3'b011;
// User design Sim
wire c3_clk0;
wire c3_rst0;
reg c3_aresetn;
wire c3_wrap_en;
wire c3_cmd_err;
wire c3_data_msmatch_err;
wire c3_write_err;
wire c3_read_err;
wire c3_test_cmptd;
wire c3_dbg_wr_sts_vld;
wire c3_dbg_rd_sts_vld;
wire [DBG_WR_STS_WIDTH-1:0] c3_dbg_wr_sts;
wire [DBG_WR_STS_WIDTH-1:0] c3_dbg_rd_sts;
wire c3_p0_cmd_en;
wire [2:0] c3_p0_cmd_instr;
wire [5:0] c3_p0_cmd_bl;
wire [29:0] c3_p0_cmd_byte_addr;
wire c3_p0_cmd_empty;
wire c3_p0_cmd_full;
wire c3_p0_wr_en;
wire [C3_P0_MASK_SIZE - 1:0] c3_p0_wr_mask;
wire [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_wr_data;
wire c3_p0_wr_full;
wire c3_p0_wr_empty;
wire [6:0] c3_p0_wr_count;
wire c3_p0_wr_underrun;
wire c3_p0_wr_error;
wire c3_p0_rd_en;
wire [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_rd_data;
wire c3_p0_rd_full;
wire c3_p0_rd_empty;
wire [6:0] c3_p0_rd_count;
wire c3_p0_rd_overflow;
wire c3_p0_rd_error;
wire c3_p1_cmd_en;
wire [2:0] c3_p1_cmd_instr;
wire [5:0] c3_p1_cmd_bl;
wire [29:0] c3_p1_cmd_byte_addr;
wire c3_p1_cmd_empty;
wire c3_p1_cmd_full;
wire c3_p1_wr_en;
wire [C3_P1_MASK_SIZE - 1:0] c3_p1_wr_mask;
wire [C3_P1_DATA_PORT_SIZE - 1:0] c3_p1_wr_data;
wire c3_p1_wr_full;
wire c3_p1_wr_empty;
wire [6:0] c3_p1_wr_count;
wire c3_p1_wr_underrun;
wire c3_p1_wr_error;
wire c3_p1_rd_en;
wire [C3_P1_DATA_PORT_SIZE - 1:0] c3_p1_rd_data;
wire c3_p1_rd_full;
wire c3_p1_rd_empty;
wire [6:0] c3_p1_rd_count;
wire c3_p1_rd_overflow;
wire c3_p1_rd_error;
wire c3_p2_cmd_en;
wire [2:0] c3_p2_cmd_instr;
wire [5:0] c3_p2_cmd_bl;
wire [29:0] c3_p2_cmd_byte_addr;
wire c3_p2_cmd_empty;
wire c3_p2_cmd_full;
wire c3_p2_wr_en;
wire [3:0] c3_p2_wr_mask;
wire [31:0] c3_p2_wr_data;
wire c3_p2_wr_full;
wire c3_p2_wr_empty;
wire [6:0] c3_p2_wr_count;
wire c3_p2_wr_underrun;
wire c3_p2_wr_error;
wire c3_p2_rd_en;
wire [31:0] c3_p2_rd_data;
wire c3_p2_rd_full;
wire c3_p2_rd_empty;
wire [6:0] c3_p2_rd_count;
wire c3_p2_rd_overflow;
wire c3_p2_rd_error;
wire c3_p3_cmd_en;
wire [2:0] c3_p3_cmd_instr;
wire [5:0] c3_p3_cmd_bl;
wire [29:0] c3_p3_cmd_byte_addr;
wire c3_p3_cmd_empty;
wire c3_p3_cmd_full;
wire c3_p3_wr_en;
wire [3:0] c3_p3_wr_mask;
wire [31:0] c3_p3_wr_data;
wire c3_p3_wr_full;
wire c3_p3_wr_empty;
wire [6:0] c3_p3_wr_count;
wire c3_p3_wr_underrun;
wire c3_p3_wr_error;
wire c3_p3_rd_en;
wire [31:0] c3_p3_rd_data;
wire c3_p3_rd_full;
wire c3_p3_rd_empty;
wire [6:0] c3_p3_rd_count;
wire c3_p3_rd_overflow;
wire c3_p3_rd_error;
wire c1_p4_cmd_clk;
wire c1_p4_cmd_en;
wire[2:0] c1_p4_cmd_instr;
wire[5:0] c1_p4_cmd_bl;
wire[29:0] c1_p4_cmd_byte_addr;
wire c1_p4_cmd_empty;
wire c1_p4_cmd_full;
wire c1_p4_wr_clk;
wire c1_p4_wr_en;
wire[3:0] c1_p4_wr_mask;
wire[31:0] c1_p4_wr_data;
wire c1_p4_wr_full;
wire c1_p4_wr_empty;
wire[6:0] c1_p4_wr_count;
wire c1_p4_wr_underrun;
wire c1_p4_wr_error;
wire c1_p4_rd_clk;
wire c1_p4_rd_en;
wire[31:0] c1_p4_rd_data;
wire c1_p4_rd_full;
wire c1_p4_rd_empty;
wire[6:0] c1_p4_rd_count;
wire c1_p4_rd_overflow;
wire c1_p4_rd_error;
wire c1_p5_cmd_clk;
wire c1_p5_cmd_en;
wire[2:0] c1_p5_cmd_instr;
wire[5:0] c1_p5_cmd_bl;
wire[29:0] c1_p5_cmd_byte_addr;
wire c1_p5_cmd_empty;
wire c1_p5_cmd_full;
wire c1_p5_wr_clk;
wire c1_p5_wr_en;
wire[3:0] c1_p5_wr_mask;
wire[31:0] c1_p5_wr_data;
wire c1_p5_wr_full;
wire c1_p5_wr_empty;
wire[6:0] c1_p5_wr_count;
wire c1_p5_wr_underrun;
wire c1_p5_wr_error;
wire c1_p5_rd_clk;
wire c1_p5_rd_en;
wire[31:0] c1_p5_rd_data;
wire c1_p5_rd_full;
wire c1_p5_rd_empty;
wire[6:0] c1_p5_rd_count;
wire c1_p5_rd_overflow;
wire c1_p5_rd_error;
wire c3_p4_cmd_clk;
wire c3_p4_cmd_en;
wire[2:0] c3_p4_cmd_instr;
wire[5:0] c3_p4_cmd_bl;
wire[29:0] c3_p4_cmd_byte_addr;
wire c3_p4_cmd_empty;
wire c3_p4_cmd_full;
wire c3_p4_wr_clk;
wire c3_p4_wr_en;
wire[3:0] c3_p4_wr_mask;
wire[31:0] c3_p4_wr_data;
wire c3_p4_wr_full;
wire c3_p4_wr_empty;
wire[6:0] c3_p4_wr_count;
wire c3_p4_wr_underrun;
wire c3_p4_wr_error;
wire c3_p4_rd_clk;
wire c3_p4_rd_en;
wire[31:0] c3_p4_rd_data;
wire c3_p4_rd_full;
wire c3_p4_rd_empty;
wire[6:0] c3_p4_rd_count;
wire c3_p4_rd_overflow;
wire c3_p4_rd_error;
wire c3_p5_cmd_clk;
wire c3_p5_cmd_en;
wire[2:0] c3_p5_cmd_instr;
wire[5:0] c3_p5_cmd_bl;
wire[29:0] c3_p5_cmd_byte_addr;
wire c3_p5_cmd_empty;
wire c3_p5_cmd_full;
wire c3_p5_wr_clk;
wire c3_p5_wr_en;
wire[3:0] c3_p5_wr_mask;
wire[31:0] c3_p5_wr_data;
wire c3_p5_wr_full;
wire c3_p5_wr_empty;
wire[6:0] c3_p5_wr_count;
wire c3_p5_wr_underrun;
wire c3_p5_wr_error;
wire c3_p5_rd_clk;
wire c3_p5_rd_en;
wire[31:0] c3_p5_rd_data;
wire c3_p5_rd_full;
wire c3_p5_rd_empty;
wire[6:0] c3_p5_rd_count;
wire c3_p5_rd_overflow;
wire c3_p5_rd_error;
// Error & Calib Signals
wire error;
wire calib_done;
wire rzq1;
wire rzq3; wire zio1;
wire zio3;
// ========================================================================== //
// Clocks Generation //
// ========================================================================== //
initial
c1_sys_clk = 1'b0;
always
#(C1_MEMCLK_PERIOD/2) c1_sys_clk = ~c1_sys_clk;
assign c1_sys_clk_p = c1_sys_clk;
assign c1_sys_clk_n = ~c1_sys_clk;
initial
c3_sys_clk = 1'b0;
always
#(C3_MEMCLK_PERIOD/2) c3_sys_clk = ~c3_sys_clk;
assign c3_sys_clk_p = c3_sys_clk;
assign c3_sys_clk_n = ~c3_sys_clk;
// ========================================================================== //
// Reset Generation //
// ========================================================================== //
initial begin
c1_sys_rst = 1'b0;
#20000;
c1_sys_rst = 1'b1;
end
assign c1_sys_rst_i = C1_RST_ACT_LOW ? c1_sys_rst : ~c1_sys_rst;
initial begin
c3_sys_rst = 1'b0;
#20000;
c3_sys_rst = 1'b1;
end
assign c3_sys_rst_i = C3_RST_ACT_LOW ? c3_sys_rst : ~c3_sys_rst;
// ========================================================================== //
// Error Grouping //
// ========================================================================== //
assign error = c1_error | c3_error;
assign calib_done = c1_calib_done & c3_calib_done;
// The PULLDOWN component is connected to the ZIO signal primarily to avoid the
// unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
PULLDOWN zio_pulldown1 (.O(zio1));
PULLDOWN zio_pulldown3 (.O(zio3)); PULLDOWN rzq_pulldown1 (.O(rzq1));
PULLDOWN rzq_pulldown3 (.O(rzq3));
// ========================================================================== //
// DESIGN TOP INSTANTIATION //
// ========================================================================== //
nkmd_ddr3 #(
.C1_P0_MASK_SIZE (C1_P0_MASK_SIZE ),
.C1_P0_DATA_PORT_SIZE (C1_P0_DATA_PORT_SIZE ),
.C1_P1_MASK_SIZE (C1_P1_MASK_SIZE ),
.C1_P1_DATA_PORT_SIZE (C1_P1_DATA_PORT_SIZE ),
.C1_MEMCLK_PERIOD (C1_MEMCLK_PERIOD),
.C1_RST_ACT_LOW (C1_RST_ACT_LOW),
.C1_INPUT_CLK_TYPE (C1_INPUT_CLK_TYPE),
.DEBUG_EN (DEBUG_EN),
.C1_MEM_ADDR_ORDER (C1_MEM_ADDR_ORDER ),
.C1_NUM_DQ_PINS (C1_NUM_DQ_PINS ),
.C1_MEM_ADDR_WIDTH (C1_MEM_ADDR_WIDTH ),
.C1_MEM_BANKADDR_WIDTH (C1_MEM_BANKADDR_WIDTH),
.C1_SIMULATION (C1_SIMULATION),
.C1_CALIB_SOFT_IP (C1_CALIB_SOFT_IP ),
.C3_P0_MASK_SIZE (C3_P0_MASK_SIZE ),
.C3_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE ),
.C3_P1_MASK_SIZE (C3_P1_MASK_SIZE ),
.C3_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE ),
.C3_MEMCLK_PERIOD (C3_MEMCLK_PERIOD),
.C3_RST_ACT_LOW (C3_RST_ACT_LOW),
.C3_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE),
.C3_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER ),
.C3_NUM_DQ_PINS (C3_NUM_DQ_PINS ),
.C3_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH ),
.C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),
.C3_SIMULATION (C3_SIMULATION),
.C3_CALIB_SOFT_IP (C3_CALIB_SOFT_IP )
)
design_top (
.c1_sys_clk (c1_sys_clk),
.c1_sys_rst_i (c1_sys_rst_i),
.mcb1_dram_dq (mcb1_dram_dq),
.mcb1_dram_a (mcb1_dram_a),
.mcb1_dram_ba (mcb1_dram_ba),
.mcb1_dram_ras_n (mcb1_dram_ras_n),
.mcb1_dram_cas_n (mcb1_dram_cas_n),
.mcb1_dram_we_n (mcb1_dram_we_n),
.mcb1_dram_odt (mcb1_dram_odt),
.mcb1_dram_cke (mcb1_dram_cke),
.mcb1_dram_ck (mcb1_dram_ck),
.mcb1_dram_ck_n (mcb1_dram_ck_n),
.mcb1_dram_dqs (mcb1_dram_dqs),
.mcb1_dram_dqs_n (mcb1_dram_dqs_n),
.mcb1_dram_udqs (mcb1_dram_udqs), // for X16 parts
.mcb1_dram_udqs_n (mcb1_dram_udqs_n), // for X16 parts
.mcb1_dram_udm (mcb1_dram_udm), // for X16 parts
.mcb1_dram_dm (mcb1_dram_dm),
.mcb1_dram_reset_n (mcb1_dram_reset_n),
.c1_clk0 (c1_clk0),
.c1_rst0 (c1_rst0),
.c1_calib_done (c1_calib_done),
.mcb1_rzq (rzq1),
.mcb1_zio (zio1),
.c1_p0_cmd_clk (c1_clk0),
.c1_p0_cmd_en (c1_p0_cmd_en),
.c1_p0_cmd_instr (c1_p0_cmd_instr),
.c1_p0_cmd_bl (c1_p0_cmd_bl),
.c1_p0_cmd_byte_addr (c1_p0_cmd_byte_addr),
.c1_p0_cmd_empty (c1_p0_cmd_empty),
.c1_p0_cmd_full (c1_p0_cmd_full),
.c1_p0_wr_clk (c1_clk0),
.c1_p0_wr_en (c1_p0_wr_en),
.c1_p0_wr_mask (c1_p0_wr_mask),
.c1_p0_wr_data (c1_p0_wr_data),
.c1_p0_wr_full (c1_p0_wr_full),
.c1_p0_wr_empty (c1_p0_wr_empty),
.c1_p0_wr_count (c1_p0_wr_count),
.c1_p0_wr_underrun (c1_p0_wr_underrun),
.c1_p0_wr_error (c1_p0_wr_error),
.c1_p0_rd_clk (c1_clk0),
.c1_p0_rd_en (c1_p0_rd_en),
.c1_p0_rd_data (c1_p0_rd_data),
.c1_p0_rd_full (c1_p0_rd_full),
.c1_p0_rd_empty (c1_p0_rd_empty),
.c1_p0_rd_count (c1_p0_rd_count),
.c1_p0_rd_overflow (c1_p0_rd_overflow),
.c1_p0_rd_error (c1_p0_rd_error),
.c1_p1_cmd_clk (c1_clk0),
.c1_p1_cmd_en (c1_p1_cmd_en),
.c1_p1_cmd_instr (c1_p1_cmd_instr),
.c1_p1_cmd_bl (c1_p1_cmd_bl),
.c1_p1_cmd_byte_addr (c1_p1_cmd_byte_addr),
.c1_p1_cmd_empty (c1_p1_cmd_empty),
.c1_p1_cmd_full (c1_p1_cmd_full),
.c1_p1_wr_clk (c1_clk0),
.c1_p1_wr_en (c1_p1_wr_en),
.c1_p1_wr_mask (c1_p1_wr_mask),
.c1_p1_wr_data (c1_p1_wr_data),
.c1_p1_wr_full (c1_p1_wr_full),
.c1_p1_wr_empty (c1_p1_wr_empty),
.c1_p1_wr_count (c1_p1_wr_count),
.c1_p1_wr_underrun (c1_p1_wr_underrun),
.c1_p1_wr_error (c1_p1_wr_error),
.c1_p1_rd_clk (c1_clk0),
.c1_p1_rd_en (c1_p1_rd_en),
.c1_p1_rd_data (c1_p1_rd_data),
.c1_p1_rd_full (c1_p1_rd_full),
.c1_p1_rd_empty (c1_p1_rd_empty),
.c1_p1_rd_count (c1_p1_rd_count),
.c1_p1_rd_overflow (c1_p1_rd_overflow),
.c1_p1_rd_error (c1_p1_rd_error),
.c1_p2_cmd_clk (c1_clk0),
.c1_p2_cmd_en (c1_p2_cmd_en),
.c1_p2_cmd_instr (c1_p2_cmd_instr),
.c1_p2_cmd_bl (c1_p2_cmd_bl),
.c1_p2_cmd_byte_addr (c1_p2_cmd_byte_addr),
.c1_p2_cmd_empty (c1_p2_cmd_empty),
.c1_p2_cmd_full (c1_p2_cmd_full),
.c1_p2_wr_clk (c1_clk0),
.c1_p2_wr_en (c1_p2_wr_en),
.c1_p2_wr_mask (c1_p2_wr_mask),
.c1_p2_wr_data (c1_p2_wr_data),
.c1_p2_wr_full (c1_p2_wr_full),
.c1_p2_wr_empty (c1_p2_wr_empty),
.c1_p2_wr_count (c1_p2_wr_count),
.c1_p2_wr_underrun (c1_p2_wr_underrun),
.c1_p2_wr_error (c1_p2_wr_error),
.c1_p2_rd_clk (c1_clk0),
.c1_p2_rd_en (c1_p2_rd_en),
.c1_p2_rd_data (c1_p2_rd_data),
.c1_p2_rd_full (c1_p2_rd_full),
.c1_p2_rd_empty (c1_p2_rd_empty),
.c1_p2_rd_count (c1_p2_rd_count),
.c1_p2_rd_overflow (c1_p2_rd_overflow),
.c1_p2_rd_error (c1_p2_rd_error),
.c1_p3_cmd_clk (c1_clk0),
.c1_p3_cmd_en (c1_p3_cmd_en),
.c1_p3_cmd_instr (c1_p3_cmd_instr),
.c1_p3_cmd_bl (c1_p3_cmd_bl),
.c1_p3_cmd_byte_addr (c1_p3_cmd_byte_addr),
.c1_p3_cmd_empty (c1_p3_cmd_empty),
.c1_p3_cmd_full (c1_p3_cmd_full),
.c1_p3_wr_clk (c1_clk0),
.c1_p3_wr_en (c1_p3_wr_en),
.c1_p3_wr_mask (c1_p3_wr_mask),
.c1_p3_wr_data (c1_p3_wr_data),
.c1_p3_wr_full (c1_p3_wr_full),
.c1_p3_wr_empty (c1_p3_wr_empty),
.c1_p3_wr_count (c1_p3_wr_count),
.c1_p3_wr_underrun (c1_p3_wr_underrun),
.c1_p3_wr_error (c1_p3_wr_error),
.c1_p3_rd_clk (c1_clk0),
.c1_p3_rd_en (c1_p3_rd_en),
.c1_p3_rd_data (c1_p3_rd_data),
.c1_p3_rd_full (c1_p3_rd_full),
.c1_p3_rd_empty (c1_p3_rd_empty),
.c1_p3_rd_count (c1_p3_rd_count),
.c1_p3_rd_overflow (c1_p3_rd_overflow),
.c1_p3_rd_error (c1_p3_rd_error),
.c3_sys_clk (c3_sys_clk),
.c3_sys_rst_i (c3_sys_rst_i),
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_odt (mcb3_dram_odt),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_udqs (mcb3_dram_udqs), // for X16 parts
.mcb3_dram_udqs_n (mcb3_dram_udqs_n), // for X16 parts
.mcb3_dram_udm (mcb3_dram_udm), // for X16 parts
.mcb3_dram_dm (mcb3_dram_dm),
.mcb3_dram_reset_n (mcb3_dram_reset_n),
.c3_clk0 (c3_clk0),
.c3_rst0 (c3_rst0),
.c3_calib_done (c3_calib_done),
.mcb3_rzq (rzq3),
.mcb3_zio (zio3),
.c3_p0_cmd_clk (c3_clk0),
.c3_p0_cmd_en (c3_p0_cmd_en),
.c3_p0_cmd_instr (c3_p0_cmd_instr),
.c3_p0_cmd_bl (c3_p0_cmd_bl),
.c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
.c3_p0_cmd_empty (c3_p0_cmd_empty),
.c3_p0_cmd_full (c3_p0_cmd_full),
.c3_p0_wr_clk (c3_clk0),
.c3_p0_wr_en (c3_p0_wr_en),
.c3_p0_wr_mask (c3_p0_wr_mask),
.c3_p0_wr_data (c3_p0_wr_data),
.c3_p0_wr_full (c3_p0_wr_full),
.c3_p0_wr_empty (c3_p0_wr_empty),
.c3_p0_wr_count (c3_p0_wr_count),
.c3_p0_wr_underrun (c3_p0_wr_underrun),
.c3_p0_wr_error (c3_p0_wr_error),
.c3_p0_rd_clk (c3_clk0),
.c3_p0_rd_en (c3_p0_rd_en),
.c3_p0_rd_data (c3_p0_rd_data),
.c3_p0_rd_full (c3_p0_rd_full),
.c3_p0_rd_empty (c3_p0_rd_empty),
.c3_p0_rd_count (c3_p0_rd_count),
.c3_p0_rd_overflow (c3_p0_rd_overflow),
.c3_p0_rd_error (c3_p0_rd_error),
.c3_p1_cmd_clk (c3_clk0),
.c3_p1_cmd_en (c3_p1_cmd_en),
.c3_p1_cmd_instr (c3_p1_cmd_instr),
.c3_p1_cmd_bl (c3_p1_cmd_bl),
.c3_p1_cmd_byte_addr (c3_p1_cmd_byte_addr),
.c3_p1_cmd_empty (c3_p1_cmd_empty),
.c3_p1_cmd_full (c3_p1_cmd_full),
.c3_p1_wr_clk (c3_clk0),
.c3_p1_wr_en (c3_p1_wr_en),
.c3_p1_wr_mask (c3_p1_wr_mask),
.c3_p1_wr_data (c3_p1_wr_data),
.c3_p1_wr_full (c3_p1_wr_full),
.c3_p1_wr_empty (c3_p1_wr_empty),
.c3_p1_wr_count (c3_p1_wr_count),
.c3_p1_wr_underrun (c3_p1_wr_underrun),
.c3_p1_wr_error (c3_p1_wr_error),
.c3_p1_rd_clk (c3_clk0),
.c3_p1_rd_en (c3_p1_rd_en),
.c3_p1_rd_data (c3_p1_rd_data),
.c3_p1_rd_full (c3_p1_rd_full),
.c3_p1_rd_empty (c3_p1_rd_empty),
.c3_p1_rd_count (c3_p1_rd_count),
.c3_p1_rd_overflow (c3_p1_rd_overflow),
.c3_p1_rd_error (c3_p1_rd_error),
.c3_p2_cmd_clk (c3_clk0),
.c3_p2_cmd_en (c3_p2_cmd_en),
.c3_p2_cmd_instr (c3_p2_cmd_instr),
.c3_p2_cmd_bl (c3_p2_cmd_bl),
.c3_p2_cmd_byte_addr (c3_p2_cmd_byte_addr),
.c3_p2_cmd_empty (c3_p2_cmd_empty),
.c3_p2_cmd_full (c3_p2_cmd_full),
.c3_p2_wr_clk (c3_clk0),
.c3_p2_wr_en (c3_p2_wr_en),
.c3_p2_wr_mask (c3_p2_wr_mask),
.c3_p2_wr_data (c3_p2_wr_data),
.c3_p2_wr_full (c3_p2_wr_full),
.c3_p2_wr_empty (c3_p2_wr_empty),
.c3_p2_wr_count (c3_p2_wr_count),
.c3_p2_wr_underrun (c3_p2_wr_underrun),
.c3_p2_wr_error (c3_p2_wr_error),
.c3_p2_rd_clk (c3_clk0),
.c3_p2_rd_en (c3_p2_rd_en),
.c3_p2_rd_data (c3_p2_rd_data),
.c3_p2_rd_full (c3_p2_rd_full),
.c3_p2_rd_empty (c3_p2_rd_empty),
.c3_p2_rd_count (c3_p2_rd_count),
.c3_p2_rd_overflow (c3_p2_rd_overflow),
.c3_p2_rd_error (c3_p2_rd_error),
.c3_p3_cmd_clk (c3_clk0),
.c3_p3_cmd_en (c3_p3_cmd_en),
.c3_p3_cmd_instr (c3_p3_cmd_instr),
.c3_p3_cmd_bl (c3_p3_cmd_bl),
.c3_p3_cmd_byte_addr (c3_p3_cmd_byte_addr),
.c3_p3_cmd_empty (c3_p3_cmd_empty),
.c3_p3_cmd_full (c3_p3_cmd_full),
.c3_p3_wr_clk (c3_clk0),
.c3_p3_wr_en (c3_p3_wr_en),
.c3_p3_wr_mask (c3_p3_wr_mask),
.c3_p3_wr_data (c3_p3_wr_data),
.c3_p3_wr_full (c3_p3_wr_full),
.c3_p3_wr_empty (c3_p3_wr_empty),
.c3_p3_wr_count (c3_p3_wr_count),
.c3_p3_wr_underrun (c3_p3_wr_underrun),
.c3_p3_wr_error (c3_p3_wr_error),
.c3_p3_rd_clk (c3_clk0),
.c3_p3_rd_en (c3_p3_rd_en),
.c3_p3_rd_data (c3_p3_rd_data),
.c3_p3_rd_full (c3_p3_rd_full),
.c3_p3_rd_empty (c3_p3_rd_empty),
.c3_p3_rd_count (c3_p3_rd_count),
.c3_p3_rd_overflow (c3_p3_rd_overflow),
.c3_p3_rd_error (c3_p3_rd_error)
);
// Test bench top for the controller-1
memc_tb_top #
(
.C_SIMULATION (C1_SIMULATION),
.C_NUM_DQ_PINS (C1_NUM_DQ_PINS),
.C_MEM_BURST_LEN (C1_MEM_BURST_LEN),
.C_MEM_NUM_COL_BITS (C1_MEM_NUM_COL_BITS),
.C_SMALL_DEVICE (C1_SMALL_DEVICE),
// The following parameters from C_PORT_ENABLE to C_P5_PORT_MODE are introduced
// to handle the static instances of all the six traffic generators inside the
// memc_tb_top module.
.C_PORT_ENABLE (C1_PORT_ENABLE),
.C_P0_MASK_SIZE (C1_P0_MASK_SIZE),
.C_P0_DATA_PORT_SIZE (C1_P0_DATA_PORT_SIZE),
.C_P1_MASK_SIZE (C1_P1_MASK_SIZE),
.C_P1_DATA_PORT_SIZE (C1_P1_DATA_PORT_SIZE),
.C_P0_PORT_MODE (C1_P0_PORT_MODE),
.C_P1_PORT_MODE (C1_P1_PORT_MODE),
.C_P2_PORT_MODE (C1_P2_PORT_MODE),
.C_P3_PORT_MODE (C1_P3_PORT_MODE),
.C_P4_PORT_MODE (C1_P4_PORT_MODE),
.C_P5_PORT_MODE (C1_P5_PORT_MODE),
.C_p0_BEGIN_ADDRESS (C1_p0_BEGIN_ADDRESS),
.C_p0_DATA_MODE (C1_p0_DATA_MODE),
.C_p0_END_ADDRESS (C1_p0_END_ADDRESS),
.C_p0_PRBS_EADDR_MASK_POS (C1_p0_PRBS_EADDR_MASK_POS),
.C_p0_PRBS_SADDR_MASK_POS (C1_p0_PRBS_SADDR_MASK_POS),
.C_p1_BEGIN_ADDRESS (C1_p1_BEGIN_ADDRESS),
.C_p1_DATA_MODE (C1_p1_DATA_MODE),
.C_p1_END_ADDRESS (C1_p1_END_ADDRESS),
.C_p1_PRBS_EADDR_MASK_POS (C1_p1_PRBS_EADDR_MASK_POS),
.C_p1_PRBS_SADDR_MASK_POS (C1_p1_PRBS_SADDR_MASK_POS),
.C_p2_BEGIN_ADDRESS (C1_p2_BEGIN_ADDRESS),
.C_p2_DATA_MODE (C1_p2_DATA_MODE),
.C_p2_END_ADDRESS (C1_p2_END_ADDRESS),
.C_p2_PRBS_EADDR_MASK_POS (C1_p2_PRBS_EADDR_MASK_POS),
.C_p2_PRBS_SADDR_MASK_POS (C1_p2_PRBS_SADDR_MASK_POS),
.C_p3_BEGIN_ADDRESS (C1_p3_BEGIN_ADDRESS),
.C_p3_DATA_MODE (C1_p3_DATA_MODE),
.C_p3_END_ADDRESS (C1_p3_END_ADDRESS),
.C_p3_PRBS_EADDR_MASK_POS (C1_p3_PRBS_EADDR_MASK_POS),
.C_p3_PRBS_SADDR_MASK_POS (C1_p3_PRBS_SADDR_MASK_POS),
.C_p4_BEGIN_ADDRESS (C1_p4_BEGIN_ADDRESS),
.C_p4_DATA_MODE (C1_p4_DATA_MODE),
.C_p4_END_ADDRESS (C1_p4_END_ADDRESS),
.C_p4_PRBS_EADDR_MASK_POS (C1_p4_PRBS_EADDR_MASK_POS),
.C_p4_PRBS_SADDR_MASK_POS (C1_p4_PRBS_SADDR_MASK_POS),
.C_p5_BEGIN_ADDRESS (C1_p5_BEGIN_ADDRESS),
.C_p5_DATA_MODE (C1_p5_DATA_MODE),
.C_p5_END_ADDRESS (C1_p5_END_ADDRESS),
.C_p5_PRBS_EADDR_MASK_POS (C1_p5_PRBS_EADDR_MASK_POS),
.C_p5_PRBS_SADDR_MASK_POS (C1_p5_PRBS_SADDR_MASK_POS)
)
memc1_tb_top_inst
(
.error (c1_error),
.calib_done (c1_calib_done),
.clk0 (c1_clk0),
.rst0 (c1_rst0),
.cmp_error (c1_cmp_error),
.cmp_data_valid (c1_cmp_data_valid),
.cmp_data (c1_cmp_data),
.vio_modify_enable (c1_vio_modify_enable),
.vio_data_mode_value (c1_vio_data_mode_value),
.vio_addr_mode_value (c1_vio_addr_mode_value),
.p0_error_status (c1_p0_error_status),
.p1_error_status (c1_p1_error_status),
.p2_error_status (c1_p2_error_status),
.p3_error_status (c1_p3_error_status),
.p4_error_status (c1_p4_error_status),
.p5_error_status (c1_p5_error_status),
// The following port map shows that all the memory controller ports are connected
// to the test bench top. However, a traffic generator can be connected to the
// corresponding port only if the port is enabled, whose information can be obtained
// from the parameters C_PORT_ENABLE.
// User Port-0 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_mcb_cmd_en (c1_p0_cmd_en),
.p0_mcb_cmd_instr (c1_p0_cmd_instr),
.p0_mcb_cmd_bl (c1_p0_cmd_bl),
.p0_mcb_cmd_addr (c1_p0_cmd_byte_addr),
.p0_mcb_cmd_full (c1_p0_cmd_full),
// User Port-0 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_mcb_wr_en (c1_p0_wr_en),
.p0_mcb_wr_mask (c1_p0_wr_mask),
.p0_mcb_wr_data (c1_p0_wr_data),
.p0_mcb_wr_full (c1_p0_wr_full),
.p0_mcb_wr_fifo_counts (c1_p0_wr_count),
// User Port-0 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_mcb_rd_en (c1_p0_rd_en),
.p0_mcb_rd_data (c1_p0_rd_data),
.p0_mcb_rd_empty (c1_p0_rd_empty),
.p0_mcb_rd_fifo_counts (c1_p0_rd_count),
// User Port-1 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_mcb_cmd_en (c1_p1_cmd_en),
.p1_mcb_cmd_instr (c1_p1_cmd_instr),
.p1_mcb_cmd_bl (c1_p1_cmd_bl),
.p1_mcb_cmd_addr (c1_p1_cmd_byte_addr),
.p1_mcb_cmd_full (c1_p1_cmd_full),
// User Port-1 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_mcb_wr_en (c1_p1_wr_en),
.p1_mcb_wr_mask (c1_p1_wr_mask),
.p1_mcb_wr_data (c1_p1_wr_data),
.p1_mcb_wr_full (c1_p1_wr_full),
.p1_mcb_wr_fifo_counts (c1_p1_wr_count),
// User Port-1 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_mcb_rd_en (c1_p1_rd_en),
.p1_mcb_rd_data (c1_p1_rd_data),
.p1_mcb_rd_empty (c1_p1_rd_empty),
.p1_mcb_rd_fifo_counts (c1_p1_rd_count),
// User Port-2 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2 and Config-3
.p2_mcb_cmd_en (c1_p2_cmd_en),
.p2_mcb_cmd_instr (c1_p2_cmd_instr),
.p2_mcb_cmd_bl (c1_p2_cmd_bl),
.p2_mcb_cmd_addr (c1_p2_cmd_byte_addr),
.p2_mcb_cmd_full (c1_p2_cmd_full),
// User Port-2 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction, Config-2 and Config-3
.p2_mcb_wr_en (c1_p2_wr_en),
.p2_mcb_wr_mask (c1_p2_wr_mask),
.p2_mcb_wr_data (c1_p2_wr_data),
.p2_mcb_wr_full (c1_p2_wr_full),
.p2_mcb_wr_fifo_counts (c1_p2_wr_count),
// User Port-2 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction, Config-2 and Config-3
.p2_mcb_rd_en (c1_p2_rd_en),
.p2_mcb_rd_data (c1_p2_rd_data),
.p2_mcb_rd_empty (c1_p2_rd_empty),
.p2_mcb_rd_fifo_counts (c1_p2_rd_count),
// User Port-3 command interface will be active only when the port is enabled in
// the port configurations Config-1 and Config-2
.p3_mcb_cmd_en (c1_p3_cmd_en),
.p3_mcb_cmd_instr (c1_p3_cmd_instr),
.p3_mcb_cmd_bl (c1_p3_cmd_bl),
.p3_mcb_cmd_addr (c1_p3_cmd_byte_addr),
.p3_mcb_cmd_full (c1_p3_cmd_full),
// User Port-3 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction and Config-2
.p3_mcb_wr_en (c1_p3_wr_en),
.p3_mcb_wr_mask (c1_p3_wr_mask),
.p3_mcb_wr_data (c1_p3_wr_data),
.p3_mcb_wr_full (c1_p3_wr_full),
.p3_mcb_wr_fifo_counts (c1_p3_wr_count),
// User Port-3 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction and Config-2
.p3_mcb_rd_en (c1_p3_rd_en),
.p3_mcb_rd_data (c1_p3_rd_data),
.p3_mcb_rd_empty (c1_p3_rd_empty),
.p3_mcb_rd_fifo_counts (c1_p3_rd_count),
// User Port-4 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p4_mcb_cmd_en (c1_p4_cmd_en),
.p4_mcb_cmd_instr (c1_p4_cmd_instr),
.p4_mcb_cmd_bl (c1_p4_cmd_bl),
.p4_mcb_cmd_addr (c1_p4_cmd_byte_addr),
.p4_mcb_cmd_full (c1_p4_cmd_full),
// User Port-4 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p4_mcb_wr_en (c1_p4_wr_en),
.p4_mcb_wr_mask (c1_p4_wr_mask),
.p4_mcb_wr_data (c1_p4_wr_data),
.p4_mcb_wr_full (c1_p4_wr_full),
.p4_mcb_wr_fifo_counts (c1_p4_wr_count),
// User Port-4 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p4_mcb_rd_en (c1_p4_rd_en),
.p4_mcb_rd_data (c1_p4_rd_data),
.p4_mcb_rd_empty (c1_p4_rd_empty),
.p4_mcb_rd_fifo_counts (c1_p4_rd_count),
// User Port-5 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p5_mcb_cmd_en (c1_p5_cmd_en),
.p5_mcb_cmd_instr (c1_p5_cmd_instr),
.p5_mcb_cmd_bl (c1_p5_cmd_bl),
.p5_mcb_cmd_addr (c1_p5_cmd_byte_addr),
.p5_mcb_cmd_full (c1_p5_cmd_full),
// User Port-5 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p5_mcb_wr_en (c1_p5_wr_en),
.p5_mcb_wr_mask (c1_p5_wr_mask),
.p5_mcb_wr_data (c1_p5_wr_data),
.p5_mcb_wr_full (c1_p5_wr_full),
.p5_mcb_wr_fifo_counts (c1_p5_wr_count),
// User Port-5 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p5_mcb_rd_en (c1_p5_rd_en),
.p5_mcb_rd_data (c1_p5_rd_data),
.p5_mcb_rd_empty (c1_p5_rd_empty),
.p5_mcb_rd_fifo_counts (c1_p5_rd_count)
);
// Test bench top for the controller-3
memc_tb_top #
(
.C_SIMULATION (C3_SIMULATION),
.C_NUM_DQ_PINS (C3_NUM_DQ_PINS),
.C_MEM_BURST_LEN (C3_MEM_BURST_LEN),
.C_MEM_NUM_COL_BITS (C3_MEM_NUM_COL_BITS),
.C_SMALL_DEVICE (C3_SMALL_DEVICE),
// The following parameters from C_PORT_ENABLE to C_P5_PORT_MODE are introduced
// to handle the static instances of all the six traffic generators inside the
// memc_tb_top module.
.C_PORT_ENABLE (C3_PORT_ENABLE),
.C_P0_MASK_SIZE (C3_P0_MASK_SIZE),
.C_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE),
.C_P1_MASK_SIZE (C3_P1_MASK_SIZE),
.C_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE),
.C_P0_PORT_MODE (C3_P0_PORT_MODE),
.C_P1_PORT_MODE (C3_P1_PORT_MODE),
.C_P2_PORT_MODE (C3_P2_PORT_MODE),
.C_P3_PORT_MODE (C3_P3_PORT_MODE),
.C_P4_PORT_MODE (C3_P4_PORT_MODE),
.C_P5_PORT_MODE (C3_P5_PORT_MODE),
.C_p0_BEGIN_ADDRESS (C3_p0_BEGIN_ADDRESS),
.C_p0_DATA_MODE (C3_p0_DATA_MODE),
.C_p0_END_ADDRESS (C3_p0_END_ADDRESS),
.C_p0_PRBS_EADDR_MASK_POS (C3_p0_PRBS_EADDR_MASK_POS),
.C_p0_PRBS_SADDR_MASK_POS (C3_p0_PRBS_SADDR_MASK_POS),
.C_p1_BEGIN_ADDRESS (C3_p1_BEGIN_ADDRESS),
.C_p1_DATA_MODE (C3_p1_DATA_MODE),
.C_p1_END_ADDRESS (C3_p1_END_ADDRESS),
.C_p1_PRBS_EADDR_MASK_POS (C3_p1_PRBS_EADDR_MASK_POS),
.C_p1_PRBS_SADDR_MASK_POS (C3_p1_PRBS_SADDR_MASK_POS),
.C_p2_BEGIN_ADDRESS (C3_p2_BEGIN_ADDRESS),
.C_p2_DATA_MODE (C3_p2_DATA_MODE),
.C_p2_END_ADDRESS (C3_p2_END_ADDRESS),
.C_p2_PRBS_EADDR_MASK_POS (C3_p2_PRBS_EADDR_MASK_POS),
.C_p2_PRBS_SADDR_MASK_POS (C3_p2_PRBS_SADDR_MASK_POS),
.C_p3_BEGIN_ADDRESS (C3_p3_BEGIN_ADDRESS),
.C_p3_DATA_MODE (C3_p3_DATA_MODE),
.C_p3_END_ADDRESS (C3_p3_END_ADDRESS),
.C_p3_PRBS_EADDR_MASK_POS (C3_p3_PRBS_EADDR_MASK_POS),
.C_p3_PRBS_SADDR_MASK_POS (C3_p3_PRBS_SADDR_MASK_POS),
.C_p4_BEGIN_ADDRESS (C3_p4_BEGIN_ADDRESS),
.C_p4_DATA_MODE (C3_p4_DATA_MODE),
.C_p4_END_ADDRESS (C3_p4_END_ADDRESS),
.C_p4_PRBS_EADDR_MASK_POS (C3_p4_PRBS_EADDR_MASK_POS),
.C_p4_PRBS_SADDR_MASK_POS (C3_p4_PRBS_SADDR_MASK_POS),
.C_p5_BEGIN_ADDRESS (C3_p5_BEGIN_ADDRESS),
.C_p5_DATA_MODE (C3_p5_DATA_MODE),
.C_p5_END_ADDRESS (C3_p5_END_ADDRESS),
.C_p5_PRBS_EADDR_MASK_POS (C3_p5_PRBS_EADDR_MASK_POS),
.C_p5_PRBS_SADDR_MASK_POS (C3_p5_PRBS_SADDR_MASK_POS)
)
memc3_tb_top_inst
(
.error (c3_error),
.calib_done (c3_calib_done),
.clk0 (c3_clk0),
.rst0 (c3_rst0),
.cmp_error (c3_cmp_error),
.cmp_data_valid (c3_cmp_data_valid),
.cmp_data (c3_cmp_data),
.vio_modify_enable (c3_vio_modify_enable),
.vio_data_mode_value (c3_vio_data_mode_value),
.vio_addr_mode_value (c3_vio_addr_mode_value),
.p0_error_status (c3_p0_error_status),
.p1_error_status (c3_p1_error_status),
.p2_error_status (c3_p2_error_status),
.p3_error_status (c3_p3_error_status),
.p4_error_status (c3_p4_error_status),
.p5_error_status (c3_p5_error_status),
// The following port map shows that all the memory controller ports are connected
// to the test bench top. However, a traffic generator can be connected to the
// corresponding port only if the port is enabled, whose information can be obtained
// from the parameters C_PORT_ENABLE.
// User Port-0 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_mcb_cmd_en (c3_p0_cmd_en),
.p0_mcb_cmd_instr (c3_p0_cmd_instr),
.p0_mcb_cmd_bl (c3_p0_cmd_bl),
.p0_mcb_cmd_addr (c3_p0_cmd_byte_addr),
.p0_mcb_cmd_full (c3_p0_cmd_full),
// User Port-0 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_mcb_wr_en (c3_p0_wr_en),
.p0_mcb_wr_mask (c3_p0_wr_mask),
.p0_mcb_wr_data (c3_p0_wr_data),
.p0_mcb_wr_full (c3_p0_wr_full),
.p0_mcb_wr_fifo_counts (c3_p0_wr_count),
// User Port-0 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_mcb_rd_en (c3_p0_rd_en),
.p0_mcb_rd_data (c3_p0_rd_data),
.p0_mcb_rd_empty (c3_p0_rd_empty),
.p0_mcb_rd_fifo_counts (c3_p0_rd_count),
// User Port-1 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_mcb_cmd_en (c3_p1_cmd_en),
.p1_mcb_cmd_instr (c3_p1_cmd_instr),
.p1_mcb_cmd_bl (c3_p1_cmd_bl),
.p1_mcb_cmd_addr (c3_p1_cmd_byte_addr),
.p1_mcb_cmd_full (c3_p1_cmd_full),
// User Port-1 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_mcb_wr_en (c3_p1_wr_en),
.p1_mcb_wr_mask (c3_p1_wr_mask),
.p1_mcb_wr_data (c3_p1_wr_data),
.p1_mcb_wr_full (c3_p1_wr_full),
.p1_mcb_wr_fifo_counts (c3_p1_wr_count),
// User Port-1 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_mcb_rd_en (c3_p1_rd_en),
.p1_mcb_rd_data (c3_p1_rd_data),
.p1_mcb_rd_empty (c3_p1_rd_empty),
.p1_mcb_rd_fifo_counts (c3_p1_rd_count),
// User Port-2 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2 and Config-3
.p2_mcb_cmd_en (c3_p2_cmd_en),
.p2_mcb_cmd_instr (c3_p2_cmd_instr),
.p2_mcb_cmd_bl (c3_p2_cmd_bl),
.p2_mcb_cmd_addr (c3_p2_cmd_byte_addr),
.p2_mcb_cmd_full (c3_p2_cmd_full),
// User Port-2 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction, Config-2 and Config-3
.p2_mcb_wr_en (c3_p2_wr_en),
.p2_mcb_wr_mask (c3_p2_wr_mask),
.p2_mcb_wr_data (c3_p2_wr_data),
.p2_mcb_wr_full (c3_p2_wr_full),
.p2_mcb_wr_fifo_counts (c3_p2_wr_count),
// User Port-2 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction, Config-2 and Config-3
.p2_mcb_rd_en (c3_p2_rd_en),
.p2_mcb_rd_data (c3_p2_rd_data),
.p2_mcb_rd_empty (c3_p2_rd_empty),
.p2_mcb_rd_fifo_counts (c3_p2_rd_count),
// User Port-3 command interface will be active only when the port is enabled in
// the port configurations Config-1 and Config-2
.p3_mcb_cmd_en (c3_p3_cmd_en),
.p3_mcb_cmd_instr (c3_p3_cmd_instr),
.p3_mcb_cmd_bl (c3_p3_cmd_bl),
.p3_mcb_cmd_addr (c3_p3_cmd_byte_addr),
.p3_mcb_cmd_full (c3_p3_cmd_full),
// User Port-3 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction and Config-2
.p3_mcb_wr_en (c3_p3_wr_en),
.p3_mcb_wr_mask (c3_p3_wr_mask),
.p3_mcb_wr_data (c3_p3_wr_data),
.p3_mcb_wr_full (c3_p3_wr_full),
.p3_mcb_wr_fifo_counts (c3_p3_wr_count),
// User Port-3 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction and Config-2
.p3_mcb_rd_en (c3_p3_rd_en),
.p3_mcb_rd_data (c3_p3_rd_data),
.p3_mcb_rd_empty (c3_p3_rd_empty),
.p3_mcb_rd_fifo_counts (c3_p3_rd_count),
// User Port-4 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p4_mcb_cmd_en (c3_p4_cmd_en),
.p4_mcb_cmd_instr (c3_p4_cmd_instr),
.p4_mcb_cmd_bl (c3_p4_cmd_bl),
.p4_mcb_cmd_addr (c3_p4_cmd_byte_addr),
.p4_mcb_cmd_full (c3_p4_cmd_full),
// User Port-4 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p4_mcb_wr_en (c3_p4_wr_en),
.p4_mcb_wr_mask (c3_p4_wr_mask),
.p4_mcb_wr_data (c3_p4_wr_data),
.p4_mcb_wr_full (c3_p4_wr_full),
.p4_mcb_wr_fifo_counts (c3_p4_wr_count),
// User Port-4 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p4_mcb_rd_en (c3_p4_rd_en),
.p4_mcb_rd_data (c3_p4_rd_data),
.p4_mcb_rd_empty (c3_p4_rd_empty),
.p4_mcb_rd_fifo_counts (c3_p4_rd_count),
// User Port-5 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p5_mcb_cmd_en (c3_p5_cmd_en),
.p5_mcb_cmd_instr (c3_p5_cmd_instr),
.p5_mcb_cmd_bl (c3_p5_cmd_bl),
.p5_mcb_cmd_addr (c3_p5_cmd_byte_addr),
.p5_mcb_cmd_full (c3_p5_cmd_full),
// User Port-5 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p5_mcb_wr_en (c3_p5_wr_en),
.p5_mcb_wr_mask (c3_p5_wr_mask),
.p5_mcb_wr_data (c3_p5_wr_data),
.p5_mcb_wr_full (c3_p5_wr_full),
.p5_mcb_wr_fifo_counts (c3_p5_wr_count),
// User Port-5 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p5_mcb_rd_en (c3_p5_rd_en),
.p5_mcb_rd_data (c3_p5_rd_data),
.p5_mcb_rd_empty (c3_p5_rd_empty),
.p5_mcb_rd_fifo_counts (c3_p5_rd_count)
);
// ========================================================================== //
// Memory model instances //
// ========================================================================== //
generate
if(C1_NUM_DQ_PINS == 16) begin : MEM_INST1
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs ({mcb1_dram_udm,mcb1_dram_dm}),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs ({mcb1_dram_udqs,mcb1_dram_dqs}),
.dqs_n ({mcb1_dram_udqs_n,mcb1_dram_dqs_n}),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end else begin
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs (mcb1_dram_dm),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs (mcb1_dram_dqs),
.dqs_n (mcb1_dram_dqs_n),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end
endgenerate
generate
if(C3_NUM_DQ_PINS == 16) begin : MEM_INST3
ddr3_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_tdqs ({mcb3_dram_udm,mcb3_dram_dm}),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs ({mcb3_dram_udqs,mcb3_dram_dqs}),
.dqs_n ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
.tdqs_n (),
.odt (mcb3_dram_odt),
.rst_n (mcb3_dram_reset_n)
);
end else begin
ddr3_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_tdqs (mcb3_dram_dm),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs (mcb3_dram_dqs),
.dqs_n (mcb3_dram_dqs_n),
.tdqs_n (),
.odt (mcb3_dram_odt),
.rst_n (mcb3_dram_reset_n)
);
end
endgenerate
// ========================================================================== //
// Reporting the test case status
// ========================================================================== //
initial
begin : Logging
fork
begin : calibration_done
wait (calib_done);
$display("Calibration Done");
#50000000;
if (!error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
#200000000;
if (!calib_done) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_512x20.v,v $
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/27 21:24:04 lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9 2001/11/27 19:45:04 lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [3:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [11:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:0]),
.EN(ce),
.WE(we),
.DO(doq[7:0])
);
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:8]),
.EN(ce),
.WE(we),
.DO(doq[15:8])
);
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI({4'b0000, di[19:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[19:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI({12'h000,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected,doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_BLACKBOX_V
`define SKY130_FD_SC_MS__O2111A_BLACKBOX_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_BLACKBOX_V
|
Require Import Verdi.Verdi.
Require Import Verdi.HandlerMonad.
Require Import Verdi.NameOverlay.
Require Import Verdi.LabeledNet.
Require Import NameAdjacency.
Require Import FailureRecorderStaticLabeled.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.classical.
Require Import Sumbool.
Require Import MSetFacts.
Require Import MSetProperties.
Require Import mathcomp.ssreflect.ssreflect.
Local Arguments update {_} {_} _ _ _ _ _ : simpl never.
Set Implicit Arguments.
Module FailureRecorderCorrect (Import NT : NameType)
(NOT : NameOrderedType NT) (NSet : MSetInterface.S with Module E := NOT)
(Import ANT : AdjacentNameType NT) (Import A : Adjacency NT NOT NSet ANT).
Module FR := FailureRecorder NT NOT NSet ANT A.
Import FR.
Module NSetFacts := Facts NSet.
Module NSetProps := Properties NSet.
Module NSetOrdProps := OrdProperties NSet.
Lemma Failure_node_not_adjacent_self :
forall net failed tr n,
step_ordered_failure_star step_ordered_failure_init (failed, net) tr ->
~ In n failed ->
~ NSet.In n (onwState net n).(adjacent).
Proof.
move => net failed tr n H.
remember step_ordered_failure_init as y in *.
have ->: failed = fst (failed, net) by [].
have ->: net = snd (failed, net) by [].
move: Heqy.
induction H using refl_trans_1n_trace_n1_ind => H_init /=.
rewrite H_init /step_ordered_failure_init /=.
move => H_f.
exact: not_adjacent_self.
move => H_f.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; rewrite /=.
- find_apply_lem_hyp net_handlers_NetHandler; break_exists.
rewrite /update /=.
case name_eq_dec => H_dec /=; last exact: IHrefl_trans_1n_trace1.
rewrite -H_dec in H3.
net_handler_cases.
find_apply_lem_hyp NSet.remove_spec.
by break_and.
- by find_apply_lem_hyp input_handlers_IOHandler.
- exact: IHrefl_trans_1n_trace1.
Qed.
Lemma Failure_self_channel_empty :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n, ~ In n failed ->
onet.(onwPackets) n n = [].
Proof.
move => onet failed tr H.
have H_eq_f: failed = fst (failed, onet) by [].
have H_eq_o: onet = snd (failed, onet) by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in *.
move: Heqy.
induction H using refl_trans_1n_trace_n1_ind => H_init {failed}; first by rewrite H_init /step_ordered_failure_init /=.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases.
rewrite /= /update2.
case (sumbool_and _ _ _ _) => H_dec; last exact: IHrefl_trans_1n_trace1.
move: H_dec => [H_dec H_dec'].
rewrite H_dec H_dec' in H2.
by rewrite IHrefl_trans_1n_trace1 in H2.
- by find_apply_lem_hyp input_handlers_IOHandler.
- move => n H_in.
rewrite collate_neq.
apply: IHrefl_trans_1n_trace1.
move => H_in'.
case: H_in.
by right.
move => H_eq.
by case: H_in; left.
Qed.
Lemma Failure_not_failed_no_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
~ In Fail (onet.(onwPackets) n n').
Proof.
move => onet failed tr H.
have H_eq_f: failed = fst (failed, onet) by [].
have H_eq_o: onet = snd (failed, onet) by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in *.
move: Heqy.
induction H using refl_trans_1n_trace_n1_ind => H_init {failed}; first by rewrite H_init /step_ordered_failure_init /=.
concludes.
move => n n' H_in.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases.
simpl in *.
contradict H4.
have H_in' := IHrefl_trans_1n_trace1 _ n' H_in.
rewrite /update2 /=.
case (sumbool_and _ _ _ _) => H_dec //.
move: H_dec => [H_eq H_eq'].
rewrite H_eq H_eq' in H2.
rewrite H2 in H_in'.
move => H_inn.
case: H_in'.
by right.
- by find_apply_lem_hyp input_handlers_IOHandler.
- rewrite /= in H_in.
have H_neq: h <> n by move => H_eq; case: H_in; left.
have H_f: ~ In n failed by move => H_in''; case: H_in; right.
rewrite collate_neq //.
exact: IHrefl_trans_1n_trace1.
Qed.
Section SingleNodeInv.
Variable onet : ordered_network.
Variable failed : list name.
Variable tr : list (name * (input + output)).
Hypothesis H_step : step_ordered_failure_star step_ordered_failure_init (failed, onet) tr.
Variable n : name.
Hypothesis not_failed : ~ In n failed.
Variable P : Data -> Prop.
Hypothesis after_init : P (InitData n).
Hypothesis recv_fail :
forall onet failed tr n',
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
~ In n failed ->
P (onet.(onwState) n) ->
P (mkData (NSet.remove n' (onet.(onwState) n).(adjacent))).
Theorem P_inv_n : P (onwState onet n).
Proof.
move: onet failed tr H_step not_failed.
clear onet failed not_failed tr H_step.
move => onet' failed' tr H'_step.
have H_eq_f: failed' = fst (failed', onet') by [].
have H_eq_o: onet' = snd (failed', onet') by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in H'_step.
move: Heqy.
induction H'_step using refl_trans_1n_trace_n1_ind => /= H_init.
rewrite H_init /step_ordered_init /= => H_in_f.
exact: after_init.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- move => H_in_f.
find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases.
rewrite /update /=.
case name_eq_dec => H_dec //.
repeat find_rewrite.
destruct d.
simpl in *.
aggressive_rewrite_goal.
exact: (recv_fail _ H'_step1).
- by find_apply_lem_hyp input_handlers_IOHandler.
- move => H_in_f.
apply: IHH'_step1.
move => H'_in_f.
case: H_in_f.
by right.
Qed.
End SingleNodeInv.
Section SingleNodeInvOut.
Variable onet : ordered_network.
Variable failed : list name.
Variable tr : list (name * (input + output)).
Hypothesis H_step : step_ordered_failure_star step_ordered_failure_init (failed, onet) tr.
Variables n n' : name.
Hypothesis not_failed : ~ In n failed.
Variable P : Data -> list msg -> Prop.
Hypothesis after_init : P (InitData n) [].
Hypothesis recv_fail_from_eq :
forall onet failed tr ms,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
~ In n failed ->
In n' failed ->
n' <> n ->
onet.(onwPackets) n' n = Fail :: ms ->
P (onet.(onwState) n) (onet.(onwPackets) n n') ->
P (mkData (NSet.remove n' (onet.(onwState) n).(adjacent))) (onet.(onwPackets) n n').
Hypothesis recv_fail_from_neq :
forall onet failed tr from ms,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
~ In n failed ->
In from failed ->
from <> n ->
from <> n' ->
onet.(onwPackets) from n = Fail :: ms ->
P (onet.(onwState) n) (onet.(onwPackets) n n') ->
P (mkData (NSet.remove from (onet.(onwState) n).(adjacent))) (onet.(onwPackets) n n').
Theorem P_inv_n_out : P (onet.(onwState) n) (onet.(onwPackets) n n').
Proof.
move: onet failed tr H_step not_failed.
clear onet failed not_failed tr H_step.
move => onet' failed' tr H'_step.
have H_eq_f: failed' = fst (failed', onet') by [].
have H_eq_o: onet' = snd (failed', onet') by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2 3}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in H'_step.
move: Heqy.
induction H'_step using refl_trans_1n_trace_n1_ind => /= H_init.
rewrite H_init /step_ordered_failure_init /= => H_in_f.
exact: after_init.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- move => H_in_f.
find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases.
rewrite /update /=.
case name_eq_dec => H_dec.
rewrite -H_dec in H1 H6 H0.
rewrite -H_dec /update2 /= {H_dec to H'_step2}.
case (sumbool_and _ _ _ _) => H_dec.
move: H_dec => [H_eq H_eq'].
rewrite H_eq {H_eq from} in H6 H0.
by rewrite (Failure_self_channel_empty H'_step1) in H0.
case: d H6 => /=.
move => adjacent0 H_eq.
rewrite H_eq {adjacent0 H_eq}.
case: H_dec => H_dec.
case (name_eq_dec from n') => H_dec'.
rewrite H_dec'.
rewrite H_dec' in H0 H_dec.
case (In_dec name_eq_dec n' failed) => H_in; first exact: (recv_fail_from_eq H'_step1 _ _ _ H0).
have H_inl := Failure_not_failed_no_fail H'_step1 _ n H_in.
rewrite H0 in H_inl.
by case: H_inl; left.
case (In_dec name_eq_dec from failed) => H_in; first exact: (recv_fail_from_neq H'_step1 _ _ _ _ H0).
have H_inl := Failure_not_failed_no_fail H'_step1 _ n H_in.
rewrite H0 in H_inl.
by case: H_inl; left.
case (name_eq_dec from n) => H_neq; first by rewrite H_neq (Failure_self_channel_empty H'_step1) in H0.
case (name_eq_dec from n') => H_dec'.
rewrite H_dec'.
rewrite H_dec' in H0 H_dec.
case (In_dec name_eq_dec n' failed) => H_in; first by apply: (recv_fail_from_eq H'_step1 _ _ _ H0) => //; auto.
have H_inl := Failure_not_failed_no_fail H'_step1 _ n H_in.
rewrite H0 in H_inl.
by case: H_inl; left.
case (In_dec name_eq_dec from failed) => H_in; first exact: (recv_fail_from_neq H'_step1 _ _ _ _ H0).
have H_inl := Failure_not_failed_no_fail H'_step1 _ n H_in.
rewrite H0 in H_inl.
by case: H_inl; left.
rewrite /update2 /=.
case (sumbool_and _ _ _ _) => H_dec' //.
move: H_dec' => [H_eq H_eq'].
rewrite H_eq H_eq' in H0 H1 H5 H_dec.
have H_f := Failure_not_failed_no_fail H'_step1 _ n' H_in_f.
rewrite H0 in H_f.
by case: H_f; left.
- by find_apply_lem_hyp input_handlers_IOHandler.
- move => H_in.
have H_neq: h <> n by move => H_eq; case: H_in; left.
have H_f: ~ In n failed by move => H_in'; case: H_in; right.
rewrite collate_neq //.
exact: IHH'_step1.
Qed.
End SingleNodeInvOut.
Section SingleNodeInvIn.
Variable onet : ordered_network.
Variable failed : list name.
Variable tr : list (name * (input + output)).
Hypothesis H_step : step_ordered_failure_star step_ordered_failure_init (failed, onet) tr.
Variables n n' : name.
Hypothesis not_failed : ~ In n failed.
Variable P : Data -> list msg -> Prop.
Hypothesis after_init : P (InitData n) [].
Hypothesis recv_fail_neq :
forall onet failed tr ms,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
~ In n failed ->
In n' failed ->
n <> n' ->
onet.(onwPackets) n' n = Fail :: ms ->
P (onet.(onwState) n) (onet.(onwPackets) n' n) ->
P (mkData (NSet.remove n' (onet.(onwState) n).(adjacent))) ms.
Hypothesis recv_fail_other_neq :
forall onet failed tr from ms,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
~ In n failed ->
n <> from ->
n' <> from ->
onet.(onwPackets) from n = Fail :: ms ->
P (onet.(onwState) n) (onet.(onwPackets) n' n) ->
P (mkData (NSet.remove from (onet.(onwState) n).(adjacent))) (onet.(onwPackets) n' n).
Hypothesis fail_adjacent :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
n' <> n ->
~ In n failed ->
~ In n' failed ->
adjacent_to n' n ->
P (onet.(onwState) n) (onet.(onwPackets) n' n) ->
P (onwState onet n) (onwPackets onet n' n ++ [Fail]).
Theorem P_inv_n_in : P (onet.(onwState) n) (onet.(onwPackets) n' n).
Proof.
move: onet failed tr H_step not_failed.
clear onet failed not_failed tr H_step.
move => onet' failed' tr H'_step.
have H_eq_f: failed' = fst (failed', onet') by [].
have H_eq_o: onet' = snd (failed', onet') by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2 3}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in H'_step.
move: Heqy.
induction H'_step using refl_trans_1n_trace_n1_ind => /= H_init.
rewrite H_init /step_ordered_failure_init /= => H_in_f.
exact: after_init.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- move => H_in_f.
find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases.
rewrite /update /=.
case name_eq_dec => H_dec.
rewrite -H_dec in H1 H6 H0.
have H_neq: n <> from.
move => H_eq.
rewrite -H_eq in H0.
by rewrite (Failure_self_channel_empty H'_step1) in H0.
rewrite -H_dec /update2 /= {H_dec to H'_step2}.
case (sumbool_and _ _ _ _) => H_dec.
move: H_dec => [H_eq H_eq'].
rewrite H_eq {H_eq from} in H0 H6 H_neq.
case: d H6 => /= adjacent0 H_eq.
rewrite H_eq {H_eq adjacent0}.
case (In_dec name_eq_dec n' failed) => H_in; first exact: (recv_fail_neq H'_step1).
have H_inl := Failure_not_failed_no_fail H'_step1 _ n H_in.
rewrite H0 in H_inl.
by case: H_inl; left.
case: H_dec => H_dec //.
case: d H6 => /= adjacent0 H_eq.
rewrite H_eq {H_eq adjacent0}.
apply: (recv_fail_other_neq H'_step1 _ _ _ H0) => //.
move => H_neq'.
by case: H_dec.
rewrite /update2 /=.
case (sumbool_and _ _ _ _) => H_dec' //.
move: H_dec' => [H_eq H_eq'].
by rewrite H_eq' in H_dec.
- by find_apply_lem_hyp input_handlers_IOHandler.
- move => H_in.
have H_neq: h <> n by move => H_eq; case: H_in; left.
have H_f: ~ In n failed by move => H_in'; case: H_in; right.
case (name_eq_dec h n') => H_dec.
rewrite H_dec in H0 H_neq H_f.
rewrite H_dec {H_dec h H'_step2 H_in}.
case (adjacent_to_dec n' n) => H_dec.
rewrite collate_map2snd_not_in_related //.
* apply (fail_adjacent H'_step1) => //.
exact: IHH'_step1.
* exact: all_names_nodes.
* exact: no_dup_nodes.
rewrite collate_map2snd_not_related //.
exact: IHH'_step1.
rewrite collate_neq //.
exact: IHH'_step1.
Qed.
End SingleNodeInvIn.
Section DualNodeInv.
Variable onet : ordered_network.
Variable failed : list name.
Variable tr : list (name * (input + output)).
Hypothesis H_step : step_ordered_failure_star step_ordered_failure_init (failed, onet) tr.
Variables n n' : name.
Hypothesis not_failed_n : ~ In n failed.
Hypothesis not_failed_n' : ~ In n' failed.
Variable P : Data -> Data -> list msg -> list msg -> Prop.
(* FIXME *)
Hypothesis after_init : P (InitData n) (InitData n') [] [].
Hypothesis recv_fail_self :
forall onet failed tr from ms,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
n' = n ->
~ In n failed ->
onet.(onwPackets) from n = Fail :: ms ->
n <> from ->
P (onet.(onwState) n) (onet.(onwState) n) (onet.(onwPackets) n n) (onet.(onwPackets) n n) ->
P (mkData (NSet.remove from (onet.(onwState) n).(adjacent)))
(mkData (NSet.remove from (onet.(onwState) n).(adjacent)))
(onet.(onwPackets) n n) (onet.(onwPackets) n n).
Hypothesis recv_fail_other :
forall onet failed tr from ms,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
~ In n failed ->
~ In n' failed ->
onet.(onwPackets) from n = Fail :: ms ->
n <> n' ->
from <> n ->
from <> n' ->
P (onet.(onwState) n) (onet.(onwState) n') (onet.(onwPackets) n n') (onet.(onwPackets) n' n) ->
P (mkData (NSet.remove from (onet.(onwState) n).(adjacent))) (onet.(onwState) n')
(onet.(onwPackets) n n') (onet.(onwPackets) n' n).
Hypothesis recv_other_fail :
forall onet failed tr from ms,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
~ In n failed ->
~ In n' failed ->
onet.(onwPackets) from n' = Fail :: ms ->
n <> n' ->
from <> n ->
from <> n' ->
P (onet.(onwState) n) (onet.(onwState) n') (onet.(onwPackets) n n') (onet.(onwPackets) n' n) ->
P (onet.(onwState) n) (mkData (NSet.remove from (onet.(onwState) n').(adjacent)))
(onet.(onwPackets) n n') (onet.(onwPackets) n' n).
Theorem P_dual_inv : P (onet.(onwState) n) (onet.(onwState) n') (onet.(onwPackets) n n') (onet.(onwPackets) n' n).
Proof.
move: onet failed tr H_step not_failed_n not_failed_n'.
clear onet failed not_failed_n not_failed_n' tr H_step.
move => onet' failed' tr H'_step.
have H_eq_f: failed' = fst (failed', onet') by [].
have H_eq_o: onet' = snd (failed', onet') by [].
rewrite H_eq_f {H_eq_f}.
rewrite {3 4 5 6}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in H'_step.
move: Heqy.
induction H'_step using refl_trans_1n_trace_n1_ind => /= H_init.
rewrite H_init /step_ordered_failure_init /= => H_in_f H_in_f'.
exact: after_init.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- rewrite /= in IHH'_step1.
move {H'_step2}.
move => H_in_f H_in_f'.
find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases.
rewrite /update /=.
case name_eq_dec => H_dec_n.
rewrite -H_dec_n.
rewrite -H_dec_n {H_dec_n to} in H6 H7 H1 H0.
case name_eq_dec => H_dec_n'.
rewrite H_dec_n'.
rewrite H_dec_n' in H_in_f' H7.
rewrite /update2.
case (sumbool_and _ _ _ _) => H_dec.
move: H_dec => [H_eq H_eq'].
rewrite H_eq in H0.
by rewrite (Failure_self_channel_empty H'_step1) in H0.
case: H_dec => H_dec //.
case: d H6 => /= adjacent0 H_eq.
rewrite H_eq {H_eq adjacent0}.
apply (recv_fail_self H'_step1 H_dec_n' H1 H0) => //.
move => H_neq.
by rewrite H_neq in H_dec.
case: d H6 => /= adjacent0 H_eq.
rewrite H_eq {H_eq adjacent0}.
rewrite /update2 /=.
case (sumbool_and _ _ _ _) => H_dec; case (sumbool_and _ _ _ _) => H_dec'.
* move: H_dec => [H_eq_n H_eq_n'].
by rewrite H_eq_n' in H_dec_n'.
* move: H_dec => [H_eq_n H_eq_n'].
by rewrite H_eq_n' in H_dec_n'.
* move: H_dec' => [H_eq_n H_eq_n'].
rewrite H_eq_n in H0.
have H_inl := Failure_not_failed_no_fail H'_step1 _ n H_in_f'.
case: H_inl.
by rewrite H0; left.
* case: H_dec' => H_dec' //.
have H_neq: from <> n.
move => H_eq'.
rewrite H_eq' in H0.
by rewrite (Failure_self_channel_empty H'_step1) in H0.
move {H_dec}.
apply (recv_fail_other H'_step1 H_in_f H_in_f' H0) => //.
move => H_neq'.
by rewrite H_neq' in H_dec_n'.
case name_eq_dec => H_dec_n'.
rewrite -H_dec_n'.
rewrite -H_dec_n' {to H_dec_n'} in H0 H_dec_n H1 H6.
case: d H6 => /= adjacent0 H_eq.
rewrite H_eq {adjacent0 H_eq}.
rewrite /update2 /=.
case (sumbool_and _ _ _ _) => H_dec; case (sumbool_and _ _ _ _) => H_dec'.
* move: H_dec' => [H_eq H_eq'].
by rewrite H_eq' in H_dec_n.
* move: H_dec => [H_eq H_eq'].
rewrite H_eq in H0.
have H_inl := Failure_not_failed_no_fail H'_step1 _ n' H_in_f.
case: H_inl.
rewrite H0.
by left.
* move: H_dec' => [H_eq H_eq'].
by rewrite H_eq' in H_dec_n.
* case: H_dec => H_dec //.
have H_neq: from <> n'.
move => H_eq'.
rewrite H_eq' in H0.
by rewrite (Failure_self_channel_empty H'_step1) in H0.
move {H_dec'}.
exact: (recv_other_fail H'_step1 H_in_f H_in_f' H0).
rewrite /update2 /=.
case (sumbool_and _ _ _ _) => H_dec; case (sumbool_and _ _ _ _) => H_dec'.
* move: H_dec => [H_eq H_eq'].
by rewrite H_eq' in H_dec_n'.
* move: H_dec => [H_eq H_eq'].
by rewrite H_eq' in H_dec_n'.
* move: H_dec' => [H_eq H_eq'].
by rewrite H_eq' in H_dec_n.
* exact: H7.
- rewrite /= in IHH'_step1.
move {H'_step2}.
move => H_in_f H_in_f'.
find_apply_lem_hyp input_handlers_IOHandler; break_exists.
by io_handler_cases.
- rewrite /= in IHH'_step1.
move => H_nor H_nor'.
have H_neq: h <> n.
move => H_eq.
case: H_nor.
by left.
have H_in_f: ~ In n failed.
move => H_in_f.
case: H_nor.
by right.
have H_neq': h <> n'.
move => H_eq.
case: H_nor'.
by left.
have H_in_f': ~ In n' failed.
move => H_in_f'.
case: H_nor'.
by right.
have IH := IHH'_step1 H_in_f H_in_f'.
move {H_nor H_nor' IHH'_step1}.
rewrite collate_neq //.
by rewrite collate_neq.
Qed.
End DualNodeInv.
Lemma Failure_in_adj_adjacent_to :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall (n n' : name),
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
adjacent_to n' n.
Proof.
move => net failed tr H_st.
move => n n' H_f.
pose P_curr (d : Data) := NSet.In n' d.(adjacent) -> adjacent_to n' n.
rewrite -/(P_curr _).
apply: (P_inv_n H_st); rewrite /P_curr //= {P_curr net tr H_st failed H_f}.
- move => H_ins.
apply adjacent_to_node_adjacency in H_ins.
apply filter_rel_related in H_ins.
move: H_ins => [H_in H_adj].
by apply adjacent_to_symmetric in H_adj.
- move => net failed tr n0 H_st H_in_f IH H_adj.
apply: IH.
by apply NSetFacts.remove_3 in H_adj.
Qed.
Lemma Failure_in_adj_or_incoming_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
~ In n' failed \/ (In n' failed /\ In Fail (onet.(onwPackets) n' n)).
Proof.
move => onet failed tr H.
have H_eq_f: failed = fst (failed, onet) by [].
have H_eq_o: onet = snd (failed, onet) by [].
rewrite H_eq_f {H_eq_f}.
rewrite {2 5}H_eq_o {H_eq_o}.
remember step_ordered_failure_init as y in *.
move: Heqy.
induction H using refl_trans_1n_trace_n1_ind => /= H_init.
rewrite H_init /= {H_init}.
move => n n' H_ins.
by left.
concludes.
match goal with
| [ H : step_ordered_failure _ _ _ |- _ ] => invc H
end; simpl.
- move => n n' H_in_f H_ins.
find_apply_lem_hyp net_handlers_NetHandler; break_exists.
net_handler_cases.
rewrite /= /update2 {H1}.
case (sumbool_and _ _ _ _) => H_dec.
move: H_dec => [H_eq H_eq'].
rewrite H_eq H_eq' {H_eq H_eq' to from} in H8 H_ins H3 H2.
rewrite /= in IHrefl_trans_1n_trace1.
move: H_ins.
rewrite /update /=.
case name_eq_dec => H_dec //.
move => H_ins.
case: d H8 H_ins => /= adjacent0 H_eq H_adj.
rewrite H_eq in H_adj.
by apply NSetFacts.remove_1 in H_adj.
move: H_ins.
rewrite /update /=.
case name_eq_dec => H_dec'.
case: H_dec => H_dec; last by rewrite H_dec' in H_dec.
case: d H8 => /= adjacent0 H_eq.
move => H_ins.
rewrite H_eq {adjacent0 H_eq} in H_ins.
rewrite -H_dec' {to H_dec'} in H2 H3 H_ins.
apply NSetFacts.remove_3 in H_ins.
exact: IHrefl_trans_1n_trace1.
move => H_ins.
exact: IHrefl_trans_1n_trace1.
- find_apply_lem_hyp input_handlers_IOHandler; break_exists.
by io_handler_cases.
- move => n n' H_in_f H_ins.
rewrite /= in IHrefl_trans_1n_trace1.
have H_neq: h <> n.
move => H_eq.
case: H_in_f.
by left.
have H_in_f': ~ In n failed0.
move => H_in.
case: H_in_f.
by right.
have IH := IHrefl_trans_1n_trace1 _ _ H_in_f' H_ins.
case (name_eq_dec h n') => H_dec.
rewrite H_dec.
right.
split; first by left.
rewrite H_dec in H2.
have H_adj := Failure_in_adj_adjacent_to H _ H_in_f' H_ins.
rewrite collate_map2snd_not_in_related //.
* apply in_or_app.
by right; left.
* exact: all_names_nodes.
* exact: no_dup_nodes.
case: IH => IH.
left.
move => H_or.
by case: H_or => H_or.
move: IH => [H_in H_fail].
right.
split; first by right.
by rewrite collate_neq.
Qed.
Lemma Failure_le_one_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
count_occ Msg_eq_dec (onet.(onwPackets) n' n) Fail <= 1.
Proof.
move => onet failed tr H_st.
move => n n' H_in_f.
pose P_curr (d : Data) (l : list Msg) :=
count_occ Msg_eq_dec l Fail <= 1.
rewrite -/(P_curr (onet.(onwState) n) _).
apply: (P_inv_n_in H_st); rewrite /P_curr //= {P_curr onet tr H_st failed H_in_f}.
- by auto with arith.
- move => onet failed tr ms.
move => H_st H_in_f H_in_f' H_neq H_eq IH.
rewrite H_eq /= in IH.
by omega.
- move => onet failed tr H_st H_neq H_in_f H_in_f'.
move => H_adj IH.
have H_f := Failure_not_failed_no_fail H_st _ n H_in_f'.
have H_cnt : ~ count_occ Msg_eq_dec (onwPackets onet n' n) Fail > 0.
move => H_cnt.
by apply count_occ_In in H_cnt.
have H_cnt_eq: count_occ Msg_eq_dec (onwPackets onet n' n) Fail = 0 by omega.
rewrite count_occ_app /= H_cnt_eq.
by auto with arith.
Qed.
Lemma Failure_adjacent_to_in_adj :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
~ In n' failed ->
adjacent_to n' n ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st.
move => n n' H_f H_f'.
pose P_curr (d d' : Data) (l l' : list Msg) :=
adjacent_to n' n ->
NSet.In n' d.(adjacent).
rewrite -/(P_curr _ (onet.(onwState) n') (onet.(onwPackets) n n')
(onet.(onwPackets) n' n)).
apply: (P_dual_inv H_st); rewrite /P_curr //= {P_curr onet tr H_st failed H_f H_f'}.
- move => H_adj.
apply adjacent_to_node_adjacency.
apply related_filter_rel; first exact: all_names_nodes.
exact: adjacent_to_symmetric.
- move => onet failed tr from ms H_st H_eq H_in_f H_eq' H_neq H_adj H_adj_to.
rewrite H_eq in H_adj_to.
contradict H_adj_to.
exact: adjacent_to_irreflexive.
- move => onet failed tr from ms H_st H_in_f H_in_f' H_eq H_neq H_neq_f H_neq_f' IH H_adj.
concludes.
by apply NSetFacts.remove_2.
Qed.
Lemma Failure_in_queue_fail_then_adjacent :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
In Fail (onet.(onwPackets) n' n) ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st.
move => n n' H_in_f.
pose P_curr (d : Data) (l : list Msg) :=
In Fail l ->
NSet.In n' d.(adjacent).
rewrite -/(P_curr _ _).
apply: (P_inv_n_in H_st); rewrite /P_curr //= {P_curr onet tr H_st failed H_in_f}.
- move => onet failed tr ms H_st H_in_f H_in_f' H_neq H_eq IH H_in.
have H_cnt: count_occ Msg_eq_dec ms Fail > 0 by apply count_occ_In.
have H_cnt': count_occ Msg_eq_dec (onet.(onwPackets) n' n) Fail > 1 by rewrite H_eq /=; auto with arith.
have H_le := Failure_le_one_fail H_st _ n' H_in_f.
by omega.
- move => onet failed tr from ms H_st H_in_f H_neq H_neq'.
move => H_eq IH H_in.
apply NSetFacts.remove_2; first by move => H_eq'; rewrite H_eq' in H_neq'.
exact: IH.
- move => onet failed tr H_st H_neq H_in_f H_in_f' H_adj IH H_in.
exact (Failure_adjacent_to_in_adj H_st H_in_f H_in_f' H_adj).
Qed.
Lemma Failure_first_fail_in_adj :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
head (onet.(onwPackets) n' n) = Some Fail ->
NSet.In n' (onet.(onwState) n).(adjacent).
Proof.
move => onet failed tr H_st.
move => n n' H_in_f.
pose P_curr (d : Data) (l : list Msg) :=
hd_error l = Some Fail ->
NSet.In n' d.(adjacent).
rewrite -/(P_curr _ _).
apply: (P_inv_n_in H_st); rewrite /P_curr //= {P_curr onet tr H_st failed H_in_f}.
- move => onet failed tr ms H_st H_in_f H_in_f' H_neq H_eq IH H_hd.
have H_neq' := hd_error_some_nil H_hd.
case: ms H_eq H_hd H_neq' => //.
case => ms H_eq H_hd H_neq'.
have H_cnt: count_occ Msg_eq_dec (onwPackets onet n' n) Fail > 1 by rewrite H_eq /=; auto with arith.
have H_le := Failure_le_one_fail H_st _ n' H_in_f.
by omega.
- move => onet failed tr from ms H_st H_in_f H_neq H_neq' H_eq IH H_hd.
concludes.
apply NSetFacts.remove_2 => //.
move => H_eq'.
by rewrite H_eq' in H_neq'.
- move => onet failed tr H_st H_neq H_in_f H_in_f' H_adj IH H_hd.
by have H_a := Failure_adjacent_to_in_adj H_st H_in_f H_in_f' H_adj.
Qed.
Lemma Failure_adjacent_failed_incoming_fail :
forall onet failed tr,
step_ordered_failure_star step_ordered_failure_init (failed, onet) tr ->
forall n n',
~ In n failed ->
NSet.In n' (onet.(onwState) n).(adjacent) ->
In n' failed ->
In Fail (onet.(onwPackets) n' n).
Proof.
move => onet failed tr H_st n n' H_in_f H_adj H_in_f'.
have H_or := Failure_in_adj_or_incoming_fail H_st _ H_in_f H_adj.
case: H_or => H_or //.
by move: H_or => [H_in H_in'].
Qed.
Definition head_message_enables_label m src dst l :=
forall net failed,
~ In dst failed ->
head (net.(onwPackets) src dst) = Some m ->
enabled lb_step_ordered_failure l (failed, net).
Lemma Fail_enables_RecvFail :
forall src dst, head_message_enables_label Fail src dst (RecvFail dst src).
Proof.
move => src dst.
rewrite /head_message_enables_label.
move => net failed H_f H_eq.
case H_eq_p: (onwPackets net src dst) => [|m ms]; first by find_rewrite.
find_rewrite.
simpl in *.
find_injection.
rewrite /enabled.
case H_hnd: (@lb_net_handlers _ FailureRecorder_LabeledMultiParams dst src Fail (onwState net dst)) => [[[lb' out] d'] l].
have H_lb := H_hnd.
rewrite /lb_net_handlers /= in H_hnd.
by net_handler_cases => //;
exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d' |}), []; apply: LabeledStepOrderedFailure_deliver; eauto.
Qed.
Lemma Tree_lb_step_ordered_failure_RecvFail_enabled :
forall net net' net'' failed failed' failed'' tr tr' dst src l,
l <> RecvFail dst src ->
lb_step_ordered_failure (failed, net) l (failed', net') tr ->
lb_step_ordered_failure (failed, net) (RecvFail dst src) (failed'', net'') tr' ->
enabled lb_step_ordered_failure (RecvFail dst src) (failed', net').
Proof.
move => net net' net'' failed failed' failed'' tr tr' dst src l H_neq H_st H_st'.
destruct l => //.
- invcs H_st => //.
* by net_handler_cases.
* invcs H_st' => //.
have H_hd: head (onwPackets net' src dst) = Some Fail by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
exact: Fail_enables_RecvFail.
- invcs H_st' => //.
have H_eq: onwPackets net src dst = Fail :: ms by net_handler_cases => //; find_injection; find_rewrite.
have H_f: ~ In dst failed'' by net_handler_cases => //; find_injection; find_rewrite.
invcs H_st => //.
set net' := {| onwPackets := _ ; onwState := _ |}.
have H_hd': head (onwPackets net' src dst) = Some Fail.
rewrite /net' /=.
net_handler_cases => //=; rewrite /update2.
* break_if.
+ by break_and; subst; intuition.
+ by find_rewrite.
exact: Fail_enables_RecvFail.
Qed.
Lemma Failure_RecvFail_enabled_weak_until_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall src dst, l_enabled lb_step_ordered_failure (RecvFail dst src) (hd s) ->
weak_until (now (l_enabled lb_step_ordered_failure (RecvFail dst src)))
(now (occurred (RecvFail dst src)))
s.
Proof.
cofix c.
case => /=.
case; case => failed net l tr s H_exec src dst.
case (Label_eq_dec l (RecvFail dst src)) => H_eq H_en.
- find_rewrite.
exact: W0.
- apply: W_tl; first by [].
apply: c; first by find_apply_lem_hyp lb_step_execution_invar.
unfold l_enabled in *.
unfold enabled in H_en.
break_exists.
destruct s as [e s].
inversion H_exec; subst_max.
inversion H5; subst.
destruct e, evt_a.
destruct e', evt_a.
destruct x.
simpl in *.
by apply: Tree_lb_step_ordered_failure_RecvFail_enabled; eauto.
Qed.
Lemma Failure_RecvFail_eventually_occurred :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst, l_enabled lb_step_ordered_failure (RecvFail dst src) (hd s) ->
eventually (now (occurred (RecvFail dst src))) s.
Proof.
move => s H_exec H_fair src dst H_en.
have H_wu := Failure_RecvFail_enabled_weak_until_occurred H_exec H_en.
apply weak_until_until_or_always in H_wu.
case: H_wu; first exact: until_eventually.
move => H_al.
apply always_continuously in H_al.
apply H_fair in H_al => //.
destruct s as [x s].
by apply always_now in H_al.
Qed.
Lemma lb_step_ordered_failure_count_occ_Fail_neq_eq :
forall net net' failed failed' lb src dst k tr,
lb <> RecvFail dst src ->
count_occ msg_eq_dec (net.(onwPackets) src dst) Fail = k ->
lb_step_ordered_failure (failed, net) lb (failed', net') tr ->
count_occ msg_eq_dec (net'.(onwPackets) src dst) Fail = k.
Proof.
move => net net' failed failed' lb src dst k tr H_neq H_cnt H_step.
invcs H_step => //=.
net_handler_cases.
rewrite /collate /= /update2.
break_if => //.
break_and; subst.
by case: H_neq.
Qed.
Lemma lb_step_ordered_failure_count_occ_Fail_recv :
forall net net' failed failed' src dst k tr,
count_occ msg_eq_dec (net.(onwPackets) src dst) Fail = S k ->
lb_step_ordered_failure (failed, net) (RecvFail dst src) (failed', net') tr ->
count_occ msg_eq_dec (net'.(onwPackets) src dst) Fail = k.
Proof.
move => net net' failed failed' src dst k tr H_cnt H_step.
invcs H_step => //=.
net_handler_cases.
rewrite /= /update2.
break_if.
break_and; subst.
rewrite H3 /= in H_cnt.
by auto with arith.
find_injection.
by break_or_hyp.
Qed.
Lemma lb_step_ordered_failure_count_occ_Fail_le_monotonic :
forall net net' failed failed' lb src dst k tr,
count_occ msg_eq_dec (net.(onwPackets) src dst) Fail <= k ->
lb_step_ordered_failure (failed, net) lb (failed', net') tr ->
count_occ msg_eq_dec (net'.(onwPackets) src dst) Fail <= k.
Proof.
move => net net' failed failed' lb src dst k tr H_cnt H_step.
invcs H_step => //=.
net_handler_cases.
rewrite /update2 /=.
break_if => //.
break_and.
repeat find_rewrite.
rewrite H3 /= in H_cnt.
by auto with arith.
Qed.
Lemma lb_step_ordered_failure_not_in_failed :
forall net net' failed failed' lb tr h,
~ In h failed ->
lb_step_ordered_failure (failed, net) lb (failed', net') tr ->
~ In h failed'.
Proof.
move => net net' failed failed' lb tr h H_in_f H_step.
by invcs H_step.
Qed.
Lemma Failure_not_in_failed_always :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall h, ~ In h (fst (hd s).(evt_a)) ->
always (now (fun e => ~ In h (fst e.(evt_a)))) s.
Proof.
cofix c.
move => s H_exec.
inversion H_exec => /=.
move => h H_in_f.
apply: Always; first by [].
rewrite /=.
apply: c; first by [].
rewrite /=.
destruct e, e', evt_a, evt_a0.
simpl in *.
by eapply lb_step_ordered_failure_not_in_failed; eauto.
Qed.
Lemma Failure_lb_step_ordered_failure_fails_occ_monotonic :
forall s, lb_step_execution lb_step_ordered_failure s ->
forall src dst k,
count_occ Msg_eq_dec ((snd (hd s).(evt_a)).(onwPackets) src dst) Fail <= k ->
always (now (fun e => count_occ Msg_eq_dec ((snd e.(evt_a)).(onwPackets) src dst) Fail <= k)) s.
Proof.
cofix c.
move => s H_exec.
inversion H_exec => /=.
move => src dst k H_cnt.
apply: Always; first by [].
apply: c; first by [].
rewrite /=.
destruct e, e', evt_a, evt_a0.
simpl in *.
move: H.
exact: lb_step_ordered_failure_count_occ_Fail_le_monotonic.
Qed.
Lemma count_occ_fail_head :
forall e src dst k,
~ In dst (fst (evt_a e)) ->
count_occ Msg_eq_dec (onwPackets (snd (evt_a e)) src dst) Fail = S k ->
l_enabled lb_step_ordered_failure (RecvFail dst src) e.
Proof.
case => /= [[failed net] lb] tr src dst k H_in_f H_cnt.
rewrite /l_enabled /= /enabled.
case H_m: (onwPackets net src dst) => [|m ms]; first by rewrite H_m in H_cnt.
destruct m.
case H_hnd: (@lb_net_handlers _ FailureRecorder_LabeledMultiParams dst src Fail (onwState net dst)) => [[[lb' out] d] l].
have H_lb := H_hnd.
rewrite /lb_net_handlers /= in H_hnd.
net_handler_cases.
exists (failed, {| onwPackets := update2 Net.name_eq_dec (onwPackets net) src dst ms; onwState := update name_eq_dec (onwState net) dst d |}).
exists [].
by apply: LabeledStepOrderedFailure_deliver; eauto.
Qed.
Lemma Failure_eventually_fewer_Fail :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst k, ~ In dst (fst (hd s).(evt_a)) ->
count_occ Msg_eq_dec (onwPackets (snd (hd s).(evt_a)) src dst) Fail = S k ->
eventually (now (fun e => count_occ Msg_eq_dec (onwPackets (snd e.(evt_a)) src dst) Fail = k)) s.
Proof.
move => s H_exec H_fair src dst k H_in_f H_cnt.
have H_en := count_occ_fail_head _ _ _ H_in_f H_cnt.
apply Failure_RecvFail_eventually_occurred in H_en => //.
move: H_exec H_fair H_in_f H_cnt.
elim: H_en => {s}.
case; case => /= [[failed net] lb] tr.
case; case; case => /= failed' net' lb' tr' s.
rewrite /occurred /= => H_eq.
rewrite -H_eq {H_eq}.
move => H_exec H_fair H_in H_cnt.
apply: E_next.
apply: E0.
rewrite /=.
inversion H_exec; subst_max.
simpl in *.
by eapply lb_step_ordered_failure_count_occ_Fail_recv; eauto.
move => e s H_ev IH H_exec H_fair H_in H_cnt.
inversion H_exec; subst.
destruct e, e'.
destruct evt_a as [failed net].
destruct evt_a0 as [failed' net'].
simpl in *.
case (Label_eq_dec (RecvFail dst src) evt_l) => H_eq.
subst_max.
apply: E_next.
apply: E0.
rewrite /=.
by eapply lb_step_ordered_failure_count_occ_Fail_recv; eauto.
apply E_next.
apply IH.
- by [].
- by apply weak_local_fairness_invar in H_fair.
- by eapply lb_step_ordered_failure_not_in_failed; eauto.
- by eapply lb_step_ordered_failure_count_occ_Fail_neq_eq; eauto.
Qed.
Lemma Failure_lb_step_ordered_failure_eventually_le_0_fail :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst,
~ In dst (fst (hd s).(evt_a)) ->
eventually (now (fun e => count_occ Msg_eq_dec ((snd e.(evt_a)).(onwPackets) src dst) Fail = 0)) s.
Proof.
move => s H_exec H_fair src dst H_in_f.
have H_ex: exists k, count_occ Msg_eq_dec (onwPackets (snd (evt_a (hd s))) src dst) Fail = k.
case count_occ; first by exists 0.
move => k.
by exists (S k).
break_exists.
elim/(well_founded_ind lt_wf): x s H_exec H_fair H_in_f H.
case => [|k] IH s H_exec H_fair H_in_f H_cnt.
apply: E0.
by destruct s.
have H_k: k < S k by auto.
have IH' := IH _ H_k.
have H_ev := Failure_eventually_fewer_Fail H_exec H_fair src dst H_in_f H_cnt.
elim: H_ev H_exec H_fair H_in_f.
move => s0 H_now H_exec H_fair H_in_f.
apply: IH' => //.
rewrite /=.
by destruct s0.
move => e s0 H_ev H_ev' H_exec H_fair H_in_f.
apply: E_next.
apply: H_ev'.
- by apply lb_step_execution_invar in H_exec.
- by apply weak_local_fairness_invar in H_fair.
- inversion H_exec.
destruct e, e'.
destruct evt_a, evt_a0.
simpl in *.
by apply: lb_step_ordered_failure_not_in_failed; eauto.
Qed.
Lemma Failure_lb_step_ordered_failure_continuously_no_fail :
forall s, lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst,
~ In dst (fst (hd s).(evt_a)) ->
continuously (now (fun e => ~ In Fail ((snd e.(evt_a)).(onwPackets) src dst))) s.
Proof.
move => s H_exec H_fair src dst H_in_f.
have H_ev := Failure_lb_step_ordered_failure_eventually_le_0_fail H_exec H_fair src dst H_in_f.
move: H_exec H_fair {H_in_f}.
elim: H_ev.
- move => s0 H_n H_exec H_fair.
apply: E0.
inversion H_exec.
rewrite -H2 /now in H_n.
have H_al := Failure_lb_step_ordered_failure_fails_occ_monotonic H_exec src dst.
rewrite -H2 /= in H_al.
have H_le_n: count_occ Msg_eq_dec (onwPackets (snd (evt_a e)) src dst) Fail <= 0 by rewrite H_n.
have H_al' := H_al _ H_le_n.
move: H_al' {H_al}.
rewrite H2.
generalize s0.
apply: always_monotonic.
case => e2 s2.
rewrite /=.
move => H_occ.
apply (count_occ_not_In Msg_eq_dec _ Fail).
by auto with arith.
- move => e s0 H_ev IH H_exec H_fair.
apply: E_next.
apply: IH; first by apply lb_step_execution_invar in H_exec.
by apply weak_local_fairness_invar in H_fair.
Qed.
Lemma Failure_lb_step_ordered_failure_no_fails_step_star_ex :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall src dst,
~ In dst (fst (hd s).(evt_a)) ->
continuously (now (fun e =>
event_step_star step_ordered_failure step_ordered_failure_init e /\
~ In dst (fst e.(evt_a)) /\
~ In Fail ((snd e.(evt_a)).(onwPackets) src dst))) s.
Proof.
move => s H_star H_exec H_fair src dst H_in_f.
have H_al := step_ordered_failure_star_lb_step_execution H_star H_exec.
have H_al' := Failure_not_in_failed_always H_exec _ H_in_f.
apply always_continuously in H_al.
apply always_continuously in H_al'.
have H_cny := Failure_lb_step_ordered_failure_continuously_no_fail H_exec H_fair src _ H_in_f.
have H_both := continuously_and_tl H_al H_al'.
have H_both' := continuously_and_tl H_both H_cny.
move: H_both'.
apply continuously_monotonic.
case => /= e s0 H_and.
unfold now, and_tl in H_and.
by break_and.
Qed.
Lemma Failure_lb_step_ordered_failure_continuously_adj_not_failed :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
weak_local_fairness lb_step_ordered_failure label_silent s ->
forall n n',
~ In n (fst (hd s).(evt_a)) ->
continuously (now (fun e =>
NSet.In n' ((snd e.(evt_a)).(onwState) n).(adjacent) ->
~ In n' (fst e.(evt_a)) /\ adjacent_to n' n)) s.
Proof.
move => s H_star H_exec H_fair n n' H_in_f.
have H_cny := Failure_lb_step_ordered_failure_no_fails_step_star_ex H_star H_exec H_fair n' _ H_in_f.
move: H_cny.
apply continuously_monotonic.
case => /= e s0 H_and H_ins.
break_and.
destruct e, evt_a.
unfold event_step_star in *.
simpl in *.
break_exists.
have H_adj := Failure_in_adj_or_incoming_fail H _ H0 H_ins.
break_or_hyp; last by break_and.
split => //.
by eapply Failure_in_adj_adjacent_to; eauto.
Qed.
End FailureRecorderCorrect.
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:24:35 02/01/2017
// Design Name: mux4_1
// Module Name: /home/aaron/Git Repos/CSE311/lab2/mux4_1_tb.v
// Project Name: lab2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mux4_1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mux4_1_tb;
// Inputs
reg [3:0] input1;
reg [3:0] input2;
reg [3:0] input3;
reg [3:0] input4;
reg [1:0] select;
// Outputs
wire [3:0] selected_out;
// Instantiate the Unit Under Test (UUT)
mux4_1 uut (
.input1(input1),
.input2(input2),
.input3(input3),
.input4(input4),
.select(select),
.selected_out(selected_out)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
input3 = 0;
input4 = 0;
select = 0;
// Wait 100 ns for global reset to finish
#100;
// Set inputs to unique values, select input1
input1 = 4'b1000;
input2 = 4'b0100;
input3 = 4'b0010;
input4 = 4'b0001;
select = 2'b00;
// Select input2
#100;
select = 2'b01;
// Select input3
#100;
select = 2'b10;
// Select input4
#100;
select = 2'b11;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:09:46 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
(E,
bid_gets_fifo_load,
bvalid_cnt_inc,
bid_gets_fifo_load_d1_reg,
D,
axi_wdata_full_cmb114_out,
SR,
s_axi_aclk,
\bvalid_cnt_reg[2] ,
wr_addr_sm_cs,
\bvalid_cnt_reg[2]_0 ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
axi_awaddr_full,
bram_addr_ld_en,
bid_gets_fifo_load_d1,
s_axi_bready,
axi_bvalid_int_reg,
bvalid_cnt,
Q,
s_axi_awid,
\bvalid_cnt_reg[1] ,
aw_active,
s_axi_awready,
s_axi_awvalid,
curr_awlen_reg_1_or_2,
axi_awlen_pipe_1_or_2,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
last_data_ack_mod,
out,
axi_wr_burst,
s_axi_wvalid,
s_axi_wlast);
output [0:0]E;
output bid_gets_fifo_load;
output bvalid_cnt_inc;
output bid_gets_fifo_load_d1_reg;
output [11:0]D;
output axi_wdata_full_cmb114_out;
input [0:0]SR;
input s_axi_aclk;
input \bvalid_cnt_reg[2] ;
input wr_addr_sm_cs;
input \bvalid_cnt_reg[2]_0 ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input axi_awaddr_full;
input bram_addr_ld_en;
input bid_gets_fifo_load_d1;
input s_axi_bready;
input axi_bvalid_int_reg;
input [2:0]bvalid_cnt;
input [11:0]Q;
input [11:0]s_axi_awid;
input \bvalid_cnt_reg[1] ;
input aw_active;
input s_axi_awready;
input s_axi_awvalid;
input curr_awlen_reg_1_or_2;
input axi_awlen_pipe_1_or_2;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input last_data_ack_mod;
input [2:0]out;
input axi_wr_burst;
input s_axi_wvalid;
input s_axi_wlast;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire [11:0]D;
wire D_0;
wire Data_Exists_DFF_i_2_n_0;
wire Data_Exists_DFF_i_3_n_0;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire [11:0]Q;
wire S;
wire S0_out;
wire S1_out;
wire [0:0]SR;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire \axi_bid_int[11]_i_3_n_0 ;
wire axi_bvalid_int_i_4_n_0;
wire axi_bvalid_int_i_5_n_0;
wire axi_bvalid_int_i_6_n_0;
wire axi_bvalid_int_reg;
wire axi_wdata_full_cmb114_out;
wire axi_wr_burst;
wire [11:0]bid_fifo_ld;
wire bid_fifo_not_empty;
wire [11:0]bid_fifo_rd;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_3_n_0;
wire bid_gets_fifo_load_d1_reg;
wire bram_addr_ld_en;
wire [2:0]bvalid_cnt;
wire bvalid_cnt_inc;
wire \bvalid_cnt_reg[1] ;
wire \bvalid_cnt_reg[2] ;
wire \bvalid_cnt_reg[2]_0 ;
wire curr_awlen_reg_1_or_2;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire [11:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_wlast;
wire s_axi_wvalid;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire wr_addr_sm_cs;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h8AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(bram_addr_ld_en),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(CI));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D_0),
.Q(bid_fifo_not_empty),
.R(SR));
LUT4 #(
.INIT(16'hFE0A))
Data_Exists_DFF_i_1
(.I0(bram_addr_ld_en),
.I1(Data_Exists_DFF_i_2_n_0),
.I2(Data_Exists_DFF_i_3_n_0),
.I3(bid_fifo_not_empty),
.O(D_0));
LUT6 #(
.INIT(64'h000000000000FFFD))
Data_Exists_DFF_i_2
(.I0(bvalid_cnt_inc),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(bid_gets_fifo_load_d1_reg),
.I5(bid_gets_fifo_load_d1),
.O(Data_Exists_DFF_i_2_n_0));
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[11]),
.Q(bid_fifo_rd[11]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.O(bid_fifo_ld[11]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[10].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[1]),
.Q(bid_fifo_rd[1]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[10].SRL16E_I_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.O(bid_fifo_ld[1]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[11].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[0]),
.Q(bid_fifo_rd[0]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[11].SRL16E_I_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.O(bid_fifo_ld[0]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[10]),
.Q(bid_fifo_rd[10]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[1].SRL16E_I_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.O(bid_fifo_ld[10]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[2].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[9]),
.Q(bid_fifo_rd[9]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[2].SRL16E_I_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.O(bid_fifo_ld[9]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[3].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[8]),
.Q(bid_fifo_rd[8]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[3].SRL16E_I_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.O(bid_fifo_ld[8]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[4].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[7]),
.Q(bid_fifo_rd[7]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[4].SRL16E_I_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.O(bid_fifo_ld[7]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[5].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[6]),
.Q(bid_fifo_rd[6]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[5].SRL16E_I_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.O(bid_fifo_ld[6]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[6].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[5]),
.Q(bid_fifo_rd[5]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[6].SRL16E_I_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.O(bid_fifo_ld[5]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[7].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[4]),
.Q(bid_fifo_rd[4]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[7].SRL16E_I_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.O(bid_fifo_ld[4]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[8].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[3]),
.Q(bid_fifo_rd[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[8].SRL16E_I_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.O(bid_fifo_ld[3]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[9].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[2]),
.Q(bid_fifo_rd[2]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[9].SRL16E_I_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.O(bid_fifo_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[0]_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[10]_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[10]),
.O(D[10]));
LUT2 #(
.INIT(4'hE))
\axi_bid_int[11]_i_1
(.I0(bid_gets_fifo_load),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[11]_i_2
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[11]),
.O(D[11]));
LUT6 #(
.INIT(64'hA888AAAAA8888888))
\axi_bid_int[11]_i_3
(.I0(bid_fifo_not_empty),
.I1(bid_gets_fifo_load_d1),
.I2(s_axi_bready),
.I3(axi_bvalid_int_reg),
.I4(bid_gets_fifo_load_d1_i_3_n_0),
.I5(bvalid_cnt_inc),
.O(\axi_bid_int[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[1]_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[2]_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[3]_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[4]_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[5]_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[6]_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[7]_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[8]_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[9]_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[9]),
.O(D[9]));
LUT6 #(
.INIT(64'h000055FD00000000))
axi_bvalid_int_i_2
(.I0(out[2]),
.I1(axi_wdata_full_cmb114_out),
.I2(axi_bvalid_int_i_4_n_0),
.I3(axi_wr_burst),
.I4(out[1]),
.I5(axi_bvalid_int_i_5_n_0),
.O(bvalid_cnt_inc));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT5 #(
.INIT(32'hFE000000))
axi_bvalid_int_i_3
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(axi_bvalid_int_reg),
.I4(s_axi_bready),
.O(bid_gets_fifo_load_d1_reg));
LUT6 #(
.INIT(64'h1F11000000000000))
axi_bvalid_int_i_4
(.I0(axi_bvalid_int_i_6_n_0),
.I1(\bvalid_cnt_reg[2] ),
.I2(wr_addr_sm_cs),
.I3(\bvalid_cnt_reg[2]_0 ),
.I4(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I5(axi_awaddr_full),
.O(axi_bvalid_int_i_4_n_0));
LUT5 #(
.INIT(32'h74446444))
axi_bvalid_int_i_5
(.I0(out[0]),
.I1(out[2]),
.I2(s_axi_wvalid),
.I3(s_axi_wlast),
.I4(axi_wdata_full_cmb114_out),
.O(axi_bvalid_int_i_5_n_0));
LUT5 #(
.INIT(32'hFEFFFFFF))
axi_bvalid_int_i_6
(.I0(curr_awlen_reg_1_or_2),
.I1(axi_awlen_pipe_1_or_2),
.I2(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I3(axi_awaddr_full),
.I4(last_data_ack_mod),
.O(axi_bvalid_int_i_6_n_0));
LUT6 #(
.INIT(64'h7F7F7F007F007F00))
axi_wready_int_mod_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(aw_active),
.I4(s_axi_awready),
.I5(s_axi_awvalid),
.O(axi_wdata_full_cmb114_out));
LUT6 #(
.INIT(64'h00000800AA00AA00))
bid_gets_fifo_load_d1_i_1
(.I0(bram_addr_ld_en),
.I1(bid_gets_fifo_load_d1_reg),
.I2(bid_fifo_not_empty),
.I3(bvalid_cnt_inc),
.I4(\bvalid_cnt_reg[1] ),
.I5(bid_gets_fifo_load_d1_i_3_n_0),
.O(bid_gets_fifo_load));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hFE))
bid_gets_fifo_load_d1_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(bid_gets_fifo_load_d1_i_3_n_0));
endmodule
(* C_BRAM_ADDR_WIDTH = "14" *) (* C_BRAM_INST_MODE = "EXTERNAL" *) (* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *) (* C_ECC_TYPE = "0" *) (* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *) (* C_MEMORY_DEPTH = "16384" *) (* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *) (* C_S_AXI_ADDR_WIDTH = "16" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [11:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [15:2]\^bram_addr_a ;
wire [15:2]\^bram_addr_b ;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[15:2] = \^bram_addr_a [15:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[15:2] = \^bram_addr_b [15:2];
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = s_axi_aclk;
assign bram_rst_b = bram_rst_a;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.bram_addr_a(\^bram_addr_a ),
.bram_addr_b(\^bram_addr_b ),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[15:2]),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[15:2]),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi \GEN_AXI4.I_FULL_AXI
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire I_WR_CHNL_n_36;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl I_RD_CHNL
(.\GEN_AWREADY.axi_aresetn_d2_reg (I_WR_CHNL_n_36),
.Q(bram_addr_b),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl I_WR_CHNL
(.\GEN_AW_DUAL.aw_active_reg_0 (I_WR_CHNL_n_36),
.SR(bram_rst_a),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
(bram_rst_a,
s_axi_rdata,
s_axi_rlast,
s_axi_rvalid,
bram_en_b,
Q,
s_axi_arready,
s_axi_rid,
s_axi_araddr,
s_axi_aclk,
\GEN_AWREADY.axi_aresetn_d2_reg ,
s_axi_rready,
s_axi_aresetn,
s_axi_arlen,
axi_aresetn_d2,
s_axi_arvalid,
axi_aresetn_re_reg,
s_axi_arid,
s_axi_arburst,
bram_rddata_b);
output bram_rst_a;
output [31:0]s_axi_rdata;
output s_axi_rlast;
output s_axi_rvalid;
output bram_en_b;
output [13:0]Q;
output s_axi_arready;
output [11:0]s_axi_rid;
input [13:0]s_axi_araddr;
input s_axi_aclk;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input s_axi_rready;
input s_axi_aresetn;
input [7:0]s_axi_arlen;
input axi_aresetn_d2;
input s_axi_arvalid;
input axi_aresetn_re_reg;
input [11:0]s_axi_arid;
input [1:0]s_axi_arburst;
input [31:0]bram_rddata_b;
wire \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ;
wire \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ;
wire \/i__n_0 ;
wire \FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ;
wire \GEN_ARREADY.axi_arready_int_i_1_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_2_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_1_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_2_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_4_n_0 ;
wire \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_full_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[10]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_2_n_0 ;
wire \GEN_RID.axi_rid_temp[1]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[2]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[3]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[4]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[5]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[6]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[7]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[8]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp_full_i_1_n_0 ;
wire I_WRAP_BRST_n_1;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_26;
wire I_WRAP_BRST_n_27;
wire I_WRAP_BRST_n_28;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [13:0]Q;
wire act_rd_burst;
wire act_rd_burst_i_1_n_0;
wire act_rd_burst_i_3_n_0;
wire act_rd_burst_i_4_n_0;
wire act_rd_burst_set;
wire act_rd_burst_two;
wire act_rd_burst_two_i_1_n_0;
wire ar_active;
wire araddr_pipe_ld43_out;
wire axi_araddr_full;
wire [1:0]axi_arburst_pipe;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [11:0]axi_arid_pipe;
wire [7:0]axi_arlen_pipe;
wire axi_arlen_pipe_1_or_2;
wire axi_arready_int;
wire [1:1]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_arsize_pipe_max_i_1_n_0;
wire axi_b2b_brst;
wire axi_b2b_brst_i_1_n_0;
wire axi_b2b_brst_i_3_n_0;
wire axi_early_arready_int;
wire axi_rd_burst;
wire axi_rd_burst_i_1_n_0;
wire axi_rd_burst_i_2_n_0;
wire axi_rd_burst_i_3_n_0;
wire axi_rd_burst_two;
wire axi_rd_burst_two_i_1_n_0;
wire axi_rd_burst_two_reg_n_0;
wire [11:0]axi_rid_temp;
wire [11:0]axi_rid_temp2;
wire [11:0]axi_rid_temp20_in;
wire axi_rid_temp2_full;
wire axi_rid_temp_full;
wire axi_rid_temp_full_d1;
wire axi_rlast_int_i_1_n_0;
wire axi_rlast_set;
wire axi_rvalid_clr_ok;
wire axi_rvalid_clr_ok_i_1_n_0;
wire axi_rvalid_clr_ok_i_2_n_0;
wire axi_rvalid_clr_ok_i_3_n_0;
wire axi_rvalid_int_i_1_n_0;
wire axi_rvalid_set;
wire axi_rvalid_set_cmb;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_en_b;
wire bram_en_int_i_10_n_0;
wire bram_en_int_i_11_n_0;
wire bram_en_int_i_1_n_0;
wire bram_en_int_i_2_n_0;
wire bram_en_int_i_3_n_0;
wire bram_en_int_i_4_n_0;
wire bram_en_int_i_6_n_0;
wire bram_en_int_i_7_n_0;
wire bram_en_int_i_9_n_0;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [7:0]brst_cnt;
wire \brst_cnt[0]_i_1_n_0 ;
wire \brst_cnt[1]_i_1_n_0 ;
wire \brst_cnt[2]_i_1_n_0 ;
wire \brst_cnt[3]_i_1_n_0 ;
wire \brst_cnt[4]_i_1_n_0 ;
wire \brst_cnt[4]_i_2_n_0 ;
wire \brst_cnt[5]_i_1_n_0 ;
wire \brst_cnt[6]_i_1_n_0 ;
wire \brst_cnt[6]_i_2_n_0 ;
wire \brst_cnt[7]_i_1_n_0 ;
wire \brst_cnt[7]_i_2_n_0 ;
wire \brst_cnt[7]_i_3_n_0 ;
wire \brst_cnt[7]_i_4_n_0 ;
wire brst_cnt_max;
wire brst_cnt_max_d1;
wire brst_one;
wire brst_one0;
wire brst_one_i_1_n_0;
wire brst_zero;
wire brst_zero_i_1_n_0;
wire brst_zero_i_2_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire disable_b2b_brst_cmb;
wire disable_b2b_brst_i_2_n_0;
wire disable_b2b_brst_i_3_n_0;
wire disable_b2b_brst_i_4_n_0;
wire end_brst_rd;
wire end_brst_rd_clr;
wire end_brst_rd_clr_i_1_n_0;
wire end_brst_rd_i_1_n_0;
wire last_bram_addr;
wire last_bram_addr0;
wire last_bram_addr_i_2_n_0;
wire last_bram_addr_i_3_n_0;
wire last_bram_addr_i_4_n_0;
wire last_bram_addr_i_5_n_0;
wire last_bram_addr_i_6_n_0;
wire last_bram_addr_i_7_n_0;
wire last_bram_addr_i_8_n_0;
wire last_bram_addr_i_9_n_0;
wire no_ar_ack;
wire no_ar_ack_i_1_n_0;
wire p_0_in13_in;
wire p_13_out;
wire p_26_out;
wire p_48_out;
wire p_4_out;
wire p_9_out;
wire pend_rd_op;
wire pend_rd_op_i_1_n_0;
wire pend_rd_op_i_2_n_0;
wire pend_rd_op_i_3_n_0;
wire pend_rd_op_i_4_n_0;
wire pend_rd_op_i_5_n_0;
wire pend_rd_op_i_6_n_0;
wire pend_rd_op_i_7_n_0;
wire pend_rd_op_i_8_n_0;
wire pend_rd_op_i_9_n_0;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire [3:0]rd_data_sm_cs;
wire \rd_data_sm_cs[0]_i_1_n_0 ;
wire \rd_data_sm_cs[0]_i_2_n_0 ;
wire \rd_data_sm_cs[0]_i_3_n_0 ;
wire \rd_data_sm_cs[0]_i_4_n_0 ;
wire \rd_data_sm_cs[1]_i_1_n_0 ;
wire \rd_data_sm_cs[1]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_1_n_0 ;
wire \rd_data_sm_cs[2]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_4_n_0 ;
wire \rd_data_sm_cs[2]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_2_n_0 ;
wire \rd_data_sm_cs[3]_i_3_n_0 ;
wire \rd_data_sm_cs[3]_i_4_n_0 ;
wire \rd_data_sm_cs[3]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_6_n_0 ;
wire \rd_data_sm_cs[3]_i_7_n_0 ;
wire rd_data_sm_ns;
wire [31:0]rd_skid_buf;
wire rd_skid_buf_ld;
wire rd_skid_buf_ld_cmb;
wire rd_skid_buf_ld_reg;
wire rddata_mux_sel;
wire rddata_mux_sel_cmb;
wire rddata_mux_sel_i_1_n_0;
wire rddata_mux_sel_i_3_n_0;
(* RTL_KEEP = "yes" *) wire [2:0]rlast_sm_cs;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
LUT6 #(
.INIT(64'h0011001300130013))
\/FSM_sequential_rlast_sm_cs[0]_i_2
(.I0(axi_rd_burst),
.I1(rlast_sm_cs[1]),
.I2(act_rd_burst_two),
.I3(axi_rd_burst_two_reg_n_0),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h003F007F003F0055))
\/FSM_sequential_rlast_sm_cs[1]_i_2
(.I0(axi_rd_burst),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rlast_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_two),
.O(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF000F111F000E000))
\/i_
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rlast_sm_cs[0]),
.I5(last_bram_addr),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h00008080000F8080))
\/i___0
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[1]),
.I4(rlast_sm_cs[2]),
.I5(s_axi_rlast),
.O(axi_rlast_set));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[0]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[0]),
.O(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[1]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[1]),
.O(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A4FFFF00A40000))
\FSM_sequential_rlast_sm_cs[2]_i_1
(.I0(rlast_sm_cs[1]),
.I1(p_0_in13_in),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[2]),
.I4(\/i__n_0 ),
.I5(rlast_sm_cs[2]),
.O(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\FSM_sequential_rlast_sm_cs[2]_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst),
.O(p_0_in13_in));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ),
.Q(rlast_sm_cs[0]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ),
.Q(rlast_sm_cs[1]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ),
.Q(rlast_sm_cs[2]),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAEEE))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(p_9_out),
.I1(axi_arready_int),
.I2(s_axi_arvalid),
.I3(axi_araddr_full),
.I4(araddr_pipe_ld43_out),
.O(\GEN_ARREADY.axi_arready_int_i_1_n_0 ));
LUT4 #(
.INIT(16'hBAAA))
\GEN_ARREADY.axi_arready_int_i_2
(.I0(axi_aresetn_re_reg),
.I1(axi_early_arready_int),
.I2(axi_araddr_full),
.I3(bram_addr_ld_en),
.O(p_9_out));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_ARREADY.axi_arready_int_i_1_n_0 ),
.Q(axi_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h0000000000000200))
\GEN_ARREADY.axi_early_arready_int_i_1
(.I0(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ),
.I1(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ),
.I2(rd_data_sm_cs[3]),
.I3(brst_one),
.I4(axi_arready_int),
.I5(I_WRAP_BRST_n_26),
.O(p_48_out));
LUT6 #(
.INIT(64'h00CC304400000044))
\GEN_ARREADY.axi_early_arready_int_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h7))
\GEN_ARREADY.axi_early_arready_int_i_3
(.I0(axi_araddr_full),
.I1(s_axi_arvalid),
.O(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_early_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_48_out),
.Q(axi_early_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCDCDCDDDCCCCCCCC))
\GEN_AR_DUAL.ar_active_i_1
(.I0(\GEN_AR_DUAL.ar_active_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(\GEN_AR_DUAL.ar_active_i_3_n_0 ),
.I3(end_brst_rd),
.I4(brst_zero),
.I5(ar_active),
.O(\GEN_AR_DUAL.ar_active_i_1_n_0 ));
LUT6 #(
.INIT(64'h808880808088A280))
\GEN_AR_DUAL.ar_active_i_2
(.I0(pend_rd_op_i_6_n_0),
.I1(rd_data_sm_cs[1]),
.I2(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(axi_rd_burst),
.O(\GEN_AR_DUAL.ar_active_i_2_n_0 ));
LUT6 #(
.INIT(64'h0010000000000000))
\GEN_AR_DUAL.ar_active_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\GEN_AR_DUAL.ar_active_i_3_n_0 ));
LUT6 #(
.INIT(64'h8A88000000000000))
\GEN_AR_DUAL.ar_active_i_4
(.I0(I_WRAP_BRST_n_27),
.I1(brst_zero),
.I2(axi_b2b_brst),
.I3(end_brst_rd),
.I4(rd_adv_buf67_out),
.I5(rd_data_sm_cs[0]),
.O(\GEN_AR_DUAL.ar_active_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_DUAL.ar_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.ar_active_i_1_n_0 ),
.Q(ar_active),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
LUT6 #(
.INIT(64'h10001000F0F01000))
\GEN_AR_DUAL.rd_addr_sm_cs_i_1
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I4(last_bram_addr),
.I5(I_WRAP_BRST_n_26),
.O(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ));
FDRE \GEN_AR_DUAL.rd_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ),
.Q(rd_addr_sm_cs),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[8]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[9]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[10]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[11]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[12]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[13]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[0]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[1]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[2]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[3]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[4]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[5]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[6]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[7]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.R(1'b0));
LUT6 #(
.INIT(64'h00C08888CCCC8888))
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1
(.I0(araddr_pipe_ld43_out),
.I1(s_axi_aresetn),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I4(axi_araddr_full),
.I5(bram_addr_ld_en),
.O(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ),
.Q(axi_araddr_full),
.R(1'b0));
LUT4 #(
.INIT(16'h03AA))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.I1(s_axi_arburst[0]),
.I2(s_axi_arburst[1]),
.I3(araddr_pipe_ld43_out),
.O(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[0]),
.Q(axi_arburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[1]),
.Q(axi_arburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[0]),
.Q(axi_arid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[10]),
.Q(axi_arid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[11]),
.Q(axi_arid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[1]),
.Q(axi_arid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[2]),
.Q(axi_arid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[3]),
.Q(axi_arid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[4]),
.Q(axi_arid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[5]),
.Q(axi_arid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[6]),
.Q(axi_arid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[7]),
.Q(axi_arid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[8]),
.Q(axi_arid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[9]),
.Q(axi_arid_pipe[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h220022002A002200))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1
(.I0(axi_aresetn_d2),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I2(rd_addr_sm_cs),
.I3(s_axi_arvalid),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I5(axi_araddr_full),
.O(araddr_pipe_ld43_out));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'hB))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2
(.I0(I_WRAP_BRST_n_26),
.I1(last_bram_addr),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'hFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3
(.I0(no_ar_ack),
.I1(pend_rd_op),
.I2(ar_active),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1
(.I0(s_axi_arlen[7]),
.I1(s_axi_arlen[1]),
.I2(s_axi_arlen[3]),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ),
.O(p_13_out));
LUT4 #(
.INIT(16'hFFFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2
(.I0(s_axi_arlen[5]),
.I1(s_axi_arlen[4]),
.I2(s_axi_arlen[2]),
.I3(s_axi_arlen[6]),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(p_13_out),
.Q(axi_arlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[0]),
.Q(axi_arlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[1]),
.Q(axi_arlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[2]),
.Q(axi_arlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[3]),
.Q(axi_arlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[4]),
.Q(axi_arlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[5]),
.Q(axi_arlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[6]),
.Q(axi_arlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[7]),
.Q(axi_arlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(1'b1),
.Q(axi_arsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000BAAA0000))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1
(.I0(brst_cnt_max),
.I1(pend_rd_op),
.I2(ar_active),
.I3(brst_zero),
.I4(s_axi_aresetn),
.I5(bram_addr_ld_en),
.O(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ),
.Q(brst_cnt_max),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(Q[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4
(.I0(Q[6]),
.I1(Q[4]),
.I2(I_WRAP_BRST_n_23),
.I3(Q[5]),
.I4(Q[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_13),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_12),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_11),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_10),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_9),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_8),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_21),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_20),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_19),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_18),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_17),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_16),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_15),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_14),
.Q(Q[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1
(.I0(rd_skid_buf[0]),
.I1(bram_rddata_b[0]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1
(.I0(rd_skid_buf[10]),
.I1(bram_rddata_b[10]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ),
.Q(s_axi_rdata[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1
(.I0(rd_skid_buf[11]),
.I1(bram_rddata_b[11]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ),
.Q(s_axi_rdata[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1
(.I0(rd_skid_buf[12]),
.I1(bram_rddata_b[12]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ),
.Q(s_axi_rdata[12]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1
(.I0(rd_skid_buf[13]),
.I1(bram_rddata_b[13]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ),
.Q(s_axi_rdata[13]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1
(.I0(rd_skid_buf[14]),
.I1(bram_rddata_b[14]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ),
.Q(s_axi_rdata[14]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1
(.I0(rd_skid_buf[15]),
.I1(bram_rddata_b[15]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ),
.Q(s_axi_rdata[15]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1
(.I0(rd_skid_buf[16]),
.I1(bram_rddata_b[16]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ),
.Q(s_axi_rdata[16]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1
(.I0(rd_skid_buf[17]),
.I1(bram_rddata_b[17]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ),
.Q(s_axi_rdata[17]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1
(.I0(rd_skid_buf[18]),
.I1(bram_rddata_b[18]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ),
.Q(s_axi_rdata[18]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1
(.I0(rd_skid_buf[19]),
.I1(bram_rddata_b[19]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ),
.Q(s_axi_rdata[19]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1
(.I0(rd_skid_buf[1]),
.I1(bram_rddata_b[1]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1
(.I0(rd_skid_buf[20]),
.I1(bram_rddata_b[20]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ),
.Q(s_axi_rdata[20]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1
(.I0(rd_skid_buf[21]),
.I1(bram_rddata_b[21]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ),
.Q(s_axi_rdata[21]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1
(.I0(rd_skid_buf[22]),
.I1(bram_rddata_b[22]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ),
.Q(s_axi_rdata[22]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1
(.I0(rd_skid_buf[23]),
.I1(bram_rddata_b[23]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ),
.Q(s_axi_rdata[23]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1
(.I0(rd_skid_buf[24]),
.I1(bram_rddata_b[24]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ),
.Q(s_axi_rdata[24]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1
(.I0(rd_skid_buf[25]),
.I1(bram_rddata_b[25]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ),
.Q(s_axi_rdata[25]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1
(.I0(rd_skid_buf[26]),
.I1(bram_rddata_b[26]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ),
.Q(s_axi_rdata[26]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1
(.I0(rd_skid_buf[27]),
.I1(bram_rddata_b[27]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ),
.Q(s_axi_rdata[27]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1
(.I0(rd_skid_buf[28]),
.I1(bram_rddata_b[28]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ),
.Q(s_axi_rdata[28]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1
(.I0(rd_skid_buf[29]),
.I1(bram_rddata_b[29]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ),
.Q(s_axi_rdata[29]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1
(.I0(rd_skid_buf[2]),
.I1(bram_rddata_b[2]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1
(.I0(rd_skid_buf[30]),
.I1(bram_rddata_b[30]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ),
.Q(s_axi_rdata[30]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1414545410000404))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2
(.I0(rd_skid_buf[31]),
.I1(bram_rddata_b[31]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.Q(s_axi_rdata[31]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1
(.I0(rd_skid_buf[3]),
.I1(bram_rddata_b[3]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ),
.Q(s_axi_rdata[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1
(.I0(rd_skid_buf[4]),
.I1(bram_rddata_b[4]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ),
.Q(s_axi_rdata[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1
(.I0(rd_skid_buf[5]),
.I1(bram_rddata_b[5]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ),
.Q(s_axi_rdata[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1
(.I0(rd_skid_buf[6]),
.I1(bram_rddata_b[6]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ),
.Q(s_axi_rdata[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1
(.I0(rd_skid_buf[7]),
.I1(bram_rddata_b[7]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ),
.Q(s_axi_rdata[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1
(.I0(rd_skid_buf[8]),
.I1(bram_rddata_b[8]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ),
.Q(s_axi_rdata[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1
(.I0(rd_skid_buf[9]),
.I1(bram_rddata_b[9]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ),
.Q(s_axi_rdata[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAEAA))
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1
(.I0(rd_skid_buf_ld_reg),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[3]),
.O(rd_skid_buf_ld));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[0]),
.Q(rd_skid_buf[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[10]),
.Q(rd_skid_buf[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[11]),
.Q(rd_skid_buf[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[12]),
.Q(rd_skid_buf[12]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[13]),
.Q(rd_skid_buf[13]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[14]),
.Q(rd_skid_buf[14]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[15]),
.Q(rd_skid_buf[15]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[16]),
.Q(rd_skid_buf[16]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[17]),
.Q(rd_skid_buf[17]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[18]),
.Q(rd_skid_buf[18]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[19]),
.Q(rd_skid_buf[19]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[1]),
.Q(rd_skid_buf[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[20]),
.Q(rd_skid_buf[20]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[21]),
.Q(rd_skid_buf[21]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[22]),
.Q(rd_skid_buf[22]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[23]),
.Q(rd_skid_buf[23]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[24]),
.Q(rd_skid_buf[24]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[25]),
.Q(rd_skid_buf[25]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[26]),
.Q(rd_skid_buf[26]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[27]),
.Q(rd_skid_buf[27]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[28]),
.Q(rd_skid_buf[28]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[29]),
.Q(rd_skid_buf[29]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[2]),
.Q(rd_skid_buf[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[30]),
.Q(rd_skid_buf[30]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[31]),
.Q(rd_skid_buf[31]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[3]),
.Q(rd_skid_buf[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[4]),
.Q(rd_skid_buf[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[5]),
.Q(rd_skid_buf[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[6]),
.Q(rd_skid_buf[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[7]),
.Q(rd_skid_buf[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[8]),
.Q(rd_skid_buf[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[9]),
.Q(rd_skid_buf[9]),
.R(bram_rst_a));
LUT4 #(
.INIT(16'h08FF))
\GEN_RID.axi_rid_int[11]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(axi_b2b_brst),
.I3(s_axi_aresetn),
.O(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEAAA))
\GEN_RID.axi_rid_int[11]_i_2
(.I0(axi_rvalid_set),
.I1(s_axi_rready),
.I2(s_axi_rlast),
.I3(axi_b2b_brst),
.O(p_4_out));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[0]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[0]),
.Q(s_axi_rid[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[10]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[10]),
.Q(s_axi_rid[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[11]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[11]),
.Q(s_axi_rid[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[1]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[1]),
.Q(s_axi_rid[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[2]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[2]),
.Q(s_axi_rid[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[3]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[3]),
.Q(s_axi_rid[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[4]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[4]),
.Q(s_axi_rid[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[5]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[5]),
.Q(s_axi_rid[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[6]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[6]),
.Q(s_axi_rid[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[7]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[7]),
.Q(s_axi_rid[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[8]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[8]),
.Q(s_axi_rid[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[9]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[9]),
.Q(s_axi_rid[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.O(axi_rid_temp20_in[0]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.O(axi_rid_temp20_in[10]));
LUT2 #(
.INIT(4'h8))
\GEN_RID.axi_rid_temp2[11]_i_1
(.I0(axi_rid_temp_full),
.I1(bram_addr_ld_en),
.O(p_26_out));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.O(axi_rid_temp20_in[11]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.O(axi_rid_temp20_in[1]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.O(axi_rid_temp20_in[2]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.O(axi_rid_temp20_in[3]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.O(axi_rid_temp20_in[4]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.O(axi_rid_temp20_in[5]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.O(axi_rid_temp20_in[6]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.O(axi_rid_temp20_in[7]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.O(axi_rid_temp20_in[8]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.O(axi_rid_temp20_in[9]));
LUT6 #(
.INIT(64'h08080000C8C800C0))
\GEN_RID.axi_rid_temp2_full_i_1
(.I0(bram_addr_ld_en),
.I1(s_axi_aresetn),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full_d1),
.I4(axi_rid_temp_full),
.I5(p_4_out),
.O(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ),
.Q(axi_rid_temp2_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[0]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[0]),
.Q(axi_rid_temp2[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[10]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[10]),
.Q(axi_rid_temp2[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[11]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[11]),
.Q(axi_rid_temp2[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[1]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[1]),
.Q(axi_rid_temp2[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[2]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[2]),
.Q(axi_rid_temp2[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[3]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[3]),
.Q(axi_rid_temp2[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[4]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[4]),
.Q(axi_rid_temp2[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[5]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[5]),
.Q(axi_rid_temp2[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[6]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[6]),
.Q(axi_rid_temp2[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[7]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[7]),
.Q(axi_rid_temp2[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[8]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[8]),
.Q(axi_rid_temp2[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[9]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[9]),
.Q(axi_rid_temp2[9]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[0]),
.O(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[10]),
.O(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hA0FFA0E0))
\GEN_RID.axi_rid_temp[11]_i_1
(.I0(p_4_out),
.I1(axi_rid_temp_full_d1),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.O(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[11]),
.O(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[1]),
.O(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[2]),
.O(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[3]),
.O(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[4]),
.O(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[5]),
.O(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[6]),
.O(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[7]),
.O(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[8]),
.O(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[9]),
.O(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rid_temp_full),
.Q(axi_rid_temp_full_d1),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0F0F0E000F0A0A0))
\GEN_RID.axi_rid_temp_full_i_1
(.I0(bram_addr_ld_en),
.I1(axi_rid_temp_full_d1),
.I2(s_axi_aresetn),
.I3(p_4_out),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2_full),
.O(\GEN_RID.axi_rid_temp_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp_full_i_1_n_0 ),
.Q(axi_rid_temp_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ),
.Q(axi_rid_temp[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ),
.Q(axi_rid_temp[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ),
.Q(axi_rid_temp[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ),
.Q(axi_rid_temp[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ),
.Q(axi_rid_temp[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ),
.Q(axi_rid_temp[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ),
.Q(axi_rid_temp[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ),
.Q(axi_rid_temp[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ),
.Q(axi_rid_temp[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ),
.Q(axi_rid_temp[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ),
.Q(axi_rid_temp[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ),
.Q(axi_rid_temp[9]),
.R(bram_rst_a));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 I_WRAP_BRST
(.D({I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16,I_WRAP_BRST_n_17,I_WRAP_BRST_n_18,I_WRAP_BRST_n_19,I_WRAP_BRST_n_20,I_WRAP_BRST_n_21}),
.E({bram_addr_ld_en_mod,I_WRAP_BRST_n_6}),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg (\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_7),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 (I_WRAP_BRST_n_25),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 (Q[9:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (I_WRAP_BRST_n_23),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ),
.Q(axi_arlen_pipe[3:0]),
.SR(bram_rst_a),
.ar_active(ar_active),
.axi_araddr_full(axi_araddr_full),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_arlen_pipe_1_or_2(axi_arlen_pipe_1_or_2),
.axi_arsize_pipe(axi_arsize_pipe),
.axi_arsize_pipe_max(axi_arsize_pipe_max),
.axi_b2b_brst(axi_b2b_brst),
.axi_b2b_brst_reg(I_WRAP_BRST_n_27),
.axi_rd_burst(axi_rd_burst),
.axi_rd_burst_two_reg(axi_rd_burst_two_reg_n_0),
.axi_rvalid_int_reg(s_axi_rvalid),
.bram_addr_ld_en(bram_addr_ld_en),
.brst_zero(brst_zero),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.disable_b2b_brst(disable_b2b_brst),
.end_brst_rd(end_brst_rd),
.last_bram_addr(last_bram_addr),
.no_ar_ack(no_ar_ack),
.pend_rd_op(pend_rd_op),
.rd_addr_sm_cs(rd_addr_sm_cs),
.rd_adv_buf67_out(rd_adv_buf67_out),
.\rd_data_sm_cs_reg[1] (I_WRAP_BRST_n_24),
.\rd_data_sm_cs_reg[3] (I_WRAP_BRST_n_28),
.\rd_data_sm_cs_reg[3]_0 (rd_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arlen(s_axi_arlen[3:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_26),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_1),
.\wrap_burst_total_reg[0]_1 (I_WRAP_BRST_n_2),
.\wrap_burst_total_reg[0]_2 (I_WRAP_BRST_n_3),
.\wrap_burst_total_reg[0]_3 (I_WRAP_BRST_n_4));
LUT6 #(
.INIT(64'h000000002EEE22E2))
act_rd_burst_i_1
(.I0(act_rd_burst),
.I1(act_rd_burst_set),
.I2(bram_addr_ld_en),
.I3(axi_rd_burst_two),
.I4(axi_rd_burst),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'hA8A8AAA8A8A8A8A8))
act_rd_burst_i_2
(.I0(pend_rd_op_i_6_n_0),
.I1(act_rd_burst_i_4_n_0),
.I2(axi_b2b_brst_i_3_n_0),
.I3(\rd_data_sm_cs[2]_i_4_n_0 ),
.I4(last_bram_addr_i_7_n_0),
.I5(bram_addr_ld_en),
.O(act_rd_burst_set));
LUT6 #(
.INIT(64'h04000010FFFFFFFF))
act_rd_burst_i_3
(.I0(\rd_data_sm_cs[3]_i_6_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(s_axi_aresetn),
.O(act_rd_burst_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h4440))
act_rd_burst_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.O(act_rd_burst_i_4_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_i_1_n_0),
.Q(act_rd_burst),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000E2EEE222))
act_rd_burst_two_i_1
(.I0(act_rd_burst_two),
.I1(act_rd_burst_set),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_two_i_1_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_two_i_1_n_0),
.Q(act_rd_burst_two),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
axi_arsize_pipe_max_i_1
(.I0(araddr_pipe_ld43_out),
.I1(axi_arsize_pipe_max),
.O(axi_arsize_pipe_max_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_arsize_pipe_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_arsize_pipe_max_i_1_n_0),
.Q(axi_arsize_pipe_max),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCC0CCC55CC0CCCCC))
axi_b2b_brst_i_1
(.I0(I_WRAP_BRST_n_27),
.I1(axi_b2b_brst),
.I2(disable_b2b_brst_i_2_n_0),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(axi_b2b_brst_i_3_n_0),
.O(axi_b2b_brst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000088880080))
axi_b2b_brst_i_3
(.I0(\rd_data_sm_cs[0]_i_3_n_0 ),
.I1(rd_adv_buf67_out),
.I2(end_brst_rd),
.I3(axi_b2b_brst),
.I4(brst_zero),
.I5(I_WRAP_BRST_n_27),
.O(axi_b2b_brst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_b2b_brst_i_1_n_0),
.Q(axi_b2b_brst),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h303000A0))
axi_rd_burst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000004))
axi_rd_burst_i_2
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(axi_rd_burst_i_3_n_0),
.I2(I_WRAP_BRST_n_3),
.I3(\brst_cnt[7]_i_3_n_0 ),
.I4(I_WRAP_BRST_n_2),
.I5(I_WRAP_BRST_n_1),
.O(axi_rd_burst_i_2_n_0));
LUT5 #(
.INIT(32'h00053305))
axi_rd_burst_i_3
(.I0(s_axi_arlen[5]),
.I1(axi_arlen_pipe[5]),
.I2(s_axi_arlen[4]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[4]),
.O(axi_rd_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_i_1_n_0),
.Q(axi_rd_burst),
.R(1'b0));
LUT5 #(
.INIT(32'hC0C000A0))
axi_rd_burst_two_i_1
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst_two),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_two_i_1_n_0));
LUT4 #(
.INIT(16'hA808))
axi_rd_burst_two_i_2
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(axi_rd_burst_two));
FDRE #(
.INIT(1'b0))
axi_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_two_i_1_n_0),
.Q(axi_rd_burst_two_reg_n_0),
.R(1'b0));
LUT4 #(
.INIT(16'h88A8))
axi_rlast_int_i_1
(.I0(s_axi_aresetn),
.I1(axi_rlast_set),
.I2(s_axi_rlast),
.I3(s_axi_rready),
.O(axi_rlast_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rlast_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rlast_int_i_1_n_0),
.Q(s_axi_rlast),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFFEEEA))
axi_rvalid_clr_ok_i_1
(.I0(axi_rvalid_clr_ok),
.I1(last_bram_addr),
.I2(disable_b2b_brst),
.I3(disable_b2b_brst_cmb),
.I4(axi_rvalid_clr_ok_i_2_n_0),
.I5(axi_rvalid_clr_ok_i_3_n_0),
.O(axi_rvalid_clr_ok_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hAAAABAAA))
axi_rvalid_clr_ok_i_2
(.I0(bram_addr_ld_en),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(axi_rvalid_clr_ok_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h4F))
axi_rvalid_clr_ok_i_3
(.I0(I_WRAP_BRST_n_26),
.I1(bram_addr_ld_en),
.I2(s_axi_aresetn),
.O(axi_rvalid_clr_ok_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_clr_ok_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_clr_ok_i_1_n_0),
.Q(axi_rvalid_clr_ok),
.R(1'b0));
LUT6 #(
.INIT(64'h00E0E0E0E0E0E0E0))
axi_rvalid_int_i_1
(.I0(s_axi_rvalid),
.I1(axi_rvalid_set),
.I2(s_axi_aresetn),
.I3(axi_rvalid_clr_ok),
.I4(s_axi_rlast),
.I5(s_axi_rready),
.O(axi_rvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_int_i_1_n_0),
.Q(s_axi_rvalid),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h0100))
axi_rvalid_set_i_1
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.O(axi_rvalid_set_cmb));
FDRE #(
.INIT(1'b0))
axi_rvalid_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_set_cmb),
.Q(axi_rvalid_set),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hEEEEFFFEEEEE000E))
bram_en_int_i_1
(.I0(bram_en_int_i_2_n_0),
.I1(bram_en_int_i_3_n_0),
.I2(bram_en_int_i_4_n_0),
.I3(I_WRAP_BRST_n_28),
.I4(bram_en_int_i_6_n_0),
.I5(bram_en_b),
.O(bram_en_int_i_1_n_0));
LUT6 #(
.INIT(64'hFFFF777FFFFFFFFF))
bram_en_int_i_10
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(act_rd_burst),
.I3(act_rd_burst_two),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_10_n_0));
LUT6 #(
.INIT(64'hD0D000F0D0D0F0F0))
bram_en_int_i_11
(.I0(\rd_data_sm_cs[3]_i_7_n_0 ),
.I1(I_WRAP_BRST_n_27),
.I2(rd_data_sm_cs[1]),
.I3(brst_one),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(bram_en_int_i_11_n_0));
LUT6 #(
.INIT(64'h00000000FDF50000))
bram_en_int_i_2
(.I0(rd_data_sm_cs[2]),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[1]),
.I5(bram_en_int_i_7_n_0),
.O(bram_en_int_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAEEAFAAAAAAEE))
bram_en_int_i_3
(.I0(I_WRAP_BRST_n_25),
.I1(bram_addr_ld_en),
.I2(p_0_in13_in),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_3_n_0));
LUT6 #(
.INIT(64'h000F007F0000007F))
bram_en_int_i_4
(.I0(pend_rd_op),
.I1(rd_adv_buf67_out),
.I2(\rd_data_sm_cs[0]_i_3_n_0 ),
.I3(bram_en_int_i_9_n_0),
.I4(bram_addr_ld_en),
.I5(bram_en_int_i_10_n_0),
.O(bram_en_int_i_4_n_0));
LUT6 #(
.INIT(64'h1010111111111110))
bram_en_int_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(bram_en_int_i_11_n_0),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_6_n_0));
LUT6 #(
.INIT(64'h5500050544444444))
bram_en_int_i_7
(.I0(rd_data_sm_cs[2]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(\rd_data_sm_cs[3]_i_7_n_0 ),
.I4(rd_adv_buf67_out),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_7_n_0));
LUT6 #(
.INIT(64'h1111111111111000))
bram_en_int_i_9
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(brst_zero),
.I5(end_brst_rd),
.O(bram_en_int_i_9_n_0));
FDRE #(
.INIT(1'b0))
bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_int_i_1_n_0),
.Q(bram_en_b),
.R(bram_rst_a));
LUT5 #(
.INIT(32'hD1DDD111))
\brst_cnt[0]_i_1
(.I0(brst_cnt[0]),
.I1(bram_addr_ld_en),
.I2(axi_arlen_pipe[0]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[0]),
.O(\brst_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[1]_i_1
(.I0(axi_arlen_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\brst_cnt[2]_i_1
(.I0(I_WRAP_BRST_n_1),
.I1(bram_addr_ld_en),
.I2(brst_cnt[2]),
.I3(brst_cnt[1]),
.I4(brst_cnt[0]),
.O(\brst_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\brst_cnt[3]_i_1
(.I0(I_WRAP_BRST_n_2),
.I1(bram_addr_ld_en),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[4]_i_1
(.I0(axi_arlen_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[4]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[4]),
.I5(\brst_cnt[4]_i_2_n_0 ),
.O(\brst_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0001))
\brst_cnt[4]_i_2
(.I0(brst_cnt[2]),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.I3(brst_cnt[3]),
.O(\brst_cnt[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[5]_i_1
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hB88BB8B8))
\brst_cnt[6]_i_1
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[6]),
.I3(brst_cnt[5]),
.I4(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[6]_i_2
(.I0(axi_arlen_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[6]),
.O(\brst_cnt[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\brst_cnt[7]_i_1
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_7),
.O(\brst_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB8B8B8B8))
\brst_cnt[7]_i_2
(.I0(\brst_cnt[7]_i_3_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[7]),
.I3(brst_cnt[6]),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[7]_i_3
(.I0(axi_arlen_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[7]),
.O(\brst_cnt[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00000001))
\brst_cnt[7]_i_4
(.I0(brst_cnt[3]),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.O(\brst_cnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
brst_cnt_max_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_cnt_max),
.Q(brst_cnt_max_d1),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[0]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[0]_i_1_n_0 ),
.Q(brst_cnt[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[1]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[1]_i_1_n_0 ),
.Q(brst_cnt[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[2]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[2]_i_1_n_0 ),
.Q(brst_cnt[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[3]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[3]_i_1_n_0 ),
.Q(brst_cnt[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[4]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[4]_i_1_n_0 ),
.Q(brst_cnt[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[5]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[5]_i_1_n_0 ),
.Q(brst_cnt[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[6]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[6]_i_1_n_0 ),
.Q(brst_cnt[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[7]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[7]_i_2_n_0 ),
.Q(brst_cnt[7]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h00000000E0EE0000))
brst_one_i_1
(.I0(brst_one),
.I1(brst_one0),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(s_axi_aresetn),
.I5(last_bram_addr_i_6_n_0),
.O(brst_one_i_1_n_0));
LUT6 #(
.INIT(64'h80FF808080808080))
brst_one_i_2
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_4),
.I2(axi_rd_burst_i_2_n_0),
.I3(brst_cnt[0]),
.I4(brst_cnt[1]),
.I5(last_bram_addr_i_8_n_0),
.O(brst_one0));
FDRE #(
.INIT(1'b0))
brst_one_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_one_i_1_n_0),
.Q(brst_one),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h00E0))
brst_zero_i_1
(.I0(brst_zero),
.I1(last_bram_addr_i_6_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero_i_2_n_0),
.O(brst_zero_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h8A80AAAA))
brst_zero_i_2
(.I0(bram_addr_ld_en),
.I1(axi_arlen_pipe[0]),
.I2(axi_araddr_full),
.I3(s_axi_arlen[0]),
.I4(axi_rd_burst_i_2_n_0),
.O(brst_zero_i_2_n_0));
FDRE #(
.INIT(1'b0))
brst_zero_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_zero_i_1_n_0),
.Q(brst_zero),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_1
(.I0(s_axi_arburst[0]),
.I1(axi_arburst_pipe[0]),
.I2(s_axi_arburst[1]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[1]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_fixed_burst),
.Q(curr_fixed_burst_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_1
(.I0(s_axi_arburst[1]),
.I1(axi_arburst_pipe[1]),
.I2(s_axi_arburst[0]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_wrap_burst),
.Q(curr_wrap_burst_reg),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF000D0000))
disable_b2b_brst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst_i_2_n_0),
.I5(disable_b2b_brst_i_3_n_0),
.O(disable_b2b_brst_cmb));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h2))
disable_b2b_brst_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.O(disable_b2b_brst_i_2_n_0));
LUT6 #(
.INIT(64'hF6EF0000F6EFF6EF))
disable_b2b_brst_i_3
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[0]),
.I4(disable_b2b_brst),
.I5(disable_b2b_brst_i_4_n_0),
.O(disable_b2b_brst_i_3_n_0));
LUT6 #(
.INIT(64'hDFDFDFDFDFDFDFFF))
disable_b2b_brst_i_4
(.I0(pend_rd_op_i_6_n_0),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(brst_zero),
.I4(end_brst_rd),
.I5(brst_one),
.O(disable_b2b_brst_i_4_n_0));
FDRE #(
.INIT(1'b0))
disable_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(disable_b2b_brst_cmb),
.Q(disable_b2b_brst),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFEFEFEFF10100000))
end_brst_rd_clr_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[0]),
.I5(end_brst_rd_clr),
.O(end_brst_rd_clr_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_clr_i_1_n_0),
.Q(end_brst_rd_clr),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h0020F020))
end_brst_rd_i_1
(.I0(brst_cnt_max),
.I1(brst_cnt_max_d1),
.I2(s_axi_aresetn),
.I3(end_brst_rd),
.I4(end_brst_rd_clr),
.O(end_brst_rd_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_i_1_n_0),
.Q(end_brst_rd),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF1F110000))
last_bram_addr_i_1
(.I0(last_bram_addr_i_2_n_0),
.I1(rd_data_sm_cs[2]),
.I2(last_bram_addr_i_3_n_0),
.I3(last_bram_addr_i_4_n_0),
.I4(last_bram_addr_i_5_n_0),
.I5(last_bram_addr_i_6_n_0),
.O(last_bram_addr0));
LUT6 #(
.INIT(64'hEF00EFFFEFFFEFFF))
last_bram_addr_i_2
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_adv_buf67_out),
.I3(rd_data_sm_cs[3]),
.I4(bram_addr_ld_en),
.I5(last_bram_addr_i_7_n_0),
.O(last_bram_addr_i_2_n_0));
LUT6 #(
.INIT(64'hDDDDDDDDFFFCFFFF))
last_bram_addr_i_3
(.I0(last_bram_addr_i_7_n_0),
.I1(I_WRAP_BRST_n_28),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(last_bram_addr_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h8880))
last_bram_addr_i_4
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(bram_addr_ld_en),
.I3(pend_rd_op),
.O(last_bram_addr_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h81))
last_bram_addr_i_5
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.O(last_bram_addr_i_5_n_0));
LUT3 #(
.INIT(8'h08))
last_bram_addr_i_6
(.I0(last_bram_addr_i_8_n_0),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.O(last_bram_addr_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h02A2))
last_bram_addr_i_7
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(last_bram_addr_i_7_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
last_bram_addr_i_8
(.I0(I_WRAP_BRST_n_7),
.I1(last_bram_addr_i_9_n_0),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.I5(brst_cnt[7]),
.O(last_bram_addr_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hE))
last_bram_addr_i_9
(.I0(brst_cnt[6]),
.I1(brst_cnt[5]),
.O(last_bram_addr_i_9_n_0));
FDRE #(
.INIT(1'b0))
last_bram_addr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(last_bram_addr0),
.Q(last_bram_addr),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAAAAA88C8AAAA))
no_ar_ack_i_1
(.I0(no_ar_ack),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[0]),
.I5(I_WRAP_BRST_n_28),
.O(no_ar_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
no_ar_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(no_ar_ack_i_1_n_0),
.Q(no_ar_ack),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hEFAAEFEF20AA2020))
pend_rd_op_i_1
(.I0(pend_rd_op_i_2_n_0),
.I1(pend_rd_op_i_3_n_0),
.I2(pend_rd_op_i_4_n_0),
.I3(pend_rd_op_i_5_n_0),
.I4(pend_rd_op_i_6_n_0),
.I5(pend_rd_op),
.O(pend_rd_op_i_1_n_0));
LUT6 #(
.INIT(64'h0FFCC8C80CCCC8C8))
pend_rd_op_i_2
(.I0(p_0_in13_in),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(pend_rd_op_i_7_n_0),
.O(pend_rd_op_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF00030005))
pend_rd_op_i_3
(.I0(pend_rd_op_i_8_n_0),
.I1(pend_rd_op_i_7_n_0),
.I2(bram_addr_ld_en),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(I_WRAP_BRST_n_28),
.O(pend_rd_op_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFFF00EA))
pend_rd_op_i_4
(.I0(bram_addr_ld_en),
.I1(end_brst_rd),
.I2(ar_active),
.I3(rd_data_sm_cs[0]),
.I4(pend_rd_op_i_9_n_0),
.O(pend_rd_op_i_4_n_0));
LUT6 #(
.INIT(64'h0303070733F3FFFF))
pend_rd_op_i_5
(.I0(p_0_in13_in),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(s_axi_rlast),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(pend_rd_op_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h1))
pend_rd_op_i_6
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.O(pend_rd_op_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_7
(.I0(ar_active),
.I1(end_brst_rd),
.O(pend_rd_op_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_8
(.I0(pend_rd_op),
.I1(s_axi_rlast),
.O(pend_rd_op_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h8000FFFF))
pend_rd_op_i_9
(.I0(pend_rd_op),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(pend_rd_op_i_9_n_0));
FDRE #(
.INIT(1'b0))
pend_rd_op_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(pend_rd_op_i_1_n_0),
.Q(pend_rd_op),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF54005555))
\rd_data_sm_cs[0]_i_1
(.I0(\rd_data_sm_cs[0]_i_2_n_0 ),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[0]_i_3_n_0 ),
.I5(\rd_data_sm_cs[0]_i_4_n_0 ),
.O(\rd_data_sm_cs[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEAAAAAAFEAAFEAA))
\rd_data_sm_cs[0]_i_2
(.I0(I_WRAP_BRST_n_28),
.I1(act_rd_burst_two),
.I2(act_rd_burst),
.I3(disable_b2b_brst_i_2_n_0),
.I4(bram_addr_ld_en),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\rd_data_sm_cs[0]_i_3
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000300BF0003008F))
\rd_data_sm_cs[0]_i_4
(.I0(rd_adv_buf67_out),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(p_0_in13_in),
.O(\rd_data_sm_cs[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\rd_data_sm_cs[1]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(I_WRAP_BRST_n_28),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(I_WRAP_BRST_n_24),
.I5(\rd_data_sm_cs[1]_i_3_n_0 ),
.O(\rd_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC0CCCCCC88888888))
\rd_data_sm_cs[1]_i_3
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(I_WRAP_BRST_n_27),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAABAAABAEAFAAAB))
\rd_data_sm_cs[2]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[3]),
.I3(\rd_data_sm_cs[2]_i_3_n_0 ),
.I4(\rd_data_sm_cs[2]_i_4_n_0 ),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(\rd_data_sm_cs[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000DF00000))
\rd_data_sm_cs[2]_i_2
(.I0(bram_addr_ld_en),
.I1(\rd_data_sm_cs[3]_i_6_n_0 ),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(rd_data_sm_cs[3]),
.O(\rd_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00C0FFFF33F3BBBB))
\rd_data_sm_cs[2]_i_3
(.I0(axi_rd_burst),
.I1(rd_data_sm_cs[0]),
.I2(rd_adv_buf67_out),
.I3(I_WRAP_BRST_n_27),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(\rd_data_sm_cs[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_5
(.I0(brst_zero),
.I1(end_brst_rd),
.O(\rd_data_sm_cs[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h8F80FF8F8F80F080))
\rd_data_sm_cs[3]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\rd_data_sm_cs[3]_i_3_n_0 ),
.I3(bram_addr_ld_en),
.I4(\rd_data_sm_cs[3]_i_4_n_0 ),
.I5(\rd_data_sm_cs[3]_i_5_n_0 ),
.O(rd_data_sm_ns));
LUT6 #(
.INIT(64'h0000004050005040))
\rd_data_sm_cs[3]_i_2
(.I0(I_WRAP_BRST_n_28),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(\rd_data_sm_cs[3]_i_6_n_0 ),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h4052))
\rd_data_sm_cs[3]_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0035))
\rd_data_sm_cs[3]_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF5EFFFF))
\rd_data_sm_cs[3]_i_5
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(\rd_data_sm_cs[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h1FFF))
\rd_data_sm_cs[3]_i_6
(.I0(act_rd_burst_two),
.I1(act_rd_burst),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\rd_data_sm_cs[3]_i_6_n_0 ));
LUT3 #(
.INIT(8'hBA))
\rd_data_sm_cs[3]_i_7
(.I0(brst_zero),
.I1(axi_b2b_brst),
.I2(end_brst_rd),
.O(\rd_data_sm_cs[3]_i_7_n_0 ));
FDRE \rd_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[0]_i_1_n_0 ),
.Q(rd_data_sm_cs[0]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[1]_i_1_n_0 ),
.Q(rd_data_sm_cs[1]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[2]_i_1_n_0 ),
.Q(rd_data_sm_cs[2]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[3]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[3]_i_2_n_0 ),
.Q(rd_data_sm_cs[3]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h1110011001100110))
rd_skid_buf_ld_reg_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(s_axi_rready),
.I5(s_axi_rvalid),
.O(rd_skid_buf_ld_cmb));
FDRE #(
.INIT(1'b0))
rd_skid_buf_ld_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_skid_buf_ld_cmb),
.Q(rd_skid_buf_ld_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFE02))
rddata_mux_sel_i_1
(.I0(rddata_mux_sel_cmb),
.I1(rd_data_sm_cs[3]),
.I2(rddata_mux_sel_i_3_n_0),
.I3(rddata_mux_sel),
.O(rddata_mux_sel_i_1_n_0));
LUT6 #(
.INIT(64'hF0F010F00F00F000))
rddata_mux_sel_i_2
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.I5(rd_adv_buf67_out),
.O(rddata_mux_sel_cmb));
LUT6 #(
.INIT(64'hF700070FF70F070F))
rddata_mux_sel_i_3
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(rddata_mux_sel_i_3_n_0));
FDRE #(
.INIT(1'b0))
rddata_mux_sel_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rddata_mux_sel_i_1_n_0),
.Q(rddata_mux_sel),
.R(bram_rst_a));
LUT4 #(
.INIT(16'hEAAA))
s_axi_arready_INST_0
(.I0(axi_arready_int),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(axi_early_arready_int),
.O(s_axi_arready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
(axi_aresetn_d2,
axi_aresetn_re_reg,
bram_en_a,
bram_wrdata_a,
s_axi_bvalid,
\GEN_AW_DUAL.aw_active_reg_0 ,
s_axi_wready,
s_axi_awready,
bram_addr_a,
s_axi_bid,
bram_we_a,
SR,
s_axi_aclk,
s_axi_awaddr,
s_axi_aresetn,
s_axi_wdata,
s_axi_wvalid,
s_axi_wlast,
s_axi_bready,
s_axi_awburst,
s_axi_awid,
s_axi_awvalid,
s_axi_awlen,
s_axi_wstrb);
output axi_aresetn_d2;
output axi_aresetn_re_reg;
output bram_en_a;
output [31:0]bram_wrdata_a;
output s_axi_bvalid;
output \GEN_AW_DUAL.aw_active_reg_0 ;
output s_axi_wready;
output s_axi_awready;
output [13:0]bram_addr_a;
output [11:0]s_axi_bid;
output [3:0]bram_we_a;
input [0:0]SR;
input s_axi_aclk;
input [13:0]s_axi_awaddr;
input s_axi_aresetn;
input [31:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_bready;
input [1:0]s_axi_awburst;
input [11:0]s_axi_awid;
input s_axi_awvalid;
input [7:0]s_axi_awlen;
input [3:0]s_axi_wstrb;
wire BID_FIFO_n_0;
wire BID_FIFO_n_10;
wire BID_FIFO_n_11;
wire BID_FIFO_n_12;
wire BID_FIFO_n_13;
wire BID_FIFO_n_14;
wire BID_FIFO_n_15;
wire BID_FIFO_n_3;
wire BID_FIFO_n_4;
wire BID_FIFO_n_5;
wire BID_FIFO_n_6;
wire BID_FIFO_n_7;
wire BID_FIFO_n_8;
wire BID_FIFO_n_9;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_1_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_2_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_3_n_0 ;
wire \GEN_AW_DUAL.aw_active_i_2_n_0 ;
wire \GEN_AW_DUAL.aw_active_reg_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ;
wire \I_RD_CHNL/axi_aresetn_d1 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [0:0]SR;
wire aw_active;
wire axi_aresetn_d2;
wire axi_aresetn_re;
wire axi_aresetn_re_reg;
wire axi_awaddr_full;
wire [1:0]axi_awburst_pipe;
wire [11:0]axi_awid_pipe;
wire [7:0]axi_awlen_pipe;
wire axi_awlen_pipe_1_or_2;
wire [1:1]axi_awsize_pipe;
wire axi_bvalid_int_i_1_n_0;
wire axi_wdata_full_cmb;
wire axi_wdata_full_cmb114_out;
wire axi_wdata_full_reg;
wire axi_wr_burst;
wire axi_wr_burst_cmb;
wire axi_wr_burst_cmb0;
wire axi_wr_burst_i_1_n_0;
wire axi_wr_burst_i_3_n_0;
wire axi_wready_int_mod_i_1_n_0;
wire axi_wready_int_mod_i_3_n_0;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_2_n_0;
wire [13:0]bram_addr_a;
wire bram_addr_inc;
wire [13:10]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire bram_en_a;
wire bram_en_cmb;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire [2:0]bvalid_cnt;
wire \bvalid_cnt[0]_i_1_n_0 ;
wire \bvalid_cnt[1]_i_1_n_0 ;
wire \bvalid_cnt[2]_i_1_n_0 ;
wire bvalid_cnt_inc;
wire bvalid_cnt_inc11_out;
wire clr_bram_we;
wire clr_bram_we_cmb;
wire curr_awlen_reg_1_or_2;
wire curr_awlen_reg_1_or_20;
wire curr_awlen_reg_1_or_2_i_2_n_0;
wire curr_awlen_reg_1_or_2_i_3_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire delay_aw_active_clr;
wire last_data_ack_mod;
wire p_18_out;
wire p_9_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire wr_addr_sm_cs;
(* RTL_KEEP = "yes" *) wire [2:0]wr_data_sm_cs;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO BID_FIFO
(.D({BID_FIFO_n_4,BID_FIFO_n_5,BID_FIFO_n_6,BID_FIFO_n_7,BID_FIFO_n_8,BID_FIFO_n_9,BID_FIFO_n_10,BID_FIFO_n_11,BID_FIFO_n_12,BID_FIFO_n_13,BID_FIFO_n_14,BID_FIFO_n_15}),
.E(BID_FIFO_n_0),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.Q(axi_awid_pipe),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_bvalid_int_reg(s_axi_bvalid),
.axi_wdata_full_cmb114_out(axi_wdata_full_cmb114_out),
.axi_wr_burst(axi_wr_burst),
.bid_gets_fifo_load(bid_gets_fifo_load),
.bid_gets_fifo_load_d1(bid_gets_fifo_load_d1),
.bid_gets_fifo_load_d1_reg(BID_FIFO_n_3),
.bram_addr_ld_en(bram_addr_ld_en),
.bvalid_cnt(bvalid_cnt),
.bvalid_cnt_inc(bvalid_cnt_inc),
.\bvalid_cnt_reg[1] (bid_gets_fifo_load_d1_i_2_n_0),
.\bvalid_cnt_reg[2] (I_WRAP_BRST_n_20),
.\bvalid_cnt_reg[2]_0 (I_WRAP_BRST_n_19),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_addr_sm_cs(wr_addr_sm_cs));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[0]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h05051F1A))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(axi_wr_burst_cmb0),
.I2(wr_data_sm_cs[0]),
.I3(axi_wdata_full_cmb114_out),
.I4(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'h5515))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3
(.I0(I_WRAP_BRST_n_21),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.O(axi_wr_burst_cmb0));
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[1]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000554000555540))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(s_axi_wlast),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[2]),
.I5(axi_wr_burst),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h44010001))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2
(.I0(wr_data_sm_cs[2]),
.I1(wr_data_sm_cs[1]),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h7774777774744444))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[0]),
.I5(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ),
.Q(wr_data_sm_cs[0]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ),
.Q(wr_data_sm_cs[1]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ),
.Q(wr_data_sm_cs[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(\I_RD_CHNL/axi_aresetn_d1 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\I_RD_CHNL/axi_aresetn_d1 ),
.Q(axi_aresetn_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\GEN_AWREADY.axi_aresetn_re_reg_i_1
(.I0(s_axi_aresetn),
.I1(\I_RD_CHNL/axi_aresetn_d1 ),
.O(axi_aresetn_re));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_re_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_aresetn_re),
.Q(axi_aresetn_re_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFBFBFFFFFAA00))
\GEN_AWREADY.axi_awready_int_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(bram_addr_ld_en),
.I4(axi_aresetn_re_reg),
.I5(s_axi_awready),
.O(\GEN_AWREADY.axi_awready_int_i_1_n_0 ));
LUT6 #(
.INIT(64'h5444444400000000))
\GEN_AWREADY.axi_awready_int_i_2
(.I0(\GEN_AWREADY.axi_awready_int_i_3_n_0 ),
.I1(aw_active),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(s_axi_awvalid),
.O(\GEN_AWREADY.axi_awready_int_i_2_n_0 ));
LUT6 #(
.INIT(64'hAABABABABABABABA))
\GEN_AWREADY.axi_awready_int_i_3
(.I0(wr_addr_sm_cs),
.I1(I_WRAP_BRST_n_21),
.I2(last_data_ack_mod),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\GEN_AWREADY.axi_awready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_awready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AWREADY.axi_awready_int_i_1_n_0 ),
.Q(s_axi_awready),
.R(SR));
LUT1 #(
.INIT(2'h1))
\GEN_AW_DUAL.aw_active_i_1
(.I0(axi_aresetn_d2),
.O(\GEN_AW_DUAL.aw_active_reg_0 ));
LUT6 #(
.INIT(64'hFFFFF7FFFFFF0000))
\GEN_AW_DUAL.aw_active_i_2
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(wr_data_sm_cs[2]),
.I3(delay_aw_active_clr),
.I4(bram_addr_ld_en),
.I5(aw_active),
.O(\GEN_AW_DUAL.aw_active_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.aw_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.aw_active_i_2_n_0 ),
.Q(aw_active),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'h80))
\GEN_AW_DUAL.last_data_ack_mod_i_1
(.I0(s_axi_wready),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(p_18_out));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.last_data_ack_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_18_out),
.Q(last_data_ack_mod),
.R(SR));
LUT6 #(
.INIT(64'h0010001000100000))
\GEN_AW_DUAL.wr_addr_sm_cs_i_1
(.I0(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ),
.I1(wr_addr_sm_cs),
.I2(s_axi_awvalid),
.I3(axi_awaddr_full),
.I4(I_WRAP_BRST_n_20),
.I5(aw_active),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_AW_DUAL.wr_addr_sm_cs_i_2
(.I0(I_WRAP_BRST_n_20),
.I1(last_data_ack_mod),
.I2(axi_awaddr_full),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(axi_awlen_pipe_1_or_2),
.I5(curr_awlen_reg_1_or_2),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ));
FDRE \GEN_AW_DUAL.wr_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ),
.Q(wr_addr_sm_cs),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[8]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[9]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[10]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[11]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[12]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[13]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[0]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[1]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[2]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[3]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[4]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[5]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[6]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[7]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.R(1'b0));
LUT5 #(
.INIT(32'h4000EA00))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(s_axi_aresetn),
.I4(bram_addr_ld_en),
.O(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ),
.Q(axi_awaddr_full),
.R(1'b0));
LUT6 #(
.INIT(64'hBF00BF00BF00FF40))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(s_axi_awburst[0]),
.I5(s_axi_awburst[1]),
.O(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[0]),
.Q(axi_awburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[1]),
.Q(axi_awburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[0]),
.Q(axi_awid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[10]),
.Q(axi_awid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[11]),
.Q(axi_awid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[1]),
.Q(axi_awid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[2]),
.Q(axi_awid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[3]),
.Q(axi_awid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[4]),
.Q(axi_awid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[5]),
.Q(axi_awid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[6]),
.Q(axi_awid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[7]),
.Q(axi_awid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[8]),
.Q(axi_awid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[9]),
.Q(axi_awid_pipe[9]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(s_axi_awlen[3]),
.I2(s_axi_awlen[2]),
.I3(s_axi_awlen[1]),
.O(p_9_out));
LUT4 #(
.INIT(16'h0001))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2
(.I0(s_axi_awlen[4]),
.I1(s_axi_awlen[6]),
.I2(s_axi_awlen[7]),
.I3(s_axi_awlen[5]),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(p_9_out),
.Q(axi_awlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[0]),
.Q(axi_awlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[1]),
.Q(axi_awlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[2]),
.Q(axi_awlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[3]),
.Q(axi_awlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[4]),
.Q(axi_awlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[5]),
.Q(axi_awlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[6]),
.Q(axi_awlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[7]),
.Q(axi_awlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(1'b1),
.Q(axi_awsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0
(.I0(bram_addr_a[4]),
.I1(bram_addr_a[1]),
.I2(bram_addr_a[0]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[3]),
.I5(bram_addr_a[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0
(.I0(bram_addr_a[6]),
.I1(bram_addr_a[4]),
.I2(I_WRAP_BRST_n_17),
.I3(bram_addr_a[5]),
.I4(bram_addr_a[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(s_axi_wvalid),
.O(bram_addr_inc));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(wr_data_sm_cs[1]),
.O(bram_addr_rst_cmb));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_8),
.Q(bram_addr_a[8]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_7),
.Q(bram_addr_a[9]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[10]),
.Q(bram_addr_a[10]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[11]),
.Q(bram_addr_a[11]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[12]),
.Q(bram_addr_a[12]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[13]),
.Q(bram_addr_a[13]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_16),
.Q(bram_addr_a[0]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_15),
.Q(bram_addr_a[1]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_14),
.Q(bram_addr_a[2]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_13),
.Q(bram_addr_a[3]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_12),
.Q(bram_addr_a[4]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_11),
.Q(bram_addr_a[5]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_10),
.Q(bram_addr_a[6]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_9),
.Q(bram_addr_a[7]),
.R(I_WRAP_BRST_n_0));
LUT5 #(
.INIT(32'h15FF1500))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.O(axi_wdata_full_cmb));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wdata_full_cmb),
.Q(axi_wdata_full_reg),
.R(SR));
LUT6 #(
.INIT(64'h4777477444444444))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(s_axi_wvalid),
.O(bram_en_cmb));
LUT3 #(
.INIT(8'h15))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_cmb),
.Q(bram_en_a),
.R(SR));
LUT6 #(
.INIT(64'h0010001000101110))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1
(.I0(wr_data_sm_cs[0]),
.I1(wr_data_sm_cs[1]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I5(axi_wr_burst),
.O(clr_bram_we_cmb));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'h80))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(clr_bram_we_cmb),
.Q(clr_bram_we),
.R(SR));
LUT6 #(
.INIT(64'hFEAAFEFF02AA0200))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ),
.I1(axi_wr_burst),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ),
.I5(delay_aw_active_clr),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000222E))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2
(.I0(s_axi_wlast),
.I1(wr_data_sm_cs[2]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[1]),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ));
LUT6 #(
.INIT(64'h8B338B0088008800))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3
(.I0(delay_aw_active_clr),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(bvalid_cnt_inc11_out),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4
(.I0(s_axi_wvalid),
.I1(s_axi_wlast),
.O(bvalid_cnt_inc11_out));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ),
.Q(delay_aw_active_clr),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[0].bram_wrdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[0]),
.Q(bram_wrdata_a[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[10].bram_wrdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[10]),
.Q(bram_wrdata_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[11].bram_wrdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[11]),
.Q(bram_wrdata_a[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[12].bram_wrdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[12]),
.Q(bram_wrdata_a[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[13].bram_wrdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[13]),
.Q(bram_wrdata_a[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[14].bram_wrdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[14]),
.Q(bram_wrdata_a[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[15].bram_wrdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[15]),
.Q(bram_wrdata_a[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[16].bram_wrdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[16]),
.Q(bram_wrdata_a[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[17].bram_wrdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[17]),
.Q(bram_wrdata_a[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[18].bram_wrdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[18]),
.Q(bram_wrdata_a[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[19].bram_wrdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[19]),
.Q(bram_wrdata_a[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[1].bram_wrdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[1]),
.Q(bram_wrdata_a[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[20].bram_wrdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[20]),
.Q(bram_wrdata_a[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[21].bram_wrdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[21]),
.Q(bram_wrdata_a[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[22].bram_wrdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[22]),
.Q(bram_wrdata_a[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[23].bram_wrdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[23]),
.Q(bram_wrdata_a[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[24].bram_wrdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[24]),
.Q(bram_wrdata_a[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[25].bram_wrdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[25]),
.Q(bram_wrdata_a[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[26].bram_wrdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[26]),
.Q(bram_wrdata_a[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[27].bram_wrdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[27]),
.Q(bram_wrdata_a[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[28].bram_wrdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[28]),
.Q(bram_wrdata_a[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[29].bram_wrdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[29]),
.Q(bram_wrdata_a[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[2].bram_wrdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[2]),
.Q(bram_wrdata_a[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[30].bram_wrdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[30]),
.Q(bram_wrdata_a[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[31].bram_wrdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[31]),
.Q(bram_wrdata_a[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[3].bram_wrdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[3]),
.Q(bram_wrdata_a[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[4].bram_wrdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[4]),
.Q(bram_wrdata_a[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[5].bram_wrdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[5]),
.Q(bram_wrdata_a[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[6].bram_wrdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[6]),
.Q(bram_wrdata_a[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[7].bram_wrdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[7]),
.Q(bram_wrdata_a[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[8].bram_wrdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[8]),
.Q(bram_wrdata_a[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[9].bram_wrdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[9]),
.Q(bram_wrdata_a[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hD0FF))
\GEN_WR_NO_ECC.bram_we_int[3]_i_1
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(clr_bram_we),
.I3(s_axi_aresetn),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\GEN_WR_NO_ECC.bram_we_int[3]_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[0]),
.Q(bram_we_a[0]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[1]),
.Q(bram_we_a[1]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[2]),
.Q(bram_we_a[2]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[3]),
.Q(bram_we_a[3]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst I_WRAP_BRST
(.D({bram_addr_ld,I_WRAP_BRST_n_7,I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16}),
.E(I_WRAP_BRST_n_2),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (I_WRAP_BRST_n_17),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ),
.Q(axi_awlen_pipe[3:0]),
.SR(I_WRAP_BRST_n_0),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_awsize_pipe(axi_awsize_pipe),
.bram_addr_a(bram_addr_a[9:0]),
.bram_addr_inc(bram_addr_inc),
.bram_addr_ld_en(bram_addr_ld_en),
.bram_addr_ld_en_mod(bram_addr_ld_en_mod),
.bram_addr_rst_cmb(bram_addr_rst_cmb),
.bvalid_cnt(bvalid_cnt),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.curr_fixed_burst(curr_fixed_burst),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_fixed_burst_reg_reg(I_WRAP_BRST_n_22),
.curr_wrap_burst(curr_wrap_burst),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.curr_wrap_burst_reg_reg(I_WRAP_BRST_n_23),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(SR),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen[3:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wvalid(s_axi_wvalid),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_19),
.\save_init_bram_addr_ld_reg[15]_1 (I_WRAP_BRST_n_20),
.\save_init_bram_addr_ld_reg[15]_2 (I_WRAP_BRST_n_21),
.wr_addr_sm_cs(wr_addr_sm_cs));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[0]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_15),
.Q(s_axi_bid[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[10]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_5),
.Q(s_axi_bid[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[11]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_4),
.Q(s_axi_bid[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[1]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_14),
.Q(s_axi_bid[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[2]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_13),
.Q(s_axi_bid[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[3]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_12),
.Q(s_axi_bid[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[4]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_11),
.Q(s_axi_bid[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[5]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_10),
.Q(s_axi_bid[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[6]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_9),
.Q(s_axi_bid[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[7]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_8),
.Q(s_axi_bid[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[8]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_7),
.Q(s_axi_bid[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[9]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_6),
.Q(s_axi_bid[9]),
.R(SR));
LUT6 #(
.INIT(64'hAAAAAAAAAAAA8A88))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt_inc),
.I2(BID_FIFO_n_3),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(bvalid_cnt[1]),
.O(axi_bvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_int_i_1_n_0),
.Q(s_axi_bvalid),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
axi_wr_burst_i_1
(.I0(axi_wr_burst_cmb),
.I1(axi_wr_burst_i_3_n_0),
.I2(axi_wr_burst),
.O(axi_wr_burst_i_1_n_0));
LUT5 #(
.INIT(32'h3088FCBB))
axi_wr_burst_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wlast),
.O(axi_wr_burst_cmb));
LUT6 #(
.INIT(64'h00000000AAAAA222))
axi_wr_burst_i_3
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[0]),
.I2(axi_wr_burst_cmb0),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[1]),
.I5(wr_data_sm_cs[2]),
.O(axi_wr_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wr_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wr_burst_i_1_n_0),
.Q(axi_wr_burst),
.R(SR));
LUT6 #(
.INIT(64'hEA00EAFF00000000))
axi_wready_int_mod_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.I5(s_axi_aresetn),
.O(axi_wready_int_mod_i_1_n_0));
LUT5 #(
.INIT(32'hF8F9F0F0))
axi_wready_int_mod_i_3
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(axi_wdata_full_reg),
.I3(axi_wdata_full_cmb114_out),
.I4(s_axi_wvalid),
.O(axi_wready_int_mod_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wready_int_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_int_mod_i_1_n_0),
.Q(s_axi_wready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hEF))
bid_gets_fifo_load_d1_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.O(bid_gets_fifo_load_d1_i_2_n_0));
FDRE #(
.INIT(1'b0))
bid_gets_fifo_load_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bid_gets_fifo_load),
.Q(bid_gets_fifo_load_d1),
.R(SR));
LUT6 #(
.INIT(64'h95956A6A95956AAA))
\bvalid_cnt[0]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD5D5BFBF2A2A4000))
\bvalid_cnt[1]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD52AFF00FF00BF00))
\bvalid_cnt[2]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[0]_i_1_n_0 ),
.Q(bvalid_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[1]_i_1_n_0 ),
.Q(bvalid_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[2]_i_1_n_0 ),
.Q(bvalid_cnt[2]),
.R(SR));
LUT6 #(
.INIT(64'h00A0000000A0E0E0))
curr_awlen_reg_1_or_2_i_1
(.I0(curr_awlen_reg_1_or_2_i_2_n_0),
.I1(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I2(curr_awlen_reg_1_or_2_i_3_n_0),
.I3(axi_awlen_pipe[3]),
.I4(axi_awaddr_full),
.I5(s_axi_awlen[3]),
.O(curr_awlen_reg_1_or_20));
LUT5 #(
.INIT(32'h00000004))
curr_awlen_reg_1_or_2_i_2
(.I0(axi_awlen_pipe[7]),
.I1(axi_awaddr_full),
.I2(axi_awlen_pipe[5]),
.I3(axi_awlen_pipe[4]),
.I4(axi_awlen_pipe[6]),
.O(curr_awlen_reg_1_or_2_i_2_n_0));
LUT5 #(
.INIT(32'h00053305))
curr_awlen_reg_1_or_2_i_3
(.I0(s_axi_awlen[2]),
.I1(axi_awlen_pipe[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[1]),
.O(curr_awlen_reg_1_or_2_i_3_n_0));
FDRE #(
.INIT(1'b0))
curr_awlen_reg_1_or_2_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_awlen_reg_1_or_20),
.Q(curr_awlen_reg_1_or_2),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_22),
.Q(curr_fixed_burst_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_23),
.Q(curr_wrap_burst_reg),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
(SR,
bram_addr_ld_en_mod,
E,
D,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
bram_addr_ld_en,
\save_init_bram_addr_ld_reg[15]_0 ,
\save_init_bram_addr_ld_reg[15]_1 ,
\save_init_bram_addr_ld_reg[15]_2 ,
curr_fixed_burst_reg_reg,
curr_wrap_burst_reg_reg,
curr_fixed_burst_reg,
bram_addr_inc,
bram_addr_rst_cmb,
s_axi_aresetn,
out,
s_axi_wvalid,
bram_addr_a,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ,
axi_awaddr_full,
s_axi_awaddr,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
wr_addr_sm_cs,
last_data_ack_mod,
bvalid_cnt,
aw_active,
s_axi_awvalid,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
axi_awlen_pipe_1_or_2,
curr_awlen_reg_1_or_2,
curr_wrap_burst_reg,
Q,
s_axi_awlen,
axi_awsize_pipe,
curr_fixed_burst,
curr_wrap_burst,
s_axi_aresetn_0,
s_axi_aclk);
output [0:0]SR;
output bram_addr_ld_en_mod;
output [0:0]E;
output [13:0]D;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
output bram_addr_ld_en;
output \save_init_bram_addr_ld_reg[15]_0 ;
output \save_init_bram_addr_ld_reg[15]_1 ;
output \save_init_bram_addr_ld_reg[15]_2 ;
output curr_fixed_burst_reg_reg;
output curr_wrap_burst_reg_reg;
input curr_fixed_burst_reg;
input bram_addr_inc;
input bram_addr_rst_cmb;
input s_axi_aresetn;
input [2:0]out;
input s_axi_wvalid;
input [9:0]bram_addr_a;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
input axi_awaddr_full;
input [13:0]s_axi_awaddr;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input wr_addr_sm_cs;
input last_data_ack_mod;
input [2:0]bvalid_cnt;
input aw_active;
input s_axi_awvalid;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input axi_awlen_pipe_1_or_2;
input curr_awlen_reg_1_or_2;
input curr_wrap_burst_reg;
input [3:0]Q;
input [3:0]s_axi_awlen;
input [0:0]axi_awsize_pipe;
input curr_fixed_burst;
input curr_wrap_burst;
input [0:0]s_axi_aresetn_0;
input s_axi_aclk;
wire [13:0]D;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
wire [3:0]Q;
wire [0:0]SR;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire [0:0]axi_awsize_pipe;
wire [9:0]bram_addr_a;
wire bram_addr_inc;
wire [9:1]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire [2:0]bvalid_cnt;
wire curr_awlen_reg_1_or_2;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_fixed_burst_reg_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire curr_wrap_burst_reg_reg;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]s_axi_aresetn_0;
wire [13:0]s_axi_awaddr;
wire [3:0]s_axi_awlen;
wire s_axi_awvalid;
wire s_axi_wvalid;
wire [15:3]save_init_bram_addr_ld;
wire \save_init_bram_addr_ld[3]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg[15]_1 ;
wire \save_init_bram_addr_ld_reg[15]_2 ;
wire wr_addr_sm_cs;
wire [2:0]wrap_burst_total;
wire \wrap_burst_total[0]_i_1__0_n_0 ;
wire \wrap_burst_total[0]_i_2__0_n_0 ;
wire \wrap_burst_total[0]_i_3_n_0 ;
wire \wrap_burst_total[1]_i_1__0_n_0 ;
wire \wrap_burst_total[1]_i_2_n_0 ;
wire \wrap_burst_total[1]_i_3_n_0 ;
wire \wrap_burst_total[2]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_2__0_n_0 ;
wire \wrap_burst_total[2]_i_3__0_n_0 ;
LUT6 #(
.INIT(64'hBB8BBBBB88B88888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1
(.I0(bram_addr_ld[8]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[7]),
.I5(bram_addr_a[8]),
.O(D[8]));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(E));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2
(.I0(bram_addr_ld[9]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[9]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ),
.I4(bram_addr_a[8]),
.O(D[9]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(save_init_bram_addr_ld[12]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1
(.I0(save_init_bram_addr_ld[13]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1
(.I0(save_init_bram_addr_ld[14]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[12]),
.O(D[12]));
LUT5 #(
.INIT(32'h4500FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(bram_addr_inc),
.I3(bram_addr_rst_cmb),
.I4(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(bram_addr_ld_en_mod));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3
(.I0(save_init_bram_addr_ld[15]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[13]),
.O(D[13]));
LUT6 #(
.INIT(64'h55555555FFFFFFDF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6
(.I0(curr_wrap_burst_reg),
.I1(wrap_burst_total[1]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[0]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'h000000008F00C000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8
(.I0(bram_addr_a[2]),
.I1(bram_addr_a[1]),
.I2(wrap_burst_total[1]),
.I3(bram_addr_a[0]),
.I4(wrap_burst_total[0]),
.I5(wrap_burst_total[2]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hB800B800B800FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1
(.I0(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.I1(axi_awaddr_full),
.I2(s_axi_awaddr[0]),
.I3(bram_addr_ld_en),
.I4(bram_addr_ld_en_mod),
.I5(bram_addr_a[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h8BB8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1
(.I0(bram_addr_ld[1]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[1]),
.I3(bram_addr_a[0]),
.O(D[1]));
LUT5 #(
.INIT(32'h8BB8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1
(.I0(bram_addr_ld[2]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[0]),
.I4(bram_addr_a[1]),
.O(D[2]));
LUT6 #(
.INIT(64'h8BB8B8B8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1
(.I0(bram_addr_ld[3]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[3]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[0]),
.I5(bram_addr_a[1]),
.O(D[3]));
LUT4 #(
.INIT(16'hB88B))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1
(.I0(bram_addr_ld[4]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.O(D[4]));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1
(.I0(bram_addr_ld[5]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[5]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I4(bram_addr_a[4]),
.O(D[5]));
LUT6 #(
.INIT(64'hB8B88BB8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1
(.I0(bram_addr_ld[6]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(bram_addr_a[4]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(bram_addr_a[5]),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0
(.I0(bram_addr_a[1]),
.I1(bram_addr_a[0]),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1
(.I0(bram_addr_ld[7]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[6]),
.O(D[7]));
LUT4 #(
.INIT(16'h00E2))
curr_fixed_burst_reg_i_1__0
(.I0(curr_fixed_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_fixed_burst),
.I3(SR),
.O(curr_fixed_burst_reg_reg));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT4 #(
.INIT(16'h00E2))
curr_wrap_burst_reg_i_1__0
(.I0(curr_wrap_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_wrap_burst),
.I3(SR),
.O(curr_wrap_burst_reg_reg));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1
(.I0(save_init_bram_addr_ld[10]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[8]),
.O(bram_addr_ld[8]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1
(.I0(save_init_bram_addr_ld[11]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[9]),
.O(bram_addr_ld[9]));
LUT6 #(
.INIT(64'h0808080808AA0808))
\save_init_bram_addr_ld[15]_i_1
(.I0(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I1(\save_init_bram_addr_ld_reg[15]_0 ),
.I2(wr_addr_sm_cs),
.I3(\save_init_bram_addr_ld_reg[15]_1 ),
.I4(last_data_ack_mod),
.I5(\save_init_bram_addr_ld_reg[15]_2 ),
.O(bram_addr_ld_en));
LUT6 #(
.INIT(64'h007F007F007F0000))
\save_init_bram_addr_ld[15]_i_2
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.I3(aw_active),
.I4(axi_awaddr_full),
.I5(s_axi_awvalid),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT3 #(
.INIT(8'h80))
\save_init_bram_addr_ld[15]_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(\save_init_bram_addr_ld_reg[15]_1 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT4 #(
.INIT(16'hFFFD))
\save_init_bram_addr_ld[15]_i_4
(.I0(axi_awaddr_full),
.I1(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I2(axi_awlen_pipe_1_or_2),
.I3(curr_awlen_reg_1_or_2),
.O(\save_init_bram_addr_ld_reg[15]_2 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1
(.I0(\save_init_bram_addr_ld[3]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[1]),
.O(bram_addr_ld[1]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hC80C))
\save_init_bram_addr_ld[3]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(save_init_bram_addr_ld[3]),
.I2(wrap_burst_total[1]),
.I3(wrap_burst_total[2]),
.O(\save_init_bram_addr_ld[3]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1
(.I0(\save_init_bram_addr_ld[4]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[2]),
.O(bram_addr_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2__0
(.I0(save_init_bram_addr_ld[4]),
.I1(wrap_burst_total[0]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\save_init_bram_addr_ld[5]_i_1
(.I0(save_init_bram_addr_ld[5]),
.I1(\save_init_bram_addr_ld[5]_i_2__0_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I3(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.I4(axi_awaddr_full),
.I5(s_axi_awaddr[3]),
.O(bram_addr_ld[3]));
LUT3 #(
.INIT(8'hFB))
\save_init_bram_addr_ld[5]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(wrap_burst_total[2]),
.I2(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[5]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1
(.I0(save_init_bram_addr_ld[6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[4]),
.O(bram_addr_ld[4]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1
(.I0(save_init_bram_addr_ld[7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[5]),
.O(bram_addr_ld[5]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1
(.I0(save_init_bram_addr_ld[8]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[6]),
.O(bram_addr_ld[6]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1
(.I0(save_init_bram_addr_ld[9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[7]),
.O(bram_addr_ld[7]));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[8]),
.Q(save_init_bram_addr_ld[10]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[9]),
.Q(save_init_bram_addr_ld[11]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(save_init_bram_addr_ld[12]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(save_init_bram_addr_ld[13]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(save_init_bram_addr_ld[14]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(save_init_bram_addr_ld[15]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[1]),
.Q(save_init_bram_addr_ld[3]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[2]),
.Q(save_init_bram_addr_ld[4]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[3]),
.Q(save_init_bram_addr_ld[5]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[4]),
.Q(save_init_bram_addr_ld[6]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[5]),
.Q(save_init_bram_addr_ld[7]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[6]),
.Q(save_init_bram_addr_ld[8]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[7]),
.Q(save_init_bram_addr_ld[9]),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0000A22200000000))
\wrap_burst_total[0]_i_1__0
(.I0(\wrap_burst_total[0]_i_2__0_n_0 ),
.I1(\wrap_burst_total[0]_i_3_n_0 ),
.I2(Q[1]),
.I3(Q[2]),
.I4(\wrap_burst_total[2]_i_2__0_n_0 ),
.I5(\wrap_burst_total[1]_i_2_n_0 ),
.O(\wrap_burst_total[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hCCA533A5FFA5FFA5))
\wrap_burst_total[0]_i_2__0
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.I5(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3
(.I0(axi_awaddr_full),
.I1(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h08000800F3000000))
\wrap_burst_total[1]_i_1__0
(.I0(\wrap_burst_total[2]_i_3__0_n_0 ),
.I1(axi_awaddr_full),
.I2(axi_awsize_pipe),
.I3(\wrap_burst_total[1]_i_2_n_0 ),
.I4(\wrap_burst_total[1]_i_3_n_0 ),
.I5(\wrap_burst_total[2]_i_2__0_n_0 ),
.O(\wrap_burst_total[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[0]),
.O(\wrap_burst_total[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[1]),
.O(\wrap_burst_total[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hA000000088008800))
\wrap_burst_total[2]_i_1__0
(.I0(\wrap_burst_total[2]_i_2__0_n_0 ),
.I1(s_axi_awlen[0]),
.I2(Q[0]),
.I3(\wrap_burst_total[2]_i_3__0_n_0 ),
.I4(axi_awsize_pipe),
.I5(axi_awaddr_full),
.O(\wrap_burst_total[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_2__0
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[3]),
.O(\wrap_burst_total[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_3__0
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.O(\wrap_burst_total[2]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1__0_n_0 ),
.Q(wrap_burst_total[0]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1__0_n_0 ),
.Q(wrap_burst_total[1]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1__0_n_0 ),
.Q(wrap_burst_total[2]),
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
(SR,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[0]_1 ,
\wrap_burst_total_reg[0]_2 ,
\wrap_burst_total_reg[0]_3 ,
E,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
D,
bram_addr_ld_en,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\rd_data_sm_cs_reg[1] ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ,
\save_init_bram_addr_ld_reg[15]_0 ,
axi_b2b_brst_reg,
\rd_data_sm_cs_reg[3] ,
rd_adv_buf67_out,
s_axi_aresetn,
Q,
axi_arsize_pipe,
s_axi_arlen,
axi_araddr_full,
curr_fixed_burst_reg,
s_axi_araddr,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ,
curr_wrap_burst_reg,
\rd_data_sm_cs_reg[3]_0 ,
axi_rd_burst_two_reg,
axi_rd_burst,
axi_aresetn_d2,
rd_addr_sm_cs,
last_bram_addr,
ar_active,
pend_rd_op,
no_ar_ack,
s_axi_arvalid,
brst_zero,
axi_rvalid_int_reg,
s_axi_rready,
end_brst_rd,
axi_b2b_brst,
axi_arsize_pipe_max,
disable_b2b_brst,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ,
axi_arlen_pipe_1_or_2,
s_axi_aclk);
output [0:0]SR;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[0]_1 ;
output \wrap_burst_total_reg[0]_2 ;
output \wrap_burst_total_reg[0]_3 ;
output [1:0]E;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output [13:0]D;
output bram_addr_ld_en;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
output \rd_data_sm_cs_reg[1] ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
output \save_init_bram_addr_ld_reg[15]_0 ;
output axi_b2b_brst_reg;
output \rd_data_sm_cs_reg[3] ;
output rd_adv_buf67_out;
input s_axi_aresetn;
input [3:0]Q;
input [0:0]axi_arsize_pipe;
input [3:0]s_axi_arlen;
input axi_araddr_full;
input curr_fixed_burst_reg;
input [13:0]s_axi_araddr;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
input [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
input curr_wrap_burst_reg;
input [3:0]\rd_data_sm_cs_reg[3]_0 ;
input axi_rd_burst_two_reg;
input axi_rd_burst;
input axi_aresetn_d2;
input rd_addr_sm_cs;
input last_bram_addr;
input ar_active;
input pend_rd_op;
input no_ar_ack;
input s_axi_arvalid;
input brst_zero;
input axi_rvalid_int_reg;
input s_axi_rready;
input end_brst_rd;
input axi_b2b_brst;
input axi_arsize_pipe_max;
input disable_b2b_brst;
input \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
input axi_arlen_pipe_1_or_2;
input s_axi_aclk;
wire [13:0]D;
wire [1:0]E;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
wire [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire [3:0]Q;
wire [0:0]SR;
wire ar_active;
wire axi_araddr_full;
wire axi_aresetn_d2;
wire axi_arlen_pipe_1_or_2;
wire [0:0]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_b2b_brst;
wire axi_b2b_brst_reg;
wire axi_rd_burst;
wire axi_rd_burst_two_reg;
wire axi_rvalid_int_reg;
wire bram_addr_ld_en;
wire brst_zero;
wire curr_fixed_burst_reg;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire end_brst_rd;
wire last_bram_addr;
wire no_ar_ack;
wire pend_rd_op;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire \rd_data_sm_cs_reg[1] ;
wire \rd_data_sm_cs_reg[3] ;
wire [3:0]\rd_data_sm_cs_reg[3]_0 ;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire s_axi_aresetn;
wire [3:0]s_axi_arlen;
wire s_axi_arvalid;
wire s_axi_rready;
wire \save_init_bram_addr_ld[10]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[11]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[15]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2_n_0 ;
wire \save_init_bram_addr_ld[4]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2_n_0 ;
wire \save_init_bram_addr_ld[5]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2_n_0 ;
wire \save_init_bram_addr_ld[6]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[7]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[8]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[9]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg_n_0_[10] ;
wire \save_init_bram_addr_ld_reg_n_0_[11] ;
wire \save_init_bram_addr_ld_reg_n_0_[12] ;
wire \save_init_bram_addr_ld_reg_n_0_[13] ;
wire \save_init_bram_addr_ld_reg_n_0_[14] ;
wire \save_init_bram_addr_ld_reg_n_0_[15] ;
wire \save_init_bram_addr_ld_reg_n_0_[3] ;
wire \save_init_bram_addr_ld_reg_n_0_[4] ;
wire \save_init_bram_addr_ld_reg_n_0_[5] ;
wire \save_init_bram_addr_ld_reg_n_0_[6] ;
wire \save_init_bram_addr_ld_reg_n_0_[7] ;
wire \save_init_bram_addr_ld_reg_n_0_[8] ;
wire \save_init_bram_addr_ld_reg_n_0_[9] ;
wire \wrap_burst_total[0]_i_1_n_0 ;
wire \wrap_burst_total[0]_i_3__0_n_0 ;
wire \wrap_burst_total[1]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_2_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[0]_1 ;
wire \wrap_burst_total_reg[0]_2 ;
wire \wrap_burst_total_reg[0]_3 ;
wire \wrap_burst_total_reg_n_0_[0] ;
wire \wrap_burst_total_reg_n_0_[1] ;
wire \wrap_burst_total_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hDF20FFFFDF200000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.O(D[8]));
LUT3 #(
.INIT(8'h5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.I2(curr_fixed_burst_reg),
.O(E[0]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hE0E0F0F0E0E0FFF0))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ),
.I2(\rd_data_sm_cs_reg[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\rd_data_sm_cs_reg[3]_0 [1]),
.I5(\rd_data_sm_cs_reg[3]_0 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5
(.I0(axi_rd_burst_two_reg),
.I1(\rd_data_sm_cs_reg[3]_0 [0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000080800080))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6
(.I0(\rd_data_sm_cs_reg[3]_0 [0]),
.I1(axi_rvalid_int_reg),
.I2(s_axi_rready),
.I3(end_brst_rd),
.I4(axi_b2b_brst),
.I5(brst_zero),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[12] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[13] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[14] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT1 #(
.INIT(2'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.O(E[1]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[15] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[13]),
.O(D[13]));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ));
LUT5 #(
.INIT(32'h88A80000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ),
.I2(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(curr_wrap_burst_reg),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'h000000008F00A000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I4(\wrap_burst_total_reg_n_0_[0] ),
.I5(\wrap_burst_total_reg_n_0_[2] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h00000000A808FD5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0
(.I0(bram_addr_ld_en),
.I1(s_axi_araddr[0]),
.I2(axi_araddr_full),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(D[0]));
LUT4 #(
.INIT(16'h6F60))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AFF6A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h6AAAFFFF6AAA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.O(D[3]));
LUT4 #(
.INIT(16'h9F90))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hA6AAFFFFA6AA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.O(D[7]));
LUT2 #(
.INIT(4'h8))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4
(.I0(axi_rvalid_int_reg),
.I1(s_axi_rready),
.O(rd_adv_buf67_out));
LUT5 #(
.INIT(32'hFFFDFFFF))
axi_b2b_brst_i_2
(.I0(axi_arsize_pipe_max),
.I1(disable_b2b_brst),
.I2(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ),
.I3(axi_arlen_pipe_1_or_2),
.I4(axi_araddr_full),
.O(axi_b2b_brst_reg));
LUT2 #(
.INIT(4'hB))
bram_en_int_i_5
(.I0(\rd_data_sm_cs_reg[3]_0 [3]),
.I1(\rd_data_sm_cs_reg[3]_0 [2]),
.O(\rd_data_sm_cs_reg[3] ));
LUT6 #(
.INIT(64'h0010000000000000))
bram_en_int_i_8
(.I0(end_brst_rd),
.I1(brst_zero),
.I2(\rd_data_sm_cs_reg[3]_0 [2]),
.I3(\rd_data_sm_cs_reg[3]_0 [0]),
.I4(axi_rvalid_int_reg),
.I5(s_axi_rready),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ));
LUT1 #(
.INIT(2'h1))
bram_rst_b_INST_0
(.I0(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'h000F000E000F0000))
\rd_data_sm_cs[1]_i_2
(.I0(axi_rd_burst_two_reg),
.I1(axi_rd_burst),
.I2(\rd_data_sm_cs_reg[3]_0 [3]),
.I3(\rd_data_sm_cs_reg[3]_0 [2]),
.I4(\rd_data_sm_cs_reg[3]_0 [1]),
.I5(\rd_data_sm_cs_reg[3]_0 [0]),
.O(\rd_data_sm_cs_reg[1] ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[10] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[8]),
.O(\save_init_bram_addr_ld[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[9]),
.O(\save_init_bram_addr_ld[11]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h02AA0202))
\save_init_bram_addr_ld[15]_i_1__0
(.I0(axi_aresetn_d2),
.I1(rd_addr_sm_cs),
.I2(\save_init_bram_addr_ld[15]_i_2__0_n_0 ),
.I3(\save_init_bram_addr_ld_reg[15]_0 ),
.I4(last_bram_addr),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hFEFEFEFF))
\save_init_bram_addr_ld[15]_i_2__0
(.I0(ar_active),
.I1(pend_rd_op),
.I2(no_ar_ack),
.I3(s_axi_arvalid),
.I4(axi_araddr_full),
.O(\save_init_bram_addr_ld[15]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\save_init_bram_addr_ld[15]_i_3__0
(.I0(axi_b2b_brst_reg),
.I1(\rd_data_sm_cs_reg[3]_0 [0]),
.I2(\rd_data_sm_cs_reg[3]_0 [1]),
.I3(\rd_data_sm_cs_reg[3] ),
.I4(brst_zero),
.I5(rd_adv_buf67_out),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1__0
(.I0(\save_init_bram_addr_ld[3]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[1]),
.O(\save_init_bram_addr_ld[3]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hA282))
\save_init_bram_addr_ld[3]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[3] ),
.I1(\wrap_burst_total_reg_n_0_[1] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[0] ),
.O(\save_init_bram_addr_ld[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1__0
(.I0(\save_init_bram_addr_ld[4]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[2]),
.O(\save_init_bram_addr_ld[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[4] ),
.I1(\wrap_burst_total_reg_n_0_[0] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\save_init_bram_addr_ld[5]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[5] ),
.I1(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.I4(axi_araddr_full),
.I5(s_axi_araddr[3]),
.O(\save_init_bram_addr_ld[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\save_init_bram_addr_ld[5]_i_2
(.I0(\wrap_burst_total_reg_n_0_[0] ),
.I1(\wrap_burst_total_reg_n_0_[2] ),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[6] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[4]),
.O(\save_init_bram_addr_ld[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[7] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[5]),
.O(\save_init_bram_addr_ld[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[8] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[6]),
.O(\save_init_bram_addr_ld[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[9] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[7]),
.O(\save_init_bram_addr_ld[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[10] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[11] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(\save_init_bram_addr_ld_reg_n_0_[12] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(\save_init_bram_addr_ld_reg_n_0_[13] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(\save_init_bram_addr_ld_reg_n_0_[14] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(\save_init_bram_addr_ld_reg_n_0_[15] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[7] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[8] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[9] ),
.R(SR));
LUT6 #(
.INIT(64'h3202010100000000))
\wrap_burst_total[0]_i_1
(.I0(\wrap_burst_total_reg[0]_0 ),
.I1(\wrap_burst_total_reg[0]_1 ),
.I2(\wrap_burst_total[0]_i_3__0_n_0 ),
.I3(Q[2]),
.I4(\wrap_burst_total_reg[0]_2 ),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2
(.I0(Q[2]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[2]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3__0
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.O(\wrap_burst_total[0]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_4
(.I0(Q[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.O(\wrap_burst_total_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_5
(.I0(Q[0]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[0]),
.O(\wrap_burst_total_reg[0]_3 ));
LUT6 #(
.INIT(64'h220A880A000A880A))
\wrap_burst_total[1]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(axi_arsize_pipe),
.I2(s_axi_arlen[3]),
.I3(axi_araddr_full),
.I4(Q[3]),
.I5(Q[2]),
.O(\wrap_burst_total[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8088008880000000))
\wrap_burst_total[2]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(\wrap_burst_total_reg[0]_1 ),
.I2(axi_arsize_pipe),
.I3(axi_araddr_full),
.I4(Q[2]),
.I5(s_axi_arlen[2]),
.O(\wrap_burst_total[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_2
(.I0(s_axi_arlen[1]),
.I1(Q[1]),
.I2(s_axi_arlen[0]),
.I3(axi_araddr_full),
.I4(Q[0]),
.O(\wrap_burst_total[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_3
(.I0(Q[3]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[3]),
.O(\wrap_burst_total_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[2] ),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [15:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input s_axi_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [15:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input s_axi_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) output [3:0]bram_we_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output [15:0]bram_addr_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) output [31:0]bram_wrdata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input [31:0]bram_rddata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) output bram_rst_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) output bram_clk_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) output bram_en_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) output [3:0]bram_we_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) output [15:0]bram_addr_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) output [31:0]bram_wrdata_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) input [31:0]bram_rddata_b;
wire [15:0]bram_addr_a;
wire [15:0]bram_addr_b;
wire bram_clk_a;
wire bram_clk_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire bram_rst_b;
wire [3:0]bram_we_a;
wire [3:0]bram_we_b;
wire [31:0]bram_wrdata_a;
wire [31:0]bram_wrdata_b;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "14" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "16384" *)
(* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *)
(* C_S_AXI_ADDR_WIDTH = "16" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_clk_a(bram_clk_a),
.bram_clk_b(bram_clk_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_rst_b(bram_rst_b),
.bram_we_a(bram_we_a),
.bram_we_b(bram_we_b),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(bram_wrdata_b),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_hs_demo s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_BEHAVIORAL_V |
//
// lfsr128.v -- a linear feedback shift register with 128 bits
// (actually constructed from 4 instances of a 32-bit lfsr)
//
`include "../../src/fpga/LogicProbe.v"
`timescale 1ns/1ns
module lfsr128(clk, reset_in_n, s, rs232_txd);
input clk;
input reset_in_n;
output [3:0] s;
output rs232_txd;
wire reset;
reg [3:0] reset_counter;
reg [31:0] lfsr0;
reg [31:0] lfsr1;
reg [31:0] lfsr2;
reg [31:0] lfsr3;
wire trigger;
wire sample;
wire [127:0] log_data;
assign reset = (reset_counter == 4'hF) ? 0 : 1;
always @(posedge clk) begin
if (reset_in_n == 0) begin
reset_counter <= 4'h0;
end else begin
if (reset_counter != 4'hF) begin
reset_counter <= reset_counter + 1;
end
end
end
always @(posedge clk) begin
if (reset == 1) begin
lfsr0 <= 32'hC70337DB;
lfsr1 <= 32'h7F4D514F;
lfsr2 <= 32'h75377599;
lfsr3 <= 32'h7D5937A3;
end else begin
if (lfsr0[0] == 0) begin
lfsr0 <= lfsr0 >> 1;
end else begin
lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001;
end
if (lfsr1[0] == 0) begin
lfsr1 <= lfsr1 >> 1;
end else begin
lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001;
end
if (lfsr2[0] == 0) begin
lfsr2 <= lfsr2 >> 1;
end else begin
lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001;
end
if (lfsr3[0] == 0) begin
lfsr3 <= lfsr3 >> 1;
end else begin
lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001;
end
end
end
assign s[3] = lfsr0[27];
assign s[2] = lfsr1[13];
assign s[1] = lfsr2[23];
assign s[0] = lfsr3[11];
assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0;
assign sample = 1;
assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 };
LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_xcvr (
// common reset
rst,
// receive interface
rx_clk,
rx_rstn,
rx_ext_sysref,
rx_sysref,
rx_ip_sync,
rx_sync,
rx_status,
// transmit interface
tx_clk,
tx_rstn,
tx_ext_sysref,
tx_sysref,
tx_sync,
tx_ip_sync,
tx_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00060162;
parameter ID = 0;
parameter DEVICE_TYPE = 0;
// common reset
output rst;
// receive interface
input rx_clk;
output rx_rstn;
input rx_ext_sysref;
output rx_sysref;
input rx_ip_sync;
output rx_sync;
input [ 7:0] rx_status;
// transmit interface
input tx_clk;
output tx_rstn;
input tx_ext_sysref;
output tx_sysref;
input tx_sync;
output tx_ip_sync;
input [ 7:0] tx_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_reset = 'd1;
reg up_rx_reset = 'd1;
reg up_tx_reset = 'd1;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_rx_sysref_sel = 'd0;
reg up_rx_sysref = 'd0;
reg up_rx_sync = 'd0;
reg up_rx_resetn = 'd0;
reg up_tx_sysref_sel = 'd0;
reg up_tx_sysref = 'd0;
reg up_tx_sync = 'd0;
reg up_tx_resetn = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg rx_rstn = 'd0;
reg rx_sysref_sel_m1 = 'd0;
reg rx_sysref_sel = 'd0;
reg rx_up_sysref_m1 = 'd0;
reg rx_up_sysref = 'd0;
reg rx_sysref = 'd0;
reg rx_up_sync_m1 = 'd0;
reg rx_up_sync = 'd0;
reg rx_sync = 'd0;
reg tx_rstn = 'd0;
reg tx_sysref_sel_m1 = 'd0;
reg tx_sysref_sel = 'd0;
reg tx_up_sysref_m1 = 'd0;
reg tx_up_sysref = 'd0;
reg tx_sysref = 'd0;
reg tx_up_sync_m1 = 'd0;
reg tx_up_sync = 'd0;
reg tx_ip_sync = 'd0;
reg [ 8:0] up_rx_status_m1 = 'd0;
reg [ 8:0] up_rx_status = 'd0;
reg [ 8:0] up_tx_status_m1 = 'd0;
reg [ 8:0] up_tx_status = 'd0;
// internal signals
wire rx_rst;
wire tx_rst;
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_reset <= 1'b1;
up_rx_reset <= 1'b1;
up_tx_reset <= 1'b1;
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_rx_sysref_sel <= 'd0;
up_rx_sysref <= 'd0;
up_rx_sync <= 'd0;
up_rx_resetn <= 'd0;
up_tx_sysref_sel <= 'd0;
up_tx_sysref <= 'd0;
up_tx_sync <= 'd0;
up_tx_resetn <= 'd0;
end else begin
up_reset <= ~up_resetn;
up_rx_reset <= ~(up_resetn & up_rx_resetn);
up_tx_reset <= ~(up_resetn & up_tx_resetn);
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h03)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_rx_sysref_sel <= up_wdata[1];
up_rx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_rx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_rx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tx_sysref_sel <= up_wdata[1];
up_tx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tx_resetn <= up_wdata[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h03: up_rdata <= {31'd0, up_resetn};
8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
8'h11: up_rdata <= {31'd0, up_rx_sync};
8'h12: up_rdata <= {23'd0, up_rx_status};
8'h13: up_rdata <= {31'd0, up_rx_resetn};
8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
8'h21: up_rdata <= {31'd0, up_tx_sync};
8'h22: up_rdata <= {23'd0, up_tx_status};
8'h23: up_rdata <= {31'd0, up_tx_resetn};
8'h30: up_rdata <= DEVICE_TYPE;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
assign rst = up_reset;
ad_rst i_rx_rst_reg (.preset(up_rx_reset), .clk(rx_clk), .rst(rx_rst));
ad_rst i_tx_rst_reg (.preset(up_tx_reset), .clk(tx_clk), .rst(tx_rst));
// rx sysref & sync
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst == 1'b1) begin
rx_rstn <= 'd0;
rx_sysref_sel_m1 <= 'd0;
rx_sysref_sel <= 'd0;
rx_up_sysref_m1 <= 'd0;
rx_up_sysref <= 'd0;
rx_sysref <= 'd0;
rx_up_sync_m1 <= 'd0;
rx_up_sync <= 'd0;
rx_sync <= 'd0;
end else begin
rx_rstn <= 1'd1;
rx_sysref_sel_m1 <= up_rx_sysref_sel;
rx_sysref_sel <= rx_sysref_sel_m1;
rx_up_sysref_m1 <= up_rx_sysref;
rx_up_sysref <= rx_up_sysref_m1;
if (rx_sysref_sel == 1'b1) begin
rx_sysref <= rx_ext_sysref;
end else begin
rx_sysref <= rx_up_sysref;
end
rx_up_sync_m1 <= up_rx_sync;
rx_up_sync <= rx_up_sync_m1;
rx_sync <= rx_up_sync & rx_ip_sync;
end
end
// tx sysref & sync
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst == 1'b1) begin
tx_rstn <= 'd0;
tx_sysref_sel_m1 <= 'd0;
tx_sysref_sel <= 'd0;
tx_up_sysref_m1 <= 'd0;
tx_up_sysref <= 'd0;
tx_sysref <= 'd0;
tx_up_sync_m1 <= 'd0;
tx_up_sync <= 'd0;
tx_ip_sync <= 'd0;
end else begin
tx_rstn <= 1'd1;
tx_sysref_sel_m1 <= up_tx_sysref_sel;
tx_sysref_sel <= tx_sysref_sel_m1;
tx_up_sysref_m1 <= up_tx_sysref;
tx_up_sysref <= tx_up_sysref_m1;
if (tx_sysref_sel == 1'b1) begin
tx_sysref <= tx_ext_sysref;
end else begin
tx_sysref <= tx_up_sysref;
end
tx_up_sync_m1 <= up_tx_sync;
tx_up_sync <= tx_up_sync_m1;
tx_ip_sync <= tx_up_sync & tx_sync;
end
end
// status
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rx_status_m1 <= 'd0;
up_rx_status <= 'd0;
up_tx_status_m1 <= 'd0;
up_tx_status <= 'd0;
end else begin
up_rx_status_m1 <= {rx_sync, rx_status};
up_rx_status <= up_rx_status_m1;
up_tx_status_m1 <= {tx_ip_sync, tx_status};
up_tx_status <= up_tx_status_m1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module butterfly1_8(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [17:0] i_0;
input signed [17:0] i_1;
input signed [17:0] i_2;
input signed [17:0] i_3;
input signed [17:0] i_4;
input signed [17:0] i_5;
input signed [17:0] i_6;
input signed [17:0] i_7;
output signed [18:0] o_0;
output signed [18:0] o_1;
output signed [18:0] o_2;
output signed [18:0] o_3;
output signed [18:0] o_4;
output signed [18:0] o_5;
output signed [18:0] o_6;
output signed [18:0] o_7;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [18:0] b_0;
wire signed [18:0] b_1;
wire signed [18:0] b_2;
wire signed [18:0] b_3;
wire signed [18:0] b_4;
wire signed [18:0] b_5;
wire signed [18:0] b_6;
wire signed [18:0] b_7;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_7;
assign b_1=i_1+i_6;
assign b_2=i_2+i_5;
assign b_3=i_3+i_4;
assign b_4=i_3-i_4;
assign b_5=i_2-i_5;
assign b_6=i_1-i_6;
assign b_7=i_0-i_7;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module cpu_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2013-2016 Colin Weltin-Wu ([email protected])
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* spi_top.v
* Top-level module which encompasses the SPI map containing all the
* control registers, and the digital register test interface.
*/
module spi_top(
// Outputs
o_ena_spi_clk, o_sdo, o_drvb,
// Map read-only inputs
// INSERT_RO
// Map write-only outputs
// INSERT_WO
// Map registered outputs
// INSERT_RW
// Register read signals
// INSERT_RD
// Register write signals
// INSERT_WR
// Inouts
io_success, vio_tbus,
// Inputs
i_rstb, i_clk_ext_osc, i_cs, i_sck, i_sdi);
// Clock and reset
input i_rstb;
input i_clk_ext_osc;
output o_ena_spi_clk;
// SPI interface
output o_sdo;
output o_drvb;
input i_cs;
input i_sck;
input i_sdi;
// SPI map controls
// Read-only inputs
// INSERT_RO_DECLARATION
// Write-only inputs
// INSERT_WO_DECLARATION
// Registered outputs
// INSERT_RW_DECLARATION
// Digital register interface
inout io_success;
inout [36:0] vio_tbus;
// Register read signals
// INSERT_RD_DECLARATION
// Register write signals
// INSERT_WR_DECLARATION
/*
* SPI core
*/
wire spi_active;
wire rx_valid;
wire [2:0] v_byte_num;
wire [7:0] v_data_rx;
wire [7:0] v_data_tx;
assign o_ena_spi_clk = spi_active;
spi_core #(.BITS_IN_BYTE(8), .NBIT_BIT_CTR(3), .NBIT_BYTE_CTR(3))
spi_interface(
// Outputs
.o_sdo (o_sdo),
.o_drvb (o_drvb),
.o_spi_active (spi_active),
.o_rx_valid (rx_valid),
.vo_byte_num (v_byte_num),
.vo_data_rx (v_data_rx),
// Inputs
.i_rstb (i_rstb),
.i_cs (i_cs),
.i_sck (i_sck),
.i_sdi (i_sdi),
.i_epol (1'b1),
.i_cpol (1'b1),
.i_cpha (1'b0),
.vi_data_tx (v_data_tx));
/*
* SPI map
*/
spi_map
spi_map_interface(
// Read-only inputs
// INSERT_RO_INST
// Write-only inputs
// INSERT_WO_INST
// Registered outputs
// INSERT_RW_INST
// Inouts
.vio_data_spi (v_data_tx),
// Inputs
.i_rstb (i_rstb),
.i_spi_active (spi_active),
.vi_data_rx (v_data_rx),
.i_rx_valid (rx_valid),
.vi_byte_num (v_byte_num));
/*
* SPI reg
*/
spi_reg
spi_reg_interface(// Register read signals
// INSERT_RD_INST
// Register write signals
// INSERT_WR_INST
// Inouts
.vio_data_regs (v_data_tx),
.io_success (io_success),
.vio_tbus (vio_tbus),
// Inputs
.i_rstb (i_rstb),
.i_clk_ext_osc (i_clk_ext_osc),
.i_spi_active (spi_active),
.vi_data_rx (v_data_rx),
.i_rx_valid (rx_valid),
.vi_byte_num (v_byte_num));
// Local Variables:
// verilog-library-directories:("/home/colinww/git/doormat_dig/scripts/spi_generation/" "/home/colinww/git/doormat_dig/source/spi_dig/")
// verilog-library-extensions:(".v" ".h")
// End:
endmodule // spi_top
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_pipe_misc.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_pipe_misc.v //
// Description : Implements the PIPE interface PIPELINE for all per link //
// interface signals //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_pipe_mics.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_pipe_misc #
(
parameter TCQ = 100,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
) (
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire [1:0] pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
input wire [5:0] pipe_tx_eqfs_i , // PIPE Tx
input wire [5:0] pipe_tx_eqlf_i , // PIPE Tx
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire [1:0] pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
output wire [5:0] pipe_tx_eqfs_o , // PIPE Tx
output wire [5:0] pipe_tx_eqlf_o , // PIPE Tx
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg [1:0] pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_eqfs_q ;
reg pipe_tx_eqlf_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg [1:0] pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
reg pipe_tx_eqfs_qq ;
reg pipe_tx_eqlf_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_i;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 1'b0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 2'b0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 3'b0;
pipe_tx_swing_q <= #TCQ 1'b0;
pipe_tx_eqfs_q <= #TCQ 5'b0;
pipe_tx_eqlf_q <= #TCQ 5'b0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_eqfs_q <= #TCQ pipe_tx_eqfs_i;
pipe_tx_eqlf_q <= #TCQ pipe_tx_eqlf_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_q;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 1'b0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 2'b0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 1'b0;
pipe_tx_swing_q <= #TCQ 1'b0;
pipe_tx_eqfs_q <= #TCQ 5'b0;
pipe_tx_eqlf_q <= #TCQ 5'b0;
pipe_tx_rcvr_det_qq <= #TCQ 1'b0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 2'b0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 1'b0;
pipe_tx_swing_qq <= #TCQ 1'b0;
pipe_tx_eqfs_qq <= #TCQ 5'b0;
pipe_tx_eqlf_qq <= #TCQ 5'b0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_eqfs_q <= #TCQ pipe_tx_eqfs_i;
pipe_tx_eqlf_q <= #TCQ pipe_tx_eqlf_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
pipe_tx_eqfs_qq <= #TCQ pipe_tx_eqfs_q;
pipe_tx_eqlf_qq <= #TCQ pipe_tx_eqlf_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_qq;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
// Default to zero pipeline stages if PIPE_PIPELINE_STAGES != 0,1,2
else begin
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_i;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_i;
end
endgenerate
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: linebuf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.1 Build 190 01/19/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module linebuf (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [23:0] data;
input [11:0] rdaddress;
input rdclock;
input [11:0] wraddress;
input wrclock;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "98304"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL "rdaddress[11..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright (c) 2013, The DDK Project
* Dmitry Nedospasov <dmitry at nedos dot net>
* Thorsten Schroeder <ths at modzero dot ch>
*
* All rights reserved.
*
* This file is part of Die Datenkrake (DDK).
*
* "THE BEER-WARE LICENSE" (Revision 42):
* <dmitry at nedos dot net> and <ths at modzero dot ch> wrote this file. As
* long as you retain this notice you can do whatever you want with this stuff.
* If we meet some day, and you think this stuff is worth it, you can buy us a
* beer in return. Die Datenkrake Project.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE DDK PROJECT BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
`timescale 1 ns/1 ps
`include "reg_defs.v"
module krake_port_tb();
reg tb_clk;
reg tb_rst;
reg tb_en;
wire tb_dout;
reg clka;
reg clkb;
reg clkc;
reg clkd;
reg tb_we_o;
reg [7:0] tb_dat_o;
reg [4:0] tb_adr_o;
reg tb_stb_o;
wire [7:0] tb_dat_i;
wire tb_ack_i;
reg [7:0] tb_cnt_a;
reg [7:0] tb_cnt_d;
wire [5:0] ch_in;
wire [5:0] ch_out;
wire [5:0] ch_oe;
krake_port_tx2 krake_porti(
.clk_i(tb_clk),
.rst_i(tb_rst),
.ack_o(tb_ack_i),
.dat_i(tb_dat_o),
.adr_i(tb_adr_o),
.dat_o(tb_dat_i),
.stb_i(tb_stb_o),
.we_i(tb_we_o),
.ch_in(ch_in),
.ch_out(ch_out),
.ch_oe(ch_oe),
.clka(clka),
.clkb(clkb),
.clkc(clkc),
.clkd(clkd));
assign ch_in[0] = ch_oe[0] ? ch_out[0] : 1'bz;
assign ch_in[1] = ch_oe[1] ? ch_out[1] : 1'bz;
assign ch_in[2] = ch_oe[2] ? ch_out[2] : 1'bz;
assign ch_in[3] = ch_oe[3] ? ch_out[3] : 1'bz;
assign ch_in[4] = ch_oe[4] ? ch_out[4] : 1'bz;
assign ch_in[5] = ch_oe[5] ? ch_out[5] : 1'bz;
//end
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_en <= 1'b0;
clka <= 1'b0;
clkb <= 1'b0;
clkc <= 1'b0;
clkd <= 1'b0;
#5 tb_rst <= 1'b1;
#20 tb_rst <= 1'b0;
tb_en <= 1'b1;
end
// Generate clock (25MHz)
always
begin
#20 clka <= ~clka;
end
// Generate clock (12.5MHz)
always
begin
#40 clkb <= ~clkb;
end
// Generate clock (6.25MHz)
always
begin
#80 clkc <= ~clkc;
end
// Generate clock (3.125MHz)
always
begin
#160 clkd <= ~clkd;
end
// Generate a system clock (50MHz)
always
begin
#10 tb_clk <= ~tb_clk;
end
task wb_write;
input [7:0] adr_o;
input [7:0] dat_o;
begin
@(posedge tb_clk);
tb_stb_o <= 1'b1;
tb_we_o <= 1'b1;
tb_dat_o <= dat_o;
tb_adr_o <= adr_o;
@(posedge tb_clk);
tb_stb_o <= 1'b0;
@(posedge tb_clk);
if(!tb_ack_i)
begin
$display("Write failed: 0x%02H, 0x%02H", tb_adr_o, tb_dat_o);
end
end
endtask
reg [7:0] read_data;
task wb_read;
input [7:0] adr_o;
begin
@(posedge tb_clk);
tb_stb_o <= 1'b1;
tb_we_o <= 1'b0;
tb_adr_o <= adr_o;
@(posedge tb_clk);
tb_stb_o <= 1'b0;
@(posedge tb_clk);
read_data <= tb_dat_i;
if(!tb_ack_i)
begin
$display("Read failed: 0x%02H, 0x%02H", tb_adr_o, tb_dat_i);
end
end
endtask
always @(posedge tb_rst)
begin
tb_dat_o <= 8'h00;
tb_we_o <= 1'b0;
tb_adr_o <= 4'd0;
tb_cnt_a <= 8'd0;
tb_cnt_d <= 8'd0;
end
initial
begin
wait(tb_en)
// (r/w) Peripheral configuration register
#1 wb_read(`UART_STATUS);
#1 if(read_data != 8'h01) $stop;
#1 wb_write(`UART_DATAREG, 8'b10101010);
#1 wb_read(`UART_DATAREG);
#1 if(read_data != 8'b10101010) $stop;
#1 wb_write(`UART_STATUS, 8'h01);
#1 wb_read(`UART_STATUS);
wait (krake_porti.tx_rdy == 1);
#1 wb_read(`UART_STATUS);
#1 if(read_data != 8'b00000001) $stop;
#1 wb_write(`UART_DATAREG, 8'b00001111);
#1 wb_write(`UART_STATUS, 8'b00000001);
#1 wb_read(`UART_STATUS);
wait (krake_porti.tx_rdy == 1);
#1 wb_read(`UART_STATUS);
#1 if(read_data != 8'b00000001) $stop;
//#1 wb_read(`PORT_CONF);
//#1 wb_write(`PORT_CONF,8'hff);
//#1 wb_read(`PORT_CONF);
//#1 if(read_data != 8'h3f) $stop;
// (r/w) Port status
//#1 wb_read(`PORT_STATUS);
//#1 wb_write(`PORT_STATUS,8'hff);
//#1 wb_read(`PORT_STATUS);
//#1 if(read_data != 8'h3f) $stop;
// (r/w) Output clocks
//#1 wb_read(`PORT_PIN0_CONF);
//#1 wb_write(`PORT_PIN0_CONF,8'h00);
//#1 wb_read(`PORT_PIN0_CONF);
//#1 if(read_data != 8'h00) $stop;
// (r/w) Output clocks
//#1 wb_read(`PORT_PIN1_CONF);
//#1 wb_write(`PORT_PIN1_CONF,8'h01);
//#1 wb_read(`PORT_PIN1_CONF);
//#1 if(read_data != 8'h01) $stop;
// (r/w) Output clocks
//#1 wb_read(`PORT_PIN2_CONF);
//#1 wb_write(`PORT_PIN2_CONF,8'h03);
//#1 wb_read(`PORT_PIN2_CONF);
//#1 if(read_data != 8'h03) $stop;
// (r/w) Output clocks
//#1 wb_read(`PORT_PIN3_CONF);
//#1 wb_write(`PORT_PIN3_CONF,8'h07);
//#1 wb_read(`PORT_PIN3_CONF);
//#1 if(read_data != 8'h07) $stop;
// (r/w) Output clocks
//#1 wb_read(`PORT_PIN4_CONF);
//#1 wb_write(`PORT_PIN4_CONF,8'h0f);
//#1 wb_read(`PORT_PIN4_CONF);
//#1 if(read_data != 8'h0f) $stop;
// (r/w) Output clocks
//#1 wb_read(`PORT_PIN5_CONF);
//#1 wb_write(`PORT_PIN5_CONF,8'h1f);
//#1 wb_read(`PORT_PIN5_CONF);
//#1 if(read_data != 8'h1f) $stop;
//$display("Testbench completed successfully!");
//$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A32OI_PP_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_PP_SYMBOL_V
|
/*!
* <b>Module:</b>oob_dev
* @file oob_dev.v
* @date 2015-07-11
* @author Alexey
*
* @brief sata oob unit implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* oob_dev.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob_dev.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
/*
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
* data iface width or to change RXRATE/TXRATE)
*/
// All references to doc = to SerialATA_Revision_2_6_Gold.pdf
module oob_dev #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 2, // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
parameter TEST_ELIDLE = 2, // test transmitting eidle between data rates (number of times)
parameter ELIDLE_DELAY = 'h28, // 80, // counter cycles
parameter ELIDLE_DURATION = 'h80 // counter cycles
)
(
// sata clk = usrclk2
input wire clk,
// reset oob
input wire rst,
input wire gtx_ready,
// oob responses
input wire rxcominitdet_in,
input wire rxcomwakedet_in,
input wire rxelecidle_in,
// oob issues
output reg txcominit,
output reg txcomwake,
output reg txelecidle,
output wire txpcsreset_req,
input wire recal_tx_done,
// output data stream to gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out,
// input data from gtx
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
output wire link_up
);
localparam STATE_RESET = 0;
localparam STATE_COMINIT = 1;
localparam STATE_AWAITCOMWAKE = 2;
localparam STATE_AWAITNOCOMWAKE = 3;
localparam STATE_CALIBRATE = 4;
localparam STATE_COMWAKE = 5;
localparam STATE_RECAL = 55;
localparam STATE_SENDALIGN = 6;
localparam STATE_EIDLE_RATE = 65;
localparam STATE_READY = 7;
localparam STATE_PARTIAL = 8;
localparam STATE_SLUMBER = 9;
localparam STATE_REDUCESPEED = 10;
localparam STATE_ERROR = 11;
reg [31:0] rate_change_cntr;
reg was_txelecidle;
reg [9:0] state;
wire retry_interval_elapsed;
wire wait_interval_elapsed;
wire elidle_rate_delay_elapsed;
wire elidle_rate_duration_elapsed;
wire nocomwake;
wire [31:0] align;
wire [31:0] sync;
assign align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // {D27.3, D10.2, D10.2, K28.5}
assign sync = {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}; // {D21.5, D21.5, D21.4, K28.3}
reg [31:0] nocomwake_timer;
assign nocomwake = nocomwake_timer == 32'd38;
always @ (posedge clk)
nocomwake_timer <= rst | rxcomwakedet_in ? 32'h0 : nocomwake ? nocomwake_timer : nocomwake_timer + 1'b1;
reg [31:0] retry_timer;
assign retry_interval_elapsed = retry_timer == 32'd1000;
always @ (posedge clk)
retry_timer <= rst | ~(state == STATE_AWAITCOMWAKE) ? 32'h0 : retry_timer + 1'b1;
reg [31:0] wait_timer;
assign wait_interval_elapsed = wait_timer == 32'd4096;
assign elidle_rate_delay_elapsed = wait_timer == ELIDLE_DELAY;
always @ (posedge clk)
wait_timer <= rst | ~(state == STATE_SENDALIGN) ? 32'h0 : wait_timer + 1'b1;
reg [31:0] elidle_timer;
assign elidle_rate_duration_elapsed = elidle_timer == ELIDLE_DURATION;
always @ (posedge clk)
elidle_timer <= rst | ~(state == STATE_EIDLE_RATE) ? 32'h0 : elidle_timer + 1'b1;
always @ (posedge clk) begin
was_txelecidle <= txelecidle;
if (rst) rate_change_cntr <= 0;
else if (txelecidle && !was_txelecidle) rate_change_cntr <= rate_change_cntr + 1;
end
reg [31:0] data;
reg [3:0] isk;
assign link_up = state == STATE_READY;
assign txdata_out = data;
assign txcharisk_out = isk;
// buf inputs from gtx
reg rxcominitdet;
reg rxcomwakedet;
reg rxelecidle;
reg [31:0] rxdata;
reg [3:0] rxcharisk;
always @ (posedge clk)
begin
rxcominitdet <= rxcominitdet_in;
rxcomwakedet <= rxcomwakedet_in;
rxelecidle <= rxelecidle_in;
rxdata <= rxdata_in;
rxcharisk <= rxcharisk_in;
end
reg [9:0] txelecidle_cnt;
wire aligndet;
wire syncdet;
assign aligndet = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}
assign syncdet = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}
assign txpcsreset_req = state == STATE_RECAL & (txelecidle_cnt == 10'd160);
always @ (posedge clk)
if (rst | (~gtx_ready & ~(state == STATE_RECAL)))
begin
state <= STATE_RESET;
txelecidle <= 1'b1;
txcominit <= 1'b0;
txcomwake <= 1'b0;
txelecidle_cnt <= 10'h0;
end
else
case (state)
STATE_RESET:
begin
if (rxcominitdet) begin
txelecidle_cnt <= 10'h0;
state <= STATE_COMINIT;
txelecidle <= 1'b1;
txcominit <= 1'b0;
txcomwake <= 1'b0;
end
end
STATE_COMINIT:
begin
state <= STATE_AWAITCOMWAKE;
txcominit <= 1'b1;
end
STATE_AWAITCOMWAKE:
begin
txcominit <= 1'b0;
if (rxcomwakedet)
state <= STATE_AWAITNOCOMWAKE;
else
if (retry_interval_elapsed)
state <= STATE_RESET;
else
state <= STATE_AWAITCOMWAKE;
end
STATE_AWAITNOCOMWAKE:
begin
if (nocomwake)
begin
state <= STATE_CALIBRATE;
end
end
STATE_CALIBRATE:
begin
state <= STATE_COMWAKE;
end
STATE_COMWAKE:
begin
txcomwake <= 1'b1;
state <= STATE_RECAL;
txelecidle_cnt <= 10'h0;
end
STATE_RECAL:
begin
data <= align;
isk <= 4'h1;
txcomwake <= 1'b0;
// txcomwake period = 213.333 ns times let's say 10 pulses => 2133.333 ns = 160 cycles of 75Mhz
if (txelecidle_cnt == 10'd160) begin
txelecidle <= 1'b0;
end
else begin
txelecidle_cnt <= txelecidle_cnt + 1'b1;
end
if (recal_tx_done) begin
state <= STATE_SENDALIGN;
end
end
STATE_SENDALIGN:
begin
txelecidle <= 1'b0;
data <= align;
isk <= 4'h1;
if (aligndet)
state <= STATE_READY;
else
if (wait_interval_elapsed)
state <= STATE_ERROR;
else if ((rate_change_cntr < TEST_ELIDLE) && elidle_rate_delay_elapsed)
state <= STATE_EIDLE_RATE;
else
state <= STATE_SENDALIGN;
end
STATE_EIDLE_RATE:
begin
txelecidle <= 1'b1;
data <= 0; // align; // 'bz;
isk <= 4'h1;
if (elidle_rate_duration_elapsed)
state <= STATE_SENDALIGN;
end
STATE_READY:
begin
txelecidle <= 1'b0;
data <= sync;
isk <= 4'h1;
if (rxelecidle_in)
state <= STATE_ERROR;
end
STATE_ERROR:
begin
txelecidle <= 1'b0;
state <= STATE_RESET;
end
endcase
/*
// 873.8 us error timer
// = 2621400 SATA2 serial ticks (period = 0.000333 us)
// = 131070 ticks @ 150Mhz
// = 65535 ticks @ 75Mhz
localparam [19:0] CLK_TO_TIMER_CONTRIB = CLK_SPEED_GRADE == 1 ? 20'h4 :
CLK_SPEED_GRADE == 2 ? 20'h2 :
CLK_SPEED_GRADE == 4 ? 20'h1 : 20'h1;
`ifdef SIMULATION
localparam [19:0] TIMER_LIMIT = 19'd200;
`else
localparam [19:0] TIMER_LIMIT = 19'd262140;
`endif
reg [19:0] timer;
wire timer_clr;
wire timer_fin;
// latching inputs from gtx
reg rxcominitdet;
reg rxcomwakedet;
reg rxelecidle;
reg [DATA_BYTE_WIDTH*8 - 1:0] rxdata;
reg [DATA_BYTE_WIDTH - 1:0] rxcharisk;
// primitives detection
wire detected_alignp;
wire detected_syncp;
// fsm, doc p265,266
wire state_idle;
reg state_wait_cominit;
reg state_wait_comwake;
reg state_wait_align;
reg state_wait_synp;
reg state_wait_linkup;
reg state_error;
wire set_wait_cominit;
wire set_wait_comwake;
wire set_wait_align;
wire set_wait_synp;
wire set_wait_linkup;
wire set_error;
wire clr_wait_cominit;
wire clr_wait_comwake;
wire clr_wait_align;
wire clr_wait_synp;
wire clr_wait_linkup;
wire clr_error;
assign state_idle = ~state_wait_cominit & ~state_wait_comwake & ~state_wait_align & ~state_wait_synp & ~state_wait_linkup & ~state_error;
always @ (posedge clk)
begin
state_wait_cominit <= (state_wait_cominit | set_wait_cominit) & ~clr_wait_cominit & ~rst;
state_wait_comwake <= (state_wait_comwake | set_wait_comwake) & ~clr_wait_comwake & ~rst;
state_wait_align <= (state_wait_align | set_wait_align ) & ~clr_wait_align & ~rst;
state_wait_synp <= (state_wait_synp | set_wait_synp ) & ~clr_wait_synp & ~rst;
state_wait_linkup <= (state_wait_linkup | set_wait_linkup ) & ~clr_wait_linkup & ~rst;
state_error <= (state_error | set_error ) & ~clr_error & ~rst;
end
assign set_wait_cominit = state_idle & oob_start & ~cominit_req;
assign set_wait_comwake = state_idle & cominit_req & cominit_allow | state_wait_cominit & rxcominitdet;
assign set_wait_align = state_wait_comwake & rxcomwakedet;
assign set_wait_synp = state_wait_align & detected_alignp;
assign set_wait_linkup = state_wait_synp & detected_syncp;
assign set_error = timer_fin & (state_wait_cominit | state_wait_comwake | state_wait_align | state_wait_synp);
assign clr_wait_cominit = set_wait_comwake | set_error;
assign clr_wait_comwake = set_wait_align | set_error;
assign clr_wait_align = set_wait_synp | set_error;
assign clr_wait_synp = set_wait_linkup | set_error;
assign clr_wait_linkup = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives
assign clr_error = state_error;
// waiting timeout timer
assign timer_fin = timer == TIMER_LIMIT;
assign timer_clr = set_error | state_error | state_idle;
always @ (posedge clk)
timer <= rst | timer_clr ? 20'h0 : timer + CLK_TO_TIMER_CONTRIB;
// something is wrong with speed grades if the host cannot lock to device's alignp stream
assign oob_incompatible = state_wait_align & set_error;
// oob sequence is done, everything is okay
assign oob_done = set_wait_linkup;
// noone responds to cominits
assign oob_silence = set_error & state_wait_cominit;
// other timeouts
assign oob_error = set_error & ~oob_silence & ~oob_incompatible;
// obvioud
assign oob_busy = ~state_idle;
// set gtx controls
reg txelecidle_r;
always @ (posedge clk)
txelecidle_r <= rst ? 1'b1 : clr_wait_cominit ? 1'b0 : set_wait_cominit ? 1'b1 : txelecidle_r;
assign txcominit = set_wait_cominit;
assign txcomwake = set_wait_comwake;
assign txelecidle = set_wait_cominit | txelecidle_r;
// indicate if link up condition was made
assign link_up = clr_wait_linkup;
// link goes down when line is idle
reg rxelecidle_r;
reg rxelecidle_rr;
always @ (posedge clk)
begin
rxelecidle_rr <= rxelecidle_r;
rxelecidle_r <= rxelecidle;
end
assign link_down = rxelecidle_rr;
// indicate that device is requesting for oob
reg cominit_req_r;
wire cominit_req_set;
assign cominit_req_set = state_idle & rxcominitdet;
always @ (posedge clk)
cominit_req_r <= (cominit_req_r | cominit_req_set) & ~(cominit_allow & cominit_req) & ~rst;
assign cominit_req = cominit_req_set | cominit_req_r;
// detect which primitives sends the device after comwake was done
generate
if (DATA_BYTE_WIDTH == 2)
begin
reg detected_alignp_f;
always @ (posedge clk)
detected_alignp_f <= rst | ~state_wait_align ? 1'b0 :
~|(rxdata ^ {8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 2'b01); // {D10.2, K28.5}
assign detected_alignp = detected_alignp_f & ~|(rxdata ^ {8'b01111011, 8'b01001010}) & ~|(rxcharisk ^ 2'b00); // {D27.3, D10.2}
reg detected_syncp_f;
always @ (posedge clk)
detected_syncp_f <= rst | ~state_wait_synp ? 1'b0 :
~|(rxdata ^ {8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 2'b01); // {D21.4, K28.3}
assign detected_syncp = detected_syncp_f & ~|(rxdata ^ {8'b10110101, 8'b10110101}) & ~|(rxcharisk ^ 2'b00); // {D21.5, D21.5}
end
else
if (DATA_BYTE_WIDTH == 4)
begin
assign detected_alignp = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}
end
else
if (DATA_BYTE_WIDTH == 8)
begin
assign detected_alignp = ~|(rxdata ^ {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}) & ~|(rxcharisk ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5}
assign detected_syncp = ~|(rxdata ^ {2{8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}}) & ~|(rxcharisk ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3}
end
else
begin
always @ (posedge clk)
begin
$display("%m oob module works only with 16/32/64 gtx input data width");
$finish;
end
end
endgenerate
// buf inputs from gtx
always @ (posedge clk)
begin
rxcominitdet <= rxcominitdet_in;
rxcomwakedet <= rxcomwakedet_in;
rxelecidle <= rxelecidle_in;
rxdata <= rxdata_in;
rxcharisk <= rxcharisk_in;
end
// set data outputs to upper levels
assign rxdata_out = rxdata;
assign rxcharisk_out = rxcharisk;
// as depicted @ doc, p264, figure 163, have to insert D10.2 and align primitives after
// getting comwake from device
reg [DATA_BYTE_WIDTH*8 - 1:0] txdata;
reg [DATA_BYTE_WIDTH - 1:0] txcharisk;
wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_d102;
wire [DATA_BYTE_WIDTH - 1:0] txcharisk_d102;
wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_align;
wire [DATA_BYTE_WIDTH - 1:0] txcharisk_align;
always @ (posedge clk)
begin
txdata <= state_wait_align ? txdata_d102 :
state_wait_synp ? txdata_align : txdata_in;
txcharisk <= state_wait_align ? txcharisk_d102 :
state_wait_synp ? txcharisk_align : txcharisk_in;
end
// Continious D10.2 primitive
assign txcharisk_d102 = {DATA_BYTE_WIDTH{1'b0}};
assign txdata_d102 = {DATA_BYTE_WIDTH{8'b01001010}};
// Align primitive: K28.5 + D10.2 + D10.2 + D27.3
generate
if (DATA_BYTE_WIDTH == 2)
begin
reg align_odd;
always @ (posedge clk)
align_odd <= rst | ~state_wait_synp ? 1'b0 : ~align_odd;
assign txcharisk_align = align_odd ? 2'b01 : 2'b00;
assign txdata_align = align_odd ? {8'b01001010, 8'b10111100} : // {D10.2, K28.5}
{8'b01111011, 8'b01001010}; // {D27.3, D10.2}
end
else
if (DATA_BYTE_WIDTH == 4)
begin
assign txcharisk_align = 4'h1;
assign txdata_align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // {D27.3, D10.2, D10.2, K28.5}
end
else
if (DATA_BYTE_WIDTH == 8)
begin
assign txcharisk_align = 8'h11;
assign txdata_align = {2{8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}}; // 2x{D27.3, D10.2, D10.2, K28.5}
end
else
always @ (posedge clk)
begin
$display("%m oob module works only with 16/32/64 gtx input data width");
$finish;
end
endgenerate
// set data outputs to gtx
assign txdata_out = txdata;
assign txcharisk_out = txcharisk;
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_TB_V
`define SKY130_FD_SC_HVL__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_2_V
`define SKY130_FD_SC_HD__A211O_2_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211o_2 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_2_V
|
`timescale 1ns / 1ps
/* gayle.v
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF328 (Terrible Fire CD32 RAM + IDE BOARD)
TF530 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF530. If not, see <http://www.gnu.org/licenses/>.
*/
module gayle(
input CLKCPU,
input RESET,
input DS,
input CS,
input RW,
input IDE_INT,
output INT2,
input A18,
input [1:0] A,
input D7,
output DOUT7
);
parameter GAYLE_ID_VAL = 4'hd;
reg data_out = 1'b0;
reg [3:0] gayleid = GAYLE_ID_VAL;
reg intena = 1'b0;
reg intlast = 1'b0;
reg ds_d = 1'b0;
// $DE1000
localparam GAYLE_ID_RD = {1'b1,2'h1,1'b1};
localparam GAYLE_ID_WR = {1'b1,2'h1,1'b0};
// $DA8000
localparam GAYLE_STAT_RD = {3'h0,1'b1};
localparam GAYLE_STAT_WR = {3'h0,4'h0,1'b0};
// $DA9000
localparam GAYLE_INTCHG_RD = {3'h1,1'b1};
localparam GAYLE_INTCHG_WR = {3'h1,1'b0};
// $DAA000
localparam GAYLE_INTENA_RD = {3'h2,1'b1};
localparam GAYLE_INTENA_WR = {3'h2,1'b0};
wire INT_CHNG;
wire INT_CHNG_ACCESS = {CS,A18,A,RW} != {1'b0,GAYLE_INTCHG_WR};
FDCPE #(.INIT(1'b1))
INT_CHNG_FF (
.Q(INT_CHNG), // Data output
.C(~DS), // Clock input
.CE(~INT_CHNG_ACCESS), // CLOCK ENABLE
.CLR(~RESET), // Asynchronous clear input
.D(D7 & INT_CHNG), // Data input
.PRE(IDE_INT != intlast) // Asynchronous set input
);
always @(posedge CLKCPU) begin
intlast <= IDE_INT;
ds_d <= DS;
if (RESET == 1'b0) begin
// resetting to low ensures that the next cycle
// after reset is disasserted is not a bus cycle.
intena <= 1'b0;
gayleid <= 4'hD;
end else begin
if ((CS | DS | ~ds_d) == 1'b0) begin
case ({A18,A,RW})
GAYLE_STAT_RD: data_out <= IDE_INT;
GAYLE_INTCHG_RD: data_out <= INT_CHNG;
GAYLE_ID_RD: begin
data_out <= gayleid[3];
gayleid <= {gayleid[2:0],1'b0};
end
GAYLE_ID_WR: gayleid <= 4'hD;
GAYLE_INTENA_RD: data_out <= INT_CHNG;
GAYLE_INTENA_WR: intena <= D7;
default: data_out <= 'b0;
endcase
end
end
end
assign INT2 = INT_CHNG & intena;
assign DOUT7 = data_out;
endmodule
|
module spi_clock_generator(
//CLK
// i_clk is the system clock (10-200MHz)
input i_clk,
//RST
// i_reset is the system reset. This is a active high signal.
// '1' : reset is active
input i_reset,
//Controll inputs from registers
input i_spr0,
input i_spr1,
input i_cpol,
input i_cpha,
input i_mstr,
// Controll output to other logic
// o_sclk: This is the SPI clock. The polarity based on the i_cpol
// The frequency is derived by i_spr0 and i_spr1
output o_sclk,
// o_sclk_rising_edge: is active one sys clk long at the rising edge of
// the sclk.
output o_sclk_rising_edge,
// o_sclk_falling_edge: is active one sys clk long at the falling edge of
// the sclk.
output o_sclk_falling_edge,
// o_sample_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
output o_sample_spi_data,
// o_setup_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
// Note that this is the alter edge than o_sample_spi_data
output o_setup_spi_data
);
// The spi clock counter. The max value is depends on the frequency which
// derived by i_spr0 and i_spr1
reg [6:0] q_spi_sclk_cntr;
wire w_sclk_internal;
wire [1:0]w_clk_select;
reg q_sclk_internal_d1; //alwaysbe reg, d1->eggyel kesleltetett
wire w_sclk_rising_edge_internal;
wire w_sclk_falling_edge_internal;
wire w_sample_spi_data_internal;
wire w_setup_spi_data;
wire [1:0] w_sample_setup_select;
always @(posedge i_clk) begin : SCLK_CNTR
if (i_reset) begin
q_spi_sclk_cntr <= 7'b0 ;
end else begin
q_spi_sclk_cntr <= q_spi_sclk_cntr + 1;
end
end
assign w_clk_select={i_spr0,i_spr1};
assign w_sclk_internal = (w_clk_select==0) ? q_spi_sclk_cntr[1] :
(w_clk_select==1) ? q_spi_sclk_cntr[3] :
(w_clk_select==2) ? q_spi_sclk_cntr[5] :
(w_clk_select==3) ? q_spi_sclk_cntr[6] :
0; // soha nem jut ide
assign o_sclk = w_sclk_internal;
always @(posedge i_clk) begin : SCLK_EDGE_DETECT
if (i_reset) begin
q_sclk_internal_d1<=0;
end
else begin
q_sclk_internal_d1 <=w_sclk_internal;
end
end
//felfuto el
assign w_sclk_rising_edge_internal = (w_sclk_internal > q_sclk_internal_d1) ? 1:
0; //ha nagyobb az aktualis, mint az elozo ->felfuto
assign o_sclk_rising_edge = w_sclk_rising_edge_internal;
//lefuto el
assign w_sclk_falling_edge_internal = (w_sclk_internal < q_sclk_internal_d1) ? 1:
0; //ha kisebb ->lefuto
assign o_sclk_falling_edge = w_sclk_falling_edge_internal;
assign w_sample_setup_select={i_cpol,i_cpha};
//o_sample_spi_data
assign w_sample_spi_data_internal = (w_sample_setup_select==0) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==1) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==2) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==3) ? w_sclk_rising_edge_internal:
0;
assign o_sample_spi_data = w_sample_spi_data_internal;
//o_setup_spi_data
assign w_setup_spi_data = (w_sample_setup_select==0) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==1) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==2) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==3) ? w_sclk_falling_edge_internal:
0;
assign o_setup_spi_data = w_setup_spi_data;
// -- TODO --
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_TB_V
`define SKY130_FD_SC_HVL__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_1_V
`define SKY130_FD_SC_HS__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Mon Oct 31 15:36:48 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2v2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n7086, NaN_reg, cordic_result_31_, ready_add_subt,
underflow_flag_mult, overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1,
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1236, n1237, n1238, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1288, n1289, n1290, n1291, n1292, n1293,
n1295, n1296, n1297, n1298, n1299, n1300, n1302, n1303, n1304, n1305,
n1306, n1307, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1481, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1911, n1912, n1914, n1915, n1916, n1917, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1930, n1932, n1933, n1934,
n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944,
n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954,
n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2191, mult_x_311_n37,
mult_x_311_n36, mult_x_311_n30, mult_x_311_n29, mult_x_311_n23,
mult_x_311_n22, mult_x_311_n18, mult_x_311_n17, mult_x_311_n15,
mult_x_311_n14, mult_x_309_n37, mult_x_309_n36, mult_x_309_n30,
mult_x_309_n29, mult_x_309_n23, mult_x_309_n22, mult_x_309_n18,
mult_x_309_n17, mult_x_309_n15, mult_x_309_n14,
DP_OP_26J1_129_1325_n18, DP_OP_26J1_129_1325_n17,
DP_OP_26J1_129_1325_n16, DP_OP_26J1_129_1325_n15,
DP_OP_26J1_129_1325_n14, DP_OP_26J1_129_1325_n8,
DP_OP_26J1_129_1325_n7, DP_OP_26J1_129_1325_n6,
DP_OP_26J1_129_1325_n5, DP_OP_26J1_129_1325_n4,
DP_OP_26J1_129_1325_n3, DP_OP_26J1_129_1325_n2,
DP_OP_26J1_129_1325_n1, DP_OP_234J1_132_4955_n22,
DP_OP_234J1_132_4955_n21, DP_OP_234J1_132_4955_n20,
DP_OP_234J1_132_4955_n19, DP_OP_234J1_132_4955_n18,
DP_OP_234J1_132_4955_n17, DP_OP_234J1_132_4955_n16,
DP_OP_234J1_132_4955_n15, DP_OP_234J1_132_4955_n9,
DP_OP_234J1_132_4955_n8, DP_OP_234J1_132_4955_n7,
DP_OP_234J1_132_4955_n6, DP_OP_234J1_132_4955_n5,
DP_OP_234J1_132_4955_n4, DP_OP_234J1_132_4955_n3,
DP_OP_234J1_132_4955_n2, DP_OP_234J1_132_4955_n1, intadd_0_A_7_,
intadd_0_A_6_, intadd_0_A_5_, intadd_0_A_4_, intadd_0_A_3_,
intadd_0_A_2_, intadd_0_A_1_, intadd_0_A_0_, intadd_0_B_7_,
intadd_0_B_6_, intadd_0_B_5_, intadd_0_B_4_, intadd_0_B_3_,
intadd_0_B_2_, intadd_0_B_1_, intadd_0_B_0_, intadd_0_CI,
intadd_0_SUM_7_, intadd_0_SUM_6_, intadd_0_SUM_5_, intadd_0_SUM_4_,
intadd_0_SUM_3_, intadd_0_SUM_2_, intadd_0_SUM_1_, intadd_0_SUM_0_,
intadd_0_n8, intadd_0_n7, intadd_0_n6, intadd_0_n5, intadd_0_n4,
intadd_0_n3, intadd_0_n2, intadd_0_n1, intadd_1_A_7_, intadd_1_A_0_,
intadd_1_B_7_, intadd_1_B_6_, intadd_1_B_1_, intadd_1_B_0_,
intadd_1_CI, intadd_1_n8, intadd_1_n7, intadd_1_n6, intadd_1_n5,
intadd_1_n4, intadd_1_n3, intadd_1_n2, intadd_1_n1, intadd_2_A_7_,
intadd_2_A_6_, intadd_2_A_5_, intadd_2_A_4_, intadd_2_A_3_,
intadd_2_A_2_, intadd_2_A_1_, intadd_2_A_0_, intadd_2_B_7_,
intadd_2_B_6_, intadd_2_B_5_, intadd_2_B_4_, intadd_2_B_3_,
intadd_2_B_2_, intadd_2_B_1_, intadd_2_B_0_, intadd_2_CI,
intadd_2_SUM_7_, intadd_2_SUM_6_, intadd_2_SUM_5_, intadd_2_SUM_4_,
intadd_2_SUM_3_, intadd_2_SUM_2_, intadd_2_SUM_1_, intadd_2_SUM_0_,
intadd_2_n8, intadd_2_n7, intadd_2_n6, intadd_2_n5, intadd_2_n4,
intadd_2_n3, intadd_2_n2, intadd_2_n1, intadd_3_A_0_, intadd_3_B_6_,
intadd_3_B_1_, intadd_3_B_0_, intadd_3_CI, intadd_3_n7, intadd_3_n6,
intadd_3_n5, intadd_3_n4, intadd_3_n3, intadd_3_n2, intadd_3_n1,
intadd_4_CI, intadd_4_SUM_2_, intadd_4_SUM_1_, intadd_4_SUM_0_,
intadd_4_n3, intadd_4_n2, intadd_4_n1, intadd_5_CI, intadd_5_SUM_2_,
intadd_5_SUM_1_, intadd_5_SUM_0_, intadd_5_n3, intadd_5_n2,
intadd_5_n1, intadd_6_CI, intadd_6_SUM_2_, intadd_6_SUM_1_,
intadd_6_SUM_0_, intadd_6_n3, intadd_6_n2, intadd_6_n1,
DP_OP_500J1_126_2852_n188, DP_OP_500J1_126_2852_n187,
DP_OP_500J1_126_2852_n186, DP_OP_500J1_126_2852_n185,
DP_OP_500J1_126_2852_n181, DP_OP_500J1_126_2852_n180,
DP_OP_500J1_126_2852_n179, DP_OP_500J1_126_2852_n178,
DP_OP_500J1_126_2852_n174, DP_OP_500J1_126_2852_n172,
DP_OP_500J1_126_2852_n171, DP_OP_500J1_126_2852_n170,
DP_OP_500J1_126_2852_n165, DP_OP_500J1_126_2852_n164,
DP_OP_500J1_126_2852_n162, DP_OP_500J1_126_2852_n161,
DP_OP_500J1_126_2852_n158, DP_OP_500J1_126_2852_n157,
DP_OP_500J1_126_2852_n155, DP_OP_500J1_126_2852_n154,
DP_OP_500J1_126_2852_n151, DP_OP_500J1_126_2852_n150,
DP_OP_500J1_126_2852_n147, DP_OP_500J1_126_2852_n141,
DP_OP_500J1_126_2852_n138, DP_OP_500J1_126_2852_n137,
DP_OP_500J1_126_2852_n136, DP_OP_500J1_126_2852_n135,
DP_OP_500J1_126_2852_n134, DP_OP_500J1_126_2852_n132,
DP_OP_500J1_126_2852_n131, DP_OP_500J1_126_2852_n130,
DP_OP_500J1_126_2852_n129, DP_OP_500J1_126_2852_n128,
DP_OP_500J1_126_2852_n127, DP_OP_500J1_126_2852_n126,
DP_OP_500J1_126_2852_n125, DP_OP_500J1_126_2852_n124,
DP_OP_500J1_126_2852_n123, DP_OP_500J1_126_2852_n122,
DP_OP_500J1_126_2852_n121, DP_OP_500J1_126_2852_n120,
DP_OP_500J1_126_2852_n119, DP_OP_500J1_126_2852_n118,
DP_OP_500J1_126_2852_n117, DP_OP_500J1_126_2852_n116,
DP_OP_500J1_126_2852_n115, DP_OP_500J1_126_2852_n112,
DP_OP_500J1_126_2852_n111, DP_OP_500J1_126_2852_n110,
DP_OP_500J1_126_2852_n109, DP_OP_500J1_126_2852_n108,
DP_OP_500J1_126_2852_n107, DP_OP_500J1_126_2852_n106,
DP_OP_500J1_126_2852_n105, DP_OP_500J1_126_2852_n104,
DP_OP_500J1_126_2852_n103, DP_OP_500J1_126_2852_n102,
DP_OP_500J1_126_2852_n101, DP_OP_500J1_126_2852_n100,
DP_OP_502J1_128_2852_n188, DP_OP_502J1_128_2852_n187,
DP_OP_502J1_128_2852_n186, DP_OP_502J1_128_2852_n185,
DP_OP_502J1_128_2852_n181, DP_OP_502J1_128_2852_n180,
DP_OP_502J1_128_2852_n179, DP_OP_502J1_128_2852_n178,
DP_OP_502J1_128_2852_n174, DP_OP_502J1_128_2852_n172,
DP_OP_502J1_128_2852_n171, DP_OP_502J1_128_2852_n170,
DP_OP_502J1_128_2852_n165, DP_OP_502J1_128_2852_n164,
DP_OP_502J1_128_2852_n162, DP_OP_502J1_128_2852_n161,
DP_OP_502J1_128_2852_n158, DP_OP_502J1_128_2852_n157,
DP_OP_502J1_128_2852_n155, DP_OP_502J1_128_2852_n154,
DP_OP_502J1_128_2852_n151, DP_OP_502J1_128_2852_n150,
DP_OP_502J1_128_2852_n147, DP_OP_502J1_128_2852_n141,
DP_OP_502J1_128_2852_n138, DP_OP_502J1_128_2852_n137,
DP_OP_502J1_128_2852_n136, DP_OP_502J1_128_2852_n135,
DP_OP_502J1_128_2852_n134, DP_OP_502J1_128_2852_n132,
DP_OP_502J1_128_2852_n131, DP_OP_502J1_128_2852_n130,
DP_OP_502J1_128_2852_n129, DP_OP_502J1_128_2852_n128,
DP_OP_502J1_128_2852_n127, DP_OP_502J1_128_2852_n126,
DP_OP_502J1_128_2852_n125, DP_OP_502J1_128_2852_n124,
DP_OP_502J1_128_2852_n123, DP_OP_502J1_128_2852_n122,
DP_OP_502J1_128_2852_n121, DP_OP_502J1_128_2852_n120,
DP_OP_502J1_128_2852_n119, DP_OP_502J1_128_2852_n118,
DP_OP_502J1_128_2852_n117, DP_OP_502J1_128_2852_n116,
DP_OP_502J1_128_2852_n115, DP_OP_502J1_128_2852_n112,
DP_OP_502J1_128_2852_n111, DP_OP_502J1_128_2852_n110,
DP_OP_502J1_128_2852_n109, DP_OP_502J1_128_2852_n108,
DP_OP_502J1_128_2852_n107, DP_OP_502J1_128_2852_n106,
DP_OP_502J1_128_2852_n105, DP_OP_502J1_128_2852_n104,
DP_OP_502J1_128_2852_n103, DP_OP_502J1_128_2852_n102,
DP_OP_502J1_128_2852_n101, DP_OP_502J1_128_2852_n100, mult_x_313_n76,
mult_x_313_n75, mult_x_313_n74, mult_x_313_n69, mult_x_313_n68,
mult_x_313_n67, mult_x_313_n66, mult_x_313_n65, mult_x_313_n62,
mult_x_313_n61, mult_x_313_n60, mult_x_313_n59, mult_x_313_n58,
mult_x_313_n56, mult_x_313_n55, mult_x_313_n54, mult_x_313_n42,
mult_x_313_n39, mult_x_313_n38, mult_x_313_n37, mult_x_313_n36,
mult_x_313_n35, mult_x_313_n34, mult_x_313_n33, mult_x_313_n32,
mult_x_313_n31, mult_x_313_n30, mult_x_313_n29, mult_x_313_n28,
mult_x_313_n27, mult_x_313_n26, mult_x_313_n25, mult_x_313_n24,
mult_x_313_n23, mult_x_313_n22, mult_x_313_n21,
DP_OP_501J1_127_1459_n952, DP_OP_501J1_127_1459_n943,
DP_OP_501J1_127_1459_n939, DP_OP_501J1_127_1459_n931,
DP_OP_501J1_127_1459_n930, DP_OP_501J1_127_1459_n910,
DP_OP_501J1_127_1459_n794, DP_OP_501J1_127_1459_n790,
DP_OP_501J1_127_1459_n782, DP_OP_501J1_127_1459_n781,
DP_OP_501J1_127_1459_n741, DP_OP_501J1_127_1459_n538,
DP_OP_501J1_127_1459_n534, DP_OP_501J1_127_1459_n533,
DP_OP_501J1_127_1459_n532, DP_OP_501J1_127_1459_n528,
DP_OP_501J1_127_1459_n527, DP_OP_501J1_127_1459_n526,
DP_OP_501J1_127_1459_n522, DP_OP_501J1_127_1459_n520,
DP_OP_501J1_127_1459_n517, DP_OP_501J1_127_1459_n514,
DP_OP_501J1_127_1459_n511, DP_OP_501J1_127_1459_n508,
DP_OP_501J1_127_1459_n506, DP_OP_501J1_127_1459_n505,
DP_OP_501J1_127_1459_n499, DP_OP_501J1_127_1459_n496,
DP_OP_501J1_127_1459_n495, DP_OP_501J1_127_1459_n494,
DP_OP_501J1_127_1459_n493, DP_OP_501J1_127_1459_n492,
DP_OP_501J1_127_1459_n490, DP_OP_501J1_127_1459_n489,
DP_OP_501J1_127_1459_n488, DP_OP_501J1_127_1459_n487,
DP_OP_501J1_127_1459_n486, DP_OP_501J1_127_1459_n485,
DP_OP_501J1_127_1459_n484, DP_OP_501J1_127_1459_n483,
DP_OP_501J1_127_1459_n482, DP_OP_501J1_127_1459_n481,
DP_OP_501J1_127_1459_n480, DP_OP_501J1_127_1459_n479,
DP_OP_501J1_127_1459_n478, DP_OP_501J1_127_1459_n477,
DP_OP_501J1_127_1459_n476, DP_OP_501J1_127_1459_n475,
DP_OP_501J1_127_1459_n474, DP_OP_501J1_127_1459_n473,
DP_OP_501J1_127_1459_n472, DP_OP_501J1_127_1459_n471,
DP_OP_501J1_127_1459_n470, DP_OP_501J1_127_1459_n469,
DP_OP_501J1_127_1459_n468, DP_OP_501J1_127_1459_n467,
DP_OP_501J1_127_1459_n466, DP_OP_501J1_127_1459_n465,
DP_OP_501J1_127_1459_n464, DP_OP_501J1_127_1459_n272,
DP_OP_501J1_127_1459_n271, DP_OP_501J1_127_1459_n270,
DP_OP_501J1_127_1459_n269, DP_OP_501J1_127_1459_n268,
DP_OP_501J1_127_1459_n264, DP_OP_501J1_127_1459_n263,
DP_OP_501J1_127_1459_n262, DP_OP_501J1_127_1459_n261,
DP_OP_501J1_127_1459_n260, DP_OP_501J1_127_1459_n256,
DP_OP_501J1_127_1459_n254, DP_OP_501J1_127_1459_n253,
DP_OP_501J1_127_1459_n252, DP_OP_501J1_127_1459_n251,
DP_OP_501J1_127_1459_n246, DP_OP_501J1_127_1459_n245,
DP_OP_501J1_127_1459_n244, DP_OP_501J1_127_1459_n243,
DP_OP_501J1_127_1459_n242, DP_OP_501J1_127_1459_n241,
DP_OP_501J1_127_1459_n238, DP_OP_501J1_127_1459_n236,
DP_OP_501J1_127_1459_n235, DP_OP_501J1_127_1459_n234,
DP_OP_501J1_127_1459_n233, DP_OP_501J1_127_1459_n228,
DP_OP_501J1_127_1459_n226, DP_OP_501J1_127_1459_n225,
DP_OP_501J1_127_1459_n223, DP_OP_501J1_127_1459_n220,
DP_OP_501J1_127_1459_n217, DP_OP_501J1_127_1459_n216,
DP_OP_501J1_127_1459_n215, DP_OP_501J1_127_1459_n212,
DP_OP_501J1_127_1459_n209, DP_OP_501J1_127_1459_n207,
DP_OP_501J1_127_1459_n202, DP_OP_501J1_127_1459_n199,
DP_OP_501J1_127_1459_n198, DP_OP_501J1_127_1459_n197,
DP_OP_501J1_127_1459_n196, DP_OP_501J1_127_1459_n195,
DP_OP_501J1_127_1459_n193, DP_OP_501J1_127_1459_n192,
DP_OP_501J1_127_1459_n191, DP_OP_501J1_127_1459_n190,
DP_OP_501J1_127_1459_n189, DP_OP_501J1_127_1459_n188,
DP_OP_501J1_127_1459_n187, DP_OP_501J1_127_1459_n186,
DP_OP_501J1_127_1459_n185, DP_OP_501J1_127_1459_n184,
DP_OP_501J1_127_1459_n183, DP_OP_501J1_127_1459_n182,
DP_OP_501J1_127_1459_n181, DP_OP_501J1_127_1459_n180,
DP_OP_501J1_127_1459_n178, DP_OP_501J1_127_1459_n177,
DP_OP_501J1_127_1459_n176, DP_OP_501J1_127_1459_n175,
DP_OP_501J1_127_1459_n174, DP_OP_501J1_127_1459_n173,
DP_OP_501J1_127_1459_n172, DP_OP_501J1_127_1459_n171,
DP_OP_501J1_127_1459_n170, DP_OP_501J1_127_1459_n169,
DP_OP_501J1_127_1459_n168, DP_OP_501J1_127_1459_n167,
DP_OP_501J1_127_1459_n166, DP_OP_501J1_127_1459_n165,
DP_OP_501J1_127_1459_n164, DP_OP_501J1_127_1459_n163,
DP_OP_501J1_127_1459_n162, DP_OP_501J1_127_1459_n161,
DP_OP_501J1_127_1459_n159, DP_OP_501J1_127_1459_n158,
DP_OP_501J1_127_1459_n157, DP_OP_501J1_127_1459_n156,
DP_OP_501J1_127_1459_n155, DP_OP_501J1_127_1459_n154,
DP_OP_501J1_127_1459_n153, DP_OP_501J1_127_1459_n152,
DP_OP_501J1_127_1459_n151, DP_OP_501J1_127_1459_n150,
DP_OP_501J1_127_1459_n149, DP_OP_501J1_127_1459_n148,
DP_OP_501J1_127_1459_n147, DP_OP_501J1_127_1459_n146,
DP_OP_501J1_127_1459_n145, DP_OP_501J1_127_1459_n144,
DP_OP_501J1_127_1459_n143, DP_OP_501J1_127_1459_n142,
DP_OP_501J1_127_1459_n141, DP_OP_501J1_127_1459_n140,
DP_OP_501J1_127_1459_n139, DP_OP_501J1_127_1459_n138,
DP_OP_501J1_127_1459_n137, DP_OP_501J1_127_1459_n136,
DP_OP_501J1_127_1459_n135, DP_OP_501J1_127_1459_n134,
DP_OP_501J1_127_1459_n133, DP_OP_501J1_127_1459_n132,
DP_OP_501J1_127_1459_n131, DP_OP_501J1_127_1459_n130,
DP_OP_501J1_127_1459_n129, DP_OP_499J1_125_4188_n304,
DP_OP_499J1_125_4188_n303, DP_OP_499J1_125_4188_n302,
DP_OP_499J1_125_4188_n301, DP_OP_499J1_125_4188_n300,
DP_OP_499J1_125_4188_n299, DP_OP_499J1_125_4188_n298,
DP_OP_499J1_125_4188_n295, DP_OP_499J1_125_4188_n294,
DP_OP_499J1_125_4188_n293, DP_OP_499J1_125_4188_n292,
DP_OP_499J1_125_4188_n291, DP_OP_499J1_125_4188_n281,
DP_OP_499J1_125_4188_n280, DP_OP_499J1_125_4188_n279,
DP_OP_499J1_125_4188_n278, DP_OP_499J1_125_4188_n277,
DP_OP_499J1_125_4188_n276, DP_OP_499J1_125_4188_n274,
DP_OP_499J1_125_4188_n273, DP_OP_499J1_125_4188_n272,
DP_OP_499J1_125_4188_n271, DP_OP_499J1_125_4188_n270,
DP_OP_499J1_125_4188_n269, DP_OP_499J1_125_4188_n266,
DP_OP_499J1_125_4188_n252, DP_OP_499J1_125_4188_n250,
DP_OP_499J1_125_4188_n249, DP_OP_499J1_125_4188_n248,
DP_OP_499J1_125_4188_n247, DP_OP_499J1_125_4188_n246,
DP_OP_499J1_125_4188_n245, DP_OP_499J1_125_4188_n244,
DP_OP_499J1_125_4188_n243, DP_OP_499J1_125_4188_n242,
DP_OP_499J1_125_4188_n241, DP_OP_499J1_125_4188_n240,
DP_OP_499J1_125_4188_n239, DP_OP_499J1_125_4188_n238,
DP_OP_499J1_125_4188_n237, DP_OP_499J1_125_4188_n236,
DP_OP_499J1_125_4188_n235, DP_OP_499J1_125_4188_n234,
DP_OP_499J1_125_4188_n233, DP_OP_499J1_125_4188_n232,
DP_OP_499J1_125_4188_n231, DP_OP_499J1_125_4188_n230,
DP_OP_499J1_125_4188_n229, DP_OP_499J1_125_4188_n228,
DP_OP_499J1_125_4188_n227, DP_OP_499J1_125_4188_n226,
DP_OP_499J1_125_4188_n225, DP_OP_499J1_125_4188_n224,
DP_OP_499J1_125_4188_n223, DP_OP_499J1_125_4188_n222,
DP_OP_499J1_125_4188_n221, DP_OP_499J1_125_4188_n220,
DP_OP_499J1_125_4188_n219, DP_OP_499J1_125_4188_n218,
DP_OP_499J1_125_4188_n217, DP_OP_499J1_125_4188_n216,
DP_OP_499J1_125_4188_n215, DP_OP_499J1_125_4188_n214,
DP_OP_499J1_125_4188_n213, DP_OP_499J1_125_4188_n212,
DP_OP_499J1_125_4188_n211, DP_OP_499J1_125_4188_n210,
DP_OP_499J1_125_4188_n209, DP_OP_499J1_125_4188_n208,
DP_OP_499J1_125_4188_n207, DP_OP_499J1_125_4188_n206,
DP_OP_499J1_125_4188_n205, DP_OP_499J1_125_4188_n204,
DP_OP_499J1_125_4188_n203, DP_OP_499J1_125_4188_n202,
DP_OP_498J1_124_4426_n152, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2213,
n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223,
n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233,
n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243,
n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253,
n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263,
n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273,
n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283,
n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293,
n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303,
n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313,
n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323,
n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525,
n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555,
n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565,
n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575,
n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585,
n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595,
n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605,
n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615,
n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625,
n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635,
n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645,
n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655,
n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665,
n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675,
n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685,
n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695,
n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705,
n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715,
n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725,
n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735,
n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745,
n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785,
n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795,
n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805,
n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815,
n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825,
n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835,
n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845,
n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855,
n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865,
n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875,
n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885,
n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975,
n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985,
n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995,
n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005,
n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015,
n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025,
n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035,
n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045,
n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055,
n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065,
n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075,
n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095,
n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105,
n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115,
n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125,
n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135,
n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145,
n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155,
n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165,
n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175,
n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185,
n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195,
n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205,
n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215,
n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225,
n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235,
n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245,
n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255,
n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265,
n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275,
n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285,
n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295,
n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305,
n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315,
n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325,
n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335,
n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345,
n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355,
n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365,
n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375,
n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385,
n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395,
n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405,
n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415,
n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425,
n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435,
n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445,
n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455,
n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465, n6466,
n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475, n6476,
n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485, n6486,
n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495, n6496,
n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505, n6506,
n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515, n6516,
n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525, n6526,
n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535, n6536,
n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545, n6546,
n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555, n6556,
n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565, n6566,
n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575, n6576,
n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585, n6586,
n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595, n6596,
n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605, n6606,
n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615, n6616,
n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625, n6626,
n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635, n6636,
n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645, n6646,
n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655, n6656,
n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665, n6666,
n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675, n6676,
n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685, n6686,
n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695, n6696,
n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705, n6706,
n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715, n6716,
n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726,
n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736,
n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745, n6746,
n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756,
n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766,
n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776,
n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786,
n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796,
n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806,
n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816,
n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826,
n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836,
n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846,
n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856,
n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866,
n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876,
n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886,
n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896,
n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906,
n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916,
n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926,
n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, n6936,
n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946,
n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956,
n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966,
n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976,
n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986,
n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996,
n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006,
n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, n7016,
n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7025, n7026, n7027,
n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, n7036, n7037,
n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, n7046, n7047,
n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, n7056, n7057,
n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065, n7066, n7067,
n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075, n7076, n7077,
n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:3] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [35:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [24:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [30:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:0] FPMULT_inst_RecursiveKOA_Result;
wire [5:0] FPMULT_inst_RecursiveKOA_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [13:0] FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [15:0] FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:0] FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [11:0] FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:0] FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:4] FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n6997), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n6997), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n2302), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n6996), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n6996), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2141), .CK(clk), .RN(n6995),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n2438) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2145), .CK(clk), .RN(
n6964), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2144), .CK(clk), .RN(
n6957), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n2453) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n6994),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2132), .CK(clk), .RN(n6994), .Q(
FPSENCOS_d_ff3_LUT_out[1]), .QN(n6822) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2130), .CK(clk), .RN(n6994), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2128), .CK(clk), .RN(n6994), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2126), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n6825) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2125), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2124), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2121), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2120), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2119), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2118), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n6823) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2117), .CK(clk), .RN(n6992), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2115), .CK(clk), .RN(n6992), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2114), .CK(clk), .RN(n6992), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2113), .CK(clk), .RN(n6992), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1853), .CK(clk), .RN(n6992),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1852), .CK(clk), .RN(n6992),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1851), .CK(clk), .RN(n6992),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1850), .CK(clk), .RN(n6992),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1849), .CK(clk), .RN(n6992),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1848), .CK(clk), .RN(n6991),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1847), .CK(clk), .RN(n6991),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1846), .CK(clk), .RN(n6991),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1951), .CK(clk), .RN(n6991),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1950), .CK(clk), .RN(n6991),
.QN(n2407) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1949), .CK(clk), .RN(n6991),
.QN(n2389) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1948), .CK(clk), .RN(n6991),
.QN(n2390) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1947), .CK(clk), .RN(n6991),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1946), .CK(clk), .RN(n6991),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1945), .CK(clk), .RN(n6991),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1944), .CK(clk), .RN(n6990),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2112), .CK(clk), .RN(n6996), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2111), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2110), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2109), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2108), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2107), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2106), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2105), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2104), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2103), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2102), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2101), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2100), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2099), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2098), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2097), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2096), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2095), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2094), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2093), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2092), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2091), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2090), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2089), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2088), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2087), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2086), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2085), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2084), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2083), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2082), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2081), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1741), .CK(clk), .RN(
n7006), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1861), .CK(clk), .RN(
n7006), .Q(FPSENCOS_d_ff2_Y[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1740), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1860), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n6797) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1739), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1859), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n6798) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1738), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1858), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n6799) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1737), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1856), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_Y[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1735), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1765), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1734), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1854), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n6742) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1788), .CK(clk), .RN(n6950),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1863), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1862), .CK(clk), .RN(n7000),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1960), .CK(clk), .RN(n7000),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1749), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1877), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1876), .CK(clk), .RN(n6999),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1974), .CK(clk), .RN(n6999),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1746), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1871), .CK(clk), .RN(
n6998), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1870), .CK(clk), .RN(n6998),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1968), .CK(clk), .RN(n6998),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1789), .CK(clk), .RN(n2360),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n6998), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1743), .CK(clk), .RN(
n6998), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1865), .CK(clk), .RN(
n6998), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1864), .CK(clk), .RN(n6997),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1962), .CK(clk), .RN(n6978),
.QN(n2416) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n6978), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1745), .CK(clk), .RN(
n6978), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1869), .CK(clk), .RN(
n6978), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1868), .CK(clk), .RN(n6978),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1966), .CK(clk), .RN(n6978),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1790), .CK(clk), .RN(n6928),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n6978), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1744), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1867), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1866), .CK(clk), .RN(n6977),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1964), .CK(clk), .RN(n6977),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1747), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1873), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1872), .CK(clk), .RN(n6976),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1970), .CK(clk), .RN(n6976),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n6976), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1760), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1899), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1898), .CK(clk), .RN(n6976),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1996), .CK(clk), .RN(n6975),
.QN(n2408) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1758), .CK(clk), .RN(
n6975), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1894), .CK(clk), .RN(n6975),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1992), .CK(clk), .RN(n6974),
.QN(n2412) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n6974), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1751), .CK(clk), .RN(
n6974), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1880), .CK(clk), .RN(n6974),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1978), .CK(clk), .RN(n6974),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n6974), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1748), .CK(clk), .RN(
n6973), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1875), .CK(clk), .RN(
n6973), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1874), .CK(clk), .RN(n6973),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1972), .CK(clk), .RN(n6973),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n6973), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1756), .CK(clk), .RN(
n6973), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1891), .CK(clk), .RN(
n6972), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1890), .CK(clk), .RN(n6972),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1988), .CK(clk), .RN(n6972),
.QN(n2402) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n6972), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1753), .CK(clk), .RN(
n6972), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1885), .CK(clk), .RN(
n6972), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1884), .CK(clk), .RN(n6971),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1982), .CK(clk), .RN(n6971),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1750), .CK(clk), .RN(
n6971), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1879), .CK(clk), .RN(
n6971), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1878), .CK(clk), .RN(n6971),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1976), .CK(clk), .RN(n6970),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1754), .CK(clk), .RN(
n6970), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1887), .CK(clk), .RN(
n6970), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1886), .CK(clk), .RN(n6970),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1984), .CK(clk), .RN(n6970),
.QN(n2396) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1798), .CK(clk), .RN(n6933), .QN(n2266) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1752), .CK(clk), .RN(
n6969), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1883), .CK(clk), .RN(
n6969), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1882), .CK(clk), .RN(n6969),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1980), .CK(clk), .RN(n6969),
.QN(n2397) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1909), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1845), .CK(clk), .RN(
n6968), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1844), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1942), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2079), .CK(clk), .RN(
n2341), .Q(FPADDSUB_bit_shift_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1761), .CK(clk), .RN(
n6968), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1901), .CK(clk), .RN(
n6967), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1900), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1998), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n6967), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1762), .CK(clk), .RN(
n6967), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1903), .CK(clk), .RN(
n6972), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1902), .CK(clk), .RN(n6990),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2000), .CK(clk), .RN(n6990),
.QN(n2419) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n6990), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1757), .CK(clk), .RN(
n6990), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1893), .CK(clk), .RN(
n6980), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1892), .CK(clk), .RN(n4560),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1990), .CK(clk), .RN(n6981),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n4563), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1907), .CK(clk), .RN(
n4561), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1906), .CK(clk), .RN(n6988),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2004), .CK(clk), .RN(n6988),
.QN(n2420) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n6988), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1763), .CK(clk), .RN(
n6988), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1905), .CK(clk), .RN(
n6988), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1904), .CK(clk), .RN(n6988),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2002), .CK(clk), .RN(n6987),
.QN(n2421) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n6987), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1755), .CK(clk), .RN(
n6987), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1889), .CK(clk), .RN(
n6987), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1888), .CK(clk), .RN(n6987),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1986), .CK(clk), .RN(n6986),
.QN(n2423) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n6986), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1759), .CK(clk), .RN(
n6986), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1897), .CK(clk), .RN(
n6986), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1896), .CK(clk), .RN(n6986),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1994), .CK(clk), .RN(n6985),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1695), .CK(clk), .RN(n6985),
.Q(cordic_result_31_) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1787), .CK(clk), .RN(n6938),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1624), .CK(clk),
.RN(n2296), .Q(FPMULT_Op_MY[31]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1680), .CK(clk),
.RN(n7015), .Q(DP_OP_501J1_127_1459_n939), .QN(n6670) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1677), .CK(clk),
.RN(n6920), .Q(FPMULT_Op_MX[19]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1668), .CK(clk),
.RN(n7012), .Q(DP_OP_501J1_127_1459_n952), .QN(n6671) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1667), .CK(clk),
.RN(n7013), .Q(FPMULT_Op_MX[9]), .QN(n6636) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1665), .CK(clk),
.RN(n7012), .Q(FPMULT_Op_MX[7]), .QN(n6692) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1664), .CK(clk),
.RN(n2380), .Q(FPMULT_Op_MX[6]), .QN(n6630) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1657), .CK(clk),
.RN(n7018), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1597), .CK(clk),
.RN(n7017), .Q(FPMULT_Add_result[23]), .QN(n6658) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1641), .CK(clk),
.RN(n2295), .Q(FPMULT_Op_MY[15]), .QN(n6882) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1639), .CK(clk),
.RN(n2295), .Q(n2224), .QN(n2444) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1632), .CK(clk),
.RN(n7016), .Q(DP_OP_501J1_127_1459_n910), .QN(n6664) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1629), .CK(clk),
.RN(n7015), .Q(FPMULT_Op_MY[3]), .QN(n6855) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1628), .CK(clk),
.RN(n7016), .Q(FPMULT_Op_MY[2]), .QN(n6652) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1627), .CK(clk),
.RN(n7015), .Q(FPMULT_Op_MY[1]), .QN(n6853) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1626), .CK(clk),
.RN(n7016), .Q(FPMULT_Op_MY[0]), .QN(n6860) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1621), .CK(
clk), .RN(n2291), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n6826) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1576), .CK(clk), .RN(n7016), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1584), .CK(clk), .RN(n7015), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1583), .CK(clk), .RN(n2293), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1582), .CK(clk), .RN(n2380), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1581), .CK(clk), .RN(n7016), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1580), .CK(clk), .RN(n6920), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1579), .CK(clk), .RN(n7013), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1578), .CK(clk), .RN(n7019), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1577), .CK(clk), .RN(n2381), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1504), .CK(clk), .RN(n2380), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1503), .CK(clk), .RN(n7011), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1502), .CK(clk), .RN(n2295), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1501), .CK(clk), .RN(n7019), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1500), .CK(clk), .RN(n2381), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1499), .CK(clk), .RN(n2380), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1498), .CK(clk), .RN(n7013), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1497), .CK(clk), .RN(n6920), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1496), .CK(clk), .RN(n7011), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1495), .CK(clk), .RN(n7019), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1494), .CK(clk), .RN(n2292), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1493), .CK(clk), .RN(n2381), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1492), .CK(clk), .RN(n2380), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1491), .CK(clk), .RN(n7013), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1490), .CK(clk), .RN(n2288), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1489), .CK(clk), .RN(n2288), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1488), .CK(clk), .RN(n2288), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1487), .CK(clk), .RN(n2289), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1486), .CK(clk), .RN(n2289), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1485), .CK(clk), .RN(n2289), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1484), .CK(clk), .RN(n2289), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1483), .CK(clk), .RN(n2289), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1481), .CK(clk), .RN(n2289), .Q(mult_result[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(
n6938), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1477), .CK(clk), .RN(
n6938), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1476), .CK(clk), .RN(
n6938), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1474), .CK(clk), .RN(
n6938), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(
n6955), .Q(result_add_subt[23]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1472), .CK(clk), .RN(
n6955), .Q(result_add_subt[24]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1471), .CK(clk), .RN(
n6955), .Q(result_add_subt[25]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1470), .CK(clk), .RN(
n6955), .Q(result_add_subt[26]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1469), .CK(clk), .RN(
n6956), .Q(result_add_subt[27]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1468), .CK(clk), .RN(
n6956), .Q(result_add_subt[28]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1467), .CK(clk), .RN(
n6956), .Q(result_add_subt[29]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1466), .CK(clk), .RN(
n6956), .Q(result_add_subt[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1460), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1459), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1458), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1455), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1454), .CK(clk), .RN(
n6964), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1450), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1449), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1444), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1440), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1435), .CK(clk), .RN(n6940),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1434), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1430), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1429), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1425), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(clk), .RN(n6941),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1412), .CK(clk), .RN(n6942), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n6956), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n6942), .Q(result_add_subt[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1407), .CK(clk), .RN(n6942),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1406), .CK(clk), .RN(
n2340), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n6942), .Q(result_add_subt[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n6942),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(
n6935), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n6942), .Q(result_add_subt[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1401), .CK(clk), .RN(n6943),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1400), .CK(clk), .RN(
n4555), .QN(n6775) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n6950), .Q(result_add_subt[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1398), .CK(clk), .RN(n6934),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1397), .CK(clk), .RN(
n4555), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n2360), .Q(result_add_subt[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1395), .CK(clk), .RN(n6928),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1394), .CK(clk), .RN(
n4557), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n6933), .Q(result_add_subt[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1392), .CK(clk), .RN(n6932),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1391), .CK(clk), .RN(
n4621), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n6929), .Q(result_add_subt[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1389), .CK(clk), .RN(n6943),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1388), .CK(clk), .RN(
n4558), .QN(n6776) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1386), .CK(clk), .RN(n6944),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1385), .CK(clk), .RN(
n6953), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1383), .CK(clk), .RN(n6944),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1382), .CK(clk), .RN(
n6928), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n6944), .Q(result_add_subt[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(n6944),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1379), .CK(clk), .RN(
n6944), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n6944), .Q(result_add_subt[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(n6944),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1376), .CK(clk), .RN(
n6966), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n6944), .Q(result_add_subt[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1374), .CK(clk), .RN(n6944),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1373), .CK(clk), .RN(
n6945), .QN(n6711) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n6945), .Q(result_add_subt[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1371), .CK(clk), .RN(n6945),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1370), .CK(clk), .RN(
n6945), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n6945), .Q(result_add_subt[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(n6945),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1367), .CK(clk), .RN(
n6945), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n6945), .Q(result_add_subt[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1365), .CK(clk), .RN(n6945),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1364), .CK(clk), .RN(
n6945), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1363), .CK(clk), .RN(
n6946), .Q(result_add_subt[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n6946),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n6946), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(clk), .RN(n6946), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1359), .CK(clk), .RN(n6946),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(clk), .RN(n6946),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(
n6953), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1356), .CK(clk), .RN(
n6946), .Q(result_add_subt[31]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n6946),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n6946), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(clk), .RN(n6946), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n6957),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n2441) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1330), .CK(clk), .RN(
n6964), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n6947), .Q(result_add_subt[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n6947),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(
n6953), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n6947),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n6947),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n6838), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(
n6956), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1318), .CK(clk), .RN(
n6956), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n6947), .Q(result_add_subt[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n6947),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(
n6953), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n6947),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n6947),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n6837), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n6947),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(
n6948), .QN(n6654) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n6948),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n6948),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n6836), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n6948), .Q(result_add_subt[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n6948),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(
n6953), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n6948),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n6948),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n6835), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n6948), .Q(result_add_subt[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n6948),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(
n6953), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n6948),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n6834), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n6949), .Q(result_add_subt[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(
n4555), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n6949), .Q(result_add_subt[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(
n6953), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n6833), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n6949),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(
n6932), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n6929),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n6943),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n6950),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n6934),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n2360),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n6928),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n6933),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n6932),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n6929),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n6832), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n6831), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n6951),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(clk), .RN(n6964),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(clk), .RN(n6964),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n6952),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n6953),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n6953),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n6953),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(clk), .RN(n6964),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n6787) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[6])
);
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[7])
);
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[9])
);
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_14_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_15_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[6])
);
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[8])
);
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[9])
);
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1_n1), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]) );
CMPR32X2TS DP_OP_234J1_132_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n2319),
.C(DP_OP_234J1_132_4955_n22), .CO(DP_OP_234J1_132_4955_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J1_132_4955_U8 ( .A(DP_OP_234J1_132_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J1_132_4955_n8), .CO(
DP_OP_234J1_132_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J1_132_4955_U6 ( .A(DP_OP_234J1_132_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J1_132_4955_n6), .CO(
DP_OP_234J1_132_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J1_132_4955_U2 ( .A(n2320), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J1_132_4955_n2), .CO(DP_OP_234J1_132_4955_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_0_U9 ( .A(intadd_0_A_0_), .B(intadd_0_B_0_), .C(
intadd_0_CI), .CO(intadd_0_n8), .S(intadd_0_SUM_0_) );
CMPR32X2TS intadd_0_U8 ( .A(intadd_0_A_1_), .B(intadd_0_B_1_), .C(
intadd_0_n8), .CO(intadd_0_n7), .S(intadd_0_SUM_1_) );
CMPR32X2TS intadd_0_U7 ( .A(intadd_0_A_2_), .B(intadd_0_B_2_), .C(
intadd_0_n7), .CO(intadd_0_n6), .S(intadd_0_SUM_2_) );
CMPR32X2TS intadd_0_U6 ( .A(intadd_0_A_3_), .B(intadd_0_B_3_), .C(
intadd_0_n6), .CO(intadd_0_n5), .S(intadd_0_SUM_3_) );
CMPR32X2TS intadd_0_U4 ( .A(intadd_0_A_5_), .B(intadd_0_B_5_), .C(
intadd_0_n4), .CO(intadd_0_n3), .S(intadd_0_SUM_5_) );
CMPR32X2TS intadd_0_U2 ( .A(intadd_0_A_7_), .B(intadd_0_B_7_), .C(
intadd_0_n2), .CO(intadd_0_n1), .S(intadd_0_SUM_7_) );
CMPR32X2TS intadd_1_U9 ( .A(intadd_1_A_0_), .B(intadd_1_B_0_), .C(
intadd_1_CI), .CO(intadd_1_n8), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1_U8 ( .A(mult_x_311_n37), .B(intadd_1_B_1_), .C(
intadd_1_n8), .CO(intadd_1_n7), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1_U6 ( .A(mult_x_311_n29), .B(mult_x_311_n23), .C(
intadd_1_n6), .CO(intadd_1_n5), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1_U5 ( .A(mult_x_311_n22), .B(mult_x_311_n18), .C(
intadd_1_n5), .CO(intadd_1_n4), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1_U4 ( .A(mult_x_311_n17), .B(mult_x_311_n15), .C(
intadd_1_n4), .CO(intadd_1_n3), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1_U2 ( .A(intadd_1_A_7_), .B(intadd_1_B_7_), .C(
intadd_1_n2), .CO(intadd_1_n1), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_2_U9 ( .A(intadd_2_A_0_), .B(intadd_2_B_0_), .C(
intadd_2_CI), .CO(intadd_2_n8), .S(intadd_2_SUM_0_) );
CMPR32X2TS intadd_2_U8 ( .A(intadd_2_A_1_), .B(intadd_2_B_1_), .C(
intadd_2_n8), .CO(intadd_2_n7), .S(intadd_2_SUM_1_) );
CMPR32X2TS intadd_2_U7 ( .A(intadd_2_A_2_), .B(intadd_2_B_2_), .C(
intadd_2_n7), .CO(intadd_2_n6), .S(intadd_2_SUM_2_) );
CMPR32X2TS intadd_2_U6 ( .A(intadd_2_A_3_), .B(intadd_2_B_3_), .C(
intadd_2_n6), .CO(intadd_2_n5), .S(intadd_2_SUM_3_) );
CMPR32X2TS intadd_2_U4 ( .A(intadd_2_A_5_), .B(intadd_2_B_5_), .C(
intadd_2_n4), .CO(intadd_2_n3), .S(intadd_2_SUM_5_) );
CMPR32X2TS intadd_3_U8 ( .A(intadd_3_A_0_), .B(intadd_3_B_0_), .C(
intadd_3_CI), .CO(intadd_3_n7), .S(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_3_U4 ( .A(mult_x_309_n22), .B(mult_x_309_n18), .C(
intadd_3_n4), .CO(intadd_3_n3), .S(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_5_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n6663), .C(intadd_5_CI), .CO(intadd_5_n3), .S(intadd_5_SUM_0_) );
CMPR32X2TS intadd_5_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n6682), .C(intadd_5_n3), .CO(intadd_5_n2), .S(intadd_5_SUM_1_) );
CMPR32X2TS intadd_5_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n2230), .C(intadd_5_n2), .CO(intadd_5_n1), .S(intadd_5_SUM_2_) );
CMPR32X2TS intadd_6_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n6682), .C(intadd_6_n3), .CO(intadd_6_n2), .S(intadd_6_SUM_1_) );
CMPR32X2TS intadd_6_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n2272), .C(intadd_6_n2), .CO(intadd_6_n1), .S(intadd_6_SUM_2_) );
CMPR42X1TS DP_OP_500J1_126_2852_U125 ( .A(DP_OP_500J1_126_2852_n174), .B(
DP_OP_500J1_126_2852_n138), .C(DP_OP_500J1_126_2852_n141), .D(
DP_OP_500J1_126_2852_n181), .ICI(DP_OP_500J1_126_2852_n188), .S(
DP_OP_500J1_126_2852_n136), .ICO(DP_OP_500J1_126_2852_n134), .CO(
DP_OP_500J1_126_2852_n135) );
CMPR42X1TS DP_OP_500J1_126_2852_U121 ( .A(DP_OP_500J1_126_2852_n151), .B(
DP_OP_500J1_126_2852_n158), .C(DP_OP_500J1_126_2852_n132), .D(
DP_OP_500J1_126_2852_n165), .ICI(DP_OP_500J1_126_2852_n130), .S(
DP_OP_500J1_126_2852_n126), .ICO(DP_OP_500J1_126_2852_n124), .CO(
DP_OP_500J1_126_2852_n125) );
CMPR42X1TS DP_OP_500J1_126_2852_U118 ( .A(DP_OP_500J1_126_2852_n124), .B(
DP_OP_500J1_126_2852_n178), .C(DP_OP_500J1_126_2852_n121), .D(
DP_OP_500J1_126_2852_n125), .ICI(DP_OP_500J1_126_2852_n120), .S(
DP_OP_500J1_126_2852_n117), .ICO(DP_OP_500J1_126_2852_n115), .CO(
DP_OP_500J1_126_2852_n116) );
CMPR42X2TS DP_OP_500J1_126_2852_U115 ( .A(DP_OP_500J1_126_2852_n170), .B(
DP_OP_500J1_126_2852_n118), .C(DP_OP_500J1_126_2852_n112), .D(
DP_OP_500J1_126_2852_n119), .ICI(DP_OP_500J1_126_2852_n115), .S(
DP_OP_500J1_126_2852_n110), .ICO(DP_OP_500J1_126_2852_n108), .CO(
DP_OP_500J1_126_2852_n109) );
CMPR42X2TS DP_OP_500J1_126_2852_U113 ( .A(DP_OP_500J1_126_2852_n162), .B(
DP_OP_500J1_126_2852_n155), .C(DP_OP_500J1_126_2852_n107), .D(
DP_OP_500J1_126_2852_n111), .ICI(DP_OP_500J1_126_2852_n108), .S(
DP_OP_500J1_126_2852_n105), .ICO(DP_OP_500J1_126_2852_n103), .CO(
DP_OP_500J1_126_2852_n104) );
CMPR42X2TS DP_OP_502J1_128_2852_U125 ( .A(DP_OP_502J1_128_2852_n174), .B(
DP_OP_502J1_128_2852_n138), .C(DP_OP_502J1_128_2852_n141), .D(
DP_OP_502J1_128_2852_n181), .ICI(DP_OP_502J1_128_2852_n188), .S(
DP_OP_502J1_128_2852_n136), .ICO(DP_OP_502J1_128_2852_n134), .CO(
DP_OP_502J1_128_2852_n135) );
CMPR42X1TS DP_OP_502J1_128_2852_U122 ( .A(DP_OP_502J1_128_2852_n137), .B(
DP_OP_502J1_128_2852_n180), .C(DP_OP_502J1_128_2852_n187), .D(
DP_OP_502J1_128_2852_n134), .ICI(DP_OP_502J1_128_2852_n131), .S(
DP_OP_502J1_128_2852_n129), .ICO(DP_OP_502J1_128_2852_n127), .CO(
DP_OP_502J1_128_2852_n128) );
CMPR42X1TS DP_OP_502J1_128_2852_U118 ( .A(DP_OP_502J1_128_2852_n178), .B(
DP_OP_502J1_128_2852_n171), .C(DP_OP_502J1_128_2852_n121), .D(
DP_OP_502J1_128_2852_n125), .ICI(DP_OP_502J1_128_2852_n120), .S(
DP_OP_502J1_128_2852_n117), .ICO(DP_OP_502J1_128_2852_n115), .CO(
DP_OP_502J1_128_2852_n116) );
CMPR42X2TS DP_OP_502J1_128_2852_U115 ( .A(DP_OP_502J1_128_2852_n170), .B(
DP_OP_502J1_128_2852_n118), .C(DP_OP_502J1_128_2852_n112), .D(
DP_OP_502J1_128_2852_n119), .ICI(DP_OP_502J1_128_2852_n115), .S(
DP_OP_502J1_128_2852_n110), .ICO(DP_OP_502J1_128_2852_n108), .CO(
DP_OP_502J1_128_2852_n109) );
CMPR42X2TS DP_OP_502J1_128_2852_U113 ( .A(DP_OP_502J1_128_2852_n162), .B(
DP_OP_502J1_128_2852_n155), .C(DP_OP_502J1_128_2852_n107), .D(
DP_OP_502J1_128_2852_n111), .ICI(DP_OP_502J1_128_2852_n108), .S(
DP_OP_502J1_128_2852_n105), .ICO(DP_OP_502J1_128_2852_n103), .CO(
DP_OP_502J1_128_2852_n104) );
CMPR42X2TS DP_OP_502J1_128_2852_U112 ( .A(DP_OP_502J1_128_2852_n161), .B(
DP_OP_502J1_128_2852_n154), .C(DP_OP_502J1_128_2852_n147), .D(
DP_OP_502J1_128_2852_n106), .ICI(DP_OP_502J1_128_2852_n103), .S(
DP_OP_502J1_128_2852_n102), .ICO(DP_OP_502J1_128_2852_n100), .CO(
DP_OP_502J1_128_2852_n101) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[3])
);
DFFRX2TS R_15 ( .D(n1670), .CK(clk), .RN(n2295), .Q(n6925), .QN(n6645) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1643), .CK(clk),
.RN(n2292), .Q(FPMULT_Op_MY[17]), .QN(n6886) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1630), .CK(clk),
.RN(n7015), .Q(FPMULT_Op_MY[4]), .QN(n6858) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1631), .CK(clk),
.RN(n7016), .Q(FPMULT_Op_MY[5]), .QN(n6857) );
DFFSX4TS R_112 ( .D(n6854), .CK(clk), .SN(n7019), .Q(n6923), .QN(n6840) );
DFFRX2TS R_122 ( .D(DP_OP_501J1_127_1459_n943), .CK(clk), .RN(n7019), .Q(
n6922), .QN(n6697) );
DFFRX2TS R_121 ( .D(DP_OP_501J1_127_1459_n930), .CK(clk), .RN(n2380), .Q(
n6926), .QN(n6690) );
DFFSX4TS R_132 ( .D(n6847), .CK(clk), .SN(n2296), .Q(n6921), .QN(n6631) );
DFFRX2TS R_137 ( .D(n1673), .CK(clk), .RN(n7012), .Q(n6927), .QN(n6704) );
DFFRX2TS R_134 ( .D(n1661), .CK(clk), .RN(n2381), .Q(n6924), .QN(n6638) );
DFFRX1TS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1625), .CK(
clk), .RN(n7016), .Q(FPMULT_zero_flag), .QN(n6824) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1619), .CK(clk), .RN(
n7017), .Q(FPMULT_Add_result[1]), .QN(n6821) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1618), .CK(clk), .RN(
n7017), .Q(FPMULT_Add_result[2]), .QN(n6820) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1617), .CK(clk), .RN(
n7017), .Q(FPMULT_Add_result[3]), .QN(n6819) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1616), .CK(clk), .RN(
n2381), .Q(FPMULT_Add_result[4]), .QN(n6818) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(
n7019), .Q(FPMULT_Add_result[5]), .QN(n6817) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1614), .CK(clk), .RN(
n7013), .Q(FPMULT_Add_result[6]), .QN(n6816) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1613), .CK(clk), .RN(
n2290), .Q(FPMULT_Add_result[7]), .QN(n6815) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1612), .CK(clk), .RN(
n7011), .Q(FPMULT_Add_result[8]), .QN(n6814) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1610), .CK(clk),
.RN(n2381), .Q(FPMULT_Add_result[10]), .QN(n6812) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1609), .CK(clk),
.RN(n7019), .Q(FPMULT_Add_result[11]), .QN(n6811) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1608), .CK(clk),
.RN(n7013), .Q(FPMULT_Add_result[12]), .QN(n6810) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1607), .CK(clk),
.RN(n7012), .Q(FPMULT_Add_result[13]), .QN(n6809) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1606), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[14]), .QN(n6808) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1605), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[15]), .QN(n6807) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1604), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[16]), .QN(n6806) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1603), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[17]), .QN(n6805) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1602), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[18]), .QN(n6804) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1601), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[19]), .QN(n6803) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1600), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[20]), .QN(n6802) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1599), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[21]), .QN(n6801) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1598), .CK(clk),
.RN(n7018), .Q(FPMULT_Add_result[22]), .QN(n6800) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1525), .CK(
clk), .RN(n2291), .Q(FPMULT_Sgf_normalized_result[20]), .QN(n6791) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1523), .CK(
clk), .RN(n2291), .Q(FPMULT_Sgf_normalized_result[18]), .QN(n6790) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1524), .CK(
clk), .RN(n2291), .Q(FPMULT_Sgf_normalized_result[19]), .QN(n6789) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1516), .CK(
clk), .RN(n2381), .Q(FPMULT_Sgf_normalized_result[11]), .QN(n6788) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1515), .CK(
clk), .RN(n7011), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n6786) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1512), .CK(
clk), .RN(n7019), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n6782) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1507), .CK(
clk), .RN(n2291), .Q(FPMULT_Sgf_normalized_result[2]), .QN(n6743) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1509), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n6731) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1511), .CK(
clk), .RN(n7013), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n6730) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1954), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_X[28]), .QN(n6728) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(n7006),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n6723) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1806), .CK(clk), .RN(n6929), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n6716) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2137), .CK(clk), .RN(n6994),
.Q(FPSENCOS_cont_var_out[0]), .QN(n6710) );
DFFRXLTS R_107 ( .D(FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk),
.RN(n6996), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n6705)
);
DFFRX1TS R_105 ( .D(FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk),
.RN(n6995), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n6699)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1510), .CK(
clk), .RN(n2296), .Q(FPMULT_Sgf_normalized_result[5]), .QN(n6691) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1508), .CK(
clk), .RN(n2292), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n6687) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1689), .CK(clk), .RN(n2288), .Q(
FPMULT_FSM_selector_A), .QN(n6736) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1622), .CK(clk), .RN(n7014), .Q(
FPMULT_FSM_selector_B[1]), .QN(n6681) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1350), .CK(clk), .RN(
n6956), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n6667) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2140), .CK(clk), .RN(n6995),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n6663) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1595), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[8]), .QN(n6656) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1465), .CK(clk), .RN(n6938),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n6655) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1513), .CK(
clk), .RN(n2381), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n6646) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1691), .CK(clk), .RN(n4559),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n6644) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1623), .CK(clk), .RN(n7015), .Q(
FPMULT_FSM_selector_B[0]), .QN(n6642) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1690), .CK(clk), .RN(n6990),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n6634) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n6996), .Q(NaN_flag)
);
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1586), .CK(clk), .RN(
n2295), .Q(underflow_flag_mult), .QN(n6785) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n6995), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .QN(n6685) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1692), .CK(clk), .RN(n6979),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n6683) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[2])
);
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[4]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[1])
);
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[3])
);
CMPR32X2TS intadd_2_U2 ( .A(intadd_2_A_7_), .B(intadd_2_B_7_), .C(
intadd_2_n2), .CO(intadd_2_n1), .S(intadd_2_SUM_7_) );
CMPR32X2TS intadd_2_U5 ( .A(intadd_2_A_4_), .B(intadd_2_B_4_), .C(
intadd_2_n5), .CO(intadd_2_n4), .S(intadd_2_SUM_4_) );
CMPR32X2TS intadd_2_U3 ( .A(intadd_2_A_6_), .B(intadd_2_B_6_), .C(
intadd_2_n3), .CO(intadd_2_n2), .S(intadd_2_SUM_6_) );
CMPR32X2TS intadd_0_U5 ( .A(intadd_0_A_4_), .B(intadd_0_B_4_), .C(
intadd_0_n5), .CO(intadd_0_n4), .S(intadd_0_SUM_4_) );
CMPR32X2TS intadd_0_U3 ( .A(intadd_0_A_6_), .B(intadd_0_B_6_), .C(
intadd_0_n3), .CO(intadd_0_n2), .S(intadd_0_SUM_6_) );
CMPR32X2TS intadd_1_U7 ( .A(mult_x_311_n36), .B(mult_x_311_n30), .C(
intadd_1_n7), .CO(intadd_1_n6), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1_U3 ( .A(mult_x_311_n14), .B(intadd_1_B_6_), .C(
intadd_1_n3), .CO(intadd_1_n2), .S(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR42X1TS mult_x_313_U22 ( .A(mult_x_313_n67), .B(mult_x_313_n60), .C(n2375), .D(mult_x_313_n33), .ICI(mult_x_313_n34), .S(mult_x_313_n31), .ICO(
mult_x_313_n29), .CO(mult_x_313_n30) );
CMPR42X1TS mult_x_313_U20 ( .A(mult_x_313_n66), .B(mult_x_313_n32), .C(
mult_x_313_n59), .D(mult_x_313_n28), .ICI(mult_x_313_n29), .S(
mult_x_313_n26), .ICO(mult_x_313_n24), .CO(mult_x_313_n25) );
CMPR42X1TS mult_x_313_U19 ( .A(mult_x_313_n27), .B(mult_x_313_n58), .C(
mult_x_313_n54), .D(mult_x_313_n65), .ICI(mult_x_313_n24), .S(
mult_x_313_n23), .ICO(mult_x_313_n21), .CO(mult_x_313_n22) );
DFFRX2TS DP_OP_501J1_127_1459_R_123 ( .D(n6622), .CK(clk), .RN(n2296), .Q(
DP_OP_501J1_127_1459_n790), .QN(n6629) );
CMPR42X1TS DP_OP_501J1_127_1459_U450 ( .A(DP_OP_501J1_127_1459_n538), .B(
DP_OP_501J1_127_1459_n508), .C(DP_OP_501J1_127_1459_n532), .D(
DP_OP_501J1_127_1459_n526), .ICI(DP_OP_501J1_127_1459_n490), .S(
DP_OP_501J1_127_1459_n484), .ICO(DP_OP_501J1_127_1459_n482), .CO(
DP_OP_501J1_127_1459_n483) );
CMPR42X1TS DP_OP_501J1_127_1459_U449 ( .A(DP_OP_501J1_127_1459_n520), .B(
DP_OP_501J1_127_1459_n514), .C(DP_OP_501J1_127_1459_n488), .D(
DP_OP_501J1_127_1459_n485), .ICI(DP_OP_501J1_127_1459_n484), .S(
DP_OP_501J1_127_1459_n481), .ICO(DP_OP_501J1_127_1459_n479), .CO(
DP_OP_501J1_127_1459_n480) );
CMPR42X2TS DP_OP_501J1_127_1459_U444 ( .A(DP_OP_501J1_127_1459_n506), .B(
DP_OP_501J1_127_1459_n477), .C(DP_OP_501J1_127_1459_n471), .D(
DP_OP_501J1_127_1459_n475), .ICI(DP_OP_501J1_127_1459_n472), .S(
DP_OP_501J1_127_1459_n469), .ICO(DP_OP_501J1_127_1459_n467), .CO(
DP_OP_501J1_127_1459_n468) );
CMPR42X2TS DP_OP_501J1_127_1459_U443 ( .A(DP_OP_501J1_127_1459_n517), .B(
DP_OP_501J1_127_1459_n511), .C(DP_OP_501J1_127_1459_n505), .D(
DP_OP_501J1_127_1459_n470), .ICI(DP_OP_501J1_127_1459_n467), .S(
DP_OP_501J1_127_1459_n466), .ICO(DP_OP_501J1_127_1459_n464), .CO(
DP_OP_501J1_127_1459_n465) );
CMPR42X1TS DP_OP_501J1_127_1459_U163 ( .A(DP_OP_501J1_127_1459_n238), .B(
DP_OP_501J1_127_1459_n187), .C(DP_OP_501J1_127_1459_n193), .D(
DP_OP_501J1_127_1459_n246), .ICI(DP_OP_501J1_127_1459_n188), .S(
DP_OP_501J1_127_1459_n185), .ICO(DP_OP_501J1_127_1459_n183), .CO(
DP_OP_501J1_127_1459_n184) );
CMPR42X1TS DP_OP_501J1_127_1459_U162 ( .A(DP_OP_501J1_127_1459_n254), .B(
DP_OP_501J1_127_1459_n270), .C(DP_OP_501J1_127_1459_n262), .D(
DP_OP_501J1_127_1459_n191), .ICI(DP_OP_501J1_127_1459_n185), .S(
DP_OP_501J1_127_1459_n182), .ICO(DP_OP_501J1_127_1459_n180), .CO(
DP_OP_501J1_127_1459_n181) );
CMPR42X1TS DP_OP_501J1_127_1459_U159 ( .A(DP_OP_501J1_127_1459_n186), .B(
DP_OP_501J1_127_1459_n245), .C(DP_OP_501J1_127_1459_n269), .D(
DP_OP_501J1_127_1459_n253), .ICI(DP_OP_501J1_127_1459_n180), .S(
DP_OP_501J1_127_1459_n175), .ICO(DP_OP_501J1_127_1459_n173), .CO(
DP_OP_501J1_127_1459_n174) );
CMPR42X2TS DP_OP_501J1_127_1459_U158 ( .A(DP_OP_501J1_127_1459_n183), .B(
DP_OP_501J1_127_1459_n261), .C(DP_OP_501J1_127_1459_n177), .D(
DP_OP_501J1_127_1459_n184), .ICI(DP_OP_501J1_127_1459_n175), .S(
DP_OP_501J1_127_1459_n172), .ICO(DP_OP_501J1_127_1459_n170), .CO(
DP_OP_501J1_127_1459_n171) );
CMPR42X2TS DP_OP_501J1_127_1459_U157 ( .A(DP_OP_501J1_127_1459_n212), .B(
DP_OP_501J1_127_1459_n220), .C(DP_OP_501J1_127_1459_n178), .D(
DP_OP_501J1_127_1459_n228), .ICI(DP_OP_501J1_127_1459_n176), .S(
DP_OP_501J1_127_1459_n169), .ICO(DP_OP_501J1_127_1459_n167), .CO(
DP_OP_501J1_127_1459_n168) );
CMPR42X2TS DP_OP_501J1_127_1459_U155 ( .A(DP_OP_501J1_127_1459_n252), .B(
DP_OP_501J1_127_1459_n173), .C(DP_OP_501J1_127_1459_n169), .D(
DP_OP_501J1_127_1459_n174), .ICI(DP_OP_501J1_127_1459_n166), .S(
DP_OP_501J1_127_1459_n163), .ICO(DP_OP_501J1_127_1459_n161), .CO(
DP_OP_501J1_127_1459_n162) );
CMPR42X2TS DP_OP_501J1_127_1459_U152 ( .A(DP_OP_501J1_127_1459_n167), .B(
DP_OP_501J1_127_1459_n251), .C(DP_OP_501J1_127_1459_n235), .D(
DP_OP_501J1_127_1459_n243), .ICI(DP_OP_501J1_127_1459_n168), .S(
DP_OP_501J1_127_1459_n156), .ICO(DP_OP_501J1_127_1459_n154), .CO(
DP_OP_501J1_127_1459_n155) );
CMPR42X2TS DP_OP_501J1_127_1459_U151 ( .A(DP_OP_501J1_127_1459_n158), .B(
DP_OP_501J1_127_1459_n164), .C(DP_OP_501J1_127_1459_n165), .D(
DP_OP_501J1_127_1459_n161), .ICI(DP_OP_501J1_127_1459_n156), .S(
DP_OP_501J1_127_1459_n153), .ICO(DP_OP_501J1_127_1459_n151), .CO(
DP_OP_501J1_127_1459_n152) );
CMPR42X1TS DP_OP_501J1_127_1459_U149 ( .A(DP_OP_501J1_127_1459_n159), .B(
DP_OP_501J1_127_1459_n226), .C(DP_OP_501J1_127_1459_n242), .D(
DP_OP_501J1_127_1459_n234), .ICI(DP_OP_501J1_127_1459_n154), .S(
DP_OP_501J1_127_1459_n148), .ICO(DP_OP_501J1_127_1459_n146), .CO(
DP_OP_501J1_127_1459_n147) );
CMPR42X2TS DP_OP_501J1_127_1459_U148 ( .A(DP_OP_501J1_127_1459_n150), .B(
DP_OP_501J1_127_1459_n157), .C(DP_OP_501J1_127_1459_n155), .D(
DP_OP_501J1_127_1459_n148), .ICI(DP_OP_501J1_127_1459_n151), .S(
DP_OP_501J1_127_1459_n145), .ICO(DP_OP_501J1_127_1459_n143), .CO(
DP_OP_501J1_127_1459_n144) );
CMPR42X2TS DP_OP_501J1_127_1459_U143 ( .A(DP_OP_501J1_127_1459_n223), .B(
DP_OP_501J1_127_1459_n207), .C(DP_OP_501J1_127_1459_n215), .D(
DP_OP_501J1_127_1459_n135), .ICI(DP_OP_501J1_127_1459_n132), .S(
DP_OP_501J1_127_1459_n131), .ICO(DP_OP_501J1_127_1459_n129), .CO(
DP_OP_501J1_127_1459_n130) );
CMPR42X2TS DP_OP_499J1_125_4188_U240 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_499J1_125_4188_n244), .D(DP_OP_499J1_125_4188_n279), .ICI(
DP_OP_499J1_125_4188_n303), .S(DP_OP_499J1_125_4188_n243), .ICO(
DP_OP_499J1_125_4188_n241), .CO(DP_OP_499J1_125_4188_n242) );
CMPR42X2TS DP_OP_499J1_125_4188_U239 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_499J1_125_4188_n241), .D(DP_OP_499J1_125_4188_n278), .ICI(
DP_OP_499J1_125_4188_n302), .S(DP_OP_499J1_125_4188_n240), .ICO(
DP_OP_499J1_125_4188_n238), .CO(DP_OP_499J1_125_4188_n239) );
CMPR42X2TS DP_OP_499J1_125_4188_U238 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_499J1_125_4188_n238), .D(DP_OP_499J1_125_4188_n277), .ICI(
DP_OP_499J1_125_4188_n301), .S(DP_OP_499J1_125_4188_n237), .ICO(
DP_OP_499J1_125_4188_n235), .CO(DP_OP_499J1_125_4188_n236) );
CMPR42X2TS DP_OP_499J1_125_4188_U237 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_499J1_125_4188_n235), .D(DP_OP_499J1_125_4188_n276), .ICI(
DP_OP_499J1_125_4188_n300), .S(DP_OP_499J1_125_4188_n234), .ICO(
DP_OP_499J1_125_4188_n232), .CO(DP_OP_499J1_125_4188_n233) );
CMPR42X2TS DP_OP_499J1_125_4188_U235 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_499J1_125_4188_n229), .D(DP_OP_499J1_125_4188_n274), .ICI(
DP_OP_499J1_125_4188_n298), .S(DP_OP_499J1_125_4188_n228), .ICO(
DP_OP_499J1_125_4188_n226), .CO(DP_OP_499J1_125_4188_n227) );
CMPR42X2TS DP_OP_499J1_125_4188_U234 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_499J1_125_4188_n273), .D(n2208), .ICI(DP_OP_499J1_125_4188_n226),
.S(DP_OP_499J1_125_4188_n225), .ICO(DP_OP_499J1_125_4188_n223), .CO(
DP_OP_499J1_125_4188_n224) );
CMPR42X2TS DP_OP_499J1_125_4188_U232 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_499J1_125_4188_n271), .D(DP_OP_499J1_125_4188_n295), .ICI(
DP_OP_499J1_125_4188_n220), .S(DP_OP_499J1_125_4188_n219), .ICO(
DP_OP_499J1_125_4188_n217), .CO(DP_OP_499J1_125_4188_n218) );
CMPR42X2TS DP_OP_499J1_125_4188_U231 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_499J1_125_4188_n270), .D(DP_OP_499J1_125_4188_n294), .ICI(
DP_OP_499J1_125_4188_n217), .S(DP_OP_499J1_125_4188_n216), .ICO(
DP_OP_499J1_125_4188_n214), .CO(DP_OP_499J1_125_4188_n215) );
CMPR42X2TS DP_OP_499J1_125_4188_U229 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
n2213), .D(DP_OP_499J1_125_4188_n292), .ICI(DP_OP_499J1_125_4188_n211),
.S(DP_OP_499J1_125_4188_n210), .ICO(DP_OP_499J1_125_4188_n208), .CO(
DP_OP_499J1_125_4188_n209) );
CMPR42X2TS DP_OP_499J1_125_4188_U228 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(
n3006), .D(DP_OP_499J1_125_4188_n291), .ICI(DP_OP_499J1_125_4188_n208),
.S(DP_OP_499J1_125_4188_n207), .ICO(DP_OP_499J1_125_4188_n205), .CO(
DP_OP_499J1_125_4188_n206) );
CMPR42X2TS DP_OP_499J1_125_4188_U227 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_499J1_125_4188_n266), .D(n2252), .ICI(DP_OP_499J1_125_4188_n205),
.S(DP_OP_499J1_125_4188_n204), .ICO(DP_OP_499J1_125_4188_n202), .CO(
DP_OP_499J1_125_4188_n203) );
CMPR42X2TS DP_OP_501J1_127_1459_U156 ( .A(DP_OP_501J1_127_1459_n268), .B(
DP_OP_501J1_127_1459_n236), .C(DP_OP_501J1_127_1459_n260), .D(
DP_OP_501J1_127_1459_n244), .ICI(DP_OP_501J1_127_1459_n170), .S(
DP_OP_501J1_127_1459_n166), .ICO(DP_OP_501J1_127_1459_n164), .CO(
DP_OP_501J1_127_1459_n165) );
CMPR42X2TS DP_OP_501J1_127_1459_U446 ( .A(DP_OP_501J1_127_1459_n478), .B(
DP_OP_501J1_127_1459_n482), .C(DP_OP_501J1_127_1459_n476), .D(
DP_OP_501J1_127_1459_n479), .ICI(DP_OP_501J1_127_1459_n483), .S(
DP_OP_501J1_127_1459_n474), .ICO(DP_OP_501J1_127_1459_n472), .CO(
DP_OP_501J1_127_1459_n473) );
CMPR42X2TS DP_OP_501J1_127_1459_U147 ( .A(DP_OP_501J1_127_1459_n241), .B(
DP_OP_501J1_127_1459_n209), .C(DP_OP_501J1_127_1459_n233), .D(
DP_OP_501J1_127_1459_n217), .ICI(DP_OP_501J1_127_1459_n146), .S(
DP_OP_501J1_127_1459_n142), .ICO(DP_OP_501J1_127_1459_n140), .CO(
DP_OP_501J1_127_1459_n141) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1336), .CK(clk), .RN(
n6955), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1832), .CK(clk), .RN(
n6929), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n2388) );
CMPR42X2TS DP_OP_501J1_127_1459_U146 ( .A(DP_OP_501J1_127_1459_n225), .B(
DP_OP_501J1_127_1459_n149), .C(DP_OP_501J1_127_1459_n142), .D(
DP_OP_501J1_127_1459_n147), .ICI(DP_OP_501J1_127_1459_n143), .S(
DP_OP_501J1_127_1459_n139), .ICO(DP_OP_501J1_127_1459_n137), .CO(
DP_OP_501J1_127_1459_n138) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1840), .CK(clk), .RN(
n2340), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n2405) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2076), .CK(clk), .RN(
n2340), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1317), .CK(clk), .RN(
n6935), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1838), .CK(clk), .RN(
n6937), .Q(FPADDSUB_intDY_EWSW[5]), .QN(n2401) );
DFFRX4TS R_114_IP ( .D(n1672), .CK(clk), .RN(n2292), .Q(
DP_OP_501J1_127_1459_n931), .QN(n2406) );
DFFXLTS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[8])
);
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[7])
);
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
DFFRXLTS R_28 ( .D(n1565), .CK(clk), .RN(n6981), .Q(n6903) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1674), .CK(clk),
.RN(n2381), .Q(FPMULT_Op_MX[16]), .QN(n6884) );
DFFSX1TS R_63 ( .D(n7063), .CK(clk), .SN(n6985), .QN(n6757) );
DFFSX1TS R_78 ( .D(n7082), .CK(clk), .SN(n6941), .QN(n6727) );
DFFRXLTS R_113 ( .D(n1672), .CK(clk), .RN(n2288), .QN(n6888) );
DFFSX1TS R_133 ( .D(n6878), .CK(clk), .SN(n7016), .QN(n6827) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1333), .CK(clk), .RN(
n6955), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n6713) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(
n6956), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1676), .CK(clk),
.RN(n7019), .Q(FPMULT_Op_MX[18]), .QN(n6856) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[3]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1836), .CK(clk), .RN(
n6936), .Q(FPADDSUB_intDY_EWSW[7]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1827), .CK(clk), .RN(
n6930), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1841), .CK(clk), .RN(
n6936), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1819), .CK(clk), .RN(
n6932), .Q(FPADDSUB_intDY_EWSW[24]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1834), .CK(clk), .RN(
n6937), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1815), .CK(clk), .RN(
n6932), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1830), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n2434) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1824), .CK(clk), .RN(
n6930), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n2428) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1823), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n2393) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1831), .CK(clk), .RN(
n6943), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n2452) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1829), .CK(clk), .RN(
n6950), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n2400) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1505), .CK(
clk), .RN(n2288), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1807), .CK(clk), .RN(n6930), .Q(FPADDSUB_Data_array_SWR[19]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1808), .CK(clk), .RN(n2360), .Q(FPADDSUB_Data_array_SWR[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SFG[11]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1810), .CK(clk), .RN(n6936), .Q(FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1809), .CK(clk), .RN(n6936), .Q(FPADDSUB_Data_array_SWR[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1262), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1266), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1826), .CK(clk), .RN(
n6950), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n2394) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1210), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SFG[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1218), .CK(clk), .RN(n6964),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1222), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SFG[19]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1230), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SFG[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1242), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SFG[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1226), .CK(clk), .RN(n6964),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1246), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1258), .CK(clk), .RN(n6962),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1940), .CK(clk), .RN(
n6937), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n6653) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1799), .CK(clk), .RN(n6930), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1214), .CK(clk), .RN(n6963),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1206), .CK(clk), .RN(n6964),
.Q(FPADDSUB_DMP_SFG[22]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2077), .CK(clk), .RN(
n2340), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n6666) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2148), .CK(clk), .RN(
n6928), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n6639) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1338), .CK(clk), .RN(
n6955), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n6718) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1335), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1938), .CK(clk), .RN(
n2340), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n2418) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1796), .CK(clk), .RN(n6933),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1923), .CK(clk), .RN(
n6943), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n2255) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1930), .CK(clk), .RN(
n6932), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n2259) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1955), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1919), .CK(clk), .RN(
n2360), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n2257) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1916), .CK(clk), .RN(
n6950), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n6707) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1345), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n6720) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1914), .CK(clk), .RN(
n6950), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n2265) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1347), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]), .QN(n6719) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1813), .CK(clk), .RN(
n6928), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n2413) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1334), .CK(clk), .RN(
n6966), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n6649) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1924), .CK(clk), .RN(
n6943), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n2264) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n6934),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n6738) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1915), .CK(clk), .RN(
n6934), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n6698) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1953), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1927), .CK(clk), .RN(
n6929), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n2258) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1933), .CK(clk), .RN(
n6934), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n2404) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1797), .CK(clk), .RN(n6937), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1921), .CK(clk), .RN(
n6950), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n2204) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1585), .CK(clk), .RN(
n2291), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1952), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1959), .CK(clk), .RN(
n7006), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX2TS R_12 ( .D(n1658), .CK(clk), .RN(n7019), .Q(FPMULT_Op_MX[0]), .QN(
n6688) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1340), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n6632) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_29_ ( .D(n1558), .CK(
clk), .RN(n4559), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_35_ ( .D(n1564), .CK(
clk), .RN(n6981), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1518), .CK(
clk), .RN(n2288), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1526), .CK(
clk), .RN(n2291), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1520), .CK(
clk), .RN(n7011), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1522), .CK(
clk), .RN(n2290), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1337), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1428), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1438), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1521), .CK(
clk), .RN(n2290), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1527), .CK(
clk), .RN(n2290), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2078), .CK(clk), .RN(
n6958), .Q(FPADDSUB_left_right_SHT2), .QN(n2267) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1517), .CK(
clk), .RN(n7012), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1519), .CK(
clk), .RN(n2380), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1941), .CK(clk), .RN(
n6936), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n2260) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_31_ ( .D(n1560), .CK(
clk), .RN(n2385), .Q(FPMULT_P_Sgf[31]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1331), .CK(clk), .RN(
n4555), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n2248) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1686), .CK(clk),
.RN(n7015), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n6675) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(
n6957), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n6676) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1688), .CK(clk),
.RN(n7012), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n6678) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1956), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1957), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1958), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1463), .CK(clk), .RN(n6938),
.Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1349), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n6732) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_24_ ( .D(n1553), .CK(
clk), .RN(n4560), .Q(FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_25_ ( .D(n1554), .CK(
clk), .RN(n4559), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_27_ ( .D(n1556), .CK(
clk), .RN(n4561), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1911), .CK(clk), .RN(
n2360), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n6708) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1912), .CK(clk), .RN(
n6928), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n6706) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1348), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n6647) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1805), .CK(clk), .RN(n6937), .Q(FPADDSUB_Data_array_SWR[17]), .QN(n6729) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1342), .CK(clk), .RN(
n6955), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n6735) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1794), .CK(clk), .RN(n6933),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1321), .CK(clk), .RN(
n6935), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n6696) );
DFFRX1TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1352), .CK(clk), .RN(n6957),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1656), .CK(clk),
.RN(n7017), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1733), .CK(clk), .RN(
n6969), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1681), .CK(clk),
.RN(n2295), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1802), .CK(clk), .RN(n6932), .Q(FPADDSUB_Data_array_SWR[14]), .QN(n6714) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1588), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1590), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1591), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1592), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1593), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1649), .CK(clk),
.RN(n2293), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n6939),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n6967),
.Q(operation_reg[0]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1937), .CK(clk), .RN(
n6933), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n2398) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(
n6957), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n6672) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(
n6957), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n6677) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n6673) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(
n6957), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n6674) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1769), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2069), .CK(clk), .RN(n6987), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2051), .CK(clk), .RN(n4563), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2066), .CK(clk), .RN(n6990), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2063), .CK(clk), .RN(n6967), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2036), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2042), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2030), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2024), .CK(clk), .RN(n6973), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2033), .CK(clk), .RN(n6974), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2054), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2021), .CK(clk), .RN(n6976), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2012), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2015), .CK(clk), .RN(n6978), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1881), .CK(clk), .RN(
n6974), .QN(n2414) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2046), .CK(clk), .RN(n6987), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2070), .CK(clk), .RN(n6988), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2073), .CK(clk), .RN(n6980), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2052), .CK(clk), .RN(n6990), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2067), .CK(clk), .RN(n6967), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2064), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2037), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2043), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2031), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2040), .CK(clk), .RN(n6972), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2049), .CK(clk), .RN(n6973), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2025), .CK(clk), .RN(n6973), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2055), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2061), .CK(clk), .RN(n6976), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2022), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2013), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2016), .CK(clk), .RN(n6978), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2010), .CK(clk), .RN(n6998), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2019), .CK(clk), .RN(n6998), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2028), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1730), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1770), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1773), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1776), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1779), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1782), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1785), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2045), .CK(clk), .RN(n6987), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2072), .CK(clk), .RN(n6988), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1908), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2039), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2048), .CK(clk), .RN(n6972), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2060), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2009), .CK(clk), .RN(n6997), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2018), .CK(clk), .RN(n6998), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2027), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1654), .CK(clk),
.RN(n7017), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1995), .CK(clk), .RN(
n6986), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1961), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(
n6957), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n6679) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2058), .CK(clk), .RN(n6986), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2007), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1418), .CK(clk), .RN(
n6966), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1250), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1316), .CK(clk), .RN(
n6935), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1279), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SFG[9]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2139), .CK(clk), .RN(n6995),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n6682) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2142), .CK(clk), .RN(
n6966), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n6737) );
DFFRX1TS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1475), .CK(clk), .RN(
n6938), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1857), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n6741) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1423), .CK(clk), .RN(
n6966), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1433), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1448), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1453), .CK(clk), .RN(
n6964), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFSX1TS R_143 ( .D(n6845), .CK(clk), .SN(n4560), .Q(n7034) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1936), .CK(clk), .RN(
n6937), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n2429) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1934), .CK(clk), .RN(
n6936), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n2432) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1443), .CK(clk), .RN(
n6965), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_1_ ( .D(n1530), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[1]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_8_ ( .D(n1537), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_9_ ( .D(n1538), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[9]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_20_ ( .D(n1549), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_0_ ( .D(n1529), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[0]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1764), .CK(clk), .RN(
n6980), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n6947), .Q(result_add_subt[7]), .QN(n2271) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n6944), .Q(result_add_subt[6]), .QN(n2270) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n6943), .Q(result_add_subt[4]), .QN(n2269) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2127), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2131), .CK(clk), .RN(n6994), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2133), .CK(clk), .RN(n6994), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n6996), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n2303), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n7010), .Q(
dataA[29]) );
DFFRX1TS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n6996), .Q(
dataB[25]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2122), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2129), .CK(clk), .RN(n6994), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_13_ ( .D(n1542), .CK(
clk), .RN(n7010), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1596), .CK(clk),
.RN(n7017), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2123), .CK(clk), .RN(n6993), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n6996), .Q(
dataB[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1837), .CK(clk), .RN(
n6934), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1833), .CK(clk), .RN(
n6934), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1816), .CK(clk), .RN(
n2360), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1822), .CK(clk), .RN(
n6930), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n2417) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1821), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n2427) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1843), .CK(clk), .RN(
n6936), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1820), .CK(clk), .RN(
n6928), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n2422) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1825), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n2433) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1828), .CK(clk), .RN(
n6930), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n2395) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1835), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n2403) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1804), .CK(clk), .RN(n6937), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1803), .CK(clk), .RN(n6933), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n6930), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1818), .CK(clk), .RN(
n6929), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n2409) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1817), .CK(clk), .RN(
n6943), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n2411) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1800), .CK(clk), .RN(n6933), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1842), .CK(clk), .RN(
n6937), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n6715) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1932), .CK(clk), .RN(
n6937), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n2256) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1922), .CK(clk), .RN(
n6950), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n2231) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1928), .CK(clk), .RN(
n2360), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n2415) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1814), .CK(clk), .RN(
n6929), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n2399) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n7023), .CK(clk),
.RN(n6995), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1917), .CK(clk), .RN(
n6933), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n6651) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1506), .CK(
clk), .RN(n2290), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1795), .CK(clk), .RN(n6937),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1939), .CK(clk), .RN(
n6936), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n2263) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2075), .CK(clk), .RN(
n2340), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n6637) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_30_ ( .D(n1559), .CK(
clk), .RN(n4560), .Q(FPMULT_P_Sgf[30]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1332), .CK(clk), .RN(
n6935), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1728), .CK(clk), .RN(
n2340), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1344), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n6695) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1341), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2149), .CK(
clk), .RN(n6932), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n6724) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1464), .CK(clk), .RN(n6938),
.Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1793), .CK(clk), .RN(n6932),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1339), .CK(clk), .RN(
n6955), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n6635) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_26_ ( .D(n1555), .CK(
clk), .RN(n2385), .Q(FPMULT_P_Sgf[26]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(
n6954), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n6648) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1791), .CK(clk), .RN(n6938),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1811), .CK(clk), .RN(n6936), .Q(FPADDSUB_Data_array_SWR[23]), .QN(n2449) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1925), .CK(clk), .RN(
n6928), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n2430) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n6781) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n6780) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1682), .CK(clk),
.RN(n2292), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n6777) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(
n6957), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n6643) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1731), .CK(clk), .RN(
n2340), .Q(FPADDSUB_intAS) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1935), .CK(clk), .RN(
n6934), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n2426) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n6997),
.Q(operation_reg[1]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n6721) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n6733) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1812), .CK(clk), .RN(n6936), .Q(FPADDSUB_Data_array_SWR[24]), .QN(n6709) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n6700) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1651), .CK(clk),
.RN(n2293), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1963), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n6734) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1766), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2057), .CK(clk), .RN(n6986), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1775), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1772), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1781), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1778), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2006), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1650), .CK(clk),
.RN(n2293), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1784), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1729), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2143), .CK(clk), .RN(
n6966), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n6657) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1410), .CK(clk), .RN(
n6935), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2191), .CK(
clk), .RN(n6943), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n6684) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2147), .CK(clk), .RN(
n6929), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n6796) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_17_ ( .D(n1546), .CK(
clk), .RN(n4561), .Q(FPMULT_P_Sgf[17]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n6995), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1855), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n6740) );
DFFSX1TS R_142 ( .D(n6846), .CK(clk), .SN(n2303), .Q(n7033) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n6994),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n2268) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_3_ ( .D(n1532), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_2_ ( .D(n1531), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[2]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n6996), .Q(
dataB[28]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_18_ ( .D(n1547), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_14_ ( .D(n1543), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_7_ ( .D(n1536), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[7]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_22_ ( .D(n1551), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[22]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_21_ ( .D(n1550), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_10_ ( .D(n1539), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_6_ ( .D(n1535), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_4_ ( .D(n1533), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2116), .CK(clk), .RN(n6992), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_5_ ( .D(n1534), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_19_ ( .D(n1548), .CK(
clk), .RN(n6983), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_12_ ( .D(n1541), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_11_ ( .D(n1540), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[11]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2136), .CK(clk), .RN(n6994),
.Q(FPSENCOS_cont_var_out[1]), .QN(n6650) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n7010), .Q(
dataB[23]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n6997), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n2302), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n6996), .Q(
dataB[26]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n2303), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n2302), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n4559), .Q(
dataB[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1413), .CK(clk), .RN(n6942),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_23_ ( .D(n1552), .CK(
clk), .RN(n6981), .Q(FPMULT_P_Sgf[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1620), .CK(clk), .RN(
n7017), .Q(FPMULT_Add_result[0]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_16_ ( .D(n1545), .CK(
clk), .RN(n6982), .Q(FPMULT_P_Sgf[16]) );
DFFSX1TS R_93 ( .D(n7050), .CK(clk), .SN(n2341), .Q(n6870) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1343), .CK(clk), .RN(
n6955), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n6693) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1684), .CK(clk),
.RN(n2293), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1685), .CK(clk),
.RN(n2290), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1687), .CK(clk),
.RN(n2288), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1683), .CK(clk),
.RN(n2291), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_28_ ( .D(n1557), .CK(
clk), .RN(n4563), .Q(FPMULT_P_Sgf[28]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n6779) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n6778) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1652), .CK(clk),
.RN(n2292), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1589), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(
n7014), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1653), .CK(clk),
.RN(n7017), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1655), .CK(clk),
.RN(n7017), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1993), .CK(clk), .RN(
n6975), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1985), .CK(clk), .RN(
n6970), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1981), .CK(clk), .RN(
n6969), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2001), .CK(clk), .RN(
n6990), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2003), .CK(clk), .RN(
n6987), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1997), .CK(clk), .RN(
n6975), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1989), .CK(clk), .RN(
n6972), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2005), .CK(clk), .RN(
n6988), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1987), .CK(clk), .RN(
n6986), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1727), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1792), .CK(clk), .RN(n6934),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1967), .CK(clk), .RN(
n6978), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1965), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1971), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1979), .CK(clk), .RN(
n6974), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1973), .CK(clk), .RN(
n6973), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1977), .CK(clk), .RN(
n6970), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1999), .CK(clk), .RN(
n6967), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(
n4563), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n6784) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(
n6958), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n6783) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1975), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1969), .CK(clk), .RN(
n6998), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1983), .CK(clk), .RN(
n6971), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1943), .CK(clk), .RN(
n6968), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n6702) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n6701) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n6712) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(
n6959), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n6722) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2034), .CK(clk), .RN(n6974), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1895), .CK(clk), .RN(
n6975), .QN(n2410) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1732), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFSX1TS R_158 ( .D(n7020), .CK(clk), .SN(n6932), .Q(n6841) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1323), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1307), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1300), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1272), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n6961),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1286), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1234), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1293), .CK(clk), .RN(n6960),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1315), .CK(clk), .RN(
n6935), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7028), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .QN(
DP_OP_498J1_124_4426_n152) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1675), .CK(clk),
.RN(n7012), .Q(FPMULT_Op_MX[17]), .QN(n2442) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1920), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n2262) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1926), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n2261) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2138), .CK(clk), .RN(n6995),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n2230) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1637), .CK(clk),
.RN(n2296), .Q(FPMULT_Op_MY[11]), .QN(n2443) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1666), .CK(clk),
.RN(n2381), .Q(FPMULT_Op_MX[8]), .QN(n2250) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1678), .CK(clk),
.RN(n7011), .Q(FPMULT_Op_MX[20]), .QN(n2247) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1633), .CK(clk),
.RN(n7015), .Q(n6641), .QN(n6668) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1679), .CK(clk),
.RN(n7011), .Q(n6640), .QN(n6680) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7029), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[0]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1646), .CK(clk),
.RN(n2293), .Q(n2223), .QN(n2237) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1644), .CK(clk),
.RN(n2292), .Q(n6662), .QN(n6665) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1635), .CK(clk),
.RN(n2296), .Q(n2228), .QN(n2235) );
DFFSX2TS DP_OP_501J1_127_1459_R_120 ( .D(n6621), .CK(clk), .SN(n4556), .Q(
DP_OP_501J1_127_1459_n794) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[11])
);
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[1])
);
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[4])
);
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7027), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_Result[0]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6829), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[1]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[9])
);
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[4])
);
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_Result[5]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]) );
DFFSX1TS R_0 ( .D(FPMULT_inst_RecursiveKOA_Result[38]), .CK(clk), .SN(n2384),
.Q(n6919) );
DFFRXLTS R_1 ( .D(n1567), .CK(clk), .RN(n6980), .Q(n6918) );
DFFSX1TS R_3 ( .D(FPMULT_inst_RecursiveKOA_Result[40]), .CK(clk), .SN(n6979),
.Q(n6917) );
DFFRXLTS R_4 ( .D(n1569), .CK(clk), .RN(n6981), .Q(n6916) );
DFFSX1TS R_6 ( .D(FPMULT_inst_RecursiveKOA_Result[44]), .CK(clk), .SN(n6979),
.Q(n6915) );
DFFRXLTS R_7 ( .D(n1573), .CK(clk), .RN(n7010), .Q(n6914) );
DFFSX1TS R_9 ( .D(FPMULT_inst_RecursiveKOA_Result[34]), .CK(clk), .SN(n2385),
.Q(n6913) );
DFFRXLTS R_10 ( .D(n1563), .CK(clk), .RN(n2384), .Q(n6912) );
DFFSX1TS R_16 ( .D(n6911), .CK(clk), .SN(n7012), .QN(n6828) );
DFFSX1TS R_18 ( .D(FPMULT_inst_RecursiveKOA_Result[43]), .CK(clk), .SN(n6989), .Q(n6910) );
DFFRXLTS R_19 ( .D(n1572), .CK(clk), .RN(n4561), .Q(n6909) );
DFFSX1TS R_21 ( .D(FPMULT_inst_RecursiveKOA_Result[42]), .CK(clk), .SN(n2384), .Q(n6908) );
DFFRXLTS R_22 ( .D(n1571), .CK(clk), .RN(n6980), .Q(n6907) );
DFFSX1TS R_24 ( .D(FPMULT_inst_RecursiveKOA_Result[41]), .CK(clk), .SN(n6979), .Q(n6906) );
DFFRXLTS R_25 ( .D(n1570), .CK(clk), .RN(n7010), .Q(n6905) );
DFFSX1TS R_27 ( .D(FPMULT_inst_RecursiveKOA_Result[36]), .CK(clk), .SN(n2385), .Q(n6904) );
DFFSX1TS R_30 ( .D(FPMULT_inst_RecursiveKOA_Result[37]), .CK(clk), .SN(n2385), .Q(n6902) );
DFFRXLTS R_31 ( .D(n1566), .CK(clk), .RN(n4560), .Q(n6901) );
DFFSX1TS R_33 ( .D(FPMULT_inst_RecursiveKOA_Result[46]), .CK(clk), .SN(n2384), .Q(n6900) );
DFFSX1TS R_35 ( .D(n7025), .CK(clk), .SN(n2384), .Q(n6899) );
DFFSX1TS R_37 ( .D(FPMULT_inst_RecursiveKOA_Result[39]), .CK(clk), .SN(n6984), .Q(n6897) );
DFFRXLTS R_38 ( .D(n1568), .CK(clk), .RN(n6981), .Q(n6896) );
DFFSX1TS R_41 ( .D(FPMULT_inst_RecursiveKOA_Result[47]), .CK(clk), .SN(n2384), .Q(n6894) );
DFFRXLTS R_42 ( .D(n1694), .CK(clk), .RN(n4559), .Q(n6893) );
DFFSX1TS R_43 ( .D(n6181), .CK(clk), .SN(n6989), .Q(n6892) );
DFFSX1TS R_44 ( .D(FPMULT_inst_RecursiveKOA_Result[45]), .CK(clk), .SN(n6979), .Q(n6891) );
DFFRXLTS R_45 ( .D(n1574), .CK(clk), .RN(n4563), .Q(n6890) );
DFFSX1TS R_48 ( .D(n6895), .CK(clk), .SN(n7015), .QN(n6795) );
DFFSX1TS R_50 ( .D(n7069), .CK(clk), .SN(n6979), .QN(n6762) );
DFFSX1TS R_51 ( .D(n7072), .CK(clk), .SN(n6989), .QN(n6765) );
DFFSX1TS R_52 ( .D(n7070), .CK(clk), .SN(n2384), .QN(n6763) );
DFFSX1TS R_53 ( .D(n7071), .CK(clk), .SN(n6989), .QN(n6764) );
DFFSX1TS R_54 ( .D(n7068), .CK(clk), .SN(n2385), .QN(n6761) );
DFFSX1TS R_55 ( .D(n7055), .CK(clk), .SN(n6984), .QN(n6749) );
DFFSX1TS R_56 ( .D(n7057), .CK(clk), .SN(n2385), .QN(n6751) );
DFFSX1TS R_57 ( .D(n7064), .CK(clk), .SN(n6985), .QN(n6758) );
DFFSX1TS R_58 ( .D(n7067), .CK(clk), .SN(n6985), .QN(n6760) );
DFFSX1TS R_59 ( .D(n7059), .CK(clk), .SN(n6985), .QN(n6753) );
DFFSX1TS R_60 ( .D(n7062), .CK(clk), .SN(n6985), .QN(n6756) );
DFFSX1TS R_61 ( .D(n7065), .CK(clk), .SN(n6985), .QN(n6759) );
DFFSX1TS R_62 ( .D(n7061), .CK(clk), .SN(n6985), .QN(n6755) );
DFFSX1TS R_64 ( .D(n7056), .CK(clk), .SN(n6985), .QN(n6750) );
DFFSX1TS R_65 ( .D(n7060), .CK(clk), .SN(n6986), .QN(n6754) );
DFFSX1TS R_66 ( .D(n7052), .CK(clk), .SN(n6987), .QN(n6747) );
DFFSX1TS R_67 ( .D(n7051), .CK(clk), .SN(n6988), .QN(n6746) );
DFFSX1TS R_68 ( .D(n7058), .CK(clk), .SN(n2384), .QN(n6752) );
DFFSX1TS R_69 ( .D(n7053), .CK(clk), .SN(n6990), .QN(n6748) );
DFFSX1TS R_70 ( .D(n7054), .CK(clk), .SN(n6967), .QN(n6745) );
DFFSX1TS R_71 ( .D(n7080), .CK(clk), .SN(n7001), .QN(n6772) );
DFFSX1TS R_72 ( .D(n7079), .CK(clk), .SN(n7002), .QN(n6771) );
DFFSX1TS R_73 ( .D(n7078), .CK(clk), .SN(n7002), .QN(n6770) );
DFFSX1TS R_74 ( .D(n7077), .CK(clk), .SN(n7003), .QN(n6769) );
DFFSX1TS R_75 ( .D(n7076), .CK(clk), .SN(n7004), .QN(n6768) );
DFFSX1TS R_76 ( .D(n7075), .CK(clk), .SN(n7005), .QN(n6767) );
DFFSX1TS R_77 ( .D(n7074), .CK(clk), .SN(n7005), .QN(n6766) );
DFFSX1TS R_79 ( .D(n7085), .CK(clk), .SN(n6942), .Q(n6881), .QN(n6661) );
DFFSX1TS R_80 ( .D(n7084), .CK(clk), .SN(n6942), .Q(n6880), .QN(n6660) );
DFFSX1TS R_81 ( .D(n7083), .CK(clk), .SN(n6942), .Q(n6879), .QN(n6659) );
DFFRXLTS R_82 ( .D(n1673), .CK(clk), .RN(n2290), .QN(n6885) );
DFFSX1TS R_86 ( .D(n7043), .CK(clk), .SN(n6934), .Q(n6876) );
DFFSX1TS R_87 ( .D(n7042), .CK(clk), .SN(n2360), .Q(n6875) );
DFFSX1TS R_85 ( .D(n7049), .CK(clk), .SN(n6928), .Q(n6877) );
DFFSX1TS R_90 ( .D(n7041), .CK(clk), .SN(n6930), .Q(n6873) );
DFFSX1TS R_89 ( .D(n7048), .CK(clk), .SN(n6930), .Q(n6874) );
DFFSX1TS R_91 ( .D(n7040), .CK(clk), .SN(n6931), .Q(n6872) );
DFFSX1TS R_94 ( .D(n7045), .CK(clk), .SN(n2341), .Q(n6869) );
DFFSX1TS R_95 ( .D(n7044), .CK(clk), .SN(n2341), .Q(n6868) );
DFFSX1TS R_92 ( .D(n7022), .CK(clk), .SN(n2341), .Q(n6871) );
DFFSX1TS R_97 ( .D(n7047), .CK(clk), .SN(n2341), .Q(n6867) );
DFFSX1TS R_98 ( .D(n7039), .CK(clk), .SN(n2341), .Q(n6866) );
DFFSX1TS R_99 ( .D(n7038), .CK(clk), .SN(n2341), .Q(n6865) );
DFFSX1TS R_101 ( .D(n7046), .CK(clk), .SN(n6943), .Q(n6864) );
DFFSX1TS R_102 ( .D(n7037), .CK(clk), .SN(n6950), .Q(n6863) );
DFFSX1TS R_103 ( .D(n7036), .CK(clk), .SN(n6933), .Q(n6862) );
DFFRX1TS R_106 ( .D(FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk),
.RN(n6995), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFSX1TS R_104 ( .D(FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk),
.SN(n7009), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSX1TS R_109 ( .D(n6898), .CK(clk), .SN(n7013), .QN(n6794) );
DFFRXLTS R_111 ( .D(n1660), .CK(clk), .RN(n2289), .QN(n6859) );
DFFSX1TS R_115 ( .D(n7073), .CK(clk), .SN(n6984), .QN(n6773) );
DFFSX1TS R_116 ( .D(n7066), .CK(clk), .SN(n2385), .QN(n6774) );
DFFSX1TS R_117 ( .D(n7081), .CK(clk), .SN(n7000), .QN(n6744) );
DFFSX1TS R_118 ( .D(n6889), .CK(clk), .SN(n7011), .QN(n6830) );
DFFSX1TS R_126 ( .D(FPMULT_inst_RecursiveKOA_Result[32]), .CK(clk), .SN(
n6979), .Q(n6851) );
DFFRXLTS R_127 ( .D(n1561), .CK(clk), .RN(n4560), .Q(n6850) );
DFFSX1TS R_129 ( .D(FPMULT_inst_RecursiveKOA_Result[33]), .CK(clk), .SN(
n6979), .Q(n6849) );
DFFRXLTS R_130 ( .D(n1562), .CK(clk), .RN(n4561), .Q(n6848) );
DFFSX1TS R_153 ( .D(n6844), .CK(clk), .SN(n6984), .Q(n7032) );
DFFSX1TS R_157 ( .D(n7021), .CK(clk), .SN(n6930), .Q(n6842) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1528), .CK(clk), .RN(n2290), .Q(
FPMULT_FSM_selector_C), .QN(n6739) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_Result[3]) );
DFFSX1TS DP_OP_501J1_127_1459_R_152 ( .D(n6626), .CK(clk), .SN(n7012), .Q(
DP_OP_501J1_127_1459_n782) );
DFFSX1TS DP_OP_501J1_127_1459_R_151 ( .D(n6625), .CK(clk), .SN(n7012), .Q(
DP_OP_501J1_127_1459_n741) );
DFFSX1TS DP_OP_501J1_127_1459_R_150 ( .D(n6624), .CK(clk), .SN(n7015), .QN(
n6627) );
DFFSX1TS DP_OP_501J1_127_1459_R_135 ( .D(n6623), .CK(clk), .SN(n7011), .Q(
DP_OP_501J1_127_1459_n781), .QN(n6628) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[5])
);
DFFSX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n6737), .CK(clk), .SN(n6931), .Q(
n6717), .QN(ready_add_subt) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1839), .CK(clk), .RN(
n6931), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1424), .CK(clk), .RN(
n6966), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1419), .CK(clk), .RN(
n6966), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[5])
);
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1636), .CK(clk),
.RN(n2296), .Q(n2206), .QN(n2236) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1669), .CK(clk),
.RN(n7016), .QN(n2226) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[4]) );
DFFHQX8TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6726), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX8TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6793), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n6995), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1663), .CK(clk),
.RN(n2380), .Q(FPMULT_Op_MX[5]), .QN(n2445) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1648), .CK(clk),
.RN(n2293), .Q(FPMULT_Op_MY[22]), .QN(n2225) );
DFFHQX8TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[4])
);
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1319), .CK(clk), .RN(
n6935), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n6703) );
ADDFHX2TS intadd_3_U2 ( .A(mult_x_309_n14), .B(intadd_3_B_6_), .CI(
intadd_3_n2), .CO(intadd_3_n1), .S(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1409), .CK(clk), .RN(
n6956), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(
n6957), .Q(FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(n6694) );
DFFSX2TS R_159 ( .D(n7026), .CK(clk), .SN(n4561), .Q(n2211) );
ADDFHX2TS DP_OP_26J1_129_1325_U2 ( .A(n6667), .B(FPADDSUB_DMP_exp_NRM2_EW[7]), .CI(DP_OP_26J1_129_1325_n2), .CO(DP_OP_26J1_129_1325_n1), .S(
FPADDSUB_exp_rslt_NRM2_EW1[7]) );
ADDFHX2TS DP_OP_234J1_132_4955_U5 ( .A(DP_OP_234J1_132_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .CI(DP_OP_234J1_132_4955_n5), .CO(
DP_OP_234J1_132_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
ADDFHX2TS DP_OP_234J1_132_4955_U4 ( .A(DP_OP_234J1_132_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .CI(DP_OP_234J1_132_4955_n4), .CO(
DP_OP_234J1_132_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1647), .CK(clk),
.RN(n2293), .Q(FPMULT_Op_MY[21]), .QN(n2229) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1634), .CK(clk),
.RN(n2296), .Q(n2207), .QN(n2234) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1645), .CK(clk),
.RN(n2292), .Q(n6633), .QN(n6669) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1611), .CK(clk), .RN(
n2380), .Q(FPMULT_Add_result[9]), .QN(n6813) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1514), .CK(
clk), .RN(n2380), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n6689) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1693), .CK(clk), .RN(n4563),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n6686) );
DFFRXLTS FPMULT_inst_RecursiveKOA_EVEN1_finalreg_Q_reg_15_ ( .D(n1544), .CK(
clk), .RN(n7010), .Q(FPMULT_P_Sgf[15]) );
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]) );
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[9])
);
DFFRXLTS R_108 ( .D(n6861), .CK(clk), .RN(n7009), .Q(n7035) );
DFFRXLTS R_154 ( .D(n6843), .CK(clk), .RN(n6997), .Q(n7031) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[8])
);
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[7])
);
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[6])
);
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_Result[1]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_Result[2]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6725), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7030), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[2]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[2])
);
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[5]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[6])
);
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]) );
DFFHQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[10])
);
DFFQX1TS FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]) );
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[0])
);
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[2])
);
DFFQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]) );
DFFHQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[3])
);
DFFQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[8])
);
DFFQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]) );
DFFQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFQX2TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[5])
);
DFFQX4TS FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[7])
);
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1320), .CK(clk), .RN(
n2341), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n6792) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1662), .CK(clk),
.RN(n7011), .Q(n2194), .QN(n6852) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1640), .CK(clk),
.RN(n2295), .Q(FPMULT_Op_MY[14]), .QN(n6883) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1642), .CK(clk),
.RN(n2295), .Q(FPMULT_Op_MY[16]), .QN(n6887) );
CMPR32X2TS DP_OP_26J1_129_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n6667), .C(DP_OP_26J1_129_1325_n18), .CO(DP_OP_26J1_129_1325_n8), .S(
FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J1_129_1325_U8 ( .A(DP_OP_26J1_129_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J1_129_1325_n8), .CO(
DP_OP_26J1_129_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J1_129_1325_U7 ( .A(DP_OP_26J1_129_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J1_129_1325_n7), .CO(
DP_OP_26J1_129_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2146), .CK(clk), .RN(
n2360), .Q(n7086), .QN(n6839) );
CMPR32X2TS DP_OP_26J1_129_1325_U6 ( .A(DP_OP_26J1_129_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J1_129_1325_n6), .CO(
DP_OP_26J1_129_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J1_129_1325_U5 ( .A(DP_OP_26J1_129_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J1_129_1325_n5), .CO(
DP_OP_26J1_129_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J1_129_1325_U4 ( .A(n6667), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J1_129_1325_n4), .CO(
DP_OP_26J1_129_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_234J1_132_4955_U9 ( .A(DP_OP_234J1_132_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J1_132_4955_n9), .CO(
DP_OP_234J1_132_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_26J1_129_1325_U3 ( .A(n6667), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J1_129_1325_n3), .CO(
DP_OP_26J1_129_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_234J1_132_4955_U7 ( .A(DP_OP_234J1_132_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J1_132_4955_n7), .CO(
DP_OP_234J1_132_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR42X1TS DP_OP_501J1_127_1459_U454 ( .A(DP_OP_501J1_127_1459_n522), .B(
DP_OP_501J1_127_1459_n528), .C(DP_OP_501J1_127_1459_n534), .D(
DP_OP_501J1_127_1459_n496), .ICI(DP_OP_501J1_127_1459_n499), .S(
DP_OP_501J1_127_1459_n494), .ICO(DP_OP_501J1_127_1459_n492), .CO(
DP_OP_501J1_127_1459_n493) );
CMPR32X2TS intadd_6_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n6663), .C(intadd_6_CI), .CO(intadd_6_n3), .S(intadd_6_SUM_0_) );
CMPR32X2TS intadd_3_U7 ( .A(mult_x_309_n37), .B(intadd_3_B_1_), .C(
intadd_3_n7), .CO(intadd_3_n6), .S(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR42X1TS DP_OP_501J1_127_1459_U451 ( .A(DP_OP_501J1_127_1459_n533), .B(
DP_OP_501J1_127_1459_n527), .C(DP_OP_501J1_127_1459_n495), .D(
DP_OP_501J1_127_1459_n492), .ICI(DP_OP_501J1_127_1459_n489), .S(
DP_OP_501J1_127_1459_n487), .ICO(DP_OP_501J1_127_1459_n485), .CO(
DP_OP_501J1_127_1459_n486) );
CMPR32X2TS intadd_3_U6 ( .A(mult_x_309_n36), .B(mult_x_309_n30), .C(
intadd_3_n6), .CO(intadd_3_n5), .S(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_3_U5 ( .A(mult_x_309_n29), .B(mult_x_309_n23), .C(
intadd_3_n5), .CO(intadd_3_n4), .S(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_4_U4 ( .A(n6879), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(
intadd_4_CI), .CO(intadd_4_n3), .S(intadd_4_SUM_0_) );
CMPR32X2TS intadd_4_U3 ( .A(n6880), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(
intadd_4_n3), .CO(intadd_4_n2), .S(intadd_4_SUM_1_) );
CMPR32X2TS intadd_3_U3 ( .A(mult_x_309_n17), .B(mult_x_309_n15), .C(
intadd_3_n3), .CO(intadd_3_n2), .S(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS DP_OP_234J1_132_4955_U3 ( .A(DP_OP_234J1_132_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J1_132_4955_n3), .CO(
DP_OP_234J1_132_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS intadd_4_U2 ( .A(n6881), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(
intadd_4_n2), .CO(intadd_4_n1), .S(intadd_4_SUM_2_) );
XOR2X1TS U2217 ( .A(n3722), .B(n4055), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9) );
XNOR2X2TS U2218 ( .A(n2218), .B(n2219), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
XOR2X2TS U2219 ( .A(n3752), .B(n3751), .Y(
FPMULT_inst_RecursiveKOA_Result[46]) );
XOR2X2TS U2220 ( .A(n3764), .B(n3763), .Y(
FPMULT_inst_RecursiveKOA_Result[42]) );
XOR2X2TS U2221 ( .A(n3113), .B(n2208), .Y(
FPMULT_inst_RecursiveKOA_Result[40]) );
XNOR2X2TS U2222 ( .A(n3740), .B(n3739), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13) );
INVX2TS U2223 ( .A(n4936), .Y(n6323) );
INVX2TS U2224 ( .A(n4613), .Y(n6253) );
INVX2TS U2225 ( .A(n6300), .Y(n6310) );
INVX2TS U2226 ( .A(n6300), .Y(n6336) );
BUFX3TS U2227 ( .A(n4965), .Y(n7020) );
INVX2TS U2228 ( .A(n2308), .Y(n2310) );
INVX2TS U2229 ( .A(n3756), .Y(n3758) );
NAND2X2TS U2230 ( .A(n5078), .B(n5892), .Y(n6489) );
AOI21X2TS U2231 ( .A0(n3982), .A1(n3981), .B0(n3980), .Y(n3986) );
AOI21X1TS U2232 ( .A0(n4203), .A1(n4202), .B0(n4201), .Y(n4204) );
OAI21X1TS U2233 ( .A0(n5352), .A1(n5341), .B0(n5340), .Y(n5345) );
AOI222X1TS U2234 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n4978) );
AOI222X1TS U2235 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n5000)
);
AOI222X1TS U2236 ( .A0(n6282), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n5004)
);
AOI222X1TS U2237 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n5006)
);
AOI222X1TS U2238 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n5010)
);
AOI222X1TS U2239 ( .A0(n6282), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n5003)
);
AOI222X1TS U2240 ( .A0(n6282), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n5005)
);
AOI222X1TS U2241 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n5002)
);
AOI222X1TS U2242 ( .A0(n6282), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n4999)
);
AOI222X1TS U2243 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n5008), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n5007), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n5001)
);
AOI211X1TS U2244 ( .A0(n6321), .A1(FPSENCOS_d_ff3_LUT_out[3]), .B0(n2249),
.C0(n6231), .Y(n4663) );
XOR2X1TS U2245 ( .A(n3420), .B(n3419), .Y(n3422) );
INVX2TS U2246 ( .A(n4936), .Y(n6326) );
INVX2TS U2247 ( .A(n5243), .Y(n2355) );
INVX2TS U2248 ( .A(n5179), .Y(n5262) );
INVX4TS U2249 ( .A(n3988), .Y(n4412) );
NOR2X1TS U2250 ( .A(n3987), .B(n4006), .Y(n3991) );
BUFX3TS U2251 ( .A(n6317), .Y(n6311) );
NOR2X2TS U2252 ( .A(n4200), .B(n4191), .Y(n4202) );
NOR2X2TS U2253 ( .A(n3760), .B(n3763), .Y(n3715) );
NOR2X2TS U2254 ( .A(n3754), .B(n3757), .Y(n3632) );
NOR2X2TS U2255 ( .A(n3753), .B(n3757), .Y(n3633) );
NOR2X2TS U2256 ( .A(n3759), .B(n3763), .Y(n3716) );
OAI21X1TS U2257 ( .A0(n4200), .A1(n4199), .B0(n4198), .Y(n4201) );
CMPR32X2TS U2258 ( .A(mult_x_313_n23), .B(mult_x_313_n25), .C(n3817), .CO(
n3824), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS U2259 ( .A(n3822), .B(n3821), .C(mult_x_313_n21), .CO(n3828), .S(
n3825) );
NOR2X4TS U2260 ( .A(n5014), .B(n5322), .Y(n4359) );
AND3X2TS U2261 ( .A(n6710), .B(FPSENCOS_cont_var_out[1]), .C(ready_add_subt),
.Y(n6256) );
NOR2X1TS U2262 ( .A(n5354), .B(n5359), .Y(n3566) );
CLKBUFX2TS U2263 ( .A(n4937), .Y(n4974) );
CLKBUFX2TS U2264 ( .A(n6384), .Y(n6419) );
INVX3TS U2265 ( .A(n3416), .Y(n5765) );
CLKINVX2TS U2266 ( .A(n4405), .Y(n2348) );
OAI21X2TS U2267 ( .A0(n4057), .A1(n4063), .B0(n4058), .Y(n3193) );
NAND2X2TS U2268 ( .A(n3975), .B(n3493), .Y(n3705) );
NAND2X2TS U2269 ( .A(n3975), .B(n3714), .Y(n3759) );
NAND2X2TS U2270 ( .A(n4190), .B(n4196), .Y(n4200) );
OAI21X1TS U2271 ( .A0(n4199), .A1(n3718), .B0(n3765), .Y(n3719) );
BUFX3TS U2272 ( .A(n2439), .Y(n5265) );
OR2X2TS U2273 ( .A(n4686), .B(operation[2]), .Y(n4687) );
NOR2X1TS U2274 ( .A(n3976), .B(n3491), .Y(n3492) );
BUFX3TS U2275 ( .A(n4538), .Y(n4960) );
BUFX3TS U2276 ( .A(n5821), .Y(n6485) );
NAND2X2TS U2277 ( .A(n4190), .B(n3767), .Y(n3769) );
AND2X2TS U2278 ( .A(n2196), .B(n4634), .Y(n4703) );
OR2X4TS U2279 ( .A(n6567), .B(n5294), .Y(n2439) );
BUFX3TS U2280 ( .A(n4338), .Y(n6421) );
NAND2X2TS U2281 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n6567), .Y(n4402) );
NOR2X1TS U2282 ( .A(n6710), .B(n6650), .Y(n5320) );
OR2X2TS U2283 ( .A(DP_OP_502J1_128_2852_n104), .B(DP_OP_502J1_128_2852_n102),
.Y(n5348) );
BUFX3TS U2284 ( .A(n6639), .Y(n5294) );
OR2X2TS U2285 ( .A(DP_OP_501J1_127_1459_n182), .B(DP_OP_501J1_127_1459_n189),
.Y(n4073) );
NOR2X6TS U2286 ( .A(n3527), .B(n3082), .Y(n3975) );
CLKINVX2TS U2287 ( .A(n3984), .Y(n3085) );
INVX3TS U2288 ( .A(n3711), .Y(n3977) );
NAND2BX2TS U2289 ( .AN(n3512), .B(n3511), .Y(n5078) );
INVX2TS U2290 ( .A(n2326), .Y(n6484) );
NAND2X2TS U2291 ( .A(n3321), .B(n3320), .Y(n6567) );
CLKINVX6TS U2292 ( .A(n3528), .Y(n3980) );
NAND2X1TS U2293 ( .A(DP_OP_501J1_127_1459_n190), .B(
DP_OP_501J1_127_1459_n196), .Y(n4077) );
NOR2BX2TS U2294 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n4628), .Y(n4552) );
NAND2X2TS U2295 ( .A(DP_OP_501J1_127_1459_n133), .B(
DP_OP_501J1_127_1459_n131), .Y(n3765) );
NOR2BX1TS U2296 ( .AN(n3510), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3511)
);
NAND2X1TS U2297 ( .A(n6391), .B(n3369), .Y(n3357) );
NAND2X1TS U2298 ( .A(n3305), .B(n3304), .Y(n3321) );
NOR2X4TS U2299 ( .A(n3997), .B(n3999), .Y(n4005) );
INVX2TS U2300 ( .A(n6477), .Y(n6478) );
AND2X2TS U2301 ( .A(n5016), .B(n5020), .Y(n6250) );
BUFX12TS U2302 ( .A(n2801), .Y(n3711) );
NAND2X1TS U2303 ( .A(n6644), .B(FPMULT_FS_Module_state_reg[0]), .Y(n5316) );
CMPR42X1TS U2304 ( .A(mult_x_313_n75), .B(mult_x_313_n55), .C(mult_x_313_n61), .D(mult_x_313_n68), .ICI(mult_x_313_n37), .S(mult_x_313_n36), .ICO(
mult_x_313_n34), .CO(mult_x_313_n35) );
NOR2X1TS U2305 ( .A(n5162), .B(n5161), .Y(n5452) );
NOR2X6TS U2306 ( .A(n3074), .B(n4013), .Y(n4006) );
NAND2X2TS U2307 ( .A(n3075), .B(n4017), .Y(n3993) );
OAI22X1TS U2308 ( .A0(n2205), .A1(n4255), .B0(n4249), .B1(n4257), .Y(
DP_OP_501J1_127_1459_n526) );
INVX2TS U2309 ( .A(n6577), .Y(n2325) );
CLKBUFX2TS U2310 ( .A(n7026), .Y(n6173) );
OAI2BB1X1TS U2311 ( .A0N(n3301), .A1N(n3300), .B0(n3299), .Y(n3305) );
CLKBUFX2TS U2312 ( .A(n6472), .Y(n6477) );
BUFX3TS U2313 ( .A(n6278), .Y(n6275) );
CMPR32X2TS U2314 ( .A(n5093), .B(n5092), .C(n5091), .CO(
DP_OP_500J1_126_2852_n130), .S(DP_OP_500J1_126_2852_n131) );
CMPR32X2TS U2315 ( .A(n4222), .B(n4221), .C(n4220), .CO(
DP_OP_501J1_127_1459_n191), .S(DP_OP_501J1_127_1459_n192) );
CMPR32X2TS U2316 ( .A(n4435), .B(n4436), .C(n4434), .CO(
DP_OP_502J1_128_2852_n130), .S(DP_OP_502J1_128_2852_n131) );
NAND2X1TS U2317 ( .A(DP_OP_501J1_127_1459_n197), .B(n3190), .Y(n4081) );
BUFX3TS U2318 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n6577) );
INVX2TS U2319 ( .A(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n6219) );
NAND2X1TS U2320 ( .A(n4896), .B(n4895), .Y(n4903) );
INVX2TS U2321 ( .A(n3418), .Y(n3064) );
INVX2TS U2322 ( .A(n6176), .Y(n7026) );
NAND2BXLTS U2323 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n4523),
.Y(n4611) );
CMPR42X2TS U2324 ( .A(DP_OP_501J1_127_1459_n216), .B(
DP_OP_501J1_127_1459_n140), .C(DP_OP_501J1_127_1459_n136), .D(
DP_OP_501J1_127_1459_n141), .ICI(DP_OP_501J1_127_1459_n137), .S(
DP_OP_501J1_127_1459_n134), .ICO(DP_OP_501J1_127_1459_n132), .CO(
DP_OP_501J1_127_1459_n133) );
NOR2X2TS U2325 ( .A(n5787), .B(n5795), .Y(n3026) );
INVX2TS U2326 ( .A(n4529), .Y(n6278) );
CMPR32X2TS U2327 ( .A(n4390), .B(n4391), .C(n4389), .CO(
DP_OP_500J1_126_2852_n111), .S(DP_OP_500J1_126_2852_n112) );
CMPR32X2TS U2328 ( .A(n4283), .B(n4282), .C(n4281), .CO(
DP_OP_501J1_127_1459_n149), .S(DP_OP_501J1_127_1459_n150) );
OAI2BB2XLTS U2329 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n3294), .A0N(n6544),
.A1N(n2422), .Y(n3295) );
CMPR32X2TS U2330 ( .A(n4619), .B(n4618), .C(n4617), .CO(
DP_OP_502J1_128_2852_n111), .S(DP_OP_502J1_128_2852_n112) );
NAND2X1TS U2331 ( .A(n3059), .B(n3058), .Y(n3060) );
NAND2X1TS U2332 ( .A(n6208), .B(n6209), .Y(n5013) );
NAND2X1TS U2333 ( .A(n2848), .B(n2847), .Y(n2849) );
NAND2X1TS U2334 ( .A(n2858), .B(n2857), .Y(n2859) );
INVX2TS U2335 ( .A(n2771), .Y(n2747) );
NOR2X1TS U2336 ( .A(n2217), .B(n6455), .Y(n4185) );
NAND2X2TS U2337 ( .A(n3024), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[1]),
.Y(n5788) );
CLKAND2X2TS U2338 ( .A(n2869), .B(n2868), .Y(n2870) );
NOR2X2TS U2339 ( .A(n3023), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[0]),
.Y(n5795) );
OAI21X2TS U2340 ( .A0(n2696), .A1(n2867), .B0(n2868), .Y(n2697) );
AOI211X1TS U2341 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3314), .B0(n3316),
.C0(n3313), .Y(n3318) );
BUFX3TS U2342 ( .A(n6175), .Y(n6176) );
CMPR32X2TS U2343 ( .A(n3689), .B(n3688), .C(n3687), .CO(n4318), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3) );
NOR2X1TS U2344 ( .A(n2413), .B(FPADDSUB_intDX_EWSW[30]), .Y(n3316) );
NOR2X1TS U2345 ( .A(n4256), .B(n4228), .Y(DP_OP_501J1_127_1459_n538) );
NOR2X1TS U2346 ( .A(n2386), .B(n4275), .Y(n4269) );
NOR2X1TS U2347 ( .A(n2768), .B(n2770), .Y(n2773) );
NOR2X1TS U2348 ( .A(n5387), .B(n5388), .Y(n4433) );
OAI22X1TS U2349 ( .A0(n2205), .A1(n4254), .B0(n4256), .B1(n4175), .Y(
DP_OP_501J1_127_1459_n532) );
OAI21X2TS U2350 ( .A0(n2771), .A1(n2770), .B0(n2769), .Y(n2772) );
OAI32X1TS U2351 ( .A0(n4293), .A1(n3681), .A2(n4323), .B0(n4328), .B1(n4293),
.Y(n4321) );
OAI21X2TS U2352 ( .A0(n2843), .A1(n3057), .B0(n3058), .Y(n2844) );
NAND3X1TS U2353 ( .A(n5099), .B(n5534), .C(n5098), .Y(n5539) );
NAND2X2TS U2354 ( .A(n3415), .B(n3524), .Y(n6175) );
CLKXOR2X2TS U2355 ( .A(n3038), .B(n3037), .Y(n3039) );
NAND2X1TS U2356 ( .A(n2989), .B(n4044), .Y(n6165) );
NAND2X1TS U2357 ( .A(n3030), .B(n3029), .Y(n3031) );
OA22X1TS U2358 ( .A0(n2427), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n2422), .B1(
n6544), .Y(n3298) );
INVX4TS U2359 ( .A(n3786), .Y(n4242) );
AOI21X2TS U2360 ( .A0(n3021), .A1(n2238), .B0(n3015), .Y(n3019) );
CLKBUFX2TS U2361 ( .A(n3361), .Y(n3605) );
BUFX3TS U2362 ( .A(n5476), .Y(n2313) );
BUFX3TS U2363 ( .A(n2243), .Y(n2217) );
CLKBUFX2TS U2364 ( .A(n2997), .Y(n3009) );
INVX4TS U2365 ( .A(n2840), .Y(n3056) );
INVX4TS U2366 ( .A(n3627), .Y(n4266) );
INVX4TS U2367 ( .A(n3838), .Y(n4234) );
INVX2TS U2368 ( .A(n6284), .Y(n3248) );
INVX4TS U2369 ( .A(n2244), .Y(n2332) );
INVX4TS U2370 ( .A(n2692), .Y(n2690) );
CLKXOR2X2TS U2371 ( .A(n4125), .B(n3690), .Y(n2243) );
OAI22X1TS U2372 ( .A0(n4305), .A1(n3671), .B0(n4303), .B1(n3666), .Y(n3685)
);
INVX2TS U2373 ( .A(n2372), .Y(n2284) );
CLKXOR2X2TS U2374 ( .A(n3699), .B(n3698), .Y(n3700) );
XNOR2X2TS U2375 ( .A(n2996), .B(n2995), .Y(n3010) );
INVX4TS U2376 ( .A(n4098), .Y(n2335) );
XOR2X1TS U2377 ( .A(n3785), .B(n3784), .Y(n3786) );
INVX6TS U2378 ( .A(n4107), .Y(n4279) );
NAND2XLTS U2379 ( .A(n4090), .B(n4095), .Y(n3733) );
INVX2TS U2380 ( .A(n4307), .Y(n4275) );
INVX4TS U2381 ( .A(n3240), .Y(n4280) );
AOI21X2TS U2382 ( .A0(n3000), .A1(n2431), .B0(n2999), .Y(n3004) );
INVX6TS U2383 ( .A(n4214), .Y(n4125) );
CLKBUFX2TS U2384 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n6578) );
INVX2TS U2385 ( .A(n2222), .Y(n4038) );
INVX4TS U2386 ( .A(n3673), .Y(n2372) );
INVX6TS U2387 ( .A(n4016), .Y(DP_OP_499J1_125_4188_n293) );
CMPR32X2TS U2388 ( .A(n6440), .B(n5500), .C(n3180), .CO(n3836), .S(n3182) );
INVX4TS U2389 ( .A(n4030), .Y(n2208) );
INVX3TS U2390 ( .A(n2997), .Y(DP_OP_499J1_125_4188_n266) );
NAND2X1TS U2391 ( .A(n4104), .B(n4103), .Y(n4105) );
NAND2X1TS U2392 ( .A(n2979), .B(n2978), .Y(n2981) );
NAND2X2TS U2393 ( .A(FPMULT_Op_MX[19]), .B(n6633), .Y(n5138) );
INVX4TS U2394 ( .A(n2443), .Y(n2370) );
NOR2X2TS U2395 ( .A(n3968), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]),
.Y(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
AND2X4TS U2396 ( .A(n3353), .B(n3404), .Y(n3332) );
OAI21X1TS U2397 ( .A0(n4116), .A1(n4115), .B0(n4114), .Y(n4117) );
INVX4TS U2398 ( .A(n2275), .Y(mult_x_313_n74) );
OAI21X1TS U2399 ( .A0(n4594), .A1(n4450), .B0(n4449), .Y(n5922) );
INVX4TS U2400 ( .A(n4045), .Y(n2209) );
NAND2X1TS U2401 ( .A(n2305), .B(n2224), .Y(n4416) );
NAND2X1TS U2402 ( .A(FPMULT_Op_MY[21]), .B(n6441), .Y(n4115) );
INVX4TS U2403 ( .A(n4047), .Y(DP_OP_499J1_125_4188_n270) );
INVX2TS U2404 ( .A(n3213), .Y(n4101) );
NAND2X1TS U2405 ( .A(n3624), .B(n3623), .Y(n3625) );
INVX4TS U2406 ( .A(n2237), .Y(n5500) );
OAI21X2TS U2407 ( .A0(n3621), .A1(n3620), .B0(n3619), .Y(n3626) );
NOR2X2TS U2408 ( .A(FPMULT_Op_MY[21]), .B(n6441), .Y(n4112) );
NAND2X1TS U2409 ( .A(DP_OP_501J1_127_1459_n910), .B(FPMULT_Op_MY[0]), .Y(
n3541) );
INVX2TS U2410 ( .A(n4040), .Y(DP_OP_499J1_125_4188_n273) );
CLKBUFX2TS U2411 ( .A(FPMULT_Op_MY[22]), .Y(n5498) );
INVX2TS U2412 ( .A(n3230), .Y(n3235) );
OR2X1TS U2413 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2448) );
NAND2XLTS U2414 ( .A(n3169), .B(n3168), .Y(n3171) );
INVX2TS U2415 ( .A(n4042), .Y(DP_OP_499J1_125_4188_n271) );
AOI21X2TS U2416 ( .A0(n3095), .A1(n3094), .B0(n3093), .Y(n3112) );
NAND2X2TS U2417 ( .A(n3218), .B(n3217), .Y(n3730) );
NAND2X2TS U2418 ( .A(n6440), .B(FPMULT_Op_MY[2]), .Y(n3569) );
XNOR2X1TS U2419 ( .A(n3954), .B(n3953), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
OAI21X1TS U2420 ( .A0(n4590), .A1(n4438), .B0(n4437), .Y(n4568) );
OR2X6TS U2421 ( .A(DP_OP_499J1_125_4188_n243), .B(DP_OP_499J1_125_4188_n245),
.Y(n3001) );
NAND2X1TS U2422 ( .A(n3480), .B(n3638), .Y(n3481) );
OR2X1TS U2423 ( .A(DP_OP_499J1_125_4188_n249), .B(n2679), .Y(n2884) );
NAND2X1TS U2424 ( .A(n3487), .B(n3486), .Y(n3488) );
OR2X4TS U2425 ( .A(DP_OP_499J1_125_4188_n246), .B(DP_OP_499J1_125_4188_n248),
.Y(n2431) );
INVX4TS U2426 ( .A(n2236), .Y(n6442) );
OR2X2TS U2427 ( .A(n3675), .B(n6455), .Y(n3226) );
OAI21X2TS U2428 ( .A0(n2888), .A1(n2965), .B0(n2887), .Y(n2890) );
INVX2TS U2429 ( .A(n6668), .Y(n2279) );
CLKXOR2X4TS U2430 ( .A(n2965), .B(n2964), .Y(n4041) );
INVX2TS U2431 ( .A(n6680), .Y(n2278) );
INVX2TS U2432 ( .A(n4011), .Y(DP_OP_499J1_125_4188_n301) );
NOR2X1TS U2433 ( .A(n3622), .B(n3620), .Y(n3147) );
NAND2X1TS U2434 ( .A(n2940), .B(n2939), .Y(n2941) );
NAND2X1TS U2435 ( .A(n2921), .B(n2932), .Y(n2922) );
NAND2X1TS U2436 ( .A(n2914), .B(n2913), .Y(n2915) );
NAND2X1TS U2437 ( .A(n2955), .B(n2954), .Y(n2956) );
NAND2X1TS U2438 ( .A(n2837), .B(n2836), .Y(n2838) );
NAND2X1TS U2439 ( .A(n3140), .B(n3204), .Y(n3141) );
NOR2X2TS U2440 ( .A(n2665), .B(n2664), .Y(n2977) );
INVX4TS U2441 ( .A(n2226), .Y(n6455) );
AOI21X2TS U2442 ( .A0(n2961), .A1(n2959), .B0(n2644), .Y(n2980) );
AOI21X2TS U2443 ( .A0(n3221), .A1(n3220), .B0(n3219), .Y(n3225) );
NOR2X1TS U2444 ( .A(n3914), .B(n3913), .Y(n3942) );
NAND2X1TS U2445 ( .A(n3914), .B(n3913), .Y(n3943) );
NAND2X1TS U2446 ( .A(n4310), .B(n3792), .Y(n3163) );
NAND2X1TS U2447 ( .A(n3917), .B(n3916), .Y(n3938) );
CLKINVX6TS U2448 ( .A(n2215), .Y(n3946) );
INVX2TS U2449 ( .A(n3070), .Y(n2664) );
XOR2X1TS U2450 ( .A(n3866), .B(n3865), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
NAND2X2TS U2451 ( .A(n2273), .B(n6438), .Y(n3168) );
NOR2X2TS U2452 ( .A(n3638), .B(n3637), .Y(n3639) );
CLKXOR2X4TS U2453 ( .A(n2753), .B(n2742), .Y(n4023) );
INVX6TS U2454 ( .A(n6853), .Y(n6438) );
INVX2TS U2455 ( .A(n2444), .Y(n2273) );
NAND2X1TS U2456 ( .A(n2741), .B(n2782), .Y(n2742) );
NAND2X1TS U2457 ( .A(n2901), .B(n2900), .Y(n2902) );
NAND2X1TS U2458 ( .A(n3223), .B(n3221), .Y(n3130) );
INVX6TS U2459 ( .A(n6883), .Y(n6447) );
CLKINVX2TS U2460 ( .A(n6142), .Y(n2647) );
NAND2X1TS U2461 ( .A(n2875), .B(n2874), .Y(n2876) );
NAND2X1TS U2462 ( .A(n2725), .B(n2862), .Y(n2863) );
NAND2X4TS U2463 ( .A(n2828), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(
n3435) );
NAND2X1TS U2464 ( .A(n3448), .B(n3457), .Y(n3449) );
NOR2X4TS U2465 ( .A(DP_OP_501J1_127_1459_n931), .B(n4818), .Y(n3205) );
NAND2X4TS U2466 ( .A(n2578), .B(n2929), .Y(n2580) );
NOR2X4TS U2467 ( .A(n2764), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(
n2783) );
INVX8TS U2468 ( .A(n6923), .Y(n4818) );
NOR2X6TS U2469 ( .A(n2938), .B(n2934), .Y(n2578) );
NAND2X2TS U2470 ( .A(n2875), .B(n2725), .Y(n2730) );
NAND2X1TS U2471 ( .A(n3907), .B(n3906), .Y(n3926) );
NOR2X4TS U2472 ( .A(n2573), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(
n2910) );
NAND2X1TS U2473 ( .A(n2588), .B(n2593), .Y(n2589) );
NAND2X1TS U2474 ( .A(n3106), .B(n3458), .Y(n3107) );
AOI21X2TS U2475 ( .A0(n2905), .A1(n2658), .B0(n2618), .Y(n2896) );
CMPR32X2TS U2476 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]), .B(
n3879), .C(n3878), .CO(n3880), .S(n3877) );
NAND2X1TS U2477 ( .A(n2737), .B(n2755), .Y(n2738) );
INVX2TS U2478 ( .A(n3411), .Y(n2565) );
AOI21X2TS U2479 ( .A0(n3117), .A1(n3116), .B0(n3115), .Y(n3846) );
AOI21X2TS U2480 ( .A0(n2791), .A1(n2732), .B0(n2731), .Y(n2739) );
OAI21X2TS U2481 ( .A0(n2788), .A1(n2802), .B0(n2804), .Y(n2789) );
NOR2X2TS U2482 ( .A(n2597), .B(n2592), .Y(n2600) );
NAND2X1TS U2483 ( .A(n2503), .B(n2500), .Y(n2498) );
NAND2X2TS U2484 ( .A(n2661), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(
n2675) );
NAND2X2TS U2485 ( .A(n2674), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(
n2702) );
NOR2X2TS U2486 ( .A(n2604), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]),
.Y(n2608) );
OR2X4TS U2487 ( .A(n2811), .B(n2810), .Y(n2812) );
INVX6TS U2488 ( .A(n2810), .Y(n2791) );
NOR2X4TS U2489 ( .A(n3447), .B(n3446), .Y(n3459) );
NAND2X1TS U2490 ( .A(n2722), .B(n2721), .Y(n2723) );
OR2X2TS U2491 ( .A(n2513), .B(n2532), .Y(n2221) );
NAND2X2TS U2492 ( .A(n2732), .B(n2756), .Y(n2716) );
NAND2X2TS U2493 ( .A(n2645), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(
n3114) );
CMPR32X2TS U2494 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]), .B(
n3468), .C(n3467), .CO(n3469), .S(n3447) );
INVX2TS U2495 ( .A(n2714), .Y(n2719) );
NAND2X2TS U2496 ( .A(n2760), .B(n2759), .Y(n2804) );
INVX2TS U2497 ( .A(n2754), .Y(n2732) );
NAND2X2TS U2498 ( .A(n2795), .B(n2794), .Y(n2803) );
NAND2X2TS U2499 ( .A(n2548), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(
n2650) );
INVX4TS U2500 ( .A(n2495), .Y(n2503) );
NOR2X4TS U2501 ( .A(n2706), .B(n2707), .Y(n2754) );
OAI21X2TS U2502 ( .A0(n2516), .A1(n2533), .B0(n2517), .Y(n2468) );
NAND2X4TS U2503 ( .A(n2470), .B(n2459), .Y(n2551) );
INVX2TS U2504 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
n2823) );
NAND2X2TS U2505 ( .A(n2483), .B(n2482), .Y(n2559) );
OR2X2TS U2506 ( .A(n2669), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2670) );
NAND2X4TS U2507 ( .A(n2552), .B(n2526), .Y(n2513) );
OR2X6TS U2508 ( .A(n2470), .B(n2469), .Y(n2552) );
INVX2TS U2509 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(
n2708) );
INVX2TS U2510 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
n2494) );
ADDFHX2TS U2511 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]), .B(
n2481), .CI(n2629), .CO(n2459), .S(n2483) );
INVX6TS U2512 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(
n2481) );
INVX4TS U2513 ( .A(FPMULT_inst_RecursiveKOA_Result[3]), .Y(n2629) );
INVX4TS U2514 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(
n2476) );
INVX3TS U2515 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(
n2461) );
INVX2TS U2516 ( .A(n6173), .Y(n2195) );
INVX2TS U2517 ( .A(n2195), .Y(n2196) );
INVX2TS U2518 ( .A(n2195), .Y(n2197) );
INVX2TS U2519 ( .A(n2211), .Y(n2198) );
INVX2TS U2520 ( .A(n2198), .Y(n2199) );
INVX2TS U2521 ( .A(n2198), .Y(n2200) );
NOR2X4TS U2522 ( .A(n2760), .B(n2759), .Y(n2802) );
ADDFX2TS U2523 ( .A(n2815), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]), .CI(
n2814), .CO(n2816), .S(n2795) );
XNOR2X1TS U2524 ( .A(n3928), .B(n3927), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
OAI21XLTS U2525 ( .A0(n3694), .A1(n4112), .B0(n4115), .Y(n3695) );
NOR2XLTS U2526 ( .A(n3287), .B(FPADDSUB_intDY_EWSW[16]), .Y(n3288) );
INVX2TS U2527 ( .A(n3002), .Y(n2681) );
NAND2X1TS U2528 ( .A(n3227), .B(n3729), .Y(n3228) );
NAND2X1TS U2529 ( .A(n6641), .B(n6438), .Y(n3536) );
OAI21X2TS U2530 ( .A0(n3058), .A1(n2846), .B0(n2847), .Y(n2691) );
OAI22X1TS U2531 ( .A0(n5400), .A1(n5388), .B0(n2311), .B1(n5386), .Y(n4616)
);
NAND2X4TS U2532 ( .A(n2480), .B(n2479), .Y(n2555) );
NAND2X4TS U2533 ( .A(DP_OP_499J1_125_4188_n225), .B(
DP_OP_499J1_125_4188_n227), .Y(n3052) );
INVX2TS U2534 ( .A(n3215), .Y(n3219) );
NAND2X1TS U2535 ( .A(n4417), .B(n4416), .Y(n4419) );
NAND2X1TS U2536 ( .A(DP_OP_499J1_125_4188_n203), .B(n2749), .Y(n2769) );
NOR2XLTS U2537 ( .A(n4277), .B(n4260), .Y(n4263) );
INVX4TS U2538 ( .A(n2246), .Y(n2333) );
OAI21X2TS U2539 ( .A0(n2928), .A1(n2924), .B0(n2925), .Y(n2946) );
NAND2X1TS U2540 ( .A(n2640), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(
n2676) );
INVX2TS U2541 ( .A(n2244), .Y(n2331) );
NAND2X1TS U2542 ( .A(n6437), .B(DP_OP_501J1_127_1459_n910), .Y(n3734) );
NOR2XLTS U2543 ( .A(n2285), .B(n4228), .Y(n3811) );
AOI21X1TS U2544 ( .A0(n3352), .A1(n3334), .B0(n3333), .Y(n3335) );
OAI21XLTS U2545 ( .A0(n5569), .A1(n5566), .B0(n5567), .Y(n4748) );
CMPR42X1TS U2546 ( .A(DP_OP_502J1_128_2852_n151), .B(
DP_OP_502J1_128_2852_n158), .C(DP_OP_502J1_128_2852_n132), .D(
DP_OP_502J1_128_2852_n165), .ICI(DP_OP_502J1_128_2852_n130), .S(
DP_OP_502J1_128_2852_n126), .ICO(DP_OP_502J1_128_2852_n124), .CO(
DP_OP_502J1_128_2852_n125) );
OR2X1TS U2547 ( .A(FPMULT_Op_MY[0]), .B(n6631), .Y(n3153) );
OAI21XLTS U2548 ( .A0(n5675), .A1(n5672), .B0(n5673), .Y(n4843) );
CLKBUFX2TS U2549 ( .A(n4047), .Y(n2985) );
NAND2X1TS U2550 ( .A(n2998), .B(n6177), .Y(n3013) );
BUFX3TS U2551 ( .A(n4121), .Y(n4256) );
INVX2TS U2552 ( .A(FPMULT_Op_MX[8]), .Y(n2276) );
NOR2XLTS U2553 ( .A(n4910), .B(n4912), .Y(n4909) );
BUFX3TS U2554 ( .A(n5471), .Y(n2299) );
CLKINVX3TS U2555 ( .A(n4420), .Y(n2365) );
INVX2TS U2556 ( .A(n2245), .Y(n2329) );
NOR2XLTS U2557 ( .A(n6733), .B(FPADDSUB_DMP_SFG[21]), .Y(n4480) );
OR2X1TS U2558 ( .A(n2985), .B(n2984), .Y(n2233) );
AOI21X1TS U2559 ( .A0(n6115), .A1(n2950), .B0(n2949), .Y(n6111) );
AOI21X1TS U2560 ( .A0(n6059), .A1(n6055), .B0(n4349), .Y(n5973) );
NOR2XLTS U2561 ( .A(n6780), .B(FPADDSUB_DMP_SFG[11]), .Y(n4460) );
NOR2XLTS U2562 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n4356) );
OAI21X1TS U2563 ( .A0(n5793), .A1(n6687), .B0(n5716), .Y(n5756) );
OAI21XLTS U2564 ( .A0(n4857), .A1(n4856), .B0(n5685), .Y(intadd_2_B_6_) );
AND2X2TS U2565 ( .A(n3337), .B(n3336), .Y(n3340) );
OR2X1TS U2566 ( .A(DP_OP_502J1_128_2852_n101), .B(n3584), .Y(n5343) );
OR2X1TS U2567 ( .A(DP_OP_502J1_128_2852_n129), .B(DP_OP_502J1_128_2852_n135),
.Y(n2446) );
OAI21XLTS U2568 ( .A0(n4762), .A1(n4761), .B0(n5578), .Y(intadd_0_B_6_) );
NOR2X2TS U2569 ( .A(DP_OP_501J1_127_1459_n145), .B(DP_OP_501J1_127_1459_n152), .Y(n4052) );
OR2X1TS U2570 ( .A(DP_OP_501J1_127_1459_n197), .B(n3190), .Y(n3173) );
NAND2X1TS U2571 ( .A(n4027), .B(n4026), .Y(n4028) );
NAND2X2TS U2572 ( .A(n2636), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(
n2652) );
BUFX3TS U2573 ( .A(n4538), .Y(n6384) );
OAI21XLTS U2574 ( .A0(n2375), .A1(n4313), .B0(n2282), .Y(mult_x_313_n65) );
OAI21XLTS U2575 ( .A0(n4831), .A1(n4830), .B0(n4829), .Y(intadd_2_A_3_) );
OR2X1TS U2576 ( .A(n3593), .B(n3592), .Y(n5084) );
OAI21XLTS U2577 ( .A0(n4920), .A1(n5624), .B0(n5625), .Y(n4921) );
NOR2X2TS U2578 ( .A(n4057), .B(n4062), .Y(n3194) );
OAI2BB1X1TS U2579 ( .A0N(n2450), .A1N(n3512), .B0(n5892), .Y(n3504) );
INVX2TS U2580 ( .A(n5812), .Y(n4641) );
CLKINVX3TS U2581 ( .A(n6337), .Y(n5009) );
INVX6TS U2582 ( .A(n6396), .Y(n2353) );
INVX2TS U2583 ( .A(n4687), .Y(n4812) );
OAI21XLTS U2584 ( .A0(n4500), .A1(n5876), .B0(n5875), .Y(n4501) );
OAI21XLTS U2585 ( .A0(n5537), .A1(n5536), .B0(n5535), .Y(n5538) );
OAI21XLTS U2586 ( .A0(n5436), .A1(n5433), .B0(n5434), .Y(n5432) );
NAND2X1TS U2587 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(n6684),
.Y(n6212) );
NAND2X1TS U2588 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n6212),
.Y(n5881) );
BUFX3TS U2589 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n5885) );
BUFX3TS U2590 ( .A(n5065), .Y(n4965) );
INVX2TS U2591 ( .A(n6421), .Y(n5065) );
OAI21X1TS U2592 ( .A0(n5352), .A1(n3589), .B0(n3588), .Y(n3595) );
OAI21XLTS U2593 ( .A0(n4227), .A1(n4223), .B0(n4224), .Y(n4158) );
BUFX3TS U2594 ( .A(n4402), .Y(n5179) );
NOR2XLTS U2595 ( .A(n6603), .B(n6602), .Y(n6604) );
NOR2XLTS U2596 ( .A(n6603), .B(n6588), .Y(n6589) );
NOR2XLTS U2597 ( .A(n6524), .B(n6523), .Y(n6525) );
NOR2XLTS U2598 ( .A(n6524), .B(n6494), .Y(n6495) );
CLKINVX3TS U2599 ( .A(n6485), .Y(n6487) );
AND2X2TS U2600 ( .A(n6433), .B(n5813), .Y(n6472) );
CLKINVX3TS U2601 ( .A(n4230), .Y(n5817) );
CLKINVX3TS U2602 ( .A(n6301), .Y(n6339) );
INVX2TS U2603 ( .A(n4613), .Y(n6251) );
OAI21XLTS U2604 ( .A0(n6327), .A1(n7049), .B0(n6329), .Y(n4610) );
OAI31X1TS U2605 ( .A0(n6270), .A1(n2230), .A2(n6682), .B0(n6243), .Y(n6242)
);
INVX1TS U2606 ( .A(result_add_subt[25]), .Y(n6400) );
OR2X2TS U2607 ( .A(n6211), .B(operation[1]), .Y(n4631) );
NOR2X2TS U2608 ( .A(n6856), .B(n6665), .Y(n7030) );
XOR2X2TS U2609 ( .A(n3979), .B(n3978), .Y(
FPMULT_inst_RecursiveKOA_Result[37]) );
NOR2XLTS U2610 ( .A(n5157), .B(n5475), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
OAI211XLTS U2611 ( .A0(n6396), .A1(n5206), .B0(n3391), .C0(n3390), .Y(n1792)
);
OAI21XLTS U2612 ( .A0(n5742), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
n4623), .Y(n1620) );
OAI211XLTS U2613 ( .A0(n5243), .A1(n5284), .B0(n5242), .C0(n5241), .Y(n1800)
);
OAI211XLTS U2614 ( .A0(n4684), .A1(n6237), .B0(n4683), .C0(n6227), .Y(n2127)
);
OAI211XLTS U2615 ( .A0(n4965), .A1(n6303), .B0(n4953), .C0(n4952), .Y(n1937)
);
OAI211XLTS U2616 ( .A0(n6394), .A1(n5225), .B0(n5224), .C0(n5223), .Y(n1794)
);
OAI211XLTS U2617 ( .A0(n2357), .A1(n6804), .B0(n4707), .C0(n4706), .Y(n1522)
);
OAI211XLTS U2618 ( .A0(n6396), .A1(n5231), .B0(n3406), .C0(n3405), .Y(n1797)
);
OAI21XLTS U2619 ( .A0(n4213), .A1(n4212), .B0(n4211), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11) );
OAI211XLTS U2620 ( .A0(n2358), .A1(n6814), .B0(n4715), .C0(n4714), .Y(n1512)
);
XNOR2X1TS U2621 ( .A(n3595), .B(n3594), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
OAI21XLTS U2622 ( .A0(n5426), .A1(n5177), .B0(n5176), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
OAI21XLTS U2623 ( .A0(n2255), .A1(n4402), .B0(n5289), .Y(n1217) );
OAI21XLTS U2624 ( .A0(n2264), .A1(n5179), .B0(n5290), .Y(n1233) );
OAI21XLTS U2625 ( .A0(n6542), .A1(n5292), .B0(n5255), .Y(n1269) );
OAI21XLTS U2626 ( .A0(n3262), .A1(n5308), .B0(n5307), .Y(n1303) );
OAI21XLTS U2627 ( .A0(n2418), .A1(n5308), .B0(n5288), .Y(n1326) );
OAI21XLTS U2628 ( .A0(n2404), .A1(n5197), .B0(n5178), .Y(n1374) );
OAI21XLTS U2629 ( .A0(n2398), .A1(n5197), .B0(n5196), .Y(n1386) );
OAI21XLTS U2630 ( .A0(n2257), .A1(n2439), .B0(n5250), .Y(n1407) );
OAI211XLTS U2631 ( .A0(n6396), .A1(n5202), .B0(n3395), .C0(n3394), .Y(n1789)
);
CLKINVX3TS U2632 ( .A(n6839), .Y(busy) );
XNOR2X4TS U2633 ( .A(n4126), .B(FPMULT_Op_MY[11]), .Y(n2205) );
INVX2TS U2634 ( .A(n6858), .Y(n5497) );
BUFX3TS U2635 ( .A(n4936), .Y(n6300) );
BUFX3TS U2636 ( .A(n4936), .Y(n6267) );
INVX2TS U2637 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n6592) );
BUFX3TS U2638 ( .A(n6380), .Y(n6375) );
BUFX3TS U2639 ( .A(n4539), .Y(n6380) );
BUFX3TS U2640 ( .A(n6255), .Y(n4613) );
BUFX3TS U2641 ( .A(n6250), .Y(n6255) );
BUFX3TS U2642 ( .A(n4612), .Y(n6317) );
BUFX3TS U2643 ( .A(n4612), .Y(n6337) );
BUFX3TS U2644 ( .A(n6275), .Y(n6301) );
INVX2TS U2645 ( .A(n6480), .Y(n2356) );
BUFX3TS U2646 ( .A(n5893), .Y(n6480) );
NAND2X4TS U2647 ( .A(n3975), .B(n3088), .Y(n3741) );
CLKMX2X2TS U2648 ( .A(n5766), .B(FPMULT_P_Sgf[28]), .S0(n6181), .Y(n1557) );
CLKMX2X2TS U2649 ( .A(n5785), .B(FPMULT_P_Sgf[26]), .S0(n2361), .Y(n1555) );
CLKMX2X2TS U2650 ( .A(n5807), .B(FPMULT_P_Sgf[23]), .S0(n7026), .Y(n1552) );
CLKMX2X2TS U2651 ( .A(n6174), .B(FPMULT_P_Sgf[21]), .S0(n2197), .Y(n1550) );
CLKMX2X2TS U2652 ( .A(n6182), .B(FPMULT_P_Sgf[22]), .S0(n6181), .Y(n1551) );
CLKMX2X2TS U2653 ( .A(n6164), .B(FPMULT_P_Sgf[20]), .S0(n2197), .Y(n1549) );
NOR2X4TS U2654 ( .A(DP_OP_499J1_125_4188_n203), .B(n2749), .Y(n2770) );
OAI211X1TS U2655 ( .A0(n5243), .A1(n5231), .B0(n3408), .C0(n3407), .Y(n1796)
);
CLKMX2X2TS U2656 ( .A(n6160), .B(FPMULT_P_Sgf[19]), .S0(n2197), .Y(n1548) );
CLKMX2X2TS U2657 ( .A(n6153), .B(FPMULT_P_Sgf[18]), .S0(n2197), .Y(n1547) );
OAI211X1TS U2658 ( .A0(n5243), .A1(n5206), .B0(n3376), .C0(n3375), .Y(n1791)
);
OAI211X1TS U2659 ( .A0(n5243), .A1(n5202), .B0(n3397), .C0(n3396), .Y(n1788)
);
AOI2BB2X1TS U2660 ( .B0(n5274), .B1(n2352), .A0N(n6393), .A1N(n5243), .Y(
n5233) );
OAI222X1TS U2661 ( .A0(n6396), .A1(n6395), .B0(n6394), .B1(n6393), .C0(n6392), .C1(n2449), .Y(n1811) );
INVX2TS U2662 ( .A(n2213), .Y(n4046) );
INVX3TS U2663 ( .A(n5246), .Y(n6396) );
CLKMX2X2TS U2664 ( .A(FPMULT_Add_result[23]), .B(n5721), .S0(n5809), .Y(
n1597) );
NAND2X4TS U2665 ( .A(n3369), .B(n5272), .Y(n5243) );
INVX2TS U2666 ( .A(n4041), .Y(DP_OP_499J1_125_4188_n272) );
CLKMX2X2TS U2667 ( .A(FPMULT_Add_result[22]), .B(n5723), .S0(n5739), .Y(
n1598) );
INVX4TS U2668 ( .A(n4043), .Y(DP_OP_499J1_125_4188_n294) );
INVX4TS U2669 ( .A(n4018), .Y(DP_OP_499J1_125_4188_n298) );
OR2X2TS U2670 ( .A(n3803), .B(n3802), .Y(n2435) );
INVX2TS U2671 ( .A(n5427), .Y(n5436) );
CLKMX2X2TS U2672 ( .A(FPMULT_Add_result[21]), .B(n5725), .S0(n5739), .Y(
n1599) );
XOR2X1TS U2673 ( .A(n6039), .B(n6038), .Y(n6044) );
INVX6TS U2674 ( .A(n2308), .Y(n2309) );
XOR2X1TS U2675 ( .A(n5368), .B(n5367), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
INVX2TS U2676 ( .A(n4039), .Y(DP_OP_499J1_125_4188_n300) );
OR2X2TS U2677 ( .A(n3187), .B(n3186), .Y(n2391) );
AO21X1TS U2678 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n6657), .B0(n5886),
.Y(n1314) );
NAND2X2TS U2679 ( .A(n6392), .B(n3366), .Y(n3359) );
INVX4TS U2680 ( .A(n6491), .Y(n2308) );
CLKMX2X2TS U2681 ( .A(FPMULT_Add_result[20]), .B(n5727), .S0(n5739), .Y(
n1600) );
AOI21X2TS U2682 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n3333), .B0(
n5886), .Y(n5271) );
CLKMX2X2TS U2683 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n5816), .Y(n1595) );
XOR2X1TS U2684 ( .A(n6001), .B(n6000), .Y(n6006) );
CLKINVX2TS U2685 ( .A(n4859), .Y(n4865) );
INVX6TS U2686 ( .A(n3441), .Y(n3095) );
ADDHX1TS U2687 ( .A(n3702), .B(n3701), .CO(DP_OP_501J1_127_1459_n495), .S(
DP_OP_501J1_127_1459_n496) );
XOR2X1TS U2688 ( .A(n5376), .B(n5375), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
NAND4BX1TS U2689 ( .AN(n5888), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n5889) );
CLKMX2X2TS U2690 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n5816), .Y(n1588) );
OAI21X1TS U2691 ( .A0(n6715), .A1(n5292), .B0(n5252), .Y(n1291) );
INVX1TS U2692 ( .A(n5078), .Y(n5079) );
INVX3TS U2693 ( .A(n2785), .Y(n2753) );
CLKMX2X2TS U2694 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n5816), .Y(n1589) );
NAND4X1TS U2695 ( .A(n4670), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .C(n4669),
.D(n4668), .Y(n4671) );
INVX4TS U2696 ( .A(n5179), .Y(n5195) );
BUFX6TS U2697 ( .A(n4277), .Y(n2373) );
INVX4TS U2698 ( .A(n5179), .Y(n6572) );
INVX4TS U2699 ( .A(n5265), .Y(n5303) );
INVX12TS U2700 ( .A(n3700), .Y(n4249) );
INVX4TS U2701 ( .A(n5265), .Y(n5306) );
CLKMX2X2TS U2702 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n5816), .Y(n1590) );
INVX4TS U2703 ( .A(n2439), .Y(n5259) );
NAND2X6TS U2704 ( .A(n3332), .B(n4648), .Y(n4645) );
INVX2TS U2705 ( .A(n4090), .Y(n4093) );
INVX4TS U2706 ( .A(n4228), .Y(n3166) );
AOI2BB2X1TS U2707 ( .B0(FPSENCOS_d_ff2_X[30]), .B1(n6279), .A0N(n6279),
.A1N(FPSENCOS_d_ff2_X[30]), .Y(n4614) );
OR2X4TS U2708 ( .A(n2726), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(
n2725) );
AO21X1TS U2709 ( .A0(n5628), .A1(n5627), .B0(n5629), .Y(n4900) );
BUFX3TS U2710 ( .A(n6380), .Y(n5041) );
AOI2BB2X1TS U2711 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n6333), .A0N(n6333),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n6334) );
OAI211X1TS U2712 ( .A0(n6275), .A1(n6823), .B0(n4679), .C0(n6238), .Y(n2118)
);
BUFX12TS U2713 ( .A(n3133), .Y(n4228) );
BUFX12TS U2714 ( .A(n3152), .Y(n4214) );
OAI21X1TS U2715 ( .A0(n6276), .A1(n6728), .B0(n6280), .Y(n4608) );
AOI2BB2X1TS U2716 ( .B0(n6332), .B1(n6328), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n6413), .Y(n1849) );
NOR2X1TS U2717 ( .A(n2298), .B(n5389), .Y(n3591) );
NAND2X1TS U2718 ( .A(n2196), .B(FPMULT_P_Sgf[35]), .Y(n3530) );
AO22X1TS U2719 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n6306), .B0(n6249),
.B1(n6248), .Y(n2115) );
AO21X1TS U2720 ( .A0(n5517), .A1(n5516), .B0(n5518), .Y(n5137) );
OAI21X1TS U2721 ( .A0(n5877), .A1(n5876), .B0(n5875), .Y(n5879) );
NAND2X4TS U2722 ( .A(n3338), .B(n5212), .Y(n4860) );
AO22X1TS U2723 ( .A0(n6335), .A1(n4609), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_y_out[23]), .Y(n1853) );
AO22X1TS U2724 ( .A0(n6599), .A1(n6483), .B0(n6486), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1474) );
AO22X1TS U2725 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n6487),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1420) );
OR2X4TS U2726 ( .A(n4538), .B(n4686), .Y(n4941) );
AO22X1TS U2727 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n6575),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1425) );
AO22X1TS U2728 ( .A0(n6576), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n6575), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1359) );
AO22X1TS U2729 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n6575),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1430) );
AO22X1TS U2730 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n6575),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1435) );
AO22X1TS U2731 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n6575),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1440) );
AO22X1TS U2732 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n6575),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1445) );
AO22X1TS U2733 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n6575),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1450) );
AO22X1TS U2734 ( .A0(n6576), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n6487),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1455) );
OAI21X1TS U2735 ( .A0(n6093), .A1(n6092), .B0(n6091), .Y(n6098) );
AND3X2TS U2736 ( .A(n3604), .B(n3603), .C(n3602), .Y(n6393) );
AO22X1TS U2737 ( .A0(n6335), .A1(intadd_5_SUM_2_), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1850) );
NOR2X1TS U2738 ( .A(n2447), .B(n5393), .Y(n4511) );
AO22X1TS U2739 ( .A0(n6577), .A1(FPADDSUB_DMP_SFG[29]), .B0(n6488), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1424) );
AO22X1TS U2740 ( .A0(n6301), .A1(intadd_5_SUM_1_), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1851) );
AO22X1TS U2741 ( .A0(n6577), .A1(FPADDSUB_DMP_SFG[30]), .B0(n6488), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1419) );
OAI21X1TS U2742 ( .A0(n6077), .A1(n5946), .B0(n5945), .Y(n5950) );
INVX4TS U2743 ( .A(n6337), .Y(n6269) );
AO22X1TS U2744 ( .A0(n6264), .A1(FPSENCOS_d_ff2_X[16]), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1972) );
OAI21X1TS U2745 ( .A0(n6077), .A1(n5924), .B0(n5923), .Y(n5927) );
AO22X1TS U2746 ( .A0(n4230), .A1(Data_2[31]), .B0(n5492), .B1(
FPMULT_Op_MY[31]), .Y(n1624) );
AO21X1TS U2747 ( .A0(n5140), .A1(n5141), .B0(n5138), .Y(n5139) );
AO22X1TS U2748 ( .A0(n6617), .A1(intadd_4_SUM_2_), .B0(n6796), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1478) );
INVX2TS U2749 ( .A(n6275), .Y(n6240) );
AO22X1TS U2750 ( .A0(n4230), .A1(Data_1[31]), .B0(n5501), .B1(
FPMULT_Op_MX[31]), .Y(n1657) );
NAND2X1TS U2751 ( .A(n3605), .B(n6696), .Y(n3381) );
CLKINVX2TS U2752 ( .A(n6246), .Y(n6224) );
NAND2X1TS U2753 ( .A(n3605), .B(n6792), .Y(n3384) );
INVX4TS U2754 ( .A(n3605), .Y(n2210) );
OA21X2TS U2755 ( .A0(n3330), .A1(FPADDSUB_Raw_mant_NRM_SWR[18]), .B0(n3344),
.Y(n3351) );
AND2X2TS U2756 ( .A(n4382), .B(n4379), .Y(n4380) );
OR2X2TS U2757 ( .A(n5131), .B(n5120), .Y(n5121) );
INVX4TS U2758 ( .A(n5742), .Y(n5777) );
INVX4TS U2759 ( .A(n4230), .Y(n5501) );
INVX4TS U2760 ( .A(n4230), .Y(n5494) );
INVX4TS U2761 ( .A(n4230), .Y(n5492) );
INVX4TS U2762 ( .A(n4230), .Y(n5496) );
OAI21X1TS U2763 ( .A0(n6075), .A1(n4456), .B0(n4455), .Y(n4457) );
OAI21X1TS U2764 ( .A0(n4601), .A1(n4600), .B0(n4599), .Y(n4603) );
AND2X2TS U2765 ( .A(n4113), .B(n4118), .Y(n2436) );
XNOR2X2TS U2766 ( .A(n2639), .B(n2658), .Y(n2640) );
NOR2X2TS U2767 ( .A(n4116), .B(n4112), .Y(n4118) );
NAND2X4TS U2768 ( .A(n3333), .B(n6618), .Y(n6392) );
NOR2X2TS U2769 ( .A(n5141), .B(n5529), .Y(n5100) );
NOR2X4TS U2770 ( .A(n3905), .B(n3904), .Y(n3950) );
NOR2X4TS U2771 ( .A(n3105), .B(n3104), .Y(n3455) );
INVX4TS U2772 ( .A(n6219), .Y(n5892) );
CLKINVX1TS U2773 ( .A(n5312), .Y(n5314) );
OR2X2TS U2774 ( .A(n3120), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(
n3121) );
NAND2BXLTS U2775 ( .AN(n2401), .B(n3255), .Y(n3256) );
OAI21X1TS U2776 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n2434), .B0(n6286), .Y(
n3268) );
INVX4TS U2777 ( .A(n6219), .Y(n6606) );
INVX1TS U2778 ( .A(n3325), .Y(n3323) );
INVX1TS U2779 ( .A(n3326), .Y(n3341) );
AOI2BB1X1TS U2780 ( .A0N(n3345), .A1N(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3346) );
INVX4TS U2781 ( .A(n6578), .Y(n4869) );
OAI21X1TS U2782 ( .A0(n4440), .A1(n4577), .B0(n4439), .Y(n4441) );
OAI21X1TS U2783 ( .A0(n4446), .A1(n6091), .B0(n4445), .Y(n4447) );
OAI21X1TS U2784 ( .A0(n6063), .A1(n6095), .B0(n6064), .Y(n4341) );
NAND4BX2TS U2785 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n4528), .D(n6685), .Y(
n4529) );
INVX4TS U2786 ( .A(n2251), .Y(n2301) );
CLKMX2X2TS U2787 ( .A(n6894), .B(n6893), .S0(n6892), .Y(n1694) );
OR2X2TS U2788 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n4482) );
OR2X2TS U2789 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n6026) );
OR2X2TS U2790 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n6009) );
OR2X2TS U2791 ( .A(DP_OP_501J1_127_1459_n910), .B(FPMULT_Op_MY[0]), .Y(n3542) );
OR2X2TS U2792 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n3348) );
CLKMX2X2TS U2793 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
INVX4TS U2794 ( .A(n6737), .Y(n6531) );
CLKMX2X2TS U2795 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
OR2X2TS U2796 ( .A(n6697), .B(n6855), .Y(n5681) );
INVX6TS U2797 ( .A(n6887), .Y(n6448) );
INVX2TS U2798 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(
n2455) );
INVX4TS U2799 ( .A(n2438), .Y(n6270) );
NOR3X2TS U2800 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4536) );
NAND2BX1TS U2801 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n3273) );
CLKBUFX2TS U2802 ( .A(n6637), .Y(n2318) );
INVX2TS U2803 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(
n2585) );
INVX4TS U2804 ( .A(operation[1]), .Y(n4686) );
INVX4TS U2805 ( .A(operation[2]), .Y(n6211) );
NOR2X4TS U2806 ( .A(n3090), .B(n3089), .Y(n3113) );
CLKMX2X2TS U2807 ( .A(n4413), .B(FPMULT_P_Sgf[31]), .S0(n2361), .Y(n1560) );
OAI21X2TS U2808 ( .A0(n3431), .A1(n7026), .B0(n3430), .Y(n1559) );
XOR2X2TS U2809 ( .A(n3429), .B(n3428), .Y(n3431) );
INVX6TS U2810 ( .A(n3082), .Y(n3983) );
NOR2X4TS U2811 ( .A(n3086), .B(n4039), .Y(n2801) );
NAND2X4TS U2812 ( .A(n3083), .B(n4023), .Y(n3528) );
NAND2X4TS U2813 ( .A(n3074), .B(n4013), .Y(n4007) );
NOR2X4TS U2814 ( .A(n3083), .B(n4023), .Y(n3527) );
XNOR2X2TS U2815 ( .A(n3777), .B(n4193), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14) );
OAI21X1TS U2816 ( .A0(n6167), .A1(n6166), .B0(n6165), .Y(n6172) );
OR2X2TS U2817 ( .A(n2775), .B(n2774), .Y(n2777) );
OAI211X1TS U2818 ( .A0(n3368), .A1(n5211), .B0(n5210), .C0(n5209), .Y(n1806)
);
OAI211X1TS U2819 ( .A0(n6393), .A1(n6396), .B0(n5276), .C0(n5275), .Y(n1810)
);
NAND2BX1TS U2820 ( .AN(n3618), .B(n3617), .Y(n1807) );
NAND2BX1TS U2821 ( .AN(n3615), .B(n3614), .Y(n1808) );
NOR2X4TS U2822 ( .A(DP_OP_499J1_125_4188_n215), .B(DP_OP_499J1_125_4188_n213), .Y(n2851) );
OAI211X1TS U2823 ( .A0(n6394), .A1(n5284), .B0(n5240), .C0(n5239), .Y(n1802)
);
OR2X2TS U2824 ( .A(n3010), .B(n3009), .Y(n2998) );
OAI211X1TS U2825 ( .A0(n6394), .A1(n5231), .B0(n5218), .C0(n5217), .Y(n1798)
);
OAI211X1TS U2826 ( .A0(n6394), .A1(n5219), .B0(n3400), .C0(n3399), .Y(n1805)
);
OAI211X1TS U2827 ( .A0(n6394), .A1(n5237), .B0(n5222), .C0(n5221), .Y(n1803)
);
XOR2X1TS U2828 ( .A(n4213), .B(n4152), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7) );
XOR2X1TS U2829 ( .A(n4066), .B(n4065), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7) );
OAI211X1TS U2830 ( .A0(n6394), .A1(n5206), .B0(n3372), .C0(n3371), .Y(n1793)
);
XOR2X1TS U2831 ( .A(n4227), .B(n4226), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5) );
OAI211X1TS U2832 ( .A0(n3368), .A1(n5206), .B0(n5205), .C0(n5204), .Y(n1790)
);
XOR2X1TS U2833 ( .A(n4163), .B(n4162), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4) );
XOR2X1TS U2834 ( .A(n4071), .B(n4070), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6) );
AOI2BB2X1TS U2835 ( .B0(n2352), .B1(n5203), .A0N(n6394), .A1N(n5202), .Y(
n5204) );
OAI211X1TS U2836 ( .A0(n6396), .A1(n5284), .B0(n5283), .C0(n5282), .Y(n1801)
);
OAI21X1TS U2837 ( .A0(n6121), .A1(n6120), .B0(n6119), .Y(n6126) );
NOR2X2TS U2838 ( .A(n4154), .B(n4223), .Y(n3808) );
NAND3X1TS U2839 ( .A(n4405), .B(FPADDSUB_Shift_reg_FLAGS_7[1]), .C(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n4406) );
OAI21X2TS U2840 ( .A0(n4154), .A1(n4224), .B0(n4155), .Y(n3807) );
NOR2X1TS U2841 ( .A(n4194), .B(n4193), .Y(n4195) );
XOR2X1TS U2842 ( .A(n4080), .B(n4079), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4) );
XOR2X1TS U2843 ( .A(n4173), .B(n4182), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1) );
NOR2X1TS U2844 ( .A(n3645), .B(n3644), .Y(n3646) );
NAND2X2TS U2845 ( .A(n4142), .B(n4147), .Y(n4131) );
INVX6TS U2846 ( .A(n6394), .Y(n4405) );
BUFX6TS U2847 ( .A(n3357), .Y(n6394) );
NOR2X2TS U2848 ( .A(n2989), .B(n4044), .Y(n6166) );
INVX2TS U2849 ( .A(n4072), .Y(n3192) );
AO21X1TS U2850 ( .A0(result_add_subt[6]), .A1(n6219), .B0(n3517), .Y(n1384)
);
OAI21X1TS U2851 ( .A0(n5352), .A1(n5087), .B0(n5086), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
AO21X1TS U2852 ( .A0(result_add_subt[7]), .A1(n6219), .B0(n3523), .Y(n1306)
);
AO21X1TS U2853 ( .A0(result_add_subt[4]), .A1(n6219), .B0(n3513), .Y(n1387)
);
INVX4TS U2854 ( .A(n3368), .Y(n5281) );
NOR2X1TS U2855 ( .A(n6120), .B(n6122), .Y(n2950) );
OR2X2TS U2856 ( .A(DP_OP_501J1_127_1459_n494), .B(n3805), .Y(n2424) );
XOR2X1TS U2857 ( .A(n5426), .B(n5425), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
XOR2X1TS U2858 ( .A(n5437), .B(n5436), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
OR2X2TS U2859 ( .A(n4137), .B(n4136), .Y(n4209) );
XOR2X1TS U2860 ( .A(n5363), .B(n5362), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
XOR2X1TS U2861 ( .A(n4086), .B(n4085), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2) );
XOR2X2TS U2862 ( .A(n2831), .B(n2830), .Y(n4018) );
OAI21X1TS U2863 ( .A0(n4871), .A1(n6657), .B0(n4870), .Y(n1318) );
OAI21X1TS U2864 ( .A0(n4871), .A1(n2307), .B0(n4868), .Y(n2077) );
INVX8TS U2865 ( .A(n2581), .Y(n2965) );
INVX8TS U2866 ( .A(n3652), .Y(n3642) );
MX2X2TS U2867 ( .A(n5819), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n2361),
.Y(n1585) );
OR2X2TS U2868 ( .A(intadd_3_n1), .B(n5532), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11) );
XOR2X1TS U2869 ( .A(n5442), .B(n5441), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
XNOR2X2TS U2870 ( .A(n2886), .B(n2885), .Y(n2989) );
BUFX12TS U2871 ( .A(n3474), .Y(n3652) );
CLKAND2X2TS U2872 ( .A(n5348), .B(n5347), .Y(n2219) );
OAI21X1TS U2873 ( .A0(n6500), .A1(n6424), .B0(n5080), .Y(n1356) );
OAI21X1TS U2874 ( .A0(n2261), .A1(n5179), .B0(n5293), .Y(n1213) );
NAND3BX1TS U2875 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n5890), .C(n5889),
.Y(n5891) );
OAI21X1TS U2876 ( .A0(n2256), .A1(n5265), .B0(n5188), .Y(n1284) );
OAI21X1TS U2877 ( .A0(n2262), .A1(n5179), .B0(n5301), .Y(n1221) );
OAI21X1TS U2878 ( .A0(n3255), .A1(n5265), .B0(n5199), .Y(n1277) );
OAI21X1TS U2879 ( .A0(n2231), .A1(n4402), .B0(n5302), .Y(n1225) );
OAI21X1TS U2880 ( .A0(n2204), .A1(n4402), .B0(n3409), .Y(n1229) );
OAI21X1TS U2881 ( .A0(n6542), .A1(n5265), .B0(n5185), .Y(n1271) );
OAI21X1TS U2882 ( .A0(n3257), .A1(n4402), .B0(n5304), .Y(n1237) );
OAI21X1TS U2883 ( .A0(n3261), .A1(n5179), .B0(n5298), .Y(n1241) );
OAI21X1TS U2884 ( .A0(n2415), .A1(n5179), .B0(n5297), .Y(n1245) );
OAI21X1TS U2885 ( .A0(n3246), .A1(n5179), .B0(n5300), .Y(n1249) );
OAI21X1TS U2886 ( .A0(n3246), .A1(n5197), .B0(n5189), .Y(n1377) );
OAI21X1TS U2887 ( .A0(n2265), .A1(n2439), .B0(n5249), .Y(n1413) );
CLKMX2X2TS U2888 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n5816), .Y(n1587) );
OAI21X1TS U2889 ( .A0(n2255), .A1(n2439), .B0(n5235), .Y(n1401) );
OAI21X1TS U2890 ( .A0(n2259), .A1(n5197), .B0(n5182), .Y(n1371) );
OAI21X1TS U2891 ( .A0(n2261), .A1(n2439), .B0(n5236), .Y(n1404) );
OAI21X1TS U2892 ( .A0(n4306), .A1(n4288), .B0(n3833), .Y(n3832) );
OAI21X1TS U2893 ( .A0(n2258), .A1(n5197), .B0(n5186), .Y(n1368) );
OAI21X1TS U2894 ( .A0(n2415), .A1(n5197), .B0(n5192), .Y(n1380) );
OAI21X1TS U2895 ( .A0(n3248), .A1(n5197), .B0(n5191), .Y(n1365) );
XOR2X1TS U2896 ( .A(n5451), .B(n5450), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
OAI21X1TS U2897 ( .A0(n5079), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n5887),
.Y(n5080) );
OAI21X1TS U2898 ( .A0(n2262), .A1(n5265), .B0(n5193), .Y(n1398) );
OAI21X1TS U2899 ( .A0(n2231), .A1(n2439), .B0(n5194), .Y(n1395) );
OR2X2TS U2900 ( .A(n5174), .B(n5173), .Y(n5408) );
OAI21X1TS U2901 ( .A0(n2418), .A1(n5197), .B0(n5180), .Y(n1328) );
OAI21X1TS U2902 ( .A0(n6698), .A1(n5308), .B0(n5285), .Y(n1462) );
OAI21X1TS U2903 ( .A0(n2204), .A1(n2439), .B0(n5184), .Y(n1392) );
OAI21X1TS U2904 ( .A0(n4676), .A1(n6657), .B0(n4675), .Y(n1322) );
OAI21X1TS U2905 ( .A0(n6707), .A1(n5308), .B0(n5268), .Y(n1463) );
NAND2X6TS U2906 ( .A(n5887), .B(n5078), .Y(n6491) );
OAI21X1TS U2907 ( .A0(n2263), .A1(n5265), .B0(n5187), .Y(n1312) );
NOR2X1TS U2908 ( .A(n2374), .B(n4275), .Y(n4283) );
OR2X2TS U2909 ( .A(DP_OP_500J1_126_2852_n101), .B(n5169), .Y(n2232) );
OAI21X1TS U2910 ( .A0(n3314), .A1(n5308), .B0(n5287), .Y(n1460) );
OAI21X1TS U2911 ( .A0(n6706), .A1(n5308), .B0(n5267), .Y(n1459) );
OAI21X1TS U2912 ( .A0(n6708), .A1(n5308), .B0(n5266), .Y(n1458) );
OAI21X1TS U2913 ( .A0(n2265), .A1(n5308), .B0(n5295), .Y(n1461) );
OAI21X1TS U2914 ( .A0(n3261), .A1(n5197), .B0(n5190), .Y(n1383) );
OAI21X1TS U2915 ( .A0(n2260), .A1(n5292), .B0(n5291), .Y(n1296) );
OAI21X1TS U2916 ( .A0(n2260), .A1(n5265), .B0(n5183), .Y(n1298) );
OAI21X1TS U2917 ( .A0(n2264), .A1(n5197), .B0(n5181), .Y(n1389) );
OAI21X1TS U2918 ( .A0(n4676), .A1(n2307), .B0(n4674), .Y(n2076) );
OAI21X1TS U2919 ( .A0(n3262), .A1(n5265), .B0(n5198), .Y(n1305) );
AOI2BB1X1TS U2920 ( .A0N(n5892), .A1N(overflow_flag_addsubt), .B0(n5887),
.Y(n1411) );
OAI21X1TS U2921 ( .A0(n2263), .A1(n5308), .B0(n5296), .Y(n1310) );
OAI21X1TS U2922 ( .A0(n4653), .A1(n6657), .B0(n4651), .Y(n1330) );
OAI21X1TS U2923 ( .A0(n2258), .A1(n5292), .B0(n5256), .Y(n1261) );
OAI21X1TS U2924 ( .A0(n6653), .A1(n5292), .B0(n5251), .Y(n1289) );
OAI21X1TS U2925 ( .A0(n2259), .A1(n5292), .B0(n5254), .Y(n1257) );
OAI21X1TS U2926 ( .A0(n2404), .A1(n5292), .B0(n5253), .Y(n1253) );
ADDHX2TS U2927 ( .A(n4322), .B(n4321), .CO(mult_x_313_n42), .S(n3819) );
OAI21X1TS U2928 ( .A0(n6651), .A1(n5308), .B0(n5261), .Y(n1464) );
OAI21X1TS U2929 ( .A0(n4653), .A1(n2307), .B0(n4652), .Y(n2075) );
OAI21X1TS U2930 ( .A0(n3248), .A1(n5292), .B0(n5260), .Y(n1265) );
OAI21X1TS U2931 ( .A0(n3255), .A1(n5292), .B0(n3322), .Y(n1275) );
NOR2X1TS U2932 ( .A(n2373), .B(n4278), .Y(n3775) );
OAI21X1TS U2933 ( .A0(n2256), .A1(n5292), .B0(n5257), .Y(n1282) );
XOR2X1TS U2934 ( .A(n5456), .B(n5455), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
XOR2X1TS U2935 ( .A(n5381), .B(n5380), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
AOI222X1TS U2936 ( .A0(n5263), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n6639), .C0(n6544), .C1(n5262), .Y(
n5264) );
OAI21X1TS U2937 ( .A0(n2257), .A1(n5179), .B0(n5258), .Y(n1209) );
OAI211X1TS U2938 ( .A0(n7020), .A1(n2414), .B0(n5055), .C0(n5054), .Y(n1928)
);
NAND3X1TS U2939 ( .A(n6341), .B(n6340), .C(n6359), .Y(n1840) );
NAND3X1TS U2940 ( .A(n6343), .B(n6342), .C(n6354), .Y(n1838) );
NAND3X1TS U2941 ( .A(n6347), .B(n6346), .C(n6349), .Y(n1836) );
OAI211X1TS U2942 ( .A0(n7020), .A1(n6312), .B0(n5053), .C0(n5052), .Y(n1927)
);
NAND3X1TS U2943 ( .A(n6386), .B(n6385), .C(n6387), .Y(n1815) );
OAI211X1TS U2944 ( .A0(n7021), .A1(n6798), .B0(n5071), .C0(n5070), .Y(n1916)
);
OAI211X1TS U2945 ( .A0(n7021), .A1(n6740), .B0(n5077), .C0(n5076), .Y(n1912)
);
OAI211X1TS U2946 ( .A0(n5065), .A1(n2407), .B0(n5064), .C0(n5063), .Y(n1819)
);
OAI211X1TS U2947 ( .A0(n7022), .A1(n2420), .B0(n5026), .C0(n5025), .Y(n1843)
);
OAI211X1TS U2948 ( .A0(n7021), .A1(n6797), .B0(n5069), .C0(n5068), .Y(n1917)
);
OAI211X1TS U2949 ( .A0(n7020), .A1(n6315), .B0(n5051), .C0(n5050), .Y(n1925)
);
OAI211X1TS U2950 ( .A0(n7021), .A1(n6297), .B0(n4943), .C0(n4942), .Y(n1941)
);
NOR2X1TS U2951 ( .A(n4256), .B(n4248), .Y(n4135) );
INVX3TS U2952 ( .A(n2240), .Y(n2285) );
NOR2X1TS U2953 ( .A(n4277), .B(n4275), .Y(n3774) );
OAI211X1TS U2954 ( .A0(n7021), .A1(n6320), .B0(n5049), .C0(n5048), .Y(n1921)
);
OAI211X1TS U2955 ( .A0(n7021), .A1(n6799), .B0(n5067), .C0(n5066), .Y(n1915)
);
OAI211X1TS U2956 ( .A0(n7021), .A1(n6741), .B0(n5075), .C0(n5074), .Y(n1914)
);
OAI211X1TS U2957 ( .A0(n5065), .A1(n2389), .B0(n4967), .C0(n4966), .Y(n1818)
);
OAI211X1TS U2958 ( .A0(n4965), .A1(n6307), .B0(n4957), .C0(n4956), .Y(n1933)
);
OAI211X1TS U2959 ( .A0(n7022), .A1(n2396), .B0(n5036), .C0(n5035), .Y(n1833)
);
OAI211X1TS U2960 ( .A0(n2357), .A1(n6808), .B0(n4705), .C0(n4704), .Y(n1518)
);
NAND3X1TS U2961 ( .A(n6367), .B(n6366), .C(n6365), .Y(n1825) );
NAND3X1TS U2962 ( .A(n6378), .B(n6377), .C(n6376), .Y(n1821) );
OAI211X1TS U2963 ( .A0(n4965), .A1(n6305), .B0(n4945), .C0(n4944), .Y(n1934)
);
OAI211X1TS U2964 ( .A0(n4965), .A1(n6304), .B0(n4947), .C0(n4946), .Y(n1936)
);
OAI211X1TS U2965 ( .A0(n2357), .A1(n6806), .B0(n4765), .C0(n4764), .Y(n1520)
);
OAI211X1TS U2966 ( .A0(n2357), .A1(n6809), .B0(n4774), .C0(n4773), .Y(n1517)
);
NOR2X1TS U2967 ( .A(n4121), .B(n4257), .Y(n4253) );
OAI211X1TS U2968 ( .A0(n7022), .A1(n2423), .B0(n5030), .C0(n5029), .Y(n1834)
);
OAI211X1TS U2969 ( .A0(n2358), .A1(n6802), .B0(n4769), .C0(n4768), .Y(n1524)
);
NAND3X1TS U2970 ( .A(n6370), .B(n6369), .C(n6376), .Y(n1824) );
OAI211X1TS U2971 ( .A0(n2358), .A1(n6812), .B0(n4771), .C0(n4770), .Y(n1514)
);
OAI211X1TS U2972 ( .A0(n2357), .A1(n6803), .B0(n4767), .C0(n4766), .Y(n1523)
);
OAI211X1TS U2973 ( .A0(n5065), .A1(n2397), .B0(n5032), .C0(n5031), .Y(n1831)
);
OAI211X1TS U2974 ( .A0(n4965), .A1(n6299), .B0(n4951), .C0(n4950), .Y(n1939)
);
OAI211X1TS U2975 ( .A0(n2358), .A1(n6816), .B0(n4780), .C0(n4779), .Y(n1510)
);
OAI211X1TS U2976 ( .A0(n4965), .A1(n2410), .B0(n4955), .C0(n4954), .Y(n1935)
);
OAI211X1TS U2977 ( .A0(n2359), .A1(n6801), .B0(n4709), .C0(n4708), .Y(n1525)
);
OAI211X1TS U2978 ( .A0(n5065), .A1(n2416), .B0(n5012), .C0(n5011), .Y(n1822)
);
AND2X2TS U2979 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3503), .Y(n2450) );
OAI211X1TS U2980 ( .A0(n2358), .A1(n6811), .B0(n4711), .C0(n4710), .Y(n1515)
);
NOR2X1TS U2981 ( .A(n2243), .B(n4246), .Y(n3812) );
OAI211X1TS U2982 ( .A0(n2359), .A1(n6815), .B0(n4713), .C0(n4712), .Y(n1511)
);
OAI211X1TS U2983 ( .A0(n4965), .A1(n6308), .B0(n4949), .C0(n4948), .Y(n1932)
);
OAI211X1TS U2984 ( .A0(n4965), .A1(n6302), .B0(n4964), .C0(n4963), .Y(n1938)
);
OAI211X1TS U2985 ( .A0(n2359), .A1(n6817), .B0(n4786), .C0(n4785), .Y(n1509)
);
OAI211X1TS U2986 ( .A0(n2359), .A1(n6819), .B0(n4718), .C0(n4717), .Y(n1507)
);
OAI211X1TS U2987 ( .A0(n5065), .A1(n2390), .B0(n4969), .C0(n4968), .Y(n1817)
);
OAI211X1TS U2988 ( .A0(n2359), .A1(n6820), .B0(n4776), .C0(n4775), .Y(n1506)
);
AO22X1TS U2989 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n6265), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n6263), .Y(n1989) );
AO22X1TS U2990 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n6265), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n6263), .Y(n1987) );
OAI2BB2XLTS U2991 ( .B0(n6798), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[25]),
.A1N(n6326), .Y(n1859) );
OAI2BB2XLTS U2992 ( .B0(n6316), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[17]),
.A1N(n6323), .Y(n1873) );
AO22X1TS U2993 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n6265), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n6263), .Y(n2005) );
AOI222X1TS U2994 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6326), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n4974), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n4939) );
OAI2BB2XLTS U2995 ( .B0(n6324), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[22]),
.A1N(n6323), .Y(n1863) );
OAI2BB2XLTS U2996 ( .B0(n6299), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[2]), .A1N(
n6336), .Y(n1903) );
AO22X1TS U2997 ( .A0(n6335), .A1(n6334), .B0(n6321), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1846) );
OAI2BB2XLTS U2998 ( .B0(n6304), .B1(n4612), .A0N(FPSENCOS_d_ff_Yn[5]), .A1N(
n6310), .Y(n1897) );
OAI2BB2XLTS U2999 ( .B0(n6312), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[14]),
.A1N(n6323), .Y(n1879) );
OAI2BB2XLTS U3000 ( .B0(n7047), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[12]),
.A1N(n6310), .Y(n1883) );
NOR2X1TS U3001 ( .A(n5580), .B(n5581), .Y(n5557) );
AOI2BB2X1TS U3002 ( .B0(n6332), .B1(n6331), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n6330), .Y(n1847) );
OAI21X1TS U3003 ( .A0(n4851), .A1(n5690), .B0(n5692), .Y(n4852) );
AO22X1TS U3004 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n6282), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n6336), .Y(n1952) );
OAI2BB2XLTS U3005 ( .B0(n6799), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[26]),
.A1N(n6326), .Y(n1858) );
AOI222X1TS U3006 ( .A0(n6282), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n5007), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n6326), .Y(n4970)
);
AO22X1TS U3007 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n6282), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n6336), .Y(n1959) );
OAI2BB2XLTS U3008 ( .B0(n6302), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[3]), .A1N(
n6310), .Y(n1901) );
OAI2BB2XLTS U3009 ( .B0(n6308), .B1(n7023), .A0N(FPSENCOS_d_ff_Yn[9]), .A1N(
n6310), .Y(n1889) );
OAI2BB2XLTS U3010 ( .B0(n6297), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[0]), .A1N(
n6336), .Y(n1907) );
AO22X1TS U3011 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n6265), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n6263), .Y(n1997) );
OAI21X1TS U3012 ( .A0(n4756), .A1(n5583), .B0(n5585), .Y(n4757) );
OAI211X1TS U3013 ( .A0(n2359), .A1(n6810), .B0(n4643), .C0(n4642), .Y(n1516)
);
OAI2BB2XLTS U3014 ( .B0(n7048), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[23]),
.A1N(n6326), .Y(n1861) );
OAI2BB2XLTS U3015 ( .B0(n6303), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[4]), .A1N(
n6310), .Y(n1899) );
OAI2BB2XLTS U3016 ( .B0(n6309), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[11]),
.A1N(n6310), .Y(n1885) );
AO22X1TS U3017 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n6282), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n6336), .Y(n1961) );
OAI2BB2XLTS U3018 ( .B0(n6298), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[1]), .A1N(
n6336), .Y(n1905) );
OAI2BB2XLTS U3019 ( .B0(n6318), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[18]),
.A1N(n6323), .Y(n1871) );
OAI211X1TS U3020 ( .A0(n2358), .A1(n6821), .B0(n4665), .C0(n4664), .Y(n1505)
);
NAND3X1TS U3021 ( .A(n6356), .B(n6355), .C(n6354), .Y(n1829) );
OAI2BB2XLTS U3022 ( .B0(n6740), .B1(n6337), .A0N(FPSENCOS_d_ff_Yn[29]),
.A1N(n6326), .Y(n1855) );
NAND3X1TS U3023 ( .A(n6373), .B(n6372), .C(n6371), .Y(n1823) );
NOR2X1TS U3024 ( .A(n2299), .B(n5462), .Y(n5168) );
NAND3X1TS U3025 ( .A(n6353), .B(n6352), .C(n6365), .Y(n1830) );
AO22X1TS U3026 ( .A0(FPSENCOS_d_ff2_X[31]), .A1(n6282), .B0(n6336), .B1(
FPSENCOS_d_ff_Xn[31]), .Y(n1943) );
NAND3X1TS U3027 ( .A(n6361), .B(n6360), .C(n6359), .Y(n1827) );
OAI2BB2XLTS U3028 ( .B0(n6320), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[20]),
.A1N(n6323), .Y(n1867) );
AOI2BB2X1TS U3029 ( .B0(n6301), .B1(n6281), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n6413), .Y(n1945) );
OAI2BB2XLTS U3030 ( .B0(n6319), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[19]),
.A1N(n6323), .Y(n1869) );
OAI2BB2XLTS U3031 ( .B0(n6315), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[16]),
.A1N(n6323), .Y(n1875) );
OAI21X1TS U3032 ( .A0(n4941), .A1(n4692), .B0(n4691), .Y(n1731) );
OAI21X1TS U3033 ( .A0(n5621), .A1(n4933), .B0(n5619), .Y(n4934) );
OAI2BB2XLTS U3034 ( .B0(n7046), .B1(n6311), .A0N(FPSENCOS_d_ff_Yn[10]),
.A1N(n6310), .Y(n1887) );
OAI2BB2XLTS U3035 ( .B0(n6322), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[21]),
.A1N(n6323), .Y(n1865) );
AO22X1TS U3036 ( .A0(n6335), .A1(n4614), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1944) );
AO22X1TS U3037 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n6282), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n6336), .Y(n1963) );
AOI21X2TS U3038 ( .A0(n4125), .A1(n4113), .B0(n4119), .Y(n3791) );
OAI2BB2XLTS U3039 ( .B0(n6307), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[8]), .A1N(
n6310), .Y(n1891) );
AO22X1TS U3040 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n6265), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n6263), .Y(n1975) );
OAI2BB2XLTS U3041 ( .B0(n2414), .B1(n7023), .A0N(FPSENCOS_d_ff_Yn[13]),
.A1N(n6323), .Y(n1881) );
NAND3X1TS U3042 ( .A(n6383), .B(n6382), .C(n6387), .Y(n1816) );
OAI211X1TS U3043 ( .A0(n6275), .A1(n6825), .B0(n6239), .C0(n6229), .Y(n2126)
);
AO22X1TS U3044 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n6265), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n6263), .Y(n1983) );
OAI2BB2XLTS U3045 ( .B0(n6741), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[27]),
.A1N(n6326), .Y(n1857) );
OAI211X1TS U3046 ( .A0(n5065), .A1(n6273), .B0(n4972), .C0(n4971), .Y(n1820)
);
OAI2BB2XLTS U3047 ( .B0(n7049), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[28]),
.A1N(n6326), .Y(n1856) );
OAI2BB2XLTS U3048 ( .B0(n6305), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[7]), .A1N(
n6310), .Y(n1893) );
OAI2BB2XLTS U3049 ( .B0(n6313), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[15]),
.A1N(n6323), .Y(n1877) );
OAI211X1TS U3050 ( .A0(n2358), .A1(n6813), .B0(n4658), .C0(n4657), .Y(n1513)
);
AO22X1TS U3051 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n6480), .B0(
mult_result[10]), .B1(n6479), .Y(n1494) );
AO22X1TS U3052 ( .A0(n4613), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n6226), .B1(
Data_1[0]), .Y(n2112) );
AO22X1TS U3053 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n6480), .B0(
mult_result[13]), .B1(n6479), .Y(n1491) );
AO22X1TS U3054 ( .A0(n6266), .A1(n4610), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1848) );
AO22X1TS U3055 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2337), .B0(
mult_result[22]), .B1(n6479), .Y(n1481) );
OAI211X1TS U3056 ( .A0(n6275), .A1(n6822), .B0(n6230), .C0(n4678), .Y(n2132)
);
OAI211X1TS U3057 ( .A0(n2359), .A1(n6818), .B0(n4656), .C0(n4655), .Y(n1508)
);
AO22X1TS U3058 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n6480), .B0(
mult_result[15]), .B1(n6479), .Y(n1489) );
AO22X1TS U3059 ( .A0(n6413), .A1(n4608), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1946) );
AO22X1TS U3060 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n2337), .B0(
mult_result[17]), .B1(n6479), .Y(n1487) );
NOR2X1TS U3061 ( .A(n5687), .B(n5688), .Y(n5662) );
INVX2TS U3062 ( .A(n6267), .Y(n4992) );
INVX4TS U3063 ( .A(n2372), .Y(n2283) );
INVX2TS U3064 ( .A(n4936), .Y(n5008) );
OAI211X1TS U3065 ( .A0(n2357), .A1(n6805), .B0(n4660), .C0(n4659), .Y(n1521)
);
OAI211X1TS U3066 ( .A0(n2357), .A1(n6800), .B0(n4662), .C0(n4661), .Y(n1526)
);
AO22X1TS U3067 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n2337), .B0(
mult_result[9]), .B1(n6476), .Y(n1495) );
ADDHX2TS U3068 ( .A(n3629), .B(n3628), .CO(n3630), .S(n3627) );
AO22X1TS U3069 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2337), .B0(
mult_result[8]), .B1(n6476), .Y(n1496) );
AO22X1TS U3070 ( .A0(n4613), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n6226), .B1(
Data_1[1]), .Y(n2111) );
AO22X1TS U3071 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n2337), .B0(
mult_result[5]), .B1(n6476), .Y(n1499) );
AO22X1TS U3072 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n6226), .B1(
Data_1[2]), .Y(n2110) );
AO22X1TS U3073 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n2337), .B0(
mult_result[4]), .B1(n6476), .Y(n1500) );
AO22X1TS U3074 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n6226), .B1(
Data_1[3]), .Y(n2109) );
AO22X1TS U3075 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n2337), .B0(
mult_result[3]), .B1(n6476), .Y(n1501) );
AO22X1TS U3076 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n6226), .B1(
Data_1[4]), .Y(n2108) );
AO22X1TS U3077 ( .A0(n6255), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n6226), .B1(
Data_1[5]), .Y(n2107) );
AO22X1TS U3078 ( .A0(n4613), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n6251), .B1(
Data_1[6]), .Y(n2106) );
AO22X1TS U3079 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n6251), .B1(
Data_1[7]), .Y(n2105) );
AO22X1TS U3080 ( .A0(n2337), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n6478), .Y(n1504) );
AO22X1TS U3081 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n6251), .B1(
Data_1[8]), .Y(n2104) );
AO22X1TS U3082 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n6251), .B1(
Data_1[9]), .Y(n2103) );
AO22X1TS U3083 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n6251), .B1(
Data_1[10]), .Y(n2102) );
AO22X1TS U3084 ( .A0(n6250), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n6251), .B1(
Data_1[11]), .Y(n2101) );
AO22X1TS U3085 ( .A0(n4613), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n6251), .B1(
Data_1[12]), .Y(n2100) );
AO22X1TS U3086 ( .A0(n4613), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n6251), .B1(
Data_1[13]), .Y(n2099) );
AO22X1TS U3087 ( .A0(n4613), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n6251), .B1(
Data_1[14]), .Y(n2098) );
OAI211X1TS U3088 ( .A0(n4682), .A1(n4679), .B0(n4678), .C0(n4677), .Y(n2123)
);
AO22X1TS U3089 ( .A0(n4613), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n6253), .B1(
Data_1[15]), .Y(n2097) );
OAI21X1TS U3090 ( .A0(n6244), .A1(n4681), .B0(n4680), .Y(n2129) );
AO22X1TS U3091 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n6253), .B1(
Data_1[16]), .Y(n2096) );
AO22X1TS U3092 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n6253), .B1(
Data_1[17]), .Y(n2095) );
AO22X1TS U3093 ( .A0(n6255), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n6253), .B1(
Data_1[27]), .Y(n2085) );
AO22X1TS U3094 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n6253), .B1(
Data_1[20]), .Y(n2092) );
AO22X1TS U3095 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n6253), .B1(
Data_1[18]), .Y(n2094) );
INVX2TS U3096 ( .A(n6267), .Y(n4997) );
AO22X1TS U3097 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n6253), .B1(
Data_1[21]), .Y(n2091) );
AO22X1TS U3098 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n6253), .B1(
Data_1[19]), .Y(n2093) );
OAI211X1TS U3099 ( .A0(n2357), .A1(n6807), .B0(n4640), .C0(n4639), .Y(n1519)
);
AO22X1TS U3100 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n6253), .B1(
Data_1[22]), .Y(n2090) );
XNOR2X2TS U3101 ( .A(n4036), .B(n4035), .Y(n6141) );
AO22X1TS U3102 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n6253), .B1(
Data_1[23]), .Y(n2089) );
AO22X1TS U3103 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n6251), .B1(
Data_1[24]), .Y(n2088) );
NOR2X1TS U3104 ( .A(n6524), .B(n6497), .Y(n6498) );
OAI21X1TS U3105 ( .A0(n5632), .A1(n5631), .B0(n5633), .Y(n4882) );
AO22X1TS U3106 ( .A0(n6255), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n6254), .B1(
Data_1[31]), .Y(n2081) );
AO22X1TS U3107 ( .A0(n6255), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n6254), .B1(
Data_1[30]), .Y(n2082) );
AO22X1TS U3108 ( .A0(n6255), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n6254), .B1(
Data_1[29]), .Y(n2083) );
AO22X1TS U3109 ( .A0(n6255), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n6254), .B1(
Data_1[28]), .Y(n2084) );
AO22X1TS U3110 ( .A0(n6255), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n6254), .B1(
Data_1[26]), .Y(n2086) );
NOR2X1TS U3111 ( .A(n6524), .B(n6501), .Y(n6502) );
AO22X1TS U3112 ( .A0(n6252), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n6254), .B1(
Data_1[25]), .Y(n2087) );
NOR2X1TS U3113 ( .A(n6524), .B(n6507), .Y(n6508) );
NOR2X1TS U3114 ( .A(n6524), .B(n6504), .Y(n6505) );
ADDHX2TS U3115 ( .A(n4109), .B(n4108), .CO(n4110), .S(n3838) );
OAI21X1TS U3116 ( .A0(n5525), .A1(n5111), .B0(n5526), .Y(n5112) );
OAI21X1TS U3117 ( .A0(n5521), .A1(n5520), .B0(n5522), .Y(n5123) );
NOR2X1TS U3118 ( .A(n5471), .B(n5466), .Y(n4431) );
OAI211X1TS U3119 ( .A0(n6271), .A1(n6682), .B0(n6244), .C0(n2230), .Y(n4680)
);
OAI21X1TS U3120 ( .A0(n5592), .A1(n5591), .B0(n5593), .Y(n4734) );
NOR2X1TS U3121 ( .A(n6524), .B(n6514), .Y(n6515) );
OAI21X1TS U3122 ( .A0(n4903), .A1(n4902), .B0(n4901), .Y(n4904) );
OAI21X1TS U3123 ( .A0(n4925), .A1(n4924), .B0(n4923), .Y(n4926) );
AOI2BB2X1TS U3124 ( .B0(n5863), .B1(n5875), .A0N(n5883), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1199) );
AOI2BB2X1TS U3125 ( .B0(n5859), .B1(n5875), .A0N(n5878), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n1197) );
AOI2BB2X1TS U3126 ( .B0(n5858), .B1(n5875), .A0N(n5878), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n1196) );
NOR2X1TS U3127 ( .A(n6603), .B(n6585), .Y(n6586) );
NOR2X1TS U3128 ( .A(n6603), .B(n6593), .Y(n6594) );
NOR2X1TS U3129 ( .A(n6603), .B(n6596), .Y(n6597) );
OAI21X1TS U3130 ( .A0(n6621), .A1(n4238), .B0(n4239), .Y(n6622) );
NOR2X4TS U3131 ( .A(n3218), .B(n3217), .Y(n3724) );
NOR2X4TS U3132 ( .A(n3673), .B(n3226), .Y(n3731) );
NOR2X1TS U3133 ( .A(n6524), .B(n6490), .Y(n6492) );
OAI211X2TS U3134 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n6271), .B0(n6233),
.C0(n6663), .Y(n4678) );
AO22X1TS U3135 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[11]), .B0(n6306), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1982) );
AO22X1TS U3136 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n6480), .B0(
mult_result[6]), .B1(n6476), .Y(n1498) );
AO22X1TS U3137 ( .A0(n6413), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6412), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1732) );
AO22X1TS U3138 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[7]), .B0(n6306), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1990) );
AO22X1TS U3139 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[15]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1974) );
AND2X2TS U3140 ( .A(n4913), .B(n4911), .Y(n5620) );
NOR2X1TS U3141 ( .A(n1673), .B(n1661), .Y(n6623) );
AO22X1TS U3142 ( .A0(n2383), .A1(n5833), .B0(n5832), .B1(n5831), .Y(n6523)
);
AO22X1TS U3143 ( .A0(n6480), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n6478), .Y(n1503) );
OAI21X1TS U3144 ( .A0(n5560), .A1(n5559), .B0(n5558), .Y(n5561) );
NOR2X1TS U3145 ( .A(n2383), .B(n5873), .Y(n5880) );
AO22X1TS U3146 ( .A0(n6413), .A1(intadd_5_SUM_0_), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1852) );
AO22X1TS U3147 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[5]), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1994) );
AO22X1TS U3148 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n6480), .B0(
mult_result[21]), .B1(n6479), .Y(n1483) );
AO22X1TS U3149 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n6480), .B0(
mult_result[16]), .B1(n6479), .Y(n1488) );
AO22X1TS U3150 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[13]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1978) );
AO22X1TS U3151 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n6480), .B0(
mult_result[14]), .B1(n6479), .Y(n1490) );
AO22X1TS U3152 ( .A0(n6413), .A1(FPSENCOS_d_ff2_X[22]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1960) );
AO22X1TS U3153 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n6480), .B0(
mult_result[12]), .B1(n6479), .Y(n1492) );
OAI21X1TS U3154 ( .A0(n5699), .A1(n5698), .B0(n5700), .Y(n4829) );
AO22X1TS U3155 ( .A0(n6266), .A1(n6242), .B0(n6306), .B1(
FPSENCOS_d_ff3_LUT_out[23]), .Y(n2117) );
AO22X1TS U3156 ( .A0(n6413), .A1(FPSENCOS_d_ff2_X[17]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1970) );
AO22X1TS U3157 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[20]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1964) );
OR2X2TS U3158 ( .A(n2378), .B(n2379), .Y(n2249) );
NOR2X2TS U3159 ( .A(n4359), .B(n6427), .Y(n4360) );
AO22X1TS U3160 ( .A0(n6413), .A1(FPSENCOS_d_ff2_X[18]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1968) );
AO21X4TS U3161 ( .A0(n6232), .A1(n6682), .B0(n6269), .Y(n4936) );
NOR2X1TS U3162 ( .A(n2383), .B(n4499), .Y(n4502) );
AO22X1TS U3163 ( .A0(n5874), .A1(n5830), .B0(n5832), .B1(n5829), .Y(n6494)
);
AO22X1TS U3164 ( .A0(n6413), .A1(FPSENCOS_d_ff2_X[19]), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1966) );
NOR2X1TS U3165 ( .A(n1670), .B(n1658), .Y(n6624) );
AOI222X1TS U3166 ( .A0(n4783), .A1(n6826), .B0(n7025), .B1(n4634), .C0(n6658), .C1(n4654), .Y(n1621) );
AO22X1TS U3167 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[3]), .B0(n6412), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1998) );
AO22X1TS U3168 ( .A0(n6266), .A1(FPSENCOS_d_ff2_X[14]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1976) );
AO22X1TS U3169 ( .A0(n2383), .A1(n5827), .B0(n5832), .B1(n5826), .Y(n5828)
);
OAI21X1TS U3170 ( .A0(n5515), .A1(n5512), .B0(n5513), .Y(n5145) );
AOI32X1TS U3171 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n6392), .A2(
n6657), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n5201), .Y(n4674)
);
INVX3TS U3172 ( .A(n6337), .Y(n4993) );
AND3X2TS U3173 ( .A(n3382), .B(n3381), .C(n3380), .Y(n5220) );
AND3X2TS U3174 ( .A(n3385), .B(n3384), .C(n3383), .Y(n5207) );
NOR2X1TS U3175 ( .A(n2272), .B(n6241), .Y(n2379) );
NOR2X1TS U3176 ( .A(n6682), .B(n6241), .Y(n2378) );
OAI21X1TS U3177 ( .A0(n5616), .A1(n5613), .B0(n5615), .Y(n5612) );
CLKMX2X2TS U3178 ( .A(Data_1[2]), .B(n6840), .S0(n5492), .Y(n1660) );
CLKMX2X2TS U3179 ( .A(Data_1[1]), .B(n6794), .S0(n5494), .Y(
DP_OP_501J1_127_1459_n943) );
CLKMX2X2TS U3180 ( .A(Data_1[12]), .B(n6828), .S0(n5496), .Y(n1670) );
CLKMX2X2TS U3181 ( .A(Data_1[13]), .B(n6795), .S0(n5496), .Y(
DP_OP_501J1_127_1459_n930) );
CLKMX2X2TS U3182 ( .A(Data_1[3]), .B(n6830), .S0(n5818), .Y(n1661) );
INVX2TS U3183 ( .A(n4123), .Y(n4124) );
AOI32X1TS U3184 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n6392), .A2(
n6657), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n5201), .Y(n4652)
);
INVX2TS U3185 ( .A(n6301), .Y(n6321) );
CLKMX2X2TS U3186 ( .A(Data_1[14]), .B(DP_OP_501J1_127_1459_n931), .S0(n5496),
.Y(n1672) );
OAI21X1TS U3187 ( .A0(n6474), .A1(underflow_flag_mult), .B0(n6473), .Y(n6475) );
INVX2TS U3188 ( .A(n6301), .Y(n6272) );
OAI21X1TS U3189 ( .A0(n5665), .A1(n5664), .B0(n5663), .Y(n5666) );
AND3X2TS U3190 ( .A(n5216), .B(n5215), .C(n5214), .Y(n5277) );
NAND3X1TS U3191 ( .A(n3365), .B(n3364), .C(n3363), .Y(n5225) );
OAI31XLTS U3192 ( .A0(n6225), .A1(FPSENCOS_cont_var_out[1]), .A2(n6710),
.B0(n4607), .Y(n2136) );
OAI21X1TS U3193 ( .A0(n6085), .A1(n6084), .B0(n6083), .Y(n6087) );
NAND2BX1TS U3194 ( .AN(n5710), .B(n5709), .Y(n5712) );
CLKMX2X2TS U3195 ( .A(Data_1[0]), .B(FPMULT_Op_MX[0]), .S0(n5494), .Y(n1658)
);
NOR2X4TS U3196 ( .A(n6101), .B(FPADDSUB_OP_FLAG_SFG), .Y(n4565) );
OAI21X1TS U3197 ( .A0(n6085), .A1(n5952), .B0(n5951), .Y(n5954) );
OAI222X1TS U3198 ( .A0(n2307), .A1(FPADDSUB_Raw_mant_NRM_SWR[9]), .B0(n2350),
.B1(FPADDSUB_Raw_mant_NRM_SWR[16]), .C0(FPADDSUB_DmP_mant_SHT1_SW[14]),
.C1(n5885), .Y(n5237) );
NOR2X1TS U3199 ( .A(n4633), .B(n4632), .Y(n1692) );
NAND3X1TS U3200 ( .A(n5815), .B(n6478), .C(n5814), .Y(n1693) );
AOI32X1TS U3201 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n6392), .A2(
n6657), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n5201), .Y(n4868)
);
NOR2X1TS U3202 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n3507) );
INVX1TS U3203 ( .A(n4732), .Y(n5560) );
NAND2X2TS U3204 ( .A(n2672), .B(n2717), .Y(n2673) );
NOR2X1TS U3205 ( .A(n5461), .B(n2346), .Y(n5089) );
NOR2X4TS U3206 ( .A(n6176), .B(n5890), .Y(n5816) );
NOR2X1TS U3207 ( .A(n4726), .B(n4727), .Y(n4731) );
NAND2X4TS U3208 ( .A(n5318), .B(n6206), .Y(n4538) );
XOR2X2TS U3209 ( .A(n4419), .B(n4418), .Y(n4420) );
AOI21X2TS U3210 ( .A0(n3237), .A1(n3233), .B0(n3148), .Y(n3149) );
NAND3BX1TS U3211 ( .AN(n4498), .B(n4497), .C(n4495), .Y(n4496) );
NOR2X1TS U3212 ( .A(n5503), .B(n5502), .Y(n4547) );
NOR2X1TS U3213 ( .A(n4315), .B(n4314), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0) );
NAND2X2TS U3214 ( .A(n2560), .B(n2559), .Y(n2561) );
AO21X1TS U3215 ( .A0(n5511), .A1(n5510), .B0(n5509), .Y(intadd_3_B_6_) );
NAND2XLTS U3216 ( .A(n3605), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3603) );
NOR2X4TS U3217 ( .A(n6176), .B(n4490), .Y(n4654) );
AND3X2TS U3218 ( .A(n5812), .B(FPMULT_FSM_selector_C), .C(n6176), .Y(n2253)
);
NAND2X2TS U3219 ( .A(n3234), .B(n3237), .Y(n3150) );
OAI211X2TS U3220 ( .A0(n2449), .A1(n3521), .B0(n3520), .C0(n5837), .Y(n5831)
);
NOR3X2TS U3221 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n6699),
.C(n4611), .Y(n4612) );
INVX6TS U3222 ( .A(n2471), .Y(n2526) );
INVX3TS U3223 ( .A(n3097), .Y(n3098) );
NAND2BX1TS U3224 ( .AN(n5603), .B(n5602), .Y(n5605) );
NOR2X4TS U3225 ( .A(n3948), .B(n3950), .Y(n3922) );
INVX4TS U3226 ( .A(n6392), .Y(n5201) );
NOR2X1TS U3227 ( .A(n4625), .B(n5401), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
INVX2TS U3228 ( .A(n3362), .Y(n5269) );
NOR2X1TS U3229 ( .A(n5387), .B(n5392), .Y(n4425) );
NOR2X1TS U3230 ( .A(n5502), .B(n5094), .Y(intadd_3_B_0_) );
NOR2X1TS U3231 ( .A(n4823), .B(n4824), .Y(n4827) );
OAI211X2TS U3232 ( .A0(n6709), .A1(n3521), .B0(n3516), .C0(n5837), .Y(n5829)
);
AND2X2TS U3233 ( .A(n2326), .B(FPADDSUB_OP_FLAG_SFG), .Y(n5894) );
OAI211X1TS U3234 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n2403), .B0(n3271), .C0(
n3274), .Y(n3285) );
NOR2X1TS U3235 ( .A(n5142), .B(n5107), .Y(n5108) );
AOI211X1TS U3236 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3246), .B0(n3292),
.C0(n3293), .Y(n3247) );
OAI211X1TS U3237 ( .A0(n4626), .A1(n6642), .B0(n5742), .C0(n6470), .Y(n1623)
);
OAI21XLTS U3238 ( .A0(n6215), .A1(n6424), .B0(n4693), .Y(op_result[31]) );
OAI21XLTS U3239 ( .A0(n4807), .A1(n6513), .B0(n4796), .Y(op_result[13]) );
OAI21XLTS U3240 ( .A0(n4807), .A1(n6522), .B0(n4801), .Y(op_result[11]) );
OAI21XLTS U3241 ( .A0(n6215), .A1(n6595), .B0(n4688), .Y(op_result[0]) );
OAI21XLTS U3242 ( .A0(n6215), .A1(n6598), .B0(n4690), .Y(op_result[1]) );
OAI21XLTS U3243 ( .A0(n4807), .A1(n6530), .B0(n4793), .Y(op_result[12]) );
OAI21XLTS U3244 ( .A0(n4807), .A1(n6528), .B0(n4806), .Y(op_result[10]) );
OAI21XLTS U3245 ( .A0(n6215), .A1(n6590), .B0(n4698), .Y(op_result[2]) );
OAI21XLTS U3246 ( .A0(n4807), .A1(n6601), .B0(n4787), .Y(op_result[9]) );
OAI21XLTS U3247 ( .A0(n6215), .A1(n6587), .B0(n4702), .Y(op_result[3]) );
OAI21XLTS U3248 ( .A0(n6215), .A1(n6520), .B0(n4701), .Y(op_result[8]) );
OAI21XLTS U3249 ( .A0(n6215), .A1(n2271), .B0(n4699), .Y(op_result[7]) );
OAI21XLTS U3250 ( .A0(n6215), .A1(n2269), .B0(n4696), .Y(op_result[4]) );
OAI21XLTS U3251 ( .A0(n4807), .A1(n2270), .B0(n4791), .Y(op_result[6]) );
OAI21XLTS U3252 ( .A0(n6215), .A1(n6605), .B0(n4700), .Y(op_result[5]) );
OAI21XLTS U3253 ( .A0(n4814), .A1(n6401), .B0(n4795), .Y(op_result[26]) );
OAI21XLTS U3254 ( .A0(n4814), .A1(n6400), .B0(n4797), .Y(op_result[25]) );
OAI21XLTS U3255 ( .A0(n4814), .A1(n6399), .B0(n4794), .Y(op_result[24]) );
OAI21XLTS U3256 ( .A0(n4814), .A1(n6398), .B0(n4810), .Y(op_result[23]) );
OAI21XLTS U3257 ( .A0(n4814), .A1(n6493), .B0(n4792), .Y(op_result[22]) );
OAI21XLTS U3258 ( .A0(n4814), .A1(n6503), .B0(n4790), .Y(op_result[21]) );
OAI21XLTS U3259 ( .A0(n4814), .A1(n6509), .B0(n4802), .Y(op_result[20]) );
OAI21XLTS U3260 ( .A0(n4814), .A1(n6403), .B0(n4800), .Y(op_result[27]) );
OAI21XLTS U3261 ( .A0(n4814), .A1(n6506), .B0(n4813), .Y(op_result[19]) );
OAI21XLTS U3262 ( .A0(n4814), .A1(n6499), .B0(n4799), .Y(op_result[18]) );
OAI21XLTS U3263 ( .A0(n4807), .A1(n6511), .B0(n4788), .Y(op_result[17]) );
OAI21XLTS U3264 ( .A0(n4807), .A1(n6516), .B0(n4798), .Y(op_result[16]) );
OAI21XLTS U3265 ( .A0(n4807), .A1(n6496), .B0(n4803), .Y(op_result[15]) );
OAI21XLTS U3266 ( .A0(n4807), .A1(n6526), .B0(n4789), .Y(op_result[14]) );
NAND2BX1TS U3267 ( .AN(n6436), .B(n6435), .Y(n1690) );
NAND3X1TS U3268 ( .A(n2230), .B(n6271), .C(n6682), .Y(n4667) );
OR2X2TS U3269 ( .A(n3524), .B(FPMULT_FS_Module_state_reg[1]), .Y(n2227) );
NAND3X1TS U3270 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2318), .C(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2254) );
NOR2X1TS U3271 ( .A(n5779), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5780)
);
CLKINVX2TS U3272 ( .A(n5014), .Y(n6216) );
INVX2TS U3273 ( .A(n4583), .Y(n4601) );
NAND2BX1TS U3274 ( .AN(n4929), .B(intadd_1_A_7_), .Y(n4495) );
NOR2X4TS U3275 ( .A(n2509), .B(n2508), .Y(n2591) );
NAND2X4TS U3276 ( .A(n2305), .B(n2279), .Y(n3778) );
NOR2X6TS U3277 ( .A(n2465), .B(n2464), .Y(n2532) );
OR2X2TS U3278 ( .A(n4869), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n3362) );
OAI21X1TS U3279 ( .A0(n1694), .A1(n4629), .B0(n5317), .Y(n4630) );
AND2X4TS U3280 ( .A(n4229), .B(n4624), .Y(n4230) );
OAI21X2TS U3281 ( .A0(n6629), .A1(n3205), .B0(n3204), .Y(n3207) );
NOR2X4TS U3282 ( .A(n2467), .B(n2466), .Y(n2516) );
AND2X2TS U3283 ( .A(n4414), .B(n4418), .Y(n4421) );
INVX8TS U3284 ( .A(n3125), .Y(n5495) );
NOR2X1TS U3285 ( .A(n2278), .B(n5499), .Y(n5311) );
ADDFHX2TS U3286 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]), .B(
n2461), .CI(n2460), .CO(n2464), .S(n2456) );
ADDFHX2TS U3287 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]), .B(
n3899), .CI(n3898), .CO(n3906), .S(n3905) );
NAND2BX1TS U3288 ( .AN(FPSENCOS_d_ff2_X[23]), .B(n6270), .Y(intadd_6_CI) );
ADDFHX2TS U3289 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]), .B(
n3658), .CI(n3445), .CO(n3446), .S(n3105) );
INVX4TS U3290 ( .A(n5885), .Y(n3333) );
NOR2X1TS U3291 ( .A(n5717), .B(n6691), .Y(n5719) );
NOR2X1TS U3292 ( .A(n5717), .B(n5757), .Y(n5718) );
NAND3X1TS U3293 ( .A(n3331), .B(n3404), .C(n5212), .Y(n4646) );
ADDFHX2TS U3294 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]), .B(
n2708), .CI(n2628), .CO(n2706), .S(n2712) );
ADDFHX2TS U3295 ( .A(n2490), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]),
.CI(n2489), .CO(n2491), .S(n2467) );
ADDFHX2TS U3296 ( .A(n2793), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]), .CI(
n2792), .CO(n2794), .S(n2760) );
NAND3X1TS U3297 ( .A(n5312), .B(FPMULT_FS_Module_state_reg[1]), .C(
FPMULT_FSM_add_overflow_flag), .Y(n3415) );
NAND2X2TS U3298 ( .A(n6434), .B(n6683), .Y(n3524) );
NAND2BX1TS U3299 ( .AN(n6705), .B(n4356), .Y(n4357) );
NOR2X1TS U3300 ( .A(n5681), .B(n6438), .Y(n5682) );
AND2X2TS U3301 ( .A(n3542), .B(n3541), .Y(n3545) );
NOR2X1TS U3302 ( .A(n3269), .B(FPADDSUB_intDY_EWSW[10]), .Y(n3270) );
INVX2TS U3303 ( .A(n6438), .Y(n5702) );
NAND3X1TS U3304 ( .A(n2411), .B(n3308), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n3310) );
NOR2X1TS U3305 ( .A(n3306), .B(FPADDSUB_intDY_EWSW[24]), .Y(n3307) );
XOR2X1TS U3306 ( .A(n6667), .B(n2448), .Y(DP_OP_26J1_129_1325_n18) );
NAND3X1TS U3307 ( .A(n2403), .B(n3271), .C(FPADDSUB_intDX_EWSW[8]), .Y(n3272) );
OAI21X1TS U3308 ( .A0(n6544), .A1(n2422), .B0(FPADDSUB_intDX_EWSW[22]), .Y(
n3294) );
OAI211X2TS U3309 ( .A0(n6286), .A1(n2452), .B0(n3281), .C0(n3267), .Y(n3283)
);
OR2X2TS U3310 ( .A(n3919), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]),
.Y(n3920) );
NAND3X1TS U3311 ( .A(n6189), .B(n6188), .C(n6187), .Y(n6843) );
NAND2BX1TS U3312 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n3308) );
NOR2X1TS U3313 ( .A(n6686), .B(FPMULT_FS_Module_state_reg[2]), .Y(n5813) );
OAI21X1TS U3314 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n2417), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n3286) );
NAND3X4TS U3315 ( .A(n6710), .B(n6650), .C(ready_add_subt), .Y(n6416) );
OR2X2TS U3316 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2251) );
NAND2BX1TS U3317 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n3271) );
NAND2BX1TS U3318 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n3302) );
NAND2BX1TS U3319 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n3267) );
NOR2X1TS U3320 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n4521) );
OAI211X2TS U3321 ( .A0(n6841), .A1(n6867), .B0(n6866), .C0(n6865), .Y(n6286)
);
NAND2BX1TS U3322 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n3245) );
OAI21X1TS U3323 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n2395), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n3277) );
NAND3X4TS U3324 ( .A(n6650), .B(FPSENCOS_cont_var_out[0]), .C(ready_add_subt), .Y(n6414) );
NAND2BX1TS U3325 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n3289) );
OAI211X2TS U3326 ( .A0(n6841), .A1(n6864), .B0(n6863), .C0(n6862), .Y(n6284)
);
NAND2BX1TS U3327 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n3309) );
CLKINVX2TS U3328 ( .A(result_add_subt[23]), .Y(n6398) );
CLKMX2X2TS U3329 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
NOR2X1TS U3330 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n6693), .Y(n3354) );
NOR2X1TS U3331 ( .A(n6656), .B(n6736), .Y(FPMULT_S_Oper_A_exp[8]) );
AOI211X1TS U3332 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n6647), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C0(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(
n3349) );
CLKINVX2TS U3333 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n5882) );
CLKINVX2TS U3334 ( .A(result_add_subt[29]), .Y(n6409) );
INVX1TS U3335 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6428) );
CLKINVX2TS U3336 ( .A(result_add_subt[24]), .Y(n6399) );
CLKINVX2TS U3337 ( .A(result_add_subt[26]), .Y(n6401) );
CLKINVX2TS U3338 ( .A(result_add_subt[27]), .Y(n6403) );
INVX3TS U3339 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
n2645) );
CLKINVX2TS U3340 ( .A(result_add_subt[28]), .Y(n6405) );
NAND3X1TS U3341 ( .A(n4331), .B(n4330), .C(n4329), .Y(n4332) );
NOR2X6TS U3342 ( .A(n3075), .B(n4017), .Y(n3992) );
NAND2X4TS U3343 ( .A(n3084), .B(n4011), .Y(n3984) );
AOI21X2TS U3344 ( .A0(n6019), .A1(n6018), .B0(n6017), .Y(n6020) );
NOR2X1TS U3345 ( .A(n3932), .B(n3933), .Y(n3911) );
ADDHX1TS U3346 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J1_125_4188_n202), .CO(n2775), .S(n2749) );
NAND2X4TS U3347 ( .A(n3439), .B(n3433), .Y(n3442) );
AOI21X2TS U3348 ( .A0(n2866), .A1(n2773), .B0(n2772), .Y(n2779) );
NOR2X4TS U3349 ( .A(n3073), .B(n3072), .Y(n3999) );
NOR2X6TS U3350 ( .A(n2532), .B(n2516), .Y(n2472) );
ADDFHX2TS U3351 ( .A(n2455), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]),
.CI(n2454), .CO(n2466), .S(n2465) );
XNOR2X2TS U3352 ( .A(n3197), .B(n3196), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10) );
NAND2X6TS U3353 ( .A(FPMULT_Op_MY[0]), .B(n6631), .Y(n3170) );
NAND2X6TS U3354 ( .A(n2573), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(
n2909) );
OAI21X4TS U3355 ( .A0(n2598), .A1(n2597), .B0(n2596), .Y(n2599) );
OAI21X1TS U3356 ( .A0(n4213), .A1(n4133), .B0(n4132), .Y(n4139) );
NOR2X4TS U3357 ( .A(DP_OP_501J1_127_1459_n474), .B(DP_OP_501J1_127_1459_n480), .Y(n4154) );
NAND2X4TS U3358 ( .A(n2576), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(
n2939) );
ADDFHX4TS U3359 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]), .B(
n2458), .CI(n2457), .CO(n2462), .S(n2470) );
OAI21X2TS U3360 ( .A0(n3722), .A1(n4052), .B0(n4053), .Y(n3197) );
INVX2TS U3361 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(
n3468) );
NOR2X6TS U3362 ( .A(n3635), .B(n3637), .Y(n3640) );
INVX4TS U3363 ( .A(n3504), .Y(n5887) );
OAI21X1TS U3364 ( .A0(n4213), .A1(n4140), .B0(n4150), .Y(n3810) );
OAI21X1TS U3365 ( .A0(n4213), .A1(n4145), .B0(n4144), .Y(n4149) );
NAND2X4TS U3366 ( .A(n2564), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n3411) );
OR2X6TS U3367 ( .A(n2564), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n3412) );
ADDFHX2TS U3368 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .B(
n2648), .CI(n2647), .CO(n4050), .S(n2643) );
INVX4TS U3369 ( .A(n2531), .Y(n2220) );
XNOR2X2TS U3370 ( .A(n4412), .B(n4411), .Y(n4413) );
AOI21X2TS U3371 ( .A0(n2437), .A1(n6108), .B0(n2908), .Y(n6134) );
AOI21X4TS U3372 ( .A0(n2371), .A1(n3716), .B0(n3715), .Y(n3717) );
OAI211X1TS U3373 ( .A0(n3368), .A1(n6395), .B0(n5234), .C0(n5233), .Y(n1809)
);
XOR2X4TS U3374 ( .A(n3709), .B(DP_OP_499J1_125_4188_n292), .Y(
FPMULT_inst_RecursiveKOA_Result[45]) );
AOI21X4TS U3375 ( .A0(n3001), .A1(n2999), .B0(n2681), .Y(n2682) );
NAND2X4TS U3376 ( .A(n2727), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(
n2874) );
NAND2X2TS U3377 ( .A(n5420), .B(n2232), .Y(n5172) );
NOR2X6TS U3378 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .B(
n2612), .Y(n2953) );
OAI21X4TS U3379 ( .A0(n3463), .A1(n3462), .B0(n3461), .Y(n3464) );
NAND2X4TS U3380 ( .A(n3636), .B(n3640), .Y(n3647) );
OR2X8TS U3381 ( .A(DP_OP_499J1_125_4188_n234), .B(DP_OP_499J1_125_4188_n236),
.Y(n3017) );
NAND2X4TS U3382 ( .A(DP_OP_499J1_125_4188_n234), .B(
DP_OP_499J1_125_4188_n236), .Y(n3016) );
OAI21X2TS U3383 ( .A0(n3722), .A1(n3201), .B0(n3200), .Y(n3203) );
CMPR42X2TS U3384 ( .A(DP_OP_501J1_127_1459_n256), .B(
DP_OP_501J1_127_1459_n199), .C(DP_OP_501J1_127_1459_n272), .D(
DP_OP_501J1_127_1459_n202), .ICI(DP_OP_501J1_127_1459_n264), .S(
DP_OP_501J1_127_1459_n197), .ICO(DP_OP_501J1_127_1459_n195), .CO(
DP_OP_501J1_127_1459_n196) );
OAI21X2TS U3385 ( .A0(n2598), .A1(n2591), .B0(n2594), .Y(n2582) );
OAI21X2TS U3386 ( .A0(n3092), .A1(n3432), .B0(n3435), .Y(n3093) );
OAI21X4TS U3387 ( .A0(n2609), .A1(n2608), .B0(n2607), .Y(n2610) );
NOR2X4TS U3388 ( .A(n2548), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(
n2649) );
NOR2X6TS U3389 ( .A(n2846), .B(n2841), .Y(n2692) );
INVX4TS U3390 ( .A(n4012), .Y(DP_OP_499J1_125_4188_n276) );
INVX6TS U3391 ( .A(n4022), .Y(n2568) );
NAND2X4TS U3392 ( .A(DP_OP_499J1_125_4188_n237), .B(
DP_OP_499J1_125_4188_n239), .Y(n3020) );
OR2X4TS U3393 ( .A(n3741), .B(n2208), .Y(n3744) );
XOR2X1TS U3394 ( .A(n3986), .B(n3985), .Y(
FPMULT_inst_RecursiveKOA_Result[36]) );
NOR3BX2TS U3395 ( .AN(n4536), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .Y(n4523) );
XOR2X4TS U3396 ( .A(n2882), .B(n2214), .Y(n2213) );
INVX2TS U3397 ( .A(n2881), .Y(n2214) );
INVX4TS U3398 ( .A(FPMULT_inst_RecursiveKOA_Result[0]), .Y(n2617) );
NOR2X2TS U3399 ( .A(n3769), .B(n4191), .Y(n3771) );
NOR2X4TS U3400 ( .A(n4052), .B(n3199), .Y(n4192) );
OAI22X2TS U3401 ( .A0(n4279), .A1(n4280), .B0(n2333), .B1(n4278), .Y(n4271)
);
XOR2X4TS U3402 ( .A(n3239), .B(n3238), .Y(n4309) );
AOI21X2TS U3403 ( .A0(n3235), .A1(n3234), .B0(n3233), .Y(n3239) );
ADDFHX4TS U3404 ( .A(mult_x_313_n31), .B(mult_x_313_n35), .CI(n4311), .CO(
n3815), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8) );
ADDFHX4TS U3405 ( .A(mult_x_313_n36), .B(mult_x_313_n38), .CI(n3816), .CO(
n4311), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7) );
ADDFHX2TS U3406 ( .A(n4320), .B(n4319), .CI(n4318), .CO(n3818), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4) );
CLKXOR2X4TS U3407 ( .A(n3171), .B(n3170), .Y(n3674) );
XOR2X1TS U3408 ( .A(n5352), .B(n5351), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
XOR2X2TS U3409 ( .A(n3538), .B(n3541), .Y(n3539) );
OAI21X1TS U3410 ( .A0(n3038), .A1(n3034), .B0(n3035), .Y(n3032) );
OAI21X4TS U3411 ( .A0(n3531), .A1(n2197), .B0(n3530), .Y(n1564) );
INVX2TS U3412 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(
n3898) );
XNOR2X4TS U3413 ( .A(n3968), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]),
.Y(FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
NAND2X4TS U3414 ( .A(n3017), .B(n2238), .Y(n2687) );
OR2X4TS U3415 ( .A(DP_OP_499J1_125_4188_n237), .B(DP_OP_499J1_125_4188_n239),
.Y(n2238) );
INVX6TS U3416 ( .A(n4015), .Y(DP_OP_499J1_125_4188_n292) );
ADDFHX2TS U3417 ( .A(n2758), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]), .CI(
n2635), .CO(n2759), .S(n2736) );
ADDFHX4TS U3418 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]), .B(
n2625), .CI(n2477), .CO(n2482), .S(n2480) );
INVX6TS U3419 ( .A(FPMULT_inst_RecursiveKOA_Result[2]), .Y(n2625) );
ADDFHX4TS U3420 ( .A(mult_x_313_n39), .B(n3814), .CI(n3813), .CO(n3816), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6) );
ADDFHX2TS U3421 ( .A(DP_OP_501J1_127_1459_n952), .B(
DP_OP_501J1_127_1459_n939), .CI(n3663), .CO(n3217), .S(n3210) );
INVX4TS U3422 ( .A(n3663), .Y(n2280) );
NAND2X1TS U3423 ( .A(n2796), .B(n2803), .Y(n2797) );
NAND2X4TS U3424 ( .A(DP_OP_499J1_125_4188_n222), .B(
DP_OP_499J1_125_4188_n224), .Y(n3047) );
OAI21X1TS U3425 ( .A0(n4065), .A1(n4062), .B0(n4063), .Y(n4061) );
NOR2X6TS U3426 ( .A(DP_OP_499J1_125_4188_n216), .B(DP_OP_499J1_125_4188_n218), .Y(n2846) );
OAI21X1TS U3427 ( .A0(n5362), .A1(n5359), .B0(n5360), .Y(n5358) );
ADDFX2TS U3428 ( .A(n3549), .B(n3548), .CI(n3547), .CO(n3563), .S(n3562) );
NAND2X4TS U3429 ( .A(n4686), .B(n6211), .Y(n4685) );
NOR2X8TS U3430 ( .A(n2882), .B(n2881), .Y(n3005) );
AOI21X4TS U3431 ( .A0(n3974), .A1(n3655), .B0(n3654), .Y(n3748) );
OAI21X2TS U3432 ( .A0(n5765), .A1(n3417), .B0(n5762), .Y(n3420) );
CMPR42X2TS U3433 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
DP_OP_499J1_125_4188_n252), .C(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .D(
DP_OP_499J1_125_4188_n250), .ICI(DP_OP_499J1_125_4188_n281), .S(
DP_OP_499J1_125_4188_n249), .ICO(DP_OP_499J1_125_4188_n247), .CO(
DP_OP_499J1_125_4188_n248) );
OAI21X2TS U3434 ( .A0(n5447), .A1(n5450), .B0(n5448), .Y(n5445) );
OA21X1TS U3435 ( .A0(n5452), .A1(n5455), .B0(n5453), .Y(n5450) );
XOR2X4TS U3436 ( .A(n3477), .B(n3471), .Y(n3473) );
AOI21X4TS U3437 ( .A0(n3974), .A1(n3714), .B0(n3713), .Y(n3760) );
AOI22X2TS U3438 ( .A0(n2275), .A1(n4313), .B0(n3665), .B1(mult_x_313_n74),
.Y(n3664) );
XOR2X4TS U3439 ( .A(n2554), .B(n2553), .Y(n2564) );
OR2X4TS U3440 ( .A(n2486), .B(n2554), .Y(n2487) );
AOI21X4TS U3441 ( .A0(n3982), .A1(n3633), .B0(n3632), .Y(n3634) );
INVX4TS U3442 ( .A(n3020), .Y(n3015) );
OAI21X2TS U3443 ( .A0(n4228), .A1(n3156), .B0(n3163), .Y(n3160) );
NAND2X4TS U3444 ( .A(n5495), .B(n2194), .Y(n3215) );
NOR2X6TS U3445 ( .A(n2654), .B(n2619), .Y(n2668) );
NAND2X4TS U3446 ( .A(n2654), .B(n2619), .Y(n2666) );
AOI21X4TS U3447 ( .A0(n2705), .A1(n2704), .B0(n2703), .Y(n2861) );
OAI21X4TS U3448 ( .A0(n2677), .A1(n2676), .B0(n2675), .Y(n2704) );
INVX4TS U3449 ( .A(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[1]), .Y(n2619) );
XOR2X4TS U3450 ( .A(n3004), .B(n3003), .Y(n3008) );
OAI21X4TS U3451 ( .A0(n3843), .A1(n3846), .B0(n3844), .Y(n3854) );
AOI21X4TS U3452 ( .A0(n4485), .A1(n4482), .B0(n4354), .Y(n6021) );
OAI21X4TS U3453 ( .A0(n6041), .A1(n6035), .B0(n6036), .Y(n4485) );
AOI21X2TS U3454 ( .A0(n4583), .A1(n4340), .B0(n4339), .Y(n5901) );
OAI21X2TS U3455 ( .A0(n4569), .A1(n4588), .B0(n4570), .Y(n4583) );
OAI21X1TS U3456 ( .A0(n4595), .A1(n4599), .B0(n4596), .Y(n4339) );
NAND2X1TS U3457 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4599) );
OAI2BB1X4TS U3458 ( .A0N(n3921), .A1N(n3911), .B0(n2216), .Y(n2215) );
OA21X4TS U3459 ( .A0(n3931), .A1(n3933), .B0(n3934), .Y(n2216) );
NOR2X6TS U3460 ( .A(n2867), .B(n2744), .Y(n2746) );
OAI2BB1X2TS U3461 ( .A0N(n3982), .A1N(n3755), .B0(n3754), .Y(n3756) );
XOR2X2TS U3462 ( .A(n2981), .B(n2980), .Y(n2984) );
OAI211X1TS U3463 ( .A0(n6396), .A1(n5219), .B0(n3388), .C0(n3387), .Y(n1804)
);
OAI21X2TS U3464 ( .A0(n3769), .A1(n4199), .B0(n3768), .Y(n3770) );
XOR2X4TS U3465 ( .A(n3746), .B(n2209), .Y(
FPMULT_inst_RecursiveKOA_Result[41]) );
AOI2BB1X4TS U3466 ( .A0N(n3745), .A1N(n3744), .B0(n3743), .Y(n3746) );
NAND2X4TS U3467 ( .A(DP_OP_499J1_125_4188_n228), .B(
DP_OP_499J1_125_4188_n230), .Y(n3029) );
NAND2X6TS U3468 ( .A(n3062), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[4]),
.Y(n5762) );
NOR2X8TS U3469 ( .A(n2910), .B(n2912), .Y(n2929) );
XOR2X4TS U3470 ( .A(n3758), .B(n3757), .Y(
FPMULT_inst_RecursiveKOA_Result[38]) );
XOR2X4TS U3471 ( .A(n4094), .B(n3242), .Y(n2244) );
OAI21X2TS U3472 ( .A0(n4094), .A1(n4093), .B0(n4092), .Y(n4097) );
XOR2X4TS U3473 ( .A(n3225), .B(n3224), .Y(n3673) );
OA21X1TS U3474 ( .A0(n5352), .A1(n5346), .B0(n5349), .Y(n2218) );
AOI21X4TS U3475 ( .A0(n2371), .A1(n3975), .B0(n3974), .Y(n3979) );
XOR2X4TS U3476 ( .A(n3019), .B(n3018), .Y(n3024) );
XNOR2X4TS U3477 ( .A(n4022), .B(n4021), .Y(n6128) );
NAND2X2TS U3478 ( .A(n4020), .B(n4019), .Y(n4021) );
INVX2TS U3479 ( .A(n6141), .Y(DP_OP_499J1_125_4188_n281) );
AOI21X4TS U3480 ( .A0(n2866), .A1(n2748), .B0(n2747), .Y(n2752) );
AOI21X4TS U3481 ( .A0(n3982), .A1(n3657), .B0(n3656), .Y(n3661) );
NOR2X4TS U3482 ( .A(n3903), .B(n3902), .Y(n3948) );
NOR2X2TS U3483 ( .A(n3747), .B(n3751), .Y(n3657) );
OAI21X2TS U3484 ( .A0(n4131), .A1(n4150), .B0(n4130), .Y(n4210) );
XOR2X4TS U3485 ( .A(n2520), .B(n2519), .Y(n2573) );
NAND2X4TS U3486 ( .A(n3975), .B(n3977), .Y(n3753) );
XOR2X4TS U3487 ( .A(n3498), .B(DP_OP_499J1_125_4188_n293), .Y(
FPMULT_inst_RecursiveKOA_Result[44]) );
AOI21X4TS U3488 ( .A0(n3982), .A1(n3495), .B0(n3494), .Y(n3498) );
NOR2X2TS U3489 ( .A(n3976), .B(n3453), .Y(n3087) );
NAND2X4TS U3490 ( .A(n3086), .B(n4039), .Y(n3976) );
XOR2X4TS U3491 ( .A(n2779), .B(n2778), .Y(n3086) );
OAI21X2TS U3492 ( .A0(n2893), .A1(n2896), .B0(n2894), .Y(n2919) );
OAI2BB2X2TS U3493 ( .B0(n4328), .B1(n4327), .A0N(n4326), .A1N(n4325), .Y(
mult_x_313_n62) );
XNOR2X4TS U3494 ( .A(n3835), .B(n3834), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13) );
ADDFHX4TS U3495 ( .A(n3828), .B(n3827), .CI(n3826), .CO(n3835), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12) );
OR2X4TS U3496 ( .A(n5495), .B(n2194), .Y(n3221) );
AOI21X4TS U3497 ( .A0(n2371), .A1(n3708), .B0(n3707), .Y(n3709) );
NOR2X4TS U3498 ( .A(n3706), .B(DP_OP_499J1_125_4188_n293), .Y(n3707) );
XOR2X4TS U3499 ( .A(n2536), .B(n2535), .Y(n2570) );
AOI21X4TS U3500 ( .A0(n2531), .A1(n2530), .B0(n2529), .Y(n2536) );
INVX4TS U3501 ( .A(n2554), .Y(n2531) );
NOR2X4TS U3502 ( .A(n3705), .B(DP_OP_499J1_125_4188_n293), .Y(n3708) );
XOR2X4TS U3503 ( .A(n2752), .B(n2751), .Y(n3084) );
AOI21X4TS U3504 ( .A0(n3974), .A1(n3088), .B0(n3087), .Y(n3742) );
XOR2X4TS U3505 ( .A(n2660), .B(n2667), .Y(n2661) );
NOR3BX4TS U3506 ( .AN(n4647), .B(n4860), .C(FPADDSUB_Raw_mant_NRM_SWR[9]),
.Y(n3353) );
AOI21X4TS U3507 ( .A0(n3982), .A1(n3750), .B0(n3749), .Y(n3752) );
XOR2X4TS U3508 ( .A(n2528), .B(n2527), .Y(n2569) );
AOI21X4TS U3509 ( .A0(n2531), .A1(n2552), .B0(n2524), .Y(n2528) );
NOR2X4TS U3510 ( .A(n2840), .B(n2690), .Y(n2694) );
NOR2X4TS U3511 ( .A(n2475), .B(n2474), .Y(n2540) );
NOR2X6TS U3512 ( .A(DP_OP_499J1_125_4188_n210), .B(DP_OP_499J1_125_4188_n212), .Y(n2856) );
AOI21X4TS U3513 ( .A0(n3982), .A1(n3762), .B0(n3761), .Y(n3764) );
XNOR2X4TS U3514 ( .A(n2716), .B(n2791), .Y(n2727) );
XOR2X4TS U3515 ( .A(n3634), .B(DP_OP_499J1_125_4188_n298), .Y(
FPMULT_inst_RecursiveKOA_Result[39]) );
XOR2X4TS U3516 ( .A(n3112), .B(n3111), .Y(n4030) );
NAND2X2TS U3517 ( .A(n2659), .B(n2656), .Y(n2639) );
AOI21X4TS U3518 ( .A0(n2937), .A1(n2929), .B0(n2931), .Y(n2923) );
OAI21X4TS U3519 ( .A0(n2899), .A1(n4026), .B0(n2900), .Y(n2571) );
XOR2X4TS U3520 ( .A(n3717), .B(DP_OP_499J1_125_4188_n294), .Y(
FPMULT_inst_RecursiveKOA_Result[43]) );
NOR2X2TS U3521 ( .A(n4025), .B(n2899), .Y(n2572) );
XOR2X4TS U3522 ( .A(n3661), .B(n2252), .Y(
FPMULT_inst_RecursiveKOA_Result[47]) );
AOI21X4TS U3523 ( .A0(n2873), .A1(n2725), .B0(n2872), .Y(n2877) );
INVX4TS U3524 ( .A(n2861), .Y(n2873) );
XOR2X4TS U3525 ( .A(n2719), .B(n2673), .Y(n2674) );
NOR2X2TS U3526 ( .A(n3748), .B(n3751), .Y(n3656) );
OAI21X4TS U3527 ( .A0(n2878), .A1(n2683), .B0(n2682), .Y(n2995) );
NAND2X2TS U3528 ( .A(n3001), .B(n2431), .Y(n2683) );
NOR2X4TS U3529 ( .A(n3711), .B(n3453), .Y(n3088) );
CMPR42X4TS U3530 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_499J1_125_4188_n247), .D(DP_OP_499J1_125_4188_n280), .ICI(
DP_OP_499J1_125_4188_n304), .S(DP_OP_499J1_125_4188_n246), .ICO(
DP_OP_499J1_125_4188_n244), .CO(DP_OP_499J1_125_4188_n245) );
XOR2X4TS U3531 ( .A(n2616), .B(n2603), .Y(n2997) );
NAND2X4TS U3532 ( .A(n3005), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(
n2616) );
XNOR2X4TS U3533 ( .A(n2476), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2475) );
AND2X4TS U3534 ( .A(n3081), .B(n3982), .Y(n3090) );
CMPR42X2TS U3535 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_499J1_125_4188_n269), .D(DP_OP_499J1_125_4188_n293), .ICI(
DP_OP_499J1_125_4188_n214), .S(DP_OP_499J1_125_4188_n213), .ICO(
DP_OP_499J1_125_4188_n211), .CO(DP_OP_499J1_125_4188_n212) );
NAND2X4TS U3536 ( .A(n2726), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(
n2862) );
XNOR2X4TS U3537 ( .A(n2724), .B(n2723), .Y(n2726) );
NOR2X2TS U3538 ( .A(n3742), .B(n2208), .Y(n3743) );
XOR2X4TS U3539 ( .A(n2701), .B(n2700), .Y(n3083) );
AOI21X4TS U3540 ( .A0(n2866), .A1(n2698), .B0(n2697), .Y(n2701) );
OAI21X4TS U3541 ( .A0(n2719), .A1(n2718), .B0(n2717), .Y(n2724) );
MX2X1TS U3542 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
INVX2TS U3543 ( .A(n6143), .Y(n4049) );
CLKAND2X2TS U3544 ( .A(n6702), .B(FPADDSUB_DMP_SFG[14]), .Y(n4465) );
MX2X1TS U3545 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
ADDHXLTS U3546 ( .A(n2194), .B(DP_OP_501J1_127_1459_n952), .CO(n3576), .S(
n4333) );
NOR2X1TS U3547 ( .A(n4751), .B(n5600), .Y(n4742) );
NOR2X1TS U3548 ( .A(n5471), .B(n5469), .Y(n4427) );
AOI2BB2XLTS U3549 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n2405), .A0N(n3251),
.A1N(FPADDSUB_intDY_EWSW[2]), .Y(n3260) );
OAI2BB2XLTS U3550 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n3277), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n2395), .Y(n3278) );
OAI2BB2XLTS U3551 ( .B0(n3276), .B1(n3283), .A0N(n3275), .A1N(n3274), .Y(
n3279) );
NOR2X4TS U3552 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n6666), .Y(n4548)
);
AOI21X2TS U3553 ( .A0(n5963), .A1(n5959), .B0(n4350), .Y(n5983) );
AOI21X1TS U3554 ( .A0(n5719), .A1(n5756), .B0(n5718), .Y(n5748) );
CLKAND2X2TS U3555 ( .A(n6712), .B(FPADDSUB_DMP_SFG[18]), .Y(n4473) );
CLKAND2X2TS U3556 ( .A(n6783), .B(FPADDSUB_DMP_SFG[12]), .Y(n4461) );
BUFX3TS U3557 ( .A(n6368), .Y(n6381) );
BUFX3TS U3558 ( .A(n6419), .Y(n6374) );
MX2X1TS U3559 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
NOR2X2TS U3560 ( .A(n6634), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6434) );
NOR2X2TS U3561 ( .A(n3963), .B(n3887), .Y(n3889) );
ADDFHX2TS U3562 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]), .B(
n2481), .CI(n2629), .CO(n2469), .S(n2478) );
NOR2X2TS U3563 ( .A(n3462), .B(n3456), .Y(n3465) );
XOR3X2TS U3564 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]), .B(
n2461), .C(n2460), .Y(n2463) );
XNOR2X2TS U3565 ( .A(n3962), .B(n3961), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
NOR2X2TS U3566 ( .A(n2780), .B(n2783), .Y(n2786) );
CLKAND2X2TS U3567 ( .A(n6924), .B(FPMULT_Op_MY[2]), .Y(n4820) );
NOR2X1TS U3568 ( .A(n2447), .B(n5396), .Y(n4615) );
NAND2X1TS U3569 ( .A(n6442), .B(FPMULT_Op_MY[4]), .Y(n4504) );
NOR2X1TS U3570 ( .A(n4846), .B(n5680), .Y(n4837) );
ADDHX1TS U3571 ( .A(n3243), .B(n4309), .CO(n3244), .S(n3240) );
INVX2TS U3572 ( .A(n3840), .Y(n4215) );
ADDHX1TS U3573 ( .A(n4294), .B(n3839), .CO(n3840), .S(n3181) );
XOR2X1TS U3574 ( .A(n4378), .B(n4377), .Y(n2242) );
NAND2X1TS U3575 ( .A(n4376), .B(n4375), .Y(n4377) );
CLKAND2X2TS U3576 ( .A(n6925), .B(n6448), .Y(n4727) );
OR2X1TS U3577 ( .A(n6690), .B(n6882), .Y(n4730) );
INVX4TS U3578 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(
n3648) );
CLKAND2X2TS U3579 ( .A(FPMULT_Op_MX[0]), .B(n5497), .Y(n4824) );
NOR2X1TS U3580 ( .A(n4742), .B(n4722), .Y(n4724) );
CLKAND2X2TS U3581 ( .A(n6927), .B(n6447), .Y(n4723) );
NAND2X1TS U3582 ( .A(n4370), .B(n4369), .Y(n4371) );
OAI32X1TS U3583 ( .A0(n3266), .A1(n3265), .A2(n3264), .B0(n3263), .B1(n3265),
.Y(n3284) );
OAI22X1TS U3584 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3250), .B0(n3262), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n3265) );
NAND2X1TS U3585 ( .A(n4918), .B(n4917), .Y(n4923) );
AO22XLTS U3586 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2327), .B0(n2362),
.B1(n2342), .Y(n4527) );
AO22XLTS U3587 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2327), .B0(n2362),
.B1(n2321), .Y(n4532) );
AO22XLTS U3588 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2342), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n2344), .Y(n4531) );
AO22XLTS U3589 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2321), .Y(n4554) );
AO22XLTS U3590 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2344), .Y(n4543) );
AO22XLTS U3591 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2344), .Y(n5823) );
AO22XLTS U3592 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2321), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2342), .Y(n4533) );
AO22XLTS U3593 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n2344), .Y(n4534) );
CLKAND2X2TS U3594 ( .A(n6722), .B(FPADDSUB_DMP_SFG[20]), .Y(n4477) );
CLKAND2X2TS U3595 ( .A(n6701), .B(FPADDSUB_DMP_SFG[16]), .Y(n4469) );
OAI21XLTS U3596 ( .A0(n6100), .A1(n6094), .B0(n6095), .Y(n6071) );
INVX2TS U3597 ( .A(n5967), .Y(n5969) );
AO21XLTS U3598 ( .A0(n5597), .A1(n5596), .B0(n5595), .Y(intadd_0_B_0_) );
INVX2TS U3599 ( .A(n5933), .Y(n5935) );
NOR2XLTS U3600 ( .A(n6076), .B(n4456), .Y(n4458) );
AO21XLTS U3601 ( .A0(n5335), .A1(n5334), .B0(n5676), .Y(intadd_2_CI) );
NAND2BXLTS U3602 ( .AN(n5316), .B(n6434), .Y(n4629) );
NAND3XLTS U3603 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n6200) );
AOI31XLTS U3604 ( .A0(n6198), .A1(n6197), .A2(n6196), .B0(n6203), .Y(n6201)
);
NAND4XLTS U3605 ( .A(n4516), .B(n4515), .C(n4514), .D(n4513), .Y(n4517) );
NOR3XLTS U3606 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n6185) );
NAND2X4TS U3607 ( .A(n4005), .B(n3077), .Y(n3079) );
NOR2X4TS U3608 ( .A(DP_OP_501J1_127_1459_n163), .B(DP_OP_501J1_127_1459_n171), .Y(n4062) );
NOR2X1TS U3609 ( .A(DP_OP_500J1_126_2852_n123), .B(DP_OP_500J1_126_2852_n128), .Y(n5438) );
AO22XLTS U3610 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2322), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2328), .Y(n4492) );
AO22XLTS U3611 ( .A0(FPADDSUB_Data_array_SWR[4]), .A1(n2343), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2345), .Y(n4491) );
NAND4XLTS U3612 ( .A(n4669), .B(n4668), .C(n6647), .D(n6732), .Y(n4650) );
OAI221XLTS U3613 ( .A0(n6707), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2263),
.B1(FPADDSUB_intDY_EWSW[2]), .C0(n6535), .Y(n6536) );
OAI221XLTS U3614 ( .A0(n6708), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n2429),
.B1(FPADDSUB_intDY_EWSW[5]), .C0(n6533), .Y(n6538) );
AOI2BB2X1TS U3615 ( .B0(n3319), .B1(n3318), .A0N(n3317), .A1N(n3316), .Y(
n3320) );
AOI221X1TS U3616 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n2413), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n2399), .C0(n3315), .Y(n3317) );
OAI221X1TS U3617 ( .A0(n2259), .A1(FPADDSUB_intDY_EWSW[11]), .B0(n2426),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n6551), .Y(n6566) );
OAI221X1TS U3618 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n6715), .B0(n6653), .B1(
FPADDSUB_intDY_EWSW[1]), .C0(n6554), .Y(n6564) );
OAI221X1TS U3619 ( .A0(n2265), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2430),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n6540), .Y(n6550) );
BUFX3TS U3620 ( .A(n2439), .Y(n5197) );
INVX2TS U3621 ( .A(n2325), .Y(n2326) );
AOI2BB2XLTS U3622 ( .B0(n5269), .B1(n6696), .A0N(
FPADDSUB_Shift_reg_FLAGS_7[1]), .A1N(FPADDSUB_DmP_mant_SHT1_SW[4]),
.Y(n3358) );
BUFX3TS U3623 ( .A(n6278), .Y(n6332) );
XNOR2X1TS U3624 ( .A(DP_OP_234J1_132_4955_n1), .B(n2227), .Y(n5819) );
AO21XLTS U3625 ( .A0(n4620), .A1(n5530), .B0(n5096), .Y(intadd_3_B_1_) );
NAND4XLTS U3626 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n5888) );
INVX2TS U3627 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(
n2669) );
INVX2TS U3628 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(
n2489) );
INVX2TS U3629 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(
n2490) );
NOR2X2TS U3630 ( .A(n3881), .B(n3880), .Y(n3887) );
OAI21X2TS U3631 ( .A0(n3872), .A1(n3871), .B0(n3870), .Y(n3890) );
NOR2X2TS U3632 ( .A(n3877), .B(n3876), .Y(n3963) );
AOI21X2TS U3633 ( .A0(n3923), .A1(n2451), .B0(n3908), .Y(n3931) );
NAND2X1TS U3634 ( .A(n3922), .B(n2451), .Y(n3932) );
INVX2TS U3635 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(
n2758) );
INVX2TS U3636 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(
n2793) );
INVX2TS U3637 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(
n2815) );
NAND2X1TS U3638 ( .A(n3960), .B(n3959), .Y(n3961) );
OAI21X1TS U3639 ( .A0(n3957), .A1(n3956), .B0(n3955), .Y(n3962) );
INVX2TS U3640 ( .A(n3854), .Y(n3957) );
INVX2TS U3641 ( .A(FPMULT_inst_RecursiveKOA_Result[1]), .Y(n2474) );
NOR2X1TS U3642 ( .A(n2592), .B(n2591), .Y(n2583) );
INVX2TS U3643 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(
n2638) );
INVX2TS U3644 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2477) );
OR2X2TS U3645 ( .A(n2476), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2479) );
OAI21X1TS U3646 ( .A0(n3949), .A1(n3948), .B0(n3947), .Y(n3954) );
NOR2X4TS U3647 ( .A(n2795), .B(n2794), .Y(n2805) );
NOR2X4TS U3648 ( .A(n2736), .B(n2735), .Y(n2757) );
OAI21X2TS U3649 ( .A0(n2805), .A1(n2804), .B0(n2803), .Y(n2806) );
NOR2X1TS U3650 ( .A(n6633), .B(n6641), .Y(n3692) );
NAND2X2TS U3651 ( .A(n3142), .B(n3665), .Y(n4099) );
NAND2BXLTS U3652 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n3253) );
NAND2X1TS U3653 ( .A(n2510), .B(n2594), .Y(n2511) );
INVX2TS U3654 ( .A(n2546), .Y(n2473) );
NAND2X2TS U3655 ( .A(n2475), .B(n2474), .Y(n2541) );
NAND2X2TS U3656 ( .A(n2638), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2656) );
NAND2X1TS U3657 ( .A(n2518), .B(n2517), .Y(n2519) );
INVX2TS U3658 ( .A(n2537), .Y(n2557) );
INVX2TS U3659 ( .A(n4037), .Y(DP_OP_499J1_125_4188_n274) );
INVX2TS U3660 ( .A(n4023), .Y(DP_OP_499J1_125_4188_n302) );
INVX2TS U3661 ( .A(n6144), .Y(DP_OP_499J1_125_4188_n278) );
NAND2X1TS U3662 ( .A(n2655), .B(n2666), .Y(n2660) );
INVX2TS U3663 ( .A(n4044), .Y(DP_OP_499J1_125_4188_n269) );
OAI21X1TS U3664 ( .A0(n3463), .A1(n3455), .B0(n3458), .Y(n3443) );
NOR2X1TS U3665 ( .A(n3456), .B(n3455), .Y(n3444) );
INVX2TS U3666 ( .A(n2702), .Y(n2703) );
ADDHXLTS U3667 ( .A(n5491), .B(n6455), .CO(n3582), .S(n3583) );
XOR2X1TS U3668 ( .A(n3550), .B(n3533), .Y(n2241) );
NAND2X1TS U3669 ( .A(n3532), .B(n3569), .Y(n3533) );
NAND2X1TS U3670 ( .A(n3223), .B(n3222), .Y(n3224) );
INVX2TS U3671 ( .A(n3214), .Y(n3220) );
NAND2X1TS U3672 ( .A(n6628), .B(DP_OP_501J1_127_1459_n782), .Y(n3206) );
AOI21X2TS U3673 ( .A0(n4119), .A1(n4118), .B0(n4117), .Y(n4123) );
OR2X2TS U3674 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[5]), .Y(n3223) );
NAND2X1TS U3675 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[5]), .Y(n3222) );
NOR2X4TS U3676 ( .A(n3731), .B(n3724), .Y(n4090) );
ADDHX1TS U3677 ( .A(n3704), .B(n3703), .CO(DP_OP_501J1_127_1459_n186), .S(
DP_OP_501J1_127_1459_n187) );
NAND2X1TS U3678 ( .A(n2323), .B(n6448), .Y(n4382) );
AOI21X2TS U3679 ( .A0(n4362), .A1(n4367), .B0(n4361), .Y(n4384) );
NOR2X1TS U3680 ( .A(n4374), .B(n4368), .Y(n4362) );
NOR2X2TS U3681 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[15]), .Y(n4368) );
INVX2TS U3682 ( .A(n4367), .Y(n4378) );
NAND2X1TS U3683 ( .A(n2223), .B(n6447), .Y(n4375) );
NOR2X2TS U3684 ( .A(n2223), .B(n6447), .Y(n4374) );
NAND2X1TS U3685 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[15]), .Y(n4369) );
OR2X1TS U3686 ( .A(n2631), .B(n2630), .Y(n2944) );
OAI21X2TS U3687 ( .A0(n2934), .A1(n2933), .B0(n2932), .Y(n2935) );
NOR2X1TS U3688 ( .A(n2930), .B(n2934), .Y(n2936) );
NAND2X4TS U3689 ( .A(n2575), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(
n2932) );
AOI21X2TS U3690 ( .A0(n2919), .A1(n2425), .B0(n2624), .Y(n2928) );
NAND2X1TS U3691 ( .A(n2534), .B(n2533), .Y(n2535) );
NAND2X1TS U3692 ( .A(n2665), .B(n2664), .Y(n2978) );
NAND2X1TS U3693 ( .A(n2974), .B(n2392), .Y(n2975) );
NAND2X2TS U3694 ( .A(DP_OP_498J1_124_4426_n152), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2546) );
NAND2X1TS U3695 ( .A(n2552), .B(n2551), .Y(n2553) );
OR2X1TS U3696 ( .A(n2643), .B(n2642), .Y(n2959) );
NAND2X2TS U3697 ( .A(n2611), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(
n2962) );
INVX4TS U3698 ( .A(n2911), .Y(n2937) );
NAND2X1TS U3699 ( .A(DP_OP_499J1_125_4188_n249), .B(n2679), .Y(n2883) );
OAI21X2TS U3700 ( .A0(n2980), .A1(n2977), .B0(n2978), .Y(n2885) );
NOR2XLTS U3701 ( .A(n4600), .B(n4595), .Y(n4340) );
INVX2TS U3702 ( .A(n3027), .Y(n3038) );
INVX2TS U3703 ( .A(n3014), .Y(n3021) );
NOR2X2TS U3704 ( .A(n2661), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(
n2677) );
NOR2X1TS U3705 ( .A(n2842), .B(n3057), .Y(n2845) );
INVX2TS U3706 ( .A(n3044), .Y(n3051) );
NOR2X1TS U3707 ( .A(n4753), .B(n4752), .Y(n5565) );
NAND2X2TS U3708 ( .A(DP_OP_499J1_125_4188_n210), .B(
DP_OP_499J1_125_4188_n212), .Y(n2857) );
NAND2X4TS U3709 ( .A(DP_OP_499J1_125_4188_n213), .B(
DP_OP_499J1_125_4188_n215), .Y(n2853) );
INVX2TS U3710 ( .A(n2851), .Y(n2855) );
OR2X2TS U3711 ( .A(n2674), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(
n2705) );
NOR2X4TS U3712 ( .A(n3473), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(
n3485) );
INVX2TS U3713 ( .A(n2862), .Y(n2872) );
OR2X4TS U3714 ( .A(n2727), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(
n2875) );
NOR2X6TS U3715 ( .A(n3479), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(
n3635) );
NAND2X1TS U3716 ( .A(n3110), .B(n3434), .Y(n3111) );
NOR2X1TS U3717 ( .A(n4848), .B(n4847), .Y(n5671) );
NAND2X1TS U3718 ( .A(n5671), .B(n5670), .Y(n5669) );
INVX2TS U3719 ( .A(n3583), .Y(n5388) );
OR2X1TS U3720 ( .A(n4503), .B(n3577), .Y(n3575) );
OA21XLTS U3721 ( .A0(n3577), .A1(n4504), .B0(n3578), .Y(n3574) );
INVX4TS U3722 ( .A(n2316), .Y(n2317) );
INVX2TS U3723 ( .A(n5402), .Y(n2316) );
ADDHXLTS U3724 ( .A(n4425), .B(n4424), .CO(DP_OP_502J1_128_2852_n141), .S(
n3548) );
INVX2TS U3725 ( .A(n2241), .Y(n2312) );
NAND2X1TS U3726 ( .A(n3551), .B(n3568), .Y(n3552) );
INVX2TS U3727 ( .A(n2241), .Y(n2311) );
NAND2X1TS U3728 ( .A(n3537), .B(n3536), .Y(n3538) );
OR2X2TS U3729 ( .A(n6448), .B(FPMULT_Op_MY[4]), .Y(n3234) );
NAND2X1TS U3730 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .Y(n3623) );
NAND2X1TS U3731 ( .A(n4744), .B(n4743), .Y(n5569) );
NOR2X1TS U3732 ( .A(n4889), .B(n4908), .Y(n4916) );
INVX4TS U3733 ( .A(n2234), .Y(n6440) );
NOR2X1TS U3734 ( .A(n4908), .B(n5643), .Y(n4894) );
CLKAND2X2TS U3735 ( .A(FPMULT_Op_MX[9]), .B(n6440), .Y(n4874) );
NAND2X1TS U3736 ( .A(n4839), .B(n4838), .Y(n5675) );
INVX2TS U3737 ( .A(n2240), .Y(n2286) );
OR2X2TS U3738 ( .A(FPMULT_Op_MX[6]), .B(n5528), .Y(n3726) );
OAI22X1TS U3739 ( .A0(n2386), .A1(n4266), .B0(n2332), .B1(n4267), .Y(
DP_OP_501J1_127_1459_n226) );
INVX4TS U3740 ( .A(n4098), .Y(n2336) );
ADDHX1TS U3741 ( .A(n3842), .B(n3841), .CO(DP_OP_501J1_127_1459_n198), .S(
DP_OP_501J1_127_1459_n199) );
INVX2TS U3742 ( .A(n3183), .Y(n4276) );
INVX2TS U3743 ( .A(n3181), .Y(n4216) );
CMPR42X1TS U3744 ( .A(DP_OP_500J1_126_2852_n150), .B(
DP_OP_500J1_126_2852_n157), .C(DP_OP_500J1_126_2852_n185), .D(
DP_OP_500J1_126_2852_n164), .ICI(DP_OP_500J1_126_2852_n171), .S(
DP_OP_500J1_126_2852_n120), .ICO(DP_OP_500J1_126_2852_n118), .CO(
DP_OP_500J1_126_2852_n119) );
INVX2TS U3745 ( .A(n2242), .Y(n2315) );
INVX2TS U3746 ( .A(n2242), .Y(n2314) );
AND2X2TS U3747 ( .A(n3329), .B(n4863), .Y(n3344) );
INVX2TS U3748 ( .A(n4548), .Y(n4550) );
NOR2X2TS U3749 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4860), .Y(n3352) );
NOR2BX1TS U3750 ( .AN(n3404), .B(n6718), .Y(n3334) );
NAND2X1TS U3751 ( .A(n2617), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .Y(
n2904) );
OR2X1TS U3752 ( .A(n2617), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .Y(
n2905) );
NOR2X6TS U3753 ( .A(n2570), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(
n2899) );
NOR2X6TS U3754 ( .A(n2569), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n4025) );
NAND2X4TS U3755 ( .A(n2569), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n4026) );
INVX2TS U3756 ( .A(n2898), .Y(n4029) );
NAND2X2TS U3757 ( .A(n2570), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(
n2900) );
NOR2XLTS U3758 ( .A(n4578), .B(n4440), .Y(n4442) );
OAI21X2TS U3759 ( .A0(n2649), .A1(n2652), .B0(n2650), .Y(n4035) );
OR2X2TS U3760 ( .A(n2549), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(
n4034) );
INVX2TS U3761 ( .A(n5901), .Y(n6069) );
NAND2X1TS U3762 ( .A(n2699), .B(n2743), .Y(n2700) );
OAI21X1TS U3763 ( .A0(n5939), .A1(n5933), .B0(n5934), .Y(n6059) );
OAI21X1TS U3764 ( .A0(n5973), .A1(n5967), .B0(n5968), .Y(n5963) );
CLKAND2X2TS U3765 ( .A(n6784), .B(FPADDSUB_DMP_SFG[9]), .Y(n4453) );
INVX2TS U3766 ( .A(begin_operation), .Y(n4535) );
INVX2TS U3767 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(
n3658) );
NAND2X1TS U3768 ( .A(n2829), .B(n3435), .Y(n2830) );
NAND2X1TS U3769 ( .A(n2832), .B(n2834), .Y(n2800) );
NAND2X1TS U3770 ( .A(n2777), .B(n2776), .Y(n2778) );
NAND2X1TS U3771 ( .A(n2775), .B(n2774), .Y(n2776) );
NAND2X1TS U3772 ( .A(n2750), .B(n2769), .Y(n2751) );
NAND2X1TS U3773 ( .A(n2765), .B(n2781), .Y(n2766) );
OAI21X2TS U3774 ( .A0(n2753), .A1(n2780), .B0(n2782), .Y(n2767) );
NOR2X6TS U3775 ( .A(n3084), .B(n4011), .Y(n3082) );
NAND2X1TS U3776 ( .A(n3710), .B(n3490), .Y(n3491) );
NAND2X1TS U3777 ( .A(n4018), .B(n4024), .Y(n3453) );
INVX4TS U3778 ( .A(n2235), .Y(n6441) );
AO21XLTS U3779 ( .A0(n5553), .A1(n5551), .B0(n5552), .Y(n4760) );
OA21X1TS U3780 ( .A0(n4875), .A1(n4874), .B0(n4896), .Y(n5632) );
AO21XLTS U3781 ( .A0(n5658), .A1(n5656), .B0(n5657), .Y(n4855) );
NOR2X2TS U3782 ( .A(DP_OP_501J1_127_1459_n133), .B(DP_OP_501J1_127_1459_n131), .Y(n3718) );
INVX2TS U3783 ( .A(n3172), .Y(n4219) );
NAND2X1TS U3784 ( .A(n3158), .B(n3157), .Y(n3159) );
CMPR42X1TS U3785 ( .A(DP_OP_500J1_126_2852_n137), .B(
DP_OP_500J1_126_2852_n180), .C(DP_OP_500J1_126_2852_n134), .D(
DP_OP_500J1_126_2852_n187), .ICI(DP_OP_500J1_126_2852_n131), .S(
DP_OP_500J1_126_2852_n129), .ICO(DP_OP_500J1_126_2852_n127), .CO(
DP_OP_500J1_126_2852_n128) );
OR2X1TS U3786 ( .A(n6662), .B(n6631), .Y(n4414) );
OR3X1TS U3787 ( .A(n5100), .B(n5105), .C(n5103), .Y(n5102) );
NAND2X1TS U3788 ( .A(n3326), .B(n3325), .Y(n4862) );
NOR2BX1TS U3789 ( .AN(n3247), .B(n3287), .Y(n3301) );
AOI221X1TS U3790 ( .A0(n6651), .A1(FPADDSUB_intDY_EWSW[24]), .B0(
FPADDSUB_intDY_EWSW[29]), .B1(n6706), .C0(n6558), .Y(n6559) );
NAND2X1TS U3791 ( .A(n5849), .B(n5848), .Y(n5852) );
NAND2X1TS U3792 ( .A(n5847), .B(n5846), .Y(n5851) );
CLKAND2X2TS U3793 ( .A(n2300), .B(FPADDSUB_Data_array_SWR[17]), .Y(n4524) );
INVX2TS U3794 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n6610) );
NAND4XLTS U3795 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(n6683), .D(n6644), .Y(n6214) );
OAI21X1TS U3796 ( .A0(n6039), .A1(n4480), .B0(n4479), .Y(n6019) );
CLKAND2X2TS U3797 ( .A(n2637), .B(n2652), .Y(n6142) );
OR2X1TS U3798 ( .A(n2636), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(
n2637) );
CLKXOR2X2TS U3799 ( .A(n2653), .B(n2652), .Y(n6143) );
NAND2X1TS U3800 ( .A(n4034), .B(n4033), .Y(n4036) );
INVX2TS U3801 ( .A(n6078), .Y(n6080) );
OAI21XLTS U3802 ( .A0(n4579), .A1(n4578), .B0(n4577), .Y(n4582) );
AO21XLTS U3803 ( .A0(n5595), .A1(n5570), .B0(n5571), .Y(n4721) );
INVX2TS U3804 ( .A(FPMULT_Op_MX[16]), .Y(n3125) );
MX2X1TS U3805 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
XOR2X1TS U3806 ( .A(n2319), .B(n3526), .Y(DP_OP_234J1_132_4955_n22) );
OAI21XLTS U3807 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n3525), .B0(n5483), .Y(
n3526) );
MX2X1TS U3808 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
NOR2X1TS U3809 ( .A(n5748), .B(n5720), .Y(n5746) );
NAND2X1TS U3810 ( .A(n3484), .B(n3482), .Y(n3452) );
NAND3XLTS U3811 ( .A(n5640), .B(n2207), .C(FPMULT_Op_MX[7]), .Y(n5642) );
AO21XLTS U3812 ( .A0(n5676), .A1(n5677), .B0(n5678), .Y(n4817) );
CMPR42X1TS U3813 ( .A(mult_x_313_n56), .B(mult_x_313_n76), .C(mult_x_313_n69), .D(mult_x_313_n62), .ICI(mult_x_313_n42), .S(mult_x_313_n39), .ICO(
mult_x_313_n37), .CO(mult_x_313_n38) );
BUFX3TS U3814 ( .A(n3664), .Y(n4305) );
NAND2X1TS U3815 ( .A(n3178), .B(n3619), .Y(n3179) );
INVX4TS U3816 ( .A(n2274), .Y(n2275) );
CLKAND2X2TS U3817 ( .A(n5489), .B(n2370), .Y(intadd_1_A_7_) );
AO21XLTS U3818 ( .A0(n4930), .A1(n4931), .B0(n4929), .Y(n4494) );
AOI21X1TS U3819 ( .A0(n4197), .A1(n3767), .B0(n3766), .Y(n3768) );
NAND2X1TS U3820 ( .A(DP_OP_501J1_127_1459_n130), .B(n3738), .Y(n4194) );
NOR2X1TS U3821 ( .A(n4191), .B(n3718), .Y(n3720) );
AOI21X1TS U3822 ( .A0(n4203), .A1(n3597), .B0(n3596), .Y(n3598) );
INVX2TS U3823 ( .A(n2245), .Y(n2330) );
NOR2X1TS U3824 ( .A(n6524), .B(n5828), .Y(n6510) );
OAI211X1TS U3825 ( .A0(n3342), .A1(n3341), .B0(n3340), .C0(n3339), .Y(n5884)
);
AND4X1TS U3826 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n3502), .Y(n3503) );
NOR3BX1TS U3827 ( .AN(n6232), .B(n6269), .C(FPSENCOS_cont_iter_out[2]), .Y(
n4937) );
INVX2TS U3828 ( .A(n2249), .Y(n6230) );
MX2X1TS U3829 ( .A(Data_2[22]), .B(n5498), .S0(n6471), .Y(n1648) );
MX2X1TS U3830 ( .A(Data_1[11]), .B(n5489), .S0(n5492), .Y(n1669) );
MX2X1TS U3831 ( .A(Data_2[9]), .B(n2228), .S0(n5496), .Y(n1635) );
MX2X1TS U3832 ( .A(Data_2[18]), .B(n6662), .S0(n6471), .Y(n1644) );
MX2X1TS U3833 ( .A(Data_2[8]), .B(n2207), .S0(n5496), .Y(n1634) );
MX2X1TS U3834 ( .A(Data_2[10]), .B(n2206), .S0(n5496), .Y(n1636) );
MX2X1TS U3835 ( .A(Data_2[20]), .B(n5500), .S0(n5501), .Y(n1646) );
MX2X1TS U3836 ( .A(Data_1[21]), .B(n6640), .S0(n5494), .Y(n1679) );
MX2X1TS U3837 ( .A(Data_2[7]), .B(n6641), .S0(n5496), .Y(n1633) );
MX2X1TS U3838 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n5494), .Y(n1678)
);
MX2X1TS U3839 ( .A(Data_1[8]), .B(FPMULT_Op_MX[8]), .S0(n5501), .Y(n1666) );
MX2X1TS U3840 ( .A(Data_2[11]), .B(n2370), .S0(n5496), .Y(n1637) );
MX2X1TS U3841 ( .A(Data_2[21]), .B(n5499), .S0(n5492), .Y(n1647) );
MX2X1TS U3842 ( .A(Data_1[17]), .B(n2346), .S0(n5494), .Y(n1675) );
MX2X1TS U3843 ( .A(Data_1[5]), .B(n5491), .S0(n5492), .Y(n1663) );
MX2X1TS U3844 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DMP_SHT2_EWSW[0]), .S0(
n5883), .Y(n1293) );
MX2X1TS U3845 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .S0(
n5883), .Y(n1234) );
MX2X1TS U3846 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .S0(
n5883), .Y(n1286) );
MX2X1TS U3847 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .S0(
n5821), .Y(n1238) );
MX2X1TS U3848 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .S0(
n5883), .Y(n1272) );
MX2X1TS U3849 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .S0(
n5821), .Y(n1300) );
MX2X1TS U3850 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DMP_SHT2_EWSW[2]), .S0(
n5883), .Y(n1307) );
MX2X1TS U3851 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .S0(
n5883), .Y(n1323) );
MX2X1TS U3852 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n6471), .Y(n1655)
);
MX2X1TS U3853 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n6471), .Y(n1653)
);
MX2X1TS U3854 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n5816), .Y(n1594) );
MX2X1TS U3855 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n6471), .Y(n1652)
);
MX2X1TS U3856 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n5818), .Y(n1683)
);
MX2X1TS U3857 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n5817), .Y(n1687)
);
MX2X1TS U3858 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n5817), .Y(n1685)
);
MX2X1TS U3859 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n5818), .Y(n1684)
);
XOR2XLTS U3860 ( .A(n5917), .B(n5916), .Y(n5921) );
INVX2TS U3861 ( .A(FPSENCOS_d_ff2_Y[31]), .Y(n7050) );
MX2X1TS U3862 ( .A(n6127), .B(FPMULT_P_Sgf[16]), .S0(n6181), .Y(n1545) );
MX2X1TS U3863 ( .A(n6118), .B(FPMULT_P_Sgf[15]), .S0(n6181), .Y(n1544) );
MX2X1TS U3864 ( .A(n6144), .B(FPMULT_P_Sgf[11]), .S0(n2196), .Y(n1540) );
MX2X1TS U3865 ( .A(n6140), .B(FPMULT_P_Sgf[12]), .S0(n6181), .Y(n1541) );
CLKAND2X2TS U3866 ( .A(n6139), .B(n6138), .Y(n6140) );
MX2X1TS U3867 ( .A(FPMULT_P_Sgf[5]), .B(FPMULT_inst_RecursiveKOA_Result[5]),
.S0(n6176), .Y(n1534) );
MX2X1TS U3868 ( .A(FPMULT_P_Sgf[4]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[4]), .S0(
n6176), .Y(n1533) );
MX2X1TS U3869 ( .A(n6142), .B(FPMULT_P_Sgf[6]), .S0(n2197), .Y(n1535) );
MX2X1TS U3870 ( .A(n6129), .B(FPMULT_P_Sgf[10]), .S0(n6181), .Y(n1539) );
MX2X1TS U3871 ( .A(n6143), .B(FPMULT_P_Sgf[7]), .S0(n2197), .Y(n1536) );
MX2X1TS U3872 ( .A(n6135), .B(FPMULT_P_Sgf[14]), .S0(n6181), .Y(n1543) );
MX2X1TS U3873 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_inst_RecursiveKOA_Result[2]),
.S0(n6176), .Y(n1531) );
MX2X1TS U3874 ( .A(FPMULT_P_Sgf[3]), .B(FPMULT_inst_RecursiveKOA_Result[3]),
.S0(n6175), .Y(n1532) );
MX2X1TS U3875 ( .A(n6114), .B(FPMULT_P_Sgf[17]), .S0(n2361), .Y(n1546) );
NAND2BXLTS U3876 ( .AN(n6213), .B(n6212), .Y(n2191) );
MX2X1TS U3877 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n5501), .Y(n1650)
);
MX2X1TS U3878 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n5501), .Y(n1651)
);
MX2X1TS U3879 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n6471), .Y(n1682)
);
XOR2XLTS U3880 ( .A(n4579), .B(n4572), .Y(n4576) );
XOR2XLTS U3881 ( .A(n5981), .B(n5980), .Y(n5986) );
MX2X1TS U3882 ( .A(FPMULT_FSM_add_overflow_flag), .B(n5810), .S0(n5777), .Y(
n1596) );
MX2X1TS U3883 ( .A(n6110), .B(FPMULT_P_Sgf[13]), .S0(n2361), .Y(n1542) );
MX2X1TS U3884 ( .A(FPMULT_P_Sgf[0]), .B(FPMULT_inst_RecursiveKOA_Result[0]),
.S0(n6176), .Y(n1529) );
MX2X1TS U3885 ( .A(n6128), .B(FPMULT_P_Sgf[9]), .S0(n6181), .Y(n1538) );
MX2X1TS U3886 ( .A(n6141), .B(FPMULT_P_Sgf[8]), .S0(n2197), .Y(n1537) );
MX2X1TS U3887 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_inst_RecursiveKOA_Result[1]),
.S0(n6175), .Y(n1530) );
MX2X1TS U3888 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n5820), .Y(n1453) );
MX2X1TS U3889 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n5820), .Y(n1448) );
MX2X1TS U3890 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n5885), .Y(n1433) );
MX2X1TS U3891 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n5820), .Y(n1423) );
AO22XLTS U3892 ( .A0(n6599), .A1(n6481), .B0(n6486), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1475) );
OAI21XLTS U3893 ( .A0(n6727), .A1(n6655), .B0(intadd_4_CI), .Y(n6481) );
MX2X1TS U3894 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DMP_SHT2_EWSW[9]), .S0(
n5821), .Y(n1279) );
MX2X1TS U3895 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .S0(
n5821), .Y(n1250) );
MX2X1TS U3896 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n6578), .Y(n1418) );
MX2X1TS U3897 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n5818), .Y(n1654)
);
MX2X1TS U3898 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n5492), .Y(n1649)
);
MX2X1TS U3899 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n5816), .Y(n1593) );
MX2X1TS U3900 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n5816), .Y(n1592) );
MX2X1TS U3901 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n5816), .Y(n1591) );
MX2X1TS U3902 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n5818), .Y(n1681)
);
MX2X1TS U3903 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n5818), .Y(n1656)
);
MX2X1TS U3904 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_OP_FLAG_SHT2), .S0(
n5883), .Y(n1352) );
XOR2XLTS U3905 ( .A(n5991), .B(n5990), .Y(n5996) );
XOR2XLTS U3906 ( .A(n6093), .B(n5900), .Y(n5908) );
MX2X1TS U3907 ( .A(n5775), .B(FPMULT_P_Sgf[27]), .S0(n2361), .Y(n1556) );
MX2X1TS U3908 ( .A(n5800), .B(FPMULT_P_Sgf[24]), .S0(n7026), .Y(n1553) );
MX2X1TS U3909 ( .A(FPADDSUB_Raw_mant_NRM_SWR[0]), .B(
FPADDSUB_DmP_mant_SFG_SWR[0]), .S0(n6577), .Y(n1349) );
MX2X1TS U3910 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n5817), .Y(n1688)
);
MX2X1TS U3911 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n5817), .Y(n1686)
);
MX2X1TS U3912 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n5885), .Y(n1438) );
MX2X1TS U3913 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n5885), .Y(n1428) );
OAI21X1TS U3914 ( .A0(n3422), .A1(n7026), .B0(n3421), .Y(n1558) );
XOR2XLTS U3915 ( .A(n6077), .B(n6066), .Y(n6074) );
CLKAND2X2TS U3916 ( .A(n6206), .B(n6220), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
XOR2XLTS U3917 ( .A(n5971), .B(n5970), .Y(n5976) );
XOR2XLTS U3918 ( .A(n4591), .B(n4590), .Y(n4593) );
CLKAND2X2TS U3919 ( .A(n4589), .B(n4588), .Y(n4591) );
AO21XLTS U3920 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n6218), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n2148) );
MX2X1TS U3921 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DMP_SHT2_EWSW[22]),
.S0(n6485), .Y(n1206) );
MX2X1TS U3922 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DMP_SHT2_EWSW[18]),
.S0(n5878), .Y(n1214) );
MX2X1TS U3923 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DMP_SHT2_EWSW[14]),
.S0(n5883), .Y(n1258) );
MX2X1TS U3924 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DMP_SHT2_EWSW[16]),
.S0(n5862), .Y(n1246) );
MX2X1TS U3925 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DMP_SHT2_EWSW[20]),
.S0(n5821), .Y(n1226) );
MX2X1TS U3926 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DMP_SHT2_EWSW[13]),
.S0(n6485), .Y(n1242) );
MX2X1TS U3927 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DMP_SHT2_EWSW[17]),
.S0(n6485), .Y(n1230) );
MX2X1TS U3928 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DMP_SHT2_EWSW[19]),
.S0(n6576), .Y(n1222) );
MX2X1TS U3929 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DMP_SHT2_EWSW[21]),
.S0(n5883), .Y(n1218) );
MX2X1TS U3930 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DMP_SHT2_EWSW[15]),
.S0(n6485), .Y(n1210) );
MX2X1TS U3931 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n6485), .Y(n1266) );
MX2X1TS U3932 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n6485), .Y(n1262) );
MX2X1TS U3933 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n6485), .Y(n1254) );
OAI2BB1X1TS U3934 ( .A0N(n3613), .A1N(n3612), .B0(n3611), .Y(n3615) );
MX2X1TS U3935 ( .A(Data_1[18]), .B(n5528), .S0(n5494), .Y(n1676) );
MX2X1TS U3936 ( .A(Data_1[16]), .B(n5495), .S0(n5494), .Y(n1674) );
MX2X1TS U3937 ( .A(n6904), .B(n6903), .S0(n2200), .Y(n1565) );
NAND2X1TS U3938 ( .A(n3597), .B(n4199), .Y(n3202) );
XOR2XLTS U3939 ( .A(n5937), .B(n5936), .Y(n5942) );
CLKAND2X2TS U3940 ( .A(n5539), .B(n5538), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
OR2X1TS U3941 ( .A(n5019), .B(n5322), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
NAND4XLTS U3942 ( .A(n7034), .B(n7033), .C(n7032), .D(n6202), .Y(n6204) );
XOR2XLTS U3943 ( .A(n6710), .B(n6225), .Y(n2137) );
AOI2BB2XLTS U3944 ( .B0(n6728), .B1(n6269), .A0N(FPSENCOS_d_ff_Xn[28]),
.A1N(n6300), .Y(n1954) );
OAI31X1TS U3945 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n4522), .A2(n5814),
.B0(n6739), .Y(n1528) );
MX2X1TS U3946 ( .A(FPMULT_Add_result[19]), .B(n5729), .S0(n5739), .Y(n1601)
);
MX2X1TS U3947 ( .A(FPMULT_Add_result[18]), .B(n5731), .S0(n5739), .Y(n1602)
);
MX2X1TS U3948 ( .A(FPMULT_Add_result[17]), .B(n5733), .S0(n5739), .Y(n1603)
);
MX2X1TS U3949 ( .A(FPMULT_Add_result[16]), .B(n5735), .S0(n5739), .Y(n1604)
);
MX2X1TS U3950 ( .A(FPMULT_Add_result[15]), .B(n5737), .S0(n5739), .Y(n1605)
);
MX2X1TS U3951 ( .A(FPMULT_Add_result[14]), .B(n5740), .S0(n5809), .Y(n1606)
);
MX2X1TS U3952 ( .A(FPMULT_Add_result[13]), .B(n5743), .S0(n5777), .Y(n1607)
);
MX2X1TS U3953 ( .A(FPMULT_Add_result[12]), .B(n5745), .S0(n5809), .Y(n1608)
);
MX2X1TS U3954 ( .A(FPMULT_Add_result[11]), .B(n5747), .S0(n5777), .Y(n1609)
);
MX2X1TS U3955 ( .A(FPMULT_Add_result[10]), .B(n5751), .S0(n5809), .Y(n1610)
);
MX2X1TS U3956 ( .A(FPMULT_Add_result[9]), .B(n5753), .S0(n5777), .Y(n1611)
);
MX2X1TS U3957 ( .A(FPMULT_Add_result[8]), .B(n5755), .S0(n5777), .Y(n1612)
);
MX2X1TS U3958 ( .A(FPMULT_Add_result[7]), .B(n5759), .S0(n5809), .Y(n1613)
);
MX2X1TS U3959 ( .A(FPMULT_Add_result[6]), .B(n5761), .S0(n5777), .Y(n1614)
);
MX2X1TS U3960 ( .A(FPMULT_Add_result[5]), .B(n5768), .S0(n5777), .Y(n1615)
);
MX2X1TS U3961 ( .A(FPMULT_Add_result[4]), .B(n5778), .S0(n5809), .Y(n1616)
);
MX2X1TS U3962 ( .A(FPMULT_Add_result[3]), .B(n5781), .S0(n5777), .Y(n1617)
);
INVX2TS U3963 ( .A(n5793), .Y(n5779) );
MX2X1TS U3964 ( .A(FPMULT_Add_result[2]), .B(n5794), .S0(n5777), .Y(n1618)
);
MX2X1TS U3965 ( .A(FPMULT_Add_result[1]), .B(n5801), .S0(n5809), .Y(n1619)
);
BUFX3TS U3966 ( .A(n4965), .Y(n7021) );
MX2X1TS U3967 ( .A(n6849), .B(n6848), .S0(n2200), .Y(n1562) );
XOR2X1TS U3968 ( .A(n4010), .B(n4009), .Y(
FPMULT_inst_RecursiveKOA_Result[33]) );
NAND2X1TS U3969 ( .A(n4008), .B(n4007), .Y(n4009) );
AOI21X1TS U3970 ( .A0(n4412), .A1(n4005), .B0(n4004), .Y(n4010) );
MX2X1TS U3971 ( .A(n6851), .B(n6850), .S0(n2200), .Y(n1561) );
XOR2X1TS U3972 ( .A(n4003), .B(n4002), .Y(
FPMULT_inst_RecursiveKOA_Result[32]) );
NAND2X1TS U3973 ( .A(n4001), .B(n4000), .Y(n4002) );
AOI21X1TS U3974 ( .A0(n4412), .A1(n4410), .B0(n3998), .Y(n4003) );
MX2X1TS U3975 ( .A(Data_1[4]), .B(n2194), .S0(n5501), .Y(n1662) );
AOI222X1TS U3976 ( .A0(n4401), .A1(n6773), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[22]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[22]), .Y(n7073) );
MX2X1TS U3977 ( .A(Data_2[5]), .B(FPMULT_Op_MY[5]), .S0(n5496), .Y(n1631) );
MX2X1TS U3978 ( .A(Data_2[4]), .B(n5497), .S0(n5501), .Y(n1630) );
INVX2TS U3979 ( .A(FPSENCOS_d_ff2_Y[10]), .Y(n7046) );
INVX2TS U3980 ( .A(FPSENCOS_d_ff2_Y[28]), .Y(n7049) );
AOI222X1TS U3981 ( .A0(n5262), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n6661),
.B1(n6639), .C0(FPADDSUB_intDX_EWSW[26]), .C1(n5263), .Y(n7085) );
AOI222X1TS U3982 ( .A0(n6432), .A1(n6766), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[23]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[23]), .Y(n7074) );
AOI222X1TS U3983 ( .A0(n4401), .A1(n6767), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[24]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[24]), .Y(n7075) );
AOI222X1TS U3984 ( .A0(n6432), .A1(n6769), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[26]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[26]), .Y(n7077) );
AOI222X1TS U3985 ( .A0(n4359), .A1(n6772), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[29]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[29]), .Y(n7080) );
MX2X1TS U3986 ( .A(Data_2[14]), .B(n6447), .S0(n5817), .Y(n1640) );
MX2X1TS U3987 ( .A(Data_2[17]), .B(FPMULT_Op_MY[17]), .S0(n5817), .Y(n1643)
);
MX2X1TS U3988 ( .A(Data_2[16]), .B(n6448), .S0(n5817), .Y(n1642) );
MX2X1TS U3989 ( .A(n6891), .B(n6890), .S0(n2199), .Y(n1574) );
MX2X1TS U3990 ( .A(n6897), .B(n6896), .S0(n2199), .Y(n1568) );
MX2X1TS U3991 ( .A(n6902), .B(n6901), .S0(n2200), .Y(n1566) );
NAND2X1TS U3992 ( .A(n3977), .B(n3976), .Y(n3978) );
NAND2X1TS U3993 ( .A(n3984), .B(n3983), .Y(n3985) );
MX2X1TS U3994 ( .A(n6906), .B(n6905), .S0(n2199), .Y(n1570) );
MX2X1TS U3995 ( .A(n6908), .B(n6907), .S0(n2199), .Y(n1571) );
INVX2TS U3996 ( .A(n3760), .Y(n3761) );
MX2X1TS U3997 ( .A(n6910), .B(n6909), .S0(n2200), .Y(n1572) );
MX2X1TS U3998 ( .A(n6913), .B(n6912), .S0(n2200), .Y(n1563) );
XOR2X1TS U3999 ( .A(n3996), .B(n3995), .Y(
FPMULT_inst_RecursiveKOA_Result[34]) );
NAND2X1TS U4000 ( .A(n3994), .B(n3993), .Y(n3995) );
AOI21X1TS U4001 ( .A0(n3991), .A1(n4412), .B0(n3990), .Y(n3996) );
MX2X1TS U4002 ( .A(n6915), .B(n6914), .S0(n2199), .Y(n1573) );
INVX2TS U4003 ( .A(n3706), .Y(n3494) );
MX2X1TS U4004 ( .A(n6917), .B(n6916), .S0(n2199), .Y(n1569) );
INVX2TS U4005 ( .A(n3742), .Y(n3089) );
MX2X1TS U4006 ( .A(n6919), .B(n6918), .S0(n2200), .Y(n1567) );
CLKBUFX3TS U4007 ( .A(n2302), .Y(n2384) );
OR2X1TS U4008 ( .A(n5641), .B(n5635), .Y(intadd_1_B_1_) );
CLKAND2X2TS U4009 ( .A(n5326), .B(n5325), .Y(n6725) );
ADDFHX2TS U4010 ( .A(mult_x_313_n22), .B(n3825), .CI(n3824), .CO(n3826), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11) );
ADDFHX2TS U4011 ( .A(mult_x_313_n26), .B(mult_x_313_n30), .CI(n3815), .CO(
n3817), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9) );
ADDFHX2TS U4012 ( .A(n3820), .B(n3819), .CI(n3818), .CO(n3813), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5) );
OAI21XLTS U4013 ( .A0(n6921), .A1(n6690), .B0(n5598), .Y(n5333) );
AOI2BB1XLTS U4014 ( .A0N(n6860), .A1N(n6697), .B0(n5713), .Y(n5714) );
XNOR2X1TS U4015 ( .A(n3810), .B(n3809), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8) );
CLKAND2X2TS U4016 ( .A(n4183), .B(n4182), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0) );
OR2X1TS U4017 ( .A(n4181), .B(n4180), .Y(n4183) );
NAND2X1TS U4018 ( .A(n4192), .B(n4202), .Y(n4205) );
CLKAND2X2TS U4019 ( .A(n4179), .B(n4178), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0) );
OR2X1TS U4020 ( .A(n4177), .B(n4176), .Y(n4179) );
OAI21X1TS U4021 ( .A0(n5426), .A1(n5406), .B0(n5405), .Y(n5410) );
CLKAND2X2TS U4022 ( .A(n5330), .B(n5329), .Y(n6726) );
XOR2XLTS U4023 ( .A(DP_OP_501J1_127_1459_n939), .B(n2323), .Y(n5510) );
AO22XLTS U4024 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1207) );
AO22XLTS U4025 ( .A0(n6620), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n6619),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1208) );
AO22XLTS U4026 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n6618),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1211) );
AO22XLTS U4027 ( .A0(n6617), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n6616),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1212) );
AO22XLTS U4028 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1215) );
AO22XLTS U4029 ( .A0(n6617), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n6616),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1216) );
AO22XLTS U4030 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1219) );
AO22XLTS U4031 ( .A0(n6617), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n6616),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1220) );
AO22XLTS U4032 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1223) );
AO22XLTS U4033 ( .A0(n6617), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n6616),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1224) );
AO22XLTS U4034 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1227) );
AO22XLTS U4035 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n6612),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1228) );
AO22XLTS U4036 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1231) );
AO22XLTS U4037 ( .A0(n6617), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n6612),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1232) );
AO22XLTS U4038 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n6839), .Y(n6831) );
AO22XLTS U4039 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n6612), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1236) );
AO22XLTS U4040 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n6839), .Y(n6832) );
AO22XLTS U4041 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n6612), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1240) );
AO22XLTS U4042 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1243) );
AO22XLTS U4043 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n6612),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1244) );
AO22XLTS U4044 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1247) );
AO22XLTS U4045 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n6612),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1248) );
AO22XLTS U4046 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1251) );
AO22XLTS U4047 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n6612), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1252) );
AO22XLTS U4048 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1255) );
AO22XLTS U4049 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n6612),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1256) );
AO22XLTS U4050 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n6615),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1259) );
AO22XLTS U4051 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n6612),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1260) );
AO22XLTS U4052 ( .A0(n6614), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1263) );
AO22XLTS U4053 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n6612),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1264) );
AO22XLTS U4054 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1267) );
AO22XLTS U4055 ( .A0(n6613), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n6592),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1268) );
AO22XLTS U4056 ( .A0(n6607), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n6610),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1270) );
AO22XLTS U4057 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n6839), .Y(n6833) );
AO22XLTS U4058 ( .A0(n6607), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n6610), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1274) );
AO22XLTS U4059 ( .A0(n6607), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n6796), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1276) );
AO22XLTS U4060 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1280) );
AO22XLTS U4061 ( .A0(n6607), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n6610), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1281) );
AO22XLTS U4062 ( .A0(n6607), .A1(FPADDSUB_DmP_EXP_EWSW[9]), .B0(n6610), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1283) );
AO22XLTS U4063 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n6618), .Y(n6834) );
AO22XLTS U4064 ( .A0(n6607), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n6610), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1288) );
AO22XLTS U4065 ( .A0(n6592), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n6599),
.B1(FPADDSUB_DmP_EXP_EWSW[1]), .Y(n1290) );
AO22XLTS U4066 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n6618), .Y(n6835) );
AO22XLTS U4067 ( .A0(n6607), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n6610), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1295) );
AO22XLTS U4068 ( .A0(n6607), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n6610), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1297) );
AO22XLTS U4069 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n6839), .Y(n6836) );
AO22XLTS U4070 ( .A0(n6607), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n6592), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1302) );
AO22XLTS U4071 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n6618), .Y(n6837) );
AO22XLTS U4072 ( .A0(n6607), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n6619), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1309) );
AO22XLTS U4073 ( .A0(n6620), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n6619), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1311) );
AO22XLTS U4074 ( .A0(n7086), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n6618), .Y(n6838) );
AO22XLTS U4075 ( .A0(n6620), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n6619), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1325) );
AO22XLTS U4076 ( .A0(n6620), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n6619), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1327) );
OAI2BB2XLTS U4077 ( .B0(n6577), .B1(n2441), .A0N(n4565), .A1N(n4355), .Y(
n1351) );
AO22XLTS U4078 ( .A0(n6609), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n6608), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1353) );
AO22XLTS U4079 ( .A0(n6620), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n6619), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1354) );
AO22XLTS U4080 ( .A0(n6578), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n3333), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1357) );
AO22XLTS U4081 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_SIGN_FLAG_SFG), .B0(n6484), .B1(FPADDSUB_SIGN_FLAG_NRM), .Y(
n1358) );
AO22XLTS U4082 ( .A0(n6609), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n6608), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1360) );
AO22XLTS U4083 ( .A0(n6620), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n6619), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1361) );
AOI31XLTS U4084 ( .A0(n6570), .A1(n6569), .A2(n6568), .B0(n6567), .Y(n6573)
);
AO22XLTS U4085 ( .A0(n6620), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n6619),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1364) );
AO22XLTS U4086 ( .A0(n6620), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n6619),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1367) );
AO22XLTS U4087 ( .A0(n6620), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n6619),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1370) );
AO22XLTS U4088 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n6517),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1376) );
AO22XLTS U4089 ( .A0(n6620), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n6517),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1379) );
AO22XLTS U4090 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n6517), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1382) );
AO22XLTS U4091 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n6517), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1385) );
AO22XLTS U4092 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n6517),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1391) );
AO22XLTS U4093 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n6517),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1394) );
AO22XLTS U4094 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n6517),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1397) );
AO22XLTS U4095 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n6517),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1403) );
AO22XLTS U4096 ( .A0(n6518), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n6517),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1406) );
AO22XLTS U4097 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1421) );
AO22XLTS U4098 ( .A0(n6518), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n6517),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1422) );
AO22XLTS U4099 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1426) );
AO22XLTS U4100 ( .A0(n6599), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n6486),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1427) );
AO22XLTS U4101 ( .A0(n6577), .A1(FPADDSUB_DMP_SFG[28]), .B0(n6484), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1429) );
AO22XLTS U4102 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1431) );
AO22XLTS U4103 ( .A0(n6518), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n6486),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1432) );
AO22XLTS U4104 ( .A0(n6577), .A1(FPADDSUB_DMP_SFG[27]), .B0(n6484), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1434) );
AO22XLTS U4105 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n6608),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1436) );
AO22XLTS U4106 ( .A0(n6599), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n6486),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1437) );
AO22XLTS U4107 ( .A0(n6577), .A1(FPADDSUB_DMP_SFG[26]), .B0(n6484), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1439) );
AO22XLTS U4108 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n6618),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1441) );
AO22XLTS U4109 ( .A0(n6599), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n6486),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1442) );
AO22XLTS U4110 ( .A0(n6577), .A1(FPADDSUB_DMP_SFG[25]), .B0(n6484), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1444) );
AO22XLTS U4111 ( .A0(n6609), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n6618),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1446) );
AO22XLTS U4112 ( .A0(n6599), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n6486),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1447) );
AO22XLTS U4113 ( .A0(n6577), .A1(FPADDSUB_DMP_SFG[24]), .B0(n2453), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1449) );
AO22XLTS U4114 ( .A0(n7086), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n6839),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1451) );
AO22XLTS U4115 ( .A0(n6599), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n6486),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1452) );
AO22XLTS U4116 ( .A0(n2326), .A1(FPADDSUB_DMP_SFG[23]), .B0(n2453), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1454) );
AO22XLTS U4117 ( .A0(n7086), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n6839),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1456) );
AO22XLTS U4118 ( .A0(n6599), .A1(intadd_4_SUM_0_), .B0(n6486), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1476) );
AO22XLTS U4119 ( .A0(n6599), .A1(intadd_4_SUM_1_), .B0(n6486), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1477) );
BUFX3TS U4120 ( .A(n6920), .Y(n7019) );
MX2X1TS U4121 ( .A(Data_2[0]), .B(FPMULT_Op_MY[0]), .S0(n5501), .Y(n1626) );
MX2X1TS U4122 ( .A(Data_2[1]), .B(FPMULT_Op_MY[1]), .S0(n5492), .Y(n1627) );
MX2X1TS U4123 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n5501), .Y(n1628) );
MX2X1TS U4124 ( .A(Data_2[3]), .B(FPMULT_Op_MY[3]), .S0(n6471), .Y(n1629) );
MX2X1TS U4125 ( .A(Data_2[6]), .B(DP_OP_501J1_127_1459_n910), .S0(n5496),
.Y(n1632) );
MX2X1TS U4126 ( .A(Data_2[13]), .B(n2224), .S0(n5817), .Y(n1639) );
MX2X1TS U4127 ( .A(Data_2[15]), .B(FPMULT_Op_MY[15]), .S0(n5817), .Y(n1641)
);
MX2X1TS U4128 ( .A(Data_2[19]), .B(n6633), .S0(n5492), .Y(n1645) );
MX2X1TS U4129 ( .A(Data_1[6]), .B(FPMULT_Op_MX[6]), .S0(n5492), .Y(n1664) );
MX2X1TS U4130 ( .A(Data_1[7]), .B(FPMULT_Op_MX[7]), .S0(n6471), .Y(n1665) );
MX2X1TS U4131 ( .A(Data_1[9]), .B(FPMULT_Op_MX[9]), .S0(n5492), .Y(n1667) );
MX2X1TS U4132 ( .A(Data_1[10]), .B(n5490), .S0(n5501), .Y(n1668) );
MX2X1TS U4133 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n5494), .Y(n1677)
);
MX2X1TS U4134 ( .A(Data_1[22]), .B(n5493), .S0(n5494), .Y(n1680) );
INVX2TS U4135 ( .A(n6670), .Y(n5493) );
NAND3BX1TS U4136 ( .AN(n4408), .B(n4407), .C(n4406), .Y(n1787) );
AO22XLTS U4137 ( .A0(n6278), .A1(FPSENCOS_d_ff2_X[31]), .B0(n6283), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1942) );
AOI2BB2XLTS U4138 ( .B0(n6278), .B1(n6277), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n6413), .Y(n1947) );
OAI21XLTS U4139 ( .A0(n6270), .A1(n7048), .B0(intadd_5_CI), .Y(n4609) );
AO21XLTS U4140 ( .A0(FPSENCOS_d_ff3_LUT_out[8]), .A1(n6338), .B0(n6233), .Y(
n2125) );
OAI21X4TS U4141 ( .A0(n2514), .A1(n2532), .B0(n2533), .Y(n2515) );
AOI21X4TS U4142 ( .A0(n2875), .A1(n2872), .B0(n2728), .Y(n2729) );
AOI2BB1X4TS U4143 ( .A0N(n2220), .A1N(n2221), .B0(n2515), .Y(n2520) );
XNOR2X4TS U4144 ( .A(n4097), .B(n4096), .Y(n4098) );
NAND2X4TS U4145 ( .A(n3063), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[5]),
.Y(n3418) );
XNOR2X4TS U4146 ( .A(n2916), .B(n2915), .Y(n2222) );
ADDFX2TS U4147 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]), .B(
n2494), .CI(n2493), .CO(n2496), .S(n2492) );
AOI21X4TS U4148 ( .A0(n2992), .A1(n6161), .B0(n2991), .Y(n5802) );
INVX4TS U4149 ( .A(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[0]), .Y(n2658) );
INVX4TS U4150 ( .A(n4024), .Y(DP_OP_499J1_125_4188_n299) );
ADDFHX2TS U4151 ( .A(FPMULT_Op_MX[9]), .B(n2278), .CI(n3208), .CO(n3209),
.S(n3142) );
ADDFHX2TS U4152 ( .A(n2277), .B(n2304), .CI(n3793), .CO(n3208), .S(n3135) );
OAI21X2TS U4153 ( .A0(n3773), .A1(n3722), .B0(n3772), .Y(n3777) );
XOR2X4TS U4154 ( .A(n3660), .B(n3468), .Y(n2252) );
OAI21X2TS U4155 ( .A0(n3599), .A1(n3722), .B0(n3598), .Y(n3601) );
ADDHX1TS U4156 ( .A(n4185), .B(n4184), .CO(DP_OP_501J1_127_1459_n490), .S(
n4186) );
INVX2TS U4157 ( .A(n2247), .Y(n2304) );
INVX8TS U4158 ( .A(n2276), .Y(n2277) );
INVX6TS U4159 ( .A(n2348), .Y(n2349) );
INVX2TS U4160 ( .A(n3134), .Y(n2274) );
BUFX3TS U4161 ( .A(n6920), .Y(n7012) );
INVX2TS U4162 ( .A(n2447), .Y(n2297) );
OA21X2TS U4163 ( .A0(n4507), .A1(n3575), .B0(n3574), .Y(n2447) );
INVX2TS U4164 ( .A(n6665), .Y(n6437) );
OA21X2TS U4165 ( .A0(n4384), .A1(n4383), .B0(n4380), .Y(n5471) );
CLKBUFX2TS U4166 ( .A(n3360), .Y(n5246) );
OR2X2TS U4167 ( .A(n3039), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[2]), .Y(
n2239) );
NAND2X2TS U4168 ( .A(n2549), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(
n4033) );
CLKXOR2X2TS U4169 ( .A(n3791), .B(n3790), .Y(n2240) );
INVX2TS U4170 ( .A(n4365), .Y(n5476) );
INVX2TS U4171 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[4]), .Y(
n2457) );
XNOR2X2TS U4172 ( .A(n3160), .B(n3159), .Y(n2245) );
INVX2TS U4173 ( .A(n4508), .Y(n5402) );
CLKXOR2X2TS U4174 ( .A(n4101), .B(n3144), .Y(n2246) );
CLKXOR2X2TS U4175 ( .A(DP_OP_501J1_127_1459_n741), .B(
DP_OP_501J1_127_1459_n794), .Y(n3134) );
XNOR2X2TS U4176 ( .A(n3207), .B(n3206), .Y(n3663) );
INVX2TS U4177 ( .A(n2229), .Y(n5499) );
INVX2TS U4178 ( .A(n5874), .Y(n5855) );
CLKBUFX3TS U4179 ( .A(n2302), .Y(n2385) );
CLKBUFX3TS U4180 ( .A(n2302), .Y(n6979) );
CLKBUFX3TS U4181 ( .A(n4555), .Y(n6935) );
NOR2X4TS U4182 ( .A(n2802), .B(n2805), .Y(n2808) );
ADDFX2TS U4183 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]), .B(
n2823), .CI(n2822), .CO(n2824), .S(n2817) );
CLKXOR2X4TS U4184 ( .A(n6629), .B(n3141), .Y(n3665) );
OAI21X2TS U4185 ( .A0(n5937), .A1(n4460), .B0(n4459), .Y(n6057) );
AOI21X4TS U4186 ( .A0(n6028), .A1(n4478), .B0(n4477), .Y(n6039) );
NOR2X2TS U4187 ( .A(n4140), .B(n4131), .Y(n4206) );
NOR2X4TS U4188 ( .A(n2754), .B(n2757), .Y(n2809) );
NAND2X8TS U4189 ( .A(n2813), .B(n2812), .Y(n3466) );
OR2X4TS U4190 ( .A(DP_OP_498J1_124_4426_n152), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2545) );
AOI21X4TS U4191 ( .A0(n5772), .A1(n5770), .B0(n3041), .Y(n3042) );
XNOR2X4TS U4192 ( .A(n4106), .B(n4105), .Y(n4107) );
OAI21X2TS U4193 ( .A0(n4101), .A1(n4100), .B0(n4099), .Y(n4106) );
OAI21X2TS U4194 ( .A0(n6134), .A1(n6130), .B0(n6131), .Y(n6115) );
ADDFHX4TS U4195 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]), .B(
n2710), .CI(n2709), .CO(n2711), .S(n2671) );
OAI21X2TS U4196 ( .A0(n6168), .A1(n6165), .B0(n6169), .Y(n2991) );
XNOR2X2TS U4197 ( .A(n3000), .B(n2880), .Y(n2990) );
NOR2X8TS U4198 ( .A(n4006), .B(n3992), .Y(n3077) );
CLKXOR2X4TS U4199 ( .A(n2663), .B(n2676), .Y(n3070) );
NAND2X4TS U4200 ( .A(n3071), .B(n3070), .Y(n4409) );
NAND2X2TS U4201 ( .A(DP_OP_501J1_127_1459_n182), .B(
DP_OP_501J1_127_1459_n189), .Y(n4072) );
XNOR2X2TS U4202 ( .A(n4299), .B(FPMULT_Op_MY[11]), .Y(n3628) );
INVX2TS U4203 ( .A(FPSENCOS_cont_iter_out[3]), .Y(n2272) );
INVX2TS U4204 ( .A(n2280), .Y(n2281) );
INVX2TS U4205 ( .A(n2280), .Y(n2282) );
CLKBUFX2TS U4206 ( .A(n2205), .Y(n2287) );
INVX2TS U4207 ( .A(n2294), .Y(n2288) );
INVX2TS U4208 ( .A(n2294), .Y(n2289) );
INVX2TS U4209 ( .A(n2294), .Y(n2290) );
INVX2TS U4210 ( .A(n2294), .Y(n2291) );
INVX2TS U4211 ( .A(n2294), .Y(n2292) );
INVX2TS U4212 ( .A(n2294), .Y(n2293) );
INVX2TS U4213 ( .A(n7016), .Y(n2294) );
INVX2TS U4214 ( .A(n2294), .Y(n2295) );
INVX2TS U4215 ( .A(n2294), .Y(n2296) );
CLKBUFX2TS U4216 ( .A(n4638), .Y(n4777) );
INVX2TS U4217 ( .A(n2297), .Y(n2298) );
INVX2TS U4218 ( .A(n2251), .Y(n2300) );
INVX2TS U4219 ( .A(rst), .Y(n2302) );
INVX2TS U4220 ( .A(rst), .Y(n2303) );
INVX4TS U4221 ( .A(n6669), .Y(n2305) );
INVX2TS U4222 ( .A(n3362), .Y(n2306) );
INVX2TS U4223 ( .A(n2306), .Y(n2307) );
INVX2TS U4224 ( .A(n2227), .Y(n2319) );
INVX2TS U4225 ( .A(n2227), .Y(n2320) );
INVX2TS U4226 ( .A(n5842), .Y(n2321) );
INVX2TS U4227 ( .A(n5842), .Y(n2322) );
INVX4TS U4228 ( .A(n2225), .Y(n2323) );
INVX2TS U4229 ( .A(n2281), .Y(n2324) );
INVX2TS U4230 ( .A(n2254), .Y(n2327) );
INVX2TS U4231 ( .A(n2254), .Y(n2328) );
INVX4TS U4232 ( .A(n2246), .Y(n2334) );
INVX2TS U4233 ( .A(n2356), .Y(n2337) );
INVX2TS U4234 ( .A(n2337), .Y(n2338) );
INVX2TS U4235 ( .A(n6935), .Y(n2339) );
INVX2TS U4236 ( .A(n2339), .Y(n2340) );
INVX2TS U4237 ( .A(n2339), .Y(n2341) );
INVX2TS U4238 ( .A(n5845), .Y(n2342) );
INVX2TS U4239 ( .A(n5845), .Y(n2343) );
INVX2TS U4240 ( .A(n5839), .Y(n2344) );
INVX2TS U4241 ( .A(n5839), .Y(n2345) );
INVX2TS U4242 ( .A(n2442), .Y(n2346) );
INVX2TS U4243 ( .A(n2442), .Y(n2347) );
INVX2TS U4244 ( .A(n5213), .Y(n2350) );
INVX2TS U4245 ( .A(n2226), .Y(n5489) );
INVX2TS U4246 ( .A(FPADDSUB_left_right_SHT2), .Y(n2351) );
INVX4TS U4247 ( .A(n6396), .Y(n2352) );
INVX4TS U4248 ( .A(n5243), .Y(n2354) );
NOR2XLTS U4249 ( .A(n6679), .B(FPADDSUB_DMP_SFG[0]), .Y(n4438) );
AOI222X1TS U4250 ( .A0(n4398), .A1(n6758), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[13]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[13]), .Y(n7064) );
AOI21X2TS U4251 ( .A0(n5213), .A1(n3404), .B0(n3403), .Y(n5244) );
AOI21X2TS U4252 ( .A0(n5213), .A1(n6720), .B0(n3373), .Y(n5203) );
AOI21X2TS U4253 ( .A0(n5269), .A1(n6720), .B0(n3398), .Y(n5208) );
AOI21X2TS U4254 ( .A0(n3610), .A1(n6648), .B0(n3609), .Y(n5232) );
OAI211X2TS U4255 ( .A0(n6871), .A1(n6870), .B0(n6869), .C0(n6868), .Y(n6582)
);
AOI211X1TS U4256 ( .A0(n3281), .A1(n3280), .B0(n3279), .C0(n3278), .Y(n3282)
);
OAI21XLTS U4257 ( .A0(n6392), .A1(n4628), .B0(n2210), .Y(n2079) );
OAI21XLTS U4258 ( .A0(n6392), .A1(n2351), .B0(n2307), .Y(n2078) );
ADDHX1TS U4259 ( .A(n4423), .B(n4422), .CO(DP_OP_500J1_126_2852_n137), .S(
DP_OP_500J1_126_2852_n138) );
NOR3X1TS U4260 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n4537) );
OAI32X1TS U4261 ( .A0(n5322), .A1(n5321), .A2(n6246), .B0(n2230), .B1(n5322),
.Y(n2138) );
NOR3X4TS U4262 ( .A(n2230), .B(n5321), .C(n6246), .Y(n5322) );
AOI222X4TS U4263 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n4976) );
AOI222X4TS U4264 ( .A0(n6269), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n4974), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n4938) );
AOI222X4TS U4265 ( .A0(n6269), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n4985) );
AOI222X4TS U4266 ( .A0(n6269), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n4987) );
AOI222X4TS U4267 ( .A0(n6269), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n4979) );
AOI222X4TS U4268 ( .A0(n6269), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n4998) );
AOI222X4TS U4269 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n4982) );
AOI222X4TS U4270 ( .A0(n6269), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n4995) );
ADDHX1TS U4271 ( .A(n4259), .B(n4258), .CO(DP_OP_501J1_127_1459_n477), .S(
DP_OP_501J1_127_1459_n478) );
NOR2X1TS U4272 ( .A(n4256), .B(n4254), .Y(n4259) );
NAND2X1TS U4273 ( .A(n6021), .B(n6787), .Y(n4355) );
BUFX3TS U4274 ( .A(n6979), .Y(n6997) );
NOR2X2TS U4275 ( .A(n5607), .B(n5606), .Y(n5613) );
OAI21X1TS U4276 ( .A0(n5628), .A1(n5627), .B0(n4900), .Y(mult_x_311_n22) );
OAI21X2TS U4277 ( .A0(n4893), .A1(n4892), .B0(n4918), .Y(n5627) );
INVX2TS U4278 ( .A(n2253), .Y(n2357) );
INVX2TS U4279 ( .A(n2253), .Y(n2358) );
INVX2TS U4280 ( .A(n2253), .Y(n2359) );
NOR2X2TS U4281 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6241), .Y(n6231) );
OAI21X2TS U4282 ( .A0(n2272), .A1(n6682), .B0(n6332), .Y(n6241) );
OAI2BB1X1TS U4283 ( .A0N(n5274), .A1N(n3612), .B0(n3616), .Y(n3618) );
NAND3X2TS U4284 ( .A(n3608), .B(n3607), .C(n3606), .Y(n5274) );
NOR2X2TS U4285 ( .A(n6692), .B(n4891), .Y(n5609) );
NOR2X2TS U4286 ( .A(n6688), .B(n6652), .Y(n5707) );
OAI2BB2XLTS U4287 ( .B0(n3368), .B1(n5202), .A0N(n2354), .A1N(n4403), .Y(
n4408) );
OAI21X2TS U4288 ( .A0(n2210), .A1(n6719), .B0(n3393), .Y(n4403) );
ADDHX1TS U4289 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .B(
n4048), .CO(DP_OP_499J1_125_4188_n252), .S(n4051) );
XNOR2X1TS U4290 ( .A(n2646), .B(n3116), .Y(n4048) );
NOR2X2TS U4291 ( .A(n6697), .B(n5702), .Y(n5705) );
INVX2TS U4292 ( .A(n4631), .Y(n4811) );
AOI21X2TS U4293 ( .A0(n5310), .A1(n5121), .B0(n5132), .Y(n5521) );
NAND3X2TS U4294 ( .A(n4624), .B(n6683), .C(n6644), .Y(n4556) );
NOR2X2TS U4295 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n4624) );
NOR2X4TS U4296 ( .A(FPSENCOS_cont_iter_out[2]), .B(n6339), .Y(n6233) );
OAI21X2TS U4297 ( .A0(n4906), .A1(n4905), .B0(n4904), .Y(n5624) );
INVX2TS U4298 ( .A(n4687), .Y(n4805) );
BUFX3TS U4299 ( .A(n2302), .Y(n4560) );
BUFX3TS U4300 ( .A(n2302), .Y(n4561) );
OAI22X2TS U4301 ( .A0(n5143), .A1(n5135), .B0(n5134), .B1(n5133), .Y(n5140)
);
AOI21X2TS U4302 ( .A0(n5269), .A1(n3404), .B0(n3402), .Y(n5245) );
BUFX3TS U4303 ( .A(n4562), .Y(n2360) );
INVX2TS U4304 ( .A(n6175), .Y(n2361) );
CLKBUFX3TS U4305 ( .A(n4557), .Y(n6966) );
AOI222X1TS U4306 ( .A0(n6432), .A1(n6744), .B0(n4392), .B1(
FPSENCOS_d_ff_Xn[30]), .C0(n4360), .C1(FPSENCOS_d_ff_Yn[30]), .Y(n7081) );
NOR3XLTS U4307 ( .A(n6450), .B(FPMULT_Op_MY[24]), .C(FPMULT_Op_MY[23]), .Y(
n6453) );
AOI222X1TS U4308 ( .A0(n6432), .A1(n6768), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[25]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[25]), .Y(n7076) );
AOI222X1TS U4309 ( .A0(n6432), .A1(n6770), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[27]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[27]), .Y(n7078) );
AOI222X1TS U4310 ( .A0(n4398), .A1(n6750), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[5]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[5]), .Y(n7056)
);
CLKBUFX3TS U4311 ( .A(n4621), .Y(n4555) );
NOR4X1TS U4312 ( .A(FPMULT_Op_MY[28]), .B(FPMULT_Op_MY[27]), .C(
FPMULT_Op_MY[26]), .D(FPMULT_Op_MY[25]), .Y(n6452) );
INVX2TS U4313 ( .A(FPADDSUB_intDX_EWSW[6]), .Y(n3261) );
OAI21X1TS U4314 ( .A0(FPADDSUB_intDY_EWSW[31]), .A1(FPADDSUB_intAS), .B0(
FPADDSUB_Shift_reg_FLAGS_7_6), .Y(n6571) );
AOI21X2TS U4315 ( .A0(FPADDSUB_intDY_EWSW[31]), .A1(FPADDSUB_intAS), .B0(
n6571), .Y(n6583) );
NOR3XLTS U4316 ( .A(n6925), .B(FPMULT_Op_MX[24]), .C(FPMULT_Op_MX[23]), .Y(
n6461) );
INVX2TS U4317 ( .A(FPADDSUB_intDX_EWSW[16]), .Y(n3246) );
OAI21X2TS U4318 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(n2350), .B0(n3392),
.Y(n5202) );
AOI21X2TS U4319 ( .A0(n5213), .A1(n4648), .B0(n3370), .Y(n5226) );
NAND2X1TS U4320 ( .A(n2361), .B(FPMULT_P_Sgf[30]), .Y(n3430) );
NAND3X2TS U4321 ( .A(n6666), .B(n2318), .C(FPADDSUB_shift_value_SHT2_EWR[3]),
.Y(n5842) );
NAND2X1TS U4322 ( .A(n2318), .B(n4548), .Y(n5845) );
NOR2X4TS U4323 ( .A(n6637), .B(n4628), .Y(n5850) );
OAI211XLTS U4324 ( .A0(n3368), .A1(n5231), .B0(n5230), .C0(n5229), .Y(n1795)
);
INVX2TS U4325 ( .A(n2266), .Y(n2362) );
NOR2X2TS U4326 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5793) );
NOR4BX2TS U4327 ( .AN(n4528), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]),
.C(n6685), .D(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n5014) );
NOR2X1TS U4328 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4337) );
AOI221X1TS U4329 ( .A0(n2260), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n2415), .C0(n6553), .Y(n6554) );
AOI32X1TS U4330 ( .A0(n2433), .A1(n3289), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n2428), .Y(n3290) );
AOI221X1TS U4331 ( .A0(n3257), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n6698), .C0(n6556), .Y(n6561) );
AOI222X1TS U4332 ( .A0(n5262), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n6660),
.B1(n5294), .C0(FPADDSUB_intDX_EWSW[25]), .C1(n5263), .Y(n7084) );
OAI221X1TS U4333 ( .A0(n2256), .A1(FPADDSUB_intDY_EWSW[9]), .B0(n2404), .B1(
FPADDSUB_intDY_EWSW[8]), .C0(n6534), .Y(n6537) );
AOI221X1TS U4334 ( .A0(n2261), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[19]), .B1(n2231), .C0(n6555), .Y(n6562) );
OAI221XLTS U4335 ( .A0(n2255), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n6542),
.B1(FPADDSUB_intDY_EWSW[12]), .C0(n6541), .Y(n6549) );
OAI221XLTS U4336 ( .A0(n6546), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2258),
.B1(FPADDSUB_intDY_EWSW[14]), .C0(n6545), .Y(n6547) );
OAI221X1TS U4337 ( .A0(n2257), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2204),
.B1(FPADDSUB_intDY_EWSW[20]), .C0(n6543), .Y(n6548) );
AOI221X1TS U4338 ( .A0(n2262), .A1(FPADDSUB_intDY_EWSW[21]), .B0(
FPADDSUB_intDY_EWSW[28]), .B1(n3314), .C0(n6557), .Y(n6560) );
OAI221X1TS U4339 ( .A0(n3248), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2432),
.B1(FPADDSUB_intDY_EWSW[7]), .C0(n6532), .Y(n6539) );
CLKBUFX2TS U4340 ( .A(n4242), .Y(n2363) );
AOI21X2TS U4341 ( .A0(n4125), .A1(n2436), .B0(n4120), .Y(n4121) );
INVX2TS U4342 ( .A(n3700), .Y(n2364) );
INVX2TS U4343 ( .A(n4420), .Y(n5467) );
INVX2TS U4344 ( .A(n3539), .Y(n2366) );
INVX2TS U4345 ( .A(n3539), .Y(n5394) );
NOR2X2TS U4346 ( .A(n6440), .B(FPMULT_Op_MY[2]), .Y(n3567) );
NOR2X2TS U4347 ( .A(n2223), .B(n6440), .Y(n3781) );
CLKBUFX2TS U4348 ( .A(n5474), .Y(n2367) );
CLKBUFX2TS U4349 ( .A(n5472), .Y(n2368) );
CLKBUFX2TS U4350 ( .A(n5398), .Y(n2369) );
BUFX20TS U4351 ( .A(n3982), .Y(n2371) );
INVX4TS U4352 ( .A(n2283), .Y(n4293) );
NOR2X1TS U4353 ( .A(n4277), .B(n4264), .Y(n4270) );
INVX2TS U4354 ( .A(n4107), .Y(n2374) );
BUFX3TS U4355 ( .A(mult_x_313_n74), .Y(n2375) );
BUFX3TS U4356 ( .A(n4338), .Y(n2376) );
AOI31XLTS U4357 ( .A0(n6194), .A1(n6193), .A2(n6192), .B0(dataB[27]), .Y(
n6205) );
INVX1TS U4358 ( .A(n5313), .Y(n4522) );
AOI32X4TS U4359 ( .A0(n6275), .A1(n2230), .A2(n6246), .B0(n4529), .B1(
FPSENCOS_d_ff3_LUT_out[26]), .Y(n4644) );
AOI222X4TS U4360 ( .A0(n6269), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n4977) );
AOI222X4TS U4361 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n4986) );
AOI222X4TS U4362 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n4989) );
AOI222X4TS U4363 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4997), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n4981) );
AOI222X4TS U4364 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n4988) );
AOI222X4TS U4365 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n4996), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n4973) );
AOI222X4TS U4366 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n4980) );
AOI222X4TS U4367 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n4984) );
AOI222X4TS U4368 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n4983) );
AOI222X4TS U4369 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n4990) );
AOI222X4TS U4370 ( .A0(n4993), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n4994) );
AOI222X4TS U4371 ( .A0(n5009), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4992), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n4991), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n4975) );
CLKXOR2X2TS U4372 ( .A(n5569), .B(n5568), .Y(n5589) );
CLKXOR2X2TS U4373 ( .A(n5675), .B(n5674), .Y(n5696) );
NOR4X1TS U4374 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n6846) );
NOR4X1TS U4375 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n6845) );
NOR2X2TS U4376 ( .A(n5559), .B(n4719), .Y(n5570) );
NOR2X2TS U4377 ( .A(n5664), .B(n4815), .Y(n5677) );
CLKBUFX2TS U4378 ( .A(n4231), .Y(n2377) );
NOR2X1TS U4379 ( .A(n4231), .B(n4275), .Y(n4233) );
OAI22X1TS U4380 ( .A0(n2329), .A1(n4216), .B0(n4231), .B1(n4215), .Y(n3841)
);
NOR2X1TS U4381 ( .A(n4231), .B(n4234), .Y(n3842) );
NOR2X1TS U4382 ( .A(n4231), .B(n4266), .Y(n4218) );
OAI22X1TS U4383 ( .A0(n2329), .A1(n4266), .B0(n4231), .B1(n4267), .Y(n3703)
);
NOR2X1TS U4384 ( .A(n4231), .B(n4280), .Y(n3704) );
OAI22X1TS U4385 ( .A0(n2329), .A1(n4234), .B0(n4231), .B1(n4264), .Y(n4217)
);
XOR2X4TS U4386 ( .A(n3166), .B(n3165), .Y(n4231) );
NOR2X1TS U4387 ( .A(n4732), .B(n4751), .Y(n4753) );
NOR2X2TS U4388 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n6329), .Y(n6333) );
OAI33X4TS U4389 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .A2(n6428), .B0(n2268), .B1(n6723),
.B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6429) );
AOI21X2TS U4390 ( .A0(n4545), .A1(n4544), .B0(n5115), .Y(n5503) );
AOI22X2TS U4391 ( .A0(n4888), .A1(n4887), .B0(n4886), .B1(n5607), .Y(n5628)
);
AOI22X2TS U4392 ( .A0(n5130), .A1(n5129), .B0(n5128), .B1(n7030), .Y(n5517)
);
NAND2X1TS U4393 ( .A(n5102), .B(n5101), .Y(n5130) );
NOR2X2TS U4394 ( .A(n6683), .B(n6644), .Y(n6433) );
NOR2X2TS U4395 ( .A(n5708), .B(n6652), .Y(n4823) );
NOR2X4TS U4396 ( .A(n6663), .B(n6271), .Y(n6247) );
AOI21X2TS U4397 ( .A0(n4897), .A1(n4872), .B0(n4902), .Y(n5631) );
OAI21X2TS U4398 ( .A0(n5528), .A1(n6662), .B0(n5127), .Y(n5524) );
OAI21X2TS U4399 ( .A0(n5141), .A1(n5140), .B0(n5139), .Y(n5515) );
OAI21X2TS U4400 ( .A0(n4750), .A1(n4749), .B0(n4748), .Y(n5584) );
OAI21X2TS U4401 ( .A0(n4724), .A1(n4723), .B0(n4744), .Y(n5592) );
NAND2X1TS U4402 ( .A(n4724), .B(n4723), .Y(n4744) );
OAI21X2TS U4403 ( .A0(n4821), .A1(n4820), .B0(n4839), .Y(n5699) );
NOR2X1TS U4404 ( .A(n4837), .B(n4819), .Y(n4821) );
NAND2X1TS U4405 ( .A(n4821), .B(n4820), .Y(n4839) );
AOI22X2TS U4406 ( .A0(n5655), .A1(n5654), .B0(n5653), .B1(n5652), .Y(n5688)
);
NAND2X1TS U4407 ( .A(n5669), .B(n4849), .Y(n5655) );
AOI22X2TS U4408 ( .A0(n5550), .A1(n5549), .B0(n5548), .B1(n5547), .Y(n5581)
);
NAND2X1TS U4409 ( .A(n5563), .B(n4754), .Y(n5550) );
AOI22X2TS U4410 ( .A0(n5620), .A1(n4915), .B0(n4914), .B1(n4913), .Y(n5623)
);
OAI22X2TS U4411 ( .A0(n5119), .A1(n5118), .B0(n5117), .B1(n5116), .Y(n5520)
);
OR2X1TS U4412 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n5948) );
OR2X1TS U4413 ( .A(n6784), .B(FPADDSUB_DMP_SFG[9]), .Y(n4454) );
AOI222X1TS U4414 ( .A0(n4401), .A1(n6774), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[15]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[15]), .Y(n7066) );
AOI222X1TS U4415 ( .A0(n4401), .A1(n6762), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[18]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[18]), .Y(n7069) );
AOI222X1TS U4416 ( .A0(n4401), .A1(n6765), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[21]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[21]), .Y(n7072) );
AOI222X1TS U4417 ( .A0(n4398), .A1(n6749), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[4]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[4]), .Y(n7055)
);
AOI222X1TS U4418 ( .A0(n4398), .A1(n6753), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[8]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[8]), .Y(n7059)
);
AOI222X1TS U4419 ( .A0(n4398), .A1(n6756), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[11]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[11]), .Y(n7062) );
AOI222X1TS U4420 ( .A0(n4359), .A1(n6746), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[0]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[0]), .Y(n7051)
);
AOI222X1TS U4421 ( .A0(n4398), .A1(n6754), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[9]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[9]), .Y(n7060)
);
AOI222X1TS U4422 ( .A0(n4359), .A1(n6771), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[28]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[28]), .Y(n7079) );
AOI222X1TS U4423 ( .A0(n4401), .A1(n6763), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[19]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[19]), .Y(n7070) );
AOI222X1TS U4424 ( .A0(n4401), .A1(n6764), .B0(n4400), .B1(
FPSENCOS_d_ff_Xn[20]), .C0(n4399), .C1(FPSENCOS_d_ff_Yn[20]), .Y(n7071) );
AOI222X1TS U4425 ( .A0(n4401), .A1(n6761), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[17]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[17]), .Y(n7068) );
AOI222X1TS U4426 ( .A0(n4398), .A1(n6751), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[6]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[6]), .Y(n7057)
);
AOI222X1TS U4427 ( .A0(n4401), .A1(n6760), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[16]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[16]), .Y(n7067) );
AOI222X1TS U4428 ( .A0(n4401), .A1(n6759), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[14]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[14]), .Y(n7065) );
AOI222X1TS U4429 ( .A0(n4398), .A1(n6755), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[10]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[10]), .Y(n7061) );
AOI222X1TS U4430 ( .A0(n4398), .A1(n6757), .B0(n4397), .B1(
FPSENCOS_d_ff_Xn[12]), .C0(n4396), .C1(FPSENCOS_d_ff_Yn[12]), .Y(n7063) );
AOI222X1TS U4431 ( .A0(n6432), .A1(n6745), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[3]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[3]), .Y(n7054)
);
AOI222X1TS U4432 ( .A0(n6432), .A1(n6748), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[2]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[2]), .Y(n7053)
);
AOI222X1TS U4433 ( .A0(n4398), .A1(n6752), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[7]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[7]), .Y(n7058)
);
AOI222X1TS U4434 ( .A0(n6432), .A1(n6747), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[1]), .C0(n4394), .C1(FPSENCOS_d_ff_Yn[1]), .Y(n7052)
);
NOR2X2TS U4435 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6094) );
NOR2X2TS U4436 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4600) );
INVX2TS U4437 ( .A(FPADDSUB_intDX_EWSW[4]), .Y(n3257) );
NOR4BX1TS U4438 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n6194) );
NOR2XLTS U4439 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n3525) );
BUFX3TS U4440 ( .A(n6920), .Y(n2380) );
BUFX3TS U4441 ( .A(n6920), .Y(n2381) );
BUFX3TS U4442 ( .A(n4556), .Y(n6920) );
CLKBUFX2TS U4443 ( .A(n5400), .Y(n2382) );
CLKXOR2X4TS U4444 ( .A(n3553), .B(n3552), .Y(n5400) );
BUFX3TS U4445 ( .A(FPADDSUB_left_right_SHT2), .Y(n2383) );
BUFX3TS U4446 ( .A(FPADDSUB_left_right_SHT2), .Y(n5874) );
OAI211XLTS U4447 ( .A0(n6658), .A1(n2358), .B0(n4637), .C0(n4636), .Y(n1527)
);
AOI21X2TS U4448 ( .A0(n3610), .A1(n4648), .B0(n3386), .Y(n5280) );
OAI21X2TS U4449 ( .A0(n2350), .A1(n6695), .B0(n3374), .Y(n5200) );
NAND2X1TS U4450 ( .A(n2361), .B(FPMULT_P_Sgf[29]), .Y(n3421) );
OAI21X2TS U4451 ( .A0(n2350), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n3358),
.Y(n5206) );
NAND2X1TS U4452 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[3]), .Y(n5680) );
NOR3X1TS U4453 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n6478), .Y(n6473) );
OA22X1TS U4454 ( .A0(n2400), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n2395), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n3281) );
NOR2X2TS U4455 ( .A(FPSENCOS_d_ff2_X[29]), .B(n6280), .Y(n6279) );
NOR2X2TS U4456 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4669) );
AOI211X1TS U4457 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2343), .B0(n5823),
.C0(n5822), .Y(n5865) );
OAI21XLTS U4458 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n2405), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n3251) );
OAI211XLTS U4459 ( .A0(n2405), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n3254), .C0(
n3253), .Y(n3259) );
INVX2TS U4460 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n5212) );
NOR2X4TS U4461 ( .A(n6223), .B(rst), .Y(n4621) );
NOR3X1TS U4462 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n4647) );
NOR2XLTS U4463 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n4861) );
XNOR2X4TS U4464 ( .A(n3229), .B(n3228), .Y(n4265) );
INVX2TS U4465 ( .A(n4265), .Y(n2386) );
INVX2TS U4466 ( .A(n4265), .Y(n2387) );
OR2X1TS U4467 ( .A(n6712), .B(FPADDSUB_DMP_SFG[18]), .Y(n4474) );
OAI211XLTS U4468 ( .A0(n3368), .A1(n5284), .B0(n5248), .C0(n5247), .Y(n1799)
);
OAI21XLTS U4469 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n6715), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n3252) );
OR2X1TS U4470 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n5959) );
OR2X1TS U4471 ( .A(n6702), .B(FPADDSUB_DMP_SFG[14]), .Y(n4466) );
OR2X1TS U4472 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n6046) );
OR2X1TS U4473 ( .A(n6701), .B(FPADDSUB_DMP_SFG[16]), .Y(n4470) );
OR2X1TS U4474 ( .A(n6722), .B(FPADDSUB_DMP_SFG[20]), .Y(n4478) );
OR2X1TS U4475 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n6055) );
NAND2X1TS U4476 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n6054) );
OR2X1TS U4477 ( .A(n6783), .B(FPADDSUB_DMP_SFG[12]), .Y(n4462) );
AOI211X2TS U4478 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n4548), .B0(n4552),
.C0(n4524), .Y(n5860) );
NOR2X1TS U4479 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n5933) );
NAND2X1TS U4480 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n5934) );
OAI2BB2XLTS U4481 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n3286), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n2417), .Y(n3297) );
OAI2BB1X1TS U4482 ( .A0N(FPADDSUB_intDY_EWSW[4]), .A1N(n3257), .B0(n3256),
.Y(n3258) );
INVX2TS U4483 ( .A(n7086), .Y(n6611) );
OAI21X2TS U4484 ( .A0(n2783), .A1(n2782), .B0(n2781), .Y(n2784) );
NAND2X2TS U4485 ( .A(n2546), .B(n2545), .Y(n2547) );
INVX4TS U4486 ( .A(n4014), .Y(n3006) );
OAI22X1TS U4487 ( .A0(n2386), .A1(n4280), .B0(n2331), .B1(n4278), .Y(
DP_OP_501J1_127_1459_n217) );
OAI21X4TS U4488 ( .A0(n3973), .A1(n3969), .B0(n3970), .Y(n3968) );
OR2X4TS U4489 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .B(
n2613), .Y(n2392) );
OR2X1TS U4490 ( .A(n2623), .B(n2622), .Y(n2425) );
INVX2TS U4491 ( .A(n3131), .Y(n5528) );
OR2X1TS U4492 ( .A(n4012), .B(n2907), .Y(n2437) );
OR2X4TS U4493 ( .A(n3063), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[5]), .Y(
n2440) );
OR2X2TS U4494 ( .A(n3907), .B(n3906), .Y(n2451) );
INVX2TS U4495 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(
n3120) );
INVX2TS U4496 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(
n3856) );
NAND2X4TS U4497 ( .A(n2530), .B(n2472), .Y(n2486) );
INVX2TS U4498 ( .A(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[4]), .Y(n2733) );
INVX2TS U4499 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(
n2454) );
OA21X2TS U4500 ( .A0(n2595), .A1(n2594), .B0(n2593), .Y(n2596) );
NOR2X1TS U4501 ( .A(n2388), .B(FPADDSUB_intDX_EWSW[11]), .Y(n3269) );
NAND2X1TS U4502 ( .A(n2604), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]),
.Y(n2607) );
AOI21X2TS U4503 ( .A0(n3873), .A1(n3885), .B0(n3890), .Y(n3967) );
AOI21X1TS U4504 ( .A0(n3260), .A1(n3259), .B0(n3258), .Y(n3264) );
INVX2TS U4505 ( .A(FPMULT_inst_RecursiveKOA_Result[5]), .Y(n2460) );
NAND2X1TS U4506 ( .A(n2605), .B(n2607), .Y(n2606) );
INVX2TS U4507 ( .A(n6129), .Y(DP_OP_499J1_125_4188_n279) );
NAND2X1TS U4508 ( .A(n2761), .B(n2804), .Y(n2762) );
NAND2X1TS U4509 ( .A(n3470), .B(n3475), .Y(n3471) );
OR2X2TS U4510 ( .A(n2817), .B(n2816), .Y(n3096) );
OAI21X2TS U4511 ( .A0(n3535), .A1(n3541), .B0(n3536), .Y(n3573) );
NOR2X2TS U4512 ( .A(n2611), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(
n2951) );
NAND2X1TS U4513 ( .A(n3100), .B(n3097), .Y(n2826) );
OAI21X2TS U4514 ( .A0(DP_OP_501J1_127_1459_n781), .A1(n3204), .B0(
DP_OP_501J1_127_1459_n782), .Y(n3126) );
NOR2X1TS U4515 ( .A(n2205), .B(n4228), .Y(n4184) );
OAI21X2TS U4516 ( .A0(n4099), .A1(n4102), .B0(n4103), .Y(n3211) );
INVX2TS U4517 ( .A(n2558), .Y(n2560) );
INVX2TS U4518 ( .A(n2951), .Y(n2963) );
NAND2X1TS U4519 ( .A(n3646), .B(n3710), .Y(n3653) );
NOR2X4TS U4520 ( .A(n2851), .B(n2856), .Y(n2865) );
NOR2X1TS U4521 ( .A(n5667), .B(n4846), .Y(n4848) );
NOR2X1TS U4522 ( .A(n2373), .B(n4276), .Y(n4282) );
INVX2TS U4523 ( .A(n3303), .Y(n3304) );
NAND2X1TS U4524 ( .A(n2526), .B(n2525), .Y(n2527) );
NAND2X1TS U4525 ( .A(n3052), .B(n3051), .Y(n3053) );
NAND2X1TS U4526 ( .A(n2853), .B(n2855), .Y(n2852) );
CMPR42X1TS U4527 ( .A(DP_OP_502J1_128_2852_n150), .B(
DP_OP_502J1_128_2852_n157), .C(DP_OP_502J1_128_2852_n185), .D(
DP_OP_502J1_128_2852_n164), .ICI(DP_OP_502J1_128_2852_n124), .S(
DP_OP_502J1_128_2852_n120), .ICO(DP_OP_502J1_128_2852_n118), .CO(
DP_OP_502J1_128_2852_n119) );
ADDHXLTS U4528 ( .A(n3812), .B(n3811), .CO(DP_OP_501J1_127_1459_n499), .S(
n3795) );
NOR2X1TS U4529 ( .A(n2377), .B(n4216), .Y(n4274) );
NOR2X4TS U4530 ( .A(n3659), .B(n3658), .Y(n3660) );
NOR2X1TS U4531 ( .A(DP_OP_502J1_128_2852_n123), .B(DP_OP_502J1_128_2852_n128), .Y(n5364) );
CMPR42X1TS U4532 ( .A(DP_OP_500J1_126_2852_n161), .B(
DP_OP_500J1_126_2852_n154), .C(DP_OP_500J1_126_2852_n147), .D(
DP_OP_500J1_126_2852_n106), .ICI(DP_OP_500J1_126_2852_n103), .S(
DP_OP_500J1_126_2852_n102), .ICO(DP_OP_500J1_126_2852_n100), .CO(
DP_OP_500J1_126_2852_n101) );
INVX2TS U4533 ( .A(n4421), .Y(n5461) );
NAND2X1TS U4534 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(n4552), .Y(n5837)
);
NAND2X1TS U4535 ( .A(n2318), .B(n2300), .Y(n5839) );
NOR2X1TS U4536 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n3327) );
INVX2TS U4537 ( .A(n4019), .Y(n3410) );
AOI21X1TS U4538 ( .A0(n5922), .A1(n4458), .B0(n4457), .Y(n5937) );
NAND2X2TS U4539 ( .A(n3073), .B(n3072), .Y(n4000) );
INVX2TS U4540 ( .A(n3982), .Y(n3745) );
NOR2XLTS U4541 ( .A(n4323), .B(n4315), .Y(n3683) );
OR2X1TS U4542 ( .A(n5159), .B(n5158), .Y(n5458) );
OAI21XLTS U4543 ( .A0(n6077), .A1(n6076), .B0(n6075), .Y(n6082) );
INVX2TS U4544 ( .A(n3368), .Y(n3612) );
OAI21XLTS U4545 ( .A0(n6664), .A1(n6692), .B0(n5640), .Y(n5332) );
OR2X1TS U4546 ( .A(n5324), .B(n5323), .Y(n5326) );
NAND2X1TS U4547 ( .A(n3765), .B(n4190), .Y(n3600) );
AO21X2TS U4548 ( .A0(n2391), .A1(n3189), .B0(n3188), .Y(n4082) );
OR2X1TS U4549 ( .A(n5328), .B(n5327), .Y(n5330) );
INVX2TS U4550 ( .A(FPSENCOS_d_ff2_Y[12]), .Y(n7047) );
INVX4TS U4551 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(
n2458) );
NOR2X8TS U4552 ( .A(n2456), .B(n2462), .Y(n2471) );
NAND2X4TS U4553 ( .A(n2463), .B(n2462), .Y(n2525) );
OAI21X4TS U4554 ( .A0(n2471), .A1(n2551), .B0(n2525), .Y(n2529) );
NAND2X4TS U4555 ( .A(n2465), .B(n2464), .Y(n2533) );
NAND2X2TS U4556 ( .A(n2467), .B(n2466), .Y(n2517) );
AOI21X4TS U4557 ( .A0(n2472), .A1(n2529), .B0(n2468), .Y(n2488) );
INVX8TS U4558 ( .A(n2513), .Y(n2530) );
AOI21X4TS U4559 ( .A0(n2545), .A1(n2617), .B0(n2473), .Y(n2543) );
OAI21X4TS U4560 ( .A0(n2543), .A1(n2540), .B0(n2541), .Y(n2537) );
NOR2X8TS U4561 ( .A(n2480), .B(n2479), .Y(n2556) );
NOR2X8TS U4562 ( .A(n2478), .B(n2482), .Y(n2558) );
NOR2X4TS U4563 ( .A(n2556), .B(n2558), .Y(n2485) );
OAI21X4TS U4564 ( .A0(n2558), .A1(n2555), .B0(n2559), .Y(n2484) );
AOI21X4TS U4565 ( .A0(n2537), .A1(n2485), .B0(n2484), .Y(n2554) );
NAND2X8TS U4566 ( .A(n2488), .B(n2487), .Y(n2601) );
INVX2TS U4567 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(
n2493) );
OR2X4TS U4568 ( .A(n2492), .B(n2491), .Y(n2522) );
NAND2X2TS U4569 ( .A(n2492), .B(n2491), .Y(n2521) );
INVX4TS U4570 ( .A(n2521), .Y(n2502) );
AOI21X4TS U4571 ( .A0(n2601), .A1(n2522), .B0(n2502), .Y(n2499) );
INVX4TS U4572 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
n2507) );
INVX2TS U4573 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(
n2506) );
NOR2X4TS U4574 ( .A(n2497), .B(n2496), .Y(n2495) );
NAND2X2TS U4575 ( .A(n2497), .B(n2496), .Y(n2500) );
XOR2X4TS U4576 ( .A(n2499), .B(n2498), .Y(n2575) );
NOR2X8TS U4577 ( .A(n2575), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(
n2934) );
NAND2X4TS U4578 ( .A(n2522), .B(n2503), .Y(n2592) );
INVX2TS U4579 ( .A(n2592), .Y(n2505) );
INVX2TS U4580 ( .A(n2500), .Y(n2501) );
AOI21X4TS U4581 ( .A0(n2503), .A1(n2502), .B0(n2501), .Y(n2598) );
INVX2TS U4582 ( .A(n2598), .Y(n2504) );
AOI21X4TS U4583 ( .A0(n2601), .A1(n2505), .B0(n2504), .Y(n2512) );
INVX2TS U4584 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n2584) );
CMPR32X2TS U4585 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]), .B(
n2507), .C(n2506), .CO(n2508), .S(n2497) );
INVX2TS U4586 ( .A(n2591), .Y(n2510) );
NAND2X2TS U4587 ( .A(n2509), .B(n2508), .Y(n2594) );
XOR2X4TS U4588 ( .A(n2512), .B(n2511), .Y(n2576) );
NOR2X8TS U4589 ( .A(n2576), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(
n2938) );
INVX2TS U4590 ( .A(n2529), .Y(n2514) );
INVX2TS U4591 ( .A(n2516), .Y(n2518) );
NAND2X1TS U4592 ( .A(n2522), .B(n2521), .Y(n2523) );
XNOR2X4TS U4593 ( .A(n2601), .B(n2523), .Y(n2574) );
NOR2X8TS U4594 ( .A(n2574), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2912) );
INVX2TS U4595 ( .A(n2551), .Y(n2524) );
INVX2TS U4596 ( .A(n2532), .Y(n2534) );
INVX2TS U4597 ( .A(n2556), .Y(n2538) );
NAND2X2TS U4598 ( .A(n2538), .B(n2555), .Y(n2539) );
XOR2X4TS U4599 ( .A(n2557), .B(n2539), .Y(n2549) );
INVX2TS U4600 ( .A(n2540), .Y(n2542) );
NAND2X4TS U4601 ( .A(n2542), .B(n2541), .Y(n2544) );
XOR2X4TS U4602 ( .A(n2544), .B(n2543), .Y(n2548) );
XNOR2X4TS U4603 ( .A(n2547), .B(n2617), .Y(n2636) );
NAND2X4TS U4604 ( .A(n4035), .B(n4034), .Y(n2550) );
NAND2X8TS U4605 ( .A(n4033), .B(n2550), .Y(n4022) );
OAI21X4TS U4606 ( .A0(n2557), .A1(n2556), .B0(n2555), .Y(n2562) );
XNOR2X4TS U4607 ( .A(n2562), .B(n2561), .Y(n2563) );
OR2X4TS U4608 ( .A(n2563), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(
n4020) );
NAND2X2TS U4609 ( .A(n3412), .B(n4020), .Y(n2567) );
NAND2X4TS U4610 ( .A(n2563), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(
n4019) );
AOI21X4TS U4611 ( .A0(n3412), .A1(n3410), .B0(n2565), .Y(n2566) );
OAI21X4TS U4612 ( .A0(n2568), .A1(n2567), .B0(n2566), .Y(n2898) );
AOI21X4TS U4613 ( .A0(n2572), .A1(n2898), .B0(n2571), .Y(n2911) );
NAND2X4TS U4614 ( .A(n2574), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2913) );
OAI21X4TS U4615 ( .A0(n2909), .A1(n2912), .B0(n2913), .Y(n2931) );
OAI21X4TS U4616 ( .A0(n2938), .A1(n2932), .B0(n2939), .Y(n2577) );
AOI21X4TS U4617 ( .A0(n2578), .A1(n2931), .B0(n2577), .Y(n2579) );
OAI21X4TS U4618 ( .A0(n2580), .A1(n2911), .B0(n2579), .Y(n2581) );
INVX12TS U4619 ( .A(n2965), .Y(n2973) );
AOI21X4TS U4620 ( .A0(n2601), .A1(n2583), .B0(n2582), .Y(n2590) );
INVX2TS U4621 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(
n2603) );
INVX2TS U4622 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n2602) );
CMPR32X2TS U4623 ( .A(n2585), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]),
.C(n2584), .CO(n2586), .S(n2509) );
NOR2X4TS U4624 ( .A(n2587), .B(n2586), .Y(n2595) );
INVX2TS U4625 ( .A(n2595), .Y(n2588) );
NAND2X2TS U4626 ( .A(n2587), .B(n2586), .Y(n2593) );
XOR2X4TS U4627 ( .A(n2590), .B(n2589), .Y(n2611) );
OR2X4TS U4628 ( .A(n2591), .B(n2595), .Y(n2597) );
AOI21X4TS U4629 ( .A0(n2601), .A1(n2600), .B0(n2599), .Y(n2609) );
CMPR32X2TS U4630 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]),
.B(n2603), .C(n2602), .CO(n2604), .S(n2587) );
INVX2TS U4631 ( .A(n2608), .Y(n2605) );
XOR2X4TS U4632 ( .A(n2609), .B(n2606), .Y(n2612) );
NOR2X4TS U4633 ( .A(n2951), .B(n2953), .Y(n2972) );
XNOR2X4TS U4634 ( .A(n2610), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]),
.Y(n2613) );
NAND2X4TS U4635 ( .A(n2972), .B(n2392), .Y(n2888) );
INVX2TS U4636 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
n2889) );
NOR2X4TS U4637 ( .A(n2888), .B(n2889), .Y(n2615) );
NAND2X2TS U4638 ( .A(n2612), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(
n2954) );
OAI21X4TS U4639 ( .A0(n2953), .A1(n2962), .B0(n2954), .Y(n2971) );
NAND2X2TS U4640 ( .A(n2613), .B(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(
n2974) );
INVX2TS U4641 ( .A(n2974), .Y(n2614) );
AOI21X4TS U4642 ( .A0(n2971), .A1(n2392), .B0(n2614), .Y(n2887) );
AOI2BB2X4TS U4643 ( .B0(n2973), .B1(n2615), .A0N(n2887), .A1N(n2889), .Y(
n2882) );
INVX2TS U4644 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
n2881) );
NOR2X6TS U4645 ( .A(DP_OP_499J1_125_4188_n227), .B(DP_OP_499J1_125_4188_n225), .Y(n3044) );
NOR2X8TS U4646 ( .A(DP_OP_499J1_125_4188_n222), .B(DP_OP_499J1_125_4188_n224), .Y(n3046) );
NOR2X6TS U4647 ( .A(n3044), .B(n3046), .Y(n3055) );
NOR2X6TS U4648 ( .A(DP_OP_499J1_125_4188_n231), .B(DP_OP_499J1_125_4188_n233), .Y(n3034) );
NOR2X8TS U4649 ( .A(DP_OP_499J1_125_4188_n228), .B(DP_OP_499J1_125_4188_n230), .Y(n3028) );
NOR2X4TS U4650 ( .A(n3034), .B(n3028), .Y(n2689) );
INVX2TS U4651 ( .A(FPMULT_inst_RecursiveKOA_Result[1]), .Y(n2621) );
XNOR2X1TS U4652 ( .A(n2621), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(
n2620) );
NOR2X1TS U4653 ( .A(n2620), .B(n2619), .Y(n2893) );
INVX2TS U4654 ( .A(n2904), .Y(n2618) );
NAND2X1TS U4655 ( .A(n2620), .B(n2619), .Y(n2894) );
OR2X2TS U4656 ( .A(n2621), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(
n2622) );
NAND2X1TS U4657 ( .A(n2623), .B(n2622), .Y(n2917) );
INVX2TS U4658 ( .A(n2917), .Y(n2624) );
INVX2TS U4659 ( .A(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[3]), .Y(n2628) );
CMPR32X2TS U4660 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .B(
n2625), .C(n2709), .CO(n2626), .S(n2623) );
NOR2X1TS U4661 ( .A(n2627), .B(n2626), .Y(n2924) );
NAND2X1TS U4662 ( .A(n2627), .B(n2626), .Y(n2925) );
CMPR32X2TS U4663 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .B(
n2629), .C(n2628), .CO(n2630), .S(n2627) );
NAND2X1TS U4664 ( .A(n2631), .B(n2630), .Y(n2943) );
INVX2TS U4665 ( .A(n2943), .Y(n2632) );
AOI21X2TS U4666 ( .A0(n2946), .A1(n2944), .B0(n2632), .Y(n2970) );
INVX2TS U4667 ( .A(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[5]), .Y(n2635) );
CMPR32X2TS U4668 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .B(
n2457), .C(n2733), .CO(n2633), .S(n2631) );
NOR2X1TS U4669 ( .A(n2634), .B(n2633), .Y(n2966) );
NAND2X1TS U4670 ( .A(n2634), .B(n2633), .Y(n2967) );
OAI21X4TS U4671 ( .A0(n2970), .A1(n2966), .B0(n2967), .Y(n2961) );
CMPR32X2TS U4672 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .B(
n2460), .C(n2635), .CO(n2648), .S(n2634) );
OR2X4TS U4673 ( .A(n2638), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2659) );
OR2X2TS U4674 ( .A(n2640), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(
n2641) );
AND2X4TS U4675 ( .A(n2641), .B(n2676), .Y(n3066) );
INVX2TS U4676 ( .A(n3066), .Y(n2642) );
NAND2X1TS U4677 ( .A(n2643), .B(n2642), .Y(n2958) );
INVX2TS U4678 ( .A(n2958), .Y(n2644) );
OR2X4TS U4679 ( .A(n2645), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(
n3117) );
NAND2X2TS U4680 ( .A(n3117), .B(n3114), .Y(n2646) );
INVX2TS U4681 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .Y(
n3116) );
INVX2TS U4682 ( .A(n2649), .Y(n2651) );
NAND2X2TS U4683 ( .A(n2651), .B(n2650), .Y(n2653) );
XNOR2X4TS U4684 ( .A(n2669), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2654) );
INVX2TS U4685 ( .A(n2668), .Y(n2655) );
INVX2TS U4686 ( .A(n2656), .Y(n2657) );
AOI21X4TS U4687 ( .A0(n2659), .A1(n2658), .B0(n2657), .Y(n2667) );
INVX2TS U4688 ( .A(n2677), .Y(n2662) );
NAND2X1TS U4689 ( .A(n2662), .B(n2675), .Y(n2663) );
OAI21X4TS U4690 ( .A0(n2668), .A1(n2667), .B0(n2666), .Y(n2714) );
INVX4TS U4691 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2710) );
INVX2TS U4692 ( .A(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[2]), .Y(n2709) );
NOR2X8TS U4693 ( .A(n2671), .B(n2670), .Y(n2718) );
INVX2TS U4694 ( .A(n2718), .Y(n2672) );
NAND2X6TS U4695 ( .A(n2671), .B(n2670), .Y(n2717) );
NAND2X1TS U4696 ( .A(n2705), .B(n2702), .Y(n2678) );
XNOR2X2TS U4697 ( .A(n2678), .B(n2704), .Y(n3072) );
INVX2TS U4698 ( .A(n3072), .Y(n2679) );
INVX2TS U4699 ( .A(n2883), .Y(n2680) );
AOI21X4TS U4700 ( .A0(n2885), .A1(n2884), .B0(n2680), .Y(n2878) );
NAND2X2TS U4701 ( .A(DP_OP_499J1_125_4188_n246), .B(
DP_OP_499J1_125_4188_n248), .Y(n2879) );
INVX2TS U4702 ( .A(n2879), .Y(n2999) );
NAND2X2TS U4703 ( .A(DP_OP_499J1_125_4188_n243), .B(
DP_OP_499J1_125_4188_n245), .Y(n3002) );
OR2X4TS U4704 ( .A(DP_OP_499J1_125_4188_n240), .B(DP_OP_499J1_125_4188_n242),
.Y(n2994) );
NAND2X2TS U4705 ( .A(DP_OP_499J1_125_4188_n240), .B(
DP_OP_499J1_125_4188_n242), .Y(n2993) );
INVX2TS U4706 ( .A(n2993), .Y(n2684) );
AOI21X4TS U4707 ( .A0(n2995), .A1(n2994), .B0(n2684), .Y(n3014) );
INVX4TS U4708 ( .A(n3016), .Y(n2685) );
AOI21X4TS U4709 ( .A0(n3017), .A1(n3015), .B0(n2685), .Y(n2686) );
OAI21X4TS U4710 ( .A0(n2687), .A1(n3014), .B0(n2686), .Y(n3027) );
NAND2X4TS U4711 ( .A(DP_OP_499J1_125_4188_n231), .B(
DP_OP_499J1_125_4188_n233), .Y(n3035) );
OAI21X4TS U4712 ( .A0(n3028), .A1(n3035), .B0(n3029), .Y(n2688) );
AOI21X4TS U4713 ( .A0(n2689), .A1(n3027), .B0(n2688), .Y(n2840) );
NOR2X4TS U4714 ( .A(DP_OP_499J1_125_4188_n219), .B(DP_OP_499J1_125_4188_n221), .Y(n2841) );
OAI21X4TS U4715 ( .A0(n3046), .A1(n3052), .B0(n3047), .Y(n3054) );
NAND2X4TS U4716 ( .A(DP_OP_499J1_125_4188_n219), .B(
DP_OP_499J1_125_4188_n221), .Y(n3058) );
NAND2X2TS U4717 ( .A(DP_OP_499J1_125_4188_n216), .B(
DP_OP_499J1_125_4188_n218), .Y(n2847) );
AOI21X4TS U4718 ( .A0(n3054), .A1(n2692), .B0(n2691), .Y(n2693) );
OAI2BB1X4TS U4719 ( .A0N(n3055), .A1N(n2694), .B0(n2693), .Y(n2866) );
INVX2TS U4720 ( .A(n2865), .Y(n2695) );
NOR2X8TS U4721 ( .A(DP_OP_499J1_125_4188_n207), .B(DP_OP_499J1_125_4188_n209), .Y(n2867) );
NOR2X2TS U4722 ( .A(n2695), .B(n2867), .Y(n2698) );
OAI21X4TS U4723 ( .A0(n2856), .A1(n2853), .B0(n2857), .Y(n2864) );
INVX2TS U4724 ( .A(n2864), .Y(n2696) );
NAND2X4TS U4725 ( .A(DP_OP_499J1_125_4188_n207), .B(
DP_OP_499J1_125_4188_n209), .Y(n2868) );
NOR2X8TS U4726 ( .A(DP_OP_499J1_125_4188_n206), .B(DP_OP_499J1_125_4188_n204), .Y(n2744) );
INVX2TS U4727 ( .A(n2744), .Y(n2699) );
NAND2X4TS U4728 ( .A(DP_OP_499J1_125_4188_n204), .B(
DP_OP_499J1_125_4188_n206), .Y(n2743) );
INVX2TS U4729 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(
n2734) );
NAND2X4TS U4730 ( .A(n2707), .B(n2706), .Y(n2756) );
NOR2X8TS U4731 ( .A(n2712), .B(n2711), .Y(n2720) );
NOR2X4TS U4732 ( .A(n2718), .B(n2720), .Y(n2715) );
NAND2X4TS U4733 ( .A(n2712), .B(n2711), .Y(n2721) );
OAI21X4TS U4734 ( .A0(n2720), .A1(n2717), .B0(n2721), .Y(n2713) );
AOI21X4TS U4735 ( .A0(n2715), .A1(n2714), .B0(n2713), .Y(n2810) );
INVX2TS U4736 ( .A(n2720), .Y(n2722) );
INVX2TS U4737 ( .A(n2874), .Y(n2728) );
OAI21X4TS U4738 ( .A0(n2861), .A1(n2730), .B0(n2729), .Y(n2785) );
INVX2TS U4739 ( .A(n2756), .Y(n2731) );
ADDFX2TS U4740 ( .A(n2734), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]), .CI(
n2733), .CO(n2735), .S(n2707) );
INVX2TS U4741 ( .A(n2757), .Y(n2737) );
NAND2X2TS U4742 ( .A(n2736), .B(n2735), .Y(n2755) );
XOR2X4TS U4743 ( .A(n2739), .B(n2738), .Y(n2740) );
NOR2X4TS U4744 ( .A(n2740), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(
n2780) );
INVX2TS U4745 ( .A(n2780), .Y(n2741) );
NAND2X4TS U4746 ( .A(n2740), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(
n2782) );
NAND2X4TS U4747 ( .A(n2865), .B(n2746), .Y(n2768) );
INVX2TS U4748 ( .A(n2768), .Y(n2748) );
OAI21X4TS U4749 ( .A0(n2744), .A1(n2868), .B0(n2743), .Y(n2745) );
AOI21X4TS U4750 ( .A0(n2746), .A1(n2864), .B0(n2745), .Y(n2771) );
INVX2TS U4751 ( .A(n2770), .Y(n2750) );
OAI21X4TS U4752 ( .A0(n2757), .A1(n2756), .B0(n2755), .Y(n2807) );
AOI21X2TS U4753 ( .A0(n2791), .A1(n2809), .B0(n2807), .Y(n2763) );
INVX2TS U4754 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(
n2792) );
INVX2TS U4755 ( .A(n2802), .Y(n2761) );
XOR2X4TS U4756 ( .A(n2763), .B(n2762), .Y(n2764) );
INVX2TS U4757 ( .A(n2783), .Y(n2765) );
NAND2X2TS U4758 ( .A(n2764), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(
n2781) );
XNOR2X4TS U4759 ( .A(n2767), .B(n2766), .Y(n4011) );
INVX2TS U4760 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]), .Y(
n2774) );
AOI21X4TS U4761 ( .A0(n2786), .A1(n2785), .B0(n2784), .Y(n3441) );
INVX2TS U4762 ( .A(n2809), .Y(n2787) );
NOR2X2TS U4763 ( .A(n2787), .B(n2802), .Y(n2790) );
INVX2TS U4764 ( .A(n2807), .Y(n2788) );
AOI21X4TS U4765 ( .A0(n2791), .A1(n2790), .B0(n2789), .Y(n2798) );
INVX2TS U4766 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(
n2814) );
INVX2TS U4767 ( .A(n2805), .Y(n2796) );
XOR2X4TS U4768 ( .A(n2798), .B(n2797), .Y(n2799) );
NAND2X4TS U4769 ( .A(n2799), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(
n2832) );
NOR2X4TS U4770 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .B(
n2799), .Y(n2819) );
INVX2TS U4771 ( .A(n2819), .Y(n2834) );
XNOR2X4TS U4772 ( .A(n3095), .B(n2800), .Y(n4039) );
AOI21X4TS U4773 ( .A0(n2807), .A1(n2808), .B0(n2806), .Y(n2813) );
NAND2X4TS U4774 ( .A(n2809), .B(n2808), .Y(n2811) );
INVX2TS U4775 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(
n2822) );
NAND2X2TS U4776 ( .A(n2817), .B(n2816), .Y(n2821) );
NAND2X1TS U4777 ( .A(n3096), .B(n2821), .Y(n2818) );
XNOR2X4TS U4778 ( .A(n3466), .B(n2818), .Y(n2820) );
NOR2X6TS U4779 ( .A(n2820), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2835) );
NOR2X4TS U4780 ( .A(n2819), .B(n2835), .Y(n3433) );
NAND2X2TS U4781 ( .A(n2820), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2836) );
OAI21X4TS U4782 ( .A0(n2832), .A1(n2835), .B0(n2836), .Y(n3438) );
AOI21X1TS U4783 ( .A0(n3095), .A1(n3433), .B0(n3438), .Y(n2831) );
INVX4TS U4784 ( .A(n2821), .Y(n3099) );
AOI21X4TS U4785 ( .A0(n3466), .A1(n3096), .B0(n3099), .Y(n2827) );
INVX2TS U4786 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(
n3103) );
OR2X4TS U4787 ( .A(n2825), .B(n2824), .Y(n3100) );
NAND2X2TS U4788 ( .A(n2825), .B(n2824), .Y(n3097) );
XOR2X4TS U4789 ( .A(n2827), .B(n2826), .Y(n2828) );
NOR2X8TS U4790 ( .A(n2828), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(
n3432) );
INVX2TS U4791 ( .A(n3432), .Y(n2829) );
INVX2TS U4792 ( .A(n2832), .Y(n2833) );
AOI21X4TS U4793 ( .A0(n3095), .A1(n2834), .B0(n2833), .Y(n2839) );
INVX2TS U4794 ( .A(n2835), .Y(n2837) );
XOR2X4TS U4795 ( .A(n2839), .B(n2838), .Y(n4024) );
INVX2TS U4796 ( .A(n3741), .Y(n3081) );
INVX2TS U4797 ( .A(n3055), .Y(n2842) );
BUFX3TS U4798 ( .A(n2841), .Y(n3057) );
INVX2TS U4799 ( .A(n3054), .Y(n2843) );
AOI21X4TS U4800 ( .A0(n3056), .A1(n2845), .B0(n2844), .Y(n2850) );
INVX2TS U4801 ( .A(n2846), .Y(n2848) );
XOR2X4TS U4802 ( .A(n2850), .B(n2849), .Y(n3071) );
NOR2X4TS U4803 ( .A(n3071), .B(n3070), .Y(n3997) );
XNOR2X4TS U4804 ( .A(n2866), .B(n2852), .Y(n3073) );
INVX2TS U4805 ( .A(n2853), .Y(n2854) );
AOI21X4TS U4806 ( .A0(n2866), .A1(n2855), .B0(n2854), .Y(n2860) );
INVX2TS U4807 ( .A(n2856), .Y(n2858) );
XOR2X4TS U4808 ( .A(n2860), .B(n2859), .Y(n3074) );
XNOR2X4TS U4809 ( .A(n2873), .B(n2863), .Y(n4013) );
AO21X4TS U4810 ( .A0(n2866), .A1(n2865), .B0(n2864), .Y(n2871) );
INVX2TS U4811 ( .A(n2867), .Y(n2869) );
XOR2X4TS U4812 ( .A(n2871), .B(n2870), .Y(n3075) );
XOR2X4TS U4813 ( .A(n2877), .B(n2876), .Y(n4017) );
INVX2TS U4814 ( .A(n2878), .Y(n3000) );
NAND2X1TS U4815 ( .A(n2431), .B(n2879), .Y(n2880) );
NOR2X2TS U4816 ( .A(n2990), .B(n4046), .Y(n6168) );
NAND2X1TS U4817 ( .A(n2884), .B(n2883), .Y(n2886) );
XNOR2X4TS U4818 ( .A(n2890), .B(n2889), .Y(n4044) );
NOR2X1TS U4819 ( .A(n6168), .B(n6166), .Y(n2992) );
INVX2TS U4820 ( .A(n2910), .Y(n2891) );
NAND2X2TS U4821 ( .A(n2891), .B(n2909), .Y(n2892) );
XNOR2X4TS U4822 ( .A(n2937), .B(n2892), .Y(n4012) );
INVX2TS U4823 ( .A(n2893), .Y(n2895) );
NAND2X1TS U4824 ( .A(n2895), .B(n2894), .Y(n2897) );
XOR2X1TS U4825 ( .A(n2897), .B(n2896), .Y(n2907) );
OAI21X4TS U4826 ( .A0(n4029), .A1(n4025), .B0(n4026), .Y(n2903) );
INVX2TS U4827 ( .A(n2899), .Y(n2901) );
XNOR2X4TS U4828 ( .A(n2903), .B(n2902), .Y(n6137) );
NAND2X1TS U4829 ( .A(n2905), .B(n2904), .Y(n2906) );
XNOR2X1TS U4830 ( .A(n2906), .B(n2658), .Y(n6136) );
NAND2X1TS U4831 ( .A(n6137), .B(n6136), .Y(n6138) );
INVX2TS U4832 ( .A(n6138), .Y(n6108) );
NAND2X1TS U4833 ( .A(n4012), .B(n2907), .Y(n6107) );
INVX2TS U4834 ( .A(n6107), .Y(n2908) );
OA21X4TS U4835 ( .A0(n2911), .A1(n2910), .B0(n2909), .Y(n2916) );
INVX2TS U4836 ( .A(n2912), .Y(n2914) );
NAND2X1TS U4837 ( .A(n2425), .B(n2917), .Y(n2918) );
XNOR2X1TS U4838 ( .A(n2919), .B(n2918), .Y(n2920) );
NOR2X1TS U4839 ( .A(n4038), .B(n2920), .Y(n6130) );
NAND2X1TS U4840 ( .A(n4038), .B(n2920), .Y(n6131) );
INVX2TS U4841 ( .A(n2934), .Y(n2921) );
XOR2X4TS U4842 ( .A(n2923), .B(n2922), .Y(n4037) );
INVX2TS U4843 ( .A(n2924), .Y(n2926) );
NAND2X1TS U4844 ( .A(n2926), .B(n2925), .Y(n2927) );
XOR2X1TS U4845 ( .A(n2928), .B(n2927), .Y(n2947) );
NOR2X2TS U4846 ( .A(n4037), .B(n2947), .Y(n6120) );
INVX2TS U4847 ( .A(n2929), .Y(n2930) );
INVX2TS U4848 ( .A(n2931), .Y(n2933) );
AOI21X2TS U4849 ( .A0(n2937), .A1(n2936), .B0(n2935), .Y(n2942) );
INVX2TS U4850 ( .A(n2938), .Y(n2940) );
XOR2X4TS U4851 ( .A(n2942), .B(n2941), .Y(n4040) );
NAND2X1TS U4852 ( .A(n2944), .B(n2943), .Y(n2945) );
XNOR2X1TS U4853 ( .A(n2946), .B(n2945), .Y(n2948) );
NOR2X2TS U4854 ( .A(n4040), .B(n2948), .Y(n6122) );
NAND2X1TS U4855 ( .A(n4037), .B(n2947), .Y(n6119) );
NAND2X1TS U4856 ( .A(n4040), .B(n2948), .Y(n6123) );
OAI21X1TS U4857 ( .A0(n6122), .A1(n6119), .B0(n6123), .Y(n2949) );
INVX2TS U4858 ( .A(n2962), .Y(n2952) );
AOI21X4TS U4859 ( .A0(n2973), .A1(n2963), .B0(n2952), .Y(n2957) );
INVX2TS U4860 ( .A(n2953), .Y(n2955) );
XOR2X4TS U4861 ( .A(n2957), .B(n2956), .Y(n4042) );
NAND2X1TS U4862 ( .A(n2959), .B(n2958), .Y(n2960) );
XNOR2X1TS U4863 ( .A(n2961), .B(n2960), .Y(n2983) );
NOR2X2TS U4864 ( .A(n4042), .B(n2983), .Y(n6148) );
NAND2X2TS U4865 ( .A(n2963), .B(n2962), .Y(n2964) );
INVX2TS U4866 ( .A(n2966), .Y(n2968) );
NAND2X1TS U4867 ( .A(n2968), .B(n2967), .Y(n2969) );
XOR2X1TS U4868 ( .A(n2970), .B(n2969), .Y(n2982) );
NOR2X1TS U4869 ( .A(n4041), .B(n2982), .Y(n6112) );
NOR2X1TS U4870 ( .A(n6148), .B(n6112), .Y(n6155) );
AO21X4TS U4871 ( .A0(n2973), .A1(n2972), .B0(n2971), .Y(n2976) );
XNOR2X4TS U4872 ( .A(n2976), .B(n2975), .Y(n4047) );
INVX2TS U4873 ( .A(n2977), .Y(n2979) );
NAND2X1TS U4874 ( .A(n6155), .B(n2233), .Y(n2988) );
NAND2X1TS U4875 ( .A(n4041), .B(n2982), .Y(n6145) );
NAND2X1TS U4876 ( .A(n4042), .B(n2983), .Y(n6149) );
OAI21X1TS U4877 ( .A0(n6148), .A1(n6145), .B0(n6149), .Y(n6154) );
NAND2X1TS U4878 ( .A(n2985), .B(n2984), .Y(n6157) );
INVX2TS U4879 ( .A(n6157), .Y(n2986) );
AOI21X1TS U4880 ( .A0(n6154), .A1(n2233), .B0(n2986), .Y(n2987) );
OAI21X2TS U4881 ( .A0(n6111), .A1(n2988), .B0(n2987), .Y(n6161) );
NAND2X1TS U4882 ( .A(n2990), .B(n4046), .Y(n6169) );
NAND2X1TS U4883 ( .A(n2994), .B(n2993), .Y(n2996) );
NAND2X1TS U4884 ( .A(n3002), .B(n3001), .Y(n3003) );
XNOR2X4TS U4885 ( .A(n3005), .B(n2585), .Y(n4014) );
NOR2X2TS U4886 ( .A(n3008), .B(n4014), .Y(n3007) );
INVX2TS U4887 ( .A(n3007), .Y(n6177) );
NAND2X2TS U4888 ( .A(n3008), .B(n4014), .Y(n6178) );
INVX2TS U4889 ( .A(n6178), .Y(n5803) );
NAND2X1TS U4890 ( .A(n3010), .B(n3009), .Y(n5804) );
INVX2TS U4891 ( .A(n5804), .Y(n3011) );
AOI21X2TS U4892 ( .A0(n2998), .A1(n5803), .B0(n3011), .Y(n3012) );
OAI21X4TS U4893 ( .A0(n5802), .A1(n3013), .B0(n3012), .Y(n5786) );
NAND2X1TS U4894 ( .A(n3017), .B(n3016), .Y(n3018) );
NOR2X4TS U4895 ( .A(n3024), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[1]),
.Y(n5787) );
NAND2X1TS U4896 ( .A(n3020), .B(n2238), .Y(n3022) );
XNOR2X2TS U4897 ( .A(n3022), .B(n3021), .Y(n3023) );
NAND2X2TS U4898 ( .A(n3023), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[0]),
.Y(n5796) );
OAI21X2TS U4899 ( .A0(n5787), .A1(n5796), .B0(n5788), .Y(n3025) );
AOI21X4TS U4900 ( .A0(n5786), .A1(n3026), .B0(n3025), .Y(n5769) );
INVX2TS U4901 ( .A(n3028), .Y(n3030) );
XNOR2X4TS U4902 ( .A(n3032), .B(n3031), .Y(n3040) );
NOR2X2TS U4903 ( .A(n3040), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[3]),
.Y(n3033) );
INVX4TS U4904 ( .A(n3033), .Y(n5772) );
INVX2TS U4905 ( .A(n3034), .Y(n3036) );
NAND2X2TS U4906 ( .A(n3036), .B(n3035), .Y(n3037) );
NAND2X2TS U4907 ( .A(n5772), .B(n2239), .Y(n3043) );
NAND2X2TS U4908 ( .A(n3039), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[2]),
.Y(n5782) );
INVX2TS U4909 ( .A(n5782), .Y(n5770) );
NAND2X2TS U4910 ( .A(n3040), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[3]),
.Y(n5771) );
INVX2TS U4911 ( .A(n5771), .Y(n3041) );
OAI21X4TS U4912 ( .A0(n5769), .A1(n3043), .B0(n3042), .Y(n3416) );
INVX2TS U4913 ( .A(n3052), .Y(n3045) );
AOI21X4TS U4914 ( .A0(n3056), .A1(n3051), .B0(n3045), .Y(n3050) );
INVX2TS U4915 ( .A(n3046), .Y(n3048) );
NAND2X2TS U4916 ( .A(n3048), .B(n3047), .Y(n3049) );
XOR2X4TS U4917 ( .A(n3050), .B(n3049), .Y(n3063) );
XNOR2X4TS U4918 ( .A(n3056), .B(n3053), .Y(n3062) );
NOR2X4TS U4919 ( .A(n3062), .B(FPMULT_inst_RecursiveKOA_EVEN1_Q_left[4]),
.Y(n3417) );
INVX4TS U4920 ( .A(n3417), .Y(n5763) );
NAND2X4TS U4921 ( .A(n2440), .B(n5763), .Y(n3424) );
AOI21X2TS U4922 ( .A0(n3056), .A1(n3055), .B0(n3054), .Y(n3061) );
INVX2TS U4923 ( .A(n3057), .Y(n3059) );
XOR2X4TS U4924 ( .A(n3061), .B(n3060), .Y(n3067) );
NOR2X6TS U4925 ( .A(n3067), .B(n3066), .Y(n3425) );
NOR2X4TS U4926 ( .A(n3424), .B(n3425), .Y(n3069) );
INVX2TS U4927 ( .A(n5762), .Y(n3065) );
AOI21X4TS U4928 ( .A0(n2440), .A1(n3065), .B0(n3064), .Y(n3423) );
NAND2X2TS U4929 ( .A(n3067), .B(n3066), .Y(n3426) );
OAI21X4TS U4930 ( .A0(n3423), .A1(n3425), .B0(n3426), .Y(n3068) );
AOI21X4TS U4931 ( .A0(n3416), .A1(n3069), .B0(n3068), .Y(n3988) );
OAI21X4TS U4932 ( .A0(n3999), .A1(n4409), .B0(n4000), .Y(n4004) );
OAI21X4TS U4933 ( .A0(n4007), .A1(n3992), .B0(n3993), .Y(n3076) );
AOI21X4TS U4934 ( .A0(n4004), .A1(n3077), .B0(n3076), .Y(n3078) );
OAI21X4TS U4935 ( .A0(n3079), .A1(n3988), .B0(n3078), .Y(n3080) );
BUFX20TS U4936 ( .A(n3080), .Y(n3982) );
AO21X4TS U4937 ( .A0(n3983), .A1(n3980), .B0(n3085), .Y(n3974) );
INVX2TS U4938 ( .A(n3433), .Y(n3091) );
NOR2X2TS U4939 ( .A(n3091), .B(n3432), .Y(n3094) );
INVX2TS U4940 ( .A(n3438), .Y(n3092) );
NAND2X4TS U4941 ( .A(n3096), .B(n3100), .Y(n3456) );
INVX2TS U4942 ( .A(n3456), .Y(n3102) );
AOI21X4TS U4943 ( .A0(n3100), .A1(n3099), .B0(n3098), .Y(n3463) );
INVX2TS U4944 ( .A(n3463), .Y(n3101) );
AOI21X4TS U4945 ( .A0(n3466), .A1(n3102), .B0(n3101), .Y(n3108) );
INVX2TS U4946 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(
n3445) );
CMPR32X2TS U4947 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]), .B(
n3648), .C(n3103), .CO(n3104), .S(n2825) );
INVX2TS U4948 ( .A(n3455), .Y(n3106) );
NAND2X2TS U4949 ( .A(n3105), .B(n3104), .Y(n3458) );
XOR2X4TS U4950 ( .A(n3108), .B(n3107), .Y(n3109) );
NOR2X8TS U4951 ( .A(n3109), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(
n3436) );
INVX2TS U4952 ( .A(n3436), .Y(n3110) );
NAND2X4TS U4953 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .B(
n3109), .Y(n3434) );
XNOR2X2TS U4954 ( .A(n3120), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(
n3119) );
INVX2TS U4955 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(
n3118) );
NOR2X4TS U4956 ( .A(n3119), .B(n3118), .Y(n3843) );
INVX2TS U4957 ( .A(n3114), .Y(n3115) );
NAND2X2TS U4958 ( .A(n3119), .B(n3118), .Y(n3844) );
INVX2TS U4959 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(
n3849) );
INVX2TS U4960 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .Y(
n3848) );
NOR2X4TS U4961 ( .A(n3122), .B(n3121), .Y(n3956) );
INVX2TS U4962 ( .A(n3956), .Y(n3123) );
NAND2X2TS U4963 ( .A(n3122), .B(n3121), .Y(n3955) );
NAND2X2TS U4964 ( .A(n3123), .B(n3955), .Y(n3124) );
XOR2X2TS U4965 ( .A(n3957), .B(n3124), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
NOR2X2TS U4966 ( .A(DP_OP_501J1_127_1459_n781), .B(n3205), .Y(n3127) );
NAND2X4TS U4967 ( .A(DP_OP_501J1_127_1459_n931), .B(n4818), .Y(n3204) );
AOI21X4TS U4968 ( .A0(DP_OP_501J1_127_1459_n790), .A1(n3127), .B0(n3126),
.Y(n3214) );
INVX2TS U4969 ( .A(n3222), .Y(n3128) );
AOI21X4TS U4970 ( .A0(n3223), .A1(n3219), .B0(n3128), .Y(n3129) );
OAI21X4TS U4971 ( .A0(n3130), .A1(n3214), .B0(n3129), .Y(n3728) );
INVX2TS U4972 ( .A(FPMULT_Op_MX[18]), .Y(n3131) );
NAND2X2TS U4973 ( .A(FPMULT_Op_MX[6]), .B(n5528), .Y(n3725) );
INVX2TS U4974 ( .A(n3725), .Y(n3132) );
AOI21X4TS U4975 ( .A0(n3728), .A1(n3726), .B0(n3132), .Y(n3133) );
OR2X4TS U4976 ( .A(n2275), .B(n3135), .Y(n3158) );
AND2X4TS U4977 ( .A(n6627), .B(DP_OP_501J1_127_1459_n794), .Y(n4310) );
ADDHX1TS U4978 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .CO(n3793), .S(
n3792) );
NOR2X2TS U4979 ( .A(n4310), .B(n3792), .Y(n3156) );
INVX2TS U4980 ( .A(n3156), .Y(n3164) );
NAND2X2TS U4981 ( .A(n3158), .B(n3164), .Y(n3139) );
INVX2TS U4982 ( .A(n3163), .Y(n3137) );
NAND2X2TS U4983 ( .A(n2275), .B(n3135), .Y(n3157) );
INVX2TS U4984 ( .A(n3157), .Y(n3136) );
AOI21X2TS U4985 ( .A0(n3158), .A1(n3137), .B0(n3136), .Y(n3138) );
OAI21X4TS U4986 ( .A0(n4228), .A1(n3139), .B0(n3138), .Y(n3213) );
INVX2TS U4987 ( .A(n3205), .Y(n3140) );
NOR2X4TS U4988 ( .A(n3142), .B(n3665), .Y(n4100) );
INVX2TS U4989 ( .A(n4100), .Y(n3143) );
NAND2X2TS U4990 ( .A(n3143), .B(n4099), .Y(n3144) );
INVX6TS U4991 ( .A(n6886), .Y(n6450) );
INVX6TS U4992 ( .A(n6857), .Y(n6439) );
OR2X4TS U4993 ( .A(n6450), .B(n6439), .Y(n3237) );
NOR2X4TS U4994 ( .A(n2273), .B(n6438), .Y(n3167) );
OAI21X4TS U4995 ( .A0(n3170), .A1(n3167), .B0(n3168), .Y(n3177) );
NOR2X4TS U4996 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .Y(n3622) );
NOR2X8TS U4997 ( .A(n6447), .B(FPMULT_Op_MY[2]), .Y(n3620) );
NAND2X2TS U4998 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n3619) );
OAI21X2TS U4999 ( .A0(n3622), .A1(n3619), .B0(n3623), .Y(n3146) );
AOI21X4TS U5000 ( .A0(n3177), .A1(n3147), .B0(n3146), .Y(n3230) );
NAND2X2TS U5001 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n3231) );
INVX2TS U5002 ( .A(n3231), .Y(n3233) );
NAND2X2TS U5003 ( .A(n6450), .B(n6439), .Y(n3236) );
INVX2TS U5004 ( .A(n3236), .Y(n3148) );
OAI21X4TS U5005 ( .A0(n3150), .A1(n3230), .B0(n3149), .Y(n3737) );
OR2X2TS U5006 ( .A(n6437), .B(DP_OP_501J1_127_1459_n910), .Y(n3735) );
INVX2TS U5007 ( .A(n3734), .Y(n3151) );
AOI21X4TS U5008 ( .A0(n3737), .A1(n3735), .B0(n3151), .Y(n3152) );
NOR2X1TS U5009 ( .A(n2334), .B(n4214), .Y(n3176) );
NAND2X1TS U5010 ( .A(n3153), .B(n3170), .Y(n3154) );
INVX2TS U5011 ( .A(n3154), .Y(n3681) );
INVX2TS U5012 ( .A(n3155), .Y(n4111) );
ADDHXLTS U5013 ( .A(n3161), .B(n3681), .CO(n3162), .S(n3155) );
INVX2TS U5014 ( .A(n3162), .Y(n4260) );
OAI22X1TS U5015 ( .A0(n2333), .A1(n4111), .B0(n2330), .B1(n4260), .Y(n3175)
);
NAND2X2TS U5016 ( .A(n3164), .B(n3163), .Y(n3165) );
ADDHXLTS U5017 ( .A(n6641), .B(n2305), .CO(n3180), .S(n3161) );
INVX2TS U5018 ( .A(n3167), .Y(n3169) );
NOR2X1TS U5019 ( .A(n4231), .B(n4219), .Y(n3185) );
NOR2X1TS U5020 ( .A(n2329), .B(n4214), .Y(n3184) );
CMPR32X2TS U5021 ( .A(n3176), .B(n3175), .C(n3174), .CO(n3190), .S(n3187) );
INVX6TS U5022 ( .A(n3177), .Y(n3621) );
INVX2TS U5023 ( .A(n3620), .Y(n3178) );
CLKXOR2X2TS U5024 ( .A(n3621), .B(n3179), .Y(n4294) );
ADDHX1TS U5025 ( .A(n3182), .B(n3674), .CO(n3183), .S(n3172) );
OAI22X1TS U5026 ( .A0(n2330), .A1(n4219), .B0(n2377), .B1(n4276), .Y(n4273)
);
NOR2X1TS U5027 ( .A(n2377), .B(n4214), .Y(n4177) );
NOR2X1TS U5028 ( .A(n2377), .B(n4111), .Y(n4176) );
NAND2X1TS U5029 ( .A(n4177), .B(n4176), .Y(n4178) );
INVX2TS U5030 ( .A(n4178), .Y(n4089) );
OAI22X1TS U5031 ( .A0(n2330), .A1(n4111), .B0(n2377), .B1(n4260), .Y(n4088)
);
ADDHX1TS U5032 ( .A(n3185), .B(n3184), .CO(n3174), .S(n4087) );
INVX2TS U5033 ( .A(n4085), .Y(n3189) );
NAND2X1TS U5034 ( .A(n3187), .B(n3186), .Y(n4084) );
INVX2TS U5035 ( .A(n4084), .Y(n3188) );
INVX2TS U5036 ( .A(n4081), .Y(n3191) );
AOI21X4TS U5037 ( .A0(n3173), .A1(n4082), .B0(n3191), .Y(n4079) );
NOR2X2TS U5038 ( .A(DP_OP_501J1_127_1459_n190), .B(DP_OP_501J1_127_1459_n196), .Y(n4076) );
OAI21X4TS U5039 ( .A0(n4079), .A1(n4076), .B0(n4077), .Y(n4075) );
AOI21X4TS U5040 ( .A0(n4075), .A1(n4073), .B0(n3192), .Y(n4070) );
NOR2X2TS U5041 ( .A(DP_OP_501J1_127_1459_n172), .B(DP_OP_501J1_127_1459_n181), .Y(n4067) );
NAND2X2TS U5042 ( .A(DP_OP_501J1_127_1459_n172), .B(
DP_OP_501J1_127_1459_n181), .Y(n4068) );
OAI21X4TS U5043 ( .A0(n4070), .A1(n4067), .B0(n4068), .Y(n4056) );
NOR2X4TS U5044 ( .A(DP_OP_501J1_127_1459_n153), .B(DP_OP_501J1_127_1459_n162), .Y(n4057) );
NAND2X2TS U5045 ( .A(DP_OP_501J1_127_1459_n163), .B(
DP_OP_501J1_127_1459_n171), .Y(n4063) );
NAND2X2TS U5046 ( .A(DP_OP_501J1_127_1459_n153), .B(
DP_OP_501J1_127_1459_n162), .Y(n4058) );
AOI21X4TS U5047 ( .A0(n4056), .A1(n3194), .B0(n3193), .Y(n3722) );
NAND2X2TS U5048 ( .A(DP_OP_501J1_127_1459_n145), .B(
DP_OP_501J1_127_1459_n152), .Y(n4053) );
NOR2X4TS U5049 ( .A(DP_OP_501J1_127_1459_n139), .B(DP_OP_501J1_127_1459_n144), .Y(n3199) );
INVX2TS U5050 ( .A(n3199), .Y(n3195) );
NAND2X2TS U5051 ( .A(DP_OP_501J1_127_1459_n139), .B(
DP_OP_501J1_127_1459_n144), .Y(n3198) );
NAND2X1TS U5052 ( .A(n3195), .B(n3198), .Y(n3196) );
INVX2TS U5053 ( .A(n4192), .Y(n3201) );
OAI21X4TS U5054 ( .A0(n3199), .A1(n4053), .B0(n3198), .Y(n4203) );
INVX2TS U5055 ( .A(n4203), .Y(n3200) );
NOR2X4TS U5056 ( .A(DP_OP_501J1_127_1459_n138), .B(DP_OP_501J1_127_1459_n134), .Y(n4191) );
INVX2TS U5057 ( .A(n4191), .Y(n3597) );
NAND2X2TS U5058 ( .A(DP_OP_501J1_127_1459_n138), .B(
DP_OP_501J1_127_1459_n134), .Y(n4199) );
XNOR2X2TS U5059 ( .A(n3203), .B(n3202), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11) );
NOR2X4TS U5060 ( .A(n3210), .B(n3209), .Y(n4102) );
NOR2X2TS U5061 ( .A(n4102), .B(n4100), .Y(n3212) );
NAND2X2TS U5062 ( .A(n3210), .B(n3209), .Y(n4103) );
AOI21X4TS U5063 ( .A0(n3213), .A1(n3212), .B0(n3211), .Y(n4094) );
NAND2X2TS U5064 ( .A(n3221), .B(n3215), .Y(n3216) );
XNOR2X4TS U5065 ( .A(n3220), .B(n3216), .Y(n3675) );
XNOR2X4TS U5066 ( .A(n3675), .B(n6455), .Y(n3218) );
OAI21X4TS U5067 ( .A0(n4094), .A1(n3724), .B0(n3730), .Y(n3229) );
INVX2TS U5068 ( .A(n3731), .Y(n3227) );
NAND2X2TS U5069 ( .A(n3673), .B(n3226), .Y(n3729) );
NAND2X2TS U5070 ( .A(n3234), .B(n3231), .Y(n3232) );
XNOR2X4TS U5071 ( .A(n3235), .B(n3232), .Y(n4299) );
OR2X2TS U5072 ( .A(n4299), .B(FPMULT_Op_MY[11]), .Y(n3243) );
NAND2X1TS U5073 ( .A(n3237), .B(n3236), .Y(n3238) );
INVX2TS U5074 ( .A(n3724), .Y(n3241) );
NAND2X2TS U5075 ( .A(n3241), .B(n3730), .Y(n3242) );
INVX4TS U5076 ( .A(n3244), .Y(n4278) );
OAI211X4TS U5077 ( .A0(n6842), .A1(n6874), .B0(n6873), .C0(n6872), .Y(n6544)
);
OAI211X4TS U5078 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n2393), .B0(n3298),
.C0(n3245), .Y(n3292) );
OAI21X1TS U5079 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n2433), .B0(n3289), .Y(
n3293) );
NOR2X1TS U5080 ( .A(n2394), .B(FPADDSUB_intDX_EWSW[17]), .Y(n3287) );
AOI21X1TS U5081 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3248), .B0(n3269), .Y(
n3274) );
INVX2TS U5082 ( .A(FPADDSUB_intDX_EWSW[5]), .Y(n3255) );
OAI2BB1X1TS U5083 ( .A0N(n3255), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n3249) );
OAI22X1TS U5084 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3249), .B0(n3255), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n3266) );
INVX2TS U5085 ( .A(FPADDSUB_intDX_EWSW[7]), .Y(n3262) );
OAI2BB1X1TS U5086 ( .A0N(n3262), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n3250) );
OAI2BB2XLTS U5087 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n3252), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n6715), .Y(n3254) );
AOI22X1TS U5088 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3262), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n3261), .Y(n3263) );
OAI2BB2XLTS U5089 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n3268), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n2434), .Y(n3280) );
AOI22X1TS U5090 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n2388), .B0(n6284), .B1(
n3270), .Y(n3276) );
AOI21X1TS U5091 ( .A0(n3273), .A1(n3272), .B0(n3283), .Y(n3275) );
OAI31X1TS U5092 ( .A0(n3285), .A1(n3284), .A2(n3283), .B0(n3282), .Y(n3300)
);
AOI22X1TS U5093 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n2394), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n3288), .Y(n3291) );
OAI32X1TS U5094 ( .A0(n3293), .A1(n3292), .A2(n3291), .B0(n3290), .B1(n3292),
.Y(n3296) );
AOI211X1TS U5095 ( .A0(n3298), .A1(n3297), .B0(n3296), .C0(n3295), .Y(n3299)
);
OAI21X1TS U5096 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n2411), .B0(n3308), .Y(
n3311) );
NOR2X1TS U5097 ( .A(n2409), .B(FPADDSUB_intDX_EWSW[25]), .Y(n3306) );
OAI211X1TS U5098 ( .A0(n6842), .A1(n6877), .B0(n6876), .C0(n6875), .Y(n6291)
);
INVX2TS U5099 ( .A(n6291), .Y(n3314) );
NOR2X1TS U5100 ( .A(n2399), .B(FPADDSUB_intDX_EWSW[29]), .Y(n3313) );
NAND4BBX1TS U5101 ( .AN(n3311), .BN(n3306), .C(n3318), .D(n3302), .Y(n3303)
);
AOI22X1TS U5102 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n2409), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n3307), .Y(n3312) );
OAI211X1TS U5103 ( .A0(n3312), .A1(n3311), .B0(n3310), .C0(n3309), .Y(n3319)
);
NOR3X1TS U5104 ( .A(n3314), .B(n3313), .C(FPADDSUB_intDY_EWSW[28]), .Y(n3315) );
BUFX3TS U5105 ( .A(n4402), .Y(n5292) );
BUFX3TS U5106 ( .A(n6639), .Y(n5299) );
AOI22X1TS U5107 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n5299), .Y(n3322) );
BUFX3TS U5108 ( .A(n6611), .Y(n6618) );
OAI31X1TS U5109 ( .A0(n6649), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .A2(
FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n6696), .Y(n3324) );
NOR2X1TS U5110 ( .A(FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3325) );
AOI21X1TS U5111 ( .A0(n3324), .A1(n3327), .B0(n3323), .Y(n3342) );
NOR2X1TS U5112 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3326) );
NOR3X1TS U5113 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n3331) );
INVX2TS U5114 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .Y(n3404) );
NOR4X1TS U5115 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(n6635), .D(n4646), .Y(n3330) );
INVX2TS U5116 ( .A(n4862), .Y(n3329) );
INVX2TS U5117 ( .A(n3327), .Y(n3328) );
NOR2X2TS U5118 ( .A(n3328), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4863) );
INVX2TS U5119 ( .A(n3351), .Y(n3337) );
NAND2X4TS U5120 ( .A(n3344), .B(n2248), .Y(n4672) );
NOR2BX4TS U5121 ( .AN(n3331), .B(n4672), .Y(n3338) );
INVX2TS U5122 ( .A(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4648) );
OAI32X4TS U5123 ( .A0(n3348), .A1(FPADDSUB_Raw_mant_NRM_SWR[2]), .A2(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n4669), .B1(n3348), .Y(n4668) );
OA21X4TS U5124 ( .A0(n4645), .A1(n4668), .B0(n3335), .Y(n3336) );
NAND2X1TS U5125 ( .A(n3338), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n3339) );
NOR2X1TS U5126 ( .A(n4869), .B(n2441), .Y(n3361) );
OAI211X4TS U5127 ( .A0(n5885), .A1(FPADDSUB_Shift_amount_SHT1_EWR[1]), .B0(
n5884), .C0(n2210), .Y(n3366) );
INVX2TS U5128 ( .A(n3359), .Y(n6391) );
NOR3X1TS U5129 ( .A(n4672), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .C(n5212),
.Y(n3343) );
AOI21X1TS U5130 ( .A0(n3344), .A1(FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n3343),
.Y(n3347) );
AOI21X1TS U5131 ( .A0(n6703), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n3345) );
OA22X1TS U5132 ( .A0(n3347), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n3346), .Y(n3356) );
NOR2X2TS U5133 ( .A(n3348), .B(n4645), .Y(n4867) );
OAI21X1TS U5134 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[4]), .A1(n6648), .B0(n6695),
.Y(n4866) );
NOR3BX2TS U5135 ( .AN(n4867), .B(n3349), .C(n4866), .Y(n3350) );
AOI211X2TS U5136 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n3352), .B0(n3351), .C0(n3350), .Y(n4859) );
OAI21X1TS U5137 ( .A0(n3354), .A1(FPADDSUB_Raw_mant_NRM_SWR[8]), .B0(n3353),
.Y(n3355) );
AOI31X2TS U5138 ( .A0(n3356), .A1(n4859), .A2(n3355), .B0(n3333), .Y(n5886)
);
NAND2X4TS U5139 ( .A(n5271), .B(n2210), .Y(n3367) );
INVX4TS U5140 ( .A(n3367), .Y(n3369) );
NOR2X2TS U5141 ( .A(n3369), .B(n3359), .Y(n3360) );
BUFX3TS U5142 ( .A(n3361), .Y(n5213) );
NAND2X1TS U5143 ( .A(n5213), .B(n6735), .Y(n3365) );
INVX2TS U5144 ( .A(n3362), .Y(n3610) );
NAND2X1TS U5145 ( .A(n3610), .B(n2248), .Y(n3364) );
OR2X1TS U5146 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n3363) );
INVX2TS U5147 ( .A(n5225), .Y(n3389) );
AOI22X1TS U5148 ( .A0(n5201), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2353),
.B1(n3389), .Y(n3372) );
BUFX3TS U5149 ( .A(n5201), .Y(n5273) );
NOR2X4TS U5150 ( .A(n5273), .B(n3366), .Y(n5272) );
NAND2X2TS U5151 ( .A(n5272), .B(n3367), .Y(n3368) );
AOI222X4TS U5152 ( .A0(n6654), .A1(n3333), .B0(n6713), .B1(n3610), .C0(n6632), .C1(n5213), .Y(n5227) );
BUFX3TS U5153 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n5820) );
OAI22X1TS U5154 ( .A0(n3362), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(n5820),
.B1(FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n3370) );
AOI22X1TS U5155 ( .A0(n3612), .A1(n5227), .B0(n2354), .B1(n5226), .Y(n3371)
);
OAI22X1TS U5156 ( .A0(n3362), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(n5820),
.B1(FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n3373) );
AOI22X1TS U5157 ( .A0(n5201), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2349),
.B1(n5203), .Y(n3376) );
AOI22X1TS U5158 ( .A0(n5269), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[3]), .B1(n4869), .Y(n3374) );
AOI22X1TS U5159 ( .A0(n3612), .A1(n3389), .B0(n2353), .B1(n5200), .Y(n3375)
);
NAND2X1TS U5160 ( .A(n5213), .B(n2248), .Y(n3379) );
NAND2X1TS U5161 ( .A(n3610), .B(n6735), .Y(n3378) );
OR2X1TS U5162 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n3377) );
NAND3X1TS U5163 ( .A(n3379), .B(n3378), .C(n3377), .Y(n5219) );
NAND2X1TS U5164 ( .A(n5269), .B(n6693), .Y(n3382) );
NAND2X1TS U5165 ( .A(n4869), .B(n6776), .Y(n3380) );
AOI22X1TS U5166 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2355),
.B1(n5220), .Y(n3388) );
NAND2X1TS U5167 ( .A(n3610), .B(n6695), .Y(n3385) );
NAND2X1TS U5168 ( .A(n4869), .B(n6775), .Y(n3383) );
OAI22X1TS U5169 ( .A0(n2210), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(n5820),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n3386) );
AOI22X1TS U5170 ( .A0(n5281), .A1(n5207), .B0(n2349), .B1(n5280), .Y(n3387)
);
AOI22X1TS U5171 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n4405),
.B1(n5200), .Y(n3391) );
AOI22X1TS U5172 ( .A0(n5281), .A1(n5226), .B0(n2354), .B1(n3389), .Y(n3390)
);
OA22X1TS U5173 ( .A0(n3362), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(n5885),
.B1(FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n3392) );
AOI22X1TS U5174 ( .A0(n3610), .A1(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n6657), .Y(n3393) );
AOI22X1TS U5175 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2349),
.B1(n4403), .Y(n3395) );
AOI22X1TS U5176 ( .A0(n3612), .A1(n5200), .B0(n2355), .B1(n5203), .Y(n3394)
);
BUFX3TS U5177 ( .A(n5201), .Y(n5278) );
OAI2BB2X1TS U5178 ( .B0(n2210), .B1(n6647), .A0N(n3610), .A1N(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4404) );
AOI22X1TS U5179 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2349),
.B1(n4404), .Y(n3397) );
AOI22X1TS U5180 ( .A0(n5281), .A1(n5203), .B0(n2353), .B1(n4403), .Y(n3396)
);
AOI22X1TS U5181 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2355),
.B1(n5207), .Y(n3400) );
OAI22X1TS U5182 ( .A0(n2350), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(n5820),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n3398) );
AOI22X1TS U5183 ( .A0(n5281), .A1(n5208), .B0(n2353), .B1(n5220), .Y(n3399)
);
OAI22X1TS U5184 ( .A0(n2307), .A1(FPADDSUB_Raw_mant_NRM_SWR[14]), .B0(n5820),
.B1(FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n3401) );
AO21X1TS U5185 ( .A0(n5213), .A1(n6718), .B0(n3401), .Y(n5231) );
AOI222X4TS U5186 ( .A0(n6711), .A1(n3333), .B0(n6649), .B1(n5269), .C0(n6635), .C1(n5213), .Y(n5228) );
AOI22X1TS U5187 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n4405),
.B1(n5228), .Y(n3406) );
OAI22X1TS U5188 ( .A0(n5885), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n2210), .Y(n3402) );
OAI22X1TS U5189 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n3362), .B0(n5885),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n3403) );
AOI22X1TS U5190 ( .A0(n5281), .A1(n5245), .B0(n2355), .B1(n5244), .Y(n3405)
);
AOI22X1TS U5191 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2349),
.B1(n5227), .Y(n3408) );
AOI22X1TS U5192 ( .A0(n3612), .A1(n5244), .B0(n2353), .B1(n5228), .Y(n3407)
);
BUFX3TS U5193 ( .A(n6639), .Y(n6217) );
AOI22X1TS U5194 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n6217), .Y(n3409) );
AOI21X4TS U5195 ( .A0(n4022), .A1(n4020), .B0(n3410), .Y(n3414) );
NAND2X2TS U5196 ( .A(n3412), .B(n3411), .Y(n3413) );
XOR2X4TS U5197 ( .A(n3414), .B(n3413), .Y(n6129) );
NOR3X2TS U5198 ( .A(n6686), .B(FPMULT_FS_Module_state_reg[0]), .C(
FPMULT_FS_Module_state_reg[2]), .Y(n5312) );
NAND2X1TS U5199 ( .A(n2440), .B(n3418), .Y(n3419) );
BUFX3TS U5200 ( .A(n7026), .Y(n6181) );
OAI21X1TS U5201 ( .A0(n5765), .A1(n3424), .B0(n3423), .Y(n3429) );
INVX2TS U5202 ( .A(n3425), .Y(n3427) );
NAND2X1TS U5203 ( .A(n3427), .B(n3426), .Y(n3428) );
NOR2X8TS U5204 ( .A(n3432), .B(n3436), .Y(n3439) );
OAI21X4TS U5205 ( .A0(n3436), .A1(n3435), .B0(n3434), .Y(n3437) );
AOI21X4TS U5206 ( .A0(n3439), .A1(n3438), .B0(n3437), .Y(n3440) );
OAI21X4TS U5207 ( .A0(n3442), .A1(n3441), .B0(n3440), .Y(n3474) );
AOI21X4TS U5208 ( .A0(n3466), .A1(n3444), .B0(n3443), .Y(n3450) );
INVX2TS U5209 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(
n3467) );
INVX2TS U5210 ( .A(n3459), .Y(n3448) );
NAND2X2TS U5211 ( .A(n3447), .B(n3446), .Y(n3457) );
XOR2X4TS U5212 ( .A(n3450), .B(n3449), .Y(n3451) );
NOR2X4TS U5213 ( .A(n3451), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(
n3472) );
INVX4TS U5214 ( .A(n3472), .Y(n3484) );
NAND2X4TS U5215 ( .A(n3451), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(
n3482) );
XOR2X4TS U5216 ( .A(n3642), .B(n3452), .Y(n4045) );
NAND2X1TS U5217 ( .A(n4030), .B(n4045), .Y(n3454) );
NOR2X2TS U5218 ( .A(n3454), .B(n3453), .Y(n3710) );
OR2X4TS U5219 ( .A(n3455), .B(n3459), .Y(n3462) );
OAI21X2TS U5220 ( .A0(n3459), .A1(n3458), .B0(n3457), .Y(n3460) );
INVX2TS U5221 ( .A(n3460), .Y(n3461) );
AOI21X4TS U5222 ( .A0(n3466), .A1(n3465), .B0(n3464), .Y(n3477) );
NOR2X2TS U5223 ( .A(n3469), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n3476) );
INVX2TS U5224 ( .A(n3476), .Y(n3470) );
NAND2X2TS U5225 ( .A(n3469), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n3475) );
NOR2X4TS U5226 ( .A(n3472), .B(n3485), .Y(n3636) );
NAND2X2TS U5227 ( .A(n3473), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(
n3486) );
OAI21X4TS U5228 ( .A0(n3485), .A1(n3482), .B0(n3486), .Y(n3641) );
AOI21X4TS U5229 ( .A0(n3474), .A1(n3636), .B0(n3641), .Y(n3496) );
OAI21X4TS U5230 ( .A0(n3477), .A1(n3476), .B0(n3475), .Y(n3478) );
XNOR2X4TS U5231 ( .A(n3478), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .Y(
n3479) );
INVX2TS U5232 ( .A(n3635), .Y(n3480) );
NAND2X4TS U5233 ( .A(n3479), .B(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(
n3638) );
XOR2X4TS U5234 ( .A(n3496), .B(n3481), .Y(n4043) );
INVX2TS U5235 ( .A(n3482), .Y(n3483) );
AOI21X4TS U5236 ( .A0(n3652), .A1(n3484), .B0(n3483), .Y(n3489) );
INVX2TS U5237 ( .A(n3485), .Y(n3487) );
XOR2X4TS U5238 ( .A(n3489), .B(n3488), .Y(n4032) );
NAND2X1TS U5239 ( .A(n4043), .B(n4032), .Y(n3644) );
INVX2TS U5240 ( .A(n3644), .Y(n3490) );
NOR2X4TS U5241 ( .A(n3711), .B(n3491), .Y(n3493) );
INVX2TS U5242 ( .A(n3705), .Y(n3495) );
AOI21X4TS U5243 ( .A0(n3974), .A1(n3493), .B0(n3492), .Y(n3706) );
OAI21X4TS U5244 ( .A0(n3496), .A1(n3635), .B0(n3638), .Y(n3497) );
INVX2TS U5245 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
n3637) );
XNOR2X4TS U5246 ( .A(n3497), .B(n3637), .Y(n4016) );
INVX2TS U5247 ( .A(FPADDSUB_bit_shift_SHT2), .Y(n4628) );
NOR2X2TS U5248 ( .A(n2301), .B(n4628), .Y(n4525) );
AOI21X2TS U5249 ( .A0(n2301), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n4525),
.Y(n5868) );
AOI22X1TS U5250 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2322), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2342), .Y(n3500) );
AOI22X1TS U5251 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2345), .Y(n3499) );
OAI211X1TS U5252 ( .A0(n5868), .A1(n6637), .B0(n3500), .C0(n3499), .Y(n5827)
);
AOI22X1TS U5253 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2300), .B0(
FPADDSUB_Data_array_SWR[22]), .B1(n4548), .Y(n3501) );
NAND2BX1TS U5254 ( .AN(n4552), .B(n3501), .Y(n5826) );
NAND2X2TS U5255 ( .A(n6637), .B(n5874), .Y(n5876) );
INVX2TS U5256 ( .A(n5876), .Y(n3522) );
AOI22X1TS U5257 ( .A0(n5827), .A1(n2351), .B0(n5826), .B1(n3522), .Y(n5863)
);
NAND2X2TS U5258 ( .A(n5874), .B(n5850), .Y(n6584) );
AND4X1TS U5259 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3502) );
XNOR2X2TS U5260 ( .A(DP_OP_26J1_129_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3512) );
INVX2TS U5261 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n3506) );
INVX2TS U5262 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n3505) );
NAND4BX1TS U5263 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n3507), .C(n3506),
.D(n3505), .Y(n3508) );
NOR2X1TS U5264 ( .A(n3508), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n3509) );
NOR2BX1TS U5265 ( .AN(n3509), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n3510)
);
AOI21X1TS U5266 ( .A0(n5863), .A1(n6584), .B0(n2309), .Y(n3513) );
AOI21X2TS U5267 ( .A0(n2301), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n4525),
.Y(n5877) );
AOI22X1TS U5268 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[15]), .B1(n2322), .Y(n3515) );
AOI22X1TS U5269 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n2342), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2344), .Y(n3514) );
OAI211X1TS U5270 ( .A0(n5877), .A1(n6637), .B0(n3515), .C0(n3514), .Y(n5830)
);
NAND2X1TS U5271 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n6666), .Y(n3521)
);
AOI22X1TS U5272 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[16]), .B1(n2301), .Y(n3516) );
AOI22X1TS U5273 ( .A0(n5830), .A1(n2351), .B0(n5829), .B1(n3522), .Y(n5859)
);
AOI21X1TS U5274 ( .A0(n5859), .A1(n6584), .B0(n2309), .Y(n3517) );
AOI21X2TS U5275 ( .A0(n2301), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n4525),
.Y(n4500) );
AOI22X1TS U5276 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2343), .Y(n3519) );
AOI22X1TS U5277 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2322), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2344), .Y(n3518) );
OAI211X1TS U5278 ( .A0(n4500), .A1(n6637), .B0(n3519), .C0(n3518), .Y(n5833)
);
AOI22X1TS U5279 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[15]), .B1(n2301), .Y(n3520) );
AOI22X1TS U5280 ( .A0(n5833), .A1(n2267), .B0(n5831), .B1(n3522), .Y(n5858)
);
AOI21X1TS U5281 ( .A0(n5858), .A1(n6584), .B0(n2309), .Y(n3523) );
OR2X2TS U5282 ( .A(FPMULT_FSM_selector_B[1]), .B(n6642), .Y(n5483) );
INVX2TS U5283 ( .A(n3527), .Y(n3981) );
NAND2X1TS U5284 ( .A(n3981), .B(n3528), .Y(n3529) );
XOR2X4TS U5285 ( .A(n2371), .B(n3529), .Y(n3531) );
NOR2X2TS U5286 ( .A(DP_OP_502J1_128_2852_n110), .B(DP_OP_502J1_128_2852_n116), .Y(n5354) );
NOR2X2TS U5287 ( .A(DP_OP_502J1_128_2852_n117), .B(DP_OP_502J1_128_2852_n122), .Y(n5359) );
NOR2X2TS U5288 ( .A(n6641), .B(n6438), .Y(n3535) );
INVX2TS U5289 ( .A(n3573), .Y(n3550) );
INVX2TS U5290 ( .A(n3567), .Y(n3532) );
INVX2TS U5291 ( .A(n3534), .Y(n5397) );
INVX2TS U5292 ( .A(n3535), .Y(n3537) );
ADDHXLTS U5293 ( .A(n6922), .B(FPMULT_Op_MX[7]), .CO(n3540), .S(n3534) );
INVX2TS U5294 ( .A(n3540), .Y(n5396) );
OAI22X1TS U5295 ( .A0(n2312), .A1(n5397), .B0(n2366), .B1(n5396), .Y(n3549)
);
INVX2TS U5296 ( .A(n3545), .Y(n5387) );
INVX2TS U5297 ( .A(n3543), .Y(n5392) );
INVX2TS U5298 ( .A(n3544), .Y(n5395) );
INVX2TS U5299 ( .A(n3545), .Y(n4625) );
ADDHXLTS U5300 ( .A(n4818), .B(n2277), .CO(n3546), .S(n3544) );
INVX2TS U5301 ( .A(n3546), .Y(n5393) );
OAI22X1TS U5302 ( .A0(n5394), .A1(n5395), .B0(n4625), .B1(n5393), .Y(n4424)
);
NOR2X1TS U5303 ( .A(n4625), .B(n5395), .Y(n3557) );
OAI22X1TS U5304 ( .A0(n5394), .A1(n5397), .B0(n5387), .B1(n5396), .Y(n3556)
);
NOR2X1TS U5305 ( .A(DP_OP_502J1_128_2852_n136), .B(n3563), .Y(n5372) );
OAI21X1TS U5306 ( .A0(n3550), .A1(n3567), .B0(n3569), .Y(n3553) );
NOR2X4TS U5307 ( .A(n6441), .B(FPMULT_Op_MY[3]), .Y(n3570) );
INVX2TS U5308 ( .A(n3570), .Y(n3551) );
NAND2X2TS U5309 ( .A(n6441), .B(FPMULT_Op_MY[3]), .Y(n3568) );
INVX2TS U5310 ( .A(n3554), .Y(n5401) );
ADDHXLTS U5311 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[0]), .CO(n3555), .S(
n3554) );
INVX2TS U5312 ( .A(n3555), .Y(n5399) );
OAI22X1TS U5313 ( .A0(n2382), .A1(n5401), .B0(n2312), .B1(n5399), .Y(n3561)
);
NOR2X1TS U5314 ( .A(n3562), .B(n3561), .Y(n5377) );
ADDHX1TS U5315 ( .A(n3557), .B(n3556), .CO(n3547), .S(n3559) );
OAI22X1TS U5316 ( .A0(n2311), .A1(n5401), .B0(n5394), .B1(n5399), .Y(n3558)
);
OR2X2TS U5317 ( .A(n3559), .B(n3558), .Y(n5383) );
OAI22X1TS U5318 ( .A0(n5394), .A1(n5401), .B0(n4625), .B1(n5399), .Y(n5324)
);
NOR2X1TS U5319 ( .A(n5387), .B(n5397), .Y(n5323) );
NAND2X1TS U5320 ( .A(n5324), .B(n5323), .Y(n5325) );
INVX2TS U5321 ( .A(n5325), .Y(n5384) );
NAND2X1TS U5322 ( .A(n3559), .B(n3558), .Y(n5382) );
INVX2TS U5323 ( .A(n5382), .Y(n3560) );
AOI21X1TS U5324 ( .A0(n5383), .A1(n5384), .B0(n3560), .Y(n5380) );
NAND2X1TS U5325 ( .A(n3562), .B(n3561), .Y(n5378) );
OA21X4TS U5326 ( .A0(n5377), .A1(n5380), .B0(n5378), .Y(n5375) );
NAND2X1TS U5327 ( .A(DP_OP_502J1_128_2852_n136), .B(n3563), .Y(n5373) );
OAI21X1TS U5328 ( .A0(n5372), .A1(n5375), .B0(n5373), .Y(n5370) );
NAND2X1TS U5329 ( .A(DP_OP_502J1_128_2852_n129), .B(
DP_OP_502J1_128_2852_n135), .Y(n5369) );
INVX2TS U5330 ( .A(n5369), .Y(n3564) );
AOI21X2TS U5331 ( .A0(n5370), .A1(n2446), .B0(n3564), .Y(n5367) );
NAND2X1TS U5332 ( .A(DP_OP_502J1_128_2852_n123), .B(
DP_OP_502J1_128_2852_n128), .Y(n5365) );
OAI21X2TS U5333 ( .A0(n5367), .A1(n5364), .B0(n5365), .Y(n5353) );
NAND2X2TS U5334 ( .A(DP_OP_502J1_128_2852_n117), .B(
DP_OP_502J1_128_2852_n122), .Y(n5360) );
NAND2X1TS U5335 ( .A(DP_OP_502J1_128_2852_n110), .B(
DP_OP_502J1_128_2852_n116), .Y(n5355) );
OAI21X1TS U5336 ( .A0(n5354), .A1(n5360), .B0(n5355), .Y(n3565) );
AOI21X4TS U5337 ( .A0(n3566), .A1(n5353), .B0(n3565), .Y(n5352) );
NOR2X2TS U5338 ( .A(n3570), .B(n3567), .Y(n3572) );
OAI21X1TS U5339 ( .A0(n3570), .A1(n3569), .B0(n3568), .Y(n3571) );
AOI21X4TS U5340 ( .A0(n3573), .A1(n3572), .B0(n3571), .Y(n4507) );
NOR2X2TS U5341 ( .A(n6442), .B(FPMULT_Op_MY[4]), .Y(n4503) );
NOR2X2TS U5342 ( .A(n2370), .B(n6439), .Y(n3577) );
NAND2X1TS U5343 ( .A(n2370), .B(n6439), .Y(n3578) );
INVX2TS U5344 ( .A(n3576), .Y(n5389) );
OAI21X1TS U5345 ( .A0(n4507), .A1(n4503), .B0(n4504), .Y(n3581) );
INVX2TS U5346 ( .A(n3577), .Y(n3579) );
NAND2X1TS U5347 ( .A(n3579), .B(n3578), .Y(n3580) );
CLKXOR2X4TS U5348 ( .A(n3581), .B(n3580), .Y(n5398) );
INVX2TS U5349 ( .A(n2445), .Y(n5491) );
INVX2TS U5350 ( .A(n3582), .Y(n5386) );
OAI22X1TS U5351 ( .A0(n2369), .A1(n5386), .B0(n2298), .B1(n5388), .Y(n3590)
);
NAND2X1TS U5352 ( .A(n5348), .B(n5343), .Y(n3587) );
NOR2X2TS U5353 ( .A(DP_OP_502J1_128_2852_n109), .B(DP_OP_502J1_128_2852_n105), .Y(n5346) );
NOR2X2TS U5354 ( .A(n3587), .B(n5346), .Y(n5081) );
INVX2TS U5355 ( .A(n5081), .Y(n3589) );
NAND2X2TS U5356 ( .A(DP_OP_502J1_128_2852_n109), .B(
DP_OP_502J1_128_2852_n105), .Y(n5349) );
NAND2X1TS U5357 ( .A(DP_OP_502J1_128_2852_n102), .B(
DP_OP_502J1_128_2852_n104), .Y(n5347) );
INVX2TS U5358 ( .A(n5347), .Y(n5338) );
NAND2X1TS U5359 ( .A(DP_OP_502J1_128_2852_n101), .B(n3584), .Y(n5342) );
INVX2TS U5360 ( .A(n5342), .Y(n3585) );
AOI21X1TS U5361 ( .A0(n5338), .A1(n5343), .B0(n3585), .Y(n3586) );
OAI21X1TS U5362 ( .A0(n3587), .A1(n5349), .B0(n3586), .Y(n5085) );
INVX2TS U5363 ( .A(n5085), .Y(n3588) );
CMPR32X2TS U5364 ( .A(n3591), .B(n3590), .C(DP_OP_502J1_128_2852_n100), .CO(
n3593), .S(n3584) );
NOR2X1TS U5365 ( .A(n2298), .B(n5386), .Y(n3592) );
NAND2X1TS U5366 ( .A(n3593), .B(n3592), .Y(n5082) );
NAND2X1TS U5367 ( .A(n5084), .B(n5082), .Y(n3594) );
NAND2X1TS U5368 ( .A(n4192), .B(n3597), .Y(n3599) );
INVX2TS U5369 ( .A(n4199), .Y(n3596) );
INVX2TS U5370 ( .A(n3718), .Y(n4190) );
XNOR2X2TS U5371 ( .A(n3601), .B(n3600), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12) );
NAND2X1TS U5372 ( .A(n5269), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n3604) );
NAND2X1TS U5373 ( .A(n4869), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n3602) );
INVX2TS U5374 ( .A(n6393), .Y(n3613) );
NAND2X1TS U5375 ( .A(n3610), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3608) );
NAND2X1TS U5376 ( .A(n3605), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3607) );
NAND2X1TS U5377 ( .A(n4869), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n3606) );
OAI22X1TS U5378 ( .A0(n2350), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(n5820),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n3609) );
AOI22X1TS U5379 ( .A0(n2354), .A1(n5274), .B0(n2353), .B1(n5232), .Y(n3611)
);
AOI22X1TS U5380 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n2349),
.B1(n5208), .Y(n3614) );
AOI22X1TS U5381 ( .A0(n2354), .A1(n5232), .B0(n2353), .B1(n5208), .Y(n3616)
);
AOI22X1TS U5382 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2349),
.B1(n5207), .Y(n3617) );
INVX2TS U5383 ( .A(n3622), .Y(n3624) );
XNOR2X4TS U5384 ( .A(n3626), .B(n3625), .Y(n3837) );
INVX4TS U5385 ( .A(n3630), .Y(n4267) );
INVX2TS U5386 ( .A(n4024), .Y(n3757) );
INVX2TS U5387 ( .A(n3976), .Y(n3631) );
AOI21X4TS U5388 ( .A0(n3974), .A1(n3977), .B0(n3631), .Y(n3754) );
AOI21X4TS U5389 ( .A0(n3641), .A1(n3640), .B0(n3639), .Y(n3649) );
OAI21X4TS U5390 ( .A0(n3642), .A1(n3647), .B0(n3649), .Y(n3643) );
XNOR2X4TS U5391 ( .A(n3643), .B(n3648), .Y(n4015) );
NAND2X1TS U5392 ( .A(n4016), .B(n4015), .Y(n3645) );
NOR2X4TS U5393 ( .A(n3711), .B(n3653), .Y(n3655) );
NAND2X2TS U5394 ( .A(n3975), .B(n3655), .Y(n3747) );
NOR2X4TS U5395 ( .A(n3647), .B(n3648), .Y(n3651) );
NOR2X4TS U5396 ( .A(n3649), .B(n3648), .Y(n3650) );
AOI21X4TS U5397 ( .A0(n3652), .A1(n3651), .B0(n3650), .Y(n3659) );
XOR2X4TS U5398 ( .A(n3659), .B(n3658), .Y(n4031) );
INVX2TS U5399 ( .A(n4031), .Y(n3751) );
NOR2X2TS U5400 ( .A(n3976), .B(n3653), .Y(n3654) );
INVX2TS U5401 ( .A(n3837), .Y(n4291) );
AOI22X1TS U5402 ( .A0(n2275), .A1(n4291), .B0(n3837), .B1(mult_x_313_n74),
.Y(n3662) );
INVX2TS U5403 ( .A(n4310), .Y(n4314) );
OAI32X1TS U5404 ( .A0(n4310), .A1(n4294), .A2(mult_x_313_n74), .B0(n3662),
.B1(n4314), .Y(n3686) );
INVX2TS U5405 ( .A(n3665), .Y(n4313) );
INVX2TS U5406 ( .A(n3674), .Y(n4287) );
AOI22X1TS U5407 ( .A0(n2282), .A1(n4287), .B0(n3674), .B1(n2280), .Y(n3671)
);
OAI221X4TS U5408 ( .A0(n3665), .A1(n2281), .B0(n4313), .B1(n2280), .C0(n3664), .Y(n4303) );
INVX2TS U5409 ( .A(n3681), .Y(n4315) );
AOI22X1TS U5410 ( .A0(n2282), .A1(n4315), .B0(n3681), .B1(n2324), .Y(n3666)
);
OAI32X1TS U5411 ( .A0(n2324), .A1(n3681), .A2(n4305), .B0(n4303), .B1(n2324),
.Y(n3688) );
INVX2TS U5412 ( .A(n4294), .Y(n4295) );
AOI22X1TS U5413 ( .A0(n2275), .A1(n4295), .B0(n4294), .B1(mult_x_313_n74),
.Y(n3667) );
OAI32X1TS U5414 ( .A0(n4310), .A1(n3674), .A2(mult_x_313_n74), .B0(n3667),
.B1(n4314), .Y(n4286) );
NOR2X1TS U5415 ( .A(n4315), .B(n4305), .Y(n4285) );
AOI21X1TS U5416 ( .A0(n3681), .A1(n4310), .B0(mult_x_313_n74), .Y(n4317) );
NAND2X1TS U5417 ( .A(n2275), .B(n4314), .Y(n3669) );
AOI22X1TS U5418 ( .A0(n2275), .A1(n4287), .B0(n3674), .B1(mult_x_313_n74),
.Y(n3668) );
OAI22X1TS U5419 ( .A0(n3681), .A1(n3669), .B0(n3668), .B1(n4314), .Y(n4316)
);
INVX2TS U5420 ( .A(n4299), .Y(n4300) );
AOI22X1TS U5421 ( .A0(n2275), .A1(n4300), .B0(n4299), .B1(mult_x_313_n74),
.Y(n3670) );
OAI32X1TS U5422 ( .A0(n4310), .A1(n3837), .A2(mult_x_313_n74), .B0(n3670),
.B1(n4314), .Y(n3684) );
INVX2TS U5423 ( .A(n3675), .Y(n3823) );
AOI22X4TS U5424 ( .A0(n2281), .A1(n3823), .B0(n2280), .B1(n3675), .Y(n4323)
);
AOI22X1TS U5425 ( .A0(n2282), .A1(n4295), .B0(n4294), .B1(n2280), .Y(n3672)
);
OAI22X1TS U5426 ( .A0(n4305), .A1(n3672), .B0(n4303), .B1(n3671), .Y(n3682)
);
AOI22X1TS U5427 ( .A0(n2282), .A1(n4291), .B0(n3837), .B1(n2324), .Y(n4302)
);
OAI22X1TS U5428 ( .A0(n4305), .A1(n4302), .B0(n4303), .B1(n3672), .Y(n3678)
);
AOI22X1TS U5429 ( .A0(n2284), .A1(n4287), .B0(n3674), .B1(n4293), .Y(n4327)
);
OAI221X4TS U5430 ( .A0(n3675), .A1(n2284), .B0(n3823), .B1(n4293), .C0(n4323), .Y(n4328) );
AOI22X1TS U5431 ( .A0(n2284), .A1(n4315), .B0(n3681), .B1(n4293), .Y(n3676)
);
OAI22X1TS U5432 ( .A0(n4323), .A1(n4327), .B0(n4328), .B1(n3676), .Y(n3677)
);
CMPR32X2TS U5433 ( .A(n3679), .B(n3678), .C(n3677), .CO(n3814), .S(n3820) );
INVX2TS U5434 ( .A(n4309), .Y(n4297) );
AOI22X1TS U5435 ( .A0(n3134), .A1(n4297), .B0(n4309), .B1(n2375), .Y(n3680)
);
OAI32X1TS U5436 ( .A0(n4310), .A1(n4299), .A2(n2375), .B0(n3680), .B1(n4314),
.Y(n4322) );
CMPR32X2TS U5437 ( .A(n3684), .B(n3683), .C(n3682), .CO(n3679), .S(n4320) );
ADDHX1TS U5438 ( .A(n3686), .B(n3685), .CO(n4319), .S(n3689) );
INVX2TS U5439 ( .A(n3692), .Y(n3780) );
NAND2X1TS U5440 ( .A(n3780), .B(n3778), .Y(n3690) );
INVX2TS U5441 ( .A(n3691), .Y(n4250) );
NOR2X1TS U5442 ( .A(n2217), .B(n4250), .Y(n3702) );
NOR2X2TS U5443 ( .A(n3692), .B(n3781), .Y(n4113) );
INVX2TS U5444 ( .A(n4113), .Y(n3693) );
NOR2X1TS U5445 ( .A(n3693), .B(n4112), .Y(n3696) );
NAND2X1TS U5446 ( .A(n2223), .B(n6440), .Y(n3782) );
OAI21X4TS U5447 ( .A0(n3781), .A1(n3778), .B0(n3782), .Y(n4119) );
INVX2TS U5448 ( .A(n4119), .Y(n3694) );
AOI21X1TS U5449 ( .A0(n4125), .A1(n3696), .B0(n3695), .Y(n3699) );
NOR2X2TS U5450 ( .A(n2323), .B(n6442), .Y(n4116) );
INVX2TS U5451 ( .A(n4116), .Y(n3697) );
NAND2X1TS U5452 ( .A(n5498), .B(n6442), .Y(n4114) );
NAND2X1TS U5453 ( .A(n3697), .B(n4114), .Y(n3698) );
NOR2X1TS U5454 ( .A(n4249), .B(n4228), .Y(n3701) );
INVX2TS U5455 ( .A(n3710), .Y(n3712) );
NOR2X4TS U5456 ( .A(n3711), .B(n3712), .Y(n3714) );
INVX2TS U5457 ( .A(n4032), .Y(n3763) );
NOR2X2TS U5458 ( .A(n3976), .B(n3712), .Y(n3713) );
NAND2X1TS U5459 ( .A(n4192), .B(n3720), .Y(n3723) );
AOI21X1TS U5460 ( .A0(n4203), .A1(n3720), .B0(n3719), .Y(n3721) );
OAI21X2TS U5461 ( .A0(n3723), .A1(n3722), .B0(n3721), .Y(n3740) );
NAND2X1TS U5462 ( .A(n3726), .B(n3725), .Y(n3727) );
XNOR2X4TS U5463 ( .A(n3728), .B(n3727), .Y(n4095) );
OAI21X4TS U5464 ( .A0(n3731), .A1(n3730), .B0(n3729), .Y(n4091) );
NAND2X2TS U5465 ( .A(n4091), .B(n4095), .Y(n3732) );
OA21X4TS U5466 ( .A0(n4094), .A1(n3733), .B0(n3732), .Y(n4277) );
NAND2X1TS U5467 ( .A(n3735), .B(n3734), .Y(n3736) );
XNOR2X4TS U5468 ( .A(n3737), .B(n3736), .Y(n4307) );
NOR2X2TS U5469 ( .A(DP_OP_501J1_127_1459_n130), .B(n3738), .Y(n4189) );
INVX2TS U5470 ( .A(n4189), .Y(n3767) );
NAND2X1TS U5471 ( .A(n3767), .B(n4194), .Y(n3739) );
INVX2TS U5472 ( .A(n3747), .Y(n3750) );
INVX2TS U5473 ( .A(n3748), .Y(n3749) );
INVX2TS U5474 ( .A(n3753), .Y(n3755) );
INVX2TS U5475 ( .A(n3759), .Y(n3762) );
NAND2X1TS U5476 ( .A(n4192), .B(n3771), .Y(n3773) );
INVX2TS U5477 ( .A(n3765), .Y(n4197) );
INVX2TS U5478 ( .A(n4194), .Y(n3766) );
AOI21X2TS U5479 ( .A0(n4203), .A1(n3771), .B0(n3770), .Y(n3772) );
CMPR32X2TS U5480 ( .A(n3775), .B(n3774), .C(DP_OP_501J1_127_1459_n129), .CO(
n3776), .S(n3738) );
INVX2TS U5481 ( .A(n3776), .Y(n4193) );
NOR2X2TS U5482 ( .A(DP_OP_501J1_127_1459_n481), .B(DP_OP_501J1_127_1459_n486), .Y(n4223) );
INVX2TS U5483 ( .A(n3778), .Y(n3779) );
AOI21X1TS U5484 ( .A0(n4125), .A1(n3780), .B0(n3779), .Y(n3785) );
INVX2TS U5485 ( .A(n3781), .Y(n3783) );
NAND2X1TS U5486 ( .A(n3783), .B(n3782), .Y(n3784) );
INVX2TS U5487 ( .A(n3787), .Y(n4255) );
ADDHXLTS U5488 ( .A(n2277), .B(FPMULT_Op_MX[20]), .CO(n3788), .S(n3787) );
INVX2TS U5489 ( .A(n3788), .Y(n4257) );
OAI22X1TS U5490 ( .A0(n2363), .A1(n4255), .B0(n2217), .B1(n4257), .Y(n3797)
);
INVX2TS U5491 ( .A(n4112), .Y(n3789) );
NAND2X1TS U5492 ( .A(n3789), .B(n4115), .Y(n3790) );
INVX2TS U5493 ( .A(n3792), .Y(n4175) );
INVX2TS U5494 ( .A(n3793), .Y(n4254) );
OAI22X1TS U5495 ( .A0(n2286), .A1(n4175), .B0(n4242), .B1(n4254), .Y(n3796)
);
INVX2TS U5496 ( .A(n3794), .Y(n4246) );
CMPR32X2TS U5497 ( .A(n3797), .B(n3796), .C(n3795), .CO(n3805), .S(n3803) );
NOR2X1TS U5498 ( .A(n2217), .B(n4255), .Y(n3799) );
NOR2X1TS U5499 ( .A(n4242), .B(n4228), .Y(n3798) );
ADDHX1TS U5500 ( .A(n3799), .B(n3798), .CO(n3802), .S(n3801) );
OAI22X1TS U5501 ( .A0(n2363), .A1(n4175), .B0(n2217), .B1(n4254), .Y(n3800)
);
NOR2X1TS U5502 ( .A(n3801), .B(n3800), .Y(n4170) );
NOR2X1TS U5503 ( .A(n2217), .B(n4228), .Y(n4181) );
NOR2X1TS U5504 ( .A(n2217), .B(n4175), .Y(n4180) );
NAND2X1TS U5505 ( .A(n4181), .B(n4180), .Y(n4182) );
NAND2X1TS U5506 ( .A(n3801), .B(n3800), .Y(n4171) );
OAI21X1TS U5507 ( .A0(n4170), .A1(n4182), .B0(n4171), .Y(n4168) );
NAND2X1TS U5508 ( .A(n3803), .B(n3802), .Y(n4167) );
INVX2TS U5509 ( .A(n4167), .Y(n3804) );
AO21X4TS U5510 ( .A0(n2435), .A1(n4168), .B0(n3804), .Y(n4165) );
NAND2X1TS U5511 ( .A(DP_OP_501J1_127_1459_n494), .B(n3805), .Y(n4164) );
INVX2TS U5512 ( .A(n4164), .Y(n3806) );
AOI21X4TS U5513 ( .A0(n2424), .A1(n4165), .B0(n3806), .Y(n4162) );
NOR2X1TS U5514 ( .A(DP_OP_501J1_127_1459_n487), .B(DP_OP_501J1_127_1459_n493), .Y(n4159) );
NAND2X1TS U5515 ( .A(DP_OP_501J1_127_1459_n487), .B(
DP_OP_501J1_127_1459_n493), .Y(n4160) );
OAI21X4TS U5516 ( .A0(n4162), .A1(n4159), .B0(n4160), .Y(n4153) );
NAND2X2TS U5517 ( .A(DP_OP_501J1_127_1459_n481), .B(
DP_OP_501J1_127_1459_n486), .Y(n4224) );
NAND2X1TS U5518 ( .A(DP_OP_501J1_127_1459_n474), .B(
DP_OP_501J1_127_1459_n480), .Y(n4155) );
AOI21X4TS U5519 ( .A0(n3808), .A1(n4153), .B0(n3807), .Y(n4213) );
NOR2X2TS U5520 ( .A(DP_OP_501J1_127_1459_n473), .B(DP_OP_501J1_127_1459_n469), .Y(n4140) );
NAND2X2TS U5521 ( .A(DP_OP_501J1_127_1459_n473), .B(
DP_OP_501J1_127_1459_n469), .Y(n4150) );
OR2X2TS U5522 ( .A(DP_OP_501J1_127_1459_n466), .B(DP_OP_501J1_127_1459_n468),
.Y(n4142) );
NAND2X1TS U5523 ( .A(DP_OP_501J1_127_1459_n466), .B(
DP_OP_501J1_127_1459_n468), .Y(n4127) );
NAND2X1TS U5524 ( .A(n4142), .B(n4127), .Y(n3809) );
INVX2TS U5525 ( .A(n4307), .Y(n4306) );
AOI22X1TS U5526 ( .A0(n2284), .A1(n4306), .B0(n4307), .B1(n2372), .Y(n4289)
);
OAI22X1TS U5527 ( .A0(n2372), .A1(n4323), .B0(n4328), .B1(n4289), .Y(n3830)
);
INVX2TS U5528 ( .A(n3830), .Y(n3822) );
AOI2BB2X4TS U5529 ( .B0(n4095), .B1(n4293), .A0N(n4293), .A1N(n4095), .Y(
n4312) );
NAND2X2TS U5530 ( .A(n2283), .B(n4095), .Y(n4288) );
OAI22X1TS U5531 ( .A0(n4297), .A1(n4312), .B0(n4300), .B1(n4288), .Y(n3821)
);
OAI22X1TS U5532 ( .A0(n4306), .A1(n4312), .B0(n4297), .B1(n4288), .Y(n3831)
);
OAI21X1TS U5533 ( .A0(n2324), .A1(n3823), .B0(n2284), .Y(n3829) );
CMPR32X2TS U5534 ( .A(n3831), .B(n3830), .C(n3829), .CO(n3833), .S(n3827) );
OAI31X1TS U5535 ( .A0(n4306), .A1(n3833), .A2(n4288), .B0(n3832), .Y(n3834)
);
CMPR32X2TS U5536 ( .A(n6441), .B(FPMULT_Op_MY[21]), .C(n3836), .CO(n4109),
.S(n3839) );
CMPR32X2TS U5537 ( .A(n6442), .B(n2323), .C(n3837), .CO(n3629), .S(n4108) );
INVX2TS U5538 ( .A(n3843), .Y(n3845) );
NAND2X2TS U5539 ( .A(n3845), .B(n3844), .Y(n3847) );
XOR2X1TS U5540 ( .A(n3847), .B(n3846), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
INVX2TS U5541 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .Y(
n3855) );
CMPR32X2TS U5542 ( .A(n3849), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]), .C(
n3848), .CO(n3850), .S(n3122) );
NOR2X4TS U5543 ( .A(n3851), .B(n3850), .Y(n3958) );
NOR2X2TS U5544 ( .A(n3956), .B(n3958), .Y(n3853) );
NAND2X2TS U5545 ( .A(n3851), .B(n3850), .Y(n3959) );
OAI21X2TS U5546 ( .A0(n3958), .A1(n3955), .B0(n3959), .Y(n3852) );
AOI21X4TS U5547 ( .A0(n3854), .A1(n3853), .B0(n3852), .Y(n3893) );
INVX4TS U5548 ( .A(n3893), .Y(n3873) );
INVX2TS U5549 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(
n3861) );
INVX2TS U5550 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .Y(
n3860) );
CMPR32X2TS U5551 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]), .B(
n3856), .C(n3855), .CO(n3857), .S(n3851) );
NOR2X2TS U5552 ( .A(n3858), .B(n3857), .Y(n3869) );
INVX2TS U5553 ( .A(n3869), .Y(n3867) );
NAND2X2TS U5554 ( .A(n3858), .B(n3857), .Y(n3871) );
INVX2TS U5555 ( .A(n3871), .Y(n3859) );
AOI21X1TS U5556 ( .A0(n3873), .A1(n3867), .B0(n3859), .Y(n3866) );
INVX2TS U5557 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(
n3875) );
INVX2TS U5558 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .Y(
n3874) );
CMPR32X2TS U5559 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]), .B(
n3861), .C(n3860), .CO(n3862), .S(n3858) );
NOR2X4TS U5560 ( .A(n3863), .B(n3862), .Y(n3872) );
INVX2TS U5561 ( .A(n3872), .Y(n3864) );
NAND2X2TS U5562 ( .A(n3863), .B(n3862), .Y(n3870) );
NAND2X1TS U5563 ( .A(n3864), .B(n3870), .Y(n3865) );
NAND2X1TS U5564 ( .A(n3867), .B(n3871), .Y(n3868) );
XNOR2X1TS U5565 ( .A(n3873), .B(n3868), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
NOR2X2TS U5566 ( .A(n3869), .B(n3872), .Y(n3885) );
INVX2TS U5567 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(
n3879) );
INVX2TS U5568 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .Y(
n3878) );
CMPR32X2TS U5569 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]), .B(
n3875), .C(n3874), .CO(n3876), .S(n3863) );
NAND2X2TS U5570 ( .A(n3877), .B(n3876), .Y(n3964) );
OAI21X1TS U5571 ( .A0(n3967), .A1(n3963), .B0(n3964), .Y(n3884) );
INVX2TS U5572 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(
n3895) );
INVX2TS U5573 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(
n3894) );
INVX2TS U5574 ( .A(n3887), .Y(n3882) );
NAND2X1TS U5575 ( .A(n3881), .B(n3880), .Y(n3886) );
NAND2X1TS U5576 ( .A(n3882), .B(n3886), .Y(n3883) );
XNOR2X1TS U5577 ( .A(n3884), .B(n3883), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
NAND2X2TS U5578 ( .A(n3885), .B(n3889), .Y(n3892) );
OAI21X1TS U5579 ( .A0(n3887), .A1(n3964), .B0(n3886), .Y(n3888) );
AOI21X2TS U5580 ( .A0(n3890), .A1(n3889), .B0(n3888), .Y(n3891) );
OAI21X4TS U5581 ( .A0(n3893), .A1(n3892), .B0(n3891), .Y(n3921) );
INVX2TS U5582 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(
n3897) );
INVX2TS U5583 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .Y(
n3896) );
CMPR32X2TS U5584 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]), .B(
n3895), .C(n3894), .CO(n3902), .S(n3881) );
INVX2TS U5585 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(
n3899) );
CMPR32X2TS U5586 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]), .B(
n3897), .C(n3896), .CO(n3904), .S(n3903) );
INVX2TS U5587 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .Y(
n3901) );
INVX2TS U5588 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .Y(
n3900) );
INVX2TS U5589 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .Y(
n3912) );
CMPR32X2TS U5590 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]),
.B(n3901), .C(n3900), .CO(n3909), .S(n3907) );
NOR2X2TS U5591 ( .A(n3910), .B(n3909), .Y(n3933) );
NAND2X2TS U5592 ( .A(n3903), .B(n3902), .Y(n3947) );
NAND2X1TS U5593 ( .A(n3905), .B(n3904), .Y(n3951) );
OAI21X2TS U5594 ( .A0(n3950), .A1(n3947), .B0(n3951), .Y(n3923) );
INVX2TS U5595 ( .A(n3926), .Y(n3908) );
NAND2X1TS U5596 ( .A(n3910), .B(n3909), .Y(n3934) );
INVX2TS U5597 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n3915) );
XNOR2X1TS U5598 ( .A(n3915), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]),
.Y(n3914) );
CMPR32X2TS U5599 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]),
.B(n2774), .C(n3912), .CO(n3913), .S(n3910) );
OAI21X4TS U5600 ( .A0(n3946), .A1(n3942), .B0(n3943), .Y(n3941) );
INVX2TS U5601 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n3919) );
XNOR2X1TS U5602 ( .A(n3919), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]),
.Y(n3917) );
OR2X2TS U5603 ( .A(n3915), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]),
.Y(n3916) );
OR2X2TS U5604 ( .A(n3917), .B(n3916), .Y(n3939) );
INVX2TS U5605 ( .A(n3938), .Y(n3918) );
AOI21X4TS U5606 ( .A0(n3941), .A1(n3939), .B0(n3918), .Y(n3973) );
NOR2X1TS U5607 ( .A(n3920), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]),
.Y(n3969) );
NAND2X1TS U5608 ( .A(n3920), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]),
.Y(n3970) );
INVX4TS U5609 ( .A(n3921), .Y(n3949) );
INVX2TS U5610 ( .A(n3922), .Y(n3925) );
INVX2TS U5611 ( .A(n3923), .Y(n3924) );
OAI21X1TS U5612 ( .A0(n3949), .A1(n3925), .B0(n3924), .Y(n3928) );
NAND2X1TS U5613 ( .A(n2451), .B(n3926), .Y(n3927) );
INVX2TS U5614 ( .A(n3948), .Y(n3929) );
NAND2X1TS U5615 ( .A(n3929), .B(n3947), .Y(n3930) );
XOR2X1TS U5616 ( .A(n3949), .B(n3930), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
OAI21X1TS U5617 ( .A0(n3949), .A1(n3932), .B0(n3931), .Y(n3937) );
INVX2TS U5618 ( .A(n3933), .Y(n3935) );
NAND2X1TS U5619 ( .A(n3935), .B(n3934), .Y(n3936) );
XNOR2X1TS U5620 ( .A(n3937), .B(n3936), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
NAND2X1TS U5621 ( .A(n3939), .B(n3938), .Y(n3940) );
XNOR2X1TS U5622 ( .A(n3941), .B(n3940), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
INVX2TS U5623 ( .A(n3942), .Y(n3944) );
NAND2X1TS U5624 ( .A(n3944), .B(n3943), .Y(n3945) );
XOR2X1TS U5625 ( .A(n3946), .B(n3945), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
INVX2TS U5626 ( .A(n3950), .Y(n3952) );
NAND2X1TS U5627 ( .A(n3952), .B(n3951), .Y(n3953) );
INVX2TS U5628 ( .A(n3958), .Y(n3960) );
INVX2TS U5629 ( .A(n3963), .Y(n3965) );
NAND2X1TS U5630 ( .A(n3965), .B(n3964), .Y(n3966) );
XOR2X1TS U5631 ( .A(n3967), .B(n3966), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
INVX2TS U5632 ( .A(n3969), .Y(n3971) );
NAND2X1TS U5633 ( .A(n3971), .B(n3970), .Y(n3972) );
XOR2X2TS U5634 ( .A(n3973), .B(n3972), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
INVX2TS U5635 ( .A(n4005), .Y(n3987) );
INVX2TS U5636 ( .A(n4004), .Y(n3989) );
OAI21X1TS U5637 ( .A0(n3989), .A1(n4006), .B0(n4007), .Y(n3990) );
INVX2TS U5638 ( .A(n3992), .Y(n3994) );
INVX2TS U5639 ( .A(n3997), .Y(n4410) );
INVX2TS U5640 ( .A(n4409), .Y(n3998) );
INVX2TS U5641 ( .A(n3999), .Y(n4001) );
INVX2TS U5642 ( .A(n4006), .Y(n4008) );
INVX4TS U5643 ( .A(n6137), .Y(DP_OP_499J1_125_4188_n277) );
INVX4TS U5644 ( .A(n4013), .Y(DP_OP_499J1_125_4188_n304) );
INVX4TS U5645 ( .A(n4017), .Y(DP_OP_499J1_125_4188_n303) );
INVX2TS U5646 ( .A(n6128), .Y(DP_OP_499J1_125_4188_n280) );
INVX2TS U5647 ( .A(n4025), .Y(n4027) );
XOR2X4TS U5648 ( .A(n4029), .B(n4028), .Y(n6144) );
INVX4TS U5649 ( .A(n4031), .Y(DP_OP_499J1_125_4188_n291) );
INVX4TS U5650 ( .A(n4032), .Y(DP_OP_499J1_125_4188_n295) );
ADDFHX4TS U5651 ( .A(n4051), .B(n4050), .CI(n4049), .CO(
DP_OP_499J1_125_4188_n250), .S(n2665) );
INVX2TS U5652 ( .A(n4052), .Y(n4054) );
NAND2X1TS U5653 ( .A(n4054), .B(n4053), .Y(n4055) );
INVX2TS U5654 ( .A(n4056), .Y(n4065) );
INVX2TS U5655 ( .A(n4057), .Y(n4059) );
NAND2X1TS U5656 ( .A(n4059), .B(n4058), .Y(n4060) );
XNOR2X1TS U5657 ( .A(n4061), .B(n4060), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8) );
INVX2TS U5658 ( .A(n4062), .Y(n4064) );
NAND2X1TS U5659 ( .A(n4064), .B(n4063), .Y(n4066) );
INVX2TS U5660 ( .A(n4067), .Y(n4069) );
NAND2X1TS U5661 ( .A(n4069), .B(n4068), .Y(n4071) );
NAND2X1TS U5662 ( .A(n4073), .B(n4072), .Y(n4074) );
XNOR2X1TS U5663 ( .A(n4075), .B(n4074), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5) );
INVX2TS U5664 ( .A(n4076), .Y(n4078) );
NAND2X1TS U5665 ( .A(n4078), .B(n4077), .Y(n4080) );
NAND2X1TS U5666 ( .A(n4081), .B(n3173), .Y(n4083) );
XNOR2X1TS U5667 ( .A(n4083), .B(n4082), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3) );
NAND2X1TS U5668 ( .A(n2391), .B(n4084), .Y(n4086) );
AFHCONX2TS U5669 ( .A(n4089), .B(n4088), .CI(n4087), .CON(n4085), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1) );
INVX2TS U5670 ( .A(n4091), .Y(n4092) );
INVX2TS U5671 ( .A(n4095), .Y(n4096) );
OAI22X1TS U5672 ( .A0(n2335), .A1(n4278), .B0(n2373), .B1(n4280), .Y(
DP_OP_501J1_127_1459_n215) );
OAI22X1TS U5673 ( .A0(n2336), .A1(n4280), .B0(n2387), .B1(n4278), .Y(
DP_OP_501J1_127_1459_n216) );
OAI22X1TS U5674 ( .A0(n2333), .A1(n4280), .B0(n2330), .B1(n4278), .Y(
DP_OP_501J1_127_1459_n220) );
OAI22X1TS U5675 ( .A0(n2336), .A1(n4266), .B0(n2387), .B1(n4267), .Y(
DP_OP_501J1_127_1459_n225) );
INVX2TS U5676 ( .A(n4102), .Y(n4104) );
OAI22X1TS U5677 ( .A0(n4279), .A1(n4266), .B0(n2334), .B1(n4267), .Y(
DP_OP_501J1_127_1459_n228) );
INVX6TS U5678 ( .A(n4110), .Y(n4264) );
OAI22X1TS U5679 ( .A0(n2335), .A1(n4264), .B0(n4277), .B1(n4234), .Y(
DP_OP_501J1_127_1459_n233) );
OAI22X1TS U5680 ( .A0(n2336), .A1(n4234), .B0(n2386), .B1(n4264), .Y(
DP_OP_501J1_127_1459_n234) );
OAI22X1TS U5681 ( .A0(n2387), .A1(n4234), .B0(n2332), .B1(n4264), .Y(
DP_OP_501J1_127_1459_n235) );
OAI22X1TS U5682 ( .A0(n2331), .A1(n4234), .B0(n4279), .B1(n4264), .Y(
DP_OP_501J1_127_1459_n236) );
OAI22X1TS U5683 ( .A0(n2333), .A1(n4234), .B0(n2329), .B1(n4264), .Y(
DP_OP_501J1_127_1459_n238) );
OAI22X1TS U5684 ( .A0(n2335), .A1(n4215), .B0(n4277), .B1(n4216), .Y(
DP_OP_501J1_127_1459_n242) );
OAI22X1TS U5685 ( .A0(n2336), .A1(n4216), .B0(n2387), .B1(n4215), .Y(
DP_OP_501J1_127_1459_n243) );
OAI22X1TS U5686 ( .A0(n2387), .A1(n4216), .B0(n2332), .B1(n4215), .Y(
DP_OP_501J1_127_1459_n244) );
OAI22X1TS U5687 ( .A0(n2331), .A1(n4216), .B0(n4279), .B1(n4215), .Y(
DP_OP_501J1_127_1459_n245) );
OAI22X1TS U5688 ( .A0(n4279), .A1(n4216), .B0(n2334), .B1(n4215), .Y(
DP_OP_501J1_127_1459_n246) );
OAI22X1TS U5689 ( .A0(n2335), .A1(n4276), .B0(n4277), .B1(n4219), .Y(
DP_OP_501J1_127_1459_n251) );
OAI22X1TS U5690 ( .A0(n2336), .A1(n4219), .B0(n2387), .B1(n4276), .Y(
DP_OP_501J1_127_1459_n252) );
OAI22X1TS U5691 ( .A0(n2387), .A1(n4219), .B0(n2332), .B1(n4276), .Y(
DP_OP_501J1_127_1459_n253) );
OAI22X1TS U5692 ( .A0(n2332), .A1(n4219), .B0(n4279), .B1(n4276), .Y(
DP_OP_501J1_127_1459_n254) );
OAI22X1TS U5693 ( .A0(n2334), .A1(n4219), .B0(n2330), .B1(n4276), .Y(
DP_OP_501J1_127_1459_n256) );
OAI22X1TS U5694 ( .A0(n2336), .A1(n4260), .B0(n2373), .B1(n4111), .Y(
DP_OP_501J1_127_1459_n260) );
OAI22X1TS U5695 ( .A0(n2336), .A1(n4111), .B0(n2387), .B1(n4260), .Y(
DP_OP_501J1_127_1459_n261) );
OAI22X1TS U5696 ( .A0(n2387), .A1(n4111), .B0(n2332), .B1(n4260), .Y(
DP_OP_501J1_127_1459_n262) );
OAI22X1TS U5697 ( .A0(n2331), .A1(n4111), .B0(n4279), .B1(n4260), .Y(
DP_OP_501J1_127_1459_n263) );
OAI22X1TS U5698 ( .A0(n2374), .A1(n4111), .B0(n2334), .B1(n4260), .Y(
DP_OP_501J1_127_1459_n264) );
NAND2X1TS U5699 ( .A(n4123), .B(n2443), .Y(n4120) );
ADDHXLTS U5700 ( .A(DP_OP_501J1_127_1459_n952), .B(DP_OP_501J1_127_1459_n939), .CO(n4122), .S(n3691) );
INVX2TS U5701 ( .A(n4122), .Y(n4248) );
AOI21X1TS U5702 ( .A0(n4125), .A1(n2436), .B0(n4124), .Y(n4126) );
INVX2TS U5703 ( .A(n6455), .Y(n4241) );
OAI22X1TS U5704 ( .A0(n2287), .A1(n4241), .B0(n4256), .B1(n5489), .Y(n4134)
);
OR2X2TS U5705 ( .A(DP_OP_501J1_127_1459_n465), .B(n4128), .Y(n4147) );
INVX2TS U5706 ( .A(n4206), .Y(n4133) );
INVX2TS U5707 ( .A(n4127), .Y(n4141) );
NAND2X1TS U5708 ( .A(DP_OP_501J1_127_1459_n465), .B(n4128), .Y(n4146) );
INVX2TS U5709 ( .A(n4146), .Y(n4129) );
AOI21X1TS U5710 ( .A0(n4141), .A1(n4147), .B0(n4129), .Y(n4130) );
INVX2TS U5711 ( .A(n4210), .Y(n4132) );
CMPR32X2TS U5712 ( .A(n4135), .B(n4134), .C(DP_OP_501J1_127_1459_n464), .CO(
n4137), .S(n4128) );
NOR2X1TS U5713 ( .A(n4256), .B(n4241), .Y(n4136) );
NAND2X1TS U5714 ( .A(n4137), .B(n4136), .Y(n4207) );
NAND2X1TS U5715 ( .A(n4209), .B(n4207), .Y(n4138) );
XNOR2X1TS U5716 ( .A(n4139), .B(n4138), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10) );
INVX2TS U5717 ( .A(n4140), .Y(n4151) );
NAND2X1TS U5718 ( .A(n4151), .B(n4142), .Y(n4145) );
INVX2TS U5719 ( .A(n4150), .Y(n4143) );
AOI21X1TS U5720 ( .A0(n4143), .A1(n4142), .B0(n4141), .Y(n4144) );
NAND2X1TS U5721 ( .A(n4147), .B(n4146), .Y(n4148) );
XNOR2X1TS U5722 ( .A(n4149), .B(n4148), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9) );
NAND2X1TS U5723 ( .A(n4151), .B(n4150), .Y(n4152) );
INVX2TS U5724 ( .A(n4153), .Y(n4227) );
INVX2TS U5725 ( .A(n4154), .Y(n4156) );
NAND2X1TS U5726 ( .A(n4156), .B(n4155), .Y(n4157) );
XNOR2X1TS U5727 ( .A(n4158), .B(n4157), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6) );
INVX2TS U5728 ( .A(n4159), .Y(n4161) );
NAND2X1TS U5729 ( .A(n4161), .B(n4160), .Y(n4163) );
NAND2X1TS U5730 ( .A(n2424), .B(n4164), .Y(n4166) );
XNOR2X1TS U5731 ( .A(n4166), .B(n4165), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3) );
NAND2X1TS U5732 ( .A(n2435), .B(n4167), .Y(n4169) );
XNOR2X1TS U5733 ( .A(n4169), .B(n4168), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2) );
INVX2TS U5734 ( .A(n4170), .Y(n4172) );
NAND2X1TS U5735 ( .A(n4172), .B(n4171), .Y(n4173) );
OAI22X1TS U5736 ( .A0(n2287), .A1(n5489), .B0(n4249), .B1(n4241), .Y(
DP_OP_501J1_127_1459_n505) );
OAI22X1TS U5737 ( .A0(n4249), .A1(n5489), .B0(n2286), .B1(n4241), .Y(
DP_OP_501J1_127_1459_n506) );
OAI22X1TS U5738 ( .A0(n4242), .A1(n6455), .B0(n2217), .B1(n4241), .Y(
DP_OP_501J1_127_1459_n508) );
OAI22X1TS U5739 ( .A0(n2205), .A1(n4248), .B0(n4256), .B1(n4250), .Y(
DP_OP_501J1_127_1459_n511) );
OAI22X1TS U5740 ( .A0(n2286), .A1(n4250), .B0(n4242), .B1(n4248), .Y(
DP_OP_501J1_127_1459_n514) );
ADDHXLTS U5741 ( .A(FPMULT_Op_MX[9]), .B(n6640), .CO(n4174), .S(n3794) );
INVX2TS U5742 ( .A(n4174), .Y(n4247) );
OAI22X1TS U5743 ( .A0(n4249), .A1(n4246), .B0(n2286), .B1(n4247), .Y(
DP_OP_501J1_127_1459_n520) );
OAI22X1TS U5744 ( .A0(n4242), .A1(n4246), .B0(n2217), .B1(n4247), .Y(
DP_OP_501J1_127_1459_n522) );
OAI22X1TS U5745 ( .A0(n4249), .A1(n4255), .B0(n2286), .B1(n4257), .Y(
DP_OP_501J1_127_1459_n527) );
OAI22X1TS U5746 ( .A0(n2286), .A1(n4255), .B0(n4242), .B1(n4257), .Y(
DP_OP_501J1_127_1459_n528) );
OAI22X1TS U5747 ( .A0(n2205), .A1(n4175), .B0(n4249), .B1(n4254), .Y(
DP_OP_501J1_127_1459_n533) );
OAI22X1TS U5748 ( .A0(n4249), .A1(n4175), .B0(n2286), .B1(n4254), .Y(
DP_OP_501J1_127_1459_n534) );
OAI22X1TS U5749 ( .A0(n4242), .A1(n4250), .B0(n2243), .B1(n4248), .Y(n4188)
);
OAI22X1TS U5750 ( .A0(n2285), .A1(n4246), .B0(n4242), .B1(n4247), .Y(n4187)
);
CMPR32X2TS U5751 ( .A(n4188), .B(n4187), .C(n4186), .CO(
DP_OP_501J1_127_1459_n488), .S(DP_OP_501J1_127_1459_n489) );
NOR2X1TS U5752 ( .A(n2331), .B(n4275), .Y(DP_OP_501J1_127_1459_n209) );
NOR2X1TS U5753 ( .A(n4189), .B(n4193), .Y(n4196) );
AOI21X1TS U5754 ( .A0(n4197), .A1(n4196), .B0(n4195), .Y(n4198) );
OAI21X1TS U5755 ( .A0(n4205), .A1(n3722), .B0(n4204), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15) );
NOR2X1TS U5756 ( .A(n4277), .B(n4215), .Y(DP_OP_501J1_127_1459_n241) );
NOR2X1TS U5757 ( .A(n4279), .B(n4214), .Y(DP_OP_501J1_127_1459_n272) );
NOR2X1TS U5758 ( .A(n2331), .B(n4214), .Y(DP_OP_501J1_127_1459_n271) );
NOR2X1TS U5759 ( .A(n2335), .B(n4275), .Y(DP_OP_501J1_127_1459_n207) );
NOR2X1TS U5760 ( .A(n2336), .B(n4214), .Y(DP_OP_501J1_127_1459_n269) );
NAND2X1TS U5761 ( .A(n4206), .B(n4209), .Y(n4212) );
INVX2TS U5762 ( .A(n4207), .Y(n4208) );
AOI21X1TS U5763 ( .A0(n4210), .A1(n4209), .B0(n4208), .Y(n4211) );
NOR2X1TS U5764 ( .A(n2386), .B(n4214), .Y(DP_OP_501J1_127_1459_n270) );
NOR2X1TS U5765 ( .A(n2373), .B(n4214), .Y(DP_OP_501J1_127_1459_n268) );
OAI22X1TS U5766 ( .A0(n2333), .A1(n4216), .B0(n2330), .B1(n4215), .Y(n4222)
);
ADDHX1TS U5767 ( .A(n4218), .B(n4217), .CO(DP_OP_501J1_127_1459_n193), .S(
n4221) );
OAI22X1TS U5768 ( .A0(n4279), .A1(n4219), .B0(n2334), .B1(n4276), .Y(n4220)
);
INVX2TS U5769 ( .A(n4223), .Y(n4225) );
NAND2X1TS U5770 ( .A(n4225), .B(n4224), .Y(n4226) );
NOR2X1TS U5771 ( .A(n2330), .B(n4275), .Y(DP_OP_501J1_127_1459_n212) );
NOR2X1TS U5772 ( .A(n4277), .B(n4267), .Y(DP_OP_501J1_127_1459_n223) );
NOR2X1TS U5773 ( .A(n4256), .B(n4247), .Y(DP_OP_501J1_127_1459_n517) );
INVX2TS U5774 ( .A(n5316), .Y(n4229) );
NAND2X1TS U5775 ( .A(n1670), .B(n1658), .Y(n6621) );
NOR2X1TS U5776 ( .A(DP_OP_501J1_127_1459_n930), .B(DP_OP_501J1_127_1459_n943), .Y(n4238) );
NAND2X1TS U5777 ( .A(DP_OP_501J1_127_1459_n930), .B(
DP_OP_501J1_127_1459_n943), .Y(n4239) );
CLKMX2X2TS U5778 ( .A(Data_1[15]), .B(n6827), .S0(n5494), .Y(n1673) );
OAI22X1TS U5779 ( .A0(n2329), .A1(n4280), .B0(n4231), .B1(n4278), .Y(n4232)
);
OAI22X1TS U5780 ( .A0(n2333), .A1(n4266), .B0(n2330), .B1(n4267), .Y(n4237)
);
CMPR22X2TS U5781 ( .A(n4233), .B(n4232), .CO(DP_OP_501J1_127_1459_n178), .S(
n4236) );
OAI22X1TS U5782 ( .A0(n4279), .A1(n4234), .B0(n2334), .B1(n4264), .Y(n4235)
);
ADDFHX1TS U5783 ( .A(n4237), .B(n4236), .CI(n4235), .CO(
DP_OP_501J1_127_1459_n176), .S(DP_OP_501J1_127_1459_n177) );
INVX2TS U5784 ( .A(n4238), .Y(n4240) );
NAND2X1TS U5785 ( .A(n4240), .B(n4239), .Y(n6625) );
NAND2X1TS U5786 ( .A(n1673), .B(n1661), .Y(n6626) );
OAI22X1TS U5787 ( .A0(n2285), .A1(n5489), .B0(n4242), .B1(n4241), .Y(n4245)
);
OAI22X1TS U5788 ( .A0(n4249), .A1(n4250), .B0(n2285), .B1(n4248), .Y(n4244)
);
OAI22X1TS U5789 ( .A0(n2205), .A1(n4246), .B0(n4249), .B1(n4247), .Y(n4243)
);
CMPR32X2TS U5790 ( .A(n4245), .B(n4244), .C(n4243), .CO(
DP_OP_501J1_127_1459_n475), .S(DP_OP_501J1_127_1459_n476) );
OAI22X1TS U5791 ( .A0(n2205), .A1(n4247), .B0(n4256), .B1(n4246), .Y(n4252)
);
OAI22X1TS U5792 ( .A0(n2205), .A1(n4250), .B0(n2364), .B1(n4248), .Y(n4251)
);
CMPR32X2TS U5793 ( .A(n4253), .B(n4252), .C(n4251), .CO(
DP_OP_501J1_127_1459_n470), .S(DP_OP_501J1_127_1459_n471) );
OAI22X1TS U5794 ( .A0(n2205), .A1(n4257), .B0(n4256), .B1(n4255), .Y(n4258)
);
OAI22X1TS U5795 ( .A0(n2332), .A1(n4266), .B0(n2374), .B1(n4267), .Y(n4262)
);
NOR2X2TS U5796 ( .A(n2334), .B(n4275), .Y(n4272) );
CMPR32X2TS U5797 ( .A(n4263), .B(n4262), .C(n4261), .CO(
DP_OP_501J1_127_1459_n157), .S(DP_OP_501J1_127_1459_n158) );
OAI22X1TS U5798 ( .A0(n2335), .A1(n4267), .B0(n4277), .B1(n4266), .Y(n4268)
);
CMPR32X2TS U5799 ( .A(n4270), .B(n4269), .C(n4268), .CO(
DP_OP_501J1_127_1459_n135), .S(DP_OP_501J1_127_1459_n136) );
ADDHX1TS U5800 ( .A(n4272), .B(n4271), .CO(DP_OP_501J1_127_1459_n159), .S(
n4261) );
ADDHX1TS U5801 ( .A(n4274), .B(n4273), .CO(DP_OP_501J1_127_1459_n202), .S(
n3186) );
OAI22X1TS U5802 ( .A0(n2332), .A1(n4280), .B0(n2374), .B1(n4278), .Y(n4281)
);
CMPR32X2TS U5803 ( .A(n4286), .B(n4285), .C(n4284), .CO(n3687), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2) );
OAI22X1TS U5804 ( .A0(n4291), .A1(n4312), .B0(n4295), .B1(n4288), .Y(
mult_x_313_n27) );
OAI22X1TS U5805 ( .A0(n4295), .A1(n4312), .B0(n4287), .B1(n4288), .Y(
mult_x_313_n32) );
OAI22X1TS U5806 ( .A0(n4300), .A1(n4312), .B0(n4291), .B1(n4288), .Y(
mult_x_313_n54) );
OAI22X1TS U5807 ( .A0(n4315), .A1(n4288), .B0(n4287), .B1(n4312), .Y(
mult_x_313_n55) );
AOI22X1TS U5808 ( .A0(n2284), .A1(n4297), .B0(n4309), .B1(n2372), .Y(n4290)
);
OAI22X1TS U5809 ( .A0(n4323), .A1(n4289), .B0(n4328), .B1(n4290), .Y(
mult_x_313_n58) );
AOI22X1TS U5810 ( .A0(n2284), .A1(n4300), .B0(n4299), .B1(n4293), .Y(n4292)
);
OAI22X1TS U5811 ( .A0(n4323), .A1(n4290), .B0(n4328), .B1(n4292), .Y(
mult_x_313_n59) );
AOI22X1TS U5812 ( .A0(n2284), .A1(n4291), .B0(n3837), .B1(n4293), .Y(n4296)
);
OAI22X1TS U5813 ( .A0(n4323), .A1(n4292), .B0(n4328), .B1(n4296), .Y(
mult_x_313_n60) );
AOI22X1TS U5814 ( .A0(n2283), .A1(n4295), .B0(n4294), .B1(n4293), .Y(n4324)
);
OAI22X1TS U5815 ( .A0(n4323), .A1(n4296), .B0(n4328), .B1(n4324), .Y(
mult_x_313_n61) );
AOI22X1TS U5816 ( .A0(n2282), .A1(n4306), .B0(n4307), .B1(n2324), .Y(n4298)
);
OAI22X1TS U5817 ( .A0(n2324), .A1(n4305), .B0(n4303), .B1(n4298), .Y(
mult_x_313_n66) );
AOI22X1TS U5818 ( .A0(n2282), .A1(n4297), .B0(n4309), .B1(n2324), .Y(n4301)
);
OAI22X1TS U5819 ( .A0(n4305), .A1(n4298), .B0(n4303), .B1(n4301), .Y(
mult_x_313_n67) );
AOI22X1TS U5820 ( .A0(n2282), .A1(n4300), .B0(n4299), .B1(n2324), .Y(n4304)
);
OAI22X1TS U5821 ( .A0(n4305), .A1(n4301), .B0(n4303), .B1(n4304), .Y(
mult_x_313_n68) );
OAI22X1TS U5822 ( .A0(n4305), .A1(n4304), .B0(n4303), .B1(n4302), .Y(
mult_x_313_n69) );
AOI21X1TS U5823 ( .A0(n4307), .A1(n4314), .B0(n2375), .Y(mult_x_313_n75) );
AOI22X1TS U5824 ( .A0(n4307), .A1(n2375), .B0(n2275), .B1(n4306), .Y(n4308)
);
OAI32X1TS U5825 ( .A0(n4310), .A1(n4309), .A2(n2375), .B0(n4308), .B1(n4314),
.Y(mult_x_313_n76) );
INVX2TS U5826 ( .A(mult_x_313_n32), .Y(mult_x_313_n33) );
NOR2X1TS U5827 ( .A(n4315), .B(n4312), .Y(mult_x_313_n56) );
INVX2TS U5828 ( .A(mult_x_313_n27), .Y(mult_x_313_n28) );
ADDHXLTS U5829 ( .A(n4317), .B(n4316), .CO(n4284), .S(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1) );
INVX2TS U5830 ( .A(n4323), .Y(n4326) );
INVX2TS U5831 ( .A(n4324), .Y(n4325) );
NOR4X1TS U5832 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n4331) );
NOR4X1TS U5833 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n4330) );
NOR4X1TS U5834 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n4329) );
NOR4X1TS U5835 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n4332),
.Y(n6844) );
INVX2TS U5836 ( .A(FPSENCOS_d_ff2_Y[23]), .Y(n7048) );
INVX2TS U5837 ( .A(n4333), .Y(n5390) );
NOR2X1TS U5838 ( .A(n4625), .B(n5390), .Y(n4336) );
ADDHXLTS U5839 ( .A(n6924), .B(FPMULT_Op_MX[9]), .CO(n4334), .S(n3543) );
INVX2TS U5840 ( .A(n4334), .Y(n5391) );
OAI22X1TS U5841 ( .A0(n5394), .A1(n5392), .B0(n5387), .B1(n5391), .Y(n4335)
);
ADDHX1TS U5842 ( .A(n4336), .B(n4335), .CO(DP_OP_502J1_128_2852_n137), .S(
DP_OP_502J1_128_2852_n138) );
NOR2BX2TS U5843 ( .AN(n7035), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n4528) );
NAND3X2TS U5844 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n4337),
.C(n4528), .Y(n6208) );
NAND3X1TS U5845 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n7035),
.C(n4536), .Y(n6209) );
OAI2BB2X4TS U5846 ( .B0(n4535), .B1(n4685), .A0N(operation[1]), .A1N(n5013),
.Y(n5318) );
OAI21X1TS U5847 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n5881), .Y(n6206) );
NOR3X2TS U5848 ( .A(n4941), .B(n6650), .C(FPSENCOS_cont_var_out[0]), .Y(
n4338) );
BUFX3TS U5849 ( .A(n6484), .Y(n6101) );
NOR2X1TS U5850 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4569) );
NAND2X1TS U5851 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4588) );
NAND2X1TS U5852 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4570) );
NOR2X2TS U5853 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4595) );
NAND2X1TS U5854 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4596) );
NOR2X1TS U5855 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n5902) );
NOR2X2TS U5856 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n5897) );
NOR2X1TS U5857 ( .A(n5902), .B(n5897), .Y(n6068) );
NOR2X2TS U5858 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6063) );
NOR2X1TS U5859 ( .A(n6094), .B(n6063), .Y(n4342) );
NAND2X1TS U5860 ( .A(n6068), .B(n4342), .Y(n4344) );
NAND2X1TS U5861 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n5914) );
NAND2X1TS U5862 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n5898) );
OAI21X1TS U5863 ( .A0(n5897), .A1(n5914), .B0(n5898), .Y(n6067) );
NAND2X1TS U5864 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6095) );
NAND2X1TS U5865 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6064) );
AOI21X1TS U5866 ( .A0(n6067), .A1(n4342), .B0(n4341), .Y(n4343) );
OAI21X2TS U5867 ( .A0(n5901), .A1(n4344), .B0(n4343), .Y(n5928) );
NOR2X1TS U5868 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n5952) );
INVX2TS U5869 ( .A(n5952), .Y(n5925) );
NAND2X1TS U5870 ( .A(n5925), .B(n5948), .Y(n6084) );
NOR2X2TS U5871 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n6078) );
NOR2X1TS U5872 ( .A(n6084), .B(n6078), .Y(n4348) );
NAND2X1TS U5873 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n5951) );
INVX2TS U5874 ( .A(n5951), .Y(n4346) );
NAND2X1TS U5875 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n5947) );
INVX2TS U5876 ( .A(n5947), .Y(n4345) );
AOI21X1TS U5877 ( .A0(n5948), .A1(n4346), .B0(n4345), .Y(n6083) );
NAND2X1TS U5878 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n6079) );
OAI21X1TS U5879 ( .A0(n6083), .A1(n6078), .B0(n6079), .Y(n4347) );
AOI21X4TS U5880 ( .A0(n5928), .A1(n4348), .B0(n4347), .Y(n5939) );
INVX2TS U5881 ( .A(n6054), .Y(n4349) );
NOR2X1TS U5882 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n5967) );
NAND2X1TS U5883 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n5968) );
NAND2X1TS U5884 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n5958) );
INVX2TS U5885 ( .A(n5958), .Y(n4350) );
NOR2X1TS U5886 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n5977) );
NAND2X1TS U5887 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n5978) );
OAI21X4TS U5888 ( .A0(n5983), .A1(n5977), .B0(n5978), .Y(n6050) );
NAND2X1TS U5889 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n6045) );
INVX2TS U5890 ( .A(n6045), .Y(n4351) );
AOI21X4TS U5891 ( .A0(n6050), .A1(n6046), .B0(n4351), .Y(n5993) );
NOR2X1TS U5892 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n5987) );
NAND2X1TS U5893 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n5988) );
OAI21X4TS U5894 ( .A0(n5993), .A1(n5987), .B0(n5988), .Y(n6013) );
NAND2X1TS U5895 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n6008) );
INVX2TS U5896 ( .A(n6008), .Y(n4352) );
AOI21X4TS U5897 ( .A0(n6013), .A1(n6009), .B0(n4352), .Y(n6003) );
NOR2X1TS U5898 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n5997) );
NAND2X1TS U5899 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n5998) );
OAI21X4TS U5900 ( .A0(n6003), .A1(n5997), .B0(n5998), .Y(n6030) );
NAND2X1TS U5901 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n6025) );
INVX2TS U5902 ( .A(n6025), .Y(n4353) );
AOI21X4TS U5903 ( .A0(n6030), .A1(n6026), .B0(n4353), .Y(n6041) );
NOR2X1TS U5904 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n6035) );
NAND2X1TS U5905 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n6036) );
NAND2X1TS U5906 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n4481) );
INVX2TS U5907 ( .A(n4481), .Y(n4354) );
NAND2BX2TS U5908 ( .AN(n4357), .B(n4523), .Y(n5321) );
INVX2TS U5909 ( .A(n6270), .Y(n6271) );
NAND2X2TS U5910 ( .A(FPSENCOS_cont_iter_out[2]), .B(n6247), .Y(n6246) );
BUFX3TS U5911 ( .A(n4359), .Y(n6432) );
XNOR2X1TS U5912 ( .A(n2268), .B(FPSENCOS_d_ff1_operation_out), .Y(n4358) );
CLKXOR2X2TS U5913 ( .A(n6428), .B(n4358), .Y(n6427) );
INVX2TS U5914 ( .A(n6427), .Y(n6426) );
NOR2X2TS U5915 ( .A(n4359), .B(n6426), .Y(n4392) );
NOR2X2TS U5916 ( .A(n2305), .B(n2224), .Y(n4415) );
NAND2X2TS U5917 ( .A(n6437), .B(n6631), .Y(n4418) );
OAI21X4TS U5918 ( .A0(n4415), .A1(n4418), .B0(n4416), .Y(n4367) );
OAI21X1TS U5919 ( .A0(n4368), .A1(n4375), .B0(n4369), .Y(n4361) );
NOR2X2TS U5920 ( .A(n5498), .B(n6448), .Y(n4383) );
INVX2TS U5921 ( .A(n4383), .Y(n4363) );
NAND2X1TS U5922 ( .A(n4363), .B(n4382), .Y(n4364) );
XOR2X1TS U5923 ( .A(n4384), .B(n4364), .Y(n4365) );
INVX2TS U5924 ( .A(n4366), .Y(n5463) );
OAI21X2TS U5925 ( .A0(n4378), .A1(n4374), .B0(n4375), .Y(n4372) );
INVX2TS U5926 ( .A(n4368), .Y(n4370) );
CLKXOR2X4TS U5927 ( .A(n4372), .B(n4371), .Y(n5474) );
ADDHXLTS U5928 ( .A(n5495), .B(DP_OP_501J1_127_1459_n939), .CO(n4373), .S(
n4366) );
INVX2TS U5929 ( .A(n4373), .Y(n5462) );
OAI22X1TS U5930 ( .A0(n2313), .A1(n5463), .B0(n5474), .B1(n5462), .Y(n4391)
);
INVX2TS U5931 ( .A(n4374), .Y(n4376) );
OAI22X1TS U5932 ( .A0(n5474), .A1(n2346), .B0(n2314), .B1(n2442), .Y(n4428)
);
INVX2TS U5933 ( .A(n6450), .Y(n4379) );
INVX2TS U5934 ( .A(n4381), .Y(n5469) );
OAI21X1TS U5935 ( .A0(n4384), .A1(n4383), .B0(n4382), .Y(n4385) );
XNOR2X1TS U5936 ( .A(n4385), .B(n6450), .Y(n4386) );
INVX4TS U5937 ( .A(n4386), .Y(n5472) );
INVX2TS U5938 ( .A(n4387), .Y(n5465) );
ADDHXLTS U5939 ( .A(n6927), .B(n2278), .CO(n4388), .S(n4387) );
INVX2TS U5940 ( .A(n4388), .Y(n5464) );
OAI22X1TS U5941 ( .A0(n5472), .A1(n5465), .B0(n2313), .B1(n5464), .Y(n4389)
);
BUFX3TS U5942 ( .A(n4392), .Y(n4400) );
BUFX3TS U5943 ( .A(n4360), .Y(n4399) );
BUFX3TS U5944 ( .A(n4392), .Y(n4395) );
BUFX3TS U5945 ( .A(n4360), .Y(n4394) );
BUFX3TS U5946 ( .A(n4359), .Y(n4401) );
BUFX3TS U5947 ( .A(n4392), .Y(n4397) );
BUFX3TS U5948 ( .A(n4360), .Y(n4396) );
BUFX3TS U5949 ( .A(n4359), .Y(n4398) );
INVX2TS U5950 ( .A(n2439), .Y(n5263) );
AOI222X1TS U5951 ( .A0(n5262), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n6727),
.B1(n5294), .C0(n6544), .C1(n5263), .Y(n7082) );
AOI21X1TS U5952 ( .A0(n5201), .A1(FPADDSUB_Data_array_SWR[0]), .B0(n4404),
.Y(n4407) );
AOI222X1TS U5953 ( .A0(n5262), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n6659),
.B1(n5294), .C0(FPADDSUB_intDX_EWSW[24]), .C1(n5263), .Y(n7083) );
NAND2X1TS U5954 ( .A(n4410), .B(n4409), .Y(n4411) );
INVX2TS U5955 ( .A(n4421), .Y(n5157) );
NOR2X1TS U5956 ( .A(n5157), .B(n5463), .Y(n4423) );
INVX2TS U5957 ( .A(n4415), .Y(n4417) );
OAI22X1TS U5958 ( .A0(n5467), .A1(n5465), .B0(n5461), .B1(n5464), .Y(n4422)
);
INVX2TS U5959 ( .A(n4426), .Y(n5466) );
OAI22X1TS U5960 ( .A0(n5476), .A1(n2347), .B0(n5474), .B1(n2442), .Y(n4430)
);
ADDHXLTS U5961 ( .A(n4428), .B(n4427), .CO(n4429), .S(n4390) );
CMPR32X2TS U5962 ( .A(n4431), .B(n4430), .C(n4429), .CO(
DP_OP_500J1_126_2852_n106), .S(DP_OP_500J1_126_2852_n107) );
BUFX3TS U5963 ( .A(n5065), .Y(n7022) );
OAI22X1TS U5964 ( .A0(n5394), .A1(n5390), .B0(n4625), .B1(n5389), .Y(n4432)
);
OAI22X1TS U5965 ( .A0(n2312), .A1(n5392), .B0(n2366), .B1(n5391), .Y(n4436)
);
ADDHXLTS U5966 ( .A(n4433), .B(n4432), .CO(DP_OP_502J1_128_2852_n132), .S(
n4435) );
OAI22X1TS U5967 ( .A0(n5400), .A1(n5395), .B0(n2312), .B1(n5393), .Y(n4434)
);
BUFX3TS U5968 ( .A(n5894), .Y(n6106) );
NAND2X1TS U5969 ( .A(n6643), .B(n6694), .Y(n4590) );
NAND2X1TS U5970 ( .A(n6679), .B(FPADDSUB_DMP_SFG[0]), .Y(n4437) );
NOR2X1TS U5971 ( .A(n6677), .B(FPADDSUB_DMP_SFG[1]), .Y(n4578) );
NOR2X1TS U5972 ( .A(n6672), .B(FPADDSUB_DMP_SFG[2]), .Y(n4440) );
NAND2X1TS U5973 ( .A(n6677), .B(FPADDSUB_DMP_SFG[1]), .Y(n4577) );
NAND2X1TS U5974 ( .A(n6672), .B(FPADDSUB_DMP_SFG[2]), .Y(n4439) );
AOI21X1TS U5975 ( .A0(n4568), .A1(n4442), .B0(n4441), .Y(n4594) );
NOR2X1TS U5976 ( .A(n6676), .B(FPADDSUB_DMP_SFG[3]), .Y(n5909) );
NOR2X1TS U5977 ( .A(n6674), .B(FPADDSUB_DMP_SFG[4]), .Y(n4444) );
NOR2X1TS U5978 ( .A(n5909), .B(n4444), .Y(n5896) );
NOR2X1TS U5979 ( .A(n6675), .B(FPADDSUB_DMP_SFG[5]), .Y(n6092) );
NOR2X1TS U5980 ( .A(n6673), .B(FPADDSUB_DMP_SFG[6]), .Y(n4446) );
NOR2X1TS U5981 ( .A(n6092), .B(n4446), .Y(n4448) );
NAND2X1TS U5982 ( .A(n5896), .B(n4448), .Y(n4450) );
NAND2X1TS U5983 ( .A(n6676), .B(FPADDSUB_DMP_SFG[3]), .Y(n5910) );
NAND2X1TS U5984 ( .A(n6674), .B(FPADDSUB_DMP_SFG[4]), .Y(n4443) );
OAI21X1TS U5985 ( .A0(n4444), .A1(n5910), .B0(n4443), .Y(n5895) );
NAND2X1TS U5986 ( .A(n6675), .B(FPADDSUB_DMP_SFG[5]), .Y(n6091) );
NAND2X1TS U5987 ( .A(n6673), .B(FPADDSUB_DMP_SFG[6]), .Y(n4445) );
AOI21X1TS U5988 ( .A0(n5895), .A1(n4448), .B0(n4447), .Y(n4449) );
NOR2X1TS U5989 ( .A(n6678), .B(FPADDSUB_DMP_SFG[7]), .Y(n5924) );
NOR2X1TS U5990 ( .A(n6777), .B(FPADDSUB_DMP_SFG[8]), .Y(n4452) );
NOR2X1TS U5991 ( .A(n5924), .B(n4452), .Y(n5943) );
NAND2X1TS U5992 ( .A(n5943), .B(n4454), .Y(n6076) );
NOR2X1TS U5993 ( .A(n6781), .B(FPADDSUB_DMP_SFG[10]), .Y(n4456) );
NAND2X1TS U5994 ( .A(n6678), .B(FPADDSUB_DMP_SFG[7]), .Y(n5923) );
NAND2X1TS U5995 ( .A(n6777), .B(FPADDSUB_DMP_SFG[8]), .Y(n4451) );
OAI21X1TS U5996 ( .A0(n4452), .A1(n5923), .B0(n4451), .Y(n5944) );
AOI21X1TS U5997 ( .A0(n5944), .A1(n4454), .B0(n4453), .Y(n6075) );
NAND2X1TS U5998 ( .A(n6781), .B(FPADDSUB_DMP_SFG[10]), .Y(n4455) );
NAND2X1TS U5999 ( .A(n6780), .B(FPADDSUB_DMP_SFG[11]), .Y(n4459) );
AOI21X4TS U6000 ( .A0(n6057), .A1(n4462), .B0(n4461), .Y(n5971) );
NOR2X1TS U6001 ( .A(n6779), .B(FPADDSUB_DMP_SFG[13]), .Y(n4464) );
NAND2X1TS U6002 ( .A(n6779), .B(FPADDSUB_DMP_SFG[13]), .Y(n4463) );
OAI21X4TS U6003 ( .A0(n5971), .A1(n4464), .B0(n4463), .Y(n5961) );
AOI21X4TS U6004 ( .A0(n5961), .A1(n4466), .B0(n4465), .Y(n5981) );
NOR2X1TS U6005 ( .A(n6700), .B(FPADDSUB_DMP_SFG[15]), .Y(n4468) );
NAND2X1TS U6006 ( .A(n6700), .B(FPADDSUB_DMP_SFG[15]), .Y(n4467) );
OAI21X4TS U6007 ( .A0(n5981), .A1(n4468), .B0(n4467), .Y(n6048) );
AOI21X4TS U6008 ( .A0(n6048), .A1(n4470), .B0(n4469), .Y(n5991) );
NOR2X1TS U6009 ( .A(n6778), .B(FPADDSUB_DMP_SFG[17]), .Y(n4472) );
NAND2X1TS U6010 ( .A(n6778), .B(FPADDSUB_DMP_SFG[17]), .Y(n4471) );
OAI21X4TS U6011 ( .A0(n5991), .A1(n4472), .B0(n4471), .Y(n6011) );
AOI21X4TS U6012 ( .A0(n6011), .A1(n4474), .B0(n4473), .Y(n6001) );
NOR2X1TS U6013 ( .A(n6721), .B(FPADDSUB_DMP_SFG[19]), .Y(n4476) );
NAND2X1TS U6014 ( .A(n6721), .B(FPADDSUB_DMP_SFG[19]), .Y(n4475) );
OAI21X4TS U6015 ( .A0(n6001), .A1(n4476), .B0(n4475), .Y(n6028) );
NAND2X1TS U6016 ( .A(n6733), .B(FPADDSUB_DMP_SFG[21]), .Y(n4479) );
NAND2X1TS U6017 ( .A(n4482), .B(n4481), .Y(n4484) );
INVX2TS U6018 ( .A(n4484), .Y(n4483) );
XNOR2X1TS U6019 ( .A(n6019), .B(n4483), .Y(n4488) );
XNOR2X1TS U6020 ( .A(n4485), .B(n4484), .Y(n4486) );
BUFX3TS U6021 ( .A(n4565), .Y(n6031) );
AOI22X1TS U6022 ( .A0(n4486), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n2325), .Y(n4487) );
OAI2BB1X1TS U6023 ( .A0N(n6106), .A1N(n4488), .B0(n4487), .Y(n1315) );
AOI2BB1X1TS U6024 ( .A0N(n6900), .A1N(n2200), .B0(n6899), .Y(n4635) );
NOR2X1TS U6025 ( .A(n6176), .B(n4635), .Y(n7025) );
NOR2X1TS U6026 ( .A(n5312), .B(n6434), .Y(n4489) );
NOR2X2TS U6027 ( .A(n4489), .B(n6644), .Y(n5812) );
BUFX3TS U6028 ( .A(n4641), .Y(n4783) );
NOR2X2TS U6029 ( .A(FPMULT_FSM_selector_C), .B(n4783), .Y(n4634) );
NAND2X1TS U6030 ( .A(FPMULT_FSM_selector_C), .B(n5812), .Y(n4490) );
NOR2X2TS U6031 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n5874), .Y(n5832)
);
INVX2TS U6032 ( .A(n5832), .Y(n5824) );
AOI211X1TS U6033 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n5831), .B0(
n4492), .C0(n4491), .Y(n4499) );
OAI22X1TS U6034 ( .A0(n4500), .A1(n5824), .B0(n4499), .B1(n5855), .Y(n4493)
);
NOR2X4TS U6035 ( .A(n5882), .B(n5892), .Y(n5821) );
NAND2X1TS U6036 ( .A(n2351), .B(n5850), .Y(n5825) );
NAND2BX2TS U6037 ( .AN(n6487), .B(n5825), .Y(n5834) );
BUFX3TS U6038 ( .A(n5821), .Y(n5878) );
OA22X1TS U6039 ( .A0(n4493), .A1(n5834), .B0(n5878), .B1(
FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n1180) );
AOI21X1TS U6040 ( .A0(operation[1]), .A1(ack_operation), .B0(n6216), .Y(
n5019) );
AOI22X1TS U6041 ( .A0(n2206), .A1(n5489), .B0(n2370), .B1(
DP_OP_501J1_127_1459_n952), .Y(n4498) );
NAND2X1TS U6042 ( .A(n2370), .B(FPMULT_Op_MX[9]), .Y(n4930) );
NAND2X1TS U6043 ( .A(n6455), .B(n2228), .Y(n4931) );
NAND2X1TS U6044 ( .A(n6442), .B(DP_OP_501J1_127_1459_n952), .Y(n4929) );
OAI21X1TS U6045 ( .A0(n4930), .A1(n4931), .B0(n4494), .Y(n4497) );
NAND2X1TS U6046 ( .A(n4496), .B(n4495), .Y(intadd_1_B_7_) );
OAI2BB2XLTS U6047 ( .B0(intadd_1_B_7_), .B1(n4498), .A0N(n4497), .A1N(n4496),
.Y(intadd_1_B_6_) );
NAND2X2TS U6048 ( .A(n6584), .B(n6485), .Y(n5872) );
INVX2TS U6049 ( .A(n5872), .Y(n5875) );
OA22X1TS U6050 ( .A0(n4502), .A1(n4501), .B0(n5878), .B1(
FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n1205) );
INVX2TS U6051 ( .A(n4503), .Y(n4505) );
NAND2X1TS U6052 ( .A(n4505), .B(n4504), .Y(n4506) );
XOR2X1TS U6053 ( .A(n4507), .B(n4506), .Y(n4508) );
OAI22X1TS U6054 ( .A0(n2317), .A1(n5388), .B0(n5400), .B1(n5386), .Y(n4510)
);
CMPR32X2TS U6055 ( .A(n4511), .B(n4510), .C(n4509), .CO(
DP_OP_502J1_128_2852_n106), .S(DP_OP_502J1_128_2852_n107) );
XNOR2X1TS U6056 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n4520) );
INVX2TS U6057 ( .A(n4520), .Y(n6474) );
OR4X2TS U6058 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[17]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[16]), .Y(n4518) );
NOR4X1TS U6059 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[21]), .C(
FPMULT_P_Sgf[18]), .D(FPMULT_P_Sgf[19]), .Y(n4516) );
NOR4X1TS U6060 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[2]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n4512) );
NOR4BX1TS U6061 ( .AN(n4512), .B(FPMULT_P_Sgf[22]), .C(FPMULT_P_Sgf[0]), .D(
FPMULT_P_Sgf[5]), .Y(n4515) );
NOR4X1TS U6062 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_P_Sgf[10]), .C(
FPMULT_P_Sgf[14]), .D(FPMULT_P_Sgf[12]), .Y(n4514) );
NOR4X1TS U6063 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .C(
FPMULT_P_Sgf[7]), .D(FPMULT_P_Sgf[11]), .Y(n4513) );
OAI22X1TS U6064 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n4518), .B1(n4517),
.Y(n4519) );
AOI221X1TS U6065 ( .A0(r_mode[1]), .A1(n6474), .B0(r_mode[0]), .B1(n4520),
.C0(n4519), .Y(n5313) );
NAND2X1TS U6066 ( .A(n4521), .B(FPMULT_FS_Module_state_reg[3]), .Y(n5814) );
BUFX3TS U6067 ( .A(n6311), .Y(n7023) );
AOI21X2TS U6068 ( .A0(n2301), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4525),
.Y(n5870) );
OAI22X1TS U6069 ( .A0(n5870), .A1(n6637), .B0(n6714), .B1(n5842), .Y(n4526)
);
AOI211X1TS U6070 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2345), .B0(n4527),
.C0(n4526), .Y(n5861) );
OAI22X1TS U6071 ( .A0(n5860), .A1(n5824), .B0(n5861), .B1(n5855), .Y(n6514)
);
BUFX3TS U6072 ( .A(n5821), .Y(n5862) );
OA22X1TS U6073 ( .A0(n6514), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n1187) );
BUFX3TS U6074 ( .A(n6278), .Y(n6330) );
OR2X1TS U6075 ( .A(FPSENCOS_d_ff3_LUT_out[27]), .B(n6330), .Y(n2113) );
INVX2TS U6076 ( .A(n6839), .Y(n6614) );
BUFX3TS U6077 ( .A(n6839), .Y(n6608) );
NOR2X1TS U6078 ( .A(n6645), .B(n6921), .Y(n7029) );
NAND2X1TS U6079 ( .A(n6450), .B(n2347), .Y(intadd_0_A_7_) );
NOR2X1TS U6080 ( .A(n6688), .B(n6860), .Y(n7027) );
NAND2X1TS U6081 ( .A(FPMULT_Op_MX[5]), .B(n6439), .Y(intadd_2_A_7_) );
INVX2TS U6082 ( .A(n6241), .Y(n6249) );
NAND2X1TS U6083 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6249), .Y(n4679) );
INVX2TS U6084 ( .A(n4679), .Y(n4858) );
AOI22X1TS U6085 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n6272), .B0(n4858),
.B1(n4667), .Y(n4530) );
NAND2X1TS U6086 ( .A(n4530), .B(n4678), .Y(n2133) );
NOR2X1TS U6087 ( .A(n6630), .B(n6664), .Y(n7028) );
AOI211X1TS U6088 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n5826), .B0(
n4532), .C0(n4531), .Y(n5869) );
OAI22X1TS U6089 ( .A0(n5869), .A1(n2267), .B0(n5868), .B1(n5824), .Y(n6507)
);
OA22X1TS U6090 ( .A0(n6507), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n1183) );
AOI211X1TS U6091 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n5829), .B0(
n4534), .C0(n4533), .Y(n5873) );
OAI22X1TS U6092 ( .A0(n5873), .A1(n2267), .B0(n5877), .B1(n5824), .Y(n6490)
);
OA22X1TS U6093 ( .A0(n6490), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1181) );
NOR2X1TS U6094 ( .A(n4686), .B(n4535), .Y(n5017) );
NAND4BX1TS U6095 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(n4537), .D(n4536), .Y(
n5016) );
NOR2BX1TS U6096 ( .AN(n5017), .B(n5016), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
NOR2X4TS U6097 ( .A(operation[1]), .B(n4960), .Y(n4940) );
CLKBUFX2TS U6098 ( .A(n4940), .Y(n6420) );
AOI22X1TS U6099 ( .A0(Data_2[30]), .A1(n6420), .B0(FPADDSUB_intDY_EWSW[30]),
.B1(n4538), .Y(n4541) );
NOR3X2TS U6100 ( .A(FPSENCOS_cont_var_out[1]), .B(n6710), .C(n4941), .Y(
n4539) );
AOI22X1TS U6101 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[30]), .B0(n5041),
.B1(FPSENCOS_d_ff3_sh_y_out[30]), .Y(n4540) );
NAND2X1TS U6102 ( .A(n4541), .B(n4540), .Y(n1813) );
OA22X1TS U6103 ( .A0(n6489), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(n6606),
.B1(result_add_subt[23]), .Y(n1473) );
OA22X1TS U6104 ( .A0(n6489), .A1(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B0(n6606),
.B1(result_add_subt[24]), .Y(n1472) );
OAI2BB2XLTS U6105 ( .B0(n5860), .B1(n6637), .A0N(FPADDSUB_Data_array_SWR[10]), .A1N(n2321), .Y(n4542) );
AOI211X1TS U6106 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n2343), .B0(n4543),
.C0(n4542), .Y(n5871) );
OAI22X1TS U6107 ( .A0(n5871), .A1(n5855), .B0(n5870), .B1(n5824), .Y(n6501)
);
OA22X1TS U6108 ( .A0(n6501), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n1182) );
INVX2TS U6109 ( .A(result_add_subt[30]), .Y(n6417) );
OAI2BB2XLTS U6110 ( .B0(n5892), .B1(n6417), .A0N(
FPADDSUB_exp_rslt_NRM2_EW1[7]), .A1N(n5887), .Y(n1466) );
NAND2X1TS U6111 ( .A(n6640), .B(n6633), .Y(n4545) );
NAND2X1TS U6112 ( .A(DP_OP_501J1_127_1459_n939), .B(n6662), .Y(n4544) );
NOR2X2TS U6113 ( .A(n4545), .B(n4544), .Y(n5115) );
INVX2TS U6114 ( .A(FPMULT_Op_MX[20]), .Y(n5537) );
NOR3X2TS U6115 ( .A(n4545), .B(n6665), .C(n5537), .Y(n5502) );
NAND2X1TS U6116 ( .A(n5528), .B(n2323), .Y(n5107) );
NAND2X1TS U6117 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[19]), .Y(n5106) );
XNOR2X1TS U6118 ( .A(n5107), .B(n5106), .Y(n4546) );
NAND2X2TS U6119 ( .A(n5500), .B(n2304), .Y(n5142) );
INVX2TS U6120 ( .A(n5142), .Y(n5135) );
XOR2X1TS U6121 ( .A(n4546), .B(n5135), .Y(n5504) );
OAI2BB2XLTS U6122 ( .B0(n4547), .B1(n5504), .A0N(n5502), .A1N(n5503), .Y(
mult_x_309_n36) );
NOR2X1TS U6123 ( .A(n6709), .B(n4550), .Y(n4549) );
AOI211X2TS U6124 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2301), .B0(n4552),
.C0(n4549), .Y(n5866) );
NOR2X1TS U6125 ( .A(n2449), .B(n4550), .Y(n4551) );
AOI211X2TS U6126 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2301), .B0(n4552),
.C0(n4551), .Y(n5864) );
OAI2BB2XLTS U6127 ( .B0(n5864), .B1(n6637), .A0N(FPADDSUB_Data_array_SWR[8]),
.A1N(n2342), .Y(n4553) );
AOI211X1TS U6128 ( .A0(FPADDSUB_Data_array_SWR[4]), .A1(n2345), .B0(n4554),
.C0(n4553), .Y(n5867) );
OAI22X1TS U6129 ( .A0(n5866), .A1(n5824), .B0(n5867), .B1(n2351), .Y(n6504)
);
OA22X1TS U6130 ( .A0(n6504), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n1184) );
CLKBUFX3TS U6131 ( .A(n2302), .Y(n6984) );
INVX2TS U6132 ( .A(n5321), .Y(n6223) );
CLKBUFX3TS U6133 ( .A(n4621), .Y(n4557) );
BUFX3TS U6134 ( .A(n4557), .Y(n6948) );
BUFX3TS U6135 ( .A(n6980), .Y(n6972) );
CLKBUFX3TS U6136 ( .A(n4621), .Y(n4558) );
BUFX3TS U6137 ( .A(n4558), .Y(n6959) );
BUFX3TS U6138 ( .A(n6981), .Y(n6971) );
BUFX3TS U6139 ( .A(n4558), .Y(n6958) );
BUFX3TS U6140 ( .A(n6989), .Y(n6973) );
BUFX3TS U6141 ( .A(n4561), .Y(n6970) );
BUFX3TS U6142 ( .A(n4555), .Y(n6952) );
BUFX3TS U6143 ( .A(n4558), .Y(n6960) );
BUFX3TS U6144 ( .A(n4557), .Y(n6963) );
CLKBUFX3TS U6145 ( .A(n4621), .Y(n4562) );
BUFX3TS U6146 ( .A(n4562), .Y(n6934) );
BUFX3TS U6147 ( .A(n4557), .Y(n6961) );
BUFX3TS U6148 ( .A(n4555), .Y(n6951) );
BUFX3TS U6149 ( .A(n6984), .Y(n6969) );
BUFX3TS U6150 ( .A(n4557), .Y(n6962) );
BUFX3TS U6151 ( .A(n6981), .Y(n6968) );
BUFX3TS U6152 ( .A(n4562), .Y(n6950) );
CLKBUFX3TS U6153 ( .A(n6979), .Y(n6985) );
CLKBUFX2TS U6154 ( .A(n2303), .Y(n4559) );
BUFX3TS U6155 ( .A(n4560), .Y(n6982) );
CLKBUFX2TS U6156 ( .A(n2303), .Y(n4563) );
BUFX3TS U6157 ( .A(n6981), .Y(n6983) );
BUFX3TS U6158 ( .A(n4555), .Y(n6954) );
BUFX3TS U6159 ( .A(n4555), .Y(n6946) );
CLKBUFX3TS U6160 ( .A(n2303), .Y(n6989) );
BUFX3TS U6161 ( .A(n4555), .Y(n6953) );
BUFX3TS U6162 ( .A(n4558), .Y(n6936) );
BUFX3TS U6163 ( .A(n4562), .Y(n6943) );
CLKBUFX2TS U6164 ( .A(n2303), .Y(n7010) );
BUFX3TS U6165 ( .A(n6997), .Y(n6988) );
BUFX3TS U6166 ( .A(n4558), .Y(n6942) );
BUFX3TS U6167 ( .A(n4557), .Y(n6941) );
BUFX3TS U6168 ( .A(n4557), .Y(n6965) );
BUFX3TS U6169 ( .A(n6989), .Y(n6987) );
BUFX3TS U6170 ( .A(n6984), .Y(n6986) );
BUFX3TS U6171 ( .A(n4557), .Y(n6937) );
BUFX3TS U6172 ( .A(n4558), .Y(n6938) );
BUFX3TS U6173 ( .A(n4558), .Y(n6956) );
BUFX3TS U6174 ( .A(n4556), .Y(n7014) );
BUFX3TS U6175 ( .A(n6980), .Y(n7002) );
BUFX3TS U6176 ( .A(n4556), .Y(n7018) );
BUFX3TS U6177 ( .A(n4556), .Y(n7017) );
BUFX3TS U6178 ( .A(n6920), .Y(n7011) );
BUFX3TS U6179 ( .A(n6920), .Y(n7013) );
BUFX3TS U6180 ( .A(n7013), .Y(n7015) );
BUFX3TS U6181 ( .A(n4561), .Y(n7001) );
CLKBUFX3TS U6182 ( .A(n4562), .Y(n6929) );
BUFX3TS U6183 ( .A(n6984), .Y(n7000) );
BUFX3TS U6184 ( .A(n4557), .Y(n6964) );
BUFX3TS U6185 ( .A(n4558), .Y(n6957) );
BUFX3TS U6186 ( .A(n6980), .Y(n6994) );
BUFX3TS U6187 ( .A(n4559), .Y(n6993) );
BUFX3TS U6188 ( .A(n6989), .Y(n6992) );
BUFX3TS U6189 ( .A(n4561), .Y(n6967) );
BUFX3TS U6190 ( .A(n6984), .Y(n6991) );
BUFX3TS U6191 ( .A(n2384), .Y(n6990) );
BUFX3TS U6192 ( .A(n6984), .Y(n6996) );
CLKBUFX3TS U6193 ( .A(n2384), .Y(n7009) );
BUFX3TS U6194 ( .A(n6984), .Y(n7008) );
BUFX3TS U6195 ( .A(n4561), .Y(n7007) );
BUFX3TS U6196 ( .A(n4560), .Y(n7005) );
BUFX3TS U6197 ( .A(n4558), .Y(n6955) );
BUFX3TS U6198 ( .A(n4562), .Y(n6928) );
BUFX3TS U6199 ( .A(n6980), .Y(n7004) );
BUFX3TS U6200 ( .A(n6980), .Y(n6995) );
BUFX3TS U6201 ( .A(n6981), .Y(n7006) );
BUFX3TS U6202 ( .A(n2303), .Y(n6980) );
BUFX3TS U6203 ( .A(n6989), .Y(n6974) );
BUFX3TS U6204 ( .A(n2303), .Y(n6981) );
BUFX3TS U6205 ( .A(n6989), .Y(n7003) );
BUFX3TS U6206 ( .A(n6997), .Y(n6975) );
BUFX3TS U6207 ( .A(n6997), .Y(n6977) );
BUFX3TS U6208 ( .A(n4562), .Y(n6932) );
BUFX3TS U6209 ( .A(n4562), .Y(n6930) );
BUFX3TS U6210 ( .A(n2385), .Y(n6978) );
BUFX3TS U6211 ( .A(n4562), .Y(n6931) );
BUFX3TS U6212 ( .A(n4560), .Y(n6976) );
BUFX3TS U6213 ( .A(n4560), .Y(n6999) );
BUFX3TS U6214 ( .A(n4562), .Y(n6933) );
BUFX3TS U6215 ( .A(n6989), .Y(n6998) );
BUFX3TS U6216 ( .A(n7013), .Y(n7016) );
INVX2TS U6217 ( .A(n6592), .Y(n6599) );
BUFX3TS U6218 ( .A(n6610), .Y(n6486) );
OAI21XLTS U6219 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n6667), .B0(n2350),
.Y(n1350) );
INVX2TS U6220 ( .A(n6256), .Y(n4564) );
INVX2TS U6221 ( .A(result_add_subt[14]), .Y(n6526) );
INVX2TS U6222 ( .A(n6256), .Y(n6257) );
OAI2BB2XLTS U6223 ( .B0(n4564), .B1(n6526), .A0N(n6257), .A1N(
FPSENCOS_d_ff_Zn[14]), .Y(n2032) );
INVX2TS U6224 ( .A(n6256), .Y(n6411) );
INVX2TS U6225 ( .A(result_add_subt[11]), .Y(n6522) );
OAI2BB2XLTS U6226 ( .B0(n6411), .B1(n6522), .A0N(n6257), .A1N(
FPSENCOS_d_ff_Zn[11]), .Y(n2041) );
INVX2TS U6227 ( .A(result_add_subt[20]), .Y(n6509) );
INVX2TS U6228 ( .A(n6256), .Y(n6262) );
OAI2BB2XLTS U6229 ( .B0(n4564), .B1(n6509), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[20]), .Y(n2014) );
INVX2TS U6230 ( .A(result_add_subt[16]), .Y(n6516) );
OAI2BB2XLTS U6231 ( .B0(n4564), .B1(n6516), .A0N(n6257), .A1N(
FPSENCOS_d_ff_Zn[16]), .Y(n2026) );
INVX2TS U6232 ( .A(result_add_subt[21]), .Y(n6503) );
INVX2TS U6233 ( .A(n6256), .Y(n6402) );
OAI2BB2XLTS U6234 ( .B0(n4564), .B1(n6503), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[21]), .Y(n2011) );
INVX2TS U6235 ( .A(result_add_subt[18]), .Y(n6499) );
OAI2BB2XLTS U6236 ( .B0(n4564), .B1(n6499), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[18]), .Y(n2020) );
INVX2TS U6237 ( .A(result_add_subt[17]), .Y(n6511) );
OAI2BB2XLTS U6238 ( .B0(n4564), .B1(n6511), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[17]), .Y(n2023) );
INVX2TS U6239 ( .A(result_add_subt[8]), .Y(n6520) );
OAI2BB2XLTS U6240 ( .B0(n6411), .B1(n6520), .A0N(n6257), .A1N(
FPSENCOS_d_ff_Zn[8]), .Y(n2050) );
INVX2TS U6241 ( .A(result_add_subt[5]), .Y(n6605) );
OAI2BB2XLTS U6242 ( .B0(n6411), .B1(n6605), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[5]), .Y(n2059) );
INVX2TS U6243 ( .A(result_add_subt[12]), .Y(n6530) );
OAI2BB2XLTS U6244 ( .B0(n4564), .B1(n6530), .A0N(n6257), .A1N(
FPSENCOS_d_ff_Zn[12]), .Y(n2038) );
INVX2TS U6245 ( .A(result_add_subt[10]), .Y(n6528) );
OAI2BB2XLTS U6246 ( .B0(n6411), .B1(n6528), .A0N(n6257), .A1N(
FPSENCOS_d_ff_Zn[10]), .Y(n2044) );
INVX2TS U6247 ( .A(result_add_subt[19]), .Y(n6506) );
OAI2BB2XLTS U6248 ( .B0(n4564), .B1(n6506), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[19]), .Y(n2017) );
INVX2TS U6249 ( .A(result_add_subt[13]), .Y(n6513) );
OAI2BB2XLTS U6250 ( .B0(n4564), .B1(n6513), .A0N(n6257), .A1N(
FPSENCOS_d_ff_Zn[13]), .Y(n2035) );
INVX2TS U6251 ( .A(result_add_subt[15]), .Y(n6496) );
OAI2BB2XLTS U6252 ( .B0(n4564), .B1(n6496), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[15]), .Y(n2029) );
INVX2TS U6253 ( .A(result_add_subt[9]), .Y(n6601) );
OAI2BB2XLTS U6254 ( .B0(n6411), .B1(n6601), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[9]), .Y(n2047) );
INVX2TS U6255 ( .A(result_add_subt[3]), .Y(n6587) );
OAI2BB2XLTS U6256 ( .B0(n6257), .B1(n6587), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[3]), .Y(n2065) );
INVX2TS U6257 ( .A(result_add_subt[2]), .Y(n6590) );
OAI2BB2XLTS U6258 ( .B0(n6257), .B1(n6590), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[2]), .Y(n2068) );
XNOR2X1TS U6259 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n6694), .Y(n4567) );
BUFX3TS U6260 ( .A(n4565), .Y(n6102) );
AOI22X1TS U6261 ( .A0(n6102), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n6101), .Y(n4566) );
OAI2BB1X1TS U6262 ( .A0N(n5894), .A1N(n4567), .B0(n4566), .Y(n1348) );
INVX2TS U6263 ( .A(n4568), .Y(n4579) );
INVX2TS U6264 ( .A(n4569), .Y(n4571) );
NAND2X1TS U6265 ( .A(n4571), .B(n4570), .Y(n4573) );
INVX2TS U6266 ( .A(n4573), .Y(n4572) );
XOR2X1TS U6267 ( .A(n4573), .B(n4588), .Y(n4574) );
AOI22X1TS U6268 ( .A0(n4574), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n6101), .Y(n4575) );
OAI2BB1X1TS U6269 ( .A0N(n5894), .A1N(n4576), .B0(n4575), .Y(n1346) );
INVX2TS U6270 ( .A(n4600), .Y(n4580) );
NAND2X1TS U6271 ( .A(n4580), .B(n4599), .Y(n4584) );
INVX2TS U6272 ( .A(n4584), .Y(n4581) );
XNOR2X1TS U6273 ( .A(n4582), .B(n4581), .Y(n4587) );
XOR2X1TS U6274 ( .A(n4601), .B(n4584), .Y(n4585) );
AOI22X1TS U6275 ( .A0(n4585), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n6101), .Y(n4586) );
OAI2BB1X1TS U6276 ( .A0N(n5894), .A1N(n4587), .B0(n4586), .Y(n1345) );
OR2X1TS U6277 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4589) );
AOI22X1TS U6278 ( .A0(n4591), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n6101), .Y(n4592) );
OAI2BB1X1TS U6279 ( .A0N(n5894), .A1N(n4593), .B0(n4592), .Y(n1347) );
INVX2TS U6280 ( .A(n4594), .Y(n5913) );
INVX2TS U6281 ( .A(n4595), .Y(n4597) );
NAND2X1TS U6282 ( .A(n4597), .B(n4596), .Y(n4602) );
INVX2TS U6283 ( .A(n4602), .Y(n4598) );
XNOR2X1TS U6284 ( .A(n5913), .B(n4598), .Y(n4606) );
XNOR2X1TS U6285 ( .A(n4603), .B(n4602), .Y(n4604) );
AOI22X1TS U6286 ( .A0(n4604), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n6101), .Y(n4605) );
OAI2BB1X1TS U6287 ( .A0N(n5894), .A1N(n4606), .B0(n4605), .Y(n1344) );
BUFX3TS U6288 ( .A(n5821), .Y(n6576) );
AND3X1TS U6289 ( .A(n6208), .B(n5321), .C(n6717), .Y(n6225) );
OAI21XLTS U6290 ( .A0(n6225), .A1(n6710), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4607) );
OAI2BB2XLTS U6291 ( .B0(n6332), .B1(n2390), .A0N(n6330), .A1N(
intadd_6_SUM_2_), .Y(n1948) );
OAI2BB2XLTS U6292 ( .B0(n6332), .B1(n2407), .A0N(n6330), .A1N(
intadd_6_SUM_0_), .Y(n1950) );
OAI2BB2XLTS U6293 ( .B0(n6332), .B1(n2389), .A0N(n6330), .A1N(
intadd_6_SUM_1_), .Y(n1949) );
BUFX3TS U6294 ( .A(n6275), .Y(n6335) );
INVX2TS U6295 ( .A(n6275), .Y(n6412) );
BUFX3TS U6296 ( .A(n6301), .Y(n6413) );
NOR2X2TS U6297 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_6_n1), .Y(n6276) );
NAND2X1TS U6298 ( .A(n6276), .B(n6728), .Y(n6280) );
INVX2TS U6299 ( .A(n6278), .Y(n6283) );
NAND2X1TS U6300 ( .A(n6270), .B(n7048), .Y(intadd_5_CI) );
CLKBUFX2TS U6301 ( .A(n6275), .Y(n6264) );
OAI2BB2XLTS U6302 ( .B0(n6335), .B1(n2421), .A0N(n6264), .A1N(
FPSENCOS_d_ff2_X[1]), .Y(n2002) );
OAI2BB2XLTS U6303 ( .B0(n6332), .B1(n2396), .A0N(n6264), .A1N(
FPSENCOS_d_ff2_X[10]), .Y(n1984) );
OAI2BB2XLTS U6304 ( .B0(n6335), .B1(n2412), .A0N(n6264), .A1N(
FPSENCOS_d_ff2_X[6]), .Y(n1992) );
OAI2BB2XLTS U6305 ( .B0(n6335), .B1(n2420), .A0N(n6264), .A1N(
FPSENCOS_d_ff2_X[0]), .Y(n2004) );
OAI2BB2XLTS U6306 ( .B0(n6335), .B1(n2419), .A0N(n6264), .A1N(
FPSENCOS_d_ff2_X[2]), .Y(n2000) );
BUFX3TS U6307 ( .A(n6301), .Y(n6266) );
NOR2X2TS U6308 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_5_n1), .Y(n6327) );
NAND2X1TS U6309 ( .A(n6327), .B(n7049), .Y(n6329) );
NAND3BX1TS U6310 ( .AN(n4611), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]),
.C(n6699), .Y(n5020) );
NOR3X2TS U6311 ( .A(FPSENCOS_cont_iter_out[3]), .B(FPSENCOS_cont_iter_out[1]), .C(n6270), .Y(n6232) );
BUFX3TS U6312 ( .A(n6311), .Y(n6268) );
OA22X1TS U6313 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n4936), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n6268), .Y(n2003) );
INVX2TS U6314 ( .A(n4613), .Y(n6226) );
OA22X1TS U6315 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n6300), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n7023), .Y(n1991) );
OA22X1TS U6316 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n6300), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n6268), .Y(n1977) );
OA22X1TS U6317 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n6300), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n6268), .Y(n1979) );
OA22X1TS U6318 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n6300), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n6268), .Y(n1967) );
OA22X1TS U6319 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n6300), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n6268), .Y(n1973) );
OA22X1TS U6320 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n6300), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n7023), .Y(n1981) );
OA22X1TS U6321 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n4936), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n7023), .Y(n1985) );
OA22X1TS U6322 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n4936), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n7023), .Y(n1993) );
OA22X1TS U6323 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n7023), .Y(n1995) );
OA22X1TS U6324 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n7023), .Y(n1999) );
OA22X1TS U6325 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n7023), .Y(n2001) );
OAI22X1TS U6326 ( .A0(n2317), .A1(n5390), .B0(n5400), .B1(n5389), .Y(n4619)
);
ADDHX1TS U6327 ( .A(n4616), .B(n4615), .CO(n4509), .S(n4618) );
OAI22X1TS U6328 ( .A0(n5398), .A1(n5392), .B0(n2317), .B1(n5391), .Y(n4617)
);
NAND2X1TS U6329 ( .A(n2223), .B(FPMULT_Op_MX[19]), .Y(n5529) );
INVX2TS U6330 ( .A(n5529), .Y(n4620) );
NOR2X1TS U6331 ( .A(n6856), .B(n2229), .Y(n5530) );
NAND2X1TS U6332 ( .A(n5528), .B(n5500), .Y(n5097) );
NOR2X1TS U6333 ( .A(n5138), .B(n5097), .Y(n5096) );
BUFX3TS U6334 ( .A(n4621), .Y(n6947) );
BUFX3TS U6335 ( .A(n6966), .Y(n6949) );
BUFX3TS U6336 ( .A(n4621), .Y(n6945) );
BUFX3TS U6337 ( .A(n4621), .Y(n6944) );
BUFX3TS U6338 ( .A(n4621), .Y(n6940) );
BUFX3TS U6339 ( .A(n4621), .Y(n6939) );
INVX2TS U6340 ( .A(n4622), .Y(n5475) );
OR2X2TS U6341 ( .A(n5814), .B(n6683), .Y(n5742) );
NAND2X1TS U6342 ( .A(n5742), .B(FPMULT_Add_result[0]), .Y(n4623) );
NOR2BX1TS U6343 ( .AN(n1694), .B(n4629), .Y(n4626) );
NAND2X2TS U6344 ( .A(n6433), .B(n4624), .Y(n6470) );
INVX2TS U6345 ( .A(n6470), .Y(n5890) );
INVX2TS U6346 ( .A(n5742), .Y(n5809) );
INVX2TS U6347 ( .A(n4626), .Y(n4627) );
OAI31X1TS U6348 ( .A0(n5890), .A1(n5777), .A2(n6681), .B0(n4627), .Y(n1622)
);
INVX2TS U6349 ( .A(intadd_2_SUM_0_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
NAND2X1TS U6350 ( .A(n6727), .B(n6655), .Y(intadd_4_CI) );
INVX2TS U6351 ( .A(intadd_0_SUM_0_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
INVX2TS U6352 ( .A(n1670), .Y(n6911) );
INVX2TS U6353 ( .A(n1660), .Y(n6854) );
INVX2TS U6354 ( .A(intadd_2_SUM_1_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
INVX2TS U6355 ( .A(n1673), .Y(n6878) );
INVX2TS U6356 ( .A(intadd_0_SUM_1_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
INVX2TS U6357 ( .A(DP_OP_501J1_127_1459_n943), .Y(n6898) );
INVX2TS U6358 ( .A(DP_OP_501J1_127_1459_n930), .Y(n6895) );
INVX2TS U6359 ( .A(n1661), .Y(n6889) );
INVX2TS U6360 ( .A(intadd_0_SUM_2_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
INVX2TS U6361 ( .A(intadd_2_SUM_2_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
INVX2TS U6362 ( .A(intadd_0_SUM_3_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
INVX2TS U6363 ( .A(intadd_2_SUM_3_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
NAND2X1TS U6364 ( .A(n6683), .B(n6634), .Y(n5317) );
AOI21X1TS U6365 ( .A0(n2320), .A1(n6824), .B0(n4630), .Y(n4633) );
INVX2TS U6366 ( .A(n4631), .Y(n5811) );
AOI21X1TS U6367 ( .A0(begin_operation), .A1(n5811), .B0(n6920), .Y(n4632) );
INVX2TS U6368 ( .A(intadd_0_SUM_4_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
INVX2TS U6369 ( .A(intadd_2_SUM_4_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
AND2X2TS U6370 ( .A(n6176), .B(n4634), .Y(n4638) );
AOI22X1TS U6371 ( .A0(n4703), .A1(n1574), .B0(n4635), .B1(n4777), .Y(n4637)
);
AOI22X1TS U6372 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4641), .B0(
n4654), .B1(FPMULT_Add_result[22]), .Y(n4636) );
BUFX3TS U6373 ( .A(n4654), .Y(n4772) );
AOI22X1TS U6374 ( .A0(n4703), .A1(n1566), .B0(n4772), .B1(
FPMULT_Add_result[14]), .Y(n4640) );
BUFX3TS U6375 ( .A(n4638), .Y(n4784) );
AOI22X1TS U6376 ( .A0(n4638), .A1(n1567), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n4783), .Y(n4639) );
AOI22X1TS U6377 ( .A0(n4703), .A1(n1563), .B0(n4784), .B1(FPMULT_P_Sgf[35]),
.Y(n4643) );
BUFX3TS U6378 ( .A(n4641), .Y(n4778) );
AOI22X1TS U6379 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4778), .B0(
n4772), .B1(FPMULT_Add_result[11]), .Y(n4642) );
INVX2TS U6380 ( .A(n4644), .Y(n2114) );
INVX2TS U6381 ( .A(n4645), .Y(n4670) );
NOR2BX1TS U6382 ( .AN(n4647), .B(n4646), .Y(n4673) );
AOI21X1TS U6383 ( .A0(n4648), .A1(n6632), .B0(n4672), .Y(n4649) );
AOI22X1TS U6384 ( .A0(n4670), .A1(n4650), .B0(n4673), .B1(n4649), .Y(n4653)
);
NAND2X1TS U6385 ( .A(n4869), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n4651)
);
INVX2TS U6386 ( .A(intadd_0_SUM_5_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
BUFX3TS U6387 ( .A(n4654), .Y(n4781) );
AOI22X1TS U6388 ( .A0(n4638), .A1(FPMULT_P_Sgf[27]), .B0(n4781), .B1(
FPMULT_Add_result[3]), .Y(n4656) );
AOI22X1TS U6389 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4778), .B0(
n4703), .B1(FPMULT_P_Sgf[26]), .Y(n4655) );
AOI22X1TS U6390 ( .A0(n4638), .A1(n1561), .B0(n4781), .B1(
FPMULT_Add_result[8]), .Y(n4658) );
AOI22X1TS U6391 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4778), .B0(
n4703), .B1(FPMULT_P_Sgf[31]), .Y(n4657) );
AOI22X1TS U6392 ( .A0(n4638), .A1(n1569), .B0(n4772), .B1(
FPMULT_Add_result[16]), .Y(n4660) );
AOI22X1TS U6393 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4641), .B0(
n4703), .B1(n1568), .Y(n4659) );
AOI22X1TS U6394 ( .A0(n4638), .A1(n1574), .B0(n4654), .B1(
FPMULT_Add_result[21]), .Y(n4662) );
AOI22X1TS U6395 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4641), .B0(
n4703), .B1(n1573), .Y(n4661) );
INVX2TS U6396 ( .A(n4663), .Y(n2130) );
AOI22X1TS U6397 ( .A0(n4777), .A1(FPMULT_P_Sgf[24]), .B0(n4781), .B1(
FPMULT_Add_result[0]), .Y(n4665) );
AOI22X1TS U6398 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4778), .B0(
n4703), .B1(FPMULT_P_Sgf[23]), .Y(n4664) );
INVX2TS U6399 ( .A(n6255), .Y(n6254) );
AOI32X1TS U6400 ( .A0(n6254), .A1(operation[0]), .A2(operation[1]), .B0(
FPSENCOS_d_ff1_operation_out), .B1(n6255), .Y(n4666) );
INVX2TS U6401 ( .A(n4666), .Y(n2080) );
INVX2TS U6402 ( .A(intadd_2_SUM_5_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
NAND2X1TS U6403 ( .A(n6249), .B(n4667), .Y(n6238) );
OA21XLTS U6404 ( .A0(n4673), .A1(n4672), .B0(n4671), .Y(n4676) );
NAND2X1TS U6405 ( .A(n4869), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n4675)
);
NOR2X1TS U6406 ( .A(FPSENCOS_cont_iter_out[3]), .B(n6270), .Y(n4682) );
NAND2X1TS U6407 ( .A(FPSENCOS_d_ff3_LUT_out[10]), .B(n6339), .Y(n4677) );
INVX2TS U6408 ( .A(intadd_0_SUM_6_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
NOR2X2TS U6409 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6339), .Y(n6244) );
AOI21X1TS U6410 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n6339), .B0(n6233),
.Y(n4681) );
NOR2XLTS U6411 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6270), .Y(n4684) );
NAND2X1TS U6412 ( .A(FPSENCOS_cont_iter_out[3]), .B(n6233), .Y(n6237) );
AOI22X1TS U6413 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n6339), .B0(n4682),
.B1(n6244), .Y(n4683) );
NAND2X1TS U6414 ( .A(n6233), .B(n6247), .Y(n6227) );
BUFX3TS U6415 ( .A(n4685), .Y(n6215) );
INVX2TS U6416 ( .A(result_add_subt[0]), .Y(n6595) );
INVX2TS U6417 ( .A(n4687), .Y(n4689) );
AOI22X1TS U6418 ( .A0(n6746), .A1(n4689), .B0(n5811), .B1(mult_result[0]),
.Y(n4688) );
INVX2TS U6419 ( .A(result_add_subt[1]), .Y(n6598) );
AOI22X1TS U6420 ( .A0(n6747), .A1(n4809), .B0(n4811), .B1(mult_result[1]),
.Y(n4690) );
INVX2TS U6421 ( .A(intadd_2_SUM_6_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
AOI2BB2XLTS U6422 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n6710), .A0N(n6710),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n4692) );
AOI22X1TS U6423 ( .A0(operation[0]), .A1(n6420), .B0(FPADDSUB_intAS), .B1(
n4538), .Y(n4691) );
INVX2TS U6424 ( .A(result_add_subt[31]), .Y(n6424) );
INVX2TS U6425 ( .A(n4687), .Y(n4809) );
INVX2TS U6426 ( .A(n4631), .Y(n4808) );
AOI22X1TS U6427 ( .A0(cordic_result_31_), .A1(n4809), .B0(n4808), .B1(
mult_result[31]), .Y(n4693) );
AOI22X1TS U6428 ( .A0(n6771), .A1(n4805), .B0(n5811), .B1(mult_result[28]),
.Y(n4694) );
OAI21XLTS U6429 ( .A0(n4685), .A1(n6405), .B0(n4694), .Y(op_result[28]) );
AOI22X1TS U6430 ( .A0(n6772), .A1(n4689), .B0(n5811), .B1(mult_result[29]),
.Y(n4695) );
OAI21XLTS U6431 ( .A0(n4685), .A1(n6409), .B0(n4695), .Y(op_result[29]) );
INVX2TS U6432 ( .A(n4631), .Y(n4804) );
AOI22X1TS U6433 ( .A0(n6749), .A1(n4812), .B0(n4811), .B1(mult_result[4]),
.Y(n4696) );
AOI22X1TS U6434 ( .A0(n6744), .A1(n4809), .B0(n4811), .B1(mult_result[30]),
.Y(n4697) );
OAI21XLTS U6435 ( .A0(n4685), .A1(n6417), .B0(n4697), .Y(op_result[30]) );
AOI22X1TS U6436 ( .A0(n6748), .A1(n4812), .B0(n4811), .B1(mult_result[2]),
.Y(n4698) );
AOI22X1TS U6437 ( .A0(n6752), .A1(n4812), .B0(n4808), .B1(mult_result[7]),
.Y(n4699) );
AOI22X1TS U6438 ( .A0(n6750), .A1(n4812), .B0(n5811), .B1(mult_result[5]),
.Y(n4700) );
AOI22X1TS U6439 ( .A0(n6753), .A1(n4812), .B0(n4811), .B1(mult_result[8]),
.Y(n4701) );
AOI22X1TS U6440 ( .A0(n6745), .A1(n4812), .B0(n5811), .B1(mult_result[3]),
.Y(n4702) );
INVX2TS U6441 ( .A(intadd_0_n1), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11) );
INVX2TS U6442 ( .A(n4703), .Y(n4763) );
INVX2TS U6443 ( .A(n4763), .Y(n4716) );
AOI22X1TS U6444 ( .A0(n4716), .A1(n1565), .B0(n4784), .B1(n1566), .Y(n4705)
);
AOI22X1TS U6445 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4778), .B0(
n4772), .B1(FPMULT_Add_result[13]), .Y(n4704) );
AOI22X1TS U6446 ( .A0(n4716), .A1(n1569), .B0(n4772), .B1(
FPMULT_Add_result[17]), .Y(n4707) );
AOI22X1TS U6447 ( .A0(n4777), .A1(n1570), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n4783), .Y(n4706) );
AOI22X1TS U6448 ( .A0(n4716), .A1(n1572), .B0(n4784), .B1(n1573), .Y(n4709)
);
AOI22X1TS U6449 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4783), .B0(
n4654), .B1(FPMULT_Add_result[20]), .Y(n4708) );
AOI22X1TS U6450 ( .A0(n4716), .A1(n1562), .B0(n4772), .B1(
FPMULT_Add_result[10]), .Y(n4711) );
AOI22X1TS U6451 ( .A0(n4777), .A1(n1563), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n4641), .Y(n4710) );
AOI22X1TS U6452 ( .A0(n4716), .A1(FPMULT_P_Sgf[29]), .B0(n4784), .B1(
FPMULT_P_Sgf[30]), .Y(n4713) );
AOI22X1TS U6453 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4778), .B0(
n4781), .B1(FPMULT_Add_result[6]), .Y(n4712) );
AOI22X1TS U6454 ( .A0(n4716), .A1(FPMULT_P_Sgf[30]), .B0(n4784), .B1(
FPMULT_P_Sgf[31]), .Y(n4715) );
AOI22X1TS U6455 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4778), .B0(
n4781), .B1(FPMULT_Add_result[7]), .Y(n4714) );
AOI22X1TS U6456 ( .A0(n4716), .A1(FPMULT_P_Sgf[25]), .B0(n4784), .B1(
FPMULT_P_Sgf[26]), .Y(n4718) );
AOI22X1TS U6457 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n4778), .B0(
n4781), .B1(FPMULT_Add_result[2]), .Y(n4717) );
INVX2TS U6458 ( .A(intadd_0_SUM_7_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
NAND2X1TS U6459 ( .A(n6927), .B(n6631), .Y(n5597) );
NAND2X1TS U6460 ( .A(DP_OP_501J1_127_1459_n931), .B(n2224), .Y(n5596) );
NOR2X2TS U6461 ( .A(n5597), .B(n5596), .Y(n5595) );
NAND2X2TS U6462 ( .A(n5495), .B(n2224), .Y(n4746) );
NOR2X2TS U6463 ( .A(n4746), .B(n5597), .Y(n5559) );
AOI22X1TS U6464 ( .A0(n6927), .A1(n2224), .B0(n5495), .B1(n6631), .Y(n4719)
);
INVX2TS U6465 ( .A(n6447), .Y(n5336) );
NOR2X2TS U6466 ( .A(n2406), .B(n5336), .Y(n4726) );
XNOR2X1TS U6467 ( .A(n4726), .B(n4730), .Y(n4720) );
XOR2X1TS U6468 ( .A(n4720), .B(n4727), .Y(n5571) );
OAI21X1TS U6469 ( .A0(n5595), .A1(n5570), .B0(n4721), .Y(intadd_0_A_2_) );
NAND2X2TS U6470 ( .A(DP_OP_501J1_127_1459_n931), .B(n6450), .Y(n4751) );
NAND2X1TS U6471 ( .A(FPMULT_Op_MY[15]), .B(n6925), .Y(n5600) );
AOI22X1TS U6472 ( .A0(DP_OP_501J1_127_1459_n931), .A1(FPMULT_Op_MY[15]),
.B0(n6925), .B1(n6450), .Y(n4722) );
INVX2TS U6473 ( .A(n5592), .Y(n4736) );
NAND2X1TS U6474 ( .A(n6631), .B(n2347), .Y(n4725) );
NOR2X2TS U6475 ( .A(n4746), .B(n4725), .Y(n5566) );
INVX2TS U6476 ( .A(n5566), .Y(n4749) );
OAI2BB1X1TS U6477 ( .A0N(n4746), .A1N(n4725), .B0(n4749), .Y(n5591) );
INVX2TS U6478 ( .A(n5591), .Y(n4735) );
INVX2TS U6479 ( .A(n4726), .Y(n4729) );
INVX2TS U6480 ( .A(n4727), .Y(n4728) );
OAI22X1TS U6481 ( .A0(n4731), .A1(n4730), .B0(n4729), .B1(n4728), .Y(n5558)
);
NAND2X1TS U6482 ( .A(n6926), .B(n6448), .Y(n4732) );
XOR2X1TS U6483 ( .A(n5559), .B(n4732), .Y(n4733) );
XOR2X1TS U6484 ( .A(n5558), .B(n4733), .Y(n5593) );
OAI21X1TS U6485 ( .A0(n4736), .A1(n4735), .B0(n4734), .Y(intadd_0_A_3_) );
NAND2X1TS U6486 ( .A(FPMULT_Op_MY[15]), .B(n5495), .Y(n4737) );
NOR2X1TS U6487 ( .A(n4751), .B(n4737), .Y(n5543) );
AOI21X1TS U6488 ( .A0(n4751), .A1(n4737), .B0(n5543), .Y(n4739) );
NAND2X1TS U6489 ( .A(n6447), .B(n2346), .Y(n4745) );
INVX2TS U6490 ( .A(n4745), .Y(n4738) );
NAND2X1TS U6491 ( .A(n4739), .B(n4738), .Y(n5544) );
INVX2TS U6492 ( .A(n4739), .Y(n4740) );
NAND2X1TS U6493 ( .A(n4740), .B(n4745), .Y(n4741) );
NAND2X1TS U6494 ( .A(n5544), .B(n4741), .Y(n5583) );
INVX2TS U6495 ( .A(n5583), .Y(n4758) );
INVX2TS U6496 ( .A(n4742), .Y(n4743) );
INVX2TS U6497 ( .A(n5569), .Y(n4750) );
NOR2X2TS U6498 ( .A(n4746), .B(n4745), .Y(n5547) );
AOI22X1TS U6499 ( .A0(n5495), .A1(n6447), .B0(n2224), .B1(n2347), .Y(n4747)
);
NOR2X1TS U6500 ( .A(n5547), .B(n4747), .Y(n5567) );
INVX2TS U6501 ( .A(n5584), .Y(n4756) );
OA22X1TS U6502 ( .A0(n6690), .A1(n6886), .B0(n6887), .B1(n6888), .Y(n4752)
);
NOR2X1TS U6503 ( .A(n6704), .B(n6882), .Y(n5564) );
NAND2X1TS U6504 ( .A(n5565), .B(n5564), .Y(n5563) );
INVX2TS U6505 ( .A(n4753), .Y(n4754) );
NAND2X1TS U6506 ( .A(n6448), .B(n6927), .Y(n5546) );
XNOR2X1TS U6507 ( .A(n5547), .B(n5546), .Y(n4755) );
XNOR2X1TS U6508 ( .A(n5550), .B(n4755), .Y(n5585) );
OAI21X1TS U6509 ( .A0(n4758), .A1(n5584), .B0(n4757), .Y(intadd_0_A_5_) );
AOI22X1TS U6510 ( .A0(n6450), .A1(n5495), .B0(n6448), .B1(n2347), .Y(n4759)
);
NAND2X1TS U6511 ( .A(n6448), .B(n5495), .Y(n5552) );
NOR2X1TS U6512 ( .A(n5552), .B(intadd_0_A_7_), .Y(n5577) );
NOR2X1TS U6513 ( .A(n4759), .B(n5577), .Y(n4762) );
NAND2X1TS U6514 ( .A(FPMULT_Op_MY[15]), .B(n2347), .Y(n5551) );
NAND2X1TS U6515 ( .A(n6450), .B(n6927), .Y(n5553) );
OAI21X1TS U6516 ( .A0(n5551), .A1(n5553), .B0(n4760), .Y(n4761) );
NAND2X1TS U6517 ( .A(n4761), .B(n4762), .Y(n5578) );
INVX2TS U6518 ( .A(n4763), .Y(n4782) );
AOI22X1TS U6519 ( .A0(n4782), .A1(n1567), .B0(n4772), .B1(
FPMULT_Add_result[15]), .Y(n4765) );
AOI22X1TS U6520 ( .A0(n4777), .A1(n1568), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n4641), .Y(n4764) );
AOI22X1TS U6521 ( .A0(n4782), .A1(n1570), .B0(n4784), .B1(n1571), .Y(n4767)
);
AOI22X1TS U6522 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4783), .B0(
n4772), .B1(FPMULT_Add_result[18]), .Y(n4766) );
AOI22X1TS U6523 ( .A0(n4782), .A1(n1571), .B0(n4784), .B1(n1572), .Y(n4769)
);
AOI22X1TS U6524 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4641), .B0(
n4772), .B1(FPMULT_Add_result[19]), .Y(n4768) );
AOI22X1TS U6525 ( .A0(n4782), .A1(n1561), .B0(n4784), .B1(n1562), .Y(n4771)
);
AOI22X1TS U6526 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4778), .B0(
n4781), .B1(FPMULT_Add_result[9]), .Y(n4770) );
AOI22X1TS U6527 ( .A0(n4782), .A1(FPMULT_P_Sgf[35]), .B0(n4772), .B1(
FPMULT_Add_result[12]), .Y(n4774) );
AOI22X1TS U6528 ( .A0(n4777), .A1(n1565), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n4641), .Y(n4773) );
AOI22X1TS U6529 ( .A0(n4782), .A1(FPMULT_P_Sgf[24]), .B0(n4781), .B1(
FPMULT_Add_result[1]), .Y(n4776) );
AOI22X1TS U6530 ( .A0(n4638), .A1(FPMULT_P_Sgf[25]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n4783), .Y(n4775) );
AOI22X1TS U6531 ( .A0(n4782), .A1(FPMULT_P_Sgf[28]), .B0(n4784), .B1(
FPMULT_P_Sgf[29]), .Y(n4780) );
AOI22X1TS U6532 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4778), .B0(
n4781), .B1(FPMULT_Add_result[5]), .Y(n4779) );
AOI22X1TS U6533 ( .A0(n4782), .A1(FPMULT_P_Sgf[27]), .B0(n4781), .B1(
FPMULT_Add_result[4]), .Y(n4786) );
AOI22X1TS U6534 ( .A0(n4638), .A1(FPMULT_P_Sgf[28]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n4783), .Y(n4785) );
BUFX3TS U6535 ( .A(n4685), .Y(n4807) );
AOI22X1TS U6536 ( .A0(n6754), .A1(n4812), .B0(n4808), .B1(mult_result[9]),
.Y(n4787) );
AOI22X1TS U6537 ( .A0(n6761), .A1(n4805), .B0(n4804), .B1(mult_result[17]),
.Y(n4788) );
AOI22X1TS U6538 ( .A0(n6759), .A1(n4689), .B0(n4804), .B1(mult_result[14]),
.Y(n4789) );
BUFX3TS U6539 ( .A(n4685), .Y(n4814) );
AOI22X1TS U6540 ( .A0(n6765), .A1(n4809), .B0(n4804), .B1(mult_result[21]),
.Y(n4790) );
AOI22X1TS U6541 ( .A0(n6751), .A1(n4812), .B0(n4808), .B1(mult_result[6]),
.Y(n4791) );
INVX2TS U6542 ( .A(result_add_subt[22]), .Y(n6493) );
AOI22X1TS U6543 ( .A0(n6773), .A1(n4805), .B0(n4811), .B1(mult_result[22]),
.Y(n4792) );
AOI22X1TS U6544 ( .A0(n6757), .A1(n4805), .B0(n4804), .B1(mult_result[12]),
.Y(n4793) );
AOI22X1TS U6545 ( .A0(n6767), .A1(n4689), .B0(n4808), .B1(mult_result[24]),
.Y(n4794) );
AOI22X1TS U6546 ( .A0(n6769), .A1(n4809), .B0(n5811), .B1(mult_result[26]),
.Y(n4795) );
AOI22X1TS U6547 ( .A0(n6758), .A1(n4689), .B0(n4804), .B1(mult_result[13]),
.Y(n4796) );
AOI22X1TS U6548 ( .A0(n6768), .A1(n4805), .B0(n4808), .B1(mult_result[25]),
.Y(n4797) );
AOI22X1TS U6549 ( .A0(n6760), .A1(n4809), .B0(n4804), .B1(mult_result[16]),
.Y(n4798) );
AOI22X1TS U6550 ( .A0(n6762), .A1(n4805), .B0(n5811), .B1(mult_result[18]),
.Y(n4799) );
AOI22X1TS U6551 ( .A0(n6770), .A1(n4689), .B0(n4811), .B1(mult_result[27]),
.Y(n4800) );
AOI22X1TS U6552 ( .A0(n6756), .A1(n4812), .B0(n5811), .B1(mult_result[11]),
.Y(n4801) );
AOI22X1TS U6553 ( .A0(n6764), .A1(n4689), .B0(n4804), .B1(mult_result[20]),
.Y(n4802) );
AOI22X1TS U6554 ( .A0(n6774), .A1(n4809), .B0(n4804), .B1(mult_result[15]),
.Y(n4803) );
AOI22X1TS U6555 ( .A0(n6755), .A1(n4689), .B0(n4811), .B1(mult_result[10]),
.Y(n4806) );
AOI22X1TS U6556 ( .A0(n6766), .A1(n4809), .B0(n4808), .B1(mult_result[23]),
.Y(n4810) );
AOI22X1TS U6557 ( .A0(n6763), .A1(n4805), .B0(n4808), .B1(mult_result[19]),
.Y(n4813) );
INVX2TS U6558 ( .A(intadd_2_n1), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11) );
INVX2TS U6559 ( .A(intadd_2_SUM_7_), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
NAND2X1TS U6560 ( .A(n6924), .B(FPMULT_Op_MY[0]), .Y(n5335) );
NAND2X1TS U6561 ( .A(n4818), .B(n6438), .Y(n5334) );
NOR2X2TS U6562 ( .A(n5335), .B(n5334), .Y(n5676) );
NAND2X2TS U6563 ( .A(n2194), .B(n6438), .Y(n4841) );
NOR2X2TS U6564 ( .A(n4841), .B(n5335), .Y(n5664) );
OA22X1TS U6565 ( .A0(n6852), .A1(n6860), .B0(n6638), .B1(n6853), .Y(n4815)
);
INVX2TS U6566 ( .A(n4818), .Y(n5708) );
XNOR2X1TS U6567 ( .A(n4823), .B(n5681), .Y(n4816) );
XOR2X1TS U6568 ( .A(n4816), .B(n4824), .Y(n5678) );
OAI21X1TS U6569 ( .A0(n5676), .A1(n5677), .B0(n4817), .Y(intadd_2_A_2_) );
NAND2X2TS U6570 ( .A(n4818), .B(n6439), .Y(n4846) );
AOI22X1TS U6571 ( .A0(n4818), .A1(FPMULT_Op_MY[3]), .B0(FPMULT_Op_MX[0]),
.B1(n6439), .Y(n4819) );
INVX2TS U6572 ( .A(n5699), .Y(n4831) );
NAND2X1TS U6573 ( .A(n5491), .B(FPMULT_Op_MY[0]), .Y(n4822) );
NOR2X2TS U6574 ( .A(n4841), .B(n4822), .Y(n5672) );
INVX2TS U6575 ( .A(n5672), .Y(n4844) );
OAI2BB1X1TS U6576 ( .A0N(n4841), .A1N(n4822), .B0(n4844), .Y(n5698) );
INVX2TS U6577 ( .A(n5698), .Y(n4830) );
INVX2TS U6578 ( .A(n4823), .Y(n4826) );
INVX2TS U6579 ( .A(n4824), .Y(n4825) );
OAI22X1TS U6580 ( .A0(n4827), .A1(n5681), .B0(n4826), .B1(n4825), .Y(n5663)
);
NAND2X2TS U6581 ( .A(n6922), .B(n5497), .Y(n5667) );
XOR2X1TS U6582 ( .A(n5664), .B(n5667), .Y(n4828) );
XOR2X1TS U6583 ( .A(n5663), .B(n4828), .Y(n5700) );
NAND2X1TS U6584 ( .A(FPMULT_Op_MY[3]), .B(n2194), .Y(n4832) );
NOR2X1TS U6585 ( .A(n4846), .B(n4832), .Y(n5648) );
AOI21X1TS U6586 ( .A0(n4846), .A1(n4832), .B0(n5648), .Y(n4834) );
NAND2X1TS U6587 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[5]), .Y(n4840) );
INVX2TS U6588 ( .A(n4840), .Y(n4833) );
NAND2X1TS U6589 ( .A(n4834), .B(n4833), .Y(n5649) );
INVX2TS U6590 ( .A(n4834), .Y(n4835) );
NAND2X1TS U6591 ( .A(n4835), .B(n4840), .Y(n4836) );
NAND2X1TS U6592 ( .A(n5649), .B(n4836), .Y(n5690) );
INVX2TS U6593 ( .A(n5690), .Y(n4853) );
INVX2TS U6594 ( .A(n4837), .Y(n4838) );
INVX2TS U6595 ( .A(n5675), .Y(n4845) );
NOR2X2TS U6596 ( .A(n4841), .B(n4840), .Y(n5652) );
AOI22X1TS U6597 ( .A0(n2194), .A1(FPMULT_Op_MY[2]), .B0(FPMULT_Op_MX[5]),
.B1(n6438), .Y(n4842) );
NOR2X1TS U6598 ( .A(n5652), .B(n4842), .Y(n5673) );
OAI21X2TS U6599 ( .A0(n4845), .A1(n4844), .B0(n4843), .Y(n5691) );
INVX2TS U6600 ( .A(n5691), .Y(n4851) );
OA22X1TS U6601 ( .A0(n6697), .A1(n6857), .B0(n6858), .B1(n6859), .Y(n4847)
);
NOR2X1TS U6602 ( .A(n6638), .B(n6855), .Y(n5670) );
INVX2TS U6603 ( .A(n4848), .Y(n4849) );
NAND2X1TS U6604 ( .A(n5497), .B(n6924), .Y(n5651) );
XNOR2X1TS U6605 ( .A(n5652), .B(n5651), .Y(n4850) );
XNOR2X1TS U6606 ( .A(n5655), .B(n4850), .Y(n5692) );
OAI21X1TS U6607 ( .A0(n4853), .A1(n5691), .B0(n4852), .Y(intadd_2_A_5_) );
AOI22X1TS U6608 ( .A0(FPMULT_Op_MY[4]), .A1(FPMULT_Op_MX[5]), .B0(n2194),
.B1(n6439), .Y(n4854) );
NAND2X1TS U6609 ( .A(FPMULT_Op_MY[4]), .B(n2194), .Y(n5657) );
NOR2X1TS U6610 ( .A(n5657), .B(intadd_2_A_7_), .Y(n5684) );
NOR2X1TS U6611 ( .A(n4854), .B(n5684), .Y(n4857) );
NAND2X1TS U6612 ( .A(n6924), .B(n6439), .Y(n5656) );
NAND2X1TS U6613 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MX[5]), .Y(n5658) );
OAI21X1TS U6614 ( .A0(n5656), .A1(n5658), .B0(n4855), .Y(n4856) );
NAND2X1TS U6615 ( .A(n4856), .B(n4857), .Y(n5685) );
NOR2X1TS U6616 ( .A(n2249), .B(n4858), .Y(n6239) );
NAND2X1TS U6617 ( .A(n6233), .B(n6271), .Y(n6229) );
OAI22X1TS U6618 ( .A0(n4863), .A1(n4862), .B0(n4861), .B1(n4860), .Y(n4864)
);
AOI211X1TS U6619 ( .A0(n4867), .A1(n4866), .B0(n4865), .C0(n4864), .Y(n4871)
);
NAND2X1TS U6620 ( .A(n4869), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n4870)
);
NOR2X1TS U6621 ( .A(n2298), .B(n5391), .Y(DP_OP_502J1_128_2852_n161) );
NAND2X2TS U6622 ( .A(n2279), .B(DP_OP_501J1_127_1459_n952), .Y(n4897) );
NAND2X1TS U6623 ( .A(DP_OP_501J1_127_1459_n910), .B(n6455), .Y(n4872) );
NOR2X2TS U6624 ( .A(n4897), .B(n4872), .Y(n4902) );
INVX2TS U6625 ( .A(n5631), .Y(n4884) );
NAND2X2TS U6626 ( .A(n2277), .B(n2370), .Y(n4908) );
NAND2X1TS U6627 ( .A(FPMULT_Op_MX[6]), .B(n6441), .Y(n5643) );
AOI22X1TS U6628 ( .A0(n2370), .A1(FPMULT_Op_MX[6]), .B0(n2277), .B1(n6441),
.Y(n4873) );
NOR2X1TS U6629 ( .A(n4894), .B(n4873), .Y(n4875) );
NAND2X1TS U6630 ( .A(n4875), .B(n4874), .Y(n4896) );
INVX2TS U6631 ( .A(n5632), .Y(n4883) );
NAND2X1TS U6632 ( .A(DP_OP_501J1_127_1459_n910), .B(FPMULT_Op_MX[9]), .Y(
n5618) );
NOR2X2TS U6633 ( .A(n4897), .B(n5618), .Y(n5607) );
NAND2X2TS U6634 ( .A(FPMULT_Op_MX[7]), .B(n6442), .Y(n4889) );
XOR2X1TS U6635 ( .A(n5607), .B(n4889), .Y(n4881) );
NAND2X1TS U6636 ( .A(n2277), .B(n6440), .Y(n5608) );
NAND2X1TS U6637 ( .A(FPMULT_Op_MX[6]), .B(n6442), .Y(n4877) );
NAND2X1TS U6638 ( .A(n5608), .B(n4877), .Y(n4876) );
INVX2TS U6639 ( .A(n6441), .Y(n4891) );
NAND2X1TS U6640 ( .A(n4876), .B(n5609), .Y(n4880) );
INVX2TS U6641 ( .A(n5608), .Y(n4878) );
INVX2TS U6642 ( .A(n4877), .Y(n5610) );
NAND2X1TS U6643 ( .A(n4878), .B(n5610), .Y(n4879) );
NAND2X1TS U6644 ( .A(n4880), .B(n4879), .Y(n4887) );
XNOR2X1TS U6645 ( .A(n4881), .B(n4887), .Y(n5633) );
OAI21X1TS U6646 ( .A0(n4884), .A1(n4883), .B0(n4882), .Y(mult_x_311_n29) );
INVX2TS U6647 ( .A(n5607), .Y(n4885) );
NAND2X1TS U6648 ( .A(n4885), .B(n4889), .Y(n4888) );
INVX2TS U6649 ( .A(n4889), .Y(n4886) );
AOI22X1TS U6650 ( .A0(FPMULT_Op_MX[7]), .A1(FPMULT_Op_MY[11]), .B0(
FPMULT_Op_MX[8]), .B1(n6442), .Y(n4890) );
NOR2X1TS U6651 ( .A(n4916), .B(n4890), .Y(n4893) );
NOR2X1TS U6652 ( .A(n4891), .B(n6636), .Y(n4892) );
NAND2X1TS U6653 ( .A(n4893), .B(n4892), .Y(n4918) );
INVX2TS U6654 ( .A(n4894), .Y(n4895) );
NAND2X1TS U6655 ( .A(n6455), .B(n6440), .Y(n4912) );
NOR2X2TS U6656 ( .A(n4897), .B(n4912), .Y(n4925) );
AOI22X1TS U6657 ( .A0(n2279), .A1(n6455), .B0(DP_OP_501J1_127_1459_n952),
.B1(n6440), .Y(n4898) );
NOR2X1TS U6658 ( .A(n4925), .B(n4898), .Y(n4901) );
XOR2X1TS U6659 ( .A(n4901), .B(n4902), .Y(n4899) );
XNOR2X1TS U6660 ( .A(n4903), .B(n4899), .Y(n5629) );
INVX2TS U6661 ( .A(n4903), .Y(n4906) );
INVX2TS U6662 ( .A(n4902), .Y(n4905) );
INVX2TS U6663 ( .A(n5624), .Y(n4922) );
NAND2X1TS U6664 ( .A(n6441), .B(DP_OP_501J1_127_1459_n952), .Y(n4907) );
NOR2X1TS U6665 ( .A(n4908), .B(n4907), .Y(n4910) );
NAND2X1TS U6666 ( .A(n4908), .B(n4907), .Y(n4915) );
NAND2X1TS U6667 ( .A(n4909), .B(n4915), .Y(n4913) );
INVX2TS U6668 ( .A(n4910), .Y(n4911) );
INVX2TS U6669 ( .A(n4912), .Y(n4914) );
INVX2TS U6670 ( .A(n5623), .Y(n4920) );
INVX2TS U6671 ( .A(n4916), .Y(n4917) );
NAND2X1TS U6672 ( .A(FPMULT_Op_MX[9]), .B(n6442), .Y(n4928) );
XOR2X1TS U6673 ( .A(n4925), .B(n4928), .Y(n4919) );
XNOR2X1TS U6674 ( .A(n4923), .B(n4919), .Y(n5625) );
OAI21X1TS U6675 ( .A0(n4922), .A1(n5623), .B0(n4921), .Y(mult_x_311_n17) );
INVX2TS U6676 ( .A(n4925), .Y(n4927) );
INVX2TS U6677 ( .A(n4928), .Y(n4924) );
OAI21X2TS U6678 ( .A0(n4928), .A1(n4927), .B0(n4926), .Y(n5621) );
INVX2TS U6679 ( .A(n5621), .Y(n4935) );
INVX2TS U6680 ( .A(n5620), .Y(n4933) );
XNOR2X1TS U6681 ( .A(n4930), .B(n4929), .Y(n4932) );
XOR2X1TS U6682 ( .A(n4932), .B(n4931), .Y(n5619) );
OAI21X1TS U6683 ( .A0(n5620), .A1(n4935), .B0(n4934), .Y(mult_x_311_n14) );
INVX2TS U6684 ( .A(n4938), .Y(n1734) );
INVX2TS U6685 ( .A(n4939), .Y(n1733) );
INVX2TS U6686 ( .A(FPSENCOS_d_ff2_Y[0]), .Y(n6297) );
BUFX3TS U6687 ( .A(n4940), .Y(n4961) );
AOI22X1TS U6688 ( .A0(n4961), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n4960), .Y(n4943) );
INVX2TS U6689 ( .A(n5320), .Y(n6207) );
NOR2X4TS U6690 ( .A(n4941), .B(n6207), .Y(n6368) );
BUFX3TS U6691 ( .A(n6380), .Y(n4962) );
AOI22X1TS U6692 ( .A0(FPSENCOS_d_ff2_Z[0]), .A1(n6381), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[0]), .Y(n4942) );
INVX2TS U6693 ( .A(FPSENCOS_d_ff2_Y[7]), .Y(n6305) );
AOI22X1TS U6694 ( .A0(Data_1[7]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n4960), .Y(n4945) );
BUFX3TS U6695 ( .A(n6368), .Y(n6285) );
AOI22X1TS U6696 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[7]), .Y(n4944) );
INVX2TS U6697 ( .A(FPSENCOS_d_ff2_Y[5]), .Y(n6304) );
AOI22X1TS U6698 ( .A0(Data_1[5]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n4538), .Y(n4947) );
AOI22X1TS U6699 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[5]), .Y(n4946) );
INVX2TS U6700 ( .A(FPSENCOS_d_ff2_Y[9]), .Y(n6308) );
AOI22X1TS U6701 ( .A0(Data_1[9]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n4960), .Y(n4949) );
AOI22X1TS U6702 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[9]), .Y(n4948) );
INVX2TS U6703 ( .A(FPSENCOS_d_ff2_Y[2]), .Y(n6299) );
AOI22X1TS U6704 ( .A0(Data_1[2]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n4960), .Y(n4951) );
AOI22X1TS U6705 ( .A0(n6381), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[2]), .Y(n4950) );
INVX2TS U6706 ( .A(FPSENCOS_d_ff2_Y[4]), .Y(n6303) );
AOI22X1TS U6707 ( .A0(Data_1[4]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n4960), .Y(n4953) );
AOI22X1TS U6708 ( .A0(n6381), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[4]), .Y(n4952) );
AOI22X1TS U6709 ( .A0(Data_1[6]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n6384), .Y(n4955) );
AOI22X1TS U6710 ( .A0(n6381), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[6]), .Y(n4954) );
INVX2TS U6711 ( .A(FPSENCOS_d_ff2_Y[8]), .Y(n6307) );
AOI22X1TS U6712 ( .A0(Data_1[8]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n6419), .Y(n4957) );
AOI22X1TS U6713 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[8]), .Y(n4956) );
INVX2TS U6714 ( .A(FPSENCOS_d_ff2_Y[1]), .Y(n6298) );
AOI22X1TS U6715 ( .A0(Data_1[1]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n4960), .Y(n4959) );
AOI22X1TS U6716 ( .A0(n6381), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[1]), .Y(n4958) );
OAI211X1TS U6717 ( .A0(n7020), .A1(n6298), .B0(n4959), .C0(n4958), .Y(n1940)
);
INVX2TS U6718 ( .A(FPSENCOS_d_ff2_Y[3]), .Y(n6302) );
AOI22X1TS U6719 ( .A0(Data_1[3]), .A1(n4961), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n4960), .Y(n4964) );
AOI22X1TS U6720 ( .A0(n6381), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4962), .B1(
FPSENCOS_d_ff2_X[3]), .Y(n4963) );
BUFX3TS U6721 ( .A(n4940), .Y(n6379) );
AOI22X1TS U6722 ( .A0(Data_2[25]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n6384), .Y(n4967) );
BUFX3TS U6723 ( .A(n6368), .Y(n5062) );
AOI22X1TS U6724 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[25]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[25]), .Y(n4966) );
AOI22X1TS U6725 ( .A0(Data_2[26]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n6384), .Y(n4969) );
AOI22X1TS U6726 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[26]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[26]), .Y(n4968) );
INVX2TS U6727 ( .A(n6317), .Y(n6282) );
BUFX3TS U6728 ( .A(n4974), .Y(n5007) );
INVX2TS U6729 ( .A(n4970), .Y(n1764) );
INVX2TS U6730 ( .A(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n6273) );
AOI22X1TS U6731 ( .A0(Data_2[23]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n6384), .Y(n4972) );
AOI22X1TS U6732 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[23]), .B0(n6380),
.B1(FPSENCOS_d_ff3_sh_y_out[23]), .Y(n4971) );
BUFX3TS U6733 ( .A(n4974), .Y(n4996) );
INVX2TS U6734 ( .A(n4973), .Y(n1744) );
BUFX3TS U6735 ( .A(n4974), .Y(n4991) );
INVX2TS U6736 ( .A(n4975), .Y(n1752) );
INVX2TS U6737 ( .A(n4976), .Y(n1742) );
INVX2TS U6738 ( .A(n4977), .Y(n1736) );
INVX2TS U6739 ( .A(n4978), .Y(n1754) );
INVX2TS U6740 ( .A(n4979), .Y(n1738) );
INVX2TS U6741 ( .A(n4980), .Y(n1747) );
INVX2TS U6742 ( .A(n4981), .Y(n1743) );
INVX2TS U6743 ( .A(n4982), .Y(n1740) );
INVX2TS U6744 ( .A(n4983), .Y(n1748) );
INVX2TS U6745 ( .A(n4984), .Y(n1751) );
INVX2TS U6746 ( .A(n4985), .Y(n1735) );
INVX2TS U6747 ( .A(n4986), .Y(n1749) );
INVX2TS U6748 ( .A(n4987), .Y(n1737) );
INVX2TS U6749 ( .A(n4988), .Y(n1745) );
INVX2TS U6750 ( .A(n4989), .Y(n1746) );
INVX2TS U6751 ( .A(n4990), .Y(n1753) );
INVX2TS U6752 ( .A(n4994), .Y(n1750) );
INVX2TS U6753 ( .A(n4995), .Y(n1741) );
INVX2TS U6754 ( .A(n4998), .Y(n1739) );
INVX2TS U6755 ( .A(n4999), .Y(n1763) );
INVX2TS U6756 ( .A(n5000), .Y(n1759) );
INVX2TS U6757 ( .A(n5001), .Y(n1755) );
INVX2TS U6758 ( .A(n5002), .Y(n1757) );
INVX2TS U6759 ( .A(n5003), .Y(n1761) );
INVX2TS U6760 ( .A(n5004), .Y(n1760) );
INVX2TS U6761 ( .A(n5005), .Y(n1762) );
INVX2TS U6762 ( .A(n5006), .Y(n1758) );
INVX2TS U6763 ( .A(n5010), .Y(n1756) );
AOI22X1TS U6764 ( .A0(Data_2[21]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n6374), .Y(n5012) );
AOI22X1TS U6765 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[21]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[21]), .Y(n5011) );
NOR2X1TS U6766 ( .A(n2447), .B(n5399), .Y(DP_OP_502J1_128_2852_n185) );
NOR4X1TS U6767 ( .A(n6337), .B(n6223), .C(n5013), .D(n6254), .Y(n5015) );
AOI21X1TS U6768 ( .A0(n5015), .A1(n6339), .B0(n5014), .Y(n5018) );
OAI22X1TS U6769 ( .A0(n5019), .A1(n5018), .B0(n5017), .B1(n5016), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
AOI32X1TS U6770 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n5020), .A2(n6224),
.B0(n5321), .B1(n5020), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[2])
);
INVX2TS U6771 ( .A(n6256), .Y(n6406) );
NOR2X1TS U6772 ( .A(n6209), .B(n6406), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
NOR4X1TS U6773 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .Y(n6861) );
BUFX3TS U6774 ( .A(n4940), .Y(n6344) );
BUFX3TS U6775 ( .A(n6384), .Y(n6294) );
AOI22X1TS U6776 ( .A0(Data_2[1]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n6294), .Y(n5022) );
BUFX3TS U6777 ( .A(n6368), .Y(n6295) );
BUFX3TS U6778 ( .A(n5041), .Y(n6345) );
AOI22X1TS U6779 ( .A0(n6295), .A1(FPSENCOS_d_ff3_LUT_out[1]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[1]), .Y(n5021) );
OAI211X1TS U6780 ( .A0(n7022), .A1(n2421), .B0(n5022), .C0(n5021), .Y(n1842)
);
BUFX3TS U6781 ( .A(n4940), .Y(n6362) );
BUFX3TS U6782 ( .A(n6419), .Y(n6348) );
AOI22X1TS U6783 ( .A0(Data_2[8]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n6348), .Y(n5024) );
AOI22X1TS U6784 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[8]), .B0(n6380),
.B1(FPSENCOS_d_ff3_sh_y_out[8]), .Y(n5023) );
OAI211X1TS U6785 ( .A0(n7022), .A1(n2402), .B0(n5024), .C0(n5023), .Y(n1835)
);
AOI22X1TS U6786 ( .A0(Data_2[0]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n6294), .Y(n5026) );
AOI22X1TS U6787 ( .A0(n6295), .A1(FPSENCOS_d_ff3_LUT_out[0]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[0]), .Y(n5025) );
AOI22X1TS U6788 ( .A0(Data_2[2]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n6294), .Y(n5028) );
AOI22X1TS U6789 ( .A0(n6295), .A1(FPSENCOS_d_ff3_LUT_out[2]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[2]), .Y(n5027) );
OAI211X1TS U6790 ( .A0(n7022), .A1(n2419), .B0(n5028), .C0(n5027), .Y(n1841)
);
AOI22X1TS U6791 ( .A0(Data_2[9]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n6348), .Y(n5030) );
AOI22X1TS U6792 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[9]), .Y(n5029) );
AOI22X1TS U6793 ( .A0(Data_2[12]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n6348), .Y(n5032) );
AOI22X1TS U6794 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[12]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[12]), .Y(n5031) );
AOI22X1TS U6795 ( .A0(Data_2[6]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n6348), .Y(n5034) );
AOI22X1TS U6796 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[6]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[6]), .Y(n5033) );
OAI211X1TS U6797 ( .A0(n7022), .A1(n2412), .B0(n5034), .C0(n5033), .Y(n1837)
);
AOI22X1TS U6798 ( .A0(Data_2[10]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n6348), .Y(n5036) );
AOI22X1TS U6799 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[10]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[10]), .Y(n5035) );
AOI22X1TS U6800 ( .A0(Data_2[4]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n6348), .Y(n5038) );
AOI22X1TS U6801 ( .A0(n6295), .A1(FPSENCOS_d_ff3_LUT_out[4]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[4]), .Y(n5037) );
OAI211X1TS U6802 ( .A0(n7022), .A1(n2408), .B0(n5038), .C0(n5037), .Y(n1839)
);
INVX2TS U6803 ( .A(FPSENCOS_d_ff2_Y[15]), .Y(n6313) );
BUFX3TS U6804 ( .A(n4940), .Y(n6287) );
BUFX3TS U6805 ( .A(n4538), .Y(n6289) );
AOI22X1TS U6806 ( .A0(Data_1[15]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n6289), .Y(n5040) );
BUFX3TS U6807 ( .A(n5041), .Y(n6288) );
AOI22X1TS U6808 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[15]), .Y(n5039) );
OAI211X1TS U6809 ( .A0(n7020), .A1(n6313), .B0(n5040), .C0(n5039), .Y(n1926)
);
INVX2TS U6810 ( .A(FPSENCOS_d_ff2_Y[22]), .Y(n6324) );
BUFX3TS U6811 ( .A(n4940), .Y(n6292) );
AOI22X1TS U6812 ( .A0(Data_1[22]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n6289), .Y(n5043) );
BUFX3TS U6813 ( .A(n6368), .Y(n6290) );
BUFX3TS U6814 ( .A(n5041), .Y(n6293) );
AOI22X1TS U6815 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[22]), .Y(n5042) );
OAI211X1TS U6816 ( .A0(n7021), .A1(n6324), .B0(n5043), .C0(n5042), .Y(n1919)
);
INVX2TS U6817 ( .A(FPSENCOS_d_ff2_Y[11]), .Y(n6309) );
AOI22X1TS U6818 ( .A0(Data_1[11]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n6384), .Y(n5045) );
AOI22X1TS U6819 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[11]), .Y(n5044) );
OAI211X1TS U6820 ( .A0(n7020), .A1(n6309), .B0(n5045), .C0(n5044), .Y(n1930)
);
INVX2TS U6821 ( .A(FPSENCOS_d_ff2_Y[18]), .Y(n6318) );
AOI22X1TS U6822 ( .A0(Data_1[18]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n6289), .Y(n5047) );
AOI22X1TS U6823 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[18]), .Y(n5046) );
OAI211X1TS U6824 ( .A0(n7020), .A1(n6318), .B0(n5047), .C0(n5046), .Y(n1923)
);
INVX2TS U6825 ( .A(FPSENCOS_d_ff2_Y[20]), .Y(n6320) );
AOI22X1TS U6826 ( .A0(Data_1[20]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n6289), .Y(n5049) );
AOI22X1TS U6827 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[20]), .Y(n5048) );
INVX2TS U6828 ( .A(FPSENCOS_d_ff2_Y[16]), .Y(n6315) );
AOI22X1TS U6829 ( .A0(Data_1[16]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n6289), .Y(n5051) );
AOI22X1TS U6830 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[16]), .Y(n5050) );
INVX2TS U6831 ( .A(FPSENCOS_d_ff2_Y[14]), .Y(n6312) );
AOI22X1TS U6832 ( .A0(Data_1[14]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n6419), .Y(n5053) );
AOI22X1TS U6833 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[14]), .Y(n5052) );
AOI22X1TS U6834 ( .A0(Data_1[13]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n6384), .Y(n5055) );
AOI22X1TS U6835 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[13]), .Y(n5054) );
INVX2TS U6836 ( .A(FPSENCOS_d_ff2_Y[19]), .Y(n6319) );
AOI22X1TS U6837 ( .A0(Data_1[19]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n6289), .Y(n5057) );
AOI22X1TS U6838 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[19]), .Y(n5056) );
OAI211X1TS U6839 ( .A0(n7020), .A1(n6319), .B0(n5057), .C0(n5056), .Y(n1922)
);
INVX2TS U6840 ( .A(FPSENCOS_d_ff2_Y[17]), .Y(n6316) );
AOI22X1TS U6841 ( .A0(Data_1[17]), .A1(n6287), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n6289), .Y(n5059) );
AOI22X1TS U6842 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[17]), .Y(n5058) );
OAI211X1TS U6843 ( .A0(n7020), .A1(n6316), .B0(n5059), .C0(n5058), .Y(n1924)
);
INVX2TS U6844 ( .A(FPSENCOS_d_ff2_Y[21]), .Y(n6322) );
AOI22X1TS U6845 ( .A0(Data_1[21]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n6289), .Y(n5061) );
AOI22X1TS U6846 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[21]), .Y(n5060) );
OAI211X1TS U6847 ( .A0(n7021), .A1(n6322), .B0(n5061), .C0(n5060), .Y(n1920)
);
AOI22X1TS U6848 ( .A0(Data_2[24]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n4538), .Y(n5064) );
AOI22X1TS U6849 ( .A0(n5062), .A1(FPSENCOS_d_ff3_LUT_out[24]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[24]), .Y(n5063) );
AOI22X1TS U6850 ( .A0(Data_1[26]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n6294), .Y(n5067) );
AOI22X1TS U6851 ( .A0(n6295), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[26]), .Y(n5066) );
AOI22X1TS U6852 ( .A0(Data_1[24]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n6289), .Y(n5069) );
AOI22X1TS U6853 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[24]), .Y(n5068) );
AOI22X1TS U6854 ( .A0(Data_1[25]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n6294), .Y(n5071) );
AOI22X1TS U6855 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[25]), .Y(n5070) );
AOI22X1TS U6856 ( .A0(Data_1[30]), .A1(n6344), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n6294), .Y(n5073) );
AOI22X1TS U6857 ( .A0(n6295), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n6345), .B1(
FPSENCOS_d_ff2_X[30]), .Y(n5072) );
OAI211X1TS U6858 ( .A0(n7022), .A1(n6742), .B0(n5073), .C0(n5072), .Y(n1911)
);
AOI22X1TS U6859 ( .A0(Data_1[27]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n6294), .Y(n5075) );
AOI22X1TS U6860 ( .A0(n6295), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[27]), .Y(n5074) );
AOI22X1TS U6861 ( .A0(Data_1[29]), .A1(n6292), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n6294), .Y(n5077) );
AOI22X1TS U6862 ( .A0(n6295), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[29]), .Y(n5076) );
INVX2TS U6863 ( .A(n6219), .Y(n6500) );
NAND2X1TS U6864 ( .A(n5081), .B(n5084), .Y(n5087) );
INVX2TS U6865 ( .A(n5082), .Y(n5083) );
AOI21X1TS U6866 ( .A0(n5085), .A1(n5084), .B0(n5083), .Y(n5086) );
OAI22X1TS U6867 ( .A0(n5467), .A1(n5463), .B0(n5157), .B1(n5462), .Y(n5088)
);
OAI22X1TS U6868 ( .A0(n2315), .A1(n5465), .B0(n2365), .B1(n5464), .Y(n5093)
);
ADDHXLTS U6869 ( .A(n5089), .B(n5088), .CO(DP_OP_500J1_126_2852_n132), .S(
n5092) );
ADDHXLTS U6870 ( .A(DP_OP_501J1_127_1459_n931), .B(n2304), .CO(n4426), .S(
n5090) );
INVX2TS U6871 ( .A(n5090), .Y(n5468) );
OAI22X1TS U6872 ( .A0(n5474), .A1(n5468), .B0(n2315), .B1(n5466), .Y(n5091)
);
AOI22X1TS U6873 ( .A0(n2278), .A1(n6662), .B0(FPMULT_Op_MX[20]), .B1(n6633),
.Y(n5094) );
INVX2TS U6874 ( .A(n5138), .Y(n5095) );
NAND2X2TS U6875 ( .A(n5095), .B(n7030), .Y(n5533) );
NAND2X1TS U6876 ( .A(n5533), .B(n6662), .Y(n5536) );
NAND2X1TS U6877 ( .A(n5536), .B(FPMULT_Op_MX[20]), .Y(n5099) );
AOI21X1TS U6878 ( .A0(n5138), .A1(n5097), .B0(n5096), .Y(n5534) );
NAND2X1TS U6879 ( .A(n5533), .B(n5537), .Y(n5098) );
OAI21X1TS U6880 ( .A0(n5533), .A1(n5537), .B0(n5539), .Y(intadd_3_A_0_) );
NAND2X2TS U6881 ( .A(n5498), .B(n2278), .Y(n5141) );
AOI22X1TS U6882 ( .A0(n2278), .A1(n2223), .B0(n5498), .B1(FPMULT_Op_MX[19]),
.Y(n5105) );
NAND2X1TS U6883 ( .A(DP_OP_501J1_127_1459_n939), .B(n6633), .Y(n5103) );
INVX2TS U6884 ( .A(n5100), .Y(n5101) );
INVX2TS U6885 ( .A(n5102), .Y(n5104) );
OAI22X2TS U6886 ( .A0(n5130), .A1(n5105), .B0(n5104), .B1(n5103), .Y(n5525)
);
INVX2TS U6887 ( .A(n5525), .Y(n5113) );
INVX2TS U6888 ( .A(n7030), .Y(n5127) );
INVX2TS U6889 ( .A(n5524), .Y(n5111) );
AOI21X1TS U6890 ( .A0(n5142), .A1(n5107), .B0(n5106), .Y(n5109) );
NOR2X1TS U6891 ( .A(n5109), .B(n5108), .Y(n5119) );
NAND2X1TS U6892 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[20]), .Y(n5117) );
XOR2X1TS U6893 ( .A(n5115), .B(n5117), .Y(n5110) );
XOR2X1TS U6894 ( .A(n5119), .B(n5110), .Y(n5526) );
OAI21X1TS U6895 ( .A0(n5113), .A1(n5524), .B0(n5112), .Y(mult_x_309_n29) );
INVX2TS U6896 ( .A(n5117), .Y(n5114) );
NOR2X1TS U6897 ( .A(n5115), .B(n5114), .Y(n5118) );
INVX2TS U6898 ( .A(n5115), .Y(n5116) );
INVX2TS U6899 ( .A(n5520), .Y(n5125) );
NAND2X1TS U6900 ( .A(n6640), .B(FPMULT_Op_MY[21]), .Y(n5310) );
NAND2X2TS U6901 ( .A(DP_OP_501J1_127_1459_n939), .B(n2323), .Y(n5508) );
NOR2X1TS U6902 ( .A(n5508), .B(n5142), .Y(n5131) );
AOI22X1TS U6903 ( .A0(DP_OP_501J1_127_1459_n939), .A1(n5500), .B0(n2323),
.B1(FPMULT_Op_MX[20]), .Y(n5120) );
NOR2X1TS U6904 ( .A(n5121), .B(n5310), .Y(n5132) );
INVX2TS U6905 ( .A(n5521), .Y(n5124) );
OA21X1TS U6906 ( .A0(FPMULT_Op_MX[19]), .A1(n6633), .B0(n5138), .Y(n5128) );
XOR2X1TS U6907 ( .A(n5128), .B(n7030), .Y(n5122) );
XOR2X1TS U6908 ( .A(n5130), .B(n5122), .Y(n5522) );
OAI21X1TS U6909 ( .A0(n5125), .A1(n5124), .B0(n5123), .Y(mult_x_309_n22) );
INVX2TS U6910 ( .A(n5128), .Y(n5126) );
NAND2X1TS U6911 ( .A(n5127), .B(n5126), .Y(n5129) );
NOR2X2TS U6912 ( .A(n5132), .B(n5131), .Y(n5516) );
NOR2X1TS U6913 ( .A(n6670), .B(n2229), .Y(n5133) );
OAI21X1TS U6914 ( .A0(FPMULT_Op_MX[20]), .A1(n5500), .B0(n5133), .Y(n5143)
);
XOR2X1TS U6915 ( .A(n5500), .B(FPMULT_Op_MX[20]), .Y(n5134) );
XNOR2X1TS U6916 ( .A(n5141), .B(n5138), .Y(n5136) );
XNOR2X1TS U6917 ( .A(n5140), .B(n5136), .Y(n5518) );
OAI21X1TS U6918 ( .A0(n5517), .A1(n5516), .B0(n5137), .Y(mult_x_309_n17) );
INVX2TS U6919 ( .A(n5515), .Y(n5147) );
NAND2X1TS U6920 ( .A(n5143), .B(n5142), .Y(n5512) );
INVX2TS U6921 ( .A(n5512), .Y(n5146) );
XNOR2X1TS U6922 ( .A(n2278), .B(n5499), .Y(n5144) );
XOR2X1TS U6923 ( .A(n5144), .B(n5508), .Y(n5513) );
OAI21X1TS U6924 ( .A0(n5147), .A1(n5146), .B0(n5145), .Y(mult_x_309_n14) );
NOR2X1TS U6925 ( .A(n5461), .B(n5465), .Y(n5150) );
OAI22X1TS U6926 ( .A0(n2365), .A1(n5468), .B0(n5157), .B1(n5466), .Y(n5149)
);
NOR2X2TS U6927 ( .A(DP_OP_500J1_126_2852_n110), .B(DP_OP_500J1_126_2852_n116), .Y(n5428) );
NOR2X2TS U6928 ( .A(DP_OP_500J1_126_2852_n117), .B(DP_OP_500J1_126_2852_n122), .Y(n5433) );
NOR2X1TS U6929 ( .A(n5428), .B(n5433), .Y(n5166) );
ADDHXLTS U6930 ( .A(n6926), .B(FPMULT_Op_MX[19]), .CO(n4381), .S(n5148) );
INVX2TS U6931 ( .A(n5148), .Y(n5470) );
OAI22X1TS U6932 ( .A0(n2314), .A1(n5470), .B0(n2365), .B1(n5469), .Y(n5153)
);
ADDHX1TS U6933 ( .A(n5150), .B(n5149), .CO(DP_OP_500J1_126_2852_n141), .S(
n5152) );
NOR2X1TS U6934 ( .A(n5157), .B(n5468), .Y(n5156) );
OAI22X1TS U6935 ( .A0(n2365), .A1(n5470), .B0(n5461), .B1(n5469), .Y(n5155)
);
NOR2X1TS U6936 ( .A(DP_OP_500J1_126_2852_n136), .B(n5163), .Y(n5447) );
CMPR32X2TS U6937 ( .A(n5153), .B(n5152), .C(n5151), .CO(n5163), .S(n5162) );
ADDHXLTS U6938 ( .A(n5528), .B(n6925), .CO(n5154), .S(n4622) );
INVX2TS U6939 ( .A(n5154), .Y(n5473) );
OAI22X1TS U6940 ( .A0(n5474), .A1(n5475), .B0(n2315), .B1(n5473), .Y(n5161)
);
ADDHX1TS U6941 ( .A(n5156), .B(n5155), .CO(n5151), .S(n5159) );
OAI22X1TS U6942 ( .A0(n2314), .A1(n5475), .B0(n2365), .B1(n5473), .Y(n5158)
);
OAI22X1TS U6943 ( .A0(n2365), .A1(n5475), .B0(n5157), .B1(n5473), .Y(n5328)
);
NOR2X1TS U6944 ( .A(n5461), .B(n5470), .Y(n5327) );
NAND2X1TS U6945 ( .A(n5328), .B(n5327), .Y(n5329) );
INVX2TS U6946 ( .A(n5329), .Y(n5459) );
NAND2X1TS U6947 ( .A(n5159), .B(n5158), .Y(n5457) );
INVX2TS U6948 ( .A(n5457), .Y(n5160) );
AOI21X1TS U6949 ( .A0(n5458), .A1(n5459), .B0(n5160), .Y(n5455) );
NAND2X1TS U6950 ( .A(n5162), .B(n5161), .Y(n5453) );
NAND2X1TS U6951 ( .A(DP_OP_500J1_126_2852_n136), .B(n5163), .Y(n5448) );
OR2X2TS U6952 ( .A(DP_OP_500J1_126_2852_n129), .B(DP_OP_500J1_126_2852_n135),
.Y(n5444) );
NAND2X1TS U6953 ( .A(DP_OP_500J1_126_2852_n129), .B(
DP_OP_500J1_126_2852_n135), .Y(n5443) );
INVX2TS U6954 ( .A(n5443), .Y(n5164) );
AOI21X2TS U6955 ( .A0(n5445), .A1(n5444), .B0(n5164), .Y(n5441) );
NAND2X1TS U6956 ( .A(DP_OP_500J1_126_2852_n123), .B(
DP_OP_500J1_126_2852_n128), .Y(n5439) );
OAI21X2TS U6957 ( .A0(n5441), .A1(n5438), .B0(n5439), .Y(n5427) );
NAND2X2TS U6958 ( .A(DP_OP_500J1_126_2852_n117), .B(
DP_OP_500J1_126_2852_n122), .Y(n5434) );
NAND2X1TS U6959 ( .A(DP_OP_500J1_126_2852_n110), .B(
DP_OP_500J1_126_2852_n116), .Y(n5429) );
OAI21X1TS U6960 ( .A0(n5428), .A1(n5434), .B0(n5429), .Y(n5165) );
AOI21X4TS U6961 ( .A0(n5166), .A1(n5427), .B0(n5165), .Y(n5426) );
OR2X2TS U6962 ( .A(DP_OP_500J1_126_2852_n102), .B(DP_OP_500J1_126_2852_n104),
.Y(n5420) );
OAI22X1TS U6963 ( .A0(n2368), .A1(n2442), .B0(n2299), .B1(n2347), .Y(n5167)
);
NOR2X2TS U6964 ( .A(DP_OP_500J1_126_2852_n109), .B(DP_OP_500J1_126_2852_n105), .Y(n5418) );
NOR2X1TS U6965 ( .A(n5172), .B(n5418), .Y(n5403) );
CMPR32X2TS U6966 ( .A(n5168), .B(n5167), .C(DP_OP_500J1_126_2852_n100), .CO(
n5174), .S(n5169) );
NOR2X1TS U6967 ( .A(n2299), .B(n2442), .Y(n5173) );
NAND2X1TS U6968 ( .A(n5403), .B(n5408), .Y(n5177) );
NAND2X2TS U6969 ( .A(DP_OP_500J1_126_2852_n109), .B(
DP_OP_500J1_126_2852_n105), .Y(n5423) );
NAND2X1TS U6970 ( .A(DP_OP_500J1_126_2852_n102), .B(
DP_OP_500J1_126_2852_n104), .Y(n5419) );
INVX2TS U6971 ( .A(n5419), .Y(n5411) );
NAND2X1TS U6972 ( .A(DP_OP_500J1_126_2852_n101), .B(n5169), .Y(n5415) );
INVX2TS U6973 ( .A(n5415), .Y(n5170) );
AOI21X1TS U6974 ( .A0(n5411), .A1(n2232), .B0(n5170), .Y(n5171) );
OAI21X1TS U6975 ( .A0(n5172), .A1(n5423), .B0(n5171), .Y(n5404) );
NAND2X1TS U6976 ( .A(n5174), .B(n5173), .Y(n5407) );
INVX2TS U6977 ( .A(n5407), .Y(n5175) );
AOI21X1TS U6978 ( .A0(n5404), .A1(n5408), .B0(n5175), .Y(n5176) );
BUFX3TS U6979 ( .A(n6639), .Y(n6579) );
AOI22X1TS U6980 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n6579), .Y(n5178) );
AOI22X1TS U6981 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n6579), .Y(n5180) );
BUFX3TS U6982 ( .A(n6639), .Y(n5286) );
AOI22X1TS U6983 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n5286), .Y(n5181) );
AOI22X1TS U6984 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n6579), .Y(n5182) );
BUFX3TS U6985 ( .A(n6639), .Y(n5305) );
AOI22X1TS U6986 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n5305), .Y(n5183) );
AOI22X1TS U6987 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n5286), .Y(n5184) );
INVX2TS U6988 ( .A(n6286), .Y(n6542) );
AOI22X1TS U6989 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n5299), .Y(n5185) );
AOI22X1TS U6990 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n6579), .Y(n5186) );
AOI22X1TS U6991 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n5305), .Y(n5187) );
AOI22X1TS U6992 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n5305), .Y(n5188) );
AOI22X1TS U6993 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n6579), .Y(n5189) );
AOI22X1TS U6994 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n6579), .Y(n5190) );
AOI22X1TS U6995 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n6579), .Y(n5191) );
AOI22X1TS U6996 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n6579), .Y(n5192) );
AOI22X1TS U6997 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n5286), .Y(n5193) );
AOI22X1TS U6998 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n5286), .Y(n5194) );
AOI22X1TS U6999 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5195), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n5286), .Y(n5196) );
AOI22X1TS U7000 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n5305), .Y(n5198) );
AOI22X1TS U7001 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n6572), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n5299), .Y(n5199) );
AOI22X1TS U7002 ( .A0(n5201), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2355),
.B1(n5200), .Y(n5205) );
INVX2TS U7003 ( .A(n5232), .Y(n5211) );
AOI22X1TS U7004 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2349),
.B1(n5220), .Y(n5210) );
AOI22X1TS U7005 ( .A0(n2355), .A1(n5208), .B0(n2352), .B1(n5207), .Y(n5209)
);
AOI22X1TS U7006 ( .A0(n5278), .A1(n2362), .B0(n2355), .B1(n5245), .Y(n5218)
);
NAND2X1TS U7007 ( .A(n5269), .B(n6718), .Y(n5216) );
NAND2X1TS U7008 ( .A(n5213), .B(n5212), .Y(n5215) );
OR2X1TS U7009 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n5214) );
AOI22X1TS U7010 ( .A0(n3612), .A1(n5277), .B0(n2352), .B1(n5244), .Y(n5217)
);
INVX2TS U7011 ( .A(n5219), .Y(n5238) );
AOI22X1TS U7012 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2354),
.B1(n5238), .Y(n5222) );
AOI22X1TS U7013 ( .A0(n5281), .A1(n5220), .B0(n2353), .B1(n5280), .Y(n5221)
);
AOI22X1TS U7014 ( .A0(n5201), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2354),
.B1(n5227), .Y(n5224) );
AOI22X1TS U7015 ( .A0(n5281), .A1(n5228), .B0(n2353), .B1(n5226), .Y(n5223)
);
AOI22X1TS U7016 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n4405),
.B1(n5226), .Y(n5230) );
AOI22X1TS U7017 ( .A0(n2354), .A1(n5228), .B0(n2352), .B1(n5227), .Y(n5229)
);
OAI22X1TS U7018 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n2210), .B0(n2307),
.B1(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n6395) );
AOI22X1TS U7019 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n2349),
.B1(n5232), .Y(n5234) );
AOI22X1TS U7020 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n5262), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n5286), .Y(n5235) );
AOI22X1TS U7021 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n5262), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n5286), .Y(n5236) );
OAI222X4TS U7022 ( .A0(n2307), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .B0(n2210), .B1(FPADDSUB_Raw_mant_NRM_SWR[15]), .C0(FPADDSUB_DmP_mant_SHT1_SW[13]), .C1(
n5820), .Y(n5284) );
INVX2TS U7023 ( .A(n5237), .Y(n5279) );
AOI22X1TS U7024 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2352),
.B1(n5279), .Y(n5240) );
AOI22X1TS U7025 ( .A0(n5281), .A1(n5238), .B0(n2355), .B1(n5280), .Y(n5239)
);
AOI22X1TS U7026 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n4405),
.B1(n5245), .Y(n5242) );
AOI22X1TS U7027 ( .A0(n5281), .A1(n5279), .B0(n2352), .B1(n5277), .Y(n5241)
);
AOI22X1TS U7028 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n4405),
.B1(n5244), .Y(n5248) );
AOI22X1TS U7029 ( .A0(n2354), .A1(n5277), .B0(n2353), .B1(n5245), .Y(n5247)
);
AOI22X1TS U7030 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n5262), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n5286), .Y(n5249) );
AOI22X1TS U7031 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n5262), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n5286), .Y(n5250) );
AOI22X1TS U7032 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n5305), .Y(n5251) );
AOI22X1TS U7033 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n5259), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n5305), .Y(n5252) );
AOI22X1TS U7034 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n5299), .Y(n5253) );
AOI22X1TS U7035 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n5299), .Y(n5254) );
AOI22X1TS U7036 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n5299), .Y(n5255) );
AOI22X1TS U7037 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n5299), .Y(n5256) );
AOI22X1TS U7038 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n5299), .Y(n5257) );
AOI22X1TS U7039 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n6579), .Y(n5258) );
AOI22X1TS U7040 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5259), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n5299), .Y(n5260) );
BUFX3TS U7041 ( .A(n4402), .Y(n5308) );
AOI22X1TS U7042 ( .A0(FPADDSUB_intDY_EWSW[24]), .A1(n5263), .B0(
FPADDSUB_DMP_EXP_EWSW[24]), .B1(n5294), .Y(n5261) );
INVX2TS U7043 ( .A(n5264), .Y(n1465) );
AOI22X1TS U7044 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n5294), .Y(n5266) );
AOI22X1TS U7045 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n5294), .Y(n5267) );
AOI22X1TS U7046 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[25]), .B1(n5294), .Y(n5268) );
NAND2X1TS U7047 ( .A(n5269), .B(n6732), .Y(n5270) );
OAI2BB1X1TS U7048 ( .A0N(n5271), .A1N(n5270), .B0(n2350), .Y(n6390) );
AOI22X1TS U7049 ( .A0(n5273), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n5272),
.B1(n6390), .Y(n5276) );
NAND2X1TS U7050 ( .A(n2349), .B(n5274), .Y(n5275) );
AOI22X1TS U7051 ( .A0(n5278), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n4405),
.B1(n5277), .Y(n5283) );
AOI22X1TS U7052 ( .A0(n5281), .A1(n5280), .B0(n2354), .B1(n5279), .Y(n5282)
);
AOI22X1TS U7053 ( .A0(FPADDSUB_intDY_EWSW[26]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[26]), .B1(n5294), .Y(n5285) );
AOI22X1TS U7054 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n5286), .Y(n5287) );
AOI22X1TS U7055 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n5305), .Y(n5288) );
AOI22X1TS U7056 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n6217), .Y(n5289) );
AOI22X1TS U7057 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n6217), .Y(n5290) );
AOI22X1TS U7058 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n5305), .Y(n5291) );
AOI22X1TS U7059 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n6217), .Y(n5293) );
AOI22X1TS U7060 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n5294), .Y(n5295) );
AOI22X1TS U7061 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n5305), .Y(n5296) );
AOI22X1TS U7062 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n6217), .Y(n5297) );
AOI22X1TS U7063 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n6217), .Y(n5298) );
AOI22X1TS U7064 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n5299), .Y(n5300) );
AOI22X1TS U7065 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n6217), .Y(n5301) );
AOI22X1TS U7066 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n6217), .Y(n5302) );
AOI22X1TS U7067 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5303), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n6217), .Y(n5304) );
AOI22X1TS U7068 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5306), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n5305), .Y(n5307) );
NOR2X1TS U7069 ( .A(n2299), .B(n5464), .Y(DP_OP_500J1_126_2852_n161) );
NAND2X1TS U7070 ( .A(n5609), .B(n6668), .Y(n5309) );
NAND2X1TS U7071 ( .A(FPMULT_Op_MX[6]), .B(n6440), .Y(n5636) );
NOR2X1TS U7072 ( .A(n5309), .B(n5636), .Y(n5641) );
NOR2X1TS U7073 ( .A(n6692), .B(n6668), .Y(n5331) );
INVX2TS U7074 ( .A(n5331), .Y(n5637) );
NOR2X1TS U7075 ( .A(n5637), .B(n5636), .Y(n5635) );
NOR2X1TS U7076 ( .A(n2299), .B(n5473), .Y(DP_OP_500J1_126_2852_n185) );
OA21X1TS U7077 ( .A0(n5311), .A1(n5508), .B0(n5310), .Y(n5511) );
NOR2X1TS U7078 ( .A(DP_OP_501J1_127_1459_n939), .B(n2323), .Y(n5506) );
OAI21X1TS U7079 ( .A0(n5511), .A1(n5506), .B0(n5508), .Y(n5532) );
NOR2XLTS U7080 ( .A(n6634), .B(n6686), .Y(n5315) );
OAI222X1TS U7081 ( .A0(n6644), .A1(n5317), .B0(n5316), .B1(n5315), .C0(n5314), .C1(n5313), .Y(n1691) );
NOR3X1TS U7082 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .C(n6684), .Y(n6213) );
AOI31XLTS U7083 ( .A0(n5318), .A1(n6212), .A2(n6738), .B0(n6213), .Y(n5319)
);
OAI21XLTS U7084 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
n5881), .B0(n5319), .Y(n2149) );
OAI21XLTS U7085 ( .A0(n5320), .A1(n6208), .B0(n4529), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
NAND2X1TS U7086 ( .A(n5331), .B(n7028), .Y(n5639) );
NAND2X1TS U7087 ( .A(FPMULT_Op_MX[6]), .B(n2279), .Y(n5640) );
CLKAND2X2TS U7088 ( .A(n5639), .B(n5332), .Y(n6793) );
NOR2X1TS U7089 ( .A(n6690), .B(n2444), .Y(n5573) );
NAND2X1TS U7090 ( .A(n7029), .B(n5573), .Y(n5576) );
NAND2X1TS U7091 ( .A(n2224), .B(n6925), .Y(n5598) );
CLKAND2X2TS U7092 ( .A(n5576), .B(n5333), .Y(n6829) );
MXI2X1TS U7093 ( .A(Data_2[12]), .B(n6631), .S0(n5817), .Y(n6847) );
NOR2X1TS U7094 ( .A(FPMULT_Op_MY[15]), .B(n2224), .Y(n6449) );
NOR2X1TS U7095 ( .A(n6645), .B(n5336), .Y(n5575) );
INVX2TS U7096 ( .A(n5575), .Y(n5337) );
OR3X1TS U7097 ( .A(n6449), .B(n5337), .C(n6690), .Y(intadd_0_B_1_) );
INVX2TS U7098 ( .A(n5346), .Y(n5350) );
NAND2X1TS U7099 ( .A(n5350), .B(n5348), .Y(n5341) );
INVX2TS U7100 ( .A(n5349), .Y(n5339) );
AOI21X1TS U7101 ( .A0(n5339), .A1(n5348), .B0(n5338), .Y(n5340) );
NAND2X1TS U7102 ( .A(n5343), .B(n5342), .Y(n5344) );
XNOR2X1TS U7103 ( .A(n5345), .B(n5344), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
NAND2X1TS U7104 ( .A(n5350), .B(n5349), .Y(n5351) );
INVX2TS U7105 ( .A(n5353), .Y(n5362) );
INVX2TS U7106 ( .A(n5354), .Y(n5356) );
NAND2X1TS U7107 ( .A(n5356), .B(n5355), .Y(n5357) );
XNOR2X1TS U7108 ( .A(n5358), .B(n5357), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
INVX2TS U7109 ( .A(n5359), .Y(n5361) );
NAND2X1TS U7110 ( .A(n5361), .B(n5360), .Y(n5363) );
INVX2TS U7111 ( .A(n5364), .Y(n5366) );
NAND2X1TS U7112 ( .A(n5366), .B(n5365), .Y(n5368) );
NAND2X1TS U7113 ( .A(n2446), .B(n5369), .Y(n5371) );
XNOR2X1TS U7114 ( .A(n5371), .B(n5370), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
INVX2TS U7115 ( .A(n5372), .Y(n5374) );
NAND2X1TS U7116 ( .A(n5374), .B(n5373), .Y(n5376) );
INVX2TS U7117 ( .A(n5377), .Y(n5379) );
NAND2X1TS U7118 ( .A(n5379), .B(n5378), .Y(n5381) );
NAND2X1TS U7119 ( .A(n5383), .B(n5382), .Y(n5385) );
XNOR2X1TS U7120 ( .A(n5385), .B(n5384), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
OAI22X1TS U7121 ( .A0(n5398), .A1(n5388), .B0(n5402), .B1(n5386), .Y(
DP_OP_502J1_128_2852_n147) );
OAI22X1TS U7122 ( .A0(n2311), .A1(n5388), .B0(n2366), .B1(n5386), .Y(
DP_OP_502J1_128_2852_n150) );
OAI22X1TS U7123 ( .A0(n5394), .A1(n5388), .B0(n5387), .B1(n5386), .Y(
DP_OP_502J1_128_2852_n151) );
OAI22X1TS U7124 ( .A0(n5398), .A1(n5389), .B0(n2298), .B1(n5390), .Y(
DP_OP_502J1_128_2852_n154) );
OAI22X1TS U7125 ( .A0(n5398), .A1(n5390), .B0(n2317), .B1(n5389), .Y(
DP_OP_502J1_128_2852_n155) );
OAI22X1TS U7126 ( .A0(n5400), .A1(n5390), .B0(n2312), .B1(n5389), .Y(
DP_OP_502J1_128_2852_n157) );
OAI22X1TS U7127 ( .A0(n2311), .A1(n5390), .B0(n5394), .B1(n5389), .Y(
DP_OP_502J1_128_2852_n158) );
OAI22X1TS U7128 ( .A0(n5398), .A1(n5391), .B0(n2447), .B1(n5392), .Y(
DP_OP_502J1_128_2852_n162) );
OAI22X1TS U7129 ( .A0(n2317), .A1(n5392), .B0(n5400), .B1(n5391), .Y(
DP_OP_502J1_128_2852_n164) );
OAI22X1TS U7130 ( .A0(n5400), .A1(n5392), .B0(n2312), .B1(n5391), .Y(
DP_OP_502J1_128_2852_n165) );
OAI22X1TS U7131 ( .A0(n5398), .A1(n5393), .B0(n2298), .B1(n5395), .Y(
DP_OP_502J1_128_2852_n170) );
OAI22X1TS U7132 ( .A0(n2369), .A1(n5395), .B0(n5402), .B1(n5393), .Y(
DP_OP_502J1_128_2852_n171) );
OAI22X1TS U7133 ( .A0(n5402), .A1(n5395), .B0(n2382), .B1(n5393), .Y(
DP_OP_502J1_128_2852_n172) );
OAI22X1TS U7134 ( .A0(n2311), .A1(n5395), .B0(n5394), .B1(n5393), .Y(
DP_OP_502J1_128_2852_n174) );
OAI22X1TS U7135 ( .A0(n2369), .A1(n5396), .B0(n2298), .B1(n5397), .Y(
DP_OP_502J1_128_2852_n178) );
OAI22X1TS U7136 ( .A0(n5398), .A1(n5397), .B0(n2317), .B1(n5396), .Y(
DP_OP_502J1_128_2852_n179) );
OAI22X1TS U7137 ( .A0(n2317), .A1(n5397), .B0(n5400), .B1(n5396), .Y(
DP_OP_502J1_128_2852_n180) );
OAI22X1TS U7138 ( .A0(n5400), .A1(n5397), .B0(n2312), .B1(n5396), .Y(
DP_OP_502J1_128_2852_n181) );
OAI22X1TS U7139 ( .A0(n5398), .A1(n5399), .B0(n2298), .B1(n5401), .Y(
DP_OP_502J1_128_2852_n186) );
OAI22X1TS U7140 ( .A0(n5398), .A1(n5401), .B0(n2317), .B1(n5399), .Y(
DP_OP_502J1_128_2852_n187) );
OAI22X1TS U7141 ( .A0(n5402), .A1(n5401), .B0(n2382), .B1(n5399), .Y(
DP_OP_502J1_128_2852_n188) );
INVX2TS U7142 ( .A(n5403), .Y(n5406) );
INVX2TS U7143 ( .A(n5404), .Y(n5405) );
NAND2X1TS U7144 ( .A(n5408), .B(n5407), .Y(n5409) );
XNOR2X1TS U7145 ( .A(n5410), .B(n5409), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U7146 ( .A(n5418), .Y(n5424) );
NAND2X1TS U7147 ( .A(n5424), .B(n5420), .Y(n5414) );
INVX2TS U7148 ( .A(n5423), .Y(n5412) );
AOI21X1TS U7149 ( .A0(n5412), .A1(n5420), .B0(n5411), .Y(n5413) );
OAI21X1TS U7150 ( .A0(n5426), .A1(n5414), .B0(n5413), .Y(n5417) );
NAND2X1TS U7151 ( .A(n2232), .B(n5415), .Y(n5416) );
XNOR2X1TS U7152 ( .A(n5417), .B(n5416), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
OAI21X1TS U7153 ( .A0(n5426), .A1(n5418), .B0(n5423), .Y(n5422) );
NAND2X1TS U7154 ( .A(n5420), .B(n5419), .Y(n5421) );
XNOR2X1TS U7155 ( .A(n5422), .B(n5421), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
NAND2X1TS U7156 ( .A(n5424), .B(n5423), .Y(n5425) );
INVX2TS U7157 ( .A(n5428), .Y(n5430) );
NAND2X1TS U7158 ( .A(n5430), .B(n5429), .Y(n5431) );
XNOR2X1TS U7159 ( .A(n5432), .B(n5431), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
INVX2TS U7160 ( .A(n5433), .Y(n5435) );
NAND2X1TS U7161 ( .A(n5435), .B(n5434), .Y(n5437) );
INVX2TS U7162 ( .A(n5438), .Y(n5440) );
NAND2X1TS U7163 ( .A(n5440), .B(n5439), .Y(n5442) );
NAND2X1TS U7164 ( .A(n5444), .B(n5443), .Y(n5446) );
XNOR2X1TS U7165 ( .A(n5446), .B(n5445), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
INVX2TS U7166 ( .A(n5447), .Y(n5449) );
NAND2X1TS U7167 ( .A(n5449), .B(n5448), .Y(n5451) );
INVX2TS U7168 ( .A(n5452), .Y(n5454) );
NAND2X1TS U7169 ( .A(n5454), .B(n5453), .Y(n5456) );
NAND2X1TS U7170 ( .A(n5458), .B(n5457), .Y(n5460) );
XNOR2X1TS U7171 ( .A(n5460), .B(n5459), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
OAI22X1TS U7172 ( .A0(n5472), .A1(n2346), .B0(n2313), .B1(n2442), .Y(
DP_OP_500J1_126_2852_n147) );
OAI22X1TS U7173 ( .A0(n2315), .A1(n2346), .B0(n2365), .B1(n2442), .Y(
DP_OP_500J1_126_2852_n150) );
OAI22X1TS U7174 ( .A0(n2365), .A1(n2346), .B0(n5461), .B1(n2442), .Y(
DP_OP_500J1_126_2852_n151) );
OAI22X1TS U7175 ( .A0(n5472), .A1(n5462), .B0(n5471), .B1(n5463), .Y(
DP_OP_500J1_126_2852_n154) );
OAI22X1TS U7176 ( .A0(n5472), .A1(n5463), .B0(n2313), .B1(n5462), .Y(
DP_OP_500J1_126_2852_n155) );
OAI22X1TS U7177 ( .A0(n5474), .A1(n5463), .B0(n2315), .B1(n5462), .Y(
DP_OP_500J1_126_2852_n157) );
OAI22X1TS U7178 ( .A0(n2315), .A1(n5463), .B0(n2365), .B1(n5462), .Y(
DP_OP_500J1_126_2852_n158) );
OAI22X1TS U7179 ( .A0(n5472), .A1(n5464), .B0(n2299), .B1(n5465), .Y(
DP_OP_500J1_126_2852_n162) );
OAI22X1TS U7180 ( .A0(n2313), .A1(n5465), .B0(n2367), .B1(n5464), .Y(
DP_OP_500J1_126_2852_n164) );
OAI22X1TS U7181 ( .A0(n5474), .A1(n5465), .B0(n2315), .B1(n5464), .Y(
DP_OP_500J1_126_2852_n165) );
OAI22X1TS U7182 ( .A0(n2368), .A1(n5466), .B0(n2299), .B1(n5468), .Y(
DP_OP_500J1_126_2852_n170) );
OAI22X1TS U7183 ( .A0(n2368), .A1(n5468), .B0(n2313), .B1(n5466), .Y(
DP_OP_500J1_126_2852_n171) );
OAI22X1TS U7184 ( .A0(n2313), .A1(n5468), .B0(n2367), .B1(n5466), .Y(
DP_OP_500J1_126_2852_n172) );
OAI22X1TS U7185 ( .A0(n2314), .A1(n5468), .B0(n2365), .B1(n5466), .Y(
DP_OP_500J1_126_2852_n174) );
OAI22X1TS U7186 ( .A0(n5472), .A1(n5469), .B0(n2299), .B1(n5470), .Y(
DP_OP_500J1_126_2852_n178) );
OAI22X1TS U7187 ( .A0(n5472), .A1(n5470), .B0(n2313), .B1(n5469), .Y(
DP_OP_500J1_126_2852_n179) );
OAI22X1TS U7188 ( .A0(n5476), .A1(n5470), .B0(n2367), .B1(n5469), .Y(
DP_OP_500J1_126_2852_n180) );
OAI22X1TS U7189 ( .A0(n5474), .A1(n5470), .B0(n2315), .B1(n5469), .Y(
DP_OP_500J1_126_2852_n181) );
OAI22X1TS U7190 ( .A0(n5472), .A1(n5473), .B0(n2299), .B1(n5475), .Y(
DP_OP_500J1_126_2852_n186) );
OAI22X1TS U7191 ( .A0(n5472), .A1(n5475), .B0(n2313), .B1(n5473), .Y(
DP_OP_500J1_126_2852_n187) );
OAI22X1TS U7192 ( .A0(n5476), .A1(n5475), .B0(n5474), .B1(n5473), .Y(
DP_OP_500J1_126_2852_n188) );
NOR3BX1TS U7193 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n5477) );
XOR2X1TS U7194 ( .A(n2320), .B(n5477), .Y(DP_OP_234J1_132_4955_n15) );
OAI2BB1X1TS U7195 ( .A0N(FPMULT_Op_MY[29]), .A1N(n6681), .B0(n5483), .Y(
n5478) );
XOR2X1TS U7196 ( .A(n2320), .B(n5478), .Y(DP_OP_234J1_132_4955_n16) );
OAI2BB1X1TS U7197 ( .A0N(FPMULT_Op_MY[28]), .A1N(n6681), .B0(n5483), .Y(
n5479) );
XOR2X1TS U7198 ( .A(n2320), .B(n5479), .Y(DP_OP_234J1_132_4955_n17) );
OAI2BB1X1TS U7199 ( .A0N(FPMULT_Op_MY[27]), .A1N(n6681), .B0(n5483), .Y(
n5480) );
XOR2X1TS U7200 ( .A(n2320), .B(n5480), .Y(DP_OP_234J1_132_4955_n18) );
OAI2BB1X1TS U7201 ( .A0N(FPMULT_Op_MY[26]), .A1N(n6681), .B0(n5483), .Y(
n5481) );
XOR2X1TS U7202 ( .A(n2320), .B(n5481), .Y(DP_OP_234J1_132_4955_n19) );
OAI2BB1X1TS U7203 ( .A0N(FPMULT_Op_MY[25]), .A1N(n6681), .B0(n5483), .Y(
n5482) );
XOR2X1TS U7204 ( .A(n2319), .B(n5482), .Y(DP_OP_234J1_132_4955_n20) );
OAI2BB1X1TS U7205 ( .A0N(FPMULT_Op_MY[24]), .A1N(n6681), .B0(n5483), .Y(
n5484) );
XOR2X1TS U7206 ( .A(n2319), .B(n5484), .Y(DP_OP_234J1_132_4955_n21) );
NOR2BX1TS U7207 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5485) );
XOR2X1TS U7208 ( .A(n6667), .B(n5485), .Y(DP_OP_26J1_129_1325_n14) );
NOR2BX1TS U7209 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5486) );
XOR2X1TS U7210 ( .A(n6667), .B(n5486), .Y(DP_OP_26J1_129_1325_n15) );
NOR2BX1TS U7211 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5487) );
XOR2X1TS U7212 ( .A(n6667), .B(n5487), .Y(DP_OP_26J1_129_1325_n16) );
NOR2BX1TS U7213 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5488) );
XOR2X1TS U7214 ( .A(n6667), .B(n5488), .Y(DP_OP_26J1_129_1325_n17) );
INVX2TS U7215 ( .A(n6671), .Y(n5490) );
XOR2X1TS U7216 ( .A(n5503), .B(n5502), .Y(n5505) );
XNOR2X1TS U7217 ( .A(n5505), .B(n5504), .Y(mult_x_309_n37) );
INVX2TS U7218 ( .A(n5506), .Y(n5507) );
AOI21X1TS U7219 ( .A0(n5508), .A1(n5507), .B0(n5511), .Y(n5509) );
XNOR2X1TS U7220 ( .A(n5513), .B(n5512), .Y(n5514) );
XNOR2X1TS U7221 ( .A(n5515), .B(n5514), .Y(mult_x_309_n15) );
XOR2X1TS U7222 ( .A(n5517), .B(n5516), .Y(n5519) );
XNOR2X1TS U7223 ( .A(n5519), .B(n5518), .Y(mult_x_309_n18) );
XOR2X1TS U7224 ( .A(n5521), .B(n5520), .Y(n5523) );
XOR2X1TS U7225 ( .A(n5523), .B(n5522), .Y(mult_x_309_n23) );
XOR2X1TS U7226 ( .A(n5525), .B(n5524), .Y(n5527) );
XNOR2X1TS U7227 ( .A(n5527), .B(n5526), .Y(mult_x_309_n30) );
NAND2X1TS U7228 ( .A(n5528), .B(n6633), .Y(n5542) );
NOR2BX1TS U7229 ( .AN(n5542), .B(n5529), .Y(n5531) );
XOR2X1TS U7230 ( .A(n5531), .B(n5530), .Y(intadd_3_CI) );
OAI2BB1X1TS U7231 ( .A0N(intadd_3_n1), .A1N(n5532), .B0(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
INVX2TS U7232 ( .A(n5533), .Y(n5540) );
AOI21X1TS U7233 ( .A0(n5540), .A1(n5537), .B0(n5534), .Y(n5535) );
NAND2X1TS U7234 ( .A(n6662), .B(FPMULT_Op_MX[19]), .Y(n5541) );
AOI21X1TS U7235 ( .A0(n5542), .A1(n5541), .B0(n5540), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
NOR2BX2TS U7236 ( .AN(n5544), .B(n5543), .Y(n5580) );
INVX2TS U7237 ( .A(n5547), .Y(n5545) );
NAND2X1TS U7238 ( .A(n5545), .B(n5546), .Y(n5549) );
INVX2TS U7239 ( .A(n5546), .Y(n5548) );
XNOR2X1TS U7240 ( .A(n5552), .B(n5551), .Y(n5554) );
XOR2X1TS U7241 ( .A(n5554), .B(n5553), .Y(n5579) );
INVX2TS U7242 ( .A(n5581), .Y(n5556) );
INVX2TS U7243 ( .A(n5580), .Y(n5555) );
OAI22X1TS U7244 ( .A0(n5557), .A1(n5579), .B0(n5556), .B1(n5555), .Y(
intadd_0_A_6_) );
INVX2TS U7245 ( .A(n5559), .Y(n5562) );
OAI21X1TS U7246 ( .A0(n5562), .A1(n4732), .B0(n5561), .Y(n5588) );
OAI21X1TS U7247 ( .A0(n5565), .A1(n5564), .B0(n5563), .Y(n5587) );
XNOR2X1TS U7248 ( .A(n5567), .B(n5566), .Y(n5568) );
ACHCINX2TS U7249 ( .CIN(n5588), .A(n5587), .B(n5589), .CO(intadd_0_A_4_) );
XNOR2X1TS U7250 ( .A(n5570), .B(n5595), .Y(n5572) );
XOR2X1TS U7251 ( .A(n5572), .B(n5571), .Y(intadd_0_A_1_) );
OAI21X1TS U7252 ( .A0(n6921), .A1(n2406), .B0(n5576), .Y(n5602) );
INVX2TS U7253 ( .A(n5573), .Y(n5574) );
XNOR2X1TS U7254 ( .A(n5575), .B(n5574), .Y(n5604) );
NOR2X1TS U7255 ( .A(n5576), .B(n2406), .Y(n5603) );
AOI21X1TS U7256 ( .A0(n5602), .A1(n5604), .B0(n5603), .Y(intadd_0_A_0_) );
NOR2BX1TS U7257 ( .AN(n5578), .B(n5577), .Y(intadd_0_B_7_) );
XOR2X1TS U7258 ( .A(n5580), .B(n5579), .Y(n5582) );
XNOR2X1TS U7259 ( .A(n5582), .B(n5581), .Y(intadd_0_B_5_) );
XOR2X1TS U7260 ( .A(n5584), .B(n5583), .Y(n5586) );
XNOR2X1TS U7261 ( .A(n5586), .B(n5585), .Y(intadd_0_B_4_) );
XOR2X1TS U7262 ( .A(n5588), .B(n5587), .Y(n5590) );
XNOR2X1TS U7263 ( .A(n5590), .B(n5589), .Y(intadd_0_B_3_) );
XOR2X1TS U7264 ( .A(n5592), .B(n5591), .Y(n5594) );
XOR2X1TS U7265 ( .A(n5594), .B(n5593), .Y(intadd_0_B_2_) );
NOR3BX1TS U7266 ( .AN(n5598), .B(n6883), .C(n6690), .Y(n5599) );
INVX2TS U7267 ( .A(n5599), .Y(n5601) );
XNOR2X1TS U7268 ( .A(n5601), .B(n5600), .Y(intadd_0_CI) );
XNOR2X1TS U7269 ( .A(n5605), .B(n5604), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
AOI22X1TS U7270 ( .A0(FPMULT_Op_MX[9]), .A1(n2279), .B0(
DP_OP_501J1_127_1459_n910), .B1(DP_OP_501J1_127_1459_n952), .Y(n5606)
);
NAND2X1TS U7271 ( .A(n2277), .B(n2279), .Y(n5617) );
NOR2X2TS U7272 ( .A(n5618), .B(n5617), .Y(n5616) );
XNOR2X1TS U7273 ( .A(n5609), .B(n5608), .Y(n5611) );
XOR2X1TS U7274 ( .A(n5611), .B(n5610), .Y(n5615) );
OAI2BB1X1TS U7275 ( .A0N(n5613), .A1N(n5616), .B0(n5612), .Y(mult_x_311_n36)
);
XOR2X1TS U7276 ( .A(n5613), .B(n5616), .Y(n5614) );
XOR2X1TS U7277 ( .A(n5615), .B(n5614), .Y(mult_x_311_n37) );
AOI21X1TS U7278 ( .A0(n5618), .A1(n5617), .B0(n5616), .Y(intadd_1_A_0_) );
XNOR2X1TS U7279 ( .A(n5620), .B(n5619), .Y(n5622) );
XOR2X1TS U7280 ( .A(n5622), .B(n5621), .Y(mult_x_311_n15) );
XOR2X1TS U7281 ( .A(n5624), .B(n5623), .Y(n5626) );
XNOR2X1TS U7282 ( .A(n5626), .B(n5625), .Y(mult_x_311_n18) );
XNOR2X1TS U7283 ( .A(n5628), .B(n5627), .Y(n5630) );
XOR2X1TS U7284 ( .A(n5630), .B(n5629), .Y(mult_x_311_n23) );
XOR2X1TS U7285 ( .A(n5632), .B(n5631), .Y(n5634) );
XOR2X1TS U7286 ( .A(n5634), .B(n5633), .Y(mult_x_311_n30) );
NOR2X1TS U7287 ( .A(n5639), .B(n2250), .Y(n5644) );
AOI21X1TS U7288 ( .A0(n5637), .A1(n5636), .B0(n5635), .Y(n5646) );
NAND2X1TS U7289 ( .A(FPMULT_Op_MX[8]), .B(DP_OP_501J1_127_1459_n910), .Y(
n5638) );
NAND2X1TS U7290 ( .A(n5639), .B(n5638), .Y(n5645) );
OA21XLTS U7291 ( .A0(n5644), .A1(n5646), .B0(n5645), .Y(intadd_1_B_0_) );
AOI21X1TS U7292 ( .A0(n5643), .A1(n5642), .B0(n5641), .Y(intadd_1_CI) );
NOR2BX1TS U7293 ( .AN(n5645), .B(n5644), .Y(n5647) );
XOR2X1TS U7294 ( .A(n5647), .B(n5646), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
NOR2BX2TS U7295 ( .AN(n5649), .B(n5648), .Y(n5687) );
INVX2TS U7296 ( .A(n5652), .Y(n5650) );
NAND2X1TS U7297 ( .A(n5650), .B(n5651), .Y(n5654) );
INVX2TS U7298 ( .A(n5651), .Y(n5653) );
XNOR2X1TS U7299 ( .A(n5657), .B(n5656), .Y(n5659) );
XOR2X1TS U7300 ( .A(n5659), .B(n5658), .Y(n5686) );
INVX2TS U7301 ( .A(n5688), .Y(n5661) );
INVX2TS U7302 ( .A(n5687), .Y(n5660) );
OAI22X1TS U7303 ( .A0(n5662), .A1(n5686), .B0(n5661), .B1(n5660), .Y(
intadd_2_A_6_) );
INVX2TS U7304 ( .A(n5664), .Y(n5668) );
INVX2TS U7305 ( .A(n5667), .Y(n5665) );
OAI21X1TS U7306 ( .A0(n5668), .A1(n5667), .B0(n5666), .Y(n5695) );
OAI21X1TS U7307 ( .A0(n5671), .A1(n5670), .B0(n5669), .Y(n5694) );
XNOR2X1TS U7308 ( .A(n5673), .B(n5672), .Y(n5674) );
ACHCINX2TS U7309 ( .CIN(n5695), .A(n5694), .B(n5696), .CO(intadd_2_A_4_) );
XOR2X1TS U7310 ( .A(n5677), .B(n5676), .Y(n5679) );
XNOR2X1TS U7311 ( .A(n5679), .B(n5678), .Y(intadd_2_A_1_) );
NOR2X1TS U7312 ( .A(n6688), .B(n5702), .Y(n5713) );
OAI31X1TS U7313 ( .A0(n5713), .A1(n6652), .A2(n6697), .B0(n5680), .Y(n5683)
);
NAND2X1TS U7314 ( .A(n5682), .B(n5707), .Y(n5703) );
NAND2X1TS U7315 ( .A(n5683), .B(n5703), .Y(intadd_2_A_0_) );
NOR2BX1TS U7316 ( .AN(n5685), .B(n5684), .Y(intadd_2_B_7_) );
XOR2X1TS U7317 ( .A(n5687), .B(n5686), .Y(n5689) );
XNOR2X1TS U7318 ( .A(n5689), .B(n5688), .Y(intadd_2_B_5_) );
XOR2X1TS U7319 ( .A(n5691), .B(n5690), .Y(n5693) );
XNOR2X1TS U7320 ( .A(n5693), .B(n5692), .Y(intadd_2_B_4_) );
XOR2X1TS U7321 ( .A(n5695), .B(n5694), .Y(n5697) );
XNOR2X1TS U7322 ( .A(n5697), .B(n5696), .Y(intadd_2_B_3_) );
XOR2X1TS U7323 ( .A(n5699), .B(n5698), .Y(n5701) );
XOR2X1TS U7324 ( .A(n5701), .B(n5700), .Y(intadd_2_B_2_) );
INVX2TS U7325 ( .A(n5703), .Y(n5704) );
AOI21X1TS U7326 ( .A0(n5707), .A1(n5705), .B0(n5704), .Y(intadd_2_B_1_) );
NAND2X1TS U7327 ( .A(n5705), .B(n7027), .Y(n5715) );
OAI21X1TS U7328 ( .A0(n6860), .A1(n5708), .B0(n5715), .Y(n5709) );
INVX2TS U7329 ( .A(n5705), .Y(n5706) );
XNOR2X1TS U7330 ( .A(n5707), .B(n5706), .Y(n5711) );
NOR2X1TS U7331 ( .A(n5715), .B(n5708), .Y(n5710) );
AOI21X1TS U7332 ( .A0(n5709), .A1(n5711), .B0(n5710), .Y(intadd_2_B_0_) );
XNOR2X1TS U7333 ( .A(n5712), .B(n5711), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
NOR2BX1TS U7334 ( .AN(n5715), .B(n5714), .Y(
FPMULT_inst_RecursiveKOA_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1) );
NAND2X1TS U7335 ( .A(FPMULT_Sgf_normalized_result[6]), .B(
FPMULT_Sgf_normalized_result[7]), .Y(n5717) );
NAND2X1TS U7336 ( .A(FPMULT_Sgf_normalized_result[3]), .B(
FPMULT_Sgf_normalized_result[2]), .Y(n5716) );
NAND2X1TS U7337 ( .A(FPMULT_Sgf_normalized_result[5]), .B(
FPMULT_Sgf_normalized_result[4]), .Y(n5757) );
NOR2X1TS U7338 ( .A(n6646), .B(n6689), .Y(n5749) );
NAND2X1TS U7339 ( .A(n5749), .B(FPMULT_Sgf_normalized_result[10]), .Y(n5720)
);
INVX2TS U7340 ( .A(n5742), .Y(n5739) );
AHHCINX2TS U7341 ( .A(FPMULT_Sgf_normalized_result[22]), .CIN(n5722), .S(
n5723), .CO(n5808) );
AHHCONX2TS U7342 ( .A(FPMULT_Sgf_normalized_result[21]), .CI(n5724), .CON(
n5722), .S(n5725) );
AHHCINX2TS U7343 ( .A(FPMULT_Sgf_normalized_result[20]), .CIN(n5726), .S(
n5727), .CO(n5724) );
AHHCONX2TS U7344 ( .A(FPMULT_Sgf_normalized_result[19]), .CI(n5728), .CON(
n5726), .S(n5729) );
AHHCINX2TS U7345 ( .A(FPMULT_Sgf_normalized_result[18]), .CIN(n5730), .S(
n5731), .CO(n5728) );
AHHCONX2TS U7346 ( .A(FPMULT_Sgf_normalized_result[17]), .CI(n5732), .CON(
n5730), .S(n5733) );
AHHCINX2TS U7347 ( .A(FPMULT_Sgf_normalized_result[16]), .CIN(n5734), .S(
n5735), .CO(n5732) );
AHHCONX2TS U7348 ( .A(FPMULT_Sgf_normalized_result[15]), .CI(n5736), .CON(
n5734), .S(n5737) );
AHHCINX2TS U7349 ( .A(FPMULT_Sgf_normalized_result[14]), .CIN(n5738), .S(
n5740), .CO(n5736) );
AHHCONX2TS U7350 ( .A(FPMULT_Sgf_normalized_result[13]), .CI(n5741), .CON(
n5738), .S(n5743) );
AHHCINX2TS U7351 ( .A(FPMULT_Sgf_normalized_result[12]), .CIN(n5744), .S(
n5745), .CO(n5741) );
AHHCONX2TS U7352 ( .A(FPMULT_Sgf_normalized_result[11]), .CI(n5746), .CON(
n5744), .S(n5747) );
INVX2TS U7353 ( .A(n5748), .Y(n5754) );
NAND2X1TS U7354 ( .A(n5754), .B(n5749), .Y(n5750) );
XOR2X1TS U7355 ( .A(n5750), .B(n6786), .Y(n5751) );
NAND2X1TS U7356 ( .A(n5754), .B(FPMULT_Sgf_normalized_result[8]), .Y(n5752)
);
XOR2X1TS U7357 ( .A(n5752), .B(n6689), .Y(n5753) );
XNOR2X1TS U7358 ( .A(n5754), .B(n6646), .Y(n5755) );
INVX2TS U7359 ( .A(n5756), .Y(n5776) );
OAI21X1TS U7360 ( .A0(n5776), .A1(n6691), .B0(n5757), .Y(n5760) );
NAND2X1TS U7361 ( .A(n5760), .B(FPMULT_Sgf_normalized_result[6]), .Y(n5758)
);
XOR2X1TS U7362 ( .A(n5758), .B(n6782), .Y(n5759) );
XNOR2X1TS U7363 ( .A(n5760), .B(n6730), .Y(n5761) );
NAND2X1TS U7364 ( .A(n5763), .B(n5762), .Y(n5764) );
XOR2X1TS U7365 ( .A(n5765), .B(n5764), .Y(n5766) );
NAND2X1TS U7366 ( .A(n5776), .B(n6731), .Y(n5767) );
XNOR2X1TS U7367 ( .A(n5767), .B(n6691), .Y(n5768) );
INVX2TS U7368 ( .A(n5769), .Y(n5784) );
AOI21X1TS U7369 ( .A0(n5784), .A1(n2239), .B0(n5770), .Y(n5774) );
NAND2X1TS U7370 ( .A(n5772), .B(n5771), .Y(n5773) );
XOR2X1TS U7371 ( .A(n5774), .B(n5773), .Y(n5775) );
XOR2X1TS U7372 ( .A(n5776), .B(FPMULT_Sgf_normalized_result[4]), .Y(n5778)
);
XOR2X1TS U7373 ( .A(n5780), .B(n6687), .Y(n5781) );
NAND2X1TS U7374 ( .A(n2239), .B(n5782), .Y(n5783) );
XNOR2X1TS U7375 ( .A(n5784), .B(n5783), .Y(n5785) );
INVX2TS U7376 ( .A(n5786), .Y(n5799) );
OAI21X1TS U7377 ( .A0(n5799), .A1(n5795), .B0(n5796), .Y(n5791) );
INVX2TS U7378 ( .A(n5787), .Y(n5789) );
NAND2X1TS U7379 ( .A(n5789), .B(n5788), .Y(n5790) );
XNOR2X1TS U7380 ( .A(n5791), .B(n5790), .Y(n5792) );
CLKMX2X2TS U7381 ( .A(n5792), .B(FPMULT_P_Sgf[25]), .S0(n6181), .Y(n1554) );
XOR2X1TS U7382 ( .A(n5793), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5794)
);
INVX2TS U7383 ( .A(n5795), .Y(n5797) );
NAND2X1TS U7384 ( .A(n5797), .B(n5796), .Y(n5798) );
XOR2X1TS U7385 ( .A(n5799), .B(n5798), .Y(n5800) );
XNOR2X1TS U7386 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5801) );
INVX2TS U7387 ( .A(n5802), .Y(n6180) );
AOI21X1TS U7388 ( .A0(n6180), .A1(n6177), .B0(n5803), .Y(n5806) );
NAND2X1TS U7389 ( .A(n2998), .B(n5804), .Y(n5805) );
XOR2X1TS U7390 ( .A(n5806), .B(n5805), .Y(n5807) );
ADDHXLTS U7391 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n5808), .CO(n5810),
.S(n5721) );
AOI21X1TS U7392 ( .A0(ack_operation), .A1(n4808), .B0(n6214), .Y(n6436) );
AOI211X1TS U7393 ( .A0(FPMULT_zero_flag), .A1(n2320), .B0(n5812), .C0(n6436),
.Y(n5815) );
NAND2X1TS U7394 ( .A(n6470), .B(n6736), .Y(n1689) );
INVX2TS U7395 ( .A(n4230), .Y(n5818) );
INVX2TS U7396 ( .A(n4230), .Y(n6471) );
MX2X1TS U7397 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1443) );
BUFX3TS U7398 ( .A(n5821), .Y(n5883) );
OAI2BB2XLTS U7399 ( .B0(n5866), .B1(n6637), .A0N(FPADDSUB_Data_array_SWR[12]), .A1N(n2321), .Y(n5822) );
OAI22X1TS U7400 ( .A0(n5865), .A1(n5855), .B0(n5864), .B1(n5824), .Y(n6497)
);
OA22X1TS U7401 ( .A0(n6497), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n1185) );
INVX2TS U7402 ( .A(n5825), .Y(n6524) );
MXI2X1TS U7403 ( .A(n6510), .B(n6778), .S0(n6487), .Y(n1186) );
OA22X1TS U7404 ( .A0(n6494), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n1188) );
OA22X1TS U7405 ( .A0(n6523), .A1(n5834), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n1189) );
AOI21X1TS U7406 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n2345), .B0(n5850),
.Y(n5836) );
AOI22X1TS U7407 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n2343), .Y(n5835) );
OAI211X1TS U7408 ( .A0(n6729), .A1(n5842), .B0(n5836), .C0(n5835), .Y(n5856)
);
NOR2BX1TS U7409 ( .AN(n5837), .B(n5850), .Y(n5844) );
AOI22X1TS U7410 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2343), .B0(
FPADDSUB_Data_array_SWR[22]), .B1(n2322), .Y(n5838) );
OAI211X1TS U7411 ( .A0(n6714), .A1(n5839), .B0(n5844), .C0(n5838), .Y(n5857)
);
AOI22X1TS U7412 ( .A0(n2383), .A1(n5856), .B0(n5857), .B1(n2351), .Y(n6512)
);
MXI2X1TS U7413 ( .A(n6512), .B(n6779), .S0(n6487), .Y(n1190) );
AOI21X1TS U7414 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2343), .B0(n5850),
.Y(n5841) );
AOI22X1TS U7415 ( .A0(n2362), .A1(n2345), .B0(FPADDSUB_Data_array_SWR[22]),
.B1(n2328), .Y(n5840) );
OAI211X1TS U7416 ( .A0(n6716), .A1(n5842), .B0(n5841), .C0(n5840), .Y(n5853)
);
AOI22X1TS U7417 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2322), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n2345), .Y(n5843) );
OAI211X1TS U7418 ( .A0(n6729), .A1(n5845), .B0(n5844), .C0(n5843), .Y(n5854)
);
AOI22X1TS U7419 ( .A0(n2383), .A1(n5853), .B0(n5854), .B1(n5855), .Y(n6529)
);
MXI2X1TS U7420 ( .A(n6529), .B(n6783), .S0(n6487), .Y(n1191) );
AOI22X1TS U7421 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2322), .B0(
FPADDSUB_Data_array_SWR[23]), .B1(n2328), .Y(n5847) );
AOI22X1TS U7422 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2343), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2345), .Y(n5846) );
AOI22X1TS U7423 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2322), .B0(
FPADDSUB_Data_array_SWR[24]), .B1(n2328), .Y(n5849) );
AOI22X1TS U7424 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2343), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2345), .Y(n5848) );
AOI221X1TS U7425 ( .A0(n2383), .A1(n5851), .B0(n2267), .B1(n5852), .C0(n5850), .Y(n6521) );
MXI2X1TS U7426 ( .A(n6521), .B(n6780), .S0(n6487), .Y(n1192) );
AOI221X1TS U7427 ( .A0(n2383), .A1(n5852), .B0(n5855), .B1(n5851), .C0(n5850), .Y(n6527) );
MXI2X1TS U7428 ( .A(n6527), .B(n6781), .S0(n6487), .Y(n1193) );
AOI22X1TS U7429 ( .A0(n2383), .A1(n5854), .B0(n5853), .B1(n5855), .Y(n6600)
);
MXI2X1TS U7430 ( .A(n6600), .B(n6784), .S0(n6487), .Y(n1194) );
AOI22X1TS U7431 ( .A0(n2383), .A1(n5857), .B0(n5856), .B1(n5855), .Y(n6519)
);
MXI2X1TS U7432 ( .A(n6519), .B(n6777), .S0(n6487), .Y(n1195) );
OAI22X1TS U7433 ( .A0(n5861), .A1(n5874), .B0(n5876), .B1(n5860), .Y(n6602)
);
OA22X1TS U7434 ( .A0(n6602), .A1(n5872), .B0(n5862), .B1(
FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1198) );
OAI22X1TS U7435 ( .A0(n5865), .A1(n5874), .B0(n5876), .B1(n5864), .Y(n6585)
);
OA22X1TS U7436 ( .A0(n6585), .A1(n5872), .B0(n5878), .B1(
FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1200) );
OAI22X1TS U7437 ( .A0(n5867), .A1(n5874), .B0(n5866), .B1(n5876), .Y(n6588)
);
OA22X1TS U7438 ( .A0(n6588), .A1(n5872), .B0(n5878), .B1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1201) );
OAI22X1TS U7439 ( .A0(n5869), .A1(n5874), .B0(n5876), .B1(n5868), .Y(n6596)
);
OA22X1TS U7440 ( .A0(n6596), .A1(n5872), .B0(n5878), .B1(
FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n1202) );
OAI22X1TS U7441 ( .A0(n5871), .A1(n5874), .B0(n5876), .B1(n5870), .Y(n6593)
);
OA22X1TS U7442 ( .A0(n6593), .A1(n5872), .B0(n5878), .B1(
FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n1203) );
OA22X1TS U7443 ( .A0(n5880), .A1(n5879), .B0(n5878), .B1(
FPADDSUB_DmP_mant_SFG_SWR[1]), .Y(n1204) );
OAI32X4TS U7444 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n5881), .B1(n6724),
.Y(n6218) );
MXI2X1TS U7445 ( .A(n5882), .B(n6101), .S0(n6218), .Y(n2144) );
OA21XLTS U7446 ( .A0(n5885), .A1(FPADDSUB_LZD_output_NRM2_EW[1]), .B0(n5884),
.Y(n1409) );
OAI22X1TS U7447 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n5891), .B0(n5890),
.B1(n6785), .Y(n1586) );
OA22X1TS U7448 ( .A0(n6489), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(n5892),
.B1(result_add_subt[29]), .Y(n1467) );
OA22X1TS U7449 ( .A0(n6489), .A1(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B0(n5892),
.B1(result_add_subt[28]), .Y(n1468) );
OA22X1TS U7450 ( .A0(n6489), .A1(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B0(n5892),
.B1(result_add_subt[27]), .Y(n1469) );
OA22X1TS U7451 ( .A0(n6489), .A1(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B0(n5892),
.B1(result_add_subt[26]), .Y(n1470) );
OA22X1TS U7452 ( .A0(n6489), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(n5892),
.B1(result_add_subt[25]), .Y(n1471) );
NOR4X1TS U7453 ( .A(n6478), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n5893) );
BUFX3TS U7454 ( .A(n5894), .Y(n6007) );
AOI21X1TS U7455 ( .A0(n5913), .A1(n5896), .B0(n5895), .Y(n6093) );
INVX2TS U7456 ( .A(n5897), .Y(n5899) );
NAND2X1TS U7457 ( .A(n5899), .B(n5898), .Y(n5904) );
INVX2TS U7458 ( .A(n5904), .Y(n5900) );
INVX2TS U7459 ( .A(n5902), .Y(n5915) );
INVX2TS U7460 ( .A(n5914), .Y(n5903) );
AOI21X1TS U7461 ( .A0(n6069), .A1(n5915), .B0(n5903), .Y(n5905) );
XOR2X1TS U7462 ( .A(n5905), .B(n5904), .Y(n5906) );
AOI22X1TS U7463 ( .A0(n5906), .A1(n4565), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n6101), .Y(n5907) );
OAI2BB1X1TS U7464 ( .A0N(n6007), .A1N(n5908), .B0(n5907), .Y(n1342) );
INVX2TS U7465 ( .A(n5909), .Y(n5912) );
INVX2TS U7466 ( .A(n5910), .Y(n5911) );
AOI21X1TS U7467 ( .A0(n5913), .A1(n5912), .B0(n5911), .Y(n5917) );
NAND2X1TS U7468 ( .A(n5915), .B(n5914), .Y(n5918) );
INVX2TS U7469 ( .A(n5918), .Y(n5916) );
XNOR2X1TS U7470 ( .A(n6069), .B(n5918), .Y(n5919) );
BUFX3TS U7471 ( .A(n6484), .Y(n6488) );
AOI22X1TS U7472 ( .A0(n5919), .A1(n4565), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n6488), .Y(n5920) );
OAI2BB1X1TS U7473 ( .A0N(n6007), .A1N(n5921), .B0(n5920), .Y(n1343) );
INVX2TS U7474 ( .A(n5922), .Y(n6077) );
NAND2X1TS U7475 ( .A(n5925), .B(n5951), .Y(n5929) );
INVX2TS U7476 ( .A(n5929), .Y(n5926) );
XNOR2X1TS U7477 ( .A(n5927), .B(n5926), .Y(n5932) );
INVX2TS U7478 ( .A(n5928), .Y(n6085) );
XOR2X1TS U7479 ( .A(n6085), .B(n5929), .Y(n5930) );
AOI22X1TS U7480 ( .A0(n5930), .A1(n4565), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n6488), .Y(n5931) );
OAI2BB1X1TS U7481 ( .A0N(n6007), .A1N(n5932), .B0(n5931), .Y(n1339) );
NAND2X1TS U7482 ( .A(n5935), .B(n5934), .Y(n5938) );
INVX2TS U7483 ( .A(n5938), .Y(n5936) );
XOR2X1TS U7484 ( .A(n5939), .B(n5938), .Y(n5940) );
AOI22X1TS U7485 ( .A0(n5940), .A1(n4565), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n6488), .Y(n5941) );
OAI2BB1X1TS U7486 ( .A0N(n6007), .A1N(n5942), .B0(n5941), .Y(n1336) );
INVX2TS U7487 ( .A(n5943), .Y(n5946) );
INVX2TS U7488 ( .A(n5944), .Y(n5945) );
NAND2X1TS U7489 ( .A(n5948), .B(n5947), .Y(n5953) );
INVX2TS U7490 ( .A(n5953), .Y(n5949) );
XNOR2X1TS U7491 ( .A(n5950), .B(n5949), .Y(n5957) );
XNOR2X1TS U7492 ( .A(n5954), .B(n5953), .Y(n5955) );
AOI22X1TS U7493 ( .A0(n5955), .A1(n4565), .B0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.B1(n6488), .Y(n5956) );
OAI2BB1X1TS U7494 ( .A0N(n6007), .A1N(n5957), .B0(n5956), .Y(n1338) );
NAND2X1TS U7495 ( .A(n5959), .B(n5958), .Y(n5962) );
INVX2TS U7496 ( .A(n5962), .Y(n5960) );
XNOR2X1TS U7497 ( .A(n5961), .B(n5960), .Y(n5966) );
XNOR2X1TS U7498 ( .A(n5963), .B(n5962), .Y(n5964) );
AOI22X1TS U7499 ( .A0(n5964), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n6488), .Y(n5965) );
OAI2BB1X1TS U7500 ( .A0N(n6007), .A1N(n5966), .B0(n5965), .Y(n1333) );
NAND2X1TS U7501 ( .A(n5969), .B(n5968), .Y(n5972) );
INVX2TS U7502 ( .A(n5972), .Y(n5970) );
XOR2X1TS U7503 ( .A(n5973), .B(n5972), .Y(n5974) );
AOI22X1TS U7504 ( .A0(n5974), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n2325), .Y(n5975) );
OAI2BB1X1TS U7505 ( .A0N(n6007), .A1N(n5976), .B0(n5975), .Y(n1334) );
INVX2TS U7506 ( .A(n5977), .Y(n5979) );
NAND2X1TS U7507 ( .A(n5979), .B(n5978), .Y(n5982) );
INVX2TS U7508 ( .A(n5982), .Y(n5980) );
XOR2X1TS U7509 ( .A(n5983), .B(n5982), .Y(n5984) );
AOI22X1TS U7510 ( .A0(n5984), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n6488), .Y(n5985) );
OAI2BB1X1TS U7511 ( .A0N(n6007), .A1N(n5986), .B0(n5985), .Y(n1332) );
INVX2TS U7512 ( .A(n5987), .Y(n5989) );
NAND2X1TS U7513 ( .A(n5989), .B(n5988), .Y(n5992) );
INVX2TS U7514 ( .A(n5992), .Y(n5990) );
XOR2X1TS U7515 ( .A(n5993), .B(n5992), .Y(n5994) );
AOI22X1TS U7516 ( .A0(n5994), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n6488), .Y(n5995) );
OAI2BB1X1TS U7517 ( .A0N(n6007), .A1N(n5996), .B0(n5995), .Y(n1321) );
INVX2TS U7518 ( .A(n5997), .Y(n5999) );
NAND2X1TS U7519 ( .A(n5999), .B(n5998), .Y(n6002) );
INVX2TS U7520 ( .A(n6002), .Y(n6000) );
XOR2X1TS U7521 ( .A(n6003), .B(n6002), .Y(n6004) );
AOI22X1TS U7522 ( .A0(n6004), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n2325), .Y(n6005) );
OAI2BB1X1TS U7523 ( .A0N(n6007), .A1N(n6006), .B0(n6005), .Y(n1319) );
NAND2X1TS U7524 ( .A(n6009), .B(n6008), .Y(n6012) );
INVX2TS U7525 ( .A(n6012), .Y(n6010) );
XNOR2X1TS U7526 ( .A(n6011), .B(n6010), .Y(n6016) );
XNOR2X1TS U7527 ( .A(n6013), .B(n6012), .Y(n6014) );
AOI22X1TS U7528 ( .A0(n6014), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n2325), .Y(n6015) );
OAI2BB1X1TS U7529 ( .A0N(n6106), .A1N(n6016), .B0(n6015), .Y(n1320) );
OR2X1TS U7530 ( .A(n6734), .B(FPADDSUB_DMP_SFG[22]), .Y(n6018) );
CLKAND2X2TS U7531 ( .A(n6734), .B(FPADDSUB_DMP_SFG[22]), .Y(n6017) );
XOR2X1TS U7532 ( .A(n6020), .B(n6787), .Y(n6024) );
XOR2X1TS U7533 ( .A(n6021), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n6022) );
AOI22X1TS U7534 ( .A0(n6022), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n2325), .Y(n6023) );
OAI2BB1X1TS U7535 ( .A0N(n6106), .A1N(n6024), .B0(n6023), .Y(n1410) );
NAND2X1TS U7536 ( .A(n6026), .B(n6025), .Y(n6029) );
INVX2TS U7537 ( .A(n6029), .Y(n6027) );
XNOR2X1TS U7538 ( .A(n6028), .B(n6027), .Y(n6034) );
XNOR2X1TS U7539 ( .A(n6030), .B(n6029), .Y(n6032) );
AOI22X1TS U7540 ( .A0(n6032), .A1(n6031), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n2325), .Y(n6033) );
OAI2BB1X1TS U7541 ( .A0N(n6106), .A1N(n6034), .B0(n6033), .Y(n1317) );
INVX2TS U7542 ( .A(n6035), .Y(n6037) );
NAND2X1TS U7543 ( .A(n6037), .B(n6036), .Y(n6040) );
INVX2TS U7544 ( .A(n6040), .Y(n6038) );
XOR2X1TS U7545 ( .A(n6041), .B(n6040), .Y(n6042) );
AOI22X1TS U7546 ( .A0(n6042), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n2325), .Y(n6043) );
OAI2BB1X1TS U7547 ( .A0N(n6106), .A1N(n6044), .B0(n6043), .Y(n1316) );
NAND2X1TS U7548 ( .A(n6046), .B(n6045), .Y(n6049) );
INVX2TS U7549 ( .A(n6049), .Y(n6047) );
XNOR2X1TS U7550 ( .A(n6048), .B(n6047), .Y(n6053) );
XNOR2X1TS U7551 ( .A(n6050), .B(n6049), .Y(n6051) );
AOI22X1TS U7552 ( .A0(n6051), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n6484), .Y(n6052) );
OAI2BB1X1TS U7553 ( .A0N(n6106), .A1N(n6053), .B0(n6052), .Y(n1331) );
NAND2X1TS U7554 ( .A(n6055), .B(n6054), .Y(n6058) );
INVX2TS U7555 ( .A(n6058), .Y(n6056) );
XNOR2X1TS U7556 ( .A(n6057), .B(n6056), .Y(n6062) );
XNOR2X1TS U7557 ( .A(n6059), .B(n6058), .Y(n6060) );
AOI22X1TS U7558 ( .A0(n6060), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n6484), .Y(n6061) );
OAI2BB1X1TS U7559 ( .A0N(n6106), .A1N(n6062), .B0(n6061), .Y(n1335) );
INVX2TS U7560 ( .A(n6063), .Y(n6065) );
NAND2X1TS U7561 ( .A(n6065), .B(n6064), .Y(n6070) );
INVX2TS U7562 ( .A(n6070), .Y(n6066) );
AOI21X1TS U7563 ( .A0(n6069), .A1(n6068), .B0(n6067), .Y(n6100) );
XNOR2X1TS U7564 ( .A(n6071), .B(n6070), .Y(n6072) );
AOI22X1TS U7565 ( .A0(n6072), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n2325), .Y(n6073) );
OAI2BB1X1TS U7566 ( .A0N(n6106), .A1N(n6074), .B0(n6073), .Y(n1340) );
NAND2X1TS U7567 ( .A(n6080), .B(n6079), .Y(n6086) );
INVX2TS U7568 ( .A(n6086), .Y(n6081) );
XNOR2X1TS U7569 ( .A(n6082), .B(n6081), .Y(n6090) );
XNOR2X1TS U7570 ( .A(n6087), .B(n6086), .Y(n6088) );
AOI22X1TS U7571 ( .A0(n6088), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n6101), .Y(n6089) );
OAI2BB1X1TS U7572 ( .A0N(n6106), .A1N(n6090), .B0(n6089), .Y(n1337) );
INVX2TS U7573 ( .A(n6094), .Y(n6096) );
NAND2X1TS U7574 ( .A(n6096), .B(n6095), .Y(n6099) );
INVX2TS U7575 ( .A(n6099), .Y(n6097) );
XNOR2X1TS U7576 ( .A(n6098), .B(n6097), .Y(n6105) );
XOR2X1TS U7577 ( .A(n6100), .B(n6099), .Y(n6103) );
AOI22X1TS U7578 ( .A0(n6103), .A1(n6102), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n6101), .Y(n6104) );
OAI2BB1X1TS U7579 ( .A0N(n6106), .A1N(n6105), .B0(n6104), .Y(n1341) );
NAND2X1TS U7580 ( .A(n2437), .B(n6107), .Y(n6109) );
XNOR2X1TS U7581 ( .A(n6109), .B(n6108), .Y(n6110) );
INVX2TS U7582 ( .A(n6111), .Y(n6156) );
INVX2TS U7583 ( .A(n6112), .Y(n6147) );
NAND2X1TS U7584 ( .A(n6147), .B(n6145), .Y(n6113) );
XNOR2X1TS U7585 ( .A(n6156), .B(n6113), .Y(n6114) );
INVX2TS U7586 ( .A(n6115), .Y(n6121) );
INVX2TS U7587 ( .A(n6120), .Y(n6116) );
NAND2X1TS U7588 ( .A(n6116), .B(n6119), .Y(n6117) );
XOR2X1TS U7589 ( .A(n6121), .B(n6117), .Y(n6118) );
INVX2TS U7590 ( .A(n6122), .Y(n6124) );
NAND2X1TS U7591 ( .A(n6124), .B(n6123), .Y(n6125) );
XNOR2X1TS U7592 ( .A(n6126), .B(n6125), .Y(n6127) );
INVX2TS U7593 ( .A(n6130), .Y(n6132) );
NAND2X1TS U7594 ( .A(n6132), .B(n6131), .Y(n6133) );
XOR2X1TS U7595 ( .A(n6134), .B(n6133), .Y(n6135) );
OR2X1TS U7596 ( .A(n6137), .B(n6136), .Y(n6139) );
INVX2TS U7597 ( .A(n6145), .Y(n6146) );
AOI21X1TS U7598 ( .A0(n6156), .A1(n6147), .B0(n6146), .Y(n6152) );
INVX2TS U7599 ( .A(n6148), .Y(n6150) );
NAND2X1TS U7600 ( .A(n6150), .B(n6149), .Y(n6151) );
XOR2X1TS U7601 ( .A(n6152), .B(n6151), .Y(n6153) );
AOI21X1TS U7602 ( .A0(n6156), .A1(n6155), .B0(n6154), .Y(n6159) );
NAND2X1TS U7603 ( .A(n2233), .B(n6157), .Y(n6158) );
XOR2X1TS U7604 ( .A(n6159), .B(n6158), .Y(n6160) );
INVX2TS U7605 ( .A(n6161), .Y(n6167) );
INVX2TS U7606 ( .A(n6166), .Y(n6162) );
NAND2X1TS U7607 ( .A(n6162), .B(n6165), .Y(n6163) );
XOR2X1TS U7608 ( .A(n6167), .B(n6163), .Y(n6164) );
INVX2TS U7609 ( .A(n6168), .Y(n6170) );
NAND2X1TS U7610 ( .A(n6170), .B(n6169), .Y(n6171) );
XNOR2X1TS U7611 ( .A(n6172), .B(n6171), .Y(n6174) );
NAND2X1TS U7612 ( .A(n6178), .B(n6177), .Y(n6179) );
XNOR2X1TS U7613 ( .A(n6180), .B(n6179), .Y(n6182) );
NOR4X1TS U7614 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n6189) );
NOR4X1TS U7615 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n6188) );
NOR4X1TS U7616 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n6186) );
NOR4X1TS U7617 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n6184) );
NOR4X1TS U7618 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n6183) );
AND4X1TS U7619 ( .A(n6186), .B(n6185), .C(n6184), .D(n6183), .Y(n6187) );
NOR4X1TS U7620 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n6193) );
NAND4XLTS U7621 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6191) );
NAND4XLTS U7622 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6190) );
OR3X1TS U7623 ( .A(n7031), .B(n6191), .C(n6190), .Y(n6195) );
NOR3X1TS U7624 ( .A(dataB[25]), .B(dataB[31]), .C(n6195), .Y(n6192) );
NOR4X1TS U7625 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6198) );
NOR4X1TS U7626 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6197) );
NOR4BX1TS U7627 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n7031), .Y(n6196) );
NOR2X1TS U7628 ( .A(operation_reg[1]), .B(n6195), .Y(n6203) );
NAND4XLTS U7629 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n6199) );
OAI31X1TS U7630 ( .A0(n6201), .A1(n6200), .A2(n6199), .B0(dataB[27]), .Y(
n6202) );
OAI2BB2XLTS U7631 ( .B0(n6205), .B1(n6204), .A0N(n6203), .A1N(
operation_reg[0]), .Y(NaN_reg) );
INVX2TS U7632 ( .A(n6218), .Y(n6220) );
OAI22X1TS U7633 ( .A0(n6256), .A1(n6209), .B0(n6208), .B1(n6207), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
OR2X1TS U7634 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n6210) );
AO22XLTS U7635 ( .A0(operation[2]), .A1(n6210), .B0(n6211), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U7636 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n6211),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
OAI222X1TS U7637 ( .A0(n4687), .A1(n6216), .B0(n6717), .B1(n6215), .C0(n4631), .C1(n6214), .Y(operation_ready) );
BUFX3TS U7638 ( .A(n6592), .Y(n6616) );
AOI22X1TS U7639 ( .A0(n6220), .A1(n6217), .B0(n6616), .B1(n6218), .Y(n2147)
);
AOI22X1TS U7640 ( .A0(n6220), .A1(n6616), .B0(n6618), .B1(n6218), .Y(n2146)
);
OAI2BB2XLTS U7641 ( .B0(n6218), .B1(n6618), .A0N(n6218), .A1N(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2145) );
AOI22X1TS U7642 ( .A0(n6220), .A1(n6488), .B0(n6657), .B1(n6218), .Y(n2143)
);
AOI22X1TS U7643 ( .A0(n6220), .A1(n6657), .B0(n6219), .B1(n6218), .Y(n2142)
);
NAND2X1TS U7644 ( .A(n6270), .B(n6223), .Y(n6221) );
OA21XLTS U7645 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n6223), .B0(n6221), .Y(
n2141) );
AOI22X1TS U7646 ( .A0(n6247), .A1(n6223), .B0(n6663), .B1(n6221), .Y(n2140)
);
NAND2X1TS U7647 ( .A(n6223), .B(n6247), .Y(n6222) );
AOI22X1TS U7648 ( .A0(n6224), .A1(n6223), .B0(n6682), .B1(n6222), .Y(n2139)
);
OAI2BB2XLTS U7649 ( .B0(n6254), .B1(n6428), .A0N(n6226), .A1N(region_flag[0]), .Y(n2135) );
OAI2BB2XLTS U7650 ( .B0(n6254), .B1(n2268), .A0N(n6226), .A1N(region_flag[1]), .Y(n2134) );
AOI22X1TS U7651 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n6321), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n6231), .Y(n6228) );
NAND2X1TS U7652 ( .A(n6228), .B(n6227), .Y(n2131) );
AOI21X1TS U7653 ( .A0(n6230), .A1(n6229), .B0(n6663), .Y(n6235) );
NOR2X1TS U7654 ( .A(n6235), .B(n6231), .Y(n6234) );
OAI2BB2XLTS U7655 ( .B0(n6232), .B1(n6234), .A0N(FPSENCOS_d_ff3_LUT_out[5]),
.A1N(n6272), .Y(n2128) );
INVX2TS U7656 ( .A(n6278), .Y(n6338) );
OAI2BB1X1TS U7657 ( .A0N(FPSENCOS_d_ff3_LUT_out[9]), .A1N(n6240), .B0(n6234),
.Y(n2124) );
AOI21X1TS U7658 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n6321), .B0(n6235),
.Y(n6236) );
NAND2X1TS U7659 ( .A(n6237), .B(n6236), .Y(n2122) );
OAI2BB1X1TS U7660 ( .A0N(FPSENCOS_d_ff3_LUT_out[13]), .A1N(n6240), .B0(n6238), .Y(n2121) );
OAI2BB1X1TS U7661 ( .A0N(FPSENCOS_d_ff3_LUT_out[15]), .A1N(n6240), .B0(n6239), .Y(n2120) );
OAI2BB1X1TS U7662 ( .A0N(FPSENCOS_d_ff3_LUT_out[19]), .A1N(n6338), .B0(n6241), .Y(n2119) );
OAI21X1TS U7663 ( .A0(n2230), .A1(n6682), .B0(n6270), .Y(n6243) );
INVX2TS U7664 ( .A(n6278), .Y(n6306) );
AOI22X1TS U7665 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n4529), .B0(n6244),
.B1(n6243), .Y(n6245) );
OAI2BB1X1TS U7666 ( .A0N(n6249), .A1N(n6247), .B0(n6245), .Y(n2116) );
OAI21XLTS U7667 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n6247), .B0(n6246),
.Y(n6248) );
BUFX3TS U7668 ( .A(n6250), .Y(n6252) );
INVX2TS U7669 ( .A(n6256), .Y(n6410) );
OAI2BB2XLTS U7670 ( .B0(n6257), .B1(n6595), .A0N(n6410), .A1N(
FPSENCOS_d_ff_Zn[0]), .Y(n2074) );
BUFX3TS U7671 ( .A(n6414), .Y(n6260) );
OAI2BB2XLTS U7672 ( .B0(n6260), .B1(n6595), .A0N(n6414), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2073) );
BUFX3TS U7673 ( .A(n6416), .Y(n6261) );
OAI2BB2XLTS U7674 ( .B0(n6261), .B1(n6595), .A0N(n6416), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n2072) );
OAI2BB2XLTS U7675 ( .B0(n6411), .B1(n6598), .A0N(n6410), .A1N(
FPSENCOS_d_ff_Zn[1]), .Y(n2071) );
BUFX3TS U7676 ( .A(n6414), .Y(n6258) );
OAI2BB2XLTS U7677 ( .B0(n6258), .B1(n6598), .A0N(n6414), .A1N(
FPSENCOS_d_ff_Yn[1]), .Y(n2070) );
BUFX3TS U7678 ( .A(n6416), .Y(n6259) );
OAI2BB2XLTS U7679 ( .B0(n6259), .B1(n6598), .A0N(n6416), .A1N(
FPSENCOS_d_ff_Xn[1]), .Y(n2069) );
BUFX3TS U7680 ( .A(n6414), .Y(n6404) );
OAI2BB2XLTS U7681 ( .B0(n6260), .B1(n6590), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2067) );
BUFX3TS U7682 ( .A(n6416), .Y(n6408) );
OAI2BB2XLTS U7683 ( .B0(n6261), .B1(n6590), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[2]), .Y(n2066) );
OAI2BB2XLTS U7684 ( .B0(n6258), .B1(n6587), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2064) );
OAI2BB2XLTS U7685 ( .B0(n6259), .B1(n6587), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[3]), .Y(n2063) );
OAI2BB2XLTS U7686 ( .B0(n6411), .B1(n2269), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[4]), .Y(n2062) );
OAI2BB2XLTS U7687 ( .B0(n6258), .B1(n2269), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2061) );
OAI2BB2XLTS U7688 ( .B0(n6259), .B1(n2269), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[4]), .Y(n2060) );
BUFX3TS U7689 ( .A(n6414), .Y(n6296) );
OAI2BB2XLTS U7690 ( .B0(n6258), .B1(n6605), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2058) );
BUFX3TS U7691 ( .A(n6416), .Y(n6397) );
OAI2BB2XLTS U7692 ( .B0(n6259), .B1(n6605), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[5]), .Y(n2057) );
OAI2BB2XLTS U7693 ( .B0(n6411), .B1(n2270), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[6]), .Y(n2056) );
OAI2BB2XLTS U7694 ( .B0(n6258), .B1(n2270), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2055) );
OAI2BB2XLTS U7695 ( .B0(n6259), .B1(n2270), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[6]), .Y(n2054) );
OAI2BB2XLTS U7696 ( .B0(n6411), .B1(n2271), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[7]), .Y(n2053) );
OAI2BB2XLTS U7697 ( .B0(n6258), .B1(n2271), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2052) );
OAI2BB2XLTS U7698 ( .B0(n6259), .B1(n2271), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[7]), .Y(n2051) );
OAI2BB2XLTS U7699 ( .B0(n6258), .B1(n6520), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2049) );
OAI2BB2XLTS U7700 ( .B0(n6259), .B1(n6520), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n2048) );
OAI2BB2XLTS U7701 ( .B0(n6258), .B1(n6601), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2046) );
OAI2BB2XLTS U7702 ( .B0(n6259), .B1(n6601), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n2045) );
OAI2BB2XLTS U7703 ( .B0(n6258), .B1(n6528), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2043) );
OAI2BB2XLTS U7704 ( .B0(n6259), .B1(n6528), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[10]), .Y(n2042) );
BUFX3TS U7705 ( .A(n6414), .Y(n6415) );
OAI2BB2XLTS U7706 ( .B0(n6415), .B1(n6522), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2040) );
BUFX3TS U7707 ( .A(n6416), .Y(n6425) );
OAI2BB2XLTS U7708 ( .B0(n6425), .B1(n6522), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n2039) );
OAI2BB2XLTS U7709 ( .B0(n6415), .B1(n6530), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2037) );
OAI2BB2XLTS U7710 ( .B0(n6425), .B1(n6530), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[12]), .Y(n2036) );
OAI2BB2XLTS U7711 ( .B0(n6415), .B1(n6513), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[13]), .Y(n2034) );
OAI2BB2XLTS U7712 ( .B0(n6425), .B1(n6513), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[13]), .Y(n2033) );
OAI2BB2XLTS U7713 ( .B0(n6415), .B1(n6526), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[14]), .Y(n2031) );
OAI2BB2XLTS U7714 ( .B0(n6425), .B1(n6526), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[14]), .Y(n2030) );
OAI2BB2XLTS U7715 ( .B0(n6258), .B1(n6496), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2028) );
OAI2BB2XLTS U7716 ( .B0(n6259), .B1(n6496), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n2027) );
OAI2BB2XLTS U7717 ( .B0(n6415), .B1(n6516), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2025) );
OAI2BB2XLTS U7718 ( .B0(n6425), .B1(n6516), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[16]), .Y(n2024) );
OAI2BB2XLTS U7719 ( .B0(n6415), .B1(n6511), .A0N(n6260), .A1N(
FPSENCOS_d_ff_Yn[17]), .Y(n2022) );
OAI2BB2XLTS U7720 ( .B0(n6425), .B1(n6511), .A0N(n6261), .A1N(
FPSENCOS_d_ff_Xn[17]), .Y(n2021) );
OAI2BB2XLTS U7721 ( .B0(n6415), .B1(n6499), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2019) );
OAI2BB2XLTS U7722 ( .B0(n6425), .B1(n6499), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n2018) );
OAI2BB2XLTS U7723 ( .B0(n6415), .B1(n6506), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[19]), .Y(n2016) );
OAI2BB2XLTS U7724 ( .B0(n6425), .B1(n6506), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[19]), .Y(n2015) );
OAI2BB2XLTS U7725 ( .B0(n6415), .B1(n6509), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[20]), .Y(n2013) );
OAI2BB2XLTS U7726 ( .B0(n6425), .B1(n6509), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[20]), .Y(n2012) );
BUFX3TS U7727 ( .A(n6414), .Y(n6407) );
OAI2BB2XLTS U7728 ( .B0(n6407), .B1(n6503), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2010) );
BUFX3TS U7729 ( .A(n6416), .Y(n6418) );
OAI2BB2XLTS U7730 ( .B0(n6418), .B1(n6503), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n2009) );
OAI2BB2XLTS U7731 ( .B0(n6406), .B1(n6493), .A0N(n6262), .A1N(
FPSENCOS_d_ff_Zn[22]), .Y(n2008) );
OAI2BB2XLTS U7732 ( .B0(n6407), .B1(n6493), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2007) );
OAI2BB2XLTS U7733 ( .B0(n6418), .B1(n6493), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n2006) );
INVX2TS U7734 ( .A(n6337), .Y(n6265) );
INVX2TS U7735 ( .A(n6300), .Y(n6263) );
OAI2BB2XLTS U7736 ( .B0(n6335), .B1(n2408), .A0N(n6330), .A1N(
FPSENCOS_d_ff2_X[4]), .Y(n1996) );
OAI2BB2XLTS U7737 ( .B0(n6332), .B1(n2402), .A0N(n6330), .A1N(
FPSENCOS_d_ff2_X[8]), .Y(n1988) );
OAI2BB2XLTS U7738 ( .B0(n6335), .B1(n2423), .A0N(n6330), .A1N(
FPSENCOS_d_ff2_X[9]), .Y(n1986) );
OAI2BB2XLTS U7739 ( .B0(n6332), .B1(n2397), .A0N(n6330), .A1N(
FPSENCOS_d_ff2_X[12]), .Y(n1980) );
OA22X1TS U7740 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n4936), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n6337), .Y(n1971) );
AO22X1TS U7741 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n6265), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n6336), .Y(n1969) );
OA22X1TS U7742 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n6268), .Y(n1965) );
OAI2BB2XLTS U7743 ( .B0(n6332), .B1(n2416), .A0N(n6330), .A1N(
FPSENCOS_d_ff2_X[21]), .Y(n1962) );
OA22X1TS U7744 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n6268), .Y(n1958) );
OA22X1TS U7745 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n6268), .Y(n1957) );
OA22X1TS U7746 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n6268), .Y(n1956) );
OA22X1TS U7747 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n4936), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n6268), .Y(n1955) );
OA22X1TS U7748 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n6267), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n4612), .Y(n1953) );
NAND2X1TS U7749 ( .A(FPSENCOS_d_ff2_X[23]), .B(n6271), .Y(n6274) );
AOI32X1TS U7750 ( .A0(intadd_6_CI), .A1(n6275), .A2(n6274), .B0(n6273), .B1(
n6272), .Y(n1951) );
AOI21X1TS U7751 ( .A0(intadd_6_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n6276),
.Y(n6277) );
AOI21X1TS U7752 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n6280), .B0(n6279), .Y(
n6281) );
AOI22X1TS U7753 ( .A0(Data_1[10]), .A1(n6287), .B0(n6284), .B1(n4960), .Y(
n7037) );
AOI22X1TS U7754 ( .A0(n6285), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[10]), .Y(n7036) );
AOI22X1TS U7755 ( .A0(Data_1[12]), .A1(n6287), .B0(n6286), .B1(n4960), .Y(
n7039) );
AOI22X1TS U7756 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n6288), .B1(
FPSENCOS_d_ff2_X[12]), .Y(n7038) );
AOI22X1TS U7757 ( .A0(Data_1[23]), .A1(n6292), .B0(n6544), .B1(n6289), .Y(
n7041) );
AOI22X1TS U7758 ( .A0(n6290), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[23]), .Y(n7040) );
AOI22X1TS U7759 ( .A0(Data_1[28]), .A1(n6292), .B0(n6291), .B1(n6294), .Y(
n7043) );
AOI22X1TS U7760 ( .A0(n6295), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n6293), .B1(
FPSENCOS_d_ff2_X[28]), .Y(n7042) );
AOI22X1TS U7761 ( .A0(Data_1[31]), .A1(n6344), .B0(n6582), .B1(n6294), .Y(
n7045) );
AOI22X1TS U7762 ( .A0(n6295), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6345), .B1(
FPSENCOS_d_ff2_X[31]), .Y(n7044) );
OAI2BB2XLTS U7763 ( .B0(n6406), .B1(n6424), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[31]), .Y(n1909) );
OAI2BB2XLTS U7764 ( .B0(n6407), .B1(n6424), .A0N(n6296), .A1N(
FPSENCOS_d_ff_Yn[31]), .Y(n1908) );
OAI2BB2XLTS U7765 ( .B0(n6339), .B1(n6297), .A0N(n6306), .A1N(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1906) );
OAI2BB2XLTS U7766 ( .B0(n6240), .B1(n6298), .A0N(n6306), .A1N(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1904) );
OAI2BB2XLTS U7767 ( .B0(n6339), .B1(n6299), .A0N(n6306), .A1N(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1902) );
INVX2TS U7768 ( .A(n6278), .Y(n6314) );
OAI2BB2XLTS U7769 ( .B0(n6240), .B1(n6302), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1900) );
OAI2BB2XLTS U7770 ( .B0(n6272), .B1(n6303), .A0N(n6306), .A1N(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1898) );
OAI2BB2XLTS U7771 ( .B0(n6339), .B1(n6304), .A0N(n6306), .A1N(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1896) );
OAI2BB2XLTS U7772 ( .B0(n2410), .B1(n6317), .A0N(FPSENCOS_d_ff_Yn[6]), .A1N(
n6310), .Y(n1895) );
OAI2BB2XLTS U7773 ( .B0(n6321), .B1(n2410), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1894) );
OAI2BB2XLTS U7774 ( .B0(n6272), .B1(n6305), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1892) );
OAI2BB2XLTS U7775 ( .B0(n6321), .B1(n6307), .A0N(n6306), .A1N(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1890) );
OAI2BB2XLTS U7776 ( .B0(n6272), .B1(n6308), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1888) );
OAI2BB2XLTS U7777 ( .B0(n6240), .B1(n7046), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1886) );
OAI2BB2XLTS U7778 ( .B0(n6272), .B1(n6309), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1884) );
OAI2BB2XLTS U7779 ( .B0(n6240), .B1(n7047), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1882) );
OAI2BB2XLTS U7780 ( .B0(n6240), .B1(n2414), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1880) );
OAI2BB2XLTS U7781 ( .B0(n6321), .B1(n6312), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1878) );
OAI2BB2XLTS U7782 ( .B0(n6321), .B1(n6313), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1876) );
OAI2BB2XLTS U7783 ( .B0(n6272), .B1(n6315), .A0N(n6314), .A1N(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1874) );
OAI2BB2XLTS U7784 ( .B0(n6339), .B1(n6316), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1872) );
OAI2BB2XLTS U7785 ( .B0(n6321), .B1(n6318), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1870) );
BUFX3TS U7786 ( .A(n6337), .Y(n6325) );
OAI2BB2XLTS U7787 ( .B0(n6272), .B1(n6319), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1868) );
OAI2BB2XLTS U7788 ( .B0(n6321), .B1(n6320), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1866) );
OAI2BB2XLTS U7789 ( .B0(n6272), .B1(n6322), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1864) );
OAI2BB2XLTS U7790 ( .B0(n6240), .B1(n6324), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1862) );
OAI2BB2XLTS U7791 ( .B0(n6797), .B1(n6325), .A0N(FPSENCOS_d_ff_Yn[24]),
.A1N(n6326), .Y(n1860) );
OAI2BB2XLTS U7792 ( .B0(n6742), .B1(n6337), .A0N(FPSENCOS_d_ff_Yn[30]),
.A1N(n6326), .Y(n1854) );
AOI21X1TS U7793 ( .A0(intadd_5_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n6327),
.Y(n6328) );
AOI21X1TS U7794 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n6329), .B0(n6333), .Y(
n6331) );
OAI2BB2XLTS U7795 ( .B0(n7050), .B1(n6337), .A0N(n6336), .A1N(
FPSENCOS_d_ff_Yn[31]), .Y(n1845) );
OAI2BB2XLTS U7796 ( .B0(n6240), .B1(n7050), .A0N(n6338), .A1N(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1844) );
AOI22X1TS U7797 ( .A0(Data_2[3]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n6348), .Y(n6341) );
AOI22X1TS U7798 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[3]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[3]), .Y(n6340) );
NAND2X1TS U7799 ( .A(n6381), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n6359) );
AOI22X1TS U7800 ( .A0(Data_2[5]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n6348), .Y(n6343) );
AOI22X1TS U7801 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[5]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[5]), .Y(n6342) );
NAND2X1TS U7802 ( .A(n6381), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n6354) );
AOI22X1TS U7803 ( .A0(Data_2[7]), .A1(n6344), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n6348), .Y(n6347) );
AOI22X1TS U7804 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[7]), .B0(n6345),
.B1(FPSENCOS_d_ff3_sh_y_out[7]), .Y(n6346) );
NAND2X1TS U7805 ( .A(n6368), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n6349) );
AOI22X1TS U7806 ( .A0(Data_2[11]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n6348), .Y(n6351) );
AOI22X1TS U7807 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[11]), .B0(n4539),
.B1(FPSENCOS_d_ff3_sh_y_out[11]), .Y(n6350) );
NAND3X1TS U7808 ( .A(n6351), .B(n6350), .C(n6349), .Y(n1832) );
AOI22X1TS U7809 ( .A0(Data_2[13]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n6374), .Y(n6353) );
AOI22X1TS U7810 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[13]), .B0(n6380),
.B1(FPSENCOS_d_ff3_sh_y_out[13]), .Y(n6352) );
NAND2X1TS U7811 ( .A(n6368), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n6365) );
AOI22X1TS U7812 ( .A0(Data_2[14]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n6374), .Y(n6356) );
AOI22X1TS U7813 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[14]), .B0(n6380),
.B1(FPSENCOS_d_ff3_sh_y_out[14]), .Y(n6355) );
AOI22X1TS U7814 ( .A0(Data_2[15]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n6374), .Y(n6358) );
AOI22X1TS U7815 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[15]), .B0(n5041),
.B1(FPSENCOS_d_ff3_sh_y_out[15]), .Y(n6357) );
NAND2X1TS U7816 ( .A(n6381), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n6371) );
NAND3X1TS U7817 ( .A(n6358), .B(n6357), .C(n6371), .Y(n1828) );
AOI22X1TS U7818 ( .A0(Data_2[16]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n6374), .Y(n6361) );
AOI22X1TS U7819 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[16]), .B0(n6380),
.B1(FPSENCOS_d_ff3_sh_y_out[16]), .Y(n6360) );
AOI22X1TS U7820 ( .A0(Data_2[17]), .A1(n6362), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n6374), .Y(n6364) );
AOI22X1TS U7821 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[17]), .B0(n4539),
.B1(FPSENCOS_d_ff3_sh_y_out[17]), .Y(n6363) );
NAND3X1TS U7822 ( .A(n6364), .B(n6363), .C(n6371), .Y(n1826) );
AOI22X1TS U7823 ( .A0(Data_2[18]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n6374), .Y(n6367) );
AOI22X1TS U7824 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[18]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[18]), .Y(n6366) );
AOI22X1TS U7825 ( .A0(Data_2[19]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n6374), .Y(n6370) );
AOI22X1TS U7826 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[19]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[19]), .Y(n6369) );
NAND2X1TS U7827 ( .A(n6368), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n6376) );
AOI22X1TS U7828 ( .A0(Data_2[20]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n6374), .Y(n6373) );
AOI22X1TS U7829 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[20]), .B0(n6380),
.B1(FPSENCOS_d_ff3_sh_y_out[20]), .Y(n6372) );
AOI22X1TS U7830 ( .A0(Data_2[22]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n6374), .Y(n6378) );
AOI22X1TS U7831 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[22]), .B0(n6375),
.B1(FPSENCOS_d_ff3_sh_y_out[22]), .Y(n6377) );
AOI22X1TS U7832 ( .A0(Data_2[27]), .A1(n6379), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n6384), .Y(n6383) );
AOI22X1TS U7833 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[27]), .B0(n6380),
.B1(FPSENCOS_d_ff3_sh_y_out[27]), .Y(n6382) );
NAND2X1TS U7834 ( .A(n6381), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n6387) );
AOI22X1TS U7835 ( .A0(Data_2[28]), .A1(n6420), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n6384), .Y(n6386) );
AOI22X1TS U7836 ( .A0(n6421), .A1(FPSENCOS_d_ff3_sh_x_out[28]), .B0(n5041),
.B1(FPSENCOS_d_ff3_sh_y_out[28]), .Y(n6385) );
AOI22X1TS U7837 ( .A0(Data_2[29]), .A1(n6420), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n6419), .Y(n6389) );
AOI22X1TS U7838 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[29]), .B0(n5041),
.B1(FPSENCOS_d_ff3_sh_y_out[29]), .Y(n6388) );
NAND3X1TS U7839 ( .A(n6389), .B(n6388), .C(n6387), .Y(n1814) );
OAI2BB2XLTS U7840 ( .B0(n6392), .B1(n6709), .A0N(n6391), .A1N(n6390), .Y(
n1812) );
OAI2BB2XLTS U7841 ( .B0(n6406), .B1(n6398), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[23]), .Y(n1786) );
OAI2BB2XLTS U7842 ( .B0(n6407), .B1(n6398), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[23]), .Y(n1785) );
OAI2BB2XLTS U7843 ( .B0(n6418), .B1(n6398), .A0N(n6397), .A1N(
FPSENCOS_d_ff_Xn[23]), .Y(n1784) );
OAI2BB2XLTS U7844 ( .B0(n6406), .B1(n6399), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[24]), .Y(n1783) );
OAI2BB2XLTS U7845 ( .B0(n6407), .B1(n6399), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1782) );
OAI2BB2XLTS U7846 ( .B0(n6418), .B1(n6399), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[24]), .Y(n1781) );
OAI2BB2XLTS U7847 ( .B0(n6406), .B1(n6400), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[25]), .Y(n1780) );
OAI2BB2XLTS U7848 ( .B0(n6407), .B1(n6400), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[25]), .Y(n1779) );
OAI2BB2XLTS U7849 ( .B0(n6418), .B1(n6400), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[25]), .Y(n1778) );
OAI2BB2XLTS U7850 ( .B0(n6406), .B1(n6401), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[26]), .Y(n1777) );
OAI2BB2XLTS U7851 ( .B0(n6407), .B1(n6401), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1776) );
OAI2BB2XLTS U7852 ( .B0(n6418), .B1(n6401), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[26]), .Y(n1775) );
OAI2BB2XLTS U7853 ( .B0(n6406), .B1(n6403), .A0N(n6402), .A1N(
FPSENCOS_d_ff_Zn[27]), .Y(n1774) );
OAI2BB2XLTS U7854 ( .B0(n6407), .B1(n6403), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[27]), .Y(n1773) );
OAI2BB2XLTS U7855 ( .B0(n6418), .B1(n6403), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[27]), .Y(n1772) );
OAI2BB2XLTS U7856 ( .B0(n6406), .B1(n6405), .A0N(n6410), .A1N(
FPSENCOS_d_ff_Zn[28]), .Y(n1771) );
OAI2BB2XLTS U7857 ( .B0(n6407), .B1(n6405), .A0N(n6404), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1770) );
OAI2BB2XLTS U7858 ( .B0(n6418), .B1(n6405), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[28]), .Y(n1769) );
OAI2BB2XLTS U7859 ( .B0(n6406), .B1(n6409), .A0N(n6410), .A1N(
FPSENCOS_d_ff_Zn[29]), .Y(n1768) );
OAI2BB2XLTS U7860 ( .B0(n6407), .B1(n6409), .A0N(n6414), .A1N(
FPSENCOS_d_ff_Yn[29]), .Y(n1767) );
OAI2BB2XLTS U7861 ( .B0(n6418), .B1(n6409), .A0N(n6408), .A1N(
FPSENCOS_d_ff_Xn[29]), .Y(n1766) );
OAI2BB2XLTS U7862 ( .B0(n6411), .B1(n6417), .A0N(n6410), .A1N(
FPSENCOS_d_ff_Zn[30]), .Y(n1765) );
OAI2BB2XLTS U7863 ( .B0(n6415), .B1(n6417), .A0N(n6414), .A1N(
FPSENCOS_d_ff_Yn[30]), .Y(n1730) );
OAI2BB2XLTS U7864 ( .B0(n6418), .B1(n6417), .A0N(n6416), .A1N(
FPSENCOS_d_ff_Xn[30]), .Y(n1729) );
AOI22X1TS U7865 ( .A0(Data_2[31]), .A1(n6420), .B0(FPADDSUB_intDY_EWSW[31]),
.B1(n6419), .Y(n6423) );
AOI22X1TS U7866 ( .A0(n2376), .A1(FPSENCOS_d_ff3_sh_x_out[31]), .B0(n5041),
.B1(FPSENCOS_d_ff3_sh_y_out[31]), .Y(n6422) );
NAND2X1TS U7867 ( .A(n6423), .B(n6422), .Y(n1728) );
OAI2BB2XLTS U7868 ( .B0(n6425), .B1(n6424), .A0N(n6416), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1727) );
AOI22X1TS U7869 ( .A0(n6427), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n6426), .Y(n6430) );
XOR2X1TS U7870 ( .A(n6430), .B(n6429), .Y(n6431) );
OAI2BB2XLTS U7871 ( .B0(n6432), .B1(n6431), .A0N(n6432), .A1N(
cordic_result_31_), .Y(n1695) );
OAI22X1TS U7872 ( .A0(n6434), .A1(n6433), .B0(n6634), .B1(n6644), .Y(n6435)
);
NOR4X1TS U7873 ( .A(n2323), .B(n5499), .C(n2370), .D(n2279), .Y(n6446) );
NOR4X1TS U7874 ( .A(DP_OP_501J1_127_1459_n910), .B(n6438), .C(
FPMULT_Op_MY[0]), .D(n6662), .Y(n6445) );
NOR4X1TS U7875 ( .A(n6439), .B(FPMULT_Op_MY[4]), .C(FPMULT_Op_MY[3]), .D(
FPMULT_Op_MY[2]), .Y(n6444) );
NOR4X1TS U7876 ( .A(n2206), .B(n2228), .C(n2207), .D(n6633), .Y(n6443) );
NAND4XLTS U7877 ( .A(n6446), .B(n6445), .C(n6444), .D(n6443), .Y(n6468) );
NOR3BX1TS U7878 ( .AN(n6449), .B(n6448), .C(n6447), .Y(n6454) );
NOR4X1TS U7879 ( .A(n5500), .B(n6631), .C(FPMULT_Op_MY[30]), .D(
FPMULT_Op_MY[29]), .Y(n6451) );
NAND4XLTS U7880 ( .A(n6454), .B(n6453), .C(n6452), .D(n6451), .Y(n6467) );
NOR4X1TS U7881 ( .A(DP_OP_501J1_127_1459_n939), .B(n5489), .C(
FPMULT_Op_MX[7]), .D(FPMULT_Op_MX[9]), .Y(n6460) );
AND4X1TS U7882 ( .A(n6638), .B(n6697), .C(n6856), .D(n6859), .Y(n6459) );
NOR4X1TS U7883 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[5]), .C(
FPMULT_Op_MX[0]), .D(n2194), .Y(n6458) );
NOR4X1TS U7884 ( .A(n2278), .B(DP_OP_501J1_127_1459_n952), .C(
FPMULT_Op_MX[8]), .D(FPMULT_Op_MX[19]), .Y(n6457) );
NAND4XLTS U7885 ( .A(n6460), .B(n6459), .C(n6458), .D(n6457), .Y(n6466) );
NOR4X1TS U7886 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[27]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[25]), .Y(n6464) );
AND4X1TS U7887 ( .A(n6884), .B(n6885), .C(n6888), .D(n6690), .Y(n6463) );
NOR4X1TS U7888 ( .A(n2304), .B(n2346), .C(FPMULT_Op_MX[30]), .D(
FPMULT_Op_MX[29]), .Y(n6462) );
NAND4XLTS U7889 ( .A(n6464), .B(n6463), .C(n6462), .D(n6461), .Y(n6465) );
OA22X1TS U7890 ( .A0(n6468), .A1(n6467), .B0(n6466), .B1(n6465), .Y(n6469)
);
OAI2BB2XLTS U7891 ( .B0(n6470), .B1(n6469), .A0N(n6470), .A1N(
FPMULT_zero_flag), .Y(n1625) );
OA22X1TS U7892 ( .A0(n6477), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n2356), .Y(n1584) );
OA22X1TS U7893 ( .A0(n6477), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n2356), .Y(n1583) );
OA22X1TS U7894 ( .A0(n6472), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n2356), .Y(n1582) );
OA22X1TS U7895 ( .A0(n6472), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n2356), .Y(n1581) );
OA22X1TS U7896 ( .A0(n6472), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n2356), .Y(n1580) );
OA22X1TS U7897 ( .A0(n6472), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n2356), .Y(n1579) );
OA22X1TS U7898 ( .A0(n6472), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n2338), .Y(n1578) );
OA22X1TS U7899 ( .A0(n6477), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n2356), .Y(n1577) );
INVX2TS U7900 ( .A(n6477), .Y(n6476) );
OAI2BB1X1TS U7901 ( .A0N(mult_result[31]), .A1N(n6476), .B0(n6475), .Y(n1576) );
OAI2BB2XLTS U7902 ( .B0(n6743), .B1(n2338), .A0N(mult_result[2]), .A1N(n6478), .Y(n1502) );
OAI2BB2XLTS U7903 ( .B0(n6782), .B1(n2338), .A0N(mult_result[7]), .A1N(n6478), .Y(n1497) );
INVX2TS U7904 ( .A(n6477), .Y(n6479) );
OAI2BB2XLTS U7905 ( .B0(n6788), .B1(n2338), .A0N(mult_result[11]), .A1N(
n6479), .Y(n1493) );
OAI2BB2XLTS U7906 ( .B0(n6790), .B1(n2338), .A0N(mult_result[18]), .A1N(
n6478), .Y(n1486) );
OAI2BB2XLTS U7907 ( .B0(n6789), .B1(n2338), .A0N(mult_result[19]), .A1N(
n6478), .Y(n1485) );
OAI2BB2XLTS U7908 ( .B0(n6791), .B1(n2338), .A0N(mult_result[20]), .A1N(
n6478), .Y(n1484) );
INVX2TS U7909 ( .A(n6616), .Y(n6617) );
XNOR2X1TS U7910 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(
FPADDSUB_DmP_EXP_EWSW[27]), .Y(n6482) );
XOR2X1TS U7911 ( .A(intadd_4_n1), .B(n6482), .Y(n6483) );
OAI2BB2XLTS U7912 ( .B0(n6616), .B1(n6655), .A0N(n6796), .A1N(
FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1457) );
INVX2TS U7913 ( .A(n6485), .Y(n6575) );
INVX2TS U7914 ( .A(n6839), .Y(n6609) );
INVX2TS U7915 ( .A(n6592), .Y(n6518) );
BUFX3TS U7916 ( .A(n6610), .Y(n6517) );
OA21XLTS U7917 ( .A0(n6500), .A1(underflow_flag_addsubt), .B0(n6489), .Y(
n1412) );
OAI22X1TS U7918 ( .A0(n6500), .A1(n6493), .B0(n6492), .B1(n6491), .Y(n1408)
);
OAI22X1TS U7919 ( .A0(n6531), .A1(n6496), .B0(n6495), .B1(n2309), .Y(n1405)
);
OAI22X1TS U7920 ( .A0(n6500), .A1(n6499), .B0(n6498), .B1(n6491), .Y(n1402)
);
INVX2TS U7921 ( .A(n6592), .Y(n6591) );
OAI2BB2XLTS U7922 ( .B0(n6617), .B1(n6775), .A0N(n6591), .A1N(
FPADDSUB_DmP_EXP_EWSW[18]), .Y(n1400) );
OAI22X1TS U7923 ( .A0(n6531), .A1(n6503), .B0(n6502), .B1(n2309), .Y(n1399)
);
OAI22X1TS U7924 ( .A0(n6531), .A1(n6506), .B0(n6505), .B1(n6491), .Y(n1396)
);
OAI22X1TS U7925 ( .A0(n6531), .A1(n6509), .B0(n6508), .B1(n2309), .Y(n1393)
);
OAI22X1TS U7926 ( .A0(n6531), .A1(n6511), .B0(n6510), .B1(n6491), .Y(n1390)
);
OAI2BB2XLTS U7927 ( .B0(n6617), .B1(n6776), .A0N(n6591), .A1N(
FPADDSUB_DmP_EXP_EWSW[17]), .Y(n1388) );
OAI22X1TS U7928 ( .A0(n6531), .A1(n6513), .B0(n6512), .B1(n2309), .Y(n1381)
);
INVX2TS U7929 ( .A(n6616), .Y(n6620) );
OAI22X1TS U7930 ( .A0(n6531), .A1(n6516), .B0(n6515), .B1(n6491), .Y(n1378)
);
OAI22X1TS U7931 ( .A0(n6531), .A1(n6520), .B0(n6519), .B1(n2309), .Y(n1375)
);
OAI2BB2XLTS U7932 ( .B0(n6617), .B1(n6711), .A0N(n6591), .A1N(
FPADDSUB_DmP_EXP_EWSW[8]), .Y(n1373) );
OAI22X1TS U7933 ( .A0(n6531), .A1(n6522), .B0(n6521), .B1(n6491), .Y(n1372)
);
BUFX3TS U7934 ( .A(n6796), .Y(n6619) );
OAI22X1TS U7935 ( .A0(n6606), .A1(n6526), .B0(n6525), .B1(n2309), .Y(n1369)
);
OAI22X1TS U7936 ( .A0(n6606), .A1(n6528), .B0(n6527), .B1(n2310), .Y(n1366)
);
OAI22X1TS U7937 ( .A0(n6531), .A1(n6530), .B0(n6529), .B1(n2309), .Y(n1363)
);
AOI22X1TS U7938 ( .A0(n3248), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2432), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n6532) );
AOI22X1TS U7939 ( .A0(n6708), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n2429), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n6533) );
AOI22X1TS U7940 ( .A0(n2256), .A1(FPADDSUB_intDY_EWSW[9]), .B0(n2404), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n6534) );
AOI22X1TS U7941 ( .A0(n6707), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2263), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n6535) );
NOR4X1TS U7942 ( .A(n6539), .B(n6538), .C(n6537), .D(n6536), .Y(n6570) );
AOI22X1TS U7943 ( .A0(n2265), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2430), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n6540) );
AOI22X1TS U7944 ( .A0(n2255), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n6542), .B1(
FPADDSUB_intDY_EWSW[12]), .Y(n6541) );
AOI22X1TS U7945 ( .A0(n2257), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2204), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n6543) );
INVX2TS U7946 ( .A(n6544), .Y(n6546) );
AOI22X1TS U7947 ( .A0(n6546), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2258), .B1(
FPADDSUB_intDY_EWSW[14]), .Y(n6545) );
NOR4X1TS U7948 ( .A(n6550), .B(n6549), .C(n6548), .D(n6547), .Y(n6569) );
AOI22X1TS U7949 ( .A0(n2259), .A1(FPADDSUB_intDY_EWSW[11]), .B0(n2426), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n6551) );
AOI22X1TS U7950 ( .A0(n2264), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n2418), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n6552) );
OAI221XLTS U7951 ( .A0(n2264), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n2418),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n6552), .Y(n6565) );
OAI22X1TS U7952 ( .A0(n2260), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n2415), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n6553) );
OAI22X1TS U7953 ( .A0(n2261), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n2231), .B1(
FPADDSUB_intDY_EWSW[19]), .Y(n6555) );
OAI22X1TS U7954 ( .A0(n2398), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n6698), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n6556) );
OAI22X1TS U7955 ( .A0(n2262), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n3314), .B1(
FPADDSUB_intDY_EWSW[28]), .Y(n6557) );
OAI22X1TS U7956 ( .A0(n6651), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n6706), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n6558) );
NAND4XLTS U7957 ( .A(n6562), .B(n6561), .C(n6560), .D(n6559), .Y(n6563) );
NOR4X1TS U7958 ( .A(n6566), .B(n6565), .C(n6564), .D(n6563), .Y(n6568) );
OAI22X1TS U7959 ( .A0(n6582), .A1(n6573), .B0(n6572), .B1(n6583), .Y(n6574)
);
OAI2BB1X1TS U7960 ( .A0N(FPADDSUB_SIGN_FLAG_EXP), .A1N(n6639), .B0(n6574),
.Y(n1362) );
AOI22X1TS U7961 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n6582), .B0(
FPADDSUB_OP_FLAG_EXP), .B1(n6579), .Y(n6581) );
INVX2TS U7962 ( .A(n6583), .Y(n6580) );
AOI22X1TS U7963 ( .A0(n6583), .A1(n6582), .B0(n6581), .B1(n6580), .Y(n1355)
);
INVX2TS U7964 ( .A(n6584), .Y(n6603) );
OAI22X1TS U7965 ( .A0(n6606), .A1(n6587), .B0(n6586), .B1(n2310), .Y(n1329)
);
OAI22X1TS U7966 ( .A0(n6606), .A1(n6590), .B0(n6589), .B1(n2310), .Y(n1313)
);
INVX2TS U7967 ( .A(n6592), .Y(n6607) );
OAI2BB2XLTS U7968 ( .B0(n6617), .B1(n6654), .A0N(n6591), .A1N(
FPADDSUB_DmP_EXP_EWSW[7]), .Y(n1304) );
OAI22X1TS U7969 ( .A0(n6606), .A1(n6595), .B0(n6594), .B1(n2310), .Y(n1299)
);
OAI22X1TS U7970 ( .A0(n6606), .A1(n6598), .B0(n6597), .B1(n2310), .Y(n1292)
);
OAI22X1TS U7971 ( .A0(n6606), .A1(n6601), .B0(n6600), .B1(n2310), .Y(n1285)
);
OAI22X1TS U7972 ( .A0(n6606), .A1(n6605), .B0(n6604), .B1(n2310), .Y(n1278)
);
INVX2TS U7973 ( .A(n6616), .Y(n6613) );
BUFX3TS U7974 ( .A(n6610), .Y(n6612) );
BUFX3TS U7975 ( .A(n6611), .Y(n6615) );
CMPR42X2TS U7976 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_499J1_125_4188_n272), .D(n2209), .ICI(DP_OP_499J1_125_4188_n223),
.S(DP_OP_499J1_125_4188_n222), .ICO(DP_OP_499J1_125_4188_n220), .CO(
DP_OP_499J1_125_4188_n221) );
CMPR42X2TS U7977 ( .A(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
FPMULT_inst_RecursiveKOA_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(n2222), .D(DP_OP_499J1_125_4188_n299), .ICI(DP_OP_499J1_125_4188_n232), .S(
DP_OP_499J1_125_4188_n231), .ICO(DP_OP_499J1_125_4188_n229), .CO(
DP_OP_499J1_125_4188_n230) );
CMPR42X1TS U7978 ( .A(DP_OP_501J1_127_1459_n198), .B(
DP_OP_501J1_127_1459_n271), .C(DP_OP_501J1_127_1459_n263), .D(
DP_OP_501J1_127_1459_n195), .ICI(DP_OP_501J1_127_1459_n192), .S(
DP_OP_501J1_127_1459_n190), .ICO(DP_OP_501J1_127_1459_n188), .CO(
DP_OP_501J1_127_1459_n189) );
CMPR42X1TS U7979 ( .A(DP_OP_502J1_128_2852_n172), .B(
DP_OP_502J1_128_2852_n186), .C(DP_OP_502J1_128_2852_n179), .D(
DP_OP_502J1_128_2852_n127), .ICI(DP_OP_502J1_128_2852_n126), .S(
DP_OP_502J1_128_2852_n123), .ICO(DP_OP_502J1_128_2852_n121), .CO(
DP_OP_502J1_128_2852_n122) );
CMPR42X1TS U7980 ( .A(DP_OP_500J1_126_2852_n172), .B(
DP_OP_500J1_126_2852_n186), .C(DP_OP_500J1_126_2852_n179), .D(
DP_OP_500J1_126_2852_n127), .ICI(DP_OP_500J1_126_2852_n126), .S(
DP_OP_500J1_126_2852_n123), .ICO(DP_OP_500J1_126_2852_n121), .CO(
DP_OP_500J1_126_2852_n122) );
initial $sdf_annotate("FPU_Interface2v2_syn.sdf");
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_miim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_miim.v,v $
// Revision 1.7 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.6 2005/02/21 12:48:07 igorm
// Warning fixes.
//
// Revision 1.5 2003/05/16 10:08:27 mohor
// Busy was set 2 cycles too late. Reported by Dennis Scott.
//
// Revision 1.4 2002/08/14 18:32:10 mohor
// - Busy signal was not set on time when scan status operation was performed
// and clock was divided with more than 2.
// - Nvalid remains valid two more clocks (was previously cleared too soon).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
input Clk; // Host Clock
input Reset; // General Reset
input [7:0] Divider; // Divider for the host clock
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
input Mdi; // MII Management Data In
output Mdc; // MII Management Data Clock
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
parameter Tp = 1;
reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal
reg EndBusy; // End Busy signal (stops the operation in progress)
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
reg RStat_q1; // Read Status operation delayed 1 Clk cycle
reg RStat_q2; // Read Status operation delayed 2 Clk cycles
reg RStat_q3; // Read Status operation delayed 3 Clk cycles
reg RStatStart; // Start Read Status Command (positive edge detected)
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
reg ScanStat_q1; // Scan Status operation delayed 1 cycle
reg ScanStat_q2; // Scan Status operation delayed 2 cycles
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
wire WriteDataOp; // Write Data Operation (positive edge detected)
wire ReadStatusOp; // Read Status Operation (positive edge detected)
wire ScanStatusOp; // Scan Status Operation (positive edge detected)
wire StartOp; // Start Operation (start of any of the preceding operations)
wire EndOp; // End of Operation
reg InProgress; // Operation in progress
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
reg [6:0] BitCounter; // Bit Counter
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= #Tp 1'b0;
EndBusy <= #Tp 1'b0;
end
else
begin
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
EndBusy <= #Tp EndBusy_d;
end
end
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= #Tp 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= #Tp 1;
else
UpdateMIIRX_DATAReg <= #Tp 0;
end
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= #Tp 1'b0;
WCtrlData_q2 <= #Tp 1'b0;
WCtrlData_q3 <= #Tp 1'b0;
RStat_q1 <= #Tp 1'b0;
RStat_q2 <= #Tp 1'b0;
RStat_q3 <= #Tp 1'b0;
ScanStat_q1 <= #Tp 1'b0;
ScanStat_q2 <= #Tp 1'b0;
SyncStatMdcEn <= #Tp 1'b0;
end
else
begin
WCtrlData_q1 <= #Tp WCtrlData;
WCtrlData_q2 <= #Tp WCtrlData_q1;
WCtrlData_q3 <= #Tp WCtrlData_q2;
RStat_q1 <= #Tp RStat;
RStat_q2 <= #Tp RStat_q1;
RStat_q3 <= #Tp RStat_q2;
ScanStat_q1 <= #Tp ScanStat;
ScanStat_q2 <= #Tp ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= #Tp ScanStat_q2;
end
end
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= #Tp 1'b0;
WCtrlDataStart_q <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= #Tp 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= #Tp 1'b1;
WCtrlDataStart_q <= #Tp WCtrlDataStart;
end
end
end
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= #Tp 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= #Tp 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= #Tp 1'b1;
end
end
end
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= #Tp 1'b0;
WCtrlDataStart_q2 <= #Tp 1'b0;
RStatStart_q1 <= #Tp 1'b0;
RStatStart_q2 <= #Tp 1'b0;
InProgress_q1 <= #Tp 1'b0;
InProgress_q2 <= #Tp 1'b0;
InProgress_q3 <= #Tp 1'b0;
LatchByte0_d <= #Tp 1'b0;
LatchByte1_d <= #Tp 1'b0;
LatchByte <= #Tp 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
RStatStart_q1 <= #Tp RStatStart;
RStatStart_q2 <= #Tp RStatStart_q1;
LatchByte[0] <= #Tp LatchByte0_d;
LatchByte[1] <= #Tp LatchByte1_d;
LatchByte0_d <= #Tp LatchByte0_d2;
LatchByte1_d <= #Tp LatchByte1_d2;
InProgress_q1 <= #Tp InProgress;
InProgress_q2 <= #Tp InProgress_q1;
InProgress_q3 <= #Tp InProgress_q2;
end
end
end
// Generation of the Operation signals
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
// Busy
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= #Tp WriteDataOp;
InProgress <= #Tp 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
end
end
end
end
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= #Tp 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= #Tp 7'h21;
else
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= #Tp 7'h0;
end
end
end
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_SYMBOL_V
`define SKY130_FD_SC_HDLL__O2BB2A_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_SYMBOL_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_data_in (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iodelay #(
parameter ODELAY_VALUE = 30,
parameter size = 2,
parameter DELAY_SRC = "IO"
) (
/* pad -> fabric */
input [size-1:0] IDATAIN,
output [size-1:0] DATAOUT,
/* fabric -> pad */
input [size-1:0] T,
output [size-1:0] TOUT,
input [size-1:0] ODATAIN,
output [size-1:0] DOUT,
/* control pins */
input INC,
input CE,
input RST,
input CAL,
input CLK,
input IOCLK0,
input IOCLK1
);
genvar i;
generate
for(i=0;i<size;i=i+1)
IODELAY2 #(
.DELAY_SRC(DELAY_SRC),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR"),
.ODELAY_VALUE(ODELAY_VALUE)
) idelay (
.IDATAIN(IDATAIN[i]),
.DATAOUT(DATAOUT[i]),
.T(T[i]),
.TOUT(TOUT[i]),
.ODATAIN(ODATAIN[i]),
.DOUT(DOUT[i]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.CAL(CAL)
);
endgenerate
endmodule
|
//ft_fifo_tester.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:ft_fifo_tester
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/08/14
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module ft_fifo_tester (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
reg [31:0] r_test_data;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
r_test_data <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
r_test_data <= i_wbs_dat;
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
//$display("user read %h", ADDR_0);
//o_wbs_dat <= ADDR_0;
o_wbs_dat <= r_test_data;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/wram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Work RAM module; implements 2KB of on-board WRAM as fpga block RAM.
***************************************************************************************************/
module wram(
input clk_in, // system clock
input en_in, // chip enable
input r_nw_in, // read/write select (read: 0, write: 1)
input [10:0] a_in, // memory address
input [ 7:0] d_in, // data input
output [ 7:0] d_out // data output
);
wire wram_bram_we;
wire [7:0] wram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) wram_bram(
.clk(clk_in),
.we(wram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(wram_bram_dout)
);
assign wram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? wram_bram_dout : 8'h00;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
|
`include "bsg_defines.v"
module bsg_dmc_controller
import bsg_dmc_pkg::*;
#(parameter `BSG_INV_PARAM( ui_addr_width_p )
,parameter `BSG_INV_PARAM( ui_data_width_p )
,parameter `BSG_INV_PARAM( burst_data_width_p )
,parameter `BSG_INV_PARAM( dfi_data_width_p )
,parameter `BSG_INV_PARAM( cmd_afifo_depth_p )
,parameter `BSG_INV_PARAM( cmd_sfifo_depth_p )
,parameter ui_burst_length_lp = burst_data_width_p / ui_data_width_p
,localparam ui_mask_width_lp = ui_data_width_p >> 3
,localparam dfi_mask_width_lp = dfi_data_width_p >> 3
,localparam dfi_burst_length_lp = burst_data_width_p / dfi_data_width_p)
// User interface clock and reset
(input ui_clk_i
,input ui_clk_sync_rst_i
// User interface signals
,input [ui_addr_width_p-1:0] app_addr_i
,input app_cmd_e app_cmd_i
,input app_en_i
,output app_rdy_o
,input app_wdf_wren_i
,input [ui_data_width_p-1:0] app_wdf_data_i
,input [ui_mask_width_lp-1:0] app_wdf_mask_i
,input app_wdf_end_i
,output app_wdf_rdy_o
,output app_rd_data_valid_o
,output [ui_data_width_p-1:0] app_rd_data_o
,output logic app_rd_data_end_o
,input app_ref_req_i
,output app_ref_ack_o
,input app_zq_req_i
,output app_zq_ack_o
,input app_sr_req_i
,output app_sr_active_o
// Status signal
,output logic init_calib_complete_o
// DDR PHY interface clock and reset
,input dfi_clk_i
,input dfi_clk_sync_rst_i
// DDR PHY interface signals
,output logic [2:0] dfi_bank_o
,output logic [15:0] dfi_address_o
,output logic dfi_cke_o
,output logic dfi_cs_n_o
,output logic dfi_ras_n_o
,output logic dfi_cas_n_o
,output logic dfi_we_n_o
,output logic dfi_reset_n_o
,output logic dfi_odt_o
,output logic dfi_wrdata_en_o
,output logic [dfi_data_width_p-1:0] dfi_wrdata_o
,output logic [dfi_mask_width_lp-1:0] dfi_wrdata_mask_o
,output logic dfi_rddata_en_o
,input [dfi_data_width_p-1:0] dfi_rddata_i
,input dfi_rddata_valid_i
// Control and Status Registers
,input bsg_dmc_s dmc_p_i);
typedef enum logic [1:0] {IDLE, INIT, REFR, LDST} state;
integer i;
genvar k;
logic cmd_afifo_wclk, cmd_afifo_rclk;
logic cmd_afifo_wrst, cmd_afifo_rrst;
logic cmd_afifo_winc, cmd_afifo_rinc;
logic cmd_afifo_wfull, cmd_afifo_rvalid;
`declare_app_cmd_afifo_entry_s(ui_addr_width_p);
app_cmd_afifo_entry_s cmd_afifo_wdata, cmd_afifo_rdata;
logic cmd_sfifo_winc, cmd_sfifo_rinc;
logic cmd_sfifo_ready, cmd_sfifo_valid;
dfi_cmd_sfifo_entry_s cmd_sfifo_wdata, cmd_sfifo_rdata;
logic wrdata_afifo_wclk, wrdata_afifo_rclk;
logic wrdata_afifo_wrst, wrdata_afifo_rrst;
logic wrdata_afifo_winc, wrdata_afifo_rinc;
logic wrdata_afifo_wfull, wrdata_afifo_rvalid;
logic [ui_data_width_p+ui_mask_width_lp-1:0] wrdata_afifo_wdata, wrdata_afifo_rdata;
logic rddata_afifo_wclk, rddata_afifo_rclk;
logic rddata_afifo_wrst, rddata_afifo_rrst;
logic rddata_afifo_winc, rddata_afifo_rinc;
logic rddata_afifo_wfull, rddata_afifo_rvalid;
logic [dfi_data_width_p-1:0] rddata_afifo_wdata, rddata_afifo_rdata;
logic tx_sipo_valid_li;
logic [ui_mask_width_lp+ui_data_width_p-1:0] tx_sipo_data_li;
logic tx_sipo_ready_lo;
logic [ui_burst_length_lp-1:0] tx_sipo_valid_lo;
logic [ui_burst_length_lp-1:0][ui_mask_width_lp+ui_data_width_p-1:0] tx_sipo_data_lo;
logic [$clog2(ui_burst_length_lp):0] tx_sipo_yumi_cnt_li;
logic tx_data_piso_valid_li;
logic [dfi_burst_length_lp-1:0][dfi_data_width_p-1:0] tx_data_piso_data_li;
logic tx_data_piso_ready_lo;
logic tx_data_piso_valid_lo;
logic [dfi_data_width_p-1:0] tx_data_piso_data_lo;
logic tx_data_piso_yumi_li;
logic tx_mask_piso_valid_li;
logic [dfi_burst_length_lp-1:0][dfi_mask_width_lp-1:0] tx_mask_piso_data_li;
logic tx_mask_piso_ready_lo;
logic tx_mask_piso_valid_lo;
logic [dfi_mask_width_lp-1:0] tx_mask_piso_data_lo;
logic tx_mask_piso_yumi_li;
logic [(dfi_data_width_p+dfi_mask_width_lp)*dfi_burst_length_lp-1:0] tx_data_mask;
logic [dfi_data_width_p*dfi_burst_length_lp-1:0] tx_data;
logic [dfi_mask_width_lp*dfi_burst_length_lp-1:0] tx_mask;
logic rx_piso_valid_li;
logic [ui_burst_length_lp-1:0][ui_data_width_p-1:0] rx_piso_data_li;
logic rx_piso_ready_lo;
logic rx_piso_valid_lo;
logic [ui_data_width_p-1:0] rx_piso_data_lo;
logic rx_piso_yumi_li;
logic rx_sipo_valid_li;
logic [dfi_data_width_p-1:0] rx_sipo_data_li;
logic rx_sipo_ready_lo;
logic [dfi_burst_length_lp-1:0] rx_sipo_valid_lo;
logic [dfi_burst_length_lp-1:0][dfi_data_width_p-1:0] rx_sipo_data_lo;
logic [$clog2(dfi_burst_length_lp):0] rx_sipo_yumi_cnt_li;
logic [dfi_data_width_p*dfi_burst_length_lp-1:0] rx_data;
logic [$clog2(cmd_afifo_depth_p):0] rd_credit;
logic [31:0] row_col_addr;
logic [15:0] row_addr, col_addr;
logic [2:0] bank_addr;
logic ap;
logic [7:0] cmd_tick;
logic [7:0] cmd_act_tick;
logic [7:0] cmd_wr_tick, cmd_rd_tick;
logic cwd_valid;
logic [7:0] cwd_tick;
logic wburst_valid;
logic [7:0] wburst_tick;
logic cas_valid;
logic [7:0] cas_tick;
logic [7:0] rburst_tick;
state cstate, nstate;
dfi_cmd_e c_cmd, n_cmd;
logic shoot;
logic [7:0] open_bank;
logic [15:0] open_row [0:7];
logic push;
logic [15:0] init_tick;
logic init_done;
logic [15:0] ref_tick;
logic [1:0] refr_tick;
logic refr_req;
logic refr_ack;
logic [1:0] ldst_tick;
logic [15:0] tick_refi;
logic [3:0] tick_mrd;
logic [3:0] tick_rfc;
logic [3:0] tick_rc;
logic [3:0] tick_rp;
logic [3:0] tick_ras;
logic [3:0] tick_rrd;
logic [3:0] tick_rcd;
logic [3:0] tick_wr;
logic [3:0] tick_wtr;
logic [3:0] tick_rtp;
logic [3:0] tick_cas;
assign app_ref_ack_o = app_ref_req_i & ~app_wdf_end_i;
assign app_zq_ack_o = app_zq_req_i;
assign app_sr_active_o = app_sr_req_i;
always_ff @(posedge ui_clk_i) begin
if(ui_clk_sync_rst_i)
rd_credit <= cmd_afifo_depth_p;
else if(app_en_i && (app_cmd_i == RD || app_cmd_i == RP) && app_rdy_o) begin
if(!(app_rd_data_valid_o && app_rd_data_end_o))
rd_credit <= rd_credit - 1;
end
else if(app_rd_data_valid_o && app_rd_data_end_o)
rd_credit <= rd_credit + 1;
end
assign app_rdy_o = ~cmd_afifo_wfull & |rd_credit;
assign cmd_afifo_wclk = ui_clk_i;
assign cmd_afifo_wrst = ui_clk_sync_rst_i;
assign cmd_afifo_winc = app_en_i & app_rdy_o;
assign cmd_afifo_wdata.cmd = app_cmd_i;
assign cmd_afifo_wdata.addr = app_addr_i;
assign cmd_afifo_rclk = dfi_clk_i;
assign cmd_afifo_rrst = dfi_clk_sync_rst_i;
assign cmd_afifo_rinc = cmd_afifo_rvalid & cmd_sfifo_ready & (cstate == LDST && ldst_tick == 0);
bsg_async_fifo #
(.width_p ( $bits(cmd_afifo_wdata) )
,.lg_size_p ( $clog2(cmd_afifo_depth_p) ))
cmd_afifo
(.r_data_o ( cmd_afifo_rdata )
,.w_full_o ( cmd_afifo_wfull )
,.r_valid_o ( cmd_afifo_rvalid )
,.w_data_i ( cmd_afifo_wdata )
,.w_enq_i ( cmd_afifo_winc )
,.w_clk_i ( cmd_afifo_wclk )
,.w_reset_i ( cmd_afifo_wrst )
,.r_deq_i ( cmd_afifo_rinc )
,.r_clk_i ( cmd_afifo_rclk )
,.r_reset_i ( cmd_afifo_rrst ));
assign wrdata_afifo_wclk = ui_clk_i;
assign wrdata_afifo_wrst = ui_clk_sync_rst_i;
assign wrdata_afifo_winc = app_wdf_wren_i & ~wrdata_afifo_wfull;
assign wrdata_afifo_wdata = {app_wdf_mask_i,app_wdf_data_i};
assign wrdata_afifo_rclk = dfi_clk_i;
assign wrdata_afifo_rrst = dfi_clk_sync_rst_i;
assign wrdata_afifo_rinc = tx_sipo_ready_lo & wrdata_afifo_rvalid;
assign app_wdf_rdy_o = ~wrdata_afifo_wfull;
bsg_async_fifo #
(.width_p ( ui_data_width_p+ui_mask_width_lp )
,.lg_size_p ( $clog2(cmd_afifo_depth_p*ui_burst_length_lp) ))
wrdata_afifo
(.r_data_o ( wrdata_afifo_rdata )
,.w_full_o ( wrdata_afifo_wfull )
,.r_valid_o ( wrdata_afifo_rvalid )
,.w_data_i ( wrdata_afifo_wdata )
,.w_enq_i ( wrdata_afifo_winc )
,.w_clk_i ( wrdata_afifo_wclk )
,.w_reset_i ( wrdata_afifo_wrst )
,.r_deq_i ( wrdata_afifo_rinc )
,.r_clk_i ( wrdata_afifo_rclk )
,.r_reset_i ( wrdata_afifo_rrst ));
assign tx_sipo_valid_li = wrdata_afifo_rvalid;
assign tx_sipo_data_li = wrdata_afifo_rdata;
assign tx_sipo_yumi_cnt_li = ($clog2(ui_burst_length_lp)+1)'((shoot&&cmd_sfifo_rdata[23:20]==WRITE)? ui_burst_length_lp: 0);
bsg_serial_in_parallel_out #
(.width_p ( ui_data_width_p+ui_mask_width_lp )
,.els_p ( ui_burst_length_lp ))
tx_sipo
(.clk_i ( dfi_clk_i )
,.reset_i ( dfi_clk_sync_rst_i )
,.valid_i ( tx_sipo_valid_li )
,.data_i ( tx_sipo_data_li )
,.ready_o ( tx_sipo_ready_lo )
,.valid_o ( tx_sipo_valid_lo )
,.data_o ( tx_sipo_data_lo )
,.yumi_cnt_i ( tx_sipo_yumi_cnt_li ));
assign row_col_addr = ((cmd_afifo_rdata.addr >> (dmc_p_i.bank_pos + dmc_p_i.bank_width)) << dmc_p_i.bank_pos) | (((1 << dmc_p_i.bank_pos) - 1) & cmd_afifo_rdata.addr);
assign col_addr = 16'(((1 << dmc_p_i.col_width) - 1) & row_col_addr[ui_addr_width_p-1:0]);
assign row_addr = 16'(((1 << dmc_p_i.row_width) - 1) & (row_col_addr >> dmc_p_i.col_width));
assign bank_addr = 3'(((1 << dmc_p_i.bank_width) - 1) & (cmd_afifo_rdata.addr >> dmc_p_i.bank_pos));
assign ap = cmd_afifo_rdata.cmd[1];
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
init_calib_complete_o <= 0;
else if(init_done)
init_calib_complete_o <= 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
init_tick <= 0;
else if(cstate == IDLE && nstate == INIT)
init_tick <= dmc_p_i.init_cycles;
else if(cstate == INIT && init_tick != 0 && push)
init_tick <= init_tick - 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
init_done <= 0;
else if(cstate == INIT && nstate == IDLE)
init_done <= 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
ref_tick <= 0;
else if(init_done) begin
if(ref_tick == dmc_p_i.trefi)
ref_tick <= 0;
else if(!refr_req)
ref_tick <= ref_tick + 1;
end
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
refr_req <= 0;
else if(init_done) begin
if(refr_ack)
refr_req <= 0;
else if(ref_tick == dmc_p_i.trefi)
refr_req <= 1;
end
end
assign refr_ack = (cstate == REFR) & push & (refr_tick == 0);
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
refr_tick <= 0;
else if(cstate == IDLE && nstate == REFR) begin
if(|open_bank)
refr_tick <= 1;
else
refr_tick <= 0;
end
else if(cstate == REFR && refr_tick != 0 && push)
refr_tick <= refr_tick - 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
ldst_tick <= 0;
else if(cstate == IDLE && nstate == LDST) begin
if(open_bank[bank_addr] && open_row[bank_addr] == row_addr)
ldst_tick <= 0;
else if(open_bank[bank_addr])
ldst_tick <= 2;
else
ldst_tick <= 1;
end
else if(cstate == LDST && ldst_tick != 0 && push)
ldst_tick <= ldst_tick - 1;
end
always_comb begin
push = 1'b0;
cmd_sfifo_wdata = {$bits(cmd_sfifo_wdata){1'b1}};
case(cstate)
INIT: begin
push = cmd_sfifo_ready;
case(init_tick)
'd4: begin cmd_sfifo_wdata.cmd = PRE; cmd_sfifo_wdata.addr = 16'h400; end
'd3: begin cmd_sfifo_wdata.cmd = REF; cmd_sfifo_wdata.addr = 16'h0; end
'd2: begin cmd_sfifo_wdata.cmd = REF; cmd_sfifo_wdata.addr = 16'h0; end
'd1: begin cmd_sfifo_wdata.cmd = LMR; cmd_sfifo_wdata.addr = {8'h0, dmc_p_i.tcas, 4'($clog2(dfi_burst_length_lp << 1))}; cmd_sfifo_wdata.ba = 4'h0; end
'd0: begin cmd_sfifo_wdata.cmd = LMR; cmd_sfifo_wdata.addr = 16'h0; cmd_sfifo_wdata.ba = 4'h2; end
default: cmd_sfifo_wdata.cmd = DESELECT;
endcase
end
REFR: begin
push = cmd_sfifo_ready;
case(refr_tick)
'd1: begin cmd_sfifo_wdata.cmd = PRE; cmd_sfifo_wdata.addr = 16'h400; end
'd0: begin cmd_sfifo_wdata.cmd = REF; end
endcase
end
LDST: begin
push = cmd_sfifo_ready;
case(ldst_tick)
'd2: begin cmd_sfifo_wdata.cmd = PRE; cmd_sfifo_wdata.ba = bank_addr; cmd_sfifo_wdata.addr = open_row[bank_addr]; end
'd1: begin cmd_sfifo_wdata.cmd = ACT; cmd_sfifo_wdata.ba = bank_addr; cmd_sfifo_wdata.addr = row_addr; end
'd0: begin
cmd_sfifo_wdata.ba = bank_addr;
cmd_sfifo_wdata.addr = {col_addr[14:10], ap, col_addr[9:0]};
if(cmd_afifo_rdata.cmd[0])
cmd_sfifo_wdata.cmd = READ;
else
cmd_sfifo_wdata.cmd = WRITE;
end
endcase
end
endcase
end
always_comb begin
nstate = IDLE;
case(cstate)
IDLE: if(!init_done) nstate = INIT;
else if(refr_req) nstate = REFR;
else if(cmd_afifo_rvalid) nstate = LDST;
else nstate = cstate;
INIT: if(init_tick == 0 && push) nstate = IDLE;
else nstate = cstate;
REFR: if(refr_tick == 0 && push) nstate = IDLE;
else nstate = cstate;
LDST: if(ldst_tick == 0 && push) nstate = IDLE;
else nstate = cstate;
default: nstate = IDLE;
endcase
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
cstate <= IDLE;
else
cstate <= nstate;
end
assign cmd_sfifo_winc = push;
assign cmd_sfifo_rinc = shoot;
bsg_fifo_1r1w_small #
(.width_p ( $bits(cmd_sfifo_wdata) )
,.els_p ( cmd_sfifo_depth_p )
,.ready_THEN_valid_p ( 1 ))
cmd_sfifo
(.clk_i ( dfi_clk_i )
,.reset_i ( dfi_clk_sync_rst_i )
,.v_i ( cmd_sfifo_winc )
,.ready_o ( cmd_sfifo_ready )
,.data_i ( cmd_sfifo_wdata )
,.v_o ( cmd_sfifo_valid )
,.data_o ( cmd_sfifo_rdata )
,.yumi_i ( cmd_sfifo_rinc ));
always_comb begin
if(cmd_sfifo_valid)
case(c_cmd)
LMR: shoot = cmd_tick >= dmc_p_i.tmrd;
REF: shoot = cmd_tick >= dmc_p_i.trfc;
PRE: shoot = (n_cmd==ACT)? (cmd_tick >= dmc_p_i.trp && cmd_act_tick >= dmc_p_i.tras): cmd_tick >= dmc_p_i.trp;
ACT: case(n_cmd)
PRE: shoot = cmd_tick >= dmc_p_i.tras;
ACT: shoot = cmd_tick >= dmc_p_i.trrd;
WRITE: shoot = (cmd_tick >= dmc_p_i.trcd) & (cmd_rd_tick >= dmc_p_i.tcas+dfi_burst_length_lp-1) & (&tx_sipo_valid_lo);
READ: shoot = (cmd_tick >= dmc_p_i.trcd) & (cmd_wr_tick >= dmc_p_i.twtr);
default: shoot = 1'b1;
endcase
WRITE: case(n_cmd)
PRE: shoot = (cmd_tick >= dmc_p_i.twr) & (cmd_act_tick >= dmc_p_i.tras);
WRITE: shoot = (cmd_tick >= dfi_burst_length_lp-1) & (&tx_sipo_valid_lo);
READ: shoot = cmd_tick >= dmc_p_i.twtr;
ACT: shoot = (cmd_act_tick >= dmc_p_i.trc) & (cmd_tick >= dmc_p_i.twr + dmc_p_i.trp);
default: shoot = 1'b1;
endcase
READ: case(n_cmd)
PRE: shoot = (cmd_tick >= dmc_p_i.trtp) & (cmd_act_tick >= dmc_p_i.tras);
WRITE: shoot = (cmd_tick >= dmc_p_i.tcas+dfi_burst_length_lp-1) & (&tx_sipo_valid_lo);
READ: shoot = cmd_tick >= dfi_burst_length_lp-1;
ACT: shoot = (cmd_act_tick >= dmc_p_i.trc) & (cmd_tick >= dmc_p_i.trtp + dmc_p_i.trp);
default: shoot = 1'b1;
endcase
default: shoot = 1'b1;
endcase
else
shoot = 1'b0;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
cmd_tick <= 0;
else if(shoot)
cmd_tick <= 0;
else if(cmd_tick != 8'hf)
cmd_tick <= cmd_tick + 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
cmd_act_tick <= 0;
else if(shoot && n_cmd == ACT)
cmd_act_tick <= 0;
else if(cmd_act_tick != 8'hf)
cmd_act_tick <= cmd_act_tick + 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
cmd_wr_tick <= 0;
else if(shoot && n_cmd == WRITE)
cmd_wr_tick <= 0;
else if(cmd_wr_tick != 8'hf)
cmd_wr_tick <= cmd_wr_tick + 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
cmd_rd_tick <= 0;
else if(shoot && n_cmd == READ)
cmd_rd_tick <= 0;
else if(cmd_rd_tick != 8'hf)
cmd_rd_tick <= cmd_rd_tick + 1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
c_cmd <= NOP;
else if(shoot)
c_cmd <= n_cmd;
end
assign n_cmd = cmd_sfifo_rdata.cmd;
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i) begin
cwd_tick <= 0;
cwd_valid <= 0;
end
else if(shoot && cmd_sfifo_rdata[23:20] == WRITE) begin
cwd_tick <= dmc_p_i.tcas - 2;
cwd_valid <= 1;
end
else if(cwd_valid) begin
cwd_tick <= cwd_tick - 1;
if(cwd_tick == 0) cwd_valid <= 0;
end
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i) begin
wburst_tick <= 0;
wburst_valid <= 0;
end
else if((shoot && cmd_sfifo_rdata[23:20] == WRITE) ) begin
wburst_tick <= dfi_burst_length_lp-1;
wburst_valid <= 1;
end
else if(wburst_valid) begin
wburst_tick <= wburst_tick - 1;
if(wburst_tick == 0) wburst_valid <= 0;
end
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i) begin
cas_tick <= 0;
cas_valid <= 0;
end
else if(shoot && cmd_sfifo_rdata[23:20] == READ) begin
cas_tick <= dmc_p_i.tcas - 1;
cas_valid <= 1;
end
else if(cas_valid) begin
cas_tick <= cas_tick - 1;
if(cas_tick == 0) cas_valid <= 0;
end
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i) begin
rburst_tick <= 0;
dfi_rddata_en_o <= 0;
end
else if(cas_valid && cas_tick == 0) begin
rburst_tick <= dfi_burst_length_lp-1;
dfi_rddata_en_o <= 1;
end
else if(dfi_rddata_en_o) begin
rburst_tick <= rburst_tick - 1;
if(rburst_tick == 0) dfi_rddata_en_o <= 0;
end
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i) begin
dfi_bank_o <= 3'b000;
dfi_address_o <= 16'h0000;
{dfi_cs_n_o, dfi_ras_n_o, dfi_cas_n_o, dfi_we_n_o} <= 4'b1111;
dfi_reset_n_o <= 1'b1;
dfi_odt_o <= 1'b1;
end
else if(shoot)begin
dfi_bank_o <= cmd_sfifo_rdata[18:16];
dfi_address_o <= cmd_sfifo_rdata[15:0];
{dfi_cs_n_o, dfi_ras_n_o, dfi_cas_n_o, dfi_we_n_o} <= n_cmd;
end
else begin
{dfi_cs_n_o, dfi_ras_n_o, dfi_cas_n_o, dfi_we_n_o} <= 4'b1111;
dfi_reset_n_o <= 1'b1;
dfi_odt_o <= 1'b1;
end
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
dfi_cke_o <= 1'b0;
else
dfi_cke_o <= 1'b1;
end
always_ff @(posedge dfi_clk_i) begin
if(dfi_clk_sync_rst_i)
open_bank <= 0;
else if(cmd_sfifo_winc) begin
case(cmd_sfifo_wdata[23:20])
ACT: begin
open_bank[cmd_sfifo_wdata[18:16]] <= 1'b1;
open_row[cmd_sfifo_wdata[18:16]] <= cmd_sfifo_wdata[15:0];
end
WRITE,
READ: open_bank[cmd_sfifo_wdata[18:16]] <= ~ap;
PRE: begin
if(cmd_sfifo_wdata[10])
open_bank <= 0;
else
open_bank[cmd_sfifo_wdata[18:16]] <= 1'b0;
end
endcase
end
end
for(k=0;k<ui_burst_length_lp;k++) begin: tx_flatten
assign tx_data[k*ui_data_width_p+:ui_data_width_p] = tx_sipo_data_lo[k][0+:ui_data_width_p];
assign tx_mask[k*ui_mask_width_lp+:ui_mask_width_lp] = tx_sipo_data_lo[k][ui_data_width_p+:ui_mask_width_lp];
end
for(k=0;k<dfi_burst_length_lp;k++) begin: tx_make
always_ff @(posedge dfi_clk_i) begin
tx_data_piso_data_li[k] <= tx_data[k*dfi_data_width_p+:dfi_data_width_p];
tx_mask_piso_data_li[k] <= tx_mask[k*dfi_mask_width_lp+:dfi_mask_width_lp];
end
end
assign tx_data_piso_valid_li = wburst_valid;
assign tx_data_piso_yumi_li = tx_data_piso_valid_lo;
assign tx_mask_piso_valid_li = wburst_valid;
assign tx_mask_piso_yumi_li = tx_mask_piso_valid_lo;
bsg_parallel_in_serial_out #
(.width_p ( dfi_data_width_p )
,.els_p ( dfi_burst_length_lp ))
tx_data_piso
(.clk_i ( dfi_clk_i )
,.reset_i ( dfi_clk_sync_rst_i )
,.valid_i ( tx_data_piso_valid_li )
,.data_i ( tx_data_piso_data_li )
,.ready_and_o ( tx_data_piso_ready_lo )
,.valid_o ( tx_data_piso_valid_lo )
,.data_o ( tx_data_piso_data_lo )
,.yumi_i ( tx_data_piso_yumi_li ));
bsg_parallel_in_serial_out #
(.width_p ( dfi_mask_width_lp )
,.els_p ( dfi_burst_length_lp ))
tx_mask_piso
(.clk_i ( dfi_clk_i )
,.reset_i ( dfi_clk_sync_rst_i )
,.valid_i ( tx_mask_piso_valid_li )
,.data_i ( tx_mask_piso_data_li )
,.ready_and_o ( tx_mask_piso_ready_lo )
,.valid_o ( tx_mask_piso_valid_lo )
,.data_o ( tx_mask_piso_data_lo )
,.yumi_i ( tx_mask_piso_yumi_li ));
assign dfi_wrdata_o = tx_data_piso_data_lo;
assign dfi_wrdata_en_o = tx_data_piso_valid_lo;
assign dfi_wrdata_mask_o = tx_mask_piso_data_lo;
assign rddata_afifo_wclk = dfi_clk_i;
assign rddata_afifo_wrst = dfi_clk_sync_rst_i;
assign rddata_afifo_winc = dfi_rddata_valid_i;
assign rddata_afifo_wdata = dfi_rddata_i;
assign rddata_afifo_rclk = ui_clk_i;
assign rddata_afifo_rrst = ui_clk_sync_rst_i;
assign rddata_afifo_rinc = rx_sipo_ready_lo && rddata_afifo_rvalid;
bsg_async_fifo #
(.width_p ( dfi_data_width_p )
,.lg_size_p ( $clog2(cmd_afifo_depth_p*dfi_burst_length_lp) ))
rddata_afifo
(.r_data_o ( rddata_afifo_rdata )
,.w_full_o ( rddata_afifo_wfull )
,.r_valid_o ( rddata_afifo_rvalid )
,.w_data_i ( rddata_afifo_wdata )
,.w_enq_i ( rddata_afifo_winc )
,.w_clk_i ( rddata_afifo_wclk )
,.w_reset_i ( rddata_afifo_wrst )
,.r_deq_i ( rddata_afifo_rinc )
,.r_clk_i ( rddata_afifo_rclk )
,.r_reset_i ( rddata_afifo_rrst ));
assign rx_sipo_valid_li = rddata_afifo_rvalid;
assign rx_sipo_data_li = rddata_afifo_rdata;
assign rx_sipo_yumi_cnt_li = ($clog2(dfi_burst_length_lp)+1)'(&rx_sipo_valid_lo? dfi_burst_length_lp: 0);
bsg_serial_in_parallel_out #
(.width_p ( dfi_data_width_p )
,.els_p ( dfi_burst_length_lp ))
rx_sipo
(.clk_i ( ui_clk_i )
,.reset_i ( ui_clk_sync_rst_i )
,.valid_i ( rx_sipo_valid_li )
,.data_i ( rx_sipo_data_li )
,.ready_o ( rx_sipo_ready_lo )
,.valid_o ( rx_sipo_valid_lo )
,.data_o ( rx_sipo_data_lo )
,.yumi_cnt_i ( rx_sipo_yumi_cnt_li ));
for(k=0;k<dfi_burst_length_lp;k++) begin: rx_flatten
assign rx_data[k*dfi_data_width_p+:dfi_data_width_p] = rx_sipo_data_lo[k];
end
for(k=0;k<ui_burst_length_lp;k++) begin: rx_make
assign rx_piso_data_li[k] = rx_data[k*ui_data_width_p+:ui_data_width_p];
end
assign rx_piso_valid_li = &rx_sipo_valid_lo;
assign rx_piso_yumi_li = app_rd_data_valid_o;
bsg_parallel_in_serial_out #
(.width_p ( ui_data_width_p )
,.els_p ( ui_burst_length_lp ))
rx_piso
(.clk_i ( ui_clk_i )
,.reset_i ( ui_clk_sync_rst_i )
,.valid_i ( rx_piso_valid_li )
,.data_i ( rx_piso_data_li )
,.ready_and_o ( rx_piso_ready_lo )
,.valid_o ( rx_piso_valid_lo )
,.data_o ( rx_piso_data_lo )
,.yumi_i ( rx_piso_yumi_li ));
logic [7:0] rd_cnt;
always_ff @(posedge ui_clk_i) begin
if(ui_clk_sync_rst_i)
rd_cnt <= 0;
else if(rx_piso_yumi_li) begin
if(rd_cnt == ui_burst_length_lp - 1)
rd_cnt <= '0;
else
rd_cnt <= rd_cnt + 1;
end
end
assign app_rd_data_valid_o = rx_piso_valid_lo;
assign app_rd_data_o = rx_piso_data_lo;
assign app_rd_data_end_o = rx_piso_valid_lo && (rd_cnt == ui_burst_length_lp - 1);
endmodule
`BSG_ABSTRACT_MODULE(bsg_dmc_controller)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_FUNCTIONAL_V |
//b12015 ROHIT PATIYAL
`include "ALU/Arith/UnSigned/UDivider/BasicCell.v"
`include "ALU/Arith/UnSigned/UDivider/stepof32.v"
`include "ALU/Arith/UnSigned/UDivider/laststepof32.v"
//`include "ALU/mux2to1.v" //`
module UDivider(Quotient, Remainder, Dividend, Divisor);
output [31:0] Quotient;
output [31:0] Remainder;
input [31:0] Divisor;
input [31:0] Dividend;
wire [31:0] TR[0:32];
wire cin;
wire cout;
wire garbage;
stepof32 myStep1(TR[0], garbage, 0, Dividend[31], Divisor, 1);
stepof32 myStep2(TR[1], Quotient[31], TR[0], Dividend[30], Divisor, garbage);
stepof32 myStep3(TR[2], Quotient[30], TR[1], Dividend[29], Divisor, Quotient[31]);
stepof32 myStep4(TR[3], Quotient[29], TR[2], Dividend[28], Divisor, Quotient[30]);
stepof32 myStep5(TR[4], Quotient[28], TR[3], Dividend[27], Divisor, Quotient[29]);
stepof32 myStep6(TR[5], Quotient[27], TR[4], Dividend[26], Divisor, Quotient[28]);
stepof32 myStep7(TR[6], Quotient[26], TR[5], Dividend[25], Divisor, Quotient[27]);
stepof32 myStep8(TR[7], Quotient[25], TR[6], Dividend[24], Divisor, Quotient[26]);
stepof32 myStep9(TR[8], Quotient[24], TR[7], Dividend[23], Divisor, Quotient[25]);
stepof32 myStep10(TR[9], Quotient[23], TR[8], Dividend[22], Divisor, Quotient[24]);
stepof32 myStep11(TR[10], Quotient[22], TR[9], Dividend[21], Divisor, Quotient[23]);
stepof32 myStep12(TR[11], Quotient[21], TR[10], Dividend[20], Divisor, Quotient[22]);
stepof32 myStep13(TR[12], Quotient[20], TR[11], Dividend[19], Divisor, Quotient[21]);
stepof32 myStep14(TR[13], Quotient[19], TR[12], Dividend[18], Divisor, Quotient[20]);
stepof32 myStep15(TR[14], Quotient[18], TR[13], Dividend[17], Divisor, Quotient[19]);
stepof32 myStep16(TR[15], Quotient[17], TR[14], Dividend[16], Divisor, Quotient[18]);
stepof32 myStep17(TR[16], Quotient[16], TR[15], Dividend[15], Divisor, Quotient[17]);
stepof32 myStep18(TR[17], Quotient[15], TR[16], Dividend[14], Divisor, Quotient[16]);
stepof32 myStep19(TR[18], Quotient[14], TR[17], Dividend[13], Divisor, Quotient[15]);
stepof32 myStep20(TR[19], Quotient[13], TR[18], Dividend[12], Divisor, Quotient[14]);
stepof32 myStep21(TR[20], Quotient[12], TR[19], Dividend[11], Divisor, Quotient[13]);
stepof32 myStep22(TR[21], Quotient[11], TR[20], Dividend[10], Divisor, Quotient[12]);
stepof32 myStep23(TR[22], Quotient[10], TR[21], Dividend[9], Divisor, Quotient[11]);
stepof32 myStep24(TR[23], Quotient[9], TR[22], Dividend[8], Divisor, Quotient[10]);
stepof32 myStep25(TR[24], Quotient[8], TR[23], Dividend[7], Divisor, Quotient[9]);
stepof32 myStep26(TR[25], Quotient[7], TR[24], Dividend[6], Divisor, Quotient[8]);
stepof32 myStep27(TR[26], Quotient[6], TR[25], Dividend[5], Divisor, Quotient[7]);
stepof32 myStep28(TR[27], Quotient[5], TR[26], Dividend[4], Divisor, Quotient[6]);
stepof32 myStep29(TR[28], Quotient[4], TR[27], Dividend[3], Divisor, Quotient[5]);
stepof32 myStep30(TR[29], Quotient[3], TR[28], Dividend[2], Divisor, Quotient[4]);
stepof32 myStep31(TR[30], Quotient[2], TR[29], Dividend[1], Divisor, Quotient[3]);
stepof32 myStep32(TR[31], Quotient[1], TR[30], Dividend[0], Divisor, Quotient[2]);
laststepof32 myStep33(Remainder,Quotient[0],TR[31],Divisor,Quotient[1]); //Includes a step similar to stepof32
//$display ("HEllo");
endmodule
|
// Crazy Small CPU version 2
// (c) 2017 Warren Toomey, GPL3
// Just a few notes on the Verilog implementation of the CSCv2.
//
// Firstly, the ram.v component waits a clock cycle before it
// outputs when the address changes. So we give it a clock signal
// twice the frequency of the main CPU clock signal.
//
// The UART is now separate from the CPU, but we output the TX
// control line which is still the OR of Aload, Bload and the clock.
//
// Because the high impedance logic state doesn't get synthesised well,
// there is a new multiplexer, databus. This chooses either the RAM
// output or the ALU output based on the RAMwrite control line.
//
// Apart from the above, everything else is exactly the same as the
// version made from 7400-style chips.
`include "register.v"
`include "alu.v"
`include "botrom.v"
`include "pc.v"
`include "ram.v"
`include "toprom.v"
module cscv2 (
input dblclk, // Clock signal
output TX, // UART control line, active low
output [3:0] Aval, // Output of A register
output [3:0] Bval, // Output of B register
// Outputs of other internal data/control lines.
// Used for debugging and diagnostics
output [7:0] PCval,
output RAMwrite,
output [7:0] address,
output [3:0] Flagsval,
output [2:0] ALUop,
output [3:0] ALUresult,
output [3:0] RAMresult,
output [3:0] databus,
output Aload,
output Bload,
output Asel
);
// Half speed clock, i.e. half the speed of the RAM clock
reg clk= 0;
// Control Wires not provided as outputs
wire PCincr;
// Register outputs
wire Cin;
assign Cin= Flagsval[0];
// Lower 4 bits of the address
wire [3:0] addrlow;
assign addrlow= address[3:0];
// ALU output
wire [3:0] ALUflags;
// Register multiplexer
wire [3:0] regmux;
assign regmux= (Asel) ? databus : addrlow;
// New multiplexer to avoid high-Z logic
assign databus= (RAMwrite) ? RAMresult : ALUresult;
// UART control line
assign TX = Aload | Bload | clk;
// Components
register A(clk, Aload, regmux, Aval);
register B(clk, Bload, regmux, Bval);
register Flags(clk, RAMwrite, ALUflags, Flagsval);
pc PC(clk, PCincr, address, PCval);
alu ALU(Aval, Bval, ALUop, Cin, Asel, ALUresult, ALUflags);
toprom TOP(PCval, Flagsval, ALUop, PCincr, Aload, Bload, Asel, RAMwrite);
botrom BOT(PCval, Flagsval, address);
ram RAM(dblclk, address, ALUresult, RAMresult, RAMwrite);
// Calculate the CPU clock from the RAM clock
always @(posedge dblclk)
clk <= ~clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:31:46 04/05/2017
// Design Name:
// Module Name: DSP48E_1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DSPCalcModule(
input signed [20:0] charge_in,
input signed [16:0] signal_in,
input delay_en,
input clk,
input store_strb,
input fb_en,
output reg signed [14:0] pout,
input bunch_strb,
output reg DSPoflow,
// input signed [12:0] banana_corr,
output reg fb_cond,
output reg dac_clk
// input fb_en
);
(* equivalent_register_removal = "no"*) reg [7:0] j;
reg signed [37:0] DSPtemp;
//reg signed [14:0] DSPtemp2;
reg signed [14:0] delayed;
//initial DSPout=0;
reg signed [37:0] DSPout;
//reg DSPoflow=1'b0;
reg signed [20:0] chargeA = 21'd0;
always @ (posedge clk) begin
chargeA <= charge_in;
DSPtemp <= chargeA*signal_in;
//DSPtemp2=DSPtemp[24:12]; // Doesnt help timing!!!
DSPout <= DSPtemp+{delayed, 12'b0}; // Remove 4096 factor added for LUT // delayed 25 bits,
pout<=DSPout[26:12];
DSPoflow<=(~&DSPout[37:26] && ~&(~DSPout[37:26]));
end
//reg signed [10:0] banana_fract;
// ***** Clk Counter after strobe *****
// No. of samples after bunch strb
always @ (posedge clk) begin
if (~store_strb) begin
j<=8;
end
else if (bunch_strb) begin j<=0;
//banana_fract<=banana_corr[12:2]; /// Bring in as 13 bit and pad with zeros to 25 bits
end
else if (~bunch_strb) begin
j<=j+1;
end
//else j<=10;
end
//reg [47:0] banana_corr_48=0;
// If more than two bunches multiplex to add banana correction
//k1_b2_offset
reg [14:0] delayed_a;
always @ (posedge clk) begin
delayed<=delayed_a; // add banana here
if (~store_strb) begin
delayed_a<=0;
end
else if (delay_en==1) begin
if (j==6) delayed_a<=pout;
end
end
//reg fb_cond2;
always @ (posedge clk) begin
if (fb_en) begin
if (j==2||j==3) fb_cond<=1;
else fb_cond<=0;
end
else fb_cond<=0;
end
(* equivalent_register_removal = "no"*) reg delay_store_strb;
reg clr_dac;
reg delay_clr_dac;
always @ (posedge clk) begin
if (fb_en) begin
if (j==6||j==7||clr_dac==1||delay_clr_dac==1) dac_clk<=1;
else dac_clk<=0;
end
else dac_clk<=0;
end
always @(posedge clk) begin
delay_store_strb<=store_strb;
delay_clr_dac<=clr_dac;
if ((delay_store_strb==1)&(store_strb==0)) clr_dac<=1;
else clr_dac<=0;
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage3.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module stage3 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/phd.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/phd.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/phd.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:14:36 05/31/2016
// Design Name:
// Module Name: Contador_AD_minutos
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD_Minutos(
input rst,
input [7:0]estado,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 6;
parameter X = 59;
always @(posedge clk)
if (rst)
Cuenta <= 0;
else if (en == 2'd1 && (estado == 8'h6C || estado == 8'h75))
begin
if (Cambio == 8'h73 && got_data)
begin
if (Cuenta == X)
Cuenta <= 0;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 0)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else
Cuenta <= Cuenta;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_PP_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_PP_V |
/*
########################################################################
ELINK CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
module erx_cfg (/*AUTOARG*/
// Outputs
mi_dout, rx_enable, mmu_enable, remap_mode, remap_base,
remap_pattern, remap_sel, timer_cfg,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, gpio_datain, rx_status
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6; // 32 registers for now
parameter GROUP = 4'h0;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; // ecfg registers reset only by "hard reset"
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_en;
input mi_we; // single we, must write 32 bit words
input [14:0] mi_addr; // complete physical address (no shifting!)
input [31:0] mi_din;
output [31:0] mi_dout;
/*****************************/
/*CONFIG SIGNALS */
/*****************************/
//rx
output rx_enable; // enable signal for rx
output mmu_enable; // enables MMU on rx path (static)
input [8:0] gpio_datain; // frame and data inputs (static)
input [15:0] rx_status; // etx status signals
output [1:0] remap_mode; // remap mode (static)
output [31:0] remap_base; // base for dynamic remap (static)
output [11:0] remap_pattern; // patter for static remap (static)
output [11:0] remap_sel; // selects for static remap (static)
output [1:0] timer_cfg; // timeout config (00=off) (static)
/*------------------------CODE BODY---------------------------------------*/
//registers
reg [31:0] ecfg_rx_reg;
reg [31:0] ecfg_offset_reg;
reg [8:0] ecfg_gpio_reg;
reg [2:0] ecfg_rx_status_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_rx_write;
wire ecfg_base_write;
wire ecfg_remap_write;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_CFG);
assign ecfg_base_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_OFFSET);
//###########################
//# RXCFG
//###########################
always @ (posedge clk)
if(reset)
ecfg_rx_reg[31:0] <= 'b0;
else if (ecfg_rx_write)
ecfg_rx_reg[31:0] <= mi_din[31:0];
assign rx_enable = 1'b1;//is there any good reason turn RX off?
assign mmu_enable = ecfg_rx_reg[1];
assign remap_mode[1:0] = ecfg_rx_reg[3:2];
assign remap_sel[11:0] = ecfg_rx_reg[15:4];
assign remap_pattern[11:0] = ecfg_rx_reg[27:16];
assign timer_cfg[1:0] = ecfg_rx_reg[29:28];
//###########################
//# DATAIN
//###########################
always @ (posedge clk)
ecfg_gpio_reg[8:0] <= gpio_datain[8:0];
//###########################1
//# DEBUG
//###########################
always @ (posedge clk)
if(reset)
ecfg_rx_status_reg[2:0] <= 'b0;
else
ecfg_rx_status_reg[2:0] <= ecfg_rx_status_reg[2:0] | rx_status[2:0];
//###########################1
//# DYNAMIC REMAP BASE
//###########################
always @ (posedge clk)
if (ecfg_base_write)
ecfg_offset_reg[31:0] <= mi_din[31:0];
assign remap_base[31:0] = ecfg_offset_reg[31:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ERX_CFG: mi_dout[31:0] <= {ecfg_rx_reg[31:0]};
`ERX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_gpio_reg[8:0]};
`ERX_STATUS: mi_dout[31:0] <= {16'b0, rx_status[15:3],ecfg_rx_status_reg[2:0]};
`ERX_OFFSET: mi_dout[31:0] <= {ecfg_offset_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_rx
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_TB_V
`define SKY130_FD_SC_HD__XNOR2_TB_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xnor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__XNOR3_PP_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:12 10/28/2015
// Design Name:
// Module Name: UART_uart_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_uart(
input clock,
input uart_rx,
input uart_reset,
input readFlag,
input writeFlag,
input [7:0]dataToSend,
output [7:0]receivedData,
output dataAvailable,
output uart_tx
);
wire baud_rate_rx,
baud_rate_tx,
uart_rx_done,
uart_tx_done,
uart_start_tx,
send_next_tx,
uart_empty_flag_rx,
uart_not_empty_flag_rx,
uart_empty_flag_tx,
uart_not_empty_flag_tx;
// uart_full_flag_rx,
// uart_full_flag_tx;
wire [7:0] uart_data_rx;
wire [7:0] uart_data_tx;
wire [7:0] uart_data;
localparam uart_COUNT = 651;
UART_baud_rate_generator #(.COUNT(uart_COUNT)) rx_baud_rate(
.clock(clock),
.baud_rate(baud_rate_rx)
);
UART_rx receptor(
.rx(uart_rx),
.s_tick(baud_rate_rx),
.clock(clock),
.reset(uart_reset),
.rx_done(uart_rx_done),
.d_out(uart_data_rx)
);
UART_fifo_interface fifo_rx(
.clock(clock),
.reset(uart_reset),
.write_flag(uart_rx_done),
.read_next(readFlag),
.data_in(uart_data_rx),
.data_out(receivedData),
.empty_flag(uart_empty_flag_rx)
// .full_flag(uart_full_flag_rx)
);
UART_baud_rate_generator #(.COUNT(uart_COUNT*16)) tx_baud_rate(
.clock(clock),
.baud_rate(baud_rate_tx)
);
UART_tx transmisor(
.clock(clock),
.reset(uart_reset),
.s_tick(baud_rate_tx),
.tx_start(uart_start_tx),
.data_in(uart_data_tx),
.tx(uart_tx),
.tx_done(uart_tx_done)
);
UART_fifo_interface #(.bits_depth(8))fifo_tx(
.clock(clock),
.reset(uart_reset),
.write_flag(writeFlag),
.read_next(send_next_tx),
.data_in(dataToSend),
.data_out(uart_data_tx),
.empty_flag(uart_empty_flag_tx)
// .full_flag(uart_full_flag_tx)
);
assign send_next_tx = uart_not_empty_flag_tx && uart_tx_done;
assign uart_start_tx = uart_empty_flag_tx;
assign uart_not_empty_flag_tx = ~uart_empty_flag_tx;
assign dataAvailable = ~uart_empty_flag_rx;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:32:12 01/08/2011
// Design Name:
// Module Name: rtc_srtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rtc (
input clkin,
input pgm_we,
input [55:0] rtc_data_in,
input we1,
input [59:0] rtc_data_in1,
output [59:0] rtc_data
);
reg [59:0] rtc_data_r;
reg [59:0] rtc_data_out_r;
reg [1:0] pgm_we_sreg;
always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01);
reg [2:0] we1_sreg;
always @(posedge clkin) we1_sreg <= {we1_sreg[1:0], we1};
wire we1_rising = (we1_sreg[2:1] == 2'b01);
reg [31:0] tick_cnt;
always @(posedge clkin) begin
tick_cnt <= tick_cnt + 1;
if((tick_cnt == 24000000) || pgm_we_rising) tick_cnt <= 0;
end
assign rtc_data = rtc_data_out_r;
reg [31:0] rtc_state;
reg carry;
reg [3:0] dom1[11:0];
reg [3:0] dom10[11:0];
reg [3:0] month;
reg [1:0] year;
reg [4:0] dow_day;
reg [3:0] dow_month;
reg [13:0] dow_year;
reg [6:0] dow_year1;
reg [6:0] dow_year100;
reg [15:0] dow_tmp;
reg [15:0] dow_year_tmp;
parameter [31:0]
STATE_SEC1 = 32'b00000000000000000000000000000001,
STATE_SEC10 = 32'b00000000000000000000000000000010,
STATE_MIN1 = 32'b00000000000000000000000000000100,
STATE_MIN10 = 32'b00000000000000000000000000001000,
STATE_HOUR1 = 32'b00000000000000000000000000010000,
STATE_HOUR10 = 32'b00000000000000000000000000100000,
STATE_DAY1 = 32'b00000000000000000000000001000000,
STATE_DAY10 = 32'b00000000000000000000000010000000,
STATE_MON1 = 32'b00000000000000000000000100000000,
STATE_MON10 = 32'b00000000000000000000001000000000,
STATE_YEAR1 = 32'b00000000000000000000010000000000,
STATE_YEAR10 = 32'b00000000000000000000100000000000,
STATE_YEAR100 = 32'b00000000000000000001000000000000,
STATE_YEAR1000 = 32'b00000000000000000010000000000000,
STATE_DOW0_0 = 32'b00000000000000000100000000000000,
STATE_DOW0_1 = 32'b00000000000000001000000000000000,
STATE_DOW0_2 = 32'b00000000000000010000000000000000,
STATE_DOW1_0_0 = 32'b00000000000000100000000000000000,
STATE_DOW1_0_1 = 32'b00000000000001000000000000000000,
STATE_DOW1_0_2 = 32'b00000000000010000000000000000000,
STATE_DOW1_0_3 = 32'b00000000000100000000000000000000,
STATE_DOW1_0_4 = 32'b00000000001000000000000000000000,
STATE_DOW1_1_0 = 32'b00000000010000000000000000000000,
STATE_DOW1_1_1 = 32'b00000000100000000000000000000000,
STATE_DOW1_1_2 = 32'b00000001000000000000000000000000,
STATE_DOW1_1_3 = 32'b00000010000000000000000000000000,
STATE_DOW2 = 32'b00000100000000000000000000000000,
STATE_DOW3 = 32'b00001000000000000000000000000000,
STATE_DOW4 = 32'b00010000000000000000000000000000,
STATE_DOW5 = 32'b00100000000000000000000000000000,
STATE_LATCH = 32'b01000000000000000000000000000000,
STATE_IDLE = 32'b10000000000000000000000000000000;
initial begin
rtc_state = STATE_IDLE;
dom1[0] = 1; dom10[0] = 3;
dom1[1] = 8; dom10[1] = 2;
dom1[2] = 1; dom10[2] = 3;
dom1[3] = 0; dom10[3] = 3;
dom1[4] = 1; dom10[4] = 3;
dom1[5] = 0; dom10[5] = 3;
dom1[6] = 1; dom10[6] = 3;
dom1[7] = 1; dom10[7] = 3;
dom1[8] = 0; dom10[8] = 3;
dom1[9] = 1; dom10[9] = 3;
dom1[10] = 0; dom10[10] = 3;
dom1[11] = 1; dom10[11] = 3;
month = 0;
rtc_data_r = 60'h220110301000000;
tick_cnt = 0;
dow_year_tmp = 0;
end
wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00);
always @(posedge clkin) begin
if(!tick_cnt) begin
rtc_state <= STATE_SEC1;
end else begin
case (rtc_state)
STATE_SEC1:
rtc_state <= STATE_SEC10;
STATE_SEC10:
rtc_state <= STATE_MIN1;
STATE_MIN1:
rtc_state <= STATE_MIN10;
STATE_MIN10:
rtc_state <= STATE_HOUR1;
STATE_HOUR1:
rtc_state <= STATE_HOUR10;
STATE_HOUR10:
rtc_state <= STATE_DAY1;
STATE_DAY1:
rtc_state <= STATE_DAY10;
STATE_DAY10:
rtc_state <= STATE_MON1;
STATE_MON1:
rtc_state <= STATE_MON10;
STATE_MON10:
rtc_state <= STATE_YEAR1;
STATE_YEAR1:
rtc_state <= STATE_YEAR10;
STATE_YEAR10:
rtc_state <= STATE_YEAR100;
STATE_YEAR100:
rtc_state <= STATE_YEAR1000;
STATE_YEAR1000:
rtc_state <= STATE_DOW0_0;
STATE_DOW0_0:
rtc_state <= STATE_DOW0_1;
STATE_DOW0_1:
rtc_state <= STATE_DOW0_2;
STATE_DOW0_2:
if(dow_month <= 2)
rtc_state <= STATE_DOW1_0_0;
else
rtc_state <= STATE_DOW1_1_0;
STATE_DOW1_0_0:
rtc_state <= STATE_DOW1_0_1;
STATE_DOW1_0_1:
rtc_state <= STATE_DOW1_0_2;
STATE_DOW1_0_2:
rtc_state <= STATE_DOW1_0_3;
STATE_DOW1_0_3:
rtc_state <= STATE_DOW1_0_4;
STATE_DOW1_1_0:
rtc_state <= STATE_DOW1_1_1;
STATE_DOW1_1_1:
rtc_state <= STATE_DOW1_1_2;
STATE_DOW1_1_2:
rtc_state <= STATE_DOW1_1_3;
STATE_DOW1_0_4,
STATE_DOW1_1_3:
rtc_state <= STATE_DOW2;
STATE_DOW2:
rtc_state <= STATE_DOW3;
STATE_DOW3:
rtc_state <= STATE_DOW4;
STATE_DOW4:
if(dow_tmp > 13)
rtc_state <= STATE_DOW4;
else
rtc_state <= STATE_DOW5;
STATE_DOW5:
rtc_state <= STATE_LATCH;
STATE_LATCH:
rtc_state <= STATE_IDLE;
default:
rtc_state <= STATE_IDLE;
endcase
end
end
always @(posedge clkin) begin
if(pgm_we_rising) begin
rtc_data_r[55:0] <= rtc_data_in;
end else if (we1_rising) begin
rtc_data_r <= rtc_data_in1;
end else begin
case(rtc_state)
STATE_SEC1: begin
if(rtc_data_r[3:0] == 9) begin
rtc_data_r[3:0] <= 0;
carry <= 1;
end else begin
rtc_data_r[3:0] <= rtc_data_r[3:0] + 1;
carry <= 0;
end
end
STATE_SEC10: begin
if(carry) begin
if(rtc_data_r[7:4] == 5) begin
rtc_data_r[7:4] <= 0;
carry <= 1;
end else begin
rtc_data_r[7:4] <= rtc_data_r[7:4] + 1;
carry <= 0;
end
end
end
STATE_MIN1: begin
if(carry) begin
if(rtc_data_r[11:8] == 9) begin
rtc_data_r[11:8] <= 0;
carry <= 1;
end else begin
rtc_data_r[11:8] <= rtc_data_r[11:8] + 1;
carry <= 0;
end
end
end
STATE_MIN10: begin
if(carry) begin
if(rtc_data_r[15:12] == 5) begin
rtc_data_r[15:12] <= 0;
carry <= 1;
end else begin
rtc_data_r[15:12] <= rtc_data_r[15:12] + 1;
carry <= 0;
end
end
end
STATE_HOUR1: begin
if(carry) begin
if(rtc_data_r[23:20] == 2 && rtc_data_r[19:16] == 3) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else if (rtc_data_r[19:16] == 9) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else begin
rtc_data_r[19:16] <= rtc_data_r[19:16] + 1;
carry <= 0;
end
end
end
STATE_HOUR10: begin
if(carry) begin
if(rtc_data_r[23:20] == 2) begin
rtc_data_r[23:20] <= 0;
carry <= 1;
end else begin
rtc_data_r[23:20] <= rtc_data_r[23:20] + 1;
carry <= 0;
end
end
end
STATE_DAY1: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]
&& rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else if (rtc_data_r[27:24] == 9) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else begin
rtc_data_r[27:24] <= rtc_data_r[27:24] + 1;
carry <= 0;
end
end
end
STATE_DAY10: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]) begin
rtc_data_r[31:28] <= 0;
rtc_data_r[27:24] <= 1;
carry <= 1;
end else begin
rtc_data_r[31:28] <= rtc_data_r[31:28] + 1;
carry <= 0;
end
end
end
STATE_MON1: begin
if(carry) begin
if(rtc_data_r[39:36] == 1 && rtc_data_r[35:32] == 2) begin
rtc_data_r[35:32] <= 1;
carry <= 1;
end else if (rtc_data_r[35:32] == 9) begin
rtc_data_r[35:32] <= 0;
carry <= 1;
end else begin
rtc_data_r[35:32] <= rtc_data_r[35:32] + 1;
carry <= 0;
end
end
end
STATE_MON10: begin
if(carry) begin
if(rtc_data_r[39:36] == 1) begin
rtc_data_r[39:36] <= 0;
carry <= 1;
end else begin
rtc_data_r[39:36] <= rtc_data_r[39:36] + 1;
carry <= 0;
end
end
end
STATE_YEAR1: begin
month <= rtc_data_r[35:32] + (rtc_data_r[36] ? 10 : 0) - 1;
if(carry) begin
if(rtc_data_r[43:40] == 9) begin
rtc_data_r[43:40] <= 0;
carry <= 1;
end else begin
rtc_data_r[43:40] <= rtc_data_r[43:40] + 1;
carry <= 0;
end
end
end
STATE_YEAR10: begin
if(carry) begin
if(rtc_data_r[47:44] == 9) begin
rtc_data_r[47:44] <= 0;
carry <= 1;
end else begin
rtc_data_r[47:44] <= rtc_data_r[47:44] + 1;
carry <= 0;
end
end
end
STATE_YEAR100: begin
if(carry) begin
if(rtc_data_r[51:48] == 9) begin
rtc_data_r[51:48] <= 0;
carry <= 1;
end else begin
rtc_data_r[51:48] <= rtc_data_r[51:48] + 1;
carry <= 0;
end
end
end
STATE_YEAR1000: begin
if(carry) begin
if(rtc_data_r[55:52] == 9) begin
rtc_data_r[55:52] <= 0;
carry <= 1;
end else begin
rtc_data_r[55:52] <= rtc_data_r[55:52] + 1;
carry <= 0;
end
end
end
STATE_DOW0_0: begin
dow_year1 <= rtc_data_r[43:40];
dow_year100 <= rtc_data_r[51:48];
dow_month <= month + 1;
dow_day <= rtc_data_r[27:24];
end
STATE_DOW0_1: begin
dow_year1 <= dow_year1 + (rtc_data_r[47:44] << 1);
dow_year100 <= dow_year100 + (rtc_data_r[55:52] << 1);
dow_day <= dow_day + rtc_data_r[31:28] << 1;
end
STATE_DOW0_2: begin
dow_year1 <= dow_year1 + (rtc_data_r[47:44] << 3);
dow_year100 <= dow_year100 + (rtc_data_r[55:52] << 3);
dow_day <= dow_day + (rtc_data_r[31:28] << 3);
end
STATE_DOW1_0_0: begin
year <= dow_year1[1:0];
dow_month <= dow_month + 10;
dow_year <= dow_year1;
end
STATE_DOW1_0_1: begin
dow_year <= dow_year + (dow_year100 << 2);
end
STATE_DOW1_0_2: begin
dow_year <= dow_year + (dow_year100 << 5);
end
STATE_DOW1_0_3: begin
dow_year <= dow_year + (dow_year100 << 6) - 1;
end
STATE_DOW1_0_4: begin
if(dow_year1)
dow_year1 <= dow_year1 - 1;
else begin
dow_year1 <= 99;
dow_year100 <= dow_year100 - 1;
end
end
STATE_DOW1_1_0: begin
year <= dow_year1[1:0];
dow_month <= dow_month - 2;
dow_year <= dow_year1;
end
STATE_DOW1_1_1: begin
dow_year <= dow_year + (dow_year100 << 2);
end
STATE_DOW1_1_2: begin
dow_year <= dow_year + (dow_year100 << 5);
end
STATE_DOW1_1_3: begin
dow_year <= dow_year + (dow_year100 << 6);
end
STATE_DOW2: begin
dow_tmp <= (83 * dow_month);
dow_year_tmp <= dow_year
+ (dow_year >> 2)
- (dow_year100)
+ (dow_year100 >> 2);
end
STATE_DOW3: begin
dow_tmp <= (dow_tmp >> 5)
+ dow_day
+ dow_year_tmp;
//+ dow_year
//+ (dow_year >> 2)
//- (dow_year100)
//+ (dow_year100 >> 2);
end
STATE_DOW4: begin
dow_tmp <= dow_tmp - 7;
end
STATE_DOW5: begin
rtc_data_r[59:56] <= {1'b0, dow_tmp[2:0]};
end
STATE_LATCH: begin
rtc_data_out_r <= rtc_data_r;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND4B_BEHAVIORAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.15 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.12 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.11 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.10 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.8 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban ([email protected])
// Company: Flextronics Semiconductor
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_wb (clk, wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
`ifdef DATA_BUS_WIDTH_8
input [7:0] wb_dat_i; //input WISHBONE bus
output [7:0] wb_dat_o;
reg [7:0] wb_dat_o;
wire [7:0] wb_dat_i;
reg [7:0] wb_dat_is;
`else // for 32 data bus mode
input [31:0] wb_dat_i; //input WISHBONE bus
output [31:0] wb_dat_o;
reg [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
reg [31:0] wb_dat_is;
`endif // !`ifdef DATA_BUS_WIDTH_8
output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
reg [3:0] wb_sel_is;
wire [3:0] wb_sel_i;
reg wre ;// timing control signal for write or read enable
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= #1 1'b0;
wbstate <= #1 0;
wre <= #1 1'b1;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= #1 0;
wbstate <= #1 1;
wb_ack_o <= #1 1;
end else begin
wre <= #1 1;
wb_ack_o <= #1 0;
end
end
1: begin
wb_ack_o <= #1 0;
wbstate <= #1 2;
wre <= #1 0;
end
2,3: begin
wb_ack_o <= #1 0;
wbstate <= #1 0;
wre <= #1 0;
end
endcase
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= #1 0;
wb_we_is <= #1 0;
wb_cyc_is <= #1 0;
wb_stb_is <= #1 0;
wb_dat_is <= #1 0;
wb_sel_is <= #1 0;
end else begin
wb_adr_is <= #1 wb_adr_i;
wb_we_is <= #1 wb_we_i;
wb_cyc_is <= #1 wb_cyc_i;
wb_stb_is <= #1 wb_stb_i;
wb_dat_is <= #1 wb_dat_i;
wb_sel_is <= #1 wb_sel_i;
end
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 0;
else
wb_dat_o <= #1 wb_dat8_o;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
assign wb_adr_int = wb_adr_is;
`else // 32-bit bus
// put output to the correct byte in 32 bits using select line
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 0;
else if (re_o)
case (wb_sel_is)
4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
default: wb_dat_o <= #1 0;
endcase // case(wb_sel_i)
reg [1:0] wb_adr_int_lsb;
always @(wb_sel_is or wb_dat_is)
begin
case (wb_sel_is)
4'b0001 : wb_dat8_i = wb_dat_is[7:0];
4'b0010 : wb_dat8_i = wb_dat_is[15:8];
4'b0100 : wb_dat8_i = wb_dat_is[23:16];
4'b1000 : wb_dat8_i = wb_dat_is[31:24];
default : wb_dat8_i = wb_dat_is[7:0];
endcase // case(wb_sel_i)
`ifdef LITLE_ENDIAN
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h0;
4'b0010 : wb_adr_int_lsb = 2'h1;
4'b0100 : wb_adr_int_lsb = 2'h2;
4'b1000 : wb_adr_int_lsb = 2'h3;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
`else
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h3;
4'b0010 : wb_adr_int_lsb = 2'h2;
4'b0100 : wb_adr_int_lsb = 2'h1;
4'b1000 : wb_adr_int_lsb = 2'h0;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
`endif
end
assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb};
`endif // !`ifdef DATA_BUS_WIDTH_8
endmodule
|
/*
* draw lines
*
* (c) Arlet Ottens <[email protected]>
*/
module line(
input clk,
/*
* vector info:
* This module outputs the vector number, and expects to get
* the coordinates + color back on the next cycle when
* read_vector=1. If read_vector=0, the previous values must be
* maintained.
*
* (x0,y0) indicates starting point, (x1,y1) indicates end point
* top left of screen = (0,0), and y1 >= y0.
*/
output reg [9:0] vector = 0, // vector number
output read_vector, // read vector enable
input [9:0] x0, // top x coordinate
input [9:0] y0, // top y coordinate
input [9:0] x1, // vector delta y (abs)
input [9:0] y1, // vector delta x (abs)
input [15:0] col, // vector color
input last_vector, // last vector
input trigger, // start of new frame
input fifo_full,
output reg fifo_write,
output reg [15:0] fifo_data );
reg [9:0] scan_y = 0;
reg [9:0] x = 0; // line x coordinate
reg [9:0] xend = 0; // line x coordinate last pixel
reg [10:0] e = 0; // Bresenham error
reg [9:0] w = 0; // width
reg [9:0] h = 0; // height
reg [9:0] off = 0; // offset (scan_y - y0)
reg [15:0] col_1; // color
reg start_frame = 0; // start a new frame
reg start_line = 0; // start a new scanline
/*
* line drawing state machine
*/
parameter
SYNC = 2'd0, // waiting for vertical trigger
DRAW = 2'd1, // draw the lines in the scanline buffer
COPY = 2'd2; // copy the scanline to the video output
reg [2:0] state = SYNC;
reg [2:0] next = SYNC;
wire draw_done;
wire last_line = (scan_y == 479);
wire copy_done;
always @(posedge clk)
if( trigger ) start_frame <= 1;
else start_frame <= 0;
always @(posedge clk)
if( trigger | copy_done ) start_line <= 1;
else start_line <= 0;
/*
* scanline counter
*/
always @(posedge clk)
if( start_frame ) scan_y <= 0;
else if( start_line ) scan_y <= scan_y + 1;
/*
* state machine
*/
always @(posedge clk)
state <= next;
always @* begin
next = state;
case( state )
SYNC: if( trigger ) next = DRAW;
DRAW: if( draw_done ) next = COPY;
COPY: if( copy_done )
if( last_line ) next = SYNC;
else next = DRAW;
endcase
end
/*
* line drawing
*/
reg [9:0] bres_wr_vector = 0; // vector state write back
wire bres_we; // state write enable
wire span; // doing horizontal span
wire [31:0] bres_rd_data; // Bresenham read state data
wire bres_valid; // Bresenham state is valid
wire [9:0] bres_x; // Bresenham state X coordinate
wire [10:0] bres_e; // Bresenham state error value
assign bres_valid = bres_rd_data[0];
assign bres_x = bres_rd_data[10:1];
assign bres_e = bres_rd_data[21:11];
RAMB16_S36_S36 Bresenham(
// state read port
.CLKA(clk),
.ADDRA(vector),
.DIPA(4'b0),
.DIA(0),
.DOA(bres_rd_data),
.ENA(read_vector),
.SSRA(1'b0),
.WEA(1'b0),
// state write back port
.CLKB(clk),
.ADDRB(bres_wr_vector),
.DIPB(4'b0),
.DIB({e + w, x, 1'b1}),
.ENB(bres_we),
.WEB(bres_we),
.SSRB(1'b0)
);
reg drawing = 0; // actively drawing
reg vector_valid = 0;
reg xy_valid = 0;
reg last_pixel = 0;
always @(posedge clk)
last_pixel <= (x == xend);
wire in_range = off < h || (off == h && !last_pixel);
assign span = xy_valid && ~e[10] && in_range;
always @(posedge clk)
if( start_line ) drawing <= 1;
else if( vector_valid & last_vector ) drawing <= 0;
always @(posedge clk)
if( start_line ) vector <= 0;
else if( read_vector & drawing ) vector <= vector + 1;
always @(posedge clk)
if( read_vector ) begin
vector_valid <= drawing;
xy_valid <= vector_valid && !last_vector;
end
reg fill = 0;
always @(posedge clk)
if( span || last_vector ) fill <= 0;
else if( vector_valid ) fill <= 1;
assign bres_we = xy_valid && off <= h && e[10];
always @(posedge clk)
if( start_line ) bres_wr_vector <= 0;
else if( bres_we ) bres_wr_vector <= bres_wr_vector + 1;
always @(posedge clk)
if( span ) begin
e <= e - h;
x <= x + 1;
end else if( read_vector ) begin
w <= x1 - x0;
h <= y1 - y0;
off <= scan_y - y0;
xend <= x1;
col_1 <= col;
if( bres_valid ) begin
x <= bres_x;
e <= bres_e;
end else begin
x <= x0;
e <= 49;
end
end
assign read_vector = !xy_valid || !span;
wire plot = (span | fill) && in_range;
reg xy_valid_1 = 0;
always @(posedge clk)
xy_valid_1 <= xy_valid;
assign draw_done = xy_valid_1 && !xy_valid;
wire [9:0] wr_addr = x;
wire [15:0] wr_data = col_1;
/*
* copy handling
*/
reg [9:0] copy_addr = 0;
assign copy_done = (copy_addr == 639) & ~fifo_full;
reg vid_data_valid = 0;
wire [15:0] rd_data;
reg [9:0] fifo_count = 0;
always @(posedge clk)
if( state != COPY ) vid_data_valid <= 0;
else vid_data_valid <= 1;
always @(posedge clk)
if( state != COPY ) copy_addr <= 0;
else if( ~fifo_full ) copy_addr <= copy_addr + 1;
RAMB16_S18_S18 line_buffer(
// read/erase port
.CLKA(clk),
.ADDRA(copy_addr),
.DIPA(2'b0),
.DIA(0),
.DOA(rd_data),
.ENA( state == COPY && ~fifo_full ),
.SSRA(1'b0),
.WEA( 1'b1 ),
// write port
.CLKB(clk),
.ADDRB(wr_addr),
.DIPB(2'b0),
.DIB(wr_data),
.ENB(plot),
.WEB(plot),
.SSRB(1'b0)
);
defparam line_buffer.WRITE_MODE_A = "READ_FIRST";
// send FIFO data
// the copy done signal indicates last pixel of the scanline
always @(posedge clk)
if( !fifo_full )
fifo_data <= rd_data;
always @(posedge clk)
if( !fifo_full )
fifo_write <= vid_data_valid;
always @(posedge clk)
if( ~vid_data_valid ) fifo_count <= 0;
else if( ~fifo_full ) fifo_count <= fifo_count + 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O2111AI_PP_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_PP_SYMBOL_V
|
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