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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_SYMBOL_V
`define SKY130_FD_SC_MS__FAHCIN_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: cocokey.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ([email protected])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
// [email protected]
////////////////////////////////////////////////////////////////////////////////
module COCOKEY(
RESET_N,
CLK50MHZ, //Not really 50 MHz
SLO_CLK,
PS2_CLK,
PS2_DATA,
KEY,
SHIFT,
SHIFT_OVERRIDE,
RESET
);
input RESET_N;
input CLK50MHZ;
input SLO_CLK;
input PS2_CLK;
input PS2_DATA;
output [55:0] KEY;
reg [55:0] KEY;
output SHIFT;
reg SHIFT;
output SHIFT_OVERRIDE;
reg SHIFT_OVERRIDE;
output RESET;
reg RESET;
reg [5:0] SLO_RESET;
wire SLO_RESET_N;
reg [4:0] KB_CLK;
wire [7:0] SCAN;
wire PRESS;
wire EXTENDED;
/* Norm Shift CTRL
00 @
01 a A ^a
02 b B ^b
03 c C ^c
04 d D ^d
05 e E ^e
06 f F ^f
07 g G ^g
08 h H ^h
09 i I ^i
10 j J ^j
11 k K ^k
12 l L ^l
13 m M ^m
14 n N ^n
15 o O ^o
16 p P ^p
17 q Q ^q
18 r R ^r
19 s S ^s
20 t T ^t
21 u U ^u
22 v V ^v
23 w W ^w
24 x X ^x
25 y Y ^y
26 z Z ^z
27 up UP ^up
28 dn DN ^dn
29 lft BS LFT ^lft
30 rgt RGT ^rgt
31 sp SP ^sp
32 0 CL ^0
33 1 ! |
34 2 " ^2
35 3 # ~
36 4 $ ^4
37 5 % ^5
38 6 & ^6
39 7 ' ^
40 8 ( [
41 9 ) ]
42 : *
43 ; +
44 , < {
45 - = _
46 . > }
47 / ? \
48 cr CR ^cr
49 tab TAB ^tab
50 esc ESC ^esc
51 alt ALT ^alt
52 ctrl CTRL ^
53 f1 F1 ^f1
54 f2 F2 ^f2
55 lsh rsh LSH RSH ^lsh ^rsh
*/
always @ (negedge SLO_CLK or negedge RESET_N)
begin
if(~RESET_N)
begin
SLO_RESET <= 6'h00;
end
else
begin
if(SLO_RESET != 6'h3F)
SLO_RESET <= SLO_RESET + 1'b1;
end
end
assign SLO_RESET_N = (SLO_RESET == 6'h3F);
always @(posedge KB_CLK[4] or negedge SLO_RESET_N)
begin
if(~SLO_RESET_N)
begin
KEY <= 56'h00000000000000;
SHIFT_OVERRIDE <= 1'b0;
SHIFT <= 1'b0;
RESET <= 1'b0;
end
else
begin
case(SCAN)
8'h76: KEY[50] <= PRESS; // ESC
8'h05: KEY[53] <= PRESS; // F1
8'h06: KEY[54] <= PRESS; // F2
8'h07: KEY[0] <= PRESS; // @ (must be used when there is a shift or ctrl)
8'h0E:
begin
if(PRESS)
begin
KEY[35] <= 1'b1; // ~ is CTRL - 3
KEY[52] <= 1'b1;
SHIFT_OVERRIDE <= 1'b1;
end
else
begin
KEY[35] <= 1'b0; // ~ is CTRL - 3
KEY[52] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
end
end
8'h16: KEY[33] <= PRESS; // 1 !
8'h1E: // 2 @
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
KEY[34] <= 1'b1; // 2
else // shifted
begin
KEY[34] <= 1'b0; // Not 2 = @
KEY[0] <= 1'b1; // @
SHIFT_OVERRIDE <= 1'b1; // Override the shift
// SHIFT <= 1'b0; // Not Right Shifted
end
end
else // Released
begin
KEY[34] <= 1'b0;
KEY[0] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
end
end
8'h26: KEY[35] <= PRESS; // 3 #
8'h25: KEY[36] <= PRESS; // 4 $
8'h2E: KEY[37] <= PRESS; // 5 %
8'h36:
begin
if(PRESS)
begin
if(!KEY[55])
KEY[38] <= PRESS; // 6
else
begin
KEY[39] <= 1'b1; // CTRL 7 = ^
KEY[52] <= 1'b1; // CTRL
SHIFT_OVERRIDE <= 1'b1; // No shift
end
end
else
begin
KEY[38] <= 1'b0;
KEY[39] <= 1'b0;
KEY[52] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
end
end
8'h3D:
begin
if(PRESS)
begin
if(!KEY[55])
KEY[39] <= 1'b1; // 7
else
KEY[38] <= 1'b1; // Shifted 6 = &
end
else
begin
KEY[38] <= 1'b0;
KEY[39] <= 1'b0;
end
end
8'h3E:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
KEY[40] <= 1'b1; // 8
else
KEY[42] <= 1'b1; // Shift : = *
end
else
begin
KEY[40] <= 1'b0;
KEY[42] <= 1'b0;
end
end
8'h46:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
KEY[41] <= 1'b1; // 9
else
KEY[40] <= 1'b1; // Shifted 8 = (
end
else
begin
KEY[40] <= 1'b0;
KEY[41] <= 1'b0;
end
end
8'h45:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
KEY[32] <= 1'b1; // 0
else
KEY[41] <= 1'b1; // shifted 9 = )
end
else
begin
KEY[32] <= 1'b0;
KEY[41] <= 1'b0;
end
end
8'h4E:
begin
if(PRESS)
begin
if(!KEY[55])
KEY[45] <= 1'b1; // -
else
begin
KEY[45] <= 1'b1; // CTRL - = _
SHIFT_OVERRIDE <= 1'b1; // not shifted
KEY[52] <= 1'b1; // CTRL
end
end
else
begin
KEY[45] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
KEY[52] <= 1'b0;
end
end
8'h55:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
begin
KEY[45] <= 1'b1; // =
// SHIFT_OVERRIDE <= 1'b1; // Override the shift
SHIFT <= 1'b1; // Shifted
end
else // shifted
begin
KEY[43] <= 1'b1; // +
end
end
else
begin
KEY[43] <= 1'b0;
KEY[45] <= 1'b0;
// SHIFT_OVERRIDE <= 1'b0;
SHIFT <= 1'b0;
end
end
8'h5D:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
begin
KEY[47] <= 1'b1; // CTRL - / = \
KEY[52] <= 1'b1; // CTRL
end
else
begin
KEY[33] <= 1'b1; // CTRL - 1 = |
KEY[52] <= 1'b1; // CTRL
SHIFT_OVERRIDE <= 1'b1;
end
end
else
begin
KEY[33] <= 1'b0;
KEY[47] <= 1'b0;
KEY[52] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
end
end
8'h66: KEY[29] <= PRESS; // backspace
8'h0D: KEY[49] <= PRESS; // TAB
8'h15: KEY[17] <= PRESS; // Q
8'h1D: KEY[23] <= PRESS; // W
8'h24: KEY[5] <= PRESS; // E
8'h2D: KEY[18] <= PRESS; // R
8'h2C: KEY[20] <= PRESS; // T
8'h35: KEY[25] <= PRESS; // Y
8'h3C: KEY[21] <= PRESS; // U
8'h43: KEY[9] <= PRESS; // I
8'h44: KEY[15] <= PRESS; // O
8'h4D: KEY[16] <= PRESS; // P
8'h54:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
begin
KEY[40] <= 1'b1; // CTRL - 8 = [
KEY[52] <= 1'b1; // CTRL
end
else
begin
KEY[44] <= 1'b1; // CTRL - , = {
KEY[52] <= 1'b1; // CTRL
SHIFT_OVERRIDE <= 1'b1;
end
end
else
begin
KEY[40] <= 1'b0;
KEY[44] <= 1'b0;
KEY[52] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
end
end
8'h5B:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
begin
KEY[41] <= 1'b1; // CTRL - 9 = ]
KEY[52] <= 1'b1; // CTRL
end
else
begin
KEY[46] <= 1'b1; // CTRL - . = }
KEY[52] <= 1'b1; // CTRL
SHIFT_OVERRIDE <= 1'b1;
end
end
else
begin
KEY[41] <= 1'b0;
KEY[46] <= 1'b0;
KEY[52] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
end
end
8'h58:
begin
KEY[32] <= PRESS; // Caps Lock = Shift 0
KEY[55] <= PRESS;
// SHIFT_OVERRIDE <= PRESS;
end
8'h1C: KEY[1] <= PRESS; // A
8'h1B: KEY[19] <= PRESS; // S
8'h23: KEY[4] <= PRESS; // D
8'h2B: KEY[6] <= PRESS; // F
8'h34: KEY[7] <= PRESS; // G
8'h33: KEY[8] <= PRESS; // H
8'h3B: KEY[10] <= PRESS; // J
8'h42: KEY[11] <= PRESS; // K
8'h4B: KEY[12] <= PRESS; // L
8'h4C:
begin
if(PRESS) // Pressed
begin
if(!KEY[55]) // not shifted
KEY[43] <= 1'b1; // ;
else
begin
KEY[42] <= 1'b1; // :
SHIFT_OVERRIDE <= 1'b1; // Override the shift
end
end
else // Released
begin
KEY[42] <= 1'b0;
KEY[43] <= 1'b0;
SHIFT_OVERRIDE <= 1'b0;
end
end
8'h52:
begin
if(PRESS)
begin
if(!KEY[55])
begin
KEY[39] <= 1'b1; // Shift 7 = '
SHIFT <= 1'b1;
end
else
begin
KEY[34] <= 1'b1; // Shift 2 = "
end
end
else
begin
KEY[34] <= 1'b0;
KEY[39] <= 1'b0;
SHIFT <= 1'b0;
end
end
8'h5A: KEY[48] <= PRESS; // CR
8'h12: KEY[55] <= PRESS; // L-Shift
8'h1A: KEY[26] <= PRESS; // Z
8'h22: KEY[24] <= PRESS; // X
8'h21: KEY[3] <= PRESS; // C
8'h2a: KEY[22] <= PRESS; // V
8'h32: KEY[2] <= PRESS; // B
8'h31: KEY[14] <= PRESS; // N
8'h3A: KEY[13] <= PRESS; // M
8'h41: KEY[44] <= PRESS; // , <
8'h49: KEY[46] <= PRESS; // . >
8'h4A: KEY[47] <= PRESS; // / ?
8'h59: KEY[55] <= PRESS; // R-Shift
8'h14: KEY[52] <= PRESS; // Ctrl either left or right
8'h11: KEY[51] <= PRESS; // ALT either left or right
8'h29: KEY[31] <= PRESS; // Space
8'h75: if(EXTENDED)
KEY[27] <= PRESS; // up
8'h74: if(EXTENDED)
KEY[30] <= PRESS; // right
8'h6B: if(EXTENDED)
KEY[29] <= PRESS; // left
8'h72: if(EXTENDED)
KEY[28] <= PRESS; // down
8'h71:
begin
if(KEY[51] & KEY[52])
RESET <= PRESS;
end
8'h7E:
begin
KEY[23] <= PRESS; // Scroll Lock = CTRL w
KEY[52] <= PRESS;
SHIFT_OVERRIDE <= PRESS;
end
endcase
end
end
// KB_CLK[0] = 50/2 = 25 MHz
// KB_CLK[1] = 50/4 = 12.5 MHz
// KB_CLK[2] = 50/8 = 6.25 MHz
// KB_CLK[3] = 50/16 = 3.125 MHz
// KB_CLK[4] = 50/32 = 1.5625 MHz
// KB_CLK[5] = 50/64 = 0.78125 MHz
always @ (posedge CLK50MHZ) //50 MHz
KB_CLK <= KB_CLK + 1'b1;
ps2_keyboard KEYBOARD(
.RESET_N(RESET_N),
.CLK(KB_CLK[4]),
.PS2_CLK(PS2_CLK),
.PS2_DATA(PS2_DATA),
.RX_SCAN(SCAN),
.RX_PRESSED(PRESS),
.RX_EXTENDED(EXTENDED)
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
lab9_soc_jtag_uart_0_sim_scfifo_w the_lab9_soc_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
lab9_soc_jtag_uart_0_sim_scfifo_r the_lab9_soc_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
lab9_soc_jtag_uart_0_scfifo_w the_lab9_soc_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
lab9_soc_jtag_uart_0_scfifo_r the_lab9_soc_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic lab9_soc_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam lab9_soc_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// lab9_soc_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// lab9_soc_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// lab9_soc_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.4 2007/03/05 13:33:58 wig Exp $
// $Date: 2007/03/05 13:33:58 $
// $Log: ent_b.v,v $
// Revision 1.4 2007/03/05 13:33:58 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No user `defines in this module
module ent_b
//
// Generated Module inst_b
//
(
port_b_1, // Will create p_mix_sig_1_go port
port_b_3, // Interhierachy link, will create p_mix_sig_3_go
port_b_4, // Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1, // Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
port_b_5_2, // Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
port_b_6i, // Conflicting definition
port_b_6o, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08 // VHDL intermediate needed (port name)
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_PP_BLACKBOX_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_sergate_plv (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_PP_BLACKBOX_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Memory_16x256.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Memory_16x256 (
aclr,
address,
clock,
data,
wren,
q);
input aclr;
input [7:0] address;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_16x256_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:00:45 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_counter_d_W4_29 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_15 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_16 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_18 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_19 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_20 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_22 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_25 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2v1_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch2v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire enab_cont_iter, load_cont_iter, enab_d_ff2_RB2, enab_d_ff4_Xn,
enab_d_ff4_Yn, enab_d_ff4_Zn, enab_d_ff5_data_out, enab_dff_5,
d_ff3_sign_out, data_output2_31_, cordic_FSM_state_next_1_,
cont_iter_net3595610, d_ff5_data_out_net3595574, reg_Z0_net3595574,
reg_val_muxZ_2stage_net3595574, reg_shift_y_net3595574,
d_ff4_Xn_net3595574, d_ff4_Yn_net3595574, d_ff4_Zn_net3595574,
d_ff5_net3595574, n180, n186, n187, n188, n189, n193, n194, n195,
n196, n197, intadd_413_CI, intadd_413_n3, intadd_413_n2,
intadd_413_n1, intadd_414_CI, intadd_414_n3, intadd_414_n2,
intadd_414_n1, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n481,
n482, n483, n484, n485;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:1] cont_iter_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [26:0] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [31:0] mux_sal;
wire [31:0] sign_inv_out;
wire [2:0] cordic_FSM_state_reg;
SNPS_CLOCK_GATE_HIGH_counter_d_W4_29 cont_iter_clk_gate_count_reg ( .CLK(clk), .EN(enab_cont_iter), .ENCLK(cont_iter_net3595610), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_13 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3595574),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_25 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(load_cont_iter), .ENCLK(reg_Z0_net3595574), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_22 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(enab_d_ff2_RB2), .ENCLK(reg_val_muxZ_2stage_net3595574),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_20 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(n269), .ENCLK(reg_shift_y_net3595574), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_19 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3595574), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_18 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3595574), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_16 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3595574), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_15 d_ff5_clk_gate_Q_reg ( .CLK(clk), .EN(
enab_dff_5), .ENCLK(d_ff5_net3595574), .TE(1'b0) );
DFFRXLTS cont_iter_count_reg_2_ ( .D(n482), .CK(cont_iter_net3595610), .RN(
n478), .QN(n274) );
DFFRXLTS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3595574),
.RN(n478), .QN(n266) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3595574), .RN(n478), .Q(d_ff1_shift_region_flag_out[0]),
.QN(n447) );
DFFRXLTS reg_ch_mux_1_Q_reg_0_ ( .D(n188), .CK(n479), .RN(n478), .Q(n265),
.QN(n448) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(data_out_LUT[0]), .CK(reg_shift_y_net3595574),
.RN(n478), .Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(data_out_LUT[1]), .CK(reg_shift_y_net3595574),
.RN(n478), .Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(data_out_LUT[2]), .CK(reg_shift_y_net3595574),
.RN(n477), .Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3595574),
.RN(n477), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(data_out_LUT[6]), .CK(reg_shift_y_net3595574),
.RN(n477), .Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(data_out_LUT[8]), .CK(reg_shift_y_net3595574),
.RN(n477), .Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(data_out_LUT[9]), .CK(reg_shift_y_net3595574),
.RN(n477), .Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(data_out_LUT[10]), .CK(
reg_shift_y_net3595574), .RN(n477), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(data_out_LUT[11]), .CK(
reg_shift_y_net3595574), .RN(n477), .Q(d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(data_out_LUT[12]), .CK(
reg_shift_y_net3595574), .RN(n477), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(data_out_LUT[14]), .CK(
reg_shift_y_net3595574), .RN(n477), .Q(d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(data_out_LUT[16]), .CK(
reg_shift_y_net3595574), .RN(n477), .Q(d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(data_out_LUT[18]), .CK(
reg_shift_y_net3595574), .RN(n477), .Q(d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(data_out_LUT[20]), .CK(
reg_shift_y_net3595574), .RN(n477), .Q(d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(data_out_LUT[21]), .CK(
reg_shift_y_net3595574), .RN(n475), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(data_out_LUT[22]), .CK(
reg_shift_y_net3595574), .RN(n471), .Q(d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(data_out_LUT[23]), .CK(
reg_shift_y_net3595574), .RN(n472), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(data_out_LUT[24]), .CK(
reg_shift_y_net3595574), .RN(n465), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3595574), .RN(n466), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(data_out_LUT[26]), .CK(
reg_shift_y_net3595574), .RN(n467), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3595574), .RN(n475),
.Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3595574), .RN(n476),
.Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3595574), .RN(n465),
.Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3595574), .RN(n471),
.Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3595574), .RN(n472),
.Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3595574), .RN(n465),
.Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3595574), .RN(n476),
.Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3595574), .RN(n476),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3595574), .RN(n476),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3595574), .RN(n476),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3595574), .RN(
n476), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3595574), .RN(
n475), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3595574), .RN(
n469), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3595574), .RN(
n470), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3595574), .RN(n473), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3595574), .RN(n468), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3595574), .RN(n469), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3595574), .RN(n470), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3595574), .RN(n473), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3595574), .RN(n468), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3595574), .RN(n469), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3595574), .RN(n470), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3595574), .RN(n474), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3595574), .RN(n474), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n474), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3595574),
.RN(n474), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3595574), .RN(n474), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n474), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3595574),
.RN(n474), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3595574), .RN(n473), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n473), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3595574),
.RN(n473), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3595574), .RN(n473), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n473), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3595574),
.RN(n473), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3595574), .RN(n473), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n473), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3595574),
.RN(n473), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3595574), .RN(n473), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n473), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3595574),
.RN(n473), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3595574), .RN(n472), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n472), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3595574),
.RN(n472), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3595574), .RN(n472), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n472), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3595574),
.RN(n472), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3595574), .RN(n472), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n472), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3595574),
.RN(n472), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3595574), .RN(n472), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n472), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3595574),
.RN(n472), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3595574), .RN(n471), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n471), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3595574), .RN(n471), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3595574), .RN(n471), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n471), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3595574), .RN(n471), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3595574), .RN(n471), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n471), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3595574), .RN(n471), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3595574), .RN(n471), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n471), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3595574), .RN(n471), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3595574), .RN(n476), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n453), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3595574), .RN(n459), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3595574), .RN(n454), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n455), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3595574), .RN(n454), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3595574), .RN(n458), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n455), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3595574), .RN(n471), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3595574), .RN(n474), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n473), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3595574), .RN(n468), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3595574), .RN(n470), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n470), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3595574), .RN(n470), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3595574), .RN(n470), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n470), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3595574), .RN(n470), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3595574), .RN(n470), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n470), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3595574), .RN(n470), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3595574), .RN(n470), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n470), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3595574), .RN(n470), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3595574), .RN(n469), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n469), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3595574), .RN(n469), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3595574), .RN(n469), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n469), .Q(d_ff2_X[23]), .QN(n442)
);
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3595574), .RN(n469), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3595574), .RN(n469), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3595574), .RN(n469), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3595574), .RN(n469), .Q(d_ff_Xn[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n468), .Q(d_ff2_X[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3595574), .RN(n468), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n468), .Q(d_ff2_X[28]), .QN(n450)
);
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3595574), .RN(n468), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3595574), .RN(n468), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n468), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3595574), .RN(n468), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n468), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3595574), .RN(n468), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3595574), .RN(n468), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n468), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3595574),
.RN(n467), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3595574), .RN(n467), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n467), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3595574),
.RN(n467), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3595574), .RN(n467), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n467), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3595574),
.RN(n467), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3595574), .RN(n467), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n467), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3595574),
.RN(n467), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3595574), .RN(n467), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n467), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3595574),
.RN(n466), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3595574), .RN(n466), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n466), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3595574),
.RN(n466), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3595574), .RN(n466), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n466), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3595574),
.RN(n466), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3595574), .RN(n466), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n466), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3595574),
.RN(n466), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3595574), .RN(n466), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n466), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3595574),
.RN(n465), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3595574), .RN(n465), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n465), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3595574),
.RN(n465), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3595574), .RN(n465), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n465), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3595574), .RN(n465), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3595574), .RN(n465), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n465), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3595574), .RN(n465), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3595574), .RN(n465), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n465), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3595574), .RN(n464), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3595574), .RN(n464), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n464), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3595574), .RN(n464), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3595574), .RN(n464), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n464), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3595574), .RN(n464), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3595574), .RN(n464), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n464), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3595574), .RN(n464), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3595574), .RN(n464), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n464), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3595574), .RN(n463), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3595574), .RN(n463), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n463), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3595574), .RN(n463), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3595574), .RN(n463), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n463), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3595574), .RN(n463), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3595574), .RN(n463), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n463), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3595574), .RN(n463), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3595574), .RN(n463), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n463), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3595574), .RN(n462), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3595574), .RN(n462), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n462), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3595574), .RN(n462), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3595574), .RN(n462), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n462), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3595574), .RN(n462), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3595574), .RN(n462), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n462), .Q(d_ff2_Y[23]), .QN(n441)
);
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3595574), .RN(n462), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3595574), .RN(n462), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3595574), .RN(n461), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3595574), .RN(n461), .Q(d_ff_Yn[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n461), .Q(d_ff2_Y[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3595574), .RN(n461), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n461), .Q(d_ff2_Y[28]), .QN(n449)
);
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3595574), .RN(n461), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3595574), .RN(n461), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n461), .Q(d_ff2_Y[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3595574), .RN(n461), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n460), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3595574), .RN(n460), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3595574), .RN(n460), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n460), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3595574), .RN(n460), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n460), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3595574), .RN(n460), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n460), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3595574), .RN(n460), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n460), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3595574), .RN(n460), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n460), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3595574), .RN(n459), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n459), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3595574), .RN(n459), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n459), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3595574), .RN(n459), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n459), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3595574), .RN(n459), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n459), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3595574), .RN(n459), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n459), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3595574), .RN(n459), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n459), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3595574), .RN(n458), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n458), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3595574), .RN(n458), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n458), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3595574), .RN(n458), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n458), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3595574), .RN(n458), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n458), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3595574), .RN(n458), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n458), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3595574), .RN(n458), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n458), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3595574), .RN(n457), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n457), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3595574), .RN(n457), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n457), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3595574), .RN(n457), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n457), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3595574), .RN(n457), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n457), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3595574), .RN(n457), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n457), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3595574), .RN(n457), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n457), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3595574), .RN(n456), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n456), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3595574), .RN(n456), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n456), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3595574), .RN(n456), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n456), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3595574), .RN(n456), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n456), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3595574), .RN(n456), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n456), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3595574), .RN(n456), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n456), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3595574), .RN(n456), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n457), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3595574), .RN(n458), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n454), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3595574), .RN(n455), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n456), .Q(d_ff2_Z[31]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(mux_sal[0]), .CK(d_ff5_net3595574), .RN(n457),
.Q(sign_inv_out[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(mux_sal[1]), .CK(d_ff5_net3595574), .RN(n458),
.Q(sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(mux_sal[2]), .CK(d_ff5_net3595574), .RN(n462),
.Q(sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(mux_sal[3]), .CK(d_ff5_net3595574), .RN(n455),
.Q(sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(mux_sal[4]), .CK(d_ff5_net3595574), .RN(n455),
.Q(sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(mux_sal[5]), .CK(d_ff5_net3595574), .RN(n455),
.Q(sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(mux_sal[6]), .CK(d_ff5_net3595574), .RN(n455),
.Q(sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(mux_sal[7]), .CK(d_ff5_net3595574), .RN(n455),
.Q(sign_inv_out[7]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(mux_sal[8]), .CK(d_ff5_net3595574), .RN(n455),
.Q(sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(mux_sal[9]), .CK(d_ff5_net3595574), .RN(n454),
.Q(sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(mux_sal[10]), .CK(d_ff5_net3595574), .RN(n454),
.Q(sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(mux_sal[11]), .CK(d_ff5_net3595574), .RN(n454),
.Q(sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(mux_sal[12]), .CK(d_ff5_net3595574), .RN(n454),
.Q(sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(mux_sal[13]), .CK(d_ff5_net3595574), .RN(n454),
.Q(sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(mux_sal[14]), .CK(d_ff5_net3595574), .RN(n454),
.Q(sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(mux_sal[15]), .CK(d_ff5_net3595574), .RN(n460),
.Q(sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(mux_sal[16]), .CK(d_ff5_net3595574), .RN(n461),
.Q(sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(mux_sal[17]), .CK(d_ff5_net3595574), .RN(n453),
.Q(sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(mux_sal[18]), .CK(d_ff5_net3595574), .RN(n457),
.Q(sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(mux_sal[19]), .CK(d_ff5_net3595574), .RN(n460),
.Q(sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(mux_sal[20]), .CK(d_ff5_net3595574), .RN(n461),
.Q(sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(mux_sal[21]), .CK(d_ff5_net3595574), .RN(n466),
.Q(sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(mux_sal[22]), .CK(d_ff5_net3595574), .RN(n467),
.Q(sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(mux_sal[23]), .CK(d_ff5_net3595574), .RN(n475),
.Q(sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(mux_sal[24]), .CK(d_ff5_net3595574), .RN(n476),
.Q(sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(mux_sal[25]), .CK(d_ff5_net3595574), .RN(n466),
.Q(sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(mux_sal[26]), .CK(d_ff5_net3595574), .RN(n467),
.Q(sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(mux_sal[27]), .CK(d_ff5_net3595574), .RN(n453),
.Q(sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(mux_sal[28]), .CK(d_ff5_net3595574), .RN(n453),
.Q(sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(mux_sal[29]), .CK(d_ff5_net3595574), .RN(n453),
.Q(sign_inv_out[29]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(mux_sal[30]), .CK(d_ff5_net3595574), .RN(n453),
.Q(sign_inv_out[30]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(mux_sal[31]), .CK(d_ff5_net3595574), .RN(n453),
.Q(data_output2_31_) );
SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2v1_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_reg_ch_mux_2_Q_reg (
.CLK(clk), .EN(n481), .ENCLK(n479), .TE(1'b0) );
CMPR32X2TS intadd_414_U3 ( .A(d_ff2_Y[25]), .B(data_out_LUT[8]), .C(
intadd_414_n3), .CO(intadd_414_n2), .S(sh_exp_y[2]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3595574), .RN(n453), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n194), .CK(n479), .RN(n478), .Q(
cont_var_out[1]), .QN(n446) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n196), .CK(clk), .RN(n180), .Q(
cordic_FSM_state_reg[2]), .QN(n445) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n187), .CK(n479), .RN(n478), .Q(
sel_mux_2_reg[0]), .QN(n444) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n193), .CK(n479), .RN(n478), .Q(
cont_var_out[0]), .QN(n443) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n180), .Q(cordic_FSM_state_reg[1]), .QN(n440) );
DFFRX2TS cont_iter_count_reg_3_ ( .D(n485), .CK(cont_iter_net3595610), .RN(
n477), .Q(cont_iter_out[3]), .QN(n438) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(sign_inv_out[0]), .CK(
d_ff5_data_out_net3595574), .RN(n463), .Q(data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(sign_inv_out[1]), .CK(
d_ff5_data_out_net3595574), .RN(n464), .Q(data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(sign_inv_out[2]), .CK(
d_ff5_data_out_net3595574), .RN(n455), .Q(data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(sign_inv_out[3]), .CK(
d_ff5_data_out_net3595574), .RN(n455), .Q(data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(sign_inv_out[4]), .CK(
d_ff5_data_out_net3595574), .RN(n455), .Q(data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(sign_inv_out[5]), .CK(
d_ff5_data_out_net3595574), .RN(n455), .Q(data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(sign_inv_out[6]), .CK(
d_ff5_data_out_net3595574), .RN(n455), .Q(data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(sign_inv_out[7]), .CK(
d_ff5_data_out_net3595574), .RN(n455), .Q(data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(sign_inv_out[8]), .CK(
d_ff5_data_out_net3595574), .RN(n454), .Q(data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(sign_inv_out[9]), .CK(
d_ff5_data_out_net3595574), .RN(n454), .Q(data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(sign_inv_out[10]), .CK(
d_ff5_data_out_net3595574), .RN(n454), .Q(data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(sign_inv_out[11]), .CK(
d_ff5_data_out_net3595574), .RN(n454), .Q(data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(sign_inv_out[12]), .CK(
d_ff5_data_out_net3595574), .RN(n454), .Q(data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(sign_inv_out[13]), .CK(
d_ff5_data_out_net3595574), .RN(n454), .Q(data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(sign_inv_out[14]), .CK(
d_ff5_data_out_net3595574), .RN(n459), .Q(data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(sign_inv_out[15]), .CK(
d_ff5_data_out_net3595574), .RN(n460), .Q(data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(sign_inv_out[16]), .CK(
d_ff5_data_out_net3595574), .RN(n461), .Q(data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(sign_inv_out[17]), .CK(
d_ff5_data_out_net3595574), .RN(n453), .Q(data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(sign_inv_out[18]), .CK(
d_ff5_data_out_net3595574), .RN(n472), .Q(data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(sign_inv_out[19]), .CK(
d_ff5_data_out_net3595574), .RN(n459), .Q(data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(sign_inv_out[20]), .CK(
d_ff5_data_out_net3595574), .RN(n464), .Q(data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(sign_inv_out[21]), .CK(
d_ff5_data_out_net3595574), .RN(n464), .Q(data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(sign_inv_out[22]), .CK(
d_ff5_data_out_net3595574), .RN(n462), .Q(data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(sign_inv_out[23]), .CK(
d_ff5_data_out_net3595574), .RN(n456), .Q(data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(sign_inv_out[24]), .CK(
d_ff5_data_out_net3595574), .RN(n463), .Q(data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(sign_inv_out[25]), .CK(
d_ff5_data_out_net3595574), .RN(n463), .Q(data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(sign_inv_out[26]), .CK(
d_ff5_data_out_net3595574), .RN(n453), .Q(data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(sign_inv_out[27]), .CK(
d_ff5_data_out_net3595574), .RN(n453), .Q(data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(sign_inv_out[28]), .CK(
d_ff5_data_out_net3595574), .RN(n453), .Q(data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(sign_inv_out[29]), .CK(
d_ff5_data_out_net3595574), .RN(n453), .Q(data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(sign_inv_out[30]), .CK(
d_ff5_data_out_net3595574), .RN(n453), .Q(data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(sign_inv_out[31]), .CK(
d_ff5_data_out_net3595574), .RN(n453), .Q(data_output[31]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3595574),
.RN(n462), .Q(d_ff3_sign_out) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n186), .CK(n479), .RN(n478), .Q(
sel_mux_2_reg[1]) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n484), .CK(cont_iter_net3595610), .RN(
n478), .Q(n451), .QN(n273) );
DFFRX4TS cont_iter_count_reg_1_ ( .D(n483), .CK(cont_iter_net3595610), .RN(
n478), .Q(cont_iter_out[1]), .QN(n436) );
DFFRX2TS reg_ch_mux_3_Q_reg_0_ ( .D(n189), .CK(n479), .RN(n478), .Q(n267),
.QN(n452) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3595574), .RN(n478), .Q(d_ff1_shift_region_flag_out[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n461), .Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n461), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n461), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n462), .Q(d_ff2_Y[24]) );
DFFRX4TS cordic_FSM_state_reg_reg_0_ ( .D(n197), .CK(clk), .RN(n180), .Q(
cordic_FSM_state_reg[0]), .QN(n437) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n468), .Q(d_ff2_X[29]) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n195), .CK(n479), .RN(n180), .Q(
n263), .QN(n439) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n469), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n469), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3595574), .RN(n469), .Q(d_ff2_X[26]) );
ADDFX1TS intadd_413_U4 ( .A(d_ff2_X[24]), .B(n436), .CI(intadd_413_CI), .CO(
intadd_413_n3), .S(sh_exp_x[1]) );
ADDFX1TS intadd_414_U4 ( .A(d_ff2_Y[24]), .B(n436), .CI(intadd_414_CI), .CO(
intadd_414_n3), .S(sh_exp_y[1]) );
ADDFX1TS intadd_413_U3 ( .A(d_ff2_X[25]), .B(data_out_LUT[8]), .CI(
intadd_413_n3), .CO(intadd_413_n2), .S(sh_exp_x[2]) );
ADDFX1TS intadd_414_U2 ( .A(d_ff2_Y[26]), .B(n438), .CI(intadd_414_n2), .CO(
intadd_414_n1), .S(sh_exp_y[3]) );
ADDFX1TS intadd_413_U2 ( .A(d_ff2_X[26]), .B(n438), .CI(intadd_413_n2), .CO(
intadd_413_n1), .S(sh_exp_x[3]) );
AOI222X1TS U437 ( .A0(n351), .A1(d_ff2_Z[8]), .B0(n427), .B1(d_ff2_Y[8]),
.C0(n426), .C1(d_ff2_X[8]), .Y(n343) );
NOR2XLTS U438 ( .A(n300), .B(n305), .Y(enab_d_ff4_Yn) );
INVX3TS U439 ( .A(n379), .Y(n404) );
NAND2XLTS U440 ( .A(sel_mux_2_reg[1]), .B(n477), .Y(n294) );
AOI222X1TS U441 ( .A0(n351), .A1(d_ff2_Z[7]), .B0(n427), .B1(d_ff2_Y[7]),
.C0(n426), .C1(d_ff2_X[7]), .Y(n345) );
AOI222X1TS U442 ( .A0(n351), .A1(d_ff2_Z[9]), .B0(n427), .B1(d_ff2_Y[9]),
.C0(n426), .C1(d_ff2_X[9]), .Y(n344) );
AOI222X1TS U443 ( .A0(n351), .A1(d_ff2_Z[10]), .B0(n427), .B1(d_ff2_Y[10]),
.C0(n426), .C1(d_ff2_X[10]), .Y(n342) );
BUFX3TS U444 ( .A(n408), .Y(n422) );
BUFX3TS U445 ( .A(n426), .Y(n366) );
BUFX4TS U446 ( .A(n293), .Y(n292) );
NOR2X2TS U447 ( .A(sel_mux_2_reg[1]), .B(n444), .Y(n288) );
NOR3X2TS U448 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[0]),
.C(n440), .Y(n264) );
BUFX4TS U449 ( .A(n316), .Y(n339) );
NOR2XLTS U450 ( .A(n263), .B(n481), .Y(enab_d_ff2_RB2) );
NOR3XLTS U451 ( .A(n304), .B(n303), .C(n305), .Y(enab_d_ff4_Xn) );
NOR3XLTS U452 ( .A(n306), .B(n309), .C(n305), .Y(enab_d_ff4_Zn) );
OR2X1TS U453 ( .A(n370), .B(load_cont_iter), .Y(enab_cont_iter) );
NAND2BXLTS U454 ( .AN(d_ff_Xn[26]), .B(n404), .Y(first_mux_X[26]) );
NAND2BXLTS U455 ( .AN(d_ff_Xn[25]), .B(n404), .Y(first_mux_X[25]) );
NAND2BXLTS U456 ( .AN(d_ff_Xn[24]), .B(n404), .Y(first_mux_X[24]) );
AOI222X1TS U457 ( .A0(n445), .A1(cordic_FSM_state_reg[1]), .B0(n445), .B1(
n306), .C0(n440), .C1(n437), .Y(n276) );
NAND2BXLTS U458 ( .AN(d_ff_Xn[29]), .B(n404), .Y(first_mux_X[29]) );
NAND3XLTS U459 ( .A(n384), .B(n478), .C(n299), .Y(n297) );
OAI32X1TS U460 ( .A0(n296), .A1(n306), .A2(n446), .B0(n295), .B1(n294), .Y(
n186) );
OAI31X1TS U461 ( .A0(cordic_FSM_state_reg[2]), .A1(n285), .A2(n437), .B0(
n284), .Y(n196) );
AOI211XLTS U462 ( .A0(cont_var_out[1]), .A1(n308), .B0(n269), .C0(n307), .Y(
n194) );
NOR2XLTS U463 ( .A(cont_var_out[1]), .B(n308), .Y(n307) );
AO22XLTS U464 ( .A0(n383), .A1(d_ff_Yn[31]), .B0(n385), .B1(d_ff_Xn[31]),
.Y(mux_sal[31]) );
AO22XLTS U465 ( .A0(n267), .A1(d_ff_Yn[30]), .B0(n385), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U466 ( .A0(n383), .A1(d_ff_Yn[29]), .B0(n452), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U467 ( .A0(n267), .A1(d_ff_Yn[28]), .B0(n452), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U468 ( .A0(n383), .A1(d_ff_Yn[27]), .B0(n452), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U469 ( .A0(n267), .A1(d_ff_Yn[26]), .B0(n386), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U470 ( .A0(n383), .A1(d_ff_Yn[25]), .B0(n452), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U471 ( .A0(n267), .A1(d_ff_Yn[24]), .B0(n385), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U472 ( .A0(n383), .A1(d_ff_Yn[23]), .B0(n386), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U473 ( .A0(n383), .A1(d_ff_Yn[22]), .B0(n385), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U474 ( .A0(n384), .A1(d_ff_Yn[21]), .B0(n385), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U475 ( .A0(n383), .A1(d_ff_Yn[20]), .B0(n385), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U476 ( .A0(n267), .A1(d_ff_Yn[19]), .B0(n385), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U477 ( .A0(n383), .A1(d_ff_Yn[18]), .B0(n385), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U478 ( .A0(n267), .A1(d_ff_Yn[17]), .B0(n385), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U479 ( .A0(n383), .A1(d_ff_Yn[16]), .B0(n385), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U480 ( .A0(n267), .A1(d_ff_Yn[15]), .B0(n385), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U481 ( .A0(n384), .A1(d_ff_Yn[14]), .B0(n385), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U482 ( .A0(n384), .A1(d_ff_Yn[13]), .B0(n385), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U483 ( .A0(n384), .A1(d_ff_Yn[12]), .B0(n385), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U484 ( .A0(n384), .A1(d_ff_Yn[11]), .B0(n452), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U485 ( .A0(n384), .A1(d_ff_Yn[10]), .B0(n386), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U486 ( .A0(n384), .A1(d_ff_Yn[9]), .B0(n452), .B1(d_ff_Xn[9]), .Y(
mux_sal[9]) );
AO22XLTS U487 ( .A0(n384), .A1(d_ff_Yn[8]), .B0(n386), .B1(d_ff_Xn[8]), .Y(
mux_sal[8]) );
AO22XLTS U488 ( .A0(n384), .A1(d_ff_Yn[7]), .B0(n386), .B1(d_ff_Xn[7]), .Y(
mux_sal[7]) );
AO22XLTS U489 ( .A0(n384), .A1(d_ff_Yn[6]), .B0(n452), .B1(d_ff_Xn[6]), .Y(
mux_sal[6]) );
AO22XLTS U490 ( .A0(n383), .A1(d_ff_Yn[4]), .B0(n386), .B1(d_ff_Xn[4]), .Y(
mux_sal[4]) );
AO22XLTS U491 ( .A0(n267), .A1(d_ff_Yn[2]), .B0(n386), .B1(d_ff_Xn[2]), .Y(
mux_sal[2]) );
AO22XLTS U492 ( .A0(n383), .A1(d_ff_Yn[1]), .B0(n386), .B1(d_ff_Xn[1]), .Y(
mux_sal[1]) );
AO22XLTS U493 ( .A0(n267), .A1(d_ff_Yn[0]), .B0(n386), .B1(d_ff_Xn[0]), .Y(
mux_sal[0]) );
AO22XLTS U494 ( .A0(n380), .A1(d_ff_Zn[30]), .B0(n379), .B1(d_ff1_Z[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U495 ( .A0(n382), .A1(d_ff_Zn[29]), .B0(n379), .B1(d_ff1_Z[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U496 ( .A0(n270), .A1(d_ff_Zn[28]), .B0(n379), .B1(d_ff1_Z[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U497 ( .A0(n270), .A1(d_ff_Zn[27]), .B0(n379), .B1(d_ff1_Z[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U498 ( .A0(n380), .A1(d_ff_Zn[26]), .B0(n379), .B1(d_ff1_Z[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U499 ( .A0(n382), .A1(d_ff_Zn[25]), .B0(n379), .B1(d_ff1_Z[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U500 ( .A0(n380), .A1(d_ff_Zn[24]), .B0(n379), .B1(d_ff1_Z[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U501 ( .A0(n270), .A1(d_ff_Zn[23]), .B0(n379), .B1(d_ff1_Z[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U502 ( .A0(n380), .A1(d_ff_Zn[22]), .B0(n379), .B1(d_ff1_Z[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U503 ( .A0(n382), .A1(d_ff_Zn[21]), .B0(n379), .B1(d_ff1_Z[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U504 ( .A0(n380), .A1(d_ff_Zn[20]), .B0(n379), .B1(d_ff1_Z[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U505 ( .A0(n382), .A1(d_ff_Zn[19]), .B0(n379), .B1(d_ff1_Z[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U506 ( .A0(n382), .A1(d_ff_Zn[18]), .B0(n379), .B1(d_ff1_Z[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U507 ( .A0(n382), .A1(d_ff_Zn[17]), .B0(n379), .B1(d_ff1_Z[17]),
.Y(first_mux_Z[17]) );
NAND2BXLTS U508 ( .AN(d_ff_Xn[28]), .B(n404), .Y(first_mux_X[28]) );
NAND2BXLTS U509 ( .AN(d_ff_Xn[27]), .B(n404), .Y(first_mux_X[27]) );
NAND2BXLTS U510 ( .AN(d_ff_Xn[20]), .B(n404), .Y(first_mux_X[20]) );
NAND2BXLTS U511 ( .AN(d_ff_Xn[19]), .B(n404), .Y(first_mux_X[19]) );
NAND2BXLTS U512 ( .AN(d_ff_Xn[17]), .B(n404), .Y(first_mux_X[17]) );
NAND2BXLTS U513 ( .AN(d_ff_Xn[16]), .B(n404), .Y(first_mux_X[16]) );
NAND2BXLTS U514 ( .AN(d_ff_Xn[12]), .B(n404), .Y(first_mux_X[12]) );
NAND2BXLTS U515 ( .AN(d_ff_Xn[6]), .B(n404), .Y(first_mux_X[6]) );
XOR2XLTS U516 ( .A(d_ff2_Y[30]), .B(n430), .Y(sh_exp_y[7]) );
OAI21XLTS U517 ( .A0(n432), .A1(n449), .B0(n431), .Y(sh_exp_y[5]) );
XOR2XLTS U518 ( .A(d_ff2_X[30]), .B(n433), .Y(sh_exp_x[7]) );
OAI21XLTS U519 ( .A0(n435), .A1(n450), .B0(n434), .Y(sh_exp_x[5]) );
NOR2XLTS U520 ( .A(cont_iter_out[3]), .B(n372), .Y(data_out_LUT[26]) );
NAND2BXLTS U521 ( .AN(data_out_LUT[12]), .B(n396), .Y(data_out_LUT[14]) );
NAND2BXLTS U522 ( .AN(n398), .B(n397), .Y(data_out_LUT[1]) );
OR4X2TS U523 ( .A(n263), .B(cordic_FSM_state_reg[1]), .C(n445), .D(n437),
.Y(n268) );
OAI32X1TS U524 ( .A0(n437), .A1(n372), .A2(n438), .B0(n371), .B1(n437), .Y(
n485) );
NOR4X1TS U525 ( .A(cordic_FSM_state_reg[1]), .B(n445), .C(n439), .D(n437),
.Y(ready_cordic) );
INVX2TS U526 ( .A(n268), .Y(n269) );
AOI222X1TS U527 ( .A0(n402), .A1(cont_iter_out[1]), .B0(n402), .B1(n451),
.C0(cont_iter_out[3]), .C1(n436), .Y(data_out_LUT[4]) );
OAI211XLTS U528 ( .A0(cont_iter_out[1]), .A1(data_out_LUT[22]), .B0(n403),
.C0(n392), .Y(data_out_LUT[24]) );
AOI31X2TS U529 ( .A0(n393), .A1(n273), .A2(n436), .B0(n281), .Y(n403) );
INVX2TS U530 ( .A(n378), .Y(n270) );
INVX4TS U531 ( .A(n270), .Y(n271) );
CLKBUFX2TS U532 ( .A(n448), .Y(n378) );
INVX2TS U533 ( .A(n266), .Y(n272) );
CLKINVX3TS U534 ( .A(n386), .Y(n384) );
CLKINVX3TS U535 ( .A(n386), .Y(n383) );
NOR4X2TS U536 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[2]),
.C(n439), .D(n437), .Y(ack_add_subt) );
AND4X2TS U537 ( .A(n439), .B(n445), .C(n440), .D(n437), .Y(n293) );
NAND3X2TS U538 ( .A(cordic_FSM_state_reg[2]), .B(n440), .C(n437), .Y(n481)
);
AOI222X4TS U539 ( .A0(n368), .A1(d_ff2_Z[30]), .B0(n367), .B1(d_ff2_Y[30]),
.C0(n366), .C1(d_ff2_X[30]), .Y(n362) );
AOI222X4TS U540 ( .A0(n368), .A1(d_ff2_Z[24]), .B0(n367), .B1(d_ff2_Y[24]),
.C0(n366), .C1(d_ff2_X[24]), .Y(n363) );
AOI222X4TS U541 ( .A0(n368), .A1(d_ff2_Z[25]), .B0(n367), .B1(d_ff2_Y[25]),
.C0(n366), .C1(d_ff2_X[25]), .Y(n364) );
AOI222X4TS U542 ( .A0(n368), .A1(d_ff2_Z[26]), .B0(n367), .B1(d_ff2_Y[26]),
.C0(n366), .C1(d_ff2_X[26]), .Y(n365) );
BUFX4TS U543 ( .A(n408), .Y(n340) );
BUFX4TS U544 ( .A(n288), .Y(n408) );
BUFX3TS U545 ( .A(n292), .Y(n277) );
AOI222X4TS U546 ( .A0(n368), .A1(d_ff2_Z[29]), .B0(n367), .B1(d_ff2_Y[29]),
.C0(n366), .C1(d_ff2_X[29]), .Y(n369) );
AOI32X4TS U547 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(n447), .A2(n272),
.B0(n387), .B1(d_ff1_shift_region_flag_out[0]), .Y(n388) );
OAI32X1TS U548 ( .A0(n295), .A1(n292), .A2(n444), .B0(n300), .B1(n296), .Y(
n187) );
NOR4X2TS U549 ( .A(n263), .B(cordic_FSM_state_reg[0]), .C(n445), .D(n440),
.Y(n295) );
BUFX4TS U550 ( .A(n316), .Y(n426) );
BUFX4TS U551 ( .A(n381), .Y(n379) );
NAND2X2TS U552 ( .A(n402), .B(cont_iter_out[3]), .Y(data_out_LUT[22]) );
NOR4X2TS U553 ( .A(n402), .B(cont_iter_out[3]), .C(n451), .D(
cont_iter_out[1]), .Y(n398) );
INVX4TS U554 ( .A(n274), .Y(n402) );
OAI21XLTS U555 ( .A0(n299), .A1(n298), .B0(n297), .Y(n189) );
AOI211XLTS U556 ( .A0(n310), .A1(n443), .B0(n269), .C0(n302), .Y(n193) );
INVX2TS U557 ( .A(n402), .Y(data_out_LUT[8]) );
NAND2X1TS U558 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n282) );
NOR3X1TS U559 ( .A(n263), .B(n445), .C(n282), .Y(beg_add_subt) );
NAND2X2TS U560 ( .A(n451), .B(cont_iter_out[1]), .Y(n401) );
NOR2X2TS U561 ( .A(data_out_LUT[22]), .B(n401), .Y(n306) );
NAND4BX1TS U562 ( .AN(ack_cordic), .B(cordic_FSM_state_reg[2]), .C(n263),
.D(n440), .Y(n312) );
INVX2TS U563 ( .A(beg_add_subt), .Y(n275) );
OAI211XLTS U564 ( .A0(n276), .A1(n439), .B0(n312), .C0(n275), .Y(n195) );
INVX4TS U565 ( .A(n277), .Y(n453) );
INVX4TS U566 ( .A(n293), .Y(n466) );
INVX4TS U567 ( .A(n277), .Y(n461) );
INVX4TS U568 ( .A(n292), .Y(n467) );
INVX4TS U569 ( .A(n277), .Y(n460) );
INVX4TS U570 ( .A(n277), .Y(n471) );
INVX4TS U571 ( .A(n277), .Y(n468) );
INVX4TS U572 ( .A(n293), .Y(n459) );
INVX4TS U573 ( .A(n277), .Y(n474) );
INVX4TS U574 ( .A(n277), .Y(n473) );
INVX4TS U575 ( .A(n277), .Y(n470) );
INVX4TS U576 ( .A(n277), .Y(n469) );
INVX4TS U577 ( .A(n292), .Y(n475) );
INVX4TS U578 ( .A(n292), .Y(n454) );
INVX4TS U579 ( .A(n292), .Y(n458) );
INVX4TS U580 ( .A(n292), .Y(n465) );
INVX4TS U581 ( .A(n292), .Y(n476) );
INVX4TS U582 ( .A(n292), .Y(n455) );
NOR3XLTS U583 ( .A(cordic_FSM_state_reg[2]), .B(n439), .C(n282), .Y(
enab_dff_5) );
NOR2XLTS U584 ( .A(n439), .B(n481), .Y(enab_d_ff5_data_out) );
INVX2TS U585 ( .A(n401), .Y(n280) );
AOI221XLTS U586 ( .A0(n402), .A1(n280), .B0(data_out_LUT[8]), .B1(n401),
.C0(n437), .Y(n482) );
NOR3X1TS U587 ( .A(n263), .B(cordic_FSM_state_reg[2]), .C(n282), .Y(n279) );
BUFX3TS U588 ( .A(n271), .Y(n381) );
INVX2TS U589 ( .A(n279), .Y(n278) );
OAI32X1TS U590 ( .A0(n279), .A1(n293), .A2(n381), .B0(n398), .B1(n278), .Y(
n188) );
NOR2X2TS U591 ( .A(n402), .B(n438), .Y(n393) );
NOR2X2TS U592 ( .A(cont_iter_out[3]), .B(data_out_LUT[8]), .Y(n400) );
NOR2X2TS U593 ( .A(n393), .B(n400), .Y(n397) );
OAI21X1TS U594 ( .A0(n402), .A1(n436), .B0(n397), .Y(data_out_LUT[20]) );
OR2X1TS U595 ( .A(data_out_LUT[20]), .B(n398), .Y(data_out_LUT[11]) );
NAND2X1TS U596 ( .A(n280), .B(n400), .Y(n371) );
INVX2TS U597 ( .A(n371), .Y(n281) );
AOI33X1TS U598 ( .A0(n451), .A1(cont_iter_out[1]), .A2(data_out_LUT[8]),
.B0(n436), .B1(n438), .B2(n273), .Y(n392) );
INVX4TS U599 ( .A(n292), .Y(n477) );
INVX4TS U600 ( .A(n292), .Y(n478) );
INVX2TS U601 ( .A(n306), .Y(n301) );
NAND2X1TS U602 ( .A(cont_var_out[1]), .B(n443), .Y(n309) );
AOI31XLTS U603 ( .A0(n263), .A1(n301), .A2(n309), .B0(
cordic_FSM_state_reg[1]), .Y(n285) );
OAI2BB2XLTS U604 ( .B0(cordic_FSM_state_reg[1]), .B1(ack_cordic), .A0N(n439),
.A1N(n282), .Y(n283) );
INVX2TS U605 ( .A(n481), .Y(n314) );
AOI21X1TS U606 ( .A0(cordic_FSM_state_reg[2]), .A1(n283), .B0(n314), .Y(n284) );
NOR2X1TS U607 ( .A(d_ff1_shift_region_flag_out[1]), .B(n272), .Y(n387) );
AOI21X1TS U608 ( .A0(n272), .A1(d_ff1_shift_region_flag_out[1]), .B0(n387),
.Y(n286) );
XNOR2X1TS U609 ( .A(d_ff1_shift_region_flag_out[0]), .B(n286), .Y(n298) );
NOR2X1TS U610 ( .A(n301), .B(n298), .Y(n304) );
AOI21X1TS U611 ( .A0(cont_var_out[0]), .A1(n301), .B0(n304), .Y(n300) );
INVX2TS U612 ( .A(n295), .Y(n296) );
NOR2BX1TS U613 ( .AN(sel_mux_2_reg[1]), .B(sel_mux_2_reg[0]), .Y(n287) );
BUFX3TS U614 ( .A(n287), .Y(n429) );
BUFX3TS U615 ( .A(n429), .Y(n425) );
NOR2X1TS U616 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n316) );
BUFX3TS U617 ( .A(n339), .Y(n421) );
AOI22X1TS U618 ( .A0(n422), .A1(d_ff3_sh_x_out[18]), .B0(n421), .B1(
d_ff3_sh_y_out[18]), .Y(n289) );
OAI2BB1X1TS U619 ( .A0N(n425), .A1N(d_ff3_LUT_out[18]), .B0(n289), .Y(
add_subt_dataB[18]) );
AOI22X1TS U620 ( .A0(n422), .A1(d_ff3_sh_x_out[16]), .B0(n421), .B1(
d_ff3_sh_y_out[16]), .Y(n290) );
OAI2BB1X1TS U621 ( .A0N(n425), .A1N(d_ff3_LUT_out[16]), .B0(n290), .Y(
add_subt_dataB[16]) );
AOI22X1TS U622 ( .A0(n422), .A1(d_ff3_sh_x_out[14]), .B0(n421), .B1(
d_ff3_sh_y_out[14]), .Y(n291) );
OAI2BB1X1TS U623 ( .A0N(n425), .A1N(d_ff3_LUT_out[14]), .B0(n291), .Y(
add_subt_dataB[14]) );
INVX4TS U624 ( .A(n292), .Y(n464) );
INVX2TS U625 ( .A(rst), .Y(n180) );
INVX4TS U626 ( .A(n292), .Y(n472) );
INVX4TS U627 ( .A(n293), .Y(n463) );
INVX4TS U628 ( .A(n292), .Y(n457) );
INVX4TS U629 ( .A(n293), .Y(n456) );
INVX4TS U630 ( .A(n293), .Y(n462) );
NAND2X1TS U631 ( .A(n442), .B(n451), .Y(intadd_413_CI) );
OAI21XLTS U632 ( .A0(n451), .A1(n442), .B0(intadd_413_CI), .Y(sh_exp_x[0])
);
NAND2X1TS U633 ( .A(n441), .B(n451), .Y(intadd_414_CI) );
OAI21XLTS U634 ( .A0(n451), .A1(n441), .B0(intadd_414_CI), .Y(sh_exp_y[0])
);
NOR2X1TS U635 ( .A(data_out_LUT[8]), .B(n401), .Y(n372) );
NOR2X1TS U636 ( .A(d_ff2_Y[27]), .B(intadd_414_n1), .Y(n432) );
OR3X1TS U637 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_414_n1), .Y(n431)
);
NOR2X1TS U638 ( .A(d_ff2_X[27]), .B(intadd_413_n1), .Y(n435) );
OR3X1TS U639 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_413_n1), .Y(n434)
);
OAI21X1TS U640 ( .A0(n402), .A1(cont_iter_out[1]), .B0(n397), .Y(
data_out_LUT[16]) );
OAI21X1TS U641 ( .A0(n402), .A1(n273), .B0(n397), .Y(data_out_LUT[18]) );
NAND4XLTS U642 ( .A(n263), .B(cordic_FSM_state_reg[1]), .C(n445), .D(n437),
.Y(n299) );
BUFX3TS U643 ( .A(n452), .Y(n386) );
NAND2X1TS U644 ( .A(ready_add_subt), .B(n440), .Y(n311) );
NAND4BX1TS U645 ( .AN(n311), .B(n263), .C(n437), .D(n445), .Y(n305) );
CLKAND2X2TS U646 ( .A(n264), .B(n439), .Y(load_cont_iter) );
NAND2X1TS U647 ( .A(ack_add_subt), .B(n301), .Y(n310) );
AOI21X1TS U648 ( .A0(n309), .A1(n443), .B0(n310), .Y(n302) );
AOI21X1TS U649 ( .A0(n446), .A1(n443), .B0(n306), .Y(n303) );
NOR2X1TS U650 ( .A(n443), .B(n310), .Y(n308) );
NAND2X1TS U651 ( .A(n439), .B(n440), .Y(n375) );
NOR2X1TS U652 ( .A(n310), .B(n309), .Y(n370) );
AOI32X1TS U653 ( .A0(n263), .A1(n312), .A2(n311), .B0(
cordic_FSM_state_reg[0]), .B1(n312), .Y(n313) );
NOR4X1TS U654 ( .A(n370), .B(n314), .C(n264), .D(n313), .Y(n315) );
OAI31X1TS U655 ( .A0(cordic_FSM_state_reg[2]), .A1(beg_fsm_cordic), .A2(n375), .B0(n315), .Y(n197) );
BUFX3TS U656 ( .A(n288), .Y(n367) );
AOI222X1TS U657 ( .A0(n429), .A1(d_ff3_LUT_out[4]), .B0(n367), .B1(
d_ff3_sh_x_out[4]), .C0(n366), .C1(d_ff3_sh_y_out[4]), .Y(n317) );
INVX2TS U658 ( .A(n317), .Y(add_subt_dataB[4]) );
BUFX3TS U659 ( .A(n426), .Y(n407) );
AOI222X1TS U660 ( .A0(n429), .A1(d_ff3_LUT_out[8]), .B0(n408), .B1(
d_ff3_sh_x_out[8]), .C0(n407), .C1(d_ff3_sh_y_out[8]), .Y(n318) );
INVX2TS U661 ( .A(n318), .Y(add_subt_dataB[8]) );
AOI222X1TS U662 ( .A0(n425), .A1(d_ff3_LUT_out[24]), .B0(n408), .B1(
d_ff3_sh_x_out[24]), .C0(n407), .C1(d_ff3_sh_y_out[24]), .Y(n319) );
INVX2TS U663 ( .A(n319), .Y(add_subt_dataB[24]) );
AOI222X1TS U664 ( .A0(n429), .A1(d_ff3_LUT_out[6]), .B0(n408), .B1(
d_ff3_sh_x_out[6]), .C0(n407), .C1(d_ff3_sh_y_out[6]), .Y(n320) );
INVX2TS U665 ( .A(n320), .Y(add_subt_dataB[6]) );
AOI222X1TS U666 ( .A0(n429), .A1(d_ff3_LUT_out[9]), .B0(n408), .B1(
d_ff3_sh_x_out[9]), .C0(n407), .C1(d_ff3_sh_y_out[9]), .Y(n321) );
INVX2TS U667 ( .A(n321), .Y(add_subt_dataB[9]) );
AOI222X1TS U668 ( .A0(n429), .A1(d_ff3_LUT_out[21]), .B0(n408), .B1(
d_ff3_sh_x_out[21]), .C0(n407), .C1(d_ff3_sh_y_out[21]), .Y(n322) );
INVX2TS U669 ( .A(n322), .Y(add_subt_dataB[21]) );
AOI222X1TS U670 ( .A0(n425), .A1(d_ff3_LUT_out[12]), .B0(n408), .B1(
d_ff3_sh_x_out[12]), .C0(n407), .C1(d_ff3_sh_y_out[12]), .Y(n323) );
INVX2TS U671 ( .A(n323), .Y(add_subt_dataB[12]) );
AOI222X1TS U672 ( .A0(n425), .A1(d_ff3_LUT_out[23]), .B0(n408), .B1(
d_ff3_sh_x_out[23]), .C0(n407), .C1(d_ff3_sh_y_out[23]), .Y(n324) );
INVX2TS U673 ( .A(n324), .Y(add_subt_dataB[23]) );
AOI222X1TS U674 ( .A0(n425), .A1(d_ff3_LUT_out[26]), .B0(n408), .B1(
d_ff3_sh_x_out[26]), .C0(n407), .C1(d_ff3_sh_y_out[26]), .Y(n325) );
INVX2TS U675 ( .A(n325), .Y(add_subt_dataB[26]) );
AOI222X1TS U676 ( .A0(n425), .A1(d_ff3_LUT_out[25]), .B0(n408), .B1(
d_ff3_sh_x_out[25]), .C0(n407), .C1(d_ff3_sh_y_out[25]), .Y(n326) );
INVX2TS U677 ( .A(n326), .Y(add_subt_dataB[25]) );
BUFX3TS U678 ( .A(n429), .Y(n353) );
AOI222X1TS U679 ( .A0(n353), .A1(d_ff2_Z[20]), .B0(n340), .B1(d_ff2_Y[20]),
.C0(n339), .C1(d_ff2_X[20]), .Y(n327) );
INVX2TS U680 ( .A(n327), .Y(add_subt_dataA[20]) );
AOI222X1TS U681 ( .A0(n353), .A1(d_ff2_Z[22]), .B0(n340), .B1(d_ff2_Y[22]),
.C0(n339), .C1(d_ff2_X[22]), .Y(n328) );
INVX2TS U682 ( .A(n328), .Y(add_subt_dataA[22]) );
AOI222X1TS U683 ( .A0(n353), .A1(d_ff2_Z[23]), .B0(n340), .B1(d_ff2_Y[23]),
.C0(n339), .C1(d_ff2_X[23]), .Y(n329) );
INVX2TS U684 ( .A(n329), .Y(add_subt_dataA[23]) );
AOI222X1TS U685 ( .A0(n353), .A1(d_ff2_Z[13]), .B0(n340), .B1(d_ff2_Y[13]),
.C0(n339), .C1(d_ff2_X[13]), .Y(n330) );
INVX2TS U686 ( .A(n330), .Y(add_subt_dataA[13]) );
AOI222X1TS U687 ( .A0(n353), .A1(d_ff2_Z[21]), .B0(n340), .B1(d_ff2_Y[21]),
.C0(n339), .C1(d_ff2_X[21]), .Y(n331) );
INVX2TS U688 ( .A(n331), .Y(add_subt_dataA[21]) );
AOI222X1TS U689 ( .A0(n353), .A1(d_ff2_Z[19]), .B0(n340), .B1(d_ff2_Y[19]),
.C0(n339), .C1(d_ff2_X[19]), .Y(n332) );
INVX2TS U690 ( .A(n332), .Y(add_subt_dataA[19]) );
AOI222X1TS U691 ( .A0(n353), .A1(d_ff2_Z[14]), .B0(n340), .B1(d_ff2_Y[14]),
.C0(n339), .C1(d_ff2_X[14]), .Y(n333) );
INVX2TS U692 ( .A(n333), .Y(add_subt_dataA[14]) );
AOI222X1TS U693 ( .A0(n353), .A1(d_ff2_Z[18]), .B0(n340), .B1(d_ff2_Y[18]),
.C0(n339), .C1(d_ff2_X[18]), .Y(n334) );
INVX2TS U694 ( .A(n334), .Y(add_subt_dataA[18]) );
AOI222X1TS U695 ( .A0(n353), .A1(d_ff2_Z[16]), .B0(n340), .B1(d_ff2_Y[16]),
.C0(n339), .C1(d_ff2_X[16]), .Y(n335) );
INVX2TS U696 ( .A(n335), .Y(add_subt_dataA[16]) );
AOI222X1TS U697 ( .A0(n353), .A1(d_ff2_Z[15]), .B0(n340), .B1(d_ff2_Y[15]),
.C0(n339), .C1(d_ff2_X[15]), .Y(n336) );
INVX2TS U698 ( .A(n336), .Y(add_subt_dataA[15]) );
AOI222X1TS U699 ( .A0(n353), .A1(d_ff2_Z[17]), .B0(n340), .B1(d_ff2_Y[17]),
.C0(n339), .C1(d_ff2_X[17]), .Y(n337) );
INVX2TS U700 ( .A(n337), .Y(add_subt_dataA[17]) );
BUFX3TS U701 ( .A(n425), .Y(n351) );
AOI222X1TS U702 ( .A0(n351), .A1(d_ff2_Z[12]), .B0(n340), .B1(d_ff2_Y[12]),
.C0(n339), .C1(d_ff2_X[12]), .Y(n338) );
INVX2TS U703 ( .A(n338), .Y(add_subt_dataA[12]) );
AOI222X1TS U704 ( .A0(n351), .A1(d_ff2_Z[11]), .B0(n340), .B1(d_ff2_Y[11]),
.C0(n339), .C1(d_ff2_X[11]), .Y(n341) );
INVX2TS U705 ( .A(n341), .Y(add_subt_dataA[11]) );
BUFX3TS U706 ( .A(n288), .Y(n427) );
INVX2TS U707 ( .A(n342), .Y(add_subt_dataA[10]) );
INVX2TS U708 ( .A(n343), .Y(add_subt_dataA[8]) );
INVX2TS U709 ( .A(n344), .Y(add_subt_dataA[9]) );
INVX2TS U710 ( .A(n345), .Y(add_subt_dataA[7]) );
AOI222X1TS U711 ( .A0(n351), .A1(d_ff2_Z[1]), .B0(n427), .B1(d_ff2_Y[1]),
.C0(n426), .C1(d_ff2_X[1]), .Y(n346) );
INVX2TS U712 ( .A(n346), .Y(add_subt_dataA[1]) );
AOI222X1TS U713 ( .A0(n351), .A1(d_ff2_Z[6]), .B0(n427), .B1(d_ff2_Y[6]),
.C0(n426), .C1(d_ff2_X[6]), .Y(n347) );
INVX2TS U714 ( .A(n347), .Y(add_subt_dataA[6]) );
AOI222X1TS U715 ( .A0(n351), .A1(d_ff2_Z[3]), .B0(n427), .B1(d_ff2_Y[3]),
.C0(n426), .C1(d_ff2_X[3]), .Y(n348) );
INVX2TS U716 ( .A(n348), .Y(add_subt_dataA[3]) );
AOI222X1TS U717 ( .A0(n351), .A1(d_ff2_Z[4]), .B0(n427), .B1(d_ff2_Y[4]),
.C0(n426), .C1(d_ff2_X[4]), .Y(n349) );
INVX2TS U718 ( .A(n349), .Y(add_subt_dataA[4]) );
AOI222X1TS U719 ( .A0(n351), .A1(d_ff2_Z[2]), .B0(n427), .B1(d_ff2_Y[2]),
.C0(n426), .C1(d_ff2_X[2]), .Y(n350) );
INVX2TS U720 ( .A(n350), .Y(add_subt_dataA[2]) );
AOI222X1TS U721 ( .A0(n351), .A1(d_ff2_Z[5]), .B0(n427), .B1(d_ff2_Y[5]),
.C0(n426), .C1(d_ff2_X[5]), .Y(n352) );
INVX2TS U722 ( .A(n352), .Y(add_subt_dataA[5]) );
BUFX3TS U723 ( .A(n353), .Y(n368) );
AOI222X1TS U724 ( .A0(n368), .A1(d_ff3_LUT_out[2]), .B0(n367), .B1(
d_ff3_sh_x_out[2]), .C0(n366), .C1(d_ff3_sh_y_out[2]), .Y(n354) );
INVX2TS U725 ( .A(n354), .Y(add_subt_dataB[2]) );
AOI222X1TS U726 ( .A0(n368), .A1(d_ff3_LUT_out[10]), .B0(n408), .B1(
d_ff3_sh_x_out[10]), .C0(n407), .C1(d_ff3_sh_y_out[10]), .Y(n355) );
INVX2TS U727 ( .A(n355), .Y(add_subt_dataB[10]) );
AOI222X1TS U728 ( .A0(n368), .A1(d_ff3_LUT_out[0]), .B0(n367), .B1(
d_ff3_sh_x_out[0]), .C0(n366), .C1(d_ff3_sh_y_out[0]), .Y(n356) );
INVX2TS U729 ( .A(n356), .Y(add_subt_dataB[0]) );
AOI222X1TS U730 ( .A0(n368), .A1(d_ff3_LUT_out[1]), .B0(n367), .B1(
d_ff3_sh_x_out[1]), .C0(n366), .C1(d_ff3_sh_y_out[1]), .Y(n357) );
INVX2TS U731 ( .A(n357), .Y(add_subt_dataB[1]) );
AOI222X1TS U732 ( .A0(n368), .A1(d_ff2_Z[27]), .B0(n367), .B1(d_ff2_Y[27]),
.C0(n366), .C1(d_ff2_X[27]), .Y(n358) );
INVX2TS U733 ( .A(n358), .Y(add_subt_dataA[27]) );
AOI222X1TS U734 ( .A0(n368), .A1(d_ff2_Z[0]), .B0(n367), .B1(d_ff2_Y[0]),
.C0(n366), .C1(d_ff2_X[0]), .Y(n359) );
INVX2TS U735 ( .A(n359), .Y(add_subt_dataA[0]) );
AOI222X1TS U736 ( .A0(n368), .A1(d_ff2_Z[28]), .B0(n367), .B1(d_ff2_Y[28]),
.C0(n366), .C1(d_ff2_X[28]), .Y(n360) );
INVX2TS U737 ( .A(n360), .Y(add_subt_dataA[28]) );
AOI222X1TS U738 ( .A0(n368), .A1(d_ff2_Z[31]), .B0(n367), .B1(d_ff2_Y[31]),
.C0(n366), .C1(d_ff2_X[31]), .Y(n361) );
INVX2TS U739 ( .A(n361), .Y(add_subt_dataA[31]) );
INVX2TS U740 ( .A(n362), .Y(add_subt_dataA[30]) );
INVX2TS U741 ( .A(n363), .Y(add_subt_dataA[24]) );
INVX2TS U742 ( .A(n364), .Y(add_subt_dataA[25]) );
INVX2TS U743 ( .A(n365), .Y(add_subt_dataA[26]) );
INVX2TS U744 ( .A(n369), .Y(add_subt_dataA[29]) );
NOR2XLTS U745 ( .A(n451), .B(n437), .Y(n484) );
NOR2X2TS U747 ( .A(n451), .B(n436), .Y(n399) );
INVX2TS U748 ( .A(n399), .Y(n395) );
OAI21X1TS U749 ( .A0(cont_iter_out[1]), .A1(n273), .B0(n395), .Y(n390) );
CLKAND2X2TS U750 ( .A(n390), .B(cordic_FSM_state_reg[0]), .Y(n483) );
INVX2TS U751 ( .A(beg_fsm_cordic), .Y(n374) );
NAND2X1TS U752 ( .A(cordic_FSM_state_reg[1]), .B(n439), .Y(n373) );
OAI32X1TS U753 ( .A0(n437), .A1(n375), .A2(n374), .B0(
cordic_FSM_state_reg[0]), .B1(n373), .Y(n376) );
OR4X2TS U754 ( .A(n269), .B(ack_add_subt), .C(n264), .D(n376), .Y(
cordic_FSM_state_next_1_) );
INVX4TS U755 ( .A(n381), .Y(n405) );
CLKAND2X2TS U756 ( .A(d_ff_Yn[0]), .B(n405), .Y(first_mux_Y[0]) );
CLKAND2X2TS U757 ( .A(d_ff_Yn[1]), .B(n270), .Y(first_mux_Y[1]) );
INVX4TS U758 ( .A(n381), .Y(n377) );
CLKAND2X2TS U759 ( .A(d_ff_Yn[2]), .B(n377), .Y(first_mux_Y[2]) );
CLKAND2X2TS U760 ( .A(d_ff_Yn[3]), .B(n377), .Y(first_mux_Y[3]) );
CLKAND2X2TS U761 ( .A(d_ff_Yn[4]), .B(n377), .Y(first_mux_Y[4]) );
INVX4TS U762 ( .A(n271), .Y(n406) );
CLKAND2X2TS U763 ( .A(d_ff_Yn[5]), .B(n406), .Y(first_mux_Y[5]) );
CLKAND2X2TS U764 ( .A(d_ff_Yn[6]), .B(n404), .Y(first_mux_Y[6]) );
CLKAND2X2TS U765 ( .A(d_ff_Yn[7]), .B(n377), .Y(first_mux_Y[7]) );
CLKAND2X2TS U766 ( .A(d_ff_Yn[8]), .B(n377), .Y(first_mux_Y[8]) );
CLKAND2X2TS U767 ( .A(d_ff_Yn[9]), .B(n405), .Y(first_mux_Y[9]) );
CLKAND2X2TS U768 ( .A(d_ff_Yn[10]), .B(n377), .Y(first_mux_Y[10]) );
CLKAND2X2TS U769 ( .A(d_ff_Yn[11]), .B(n405), .Y(first_mux_Y[11]) );
CLKAND2X2TS U770 ( .A(d_ff_Yn[12]), .B(n377), .Y(first_mux_Y[12]) );
CLKAND2X2TS U771 ( .A(d_ff_Yn[13]), .B(n405), .Y(first_mux_Y[13]) );
CLKAND2X2TS U772 ( .A(d_ff_Yn[14]), .B(n377), .Y(first_mux_Y[14]) );
CLKAND2X2TS U773 ( .A(d_ff_Yn[15]), .B(n377), .Y(first_mux_Y[15]) );
CLKAND2X2TS U774 ( .A(d_ff_Yn[16]), .B(n270), .Y(first_mux_Y[16]) );
INVX4TS U775 ( .A(n381), .Y(n380) );
CLKAND2X2TS U776 ( .A(d_ff_Yn[17]), .B(n380), .Y(first_mux_Y[17]) );
CLKAND2X2TS U777 ( .A(d_ff_Yn[18]), .B(n377), .Y(first_mux_Y[18]) );
INVX4TS U778 ( .A(n381), .Y(n382) );
CLKAND2X2TS U779 ( .A(d_ff_Yn[19]), .B(n382), .Y(first_mux_Y[19]) );
CLKAND2X2TS U780 ( .A(d_ff_Yn[20]), .B(n377), .Y(first_mux_Y[20]) );
CLKAND2X2TS U781 ( .A(d_ff_Yn[21]), .B(n380), .Y(first_mux_Y[21]) );
CLKAND2X2TS U782 ( .A(d_ff_Yn[22]), .B(n377), .Y(first_mux_Y[22]) );
CLKAND2X2TS U783 ( .A(d_ff_Yn[23]), .B(n382), .Y(first_mux_Y[23]) );
CLKAND2X2TS U784 ( .A(d_ff_Yn[24]), .B(n377), .Y(first_mux_Y[24]) );
CLKAND2X2TS U785 ( .A(d_ff_Yn[25]), .B(n405), .Y(first_mux_Y[25]) );
CLKAND2X2TS U786 ( .A(d_ff_Yn[26]), .B(n405), .Y(first_mux_Y[26]) );
CLKAND2X2TS U787 ( .A(d_ff_Yn[27]), .B(n406), .Y(first_mux_Y[27]) );
CLKAND2X2TS U788 ( .A(d_ff_Yn[28]), .B(n377), .Y(first_mux_Y[28]) );
CLKAND2X2TS U789 ( .A(d_ff_Yn[29]), .B(n405), .Y(first_mux_Y[29]) );
CLKAND2X2TS U790 ( .A(d_ff_Yn[30]), .B(n377), .Y(first_mux_Y[30]) );
CLKAND2X2TS U791 ( .A(d_ff_Yn[31]), .B(n405), .Y(first_mux_Y[31]) );
AO22XLTS U792 ( .A0(n380), .A1(d_ff_Zn[0]), .B0(n381), .B1(d_ff1_Z[0]), .Y(
first_mux_Z[0]) );
AO22XLTS U793 ( .A0(n382), .A1(d_ff_Zn[1]), .B0(n381), .B1(d_ff1_Z[1]), .Y(
first_mux_Z[1]) );
AO22XLTS U794 ( .A0(n380), .A1(d_ff_Zn[2]), .B0(n381), .B1(d_ff1_Z[2]), .Y(
first_mux_Z[2]) );
AO22XLTS U795 ( .A0(n382), .A1(d_ff_Zn[3]), .B0(n448), .B1(d_ff1_Z[3]), .Y(
first_mux_Z[3]) );
AO22XLTS U796 ( .A0(n380), .A1(d_ff_Zn[4]), .B0(n271), .B1(d_ff1_Z[4]), .Y(
first_mux_Z[4]) );
AO22XLTS U797 ( .A0(n382), .A1(d_ff_Zn[5]), .B0(n271), .B1(d_ff1_Z[5]), .Y(
first_mux_Z[5]) );
AO22XLTS U798 ( .A0(n380), .A1(d_ff_Zn[6]), .B0(n271), .B1(d_ff1_Z[6]), .Y(
first_mux_Z[6]) );
AO22XLTS U799 ( .A0(n265), .A1(d_ff_Zn[7]), .B0(n271), .B1(d_ff1_Z[7]), .Y(
first_mux_Z[7]) );
AO22XLTS U800 ( .A0(n382), .A1(d_ff_Zn[8]), .B0(n271), .B1(d_ff1_Z[8]), .Y(
first_mux_Z[8]) );
AO22XLTS U801 ( .A0(n382), .A1(d_ff_Zn[9]), .B0(n271), .B1(d_ff1_Z[9]), .Y(
first_mux_Z[9]) );
AO22XLTS U802 ( .A0(n380), .A1(d_ff_Zn[10]), .B0(n271), .B1(d_ff1_Z[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U803 ( .A0(n382), .A1(d_ff_Zn[11]), .B0(n271), .B1(d_ff1_Z[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U804 ( .A0(n380), .A1(d_ff_Zn[12]), .B0(n271), .B1(d_ff1_Z[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U805 ( .A0(n265), .A1(d_ff_Zn[13]), .B0(n271), .B1(d_ff1_Z[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U806 ( .A0(n380), .A1(d_ff_Zn[14]), .B0(n271), .B1(d_ff1_Z[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U807 ( .A0(n270), .A1(d_ff_Zn[15]), .B0(n271), .B1(d_ff1_Z[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U808 ( .A0(n380), .A1(d_ff_Zn[16]), .B0(n271), .B1(d_ff1_Z[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U809 ( .A0(n382), .A1(d_ff_Zn[31]), .B0(n381), .B1(d_ff1_Z[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U810 ( .A0(n383), .A1(d_ff_Yn[3]), .B0(n452), .B1(d_ff_Xn[3]), .Y(
mux_sal[3]) );
AO22XLTS U811 ( .A0(n267), .A1(d_ff_Yn[5]), .B0(n452), .B1(d_ff_Xn[5]), .Y(
mux_sal[5]) );
BUFX3TS U812 ( .A(n386), .Y(n385) );
XNOR2X1TS U813 ( .A(data_output2_31_), .B(n388), .Y(sign_inv_out[31]) );
AOI21X1TS U814 ( .A0(n273), .A1(n436), .B0(cont_iter_out[3]), .Y(n389) );
OAI32X1TS U815 ( .A0(n436), .A1(cont_iter_out[3]), .A2(n273), .B0(n389),
.B1(n402), .Y(data_out_LUT[10]) );
AO21XLTS U816 ( .A0(n400), .A1(n399), .B0(data_out_LUT[10]), .Y(
data_out_LUT[0]) );
NAND2X1TS U817 ( .A(n393), .B(n390), .Y(n391) );
NAND2X1TS U818 ( .A(n392), .B(n391), .Y(data_out_LUT[6]) );
AO21XLTS U819 ( .A0(n399), .A1(data_out_LUT[8]), .B0(data_out_LUT[16]), .Y(
data_out_LUT[9]) );
AOI21X1TS U820 ( .A0(cont_iter_out[1]), .A1(n400), .B0(n393), .Y(n394) );
OAI21X1TS U821 ( .A0(cont_iter_out[3]), .A1(n395), .B0(n394), .Y(
data_out_LUT[12]) );
NAND3XLTS U822 ( .A(n451), .B(n438), .C(n436), .Y(n396) );
AO21XLTS U823 ( .A0(n399), .A1(data_out_LUT[8]), .B0(data_out_LUT[18]), .Y(
data_out_LUT[21]) );
OAI2BB2XLTS U824 ( .B0(n402), .B1(n401), .A0N(n436), .A1N(n400), .Y(
data_out_LUT[2]) );
AOI2BB2XLTS U825 ( .B0(n273), .B1(data_out_LUT[22]), .A0N(data_out_LUT[22]),
.A1N(n273), .Y(data_out_LUT[23]) );
AOI32X1TS U826 ( .A0(n451), .A1(n403), .A2(cont_iter_out[1]), .B0(n402),
.B1(n403), .Y(data_out_LUT[25]) );
CLKAND2X2TS U827 ( .A(d_ff_Xn[0]), .B(n405), .Y(first_mux_X[0]) );
NAND2BXLTS U828 ( .AN(d_ff_Xn[1]), .B(n406), .Y(first_mux_X[1]) );
NAND2BXLTS U829 ( .AN(d_ff_Xn[2]), .B(n406), .Y(first_mux_X[2]) );
NAND2BXLTS U830 ( .AN(d_ff_Xn[3]), .B(n406), .Y(first_mux_X[3]) );
CLKAND2X2TS U831 ( .A(d_ff_Xn[4]), .B(n405), .Y(first_mux_X[4]) );
NAND2BXLTS U832 ( .AN(d_ff_Xn[5]), .B(n406), .Y(first_mux_X[5]) );
NAND2BXLTS U833 ( .AN(d_ff_Xn[7]), .B(n406), .Y(first_mux_X[7]) );
CLKAND2X2TS U834 ( .A(d_ff_Xn[8]), .B(n405), .Y(first_mux_X[8]) );
CLKAND2X2TS U835 ( .A(d_ff_Xn[9]), .B(n405), .Y(first_mux_X[9]) );
NAND2BXLTS U836 ( .AN(d_ff_Xn[10]), .B(n406), .Y(first_mux_X[10]) );
CLKAND2X2TS U837 ( .A(d_ff_Xn[11]), .B(n406), .Y(first_mux_X[11]) );
NAND2BXLTS U838 ( .AN(d_ff_Xn[13]), .B(n406), .Y(first_mux_X[13]) );
NAND2BXLTS U839 ( .AN(d_ff_Xn[14]), .B(n406), .Y(first_mux_X[14]) );
CLKAND2X2TS U840 ( .A(d_ff_Xn[15]), .B(n406), .Y(first_mux_X[15]) );
CLKAND2X2TS U841 ( .A(d_ff_Xn[18]), .B(n405), .Y(first_mux_X[18]) );
CLKAND2X2TS U842 ( .A(d_ff_Xn[21]), .B(n406), .Y(first_mux_X[21]) );
CLKAND2X2TS U843 ( .A(d_ff_Xn[22]), .B(n405), .Y(first_mux_X[22]) );
CLKAND2X2TS U844 ( .A(d_ff_Xn[23]), .B(n406), .Y(first_mux_X[23]) );
CLKAND2X2TS U845 ( .A(d_ff_Xn[30]), .B(n405), .Y(first_mux_X[30]) );
CLKAND2X2TS U846 ( .A(d_ff_Xn[31]), .B(n406), .Y(first_mux_X[31]) );
AO22XLTS U847 ( .A0(n408), .A1(d_ff3_sh_x_out[31]), .B0(n407), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U848 ( .A0(n408), .A1(d_ff3_sh_x_out[30]), .B0(n407), .B1(
d_ff3_sh_y_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U849 ( .A0(n422), .A1(d_ff3_sh_x_out[29]), .B0(n421), .B1(
d_ff3_sh_y_out[29]), .Y(n409) );
NAND2X1TS U850 ( .A(n429), .B(d_ff3_LUT_out[27]), .Y(n411) );
NAND2X1TS U851 ( .A(n409), .B(n411), .Y(add_subt_dataB[29]) );
AOI22X1TS U852 ( .A0(n422), .A1(d_ff3_sh_x_out[28]), .B0(n421), .B1(
d_ff3_sh_y_out[28]), .Y(n410) );
NAND2X1TS U853 ( .A(n410), .B(n411), .Y(add_subt_dataB[28]) );
AOI22X1TS U854 ( .A0(n422), .A1(d_ff3_sh_x_out[27]), .B0(n421), .B1(
d_ff3_sh_y_out[27]), .Y(n412) );
NAND2X1TS U855 ( .A(n412), .B(n411), .Y(add_subt_dataB[27]) );
AOI22X1TS U856 ( .A0(n422), .A1(d_ff3_sh_x_out[22]), .B0(n421), .B1(
d_ff3_sh_y_out[22]), .Y(n413) );
OAI2BB1X1TS U857 ( .A0N(n429), .A1N(d_ff3_LUT_out[22]), .B0(n413), .Y(
add_subt_dataB[22]) );
AOI22X1TS U858 ( .A0(n422), .A1(d_ff3_sh_x_out[20]), .B0(n421), .B1(
d_ff3_sh_y_out[20]), .Y(n414) );
NAND2X1TS U859 ( .A(n429), .B(d_ff3_LUT_out[20]), .Y(n417) );
NAND2X1TS U860 ( .A(n414), .B(n417), .Y(add_subt_dataB[20]) );
AOI22X1TS U861 ( .A0(n422), .A1(d_ff3_sh_x_out[19]), .B0(n421), .B1(
d_ff3_sh_y_out[19]), .Y(n415) );
OAI2BB1X1TS U862 ( .A0N(n429), .A1N(d_ff3_LUT_out[22]), .B0(n415), .Y(
add_subt_dataB[19]) );
AOI22X1TS U863 ( .A0(n422), .A1(d_ff3_sh_x_out[17]), .B0(n421), .B1(
d_ff3_sh_y_out[17]), .Y(n416) );
NAND2X1TS U864 ( .A(n416), .B(n417), .Y(add_subt_dataB[17]) );
AOI22X1TS U865 ( .A0(n422), .A1(d_ff3_sh_x_out[15]), .B0(n421), .B1(
d_ff3_sh_y_out[15]), .Y(n418) );
NAND2X1TS U866 ( .A(n418), .B(n417), .Y(add_subt_dataB[15]) );
AOI22X1TS U867 ( .A0(n427), .A1(d_ff3_sh_x_out[13]), .B0(n426), .B1(
d_ff3_sh_y_out[13]), .Y(n419) );
OAI2BB1X1TS U868 ( .A0N(n425), .A1N(d_ff3_LUT_out[18]), .B0(n419), .Y(
add_subt_dataB[13]) );
AOI22X1TS U869 ( .A0(n422), .A1(d_ff3_sh_x_out[11]), .B0(n421), .B1(
d_ff3_sh_y_out[11]), .Y(n420) );
OAI2BB1X1TS U870 ( .A0N(n425), .A1N(d_ff3_LUT_out[11]), .B0(n420), .Y(
add_subt_dataB[11]) );
AOI22X1TS U871 ( .A0(n422), .A1(d_ff3_sh_x_out[7]), .B0(n421), .B1(
d_ff3_sh_y_out[7]), .Y(n423) );
OAI2BB1X1TS U872 ( .A0N(n425), .A1N(d_ff3_LUT_out[11]), .B0(n423), .Y(
add_subt_dataB[7]) );
AOI22X1TS U873 ( .A0(n427), .A1(d_ff3_sh_x_out[5]), .B0(n426), .B1(
d_ff3_sh_y_out[5]), .Y(n424) );
OAI2BB1X1TS U874 ( .A0N(n425), .A1N(d_ff3_LUT_out[14]), .B0(n424), .Y(
add_subt_dataB[5]) );
AOI22X1TS U875 ( .A0(n427), .A1(d_ff3_sh_x_out[3]), .B0(n426), .B1(
d_ff3_sh_y_out[3]), .Y(n428) );
OAI2BB1X1TS U876 ( .A0N(n429), .A1N(d_ff3_LUT_out[16]), .B0(n428), .Y(
add_subt_dataB[3]) );
XNOR2X1TS U877 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(op_add_subt) );
NOR2XLTS U879 ( .A(d_ff2_Y[29]), .B(n431), .Y(n430) );
XNOR2X1TS U880 ( .A(d_ff2_Y[29]), .B(n431), .Y(sh_exp_y[6]) );
AO21XLTS U881 ( .A0(intadd_414_n1), .A1(d_ff2_Y[27]), .B0(n432), .Y(
sh_exp_y[4]) );
NOR2XLTS U882 ( .A(d_ff2_X[29]), .B(n434), .Y(n433) );
XNOR2X1TS U883 ( .A(d_ff2_X[29]), .B(n434), .Y(sh_exp_x[6]) );
AO21XLTS U884 ( .A0(intadd_413_n1), .A1(d_ff2_X[27]), .B0(n435), .Y(
sh_exp_x[4]) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
/*
Copyright (c) 2020-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
input wire uart_rts,
output wire uart_cts,
/*
* Ethernet: SFP+
*/
input wire sfp0_tx_clk,
input wire sfp0_tx_rst,
output wire [63:0] sfp0_txd,
output wire [7:0] sfp0_txc,
input wire sfp0_rx_clk,
input wire sfp0_rx_rst,
input wire [63:0] sfp0_rxd,
input wire [7:0] sfp0_rxc,
input wire sfp1_tx_clk,
input wire sfp1_tx_rst,
output wire [63:0] sfp1_txd,
output wire [7:0] sfp1_txc,
input wire sfp1_rx_clk,
input wire sfp1_rx_rst,
input wire [63:0] sfp1_rxd,
input wire [7:0] sfp1_rxc
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = ~match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((~match_cond_reg & ~no_match_reg) |
(rx_udp_payload_axis_tvalid & rx_udp_payload_axis_tready & rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid & match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready & match_cond) | no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid & match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready & match_cond_reg) | no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid & ~valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign led = led_reg;
assign sfp1_txd = 64'h0707070707070707;
assign sfp1_txc = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(sfp0_rx_clk),
.rx_rst(sfp0_rx_rst),
.tx_clk(sfp0_tx_clk),
.tx_rst(sfp0_tx_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(sfp0_rxd),
.xgmii_rxc(sfp0_rxc),
.xgmii_txd(sfp0_txd),
.xgmii_txc(sfp0_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
`timescale 1 ns / 1 ps
module axi_bram_writer #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
output wire [BRAM_DATA_WIDTH/8-1:0] bram_porta_we
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
reg int_awready_reg, int_awready_next;
reg int_wready_reg, int_wready_next;
reg int_bvalid_reg, int_bvalid_next;
wire int_wvalid_wire;
assign int_wvalid_wire = s_axi_awvalid & s_axi_wvalid;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awready_reg <= 1'b0;
int_wready_reg <= 1'b0;
int_bvalid_reg <= 1'b0;
end
else
begin
int_awready_reg <= int_awready_next;
int_wready_reg <= int_wready_next;
int_bvalid_reg <= int_bvalid_next;
end
end
always @*
begin
int_awready_next = int_awready_reg;
int_wready_next = int_wready_reg;
int_bvalid_next = int_bvalid_reg;
if(int_wvalid_wire & ~int_awready_reg)
begin
int_awready_next = 1'b1;
int_wready_next = 1'b1;
end
if(int_awready_reg)
begin
int_awready_next = 1'b0;
int_wready_next = 1'b0;
int_bvalid_next = 1'b1;
end
if(s_axi_bready & int_bvalid_reg)
begin
int_bvalid_next = 1'b0;
end
end
assign s_axi_bresp = 2'd0;
assign s_axi_awready = int_awready_reg;
assign s_axi_wready = int_wready_reg;
assign s_axi_bvalid = int_bvalid_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = s_axi_awaddr[ADDR_LSB+BRAM_ADDR_WIDTH-1:ADDR_LSB];
assign bram_porta_wrdata = s_axi_wdata;
assign bram_porta_we = int_wvalid_wire ? s_axi_wstrb : {(BRAM_DATA_WIDTH/8){1'b0}};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O21BAI_BEHAVIORAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_BEHAVIORAL_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_fe1
//
// Generated
// by: lutscher
// on: Wed Dec 14 16:43:27 2005
// cmd: /home/lutscher/work/MIX/mix_0.pl -strip -nodelta ../../reg_shell.sxc
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: lutscher $
// $Id: rs_fe1.v,v 1.8 2005/12/14 15:43:45 lutscher Exp $
// $Date: 2005/12/14 15:43:45 $
// $Log: rs_fe1.v,v $
// Revision 1.8 2005/12/14 15:43:45 lutscher
// updated
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.43 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_fe1
//
// No user `defines in this module
module rs_fe1
//
// Generated module rs_fe1_i
//
(
input wire clk_f20,
input wire res_f20_n_i,
input wire mreset_n_i,
input wire [2:0] mcmd_i,
input wire [13:0] maddr_i,
input wire [31:0] mdata_i,
input wire mrespaccept_i,
output wire scmdaccept_o,
output wire [1:0] sresp_o,
output wire [31:0] sdata_o,
input wire clk_a,
input wire res_a_n_i,
input wire test_i,
output wire Cvbsdetect_par_o,
input wire Cvbsdetect_set_p_i,
input wire ycdetect_par_i,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output wire usr_r_test_rd_p_o,
input wire [7:0] sha_r_test_par_i,
output wire [4:0] mvstart_par_o,
output wire [5:0] mvstop_par_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_par_i,
input wire usr_rw_test_trans_done_p_i,
output wire usr_rw_test_rd_p_o,
output wire usr_rw_test_wr_p_o,
output wire [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i,
output wire [3:0] dgatel_par_o,
output wire [4:0] dgates_par_o,
output wire [2:0] dummy_fe_par_o,
output wire [3:0] usr_w_test_par_o,
input wire usr_w_test_trans_done_p_i,
output wire usr_w_test_wr_p_o,
output wire [3:0] w_test_par_o,
output wire [3:0] sha_w_test_par_o,
input wire [2:0] r_test_par_i,
input wire upd_w_en_i,
input wire upd_w_force_i,
input wire upd_w_i
);
// Module parameters:
parameter cgtransp = 0;
parameter P_TOCNT_WIDTH = 10;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [13:0] addr;
wire [31:0] rd_data;
wire [63:0] rd_data_vec;
wire rd_err;
wire [1:0] rd_err_vec;
wire rd_wr;
wire trans_done;
wire [1:0] trans_done_vec;
wire trans_start;
wire [31:0] wr_data;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for rs_cfg_fe1_clk_a_i
rs_cfg_fe1_clk_a #(
.cgtransp(cgtransp), // __W_ILLEGAL_PARAM
.sync(1)
) rs_cfg_fe1_clk_a_i ( // Config register module for clock domain 'clk_a'
.addr_i(addr),
.clk_a(clk_a),
.dgatel_par_o(dgatel_par_o),
.dgates_par_o(dgates_par_o),
.dummy_fe_par_o(dummy_fe_par_o),
.r_test_par_i(r_test_par_i),
.rd_data_o(rd_data_vec[31:0]),
.rd_err_o(rd_err_vec[0]),
.rd_wr_i(rd_wr),
.res_a_n_i(res_a_n_i),
.sha_w_test_par_o(sha_w_test_par_o),
.test_i(test_i),
.trans_done_o(trans_done_vec[0]),
.trans_start(trans_start),
.upd_w_en_i(upd_w_en_i),
.upd_w_force_i(upd_w_force_i),
.upd_w_i(upd_w_i),
.usr_w_test_par_o(usr_w_test_par_o),
.usr_w_test_trans_done_p_i(usr_w_test_trans_done_p_i),
.usr_w_test_wr_p_o(usr_w_test_wr_p_o),
.w_test_par_o(w_test_par_o),
.wr_data_i(wr_data)
);
// End of Generated Instance Port Map for rs_cfg_fe1_clk_a_i
// Generated Instance Port Map for rs_cfg_fe1_i
rs_cfg_fe1 #(
.cgtransp(cgtransp), // __W_ILLEGAL_PARAM
.sync(0)
) rs_cfg_fe1_i ( // Config register module
.Cvbsdetect_par_o(Cvbsdetect_par_o),
.Cvbsdetect_set_p_i(Cvbsdetect_set_p_i),
.addr_i(addr),
.clk_f20(clk_f20),
.mvstart_par_o(mvstart_par_o),
.mvstop_par_o(mvstop_par_o),
.rd_data_o(rd_data_vec[63:32]),
.rd_err_o(rd_err_vec[1]),
.rd_wr_i(rd_wr),
.res_f20_n_i(res_f20_n_i),
.sha_r_test_par_i(sha_r_test_par_i),
.sha_rw2_par_o(sha_rw2_par_o),
.test_i(test_i),
.trans_done_o(trans_done_vec[1]),
.trans_start(trans_start),
.upd_r_en_i(upd_r_en_i),
.upd_r_force_i(upd_r_force_i),
.upd_r_i(upd_r_i),
.upd_rw_en_i(upd_rw_en_i),
.upd_rw_force_i(upd_rw_force_i),
.upd_rw_i(upd_rw_i),
.usr_r_test_par_i(usr_r_test_par_i),
.usr_r_test_rd_p_o(usr_r_test_rd_p_o),
.usr_r_test_trans_done_p_i(usr_r_test_trans_done_p_i),
.usr_rw_test_par_i(usr_rw_test_par_i),
.usr_rw_test_par_o(usr_rw_test_par_o),
.usr_rw_test_rd_p_o(usr_rw_test_rd_p_o),
.usr_rw_test_trans_done_p_i(usr_rw_test_trans_done_p_i),
.usr_rw_test_wr_p_o(usr_rw_test_wr_p_o),
.wd_16_test2_par_o(wd_16_test2_par_o),
.wd_16_test_par_o(wd_16_test_par_o),
.wr_data_i(wr_data),
.ycdetect_par_i(ycdetect_par_i)
);
// End of Generated Instance Port Map for rs_cfg_fe1_i
// Generated Instance Port Map for u0_ocp_target_i
ocp_target #(
.P_AWIDTH(14),
.P_DWIDTH(32),
.P_TOCNT_WIDTH(P_TOCNT_WIDTH), // __W_ILLEGAL_PARAM
.sync(0)
) u0_ocp_target_i ( // OCP target module
.addr_o(addr),
.clk_i(clk_f20),
.maddr_i(maddr_i),
.mcmd_i(mcmd_i),
.mdata_i(mdata_i),
.mreset_n_i(mreset_n_i),
.mrespaccept_i(mrespaccept_i),
.rd_data_i(rd_data),
.rd_err_i(rd_err),
.rd_wr_o(rd_wr),
.reset_n_i(res_f20_n_i),
.scmdaccept_o(scmdaccept_o),
.sdata_o(sdata_o),
.sresp_o(sresp_o),
.trans_done_i(trans_done),
.trans_start_o(trans_start),
.wr_data_o(wr_data)
);
// End of Generated Instance Port Map for u0_ocp_target_i
// Generated Instance Port Map for u1_rs_mcda_i
rs_mcda #(
.N_DOMAINS(2),
.N_SYNCDOM(1),
.P_DWIDTH(32)
) u1_rs_mcda_i ( // Multi-clock-domain Adapter
.clk_ocp(clk_f20),
.mreset_n_i(mreset_n_i),
.rd_data_o(rd_data),
.rd_data_vec_i(rd_data_vec),
.rd_err_o(rd_err),
.rd_err_vec_i(rd_err_vec),
.rst_ocp_n_i(res_f20_n_i),
.trans_done_o(trans_done),
.trans_done_vec_i(trans_done_vec),
.trans_start_i(trans_start)
);
// End of Generated Instance Port Map for u1_rs_mcda_i
endmodule
//
// End of Generated Module rtl of rs_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:36
`timescale 1 ps / 1 ps
module system_mm_interconnect_0 (
input wire acl_iface_kernel_clk_clk, // acl_iface_kernel_clk.clk
input wire Erosion_system_clock_reset_reset_reset_bridge_in_reset_reset, // Erosion_system_clock_reset_reset_reset_bridge_in_reset.reset
input wire [29:0] Erosion_system_avm_memgmem0_port_0_0_rw_address, // Erosion_system_avm_memgmem0_port_0_0_rw.address
output wire Erosion_system_avm_memgmem0_port_0_0_rw_waitrequest, // .waitrequest
input wire [4:0] Erosion_system_avm_memgmem0_port_0_0_rw_burstcount, // .burstcount
input wire [31:0] Erosion_system_avm_memgmem0_port_0_0_rw_byteenable, // .byteenable
input wire Erosion_system_avm_memgmem0_port_0_0_rw_read, // .read
output wire [255:0] Erosion_system_avm_memgmem0_port_0_0_rw_readdata, // .readdata
output wire Erosion_system_avm_memgmem0_port_0_0_rw_readdatavalid, // .readdatavalid
input wire Erosion_system_avm_memgmem0_port_0_0_rw_write, // .write
input wire [255:0] Erosion_system_avm_memgmem0_port_0_0_rw_writedata, // .writedata
output wire [29:0] acl_iface_kernel_mem0_address, // acl_iface_kernel_mem0.address
output wire acl_iface_kernel_mem0_write, // .write
output wire acl_iface_kernel_mem0_read, // .read
input wire [255:0] acl_iface_kernel_mem0_readdata, // .readdata
output wire [255:0] acl_iface_kernel_mem0_writedata, // .writedata
output wire [4:0] acl_iface_kernel_mem0_burstcount, // .burstcount
output wire [31:0] acl_iface_kernel_mem0_byteenable, // .byteenable
input wire acl_iface_kernel_mem0_readdatavalid, // .readdatavalid
input wire acl_iface_kernel_mem0_waitrequest, // .waitrequest
output wire acl_iface_kernel_mem0_debugaccess // .debugaccess
);
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest; // acl_iface_kernel_mem0_translator:uav_waitrequest -> Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_waitrequest
wire [9:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_burstcount -> acl_iface_kernel_mem0_translator:uav_burstcount
wire [255:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_writedata -> acl_iface_kernel_mem0_translator:uav_writedata
wire [29:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_address -> acl_iface_kernel_mem0_translator:uav_address
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_lock -> acl_iface_kernel_mem0_translator:uav_lock
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_write -> acl_iface_kernel_mem0_translator:uav_write
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_read -> acl_iface_kernel_mem0_translator:uav_read
wire [255:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata; // acl_iface_kernel_mem0_translator:uav_readdata -> Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_readdata
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_debugaccess -> acl_iface_kernel_mem0_translator:uav_debugaccess
wire [31:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_byteenable -> acl_iface_kernel_mem0_translator:uav_byteenable
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid; // acl_iface_kernel_mem0_translator:uav_readdatavalid -> Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (1),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) erosion_system_avm_memgmem0_port_0_0_rw_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (Erosion_system_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Erosion_system_avm_memgmem0_port_0_0_rw_address), // avalon_anti_master_0.address
.av_waitrequest (Erosion_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.av_burstcount (Erosion_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.av_byteenable (Erosion_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.av_read (Erosion_system_avm_memgmem0_port_0_0_rw_read), // .read
.av_readdata (Erosion_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.av_readdatavalid (Erosion_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.av_write (Erosion_system_avm_memgmem0_port_0_0_rw_write), // .write
.av_writedata (Erosion_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_iface_kernel_mem0_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (Erosion_system_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (acl_iface_kernel_mem0_address), // avalon_anti_slave_0.address
.av_write (acl_iface_kernel_mem0_write), // .write
.av_read (acl_iface_kernel_mem0_read), // .read
.av_readdata (acl_iface_kernel_mem0_readdata), // .readdata
.av_writedata (acl_iface_kernel_mem0_writedata), // .writedata
.av_burstcount (acl_iface_kernel_mem0_burstcount), // .burstcount
.av_byteenable (acl_iface_kernel_mem0_byteenable), // .byteenable
.av_readdatavalid (acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.av_waitrequest (acl_iface_kernel_mem0_waitrequest), // .waitrequest
.av_debugaccess (acl_iface_kernel_mem0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_crossbar_v2_1_8_axi_crossbar,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_TEST_xbar_0,axi_crossbar_v2_1_8_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "design_TEST_xbar_0,axi_crossbar_v2_1_8_axi_crossbar,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000404100000000000040400000,C_M_AXI_ADDR_WIDTH=0x0000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_M_AXI_READ_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x0000000100000001,C_M_AXI_READ_ISSUING=0x0000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_TEST_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_8_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H00000000404100000000000040400000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(64'H0000000100000001),
.C_M_AXI_READ_ISSUING(64'H0000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(2'H3),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
wire req0, req1, req2;
wire ack0, ack1, ack2;
reg req0_reg;
assign req0 = req0_reg;
wire [7:0] data0;
reg [7:0] data0_reg;
wire [7:0] data1;
wire [7:0] data2;
wire [7:0] data3;
assign data0 = data0_reg;
// two_phase_event_gen U_PORT1_EVENT_GEN (
// .run(rst_async_n),
// .req(req0),
// .ack(a)
// );
mousetrap_elt U_MOUSETRAP_STAGE0(
.ackNm1(a),
.reqN(req0),
.ackN(ack0),
.doneN(done0),
.datain(data0),
.dataout(data1),
.rstn(rst_async_n)
);
buff #(.DELAY(20)) U_DELAY0(.i(done0), .z(req1));
mousetrap_elt U_MOUSETRAP_STAGE1(
.ackNm1(ack0),
.reqN(req1),
.ackN(ack1),
.doneN(done1),
.datain(data1),
.dataout(data2),
.rstn(rst_async_n)
);
buff #(.DELAY(20)) U_DELAY1(.i(done1), .z(req2));
mousetrap_elt U_MOUSETRAP_STAGE2(
.ackNm1(ack1),
.reqN(req2),
.ackN(ack2),
.doneN(done2),
.datain(data2),
.dataout(data3),
.rstn(rst_async_n)
);
buff #(.DELAY(20)) U_DELAY2(.i(done2), .z(req3));
// two_phase_slave U_SLAVE(.req(req3), .ack(ack2));
assign #30 ack2_tmp = req3;
assign ack2 = (ack2_tmp === 1'b1);
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n <= 1'b0;
data0_reg <= 8'h00;
req0_reg <= 0;
// Wait long enough for the X's in the delay elements to disappears
#500;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#10;
data0_reg <= 8'hAA;
#1;
req0_reg <= 1'b1;
wait(a === 1'b1);
#30;
data0_reg <= 8'h55;
#1;
req0_reg <= !req0_reg;
wait(a === 1'b0);
#10;
data0_reg <= 8'hBB;
#1;
req0_reg <= 1'b1;
wait(a === 1'b1);
#10;
data0_reg <= 8'hCC;
#1;
req0_reg <= 1'b0;
wait(a === 1'b0);
#200000;
$display("-I- Done !");
$finish;
end
endmodule // tb
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 28.06.2017 17:24:09
// Design Name:
// Module Name: dmem
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dmem(
output [31:0] RD,
input [31:0] A, WD,
input WE, clk
);
reg [31:0] RAM [0:255];
assign RD = (A != 0) ? RAM[A[7:0]] : 0;
always @ (posedge clk)
if (WE)
RAM[A[7:0]] <= WD;
// when a 32 bit number is sent to the address field, this is the calculated
// address from the ALU. Meaning that the instruction is for "lw" or "sw".
// Another indicator for this is when the signal "MemWrite" is 1.
// All other times, "MemWrite" is 0, and the ALUResult that is sent to A
// is ignored.
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_PP_BLACKBOX_V
|
//======================================================================
//
// Module Name: WHIRLPOOL_WCIPHER_ROUND
// Description: Top-level Round function of Whirlpool W-Cipher
//
// Language: Verilog-2001
//
// Module Dependencies:
// WHIRLPOOL_WCIPHER_PI
// WHIRLPOOL_WCIPHER_MU
// WHIRLPOOL_WCIPHER_THETA
// WHIRLPOOL_WCIPHER_MU_INVERSE
// WHIRLPOOL_WCIPHER_GAMMA
//
// Developer: Saied H. Khayat
// URL: https://github.com/saiedhk
// Date: May 2014
//
// Copyright Notice: Free use of this library is permitted under the
// guidelines and in accordance with the MIT License (MIT).
// http://opensource.org/licenses/MIT
//
//======================================================================
`timescale 1ns/1ps
//`define DEBUG
module WHIRLPOOL_WCIPHER_ROUND (
output [0:511] odata,
input [0:511] idata,
input [0:511] subkey
);
//---------wires, registers----------
wire [7:0] A00, A01, A02, A03, A04, A05, A06, A07,
A10, A11, A12, A13, A14, A15, A16, A17,
A20, A21, A22, A23, A24, A25, A26, A27,
A30, A31, A32, A33, A34, A35, A36, A37,
A40, A41, A42, A43, A44, A45, A46, A47,
A50, A51, A52, A53, A54, A55, A56, A57,
A60, A61, A62, A63, A64, A65, A66, A67,
A70, A71, A72, A73, A74, A75, A76, A77;
wire [7:0] B00, B01, B02, B03, B04, B05, B06, B07,
B10, B11, B12, B13, B14, B15, B16, B17,
B20, B21, B22, B23, B24, B25, B26, B27,
B30, B31, B32, B33, B34, B35, B36, B37,
B40, B41, B42, B43, B44, B45, B46, B47,
B50, B51, B52, B53, B54, B55, B56, B57,
B60, B61, B62, B63, B64, B65, B66, B67,
B70, B71, B72, B73, B74, B75, B76, B77;
wire [7:0] C00, C01, C02, C03, C04, C05, C06, C07,
C10, C11, C12, C13, C14, C15, C16, C17,
C20, C21, C22, C23, C24, C25, C26, C27,
C30, C31, C32, C33, C34, C35, C36, C37,
C40, C41, C42, C43, C44, C45, C46, C47,
C50, C51, C52, C53, C54, C55, C56, C57,
C60, C61, C62, C63, C64, C65, C66, C67,
C70, C71, C72, C73, C74, C75, C76, C77;
wire [7:0] D00, D01, D02, D03, D04, D05, D06, D07,
D10, D11, D12, D13, D14, D15, D16, D17,
D20, D21, D22, D23, D24, D25, D26, D27,
D30, D31, D32, D33, D34, D35, D36, D37,
D40, D41, D42, D43, D44, D45, D46, D47,
D50, D51, D52, D53, D54, D55, D56, D57,
D60, D61, D62, D63, D64, D65, D66, D67,
D70, D71, D72, D73, D74, D75, D76, D77;
wire [0:511] E;
//---------instantiations--------------------
// turn input bit vector into internal state matrix
WHIRLPOOL_WCIPHER_MU whirlpool_wcipher_mu
(
// outputs
.B00(A00), .B01(A01), .B02(A02), .B03(A03), .B04(A04), .B05(A05), .B06(A06), .B07(A07),
.B10(A10), .B11(A11), .B12(A12), .B13(A13), .B14(A14), .B15(A15), .B16(A16), .B17(A17),
.B20(A20), .B21(A21), .B22(A22), .B23(A23), .B24(A24), .B25(A25), .B26(A26), .B27(A27),
.B30(A30), .B31(A31), .B32(A32), .B33(A33), .B34(A34), .B35(A35), .B36(A36), .B37(A37),
.B40(A40), .B41(A41), .B42(A42), .B43(A43), .B44(A44), .B45(A45), .B46(A46), .B47(A47),
.B50(A50), .B51(A51), .B52(A52), .B53(A53), .B54(A54), .B55(A55), .B56(A56), .B57(A57),
.B60(A60), .B61(A61), .B62(A62), .B63(A63), .B64(A64), .B65(A65), .B66(A66), .B67(A67),
.B70(A70), .B71(A71), .B72(A72), .B73(A73), .B74(A74), .B75(A75), .B76(A76), .B77(A77),
// input
.A(idata)
);
// Sub-byte operation (Gamma Function)
WHIRLPOOL_WCIPHER_GAMMA whirlpool_wcipher_gamma
(
// outputs
.B00(B00), .B01(B01), .B02(B02), .B03(B03), .B04(B04), .B05(B05), .B06(B06), .B07(B07),
.B10(B10), .B11(B11), .B12(B12), .B13(B13), .B14(B14), .B15(B15), .B16(B16), .B17(B17),
.B20(B20), .B21(B21), .B22(B22), .B23(B23), .B24(B24), .B25(B25), .B26(B26), .B27(B27),
.B30(B30), .B31(B31), .B32(B32), .B33(B33), .B34(B34), .B35(B35), .B36(B36), .B37(B37),
.B40(B40), .B41(B41), .B42(B42), .B43(B43), .B44(B44), .B45(B45), .B46(B46), .B47(B47),
.B50(B50), .B51(B51), .B52(B52), .B53(B53), .B54(B54), .B55(B55), .B56(B56), .B57(B57),
.B60(B60), .B61(B61), .B62(B62), .B63(B63), .B64(B64), .B65(B65), .B66(B66), .B67(B67),
.B70(B70), .B71(B71), .B72(B72), .B73(B73), .B74(B74), .B75(B75), .B76(B76), .B77(B77),
// inputs
.A00(A00), .A01(A01), .A02(A02), .A03(A03), .A04(A04), .A05(A05), .A06(A06), .A07(A07),
.A10(A10), .A11(A11), .A12(A12), .A13(A13), .A14(A14), .A15(A15), .A16(A16), .A17(A17),
.A20(A20), .A21(A21), .A22(A22), .A23(A23), .A24(A24), .A25(A25), .A26(A26), .A27(A27),
.A30(A30), .A31(A31), .A32(A32), .A33(A33), .A34(A34), .A35(A35), .A36(A36), .A37(A37),
.A40(A40), .A41(A41), .A42(A42), .A43(A43), .A44(A44), .A45(A45), .A46(A46), .A47(A47),
.A50(A50), .A51(A51), .A52(A52), .A53(A53), .A54(A54), .A55(A55), .A56(A56), .A57(A57),
.A60(A60), .A61(A61), .A62(A62), .A63(A63), .A64(A64), .A65(A65), .A66(A66), .A67(A67),
.A70(A70), .A71(A71), .A72(A72), .A73(A73), .A74(A74), .A75(A75), .A76(A76), .A77(A77)
);
// ShiftColumn operation (Pi Function)
WHIRLPOOL_WCIPHER_PI whirlpool_wcipher_pi
(
// outputs
.B00(C00), .B01(C01), .B02(C02), .B03(C03), .B04(C04), .B05(C05), .B06(C06), .B07(C07),
.B10(C10), .B11(C11), .B12(C12), .B13(C13), .B14(C14), .B15(C15), .B16(C16), .B17(C17),
.B20(C20), .B21(C21), .B22(C22), .B23(C23), .B24(C24), .B25(C25), .B26(C26), .B27(C27),
.B30(C30), .B31(C31), .B32(C32), .B33(C33), .B34(C34), .B35(C35), .B36(C36), .B37(C37),
.B40(C40), .B41(C41), .B42(C42), .B43(C43), .B44(C44), .B45(C45), .B46(C46), .B47(C47),
.B50(C50), .B51(C51), .B52(C52), .B53(C53), .B54(C54), .B55(C55), .B56(C56), .B57(C57),
.B60(C60), .B61(C61), .B62(C62), .B63(C63), .B64(C64), .B65(C65), .B66(C66), .B67(C67),
.B70(C70), .B71(C71), .B72(C72), .B73(C73), .B74(C74), .B75(C75), .B76(C76), .B77(C77),
// inputs
.A00(B00), .A01(B01), .A02(B02), .A03(B03), .A04(B04), .A05(B05), .A06(B06), .A07(B07),
.A10(B10), .A11(B11), .A12(B12), .A13(B13), .A14(B14), .A15(B15), .A16(B16), .A17(B17),
.A20(B20), .A21(B21), .A22(B22), .A23(B23), .A24(B24), .A25(B25), .A26(B26), .A27(B27),
.A30(B30), .A31(B31), .A32(B32), .A33(B33), .A34(B34), .A35(B35), .A36(B36), .A37(B37),
.A40(B40), .A41(B41), .A42(B42), .A43(B43), .A44(B44), .A45(B45), .A46(B46), .A47(B47),
.A50(B50), .A51(B51), .A52(B52), .A53(B53), .A54(B54), .A55(B55), .A56(B56), .A57(B57),
.A60(B60), .A61(B61), .A62(B62), .A63(B63), .A64(B64), .A65(B65), .A66(B66), .A67(B67),
.A70(B70), .A71(B71), .A72(B72), .A73(B73), .A74(B74), .A75(B75), .A76(B76), .A77(B77)
);
// MixRow operation (Theta Function)
WHIRLPOOL_WCIPHER_THETA whirlpool_wcipher_theta
(
// outputs
.B00(D00), .B01(D01), .B02(D02), .B03(D03), .B04(D04), .B05(D05), .B06(D06), .B07(D07),
.B10(D10), .B11(D11), .B12(D12), .B13(D13), .B14(D14), .B15(D15), .B16(D16), .B17(D17),
.B20(D20), .B21(D21), .B22(D22), .B23(D23), .B24(D24), .B25(D25), .B26(D26), .B27(D27),
.B30(D30), .B31(D31), .B32(D32), .B33(D33), .B34(D34), .B35(D35), .B36(D36), .B37(D37),
.B40(D40), .B41(D41), .B42(D42), .B43(D43), .B44(D44), .B45(D45), .B46(D46), .B47(D47),
.B50(D50), .B51(D51), .B52(D52), .B53(D53), .B54(D54), .B55(D55), .B56(D56), .B57(D57),
.B60(D60), .B61(D61), .B62(D62), .B63(D63), .B64(D64), .B65(D65), .B66(D66), .B67(D67),
.B70(D70), .B71(D71), .B72(D72), .B73(D73), .B74(D74), .B75(D75), .B76(D76), .B77(D77),
// inputs
.A00(C00), .A01(C01), .A02(C02), .A03(C03), .A04(C04), .A05(C05), .A06(C06), .A07(C07),
.A10(C10), .A11(C11), .A12(C12), .A13(C13), .A14(C14), .A15(C15), .A16(C16), .A17(C17),
.A20(C20), .A21(C21), .A22(C22), .A23(C23), .A24(C24), .A25(C25), .A26(C26), .A27(C27),
.A30(C30), .A31(C31), .A32(C32), .A33(C33), .A34(C34), .A35(C35), .A36(C36), .A37(C37),
.A40(C40), .A41(C41), .A42(C42), .A43(C43), .A44(C44), .A45(C45), .A46(C46), .A47(C47),
.A50(C50), .A51(C51), .A52(C52), .A53(C53), .A54(C54), .A55(C55), .A56(C56), .A57(C57),
.A60(C60), .A61(C61), .A62(C62), .A63(C63), .A64(C64), .A65(C65), .A66(C66), .A67(C67),
.A70(C70), .A71(C71), .A72(C72), .A73(C73), .A74(C74), .A75(C75), .A76(C76), .A77(C77)
);
// turn state matrix into bit vector
WHIRLPOOL_WCIPHER_MU_INVERSE whirlpool_wcipher_mu_inverse
(
// outputs
.A(E[0:511]),
// input
.B00(D00), .B01(D01), .B02(D02), .B03(D03), .B04(D04), .B05(D05), .B06(D06), .B07(D07),
.B10(D10), .B11(D11), .B12(D12), .B13(D13), .B14(D14), .B15(D15), .B16(D16), .B17(D17),
.B20(D20), .B21(D21), .B22(D22), .B23(D23), .B24(D24), .B25(D25), .B26(D26), .B27(D27),
.B30(D30), .B31(D31), .B32(D32), .B33(D33), .B34(D34), .B35(D35), .B36(D36), .B37(D37),
.B40(D40), .B41(D41), .B42(D42), .B43(D43), .B44(D44), .B45(D45), .B46(D46), .B47(D47),
.B50(D50), .B51(D51), .B52(D52), .B53(D53), .B54(D54), .B55(D55), .B56(D56), .B57(D57),
.B60(D60), .B61(D61), .B62(D62), .B63(D63), .B64(D64), .B65(D65), .B66(D66), .B67(D67),
.B70(D70), .B71(D71), .B72(D72), .B73(D73), .B74(D74), .B75(D75), .B76(D76), .B77(D77)
);
//---------combinational processes----------
// Add round key operation (sigma function)
assign odata[0:511] = E[0:511] ^ subkey[0:511];
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_pl.v
// Version : 1.11
//--
//--------------------------------------------------------------------------------
module pci_exp_usrapp_pl (
pl_initial_link_width,
pl_lane_reversal_mode,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_link_upcfg_capable,
pl_ltssm_state,
pl_received_hot_rst,
pl_sel_link_rate,
pl_sel_link_width,
pl_directed_link_auton,
pl_directed_link_change,
pl_directed_link_speed,
pl_directed_link_width,
pl_upstream_prefer_deemph,
speed_change_done_n,
trn_lnk_up_n,
trn_clk,
trn_reset_n
);
input [2:0] pl_initial_link_width;
input [1:0] pl_lane_reversal_mode;
input pl_link_gen2_capable;
input pl_link_partner_gen2_supported;
input pl_link_upcfg_capable;
input [5:0] pl_ltssm_state;
input pl_received_hot_rst;
input pl_sel_link_rate;
input [1:0] pl_sel_link_width;
output pl_directed_link_auton;
output [1:0] pl_directed_link_change;
output pl_directed_link_speed;
output [1:0] pl_directed_link_width;
output pl_upstream_prefer_deemph;
output speed_change_done_n;
input trn_lnk_up_n;
input trn_clk;
input trn_reset_n;
parameter Tcq = 1;
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1;
reg pl_directed_link_auton;
reg [1:0] pl_directed_link_change;
reg pl_directed_link_speed;
reg [1:0] pl_directed_link_width;
reg pl_upstream_prefer_deemph;
reg speed_change_done_n;
initial begin
pl_directed_link_auton <= 1'b0;
pl_directed_link_change <= 2'b0;
pl_directed_link_speed <= 1'b0;
pl_directed_link_width <= 2'b0;
pl_upstream_prefer_deemph <= 1'b0;
speed_change_done_n <= 1'b1;
if (LINK_CAP_MAX_LINK_SPEED == 4'h2) begin
wait (trn_lnk_up_n == 1'b0);
if (pl_link_gen2_capable && pl_link_partner_gen2_supported) begin
wait (pl_sel_link_rate == 1'h1);
wait (pl_ltssm_state == 6'h16);
speed_change_done_n <= 1'b0;
end
end
end
endmodule // pci_exp_usrapp_pl
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:52 EST 2017
//
// Method conflict info:
// Method: enq
// Conflict-free: deq, first, notFull, notEmpty, count, clear
// Conflicts: enq
//
// Method: deq
// Conflict-free: enq, first, notFull, notEmpty, count, clear
// Conflicts: deq
//
// Method: first
// Conflict-free: enq, deq, first, notFull, notEmpty, count, clear
//
// Method: notFull
// Conflict-free: enq, deq, first, notFull, notEmpty, count, clear
//
// Method: notEmpty
// Conflict-free: enq, deq, first, notFull, notEmpty, count, clear
//
// Method: count
// Conflict-free: enq, deq, first, notFull, notEmpty, count, clear
//
// Method: clear
// Conflict-free: enq, deq, first, notFull, notEmpty, count
// Conflicts: clear
//
//
// Ports:
// Name I/O size props
// RDY_enq O 1 const
// RDY_deq O 1 const
// first O 3
// RDY_first O 1 const
// notFull O 1
// RDY_notFull O 1 const
// notEmpty O 1
// RDY_notEmpty O 1 const
// count O 4 reg
// RDY_count O 1 const
// RDY_clear O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// enq_sendData I 3 reg
// EN_enq I 1
// EN_deq I 1
// EN_clear I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkOutPortFIFO(CLK,
RST_N,
enq_sendData,
EN_enq,
RDY_enq,
EN_deq,
RDY_deq,
first,
RDY_first,
notFull,
RDY_notFull,
notEmpty,
RDY_notEmpty,
count,
RDY_count,
EN_clear,
RDY_clear);
input CLK;
input RST_N;
// action method enq
input [2 : 0] enq_sendData;
input EN_enq;
output RDY_enq;
// action method deq
input EN_deq;
output RDY_deq;
// value method first
output [2 : 0] first;
output RDY_first;
// value method notFull
output notFull;
output RDY_notFull;
// value method notEmpty
output notEmpty;
output RDY_notEmpty;
// value method count
output [3 : 0] count;
output RDY_count;
// action method clear
input EN_clear;
output RDY_clear;
// signals for module outputs
reg [2 : 0] first;
wire [3 : 0] count;
wire RDY_clear,
RDY_count,
RDY_deq,
RDY_enq,
RDY_first,
RDY_notEmpty,
RDY_notFull,
notEmpty,
notFull;
// register outPortFIFO_ifc_fifo_almost_full
reg outPortFIFO_ifc_fifo_almost_full;
wire outPortFIFO_ifc_fifo_almost_full$D_IN,
outPortFIFO_ifc_fifo_almost_full$EN;
// register outPortFIFO_ifc_fifo_deq_cnt
reg [63 : 0] outPortFIFO_ifc_fifo_deq_cnt;
wire [63 : 0] outPortFIFO_ifc_fifo_deq_cnt$D_IN;
wire outPortFIFO_ifc_fifo_deq_cnt$EN;
// register outPortFIFO_ifc_fifo_empty
reg outPortFIFO_ifc_fifo_empty;
wire outPortFIFO_ifc_fifo_empty$D_IN, outPortFIFO_ifc_fifo_empty$EN;
// register outPortFIFO_ifc_fifo_enq_cnt
reg [63 : 0] outPortFIFO_ifc_fifo_enq_cnt;
wire [63 : 0] outPortFIFO_ifc_fifo_enq_cnt$D_IN;
wire outPortFIFO_ifc_fifo_enq_cnt$EN;
// register outPortFIFO_ifc_fifo_full
reg outPortFIFO_ifc_fifo_full;
wire outPortFIFO_ifc_fifo_full$D_IN, outPortFIFO_ifc_fifo_full$EN;
// register outPortFIFO_ifc_fifo_head
reg [2 : 0] outPortFIFO_ifc_fifo_head;
wire [2 : 0] outPortFIFO_ifc_fifo_head$D_IN;
wire outPortFIFO_ifc_fifo_head$EN;
// register outPortFIFO_ifc_fifo_mem
reg [2 : 0] outPortFIFO_ifc_fifo_mem;
wire [2 : 0] outPortFIFO_ifc_fifo_mem$D_IN;
wire outPortFIFO_ifc_fifo_mem$EN;
// register outPortFIFO_ifc_fifo_mem_1
reg [2 : 0] outPortFIFO_ifc_fifo_mem_1;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_1$D_IN;
wire outPortFIFO_ifc_fifo_mem_1$EN;
// register outPortFIFO_ifc_fifo_mem_2
reg [2 : 0] outPortFIFO_ifc_fifo_mem_2;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_2$D_IN;
wire outPortFIFO_ifc_fifo_mem_2$EN;
// register outPortFIFO_ifc_fifo_mem_3
reg [2 : 0] outPortFIFO_ifc_fifo_mem_3;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_3$D_IN;
wire outPortFIFO_ifc_fifo_mem_3$EN;
// register outPortFIFO_ifc_fifo_mem_4
reg [2 : 0] outPortFIFO_ifc_fifo_mem_4;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_4$D_IN;
wire outPortFIFO_ifc_fifo_mem_4$EN;
// register outPortFIFO_ifc_fifo_mem_5
reg [2 : 0] outPortFIFO_ifc_fifo_mem_5;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_5$D_IN;
wire outPortFIFO_ifc_fifo_mem_5$EN;
// register outPortFIFO_ifc_fifo_mem_6
reg [2 : 0] outPortFIFO_ifc_fifo_mem_6;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_6$D_IN;
wire outPortFIFO_ifc_fifo_mem_6$EN;
// register outPortFIFO_ifc_fifo_mem_7
reg [2 : 0] outPortFIFO_ifc_fifo_mem_7;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_7$D_IN;
wire outPortFIFO_ifc_fifo_mem_7$EN;
// register outPortFIFO_ifc_fifo_size_cnt
reg [3 : 0] outPortFIFO_ifc_fifo_size_cnt;
wire [3 : 0] outPortFIFO_ifc_fifo_size_cnt$D_IN;
wire outPortFIFO_ifc_fifo_size_cnt$EN;
// register outPortFIFO_ifc_fifo_tail
reg [2 : 0] outPortFIFO_ifc_fifo_tail;
wire [2 : 0] outPortFIFO_ifc_fifo_tail$D_IN;
wire outPortFIFO_ifc_fifo_tail$EN;
// rule scheduling signals
wire WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert;
// remaining internal signals
wire [63 : 0] x__h1275, x__h2099;
wire [3 : 0] IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d48,
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d47;
wire [2 : 0] outPortFIFO_ifc_fifo_head_PLUS_1___d110,
outPortFIFO_ifc_fifo_tail_PLUS_1___d111;
wire IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115,
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d33,
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d41,
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d32,
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d40,
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d23,
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d31,
outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82;
// action method enq
assign RDY_enq = 1'd1 ;
// action method deq
assign RDY_deq = 1'd1 ;
// value method first
always@(outPortFIFO_ifc_fifo_head or
outPortFIFO_ifc_fifo_mem_7 or
outPortFIFO_ifc_fifo_mem or
outPortFIFO_ifc_fifo_mem_1 or
outPortFIFO_ifc_fifo_mem_2 or
outPortFIFO_ifc_fifo_mem_3 or
outPortFIFO_ifc_fifo_mem_4 or
outPortFIFO_ifc_fifo_mem_5 or outPortFIFO_ifc_fifo_mem_6)
begin
case (outPortFIFO_ifc_fifo_head)
3'd0: first = outPortFIFO_ifc_fifo_mem;
3'd1: first = outPortFIFO_ifc_fifo_mem_1;
3'd2: first = outPortFIFO_ifc_fifo_mem_2;
3'd3: first = outPortFIFO_ifc_fifo_mem_3;
3'd4: first = outPortFIFO_ifc_fifo_mem_4;
3'd5: first = outPortFIFO_ifc_fifo_mem_5;
3'd6: first = outPortFIFO_ifc_fifo_mem_6;
3'd7: first = outPortFIFO_ifc_fifo_mem_7;
endcase
end
assign RDY_first = 1'd1 ;
// value method notFull
assign notFull = !outPortFIFO_ifc_fifo_full ;
assign RDY_notFull = 1'd1 ;
// value method notEmpty
assign notEmpty = !outPortFIFO_ifc_fifo_empty ;
assign RDY_notEmpty = 1'd1 ;
// value method count
assign count = outPortFIFO_ifc_fifo_size_cnt ;
assign RDY_count = 1'd1 ;
// action method clear
assign RDY_clear = 1'd1 ;
// rule RL_outPortFIFO_ifc_fifo_continuousAssert
assign WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert =
outPortFIFO_ifc_fifo_empty &&
outPortFIFO_ifc_fifo_enq_cnt != outPortFIFO_ifc_fifo_deq_cnt ;
// register outPortFIFO_ifc_fifo_almost_full
assign outPortFIFO_ifc_fifo_almost_full$D_IN =
!EN_clear &&
(IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d33 ||
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115) ;
assign outPortFIFO_ifc_fifo_almost_full$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_deq_cnt
assign outPortFIFO_ifc_fifo_deq_cnt$D_IN = EN_clear ? 64'd0 : x__h1275 ;
assign outPortFIFO_ifc_fifo_deq_cnt$EN = EN_clear || EN_deq ;
// register outPortFIFO_ifc_fifo_empty
assign outPortFIFO_ifc_fifo_empty$D_IN =
EN_clear ||
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d41 ;
assign outPortFIFO_ifc_fifo_empty$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_enq_cnt
assign outPortFIFO_ifc_fifo_enq_cnt$D_IN = EN_clear ? 64'd0 : x__h2099 ;
assign outPortFIFO_ifc_fifo_enq_cnt$EN = EN_clear || EN_enq ;
// register outPortFIFO_ifc_fifo_full
assign outPortFIFO_ifc_fifo_full$D_IN =
!EN_clear &&
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115 ;
assign outPortFIFO_ifc_fifo_full$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_head
assign outPortFIFO_ifc_fifo_head$D_IN =
EN_clear ? 3'd0 : outPortFIFO_ifc_fifo_head_PLUS_1___d110 ;
assign outPortFIFO_ifc_fifo_head$EN = EN_clear || EN_deq ;
// register outPortFIFO_ifc_fifo_mem
assign outPortFIFO_ifc_fifo_mem$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd0 ;
// register outPortFIFO_ifc_fifo_mem_1
assign outPortFIFO_ifc_fifo_mem_1$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_1$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd1 ;
// register outPortFIFO_ifc_fifo_mem_2
assign outPortFIFO_ifc_fifo_mem_2$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_2$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd2 ;
// register outPortFIFO_ifc_fifo_mem_3
assign outPortFIFO_ifc_fifo_mem_3$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_3$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd3 ;
// register outPortFIFO_ifc_fifo_mem_4
assign outPortFIFO_ifc_fifo_mem_4$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_4$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd4 ;
// register outPortFIFO_ifc_fifo_mem_5
assign outPortFIFO_ifc_fifo_mem_5$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_5$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd5 ;
// register outPortFIFO_ifc_fifo_mem_6
assign outPortFIFO_ifc_fifo_mem_6$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_6$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd6 ;
// register outPortFIFO_ifc_fifo_mem_7
assign outPortFIFO_ifc_fifo_mem_7$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_7$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd7 ;
// register outPortFIFO_ifc_fifo_size_cnt
assign outPortFIFO_ifc_fifo_size_cnt$D_IN =
EN_clear ?
4'd0 :
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d48 ;
assign outPortFIFO_ifc_fifo_size_cnt$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_tail
assign outPortFIFO_ifc_fifo_tail$D_IN =
EN_clear ? 3'd0 : outPortFIFO_ifc_fifo_tail_PLUS_1___d111 ;
assign outPortFIFO_ifc_fifo_tail$EN = EN_clear || EN_enq ;
// remaining internal signals
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_full :
!EN_deq &&
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d23 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d33 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_almost_full :
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d32 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d41 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_empty :
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d40 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d48 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_size_cnt :
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d47 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d32 =
EN_deq ?
outPortFIFO_ifc_fifo_tail == outPortFIFO_ifc_fifo_head :
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d31 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d40 =
EN_deq ?
outPortFIFO_ifc_fifo_head_PLUS_1___d110 ==
outPortFIFO_ifc_fifo_tail :
!EN_enq && outPortFIFO_ifc_fifo_empty ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d47 =
EN_deq ?
outPortFIFO_ifc_fifo_size_cnt - 4'd1 :
(EN_enq ?
outPortFIFO_ifc_fifo_size_cnt + 4'd1 :
outPortFIFO_ifc_fifo_size_cnt) ;
assign IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d23 =
EN_enq ?
outPortFIFO_ifc_fifo_tail_PLUS_1___d111 ==
outPortFIFO_ifc_fifo_head :
outPortFIFO_ifc_fifo_full ;
assign IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d31 =
EN_enq ?
outPortFIFO_ifc_fifo_tail + 3'd2 == outPortFIFO_ifc_fifo_head :
outPortFIFO_ifc_fifo_almost_full ;
assign outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82 =
outPortFIFO_ifc_fifo_empty ==
(outPortFIFO_ifc_fifo_head == outPortFIFO_ifc_fifo_tail &&
!outPortFIFO_ifc_fifo_full) ;
assign outPortFIFO_ifc_fifo_head_PLUS_1___d110 =
outPortFIFO_ifc_fifo_head + 3'd1 ;
assign outPortFIFO_ifc_fifo_tail_PLUS_1___d111 =
outPortFIFO_ifc_fifo_tail + 3'd1 ;
assign x__h1275 = outPortFIFO_ifc_fifo_deq_cnt + 64'd1 ;
assign x__h2099 = outPortFIFO_ifc_fifo_enq_cnt + 64'd1 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
outPortFIFO_ifc_fifo_almost_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
outPortFIFO_ifc_fifo_deq_cnt <= `BSV_ASSIGNMENT_DELAY 64'd0;
outPortFIFO_ifc_fifo_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
outPortFIFO_ifc_fifo_enq_cnt <= `BSV_ASSIGNMENT_DELAY 64'd0;
outPortFIFO_ifc_fifo_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
outPortFIFO_ifc_fifo_head <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_2 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_3 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_4 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_5 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_6 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_7 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_size_cnt <= `BSV_ASSIGNMENT_DELAY 4'd0;
outPortFIFO_ifc_fifo_tail <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (outPortFIFO_ifc_fifo_almost_full$EN)
outPortFIFO_ifc_fifo_almost_full <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_almost_full$D_IN;
if (outPortFIFO_ifc_fifo_deq_cnt$EN)
outPortFIFO_ifc_fifo_deq_cnt <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_deq_cnt$D_IN;
if (outPortFIFO_ifc_fifo_empty$EN)
outPortFIFO_ifc_fifo_empty <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_empty$D_IN;
if (outPortFIFO_ifc_fifo_enq_cnt$EN)
outPortFIFO_ifc_fifo_enq_cnt <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_enq_cnt$D_IN;
if (outPortFIFO_ifc_fifo_full$EN)
outPortFIFO_ifc_fifo_full <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_full$D_IN;
if (outPortFIFO_ifc_fifo_head$EN)
outPortFIFO_ifc_fifo_head <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_head$D_IN;
if (outPortFIFO_ifc_fifo_mem$EN)
outPortFIFO_ifc_fifo_mem <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem$D_IN;
if (outPortFIFO_ifc_fifo_mem_1$EN)
outPortFIFO_ifc_fifo_mem_1 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_1$D_IN;
if (outPortFIFO_ifc_fifo_mem_2$EN)
outPortFIFO_ifc_fifo_mem_2 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_2$D_IN;
if (outPortFIFO_ifc_fifo_mem_3$EN)
outPortFIFO_ifc_fifo_mem_3 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_3$D_IN;
if (outPortFIFO_ifc_fifo_mem_4$EN)
outPortFIFO_ifc_fifo_mem_4 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_4$D_IN;
if (outPortFIFO_ifc_fifo_mem_5$EN)
outPortFIFO_ifc_fifo_mem_5 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_5$D_IN;
if (outPortFIFO_ifc_fifo_mem_6$EN)
outPortFIFO_ifc_fifo_mem_6 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_6$D_IN;
if (outPortFIFO_ifc_fifo_mem_7$EN)
outPortFIFO_ifc_fifo_mem_7 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_7$D_IN;
if (outPortFIFO_ifc_fifo_size_cnt$EN)
outPortFIFO_ifc_fifo_size_cnt <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_size_cnt$D_IN;
if (outPortFIFO_ifc_fifo_tail$EN)
outPortFIFO_ifc_fifo_tail <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_tail$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
outPortFIFO_ifc_fifo_almost_full = 1'h0;
outPortFIFO_ifc_fifo_deq_cnt = 64'hAAAAAAAAAAAAAAAA;
outPortFIFO_ifc_fifo_empty = 1'h0;
outPortFIFO_ifc_fifo_enq_cnt = 64'hAAAAAAAAAAAAAAAA;
outPortFIFO_ifc_fifo_full = 1'h0;
outPortFIFO_ifc_fifo_head = 3'h2;
outPortFIFO_ifc_fifo_mem = 3'h2;
outPortFIFO_ifc_fifo_mem_1 = 3'h2;
outPortFIFO_ifc_fifo_mem_2 = 3'h2;
outPortFIFO_ifc_fifo_mem_3 = 3'h2;
outPortFIFO_ifc_fifo_mem_4 = 3'h2;
outPortFIFO_ifc_fifo_mem_5 = 3'h2;
outPortFIFO_ifc_fifo_mem_6 = 3'h2;
outPortFIFO_ifc_fifo_mem_7 = 3'h2;
outPortFIFO_ifc_fifo_size_cnt = 4'hA;
outPortFIFO_ifc_fifo_tail = 3'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (EN_enq && outPortFIFO_ifc_fifo_full)
$display("location of dfifo: ",
"\"RegFIFO.bsv\", line 25, column 33\n");
if (RST_N)
if (EN_enq && outPortFIFO_ifc_fifo_full)
$display("Dynamic assertion failed: \"RegFIFO.bsv\", line 191, column 27\nouch, enqueuing to full FIFO");
if (RST_N) if (EN_enq && outPortFIFO_ifc_fifo_full) $finish(32'd0);
if (RST_N)
if (EN_deq && outPortFIFO_ifc_fifo_empty)
$display("location of dfifo: ",
"\"RegFIFO.bsv\", line 25, column 33\n");
if (RST_N)
if (EN_deq && outPortFIFO_ifc_fifo_empty)
$display("Dynamic assertion failed: \"RegFIFO.bsv\", line 198, column 28\nouch, dequeueing from empty FIFO");
if (RST_N) if (EN_deq && outPortFIFO_ifc_fifo_empty) $finish(32'd0);
if (RST_N)
if (WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert)
$display("Continuous assertion failed: \"RegFIFO.bsv\", line 167, column 59\nmismatched in enq/deq count");
if (RST_N)
if (WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert) $finish(32'd0);
if (RST_N)
if (!outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82)
$display("Continuous assertion failed: \"RegFIFO.bsv\", line 170, column 45\nerror in empty signals");
if (RST_N)
if (!outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82)
$finish(32'd0);
end
// synopsys translate_on
endmodule // mkOutPortFIFO
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__XNOR3_FUNCTIONAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_TB_V
`define SKY130_FD_SC_HS__O21BA_TB_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ba.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1_N = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1_N = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_TB_V
|
`timescale 1ns / 1ps
module uart_ctrl(
input CLK,
input RST,
input EN,
input [3:0] BAUD,
input TXEN,
input RXEN,
output TX,
input RX,
input WRITE,
input [7:0] WRDATA,
output ISFULL,
input READ,
output [7:0] RDDATA,
output DATARDY
);
wire uart_clk;
wire uart_tx_read;
wire [7:0] uart_tx_data;
wire uart_tx_datardy;
wire uart_tx_empty;
wire uart_rx_write;
wire [7:0] uart_rx_data;
wire uart_rx_full;
wire uart_rx_empty;
wire tx_en;
wire rx_en;
clk_div clk_div_inst(
.CLKIN(CLK),
.RST(RST),
.BAUD(BAUD),
.CLKOUT(uart_clk)
);
circular_buff buff_tx(
.CLK(CLK),
.RST(RST),
.WRITE(WRITE),
.WRDATA(WRDATA),
.READ(uart_tx_read),
.RDDATA(uart_tx_data),
.ISFULL(ISFULL),
.ISEMPTY(uart_tx_empty)
);
assign uart_tx_datardy = ~uart_tx_empty;
circular_buff buff_rx(
.CLK(CLK),
.RST(RST),
.WRITE(uart_rx_write),
.WRDATA(uart_rx_data),
.READ(READ),
.RDDATA(RDDATA),
.ISFULL(uart_rx_full),
.ISEMPTY(uart_rx_empty)
);
assign DATARDY = ~uart_rx_empty;
uart_tx tx(
.CLK(uart_clk),
.RST(RST),
.EN(tx_en),
.DATA(uart_tx_data),
.DATARDY(uart_tx_datardy),
.READ(uart_tx_read),
.TX(TX)
);
uart_rx rx(
.CLK(uart_clk),
.RST(RST),
.EN(rx_en),
.RX(RX),
.ISFULL(uart_rx_full),
.WRITE(uart_rx_write),
.DATA(uart_rx_data)
);
assign tx_en = EN ? TXEN ? 1'b1 : 1'b0 : 1'b0;
assign rx_en = EN ? RXEN ? 1'b1 : 1'b0 : 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V |
/******************************************************************************/
/* FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** Comparator *****/
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** Sorter cell emitting multiple values at once *****/
/**************************************************************************************************/
module SCELL #(parameter SORTW = 32,
parameter M_LOG = 2)
(input wire CLK,
input wire RST,
input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [(SORTW<<M_LOG)-1:0] din1,
input wire [(SORTW<<M_LOG)-1:0] din2,
input wire full,
output wire [(SORTW<<M_LOG)-1:0] dout,
output wire enq);
function [(SORTW<<M_LOG)-1:0] mux;
input [(SORTW<<M_LOG)-1:0] a;
input [(SORTW<<M_LOG)-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire cmp = (din1[SORTW-1:0] < din2[SORTW-1:0]);
wire [(SORTW<<M_LOG)-1:0] cmp_dout = mux(din2, din1, cmp);
wire F_enq;
wire F_deq;
wire F_emp;
wire F_full;
wire [(SORTW<<M_LOG)-1:0] F_dot;
MRE2 #(1,(SORTW<<M_LOG)) F(.CLK(CLK), .RST(RST), .enq(F_enq), .deq(F_deq),
.din(cmp_dout), .dot(F_dot), .emp(F_emp), .full(F_full));
assign F_enq = &{~F_full,valid1,valid2}; // assign F_enq = (!F_full && valid1 && valid2);
assign F_deq = ~|{full,F_emp}; // assign F_deq = !full && !F_emp;
reg [(SORTW<<M_LOG)-1:0] fbdata;
reg [(SORTW<<M_LOG)-1:0] fbdata_a; // duplicated register
reg [(SORTW<<M_LOG)-1:0] fbdata_b; // duplicated register
reg fbinvoke;
assign enq = (F_deq && fbinvoke);
assign deq1 = (F_enq && cmp);
assign deq2 = (F_enq && !cmp);
localparam P_DATAWIDTH = 32;
wire [P_DATAWIDTH-1:0] a, b, c, d, e, f, g, h;
wire [P_DATAWIDTH-1:0] e_a, f_a, g_a, h_a; // for duplicated register
wire [P_DATAWIDTH-1:0] e_b, f_b, g_b, h_b; // for duplicated register
assign a = F_dot[ 31: 0];
assign b = F_dot[ 63:32];
assign c = F_dot[ 95:64];
assign d = F_dot[127:96];
assign e = fbdata[ 31: 0];
assign f = fbdata[ 63:32];
assign g = fbdata[ 95:64];
assign h = fbdata[127:96];
assign e_a = fbdata_a[ 31: 0];
assign f_a = fbdata_a[ 63:32];
assign g_a = fbdata_a[ 95:64];
assign h_a = fbdata_a[127:96];
assign e_b = fbdata_b[ 31: 0];
assign f_b = fbdata_b[ 63:32];
assign g_b = fbdata_b[ 95:64];
assign h_b = fbdata_b[127:96];
wire t0_c0 = (a < h);
wire t0_c1 = (b < g);
wire t0_c2 = (c < f);
wire t0_c3 = (d < e);
wire t0_x0 = t0_c0 ^ t0_c1;
wire t0_x1 = t0_c2 ^ t0_c3;
wire t0 = t0_x0 ^ t0_x1;
wire s2_c0 = (b < e);
wire s2_c1 = (a < f);
wire s3_c0 = (c < h);
wire s3_c1 = (d < g);
wire s4_c0 = (a < g);
wire s4_c1 = (b < f);
wire s4_c2 = (c < e);
wire s5_c0 = (d < f);
wire s5_c1 = (c < g);
wire s5_c2 = (b < h);
wire s0 = (a < e);
wire s1 = (d < h);
wire [1:0] s2 = {s0, (s2_c0 ^ s2_c1)};
wire [1:0] s3 = {s1, (s3_c0 ^ s3_c1)};
wire [2:0] s4 = {s2, (s4_c0 ^ s4_c1 ^ s4_c2)};
wire [2:0] s5 = {s3, (s5_c0 ^ s5_c1 ^ s5_c2)};
wire [3:0] s6 = {s4, t0};
wire [3:0] s7 = {s5, t0};
wire [P_DATAWIDTH-1:0] m0, m1, m2, m3, m4, m5, m6, m7;
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [32-1:0] mux4in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [1:0] sel;
begin
case (sel)
2'b00: mux4in32 = a;
2'b01: mux4in32 = b;
2'b10: mux4in32 = c;
2'b11: mux4in32 = d;
endcase
end
endfunction
function [32-1:0] mux6in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [2:0] sel;
begin
casex (sel)
3'b000: mux6in32 = a;
3'b001: mux6in32 = b;
3'b100: mux6in32 = c;
3'b101: mux6in32 = d;
3'bx10: mux6in32 = e;
3'bx11: mux6in32 = f;
endcase
end
endfunction
function [32-1:0] mux12in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [32-1:0] g;
input [32-1:0] h;
input [32-1:0] i;
input [32-1:0] j;
input [32-1:0] k;
input [32-1:0] l;
input [3:0] sel;
begin
casex (sel)
4'b0000: mux12in32 = a;
4'b0001: mux12in32 = b;
4'b0010: mux12in32 = c;
4'b0011: mux12in32 = d;
4'b1000: mux12in32 = e;
4'b1001: mux12in32 = f;
4'b1010: mux12in32 = g;
4'b1011: mux12in32 = h;
4'bx100: mux12in32 = i;
4'bx101: mux12in32 = j;
4'bx110: mux12in32 = k;
4'bx111: mux12in32 = l;
endcase
end
endfunction
assign m0 = mux32(e, a, s0);
assign m1 = mux32(d, h, s1);
assign m2 = mux4in32(f, a, b, e, s2);
assign m3 = mux4in32(c, h, g, d, s3);
assign m4 = mux6in32(g, a, e, c, b, f, s4);
assign m5 = mux6in32(b, h, d, f, g, c, s5);
// using duplicated registers
assign m6 = mux12in32(h_a, a, b, g_a, f_a, c, d, e_a, f_a, c, b, g_a, s6);
assign m7 = mux12in32(a, h_b, g_b, b, c, f_b, e_b, d, c, f_b, g_b, b, s7);
// output and feedback
//////////////////////////////////////////////////////////
assign dout = {m6,m4,m2,m0}; // output
always @(posedge CLK) begin // feedback
if (RST) begin
fbdata <= 0;
fbdata_a <= 0;
fbdata_b <= 0;
fbinvoke <= 0;
end else begin
if (F_deq) begin
fbdata <= {m1,m3,m5,m7};
fbdata_a <= {m1,m3,m5,m7};
fbdata_b <= {m1,m3,m5,m7};
fbinvoke <= 1;
end
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire rx_wait,
output wire [`MERGW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg [1:0] im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
(* mark_debug = "true" *) wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den;
wire im_deq = (req && !im_emp);
assign rx_wait = im_cnt[`IB_SIZE-1];
always @(posedge CLK) im_req <= (im_cnt==0) ? 3 : (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/ // todo
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`MERGW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [1:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`MERGW-1:0] mux;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[`MERGW-1:0], dot[`MERGW-1:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==3)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==2)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {`MERGW'b0, dot_t[`DRAMW-1:`MERGW]};
2'b11: dot_t <= {`MERGW'b0, dot[`DRAMW-1:`MERGW]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`MERGW-1:0] din, // data in
output wire [`MERGW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`MERGW-1:0] mux128;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux128 = a;
1'b1: mux128 = b;
endcase
end
endfunction
/*****************************************/
wire [`MERGW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`MERGW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux128(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 4;
if (ecnt==4 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`MERGW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`MERGW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15;
assign {d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [`MERGW-1:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [`MERGW-1:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [`MERGW-1:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [`MERGW-1:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [`MERGW-1:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [`MERGW-1:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [`MERGW-1:0] F07_din, F07_dot; wire [1:0] F07_cnt;
wire F08_enq, F08_deq, F08_emp, F08_full; wire [`MERGW-1:0] F08_din, F08_dot; wire [1:0] F08_cnt;
wire F09_enq, F09_deq, F09_emp, F09_full; wire [`MERGW-1:0] F09_din, F09_dot; wire [1:0] F09_cnt;
wire F10_enq, F10_deq, F10_emp, F10_full; wire [`MERGW-1:0] F10_din, F10_dot; wire [1:0] F10_cnt;
wire F11_enq, F11_deq, F11_emp, F11_full; wire [`MERGW-1:0] F11_din, F11_dot; wire [1:0] F11_cnt;
wire F12_enq, F12_deq, F12_emp, F12_full; wire [`MERGW-1:0] F12_din, F12_dot; wire [1:0] F12_cnt;
wire F13_enq, F13_deq, F13_emp, F13_full; wire [`MERGW-1:0] F13_din, F13_dot; wire [1:0] F13_cnt;
wire F14_enq, F14_deq, F14_emp, F14_full; wire [`MERGW-1:0] F14_din, F14_dot; wire [1:0] F14_cnt;
wire F15_enq, F15_deq, F15_emp, F15_full; wire [`MERGW-1:0] F15_din, F15_dot; wire [1:0] F15_cnt;
wire F16_enq, F16_deq, F16_emp, F16_full; wire [`MERGW-1:0] F16_din, F16_dot; wire [1:0] F16_cnt;
wire F17_enq, F17_deq, F17_emp, F17_full; wire [`MERGW-1:0] F17_din, F17_dot; wire [1:0] F17_cnt;
wire F18_enq, F18_deq, F18_emp, F18_full; wire [`MERGW-1:0] F18_din, F18_dot; wire [1:0] F18_cnt;
wire F19_enq, F19_deq, F19_emp, F19_full; wire [`MERGW-1:0] F19_din, F19_dot; wire [1:0] F19_cnt;
wire F20_enq, F20_deq, F20_emp, F20_full; wire [`MERGW-1:0] F20_din, F20_dot; wire [1:0] F20_cnt;
wire F21_enq, F21_deq, F21_emp, F21_full; wire [`MERGW-1:0] F21_din, F21_dot; wire [1:0] F21_cnt;
wire F22_enq, F22_deq, F22_emp, F22_full; wire [`MERGW-1:0] F22_din, F22_dot; wire [1:0] F22_cnt;
wire F23_enq, F23_deq, F23_emp, F23_full; wire [`MERGW-1:0] F23_din, F23_dot; wire [1:0] F23_cnt;
wire F24_enq, F24_deq, F24_emp, F24_full; wire [`MERGW-1:0] F24_din, F24_dot; wire [1:0] F24_cnt;
wire F25_enq, F25_deq, F25_emp, F25_full; wire [`MERGW-1:0] F25_din, F25_dot; wire [1:0] F25_cnt;
wire F26_enq, F26_deq, F26_emp, F26_full; wire [`MERGW-1:0] F26_din, F26_dot; wire [1:0] F26_cnt;
wire F27_enq, F27_deq, F27_emp, F27_full; wire [`MERGW-1:0] F27_din, F27_dot; wire [1:0] F27_cnt;
wire F28_enq, F28_deq, F28_emp, F28_full; wire [`MERGW-1:0] F28_din, F28_dot; wire [1:0] F28_cnt;
wire F29_enq, F29_deq, F29_emp, F29_full; wire [`MERGW-1:0] F29_din, F29_dot; wire [1:0] F29_cnt;
wire F30_enq, F30_deq, F30_emp, F30_full; wire [`MERGW-1:0] F30_din, F30_dot; wire [1:0] F30_cnt;
wire F31_enq, F31_deq, F31_emp, F31_full; wire [`MERGW-1:0] F31_din, F31_dot; wire [1:0] F31_cnt;
INBUF IN16(CLK, RST, full[0], F16_full, F16_enq, d00, F16_din, enq[0], phase, irst);
INBUF IN17(CLK, RST, full[1], F17_full, F17_enq, d01, F17_din, enq[1], phase, irst);
INBUF IN18(CLK, RST, full[2], F18_full, F18_enq, d02, F18_din, enq[2], phase, irst);
INBUF IN19(CLK, RST, full[3], F19_full, F19_enq, d03, F19_din, enq[3], phase, irst);
INBUF IN20(CLK, RST, full[4], F20_full, F20_enq, d04, F20_din, enq[4], phase, irst);
INBUF IN21(CLK, RST, full[5], F21_full, F21_enq, d05, F21_din, enq[5], phase, irst);
INBUF IN22(CLK, RST, full[6], F22_full, F22_enq, d06, F22_din, enq[6], phase, irst);
INBUF IN23(CLK, RST, full[7], F23_full, F23_enq, d07, F23_din, enq[7], phase, irst);
INBUF IN24(CLK, RST, full[8], F24_full, F24_enq, d08, F24_din, enq[8], phase, irst);
INBUF IN25(CLK, RST, full[9], F25_full, F25_enq, d09, F25_din, enq[9], phase, irst);
INBUF IN26(CLK, RST, full[10], F26_full, F26_enq, d10, F26_din, enq[10], phase, irst);
INBUF IN27(CLK, RST, full[11], F27_full, F27_enq, d11, F27_din, enq[11], phase, irst);
INBUF IN28(CLK, RST, full[12], F28_full, F28_enq, d12, F28_din, enq[12], phase, irst);
INBUF IN29(CLK, RST, full[13], F29_full, F29_enq, d13, F29_din, enq[13], phase, irst);
INBUF IN30(CLK, RST, full[14], F30_full, F30_enq, d14, F30_din, enq[14], phase, irst);
INBUF IN31(CLK, RST, full[15], F31_full, F31_enq, d15, F31_din, enq[15], phase, irst);
MRE2 #(1, `MERGW) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1, `MERGW) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1, `MERGW) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1, `MERGW) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1, `MERGW) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1, `MERGW) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1, `MERGW) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
MRE2 #(1, `MERGW) F08(CLK, frst, F08_enq, F08_deq, F08_din, F08_dot, F08_emp, F08_full, F08_cnt);
MRE2 #(1, `MERGW) F09(CLK, frst, F09_enq, F09_deq, F09_din, F09_dot, F09_emp, F09_full, F09_cnt);
MRE2 #(1, `MERGW) F10(CLK, frst, F10_enq, F10_deq, F10_din, F10_dot, F10_emp, F10_full, F10_cnt);
MRE2 #(1, `MERGW) F11(CLK, frst, F11_enq, F11_deq, F11_din, F11_dot, F11_emp, F11_full, F11_cnt);
MRE2 #(1, `MERGW) F12(CLK, frst, F12_enq, F12_deq, F12_din, F12_dot, F12_emp, F12_full, F12_cnt);
MRE2 #(1, `MERGW) F13(CLK, frst, F13_enq, F13_deq, F13_din, F13_dot, F13_emp, F13_full, F13_cnt);
MRE2 #(1, `MERGW) F14(CLK, frst, F14_enq, F14_deq, F14_din, F14_dot, F14_emp, F14_full, F14_cnt);
MRE2 #(1, `MERGW) F15(CLK, frst, F15_enq, F15_deq, F15_din, F15_dot, F15_emp, F15_full, F15_cnt);
MRE2 #(1, `MERGW) F16(CLK, frst, F16_enq, F16_deq, F16_din, F16_dot, F16_emp, F16_full, F16_cnt);
MRE2 #(1, `MERGW) F17(CLK, frst, F17_enq, F17_deq, F17_din, F17_dot, F17_emp, F17_full, F17_cnt);
MRE2 #(1, `MERGW) F18(CLK, frst, F18_enq, F18_deq, F18_din, F18_dot, F18_emp, F18_full, F18_cnt);
MRE2 #(1, `MERGW) F19(CLK, frst, F19_enq, F19_deq, F19_din, F19_dot, F19_emp, F19_full, F19_cnt);
MRE2 #(1, `MERGW) F20(CLK, frst, F20_enq, F20_deq, F20_din, F20_dot, F20_emp, F20_full, F20_cnt);
MRE2 #(1, `MERGW) F21(CLK, frst, F21_enq, F21_deq, F21_din, F21_dot, F21_emp, F21_full, F21_cnt);
MRE2 #(1, `MERGW) F22(CLK, frst, F22_enq, F22_deq, F22_din, F22_dot, F22_emp, F22_full, F22_cnt);
MRE2 #(1, `MERGW) F23(CLK, frst, F23_enq, F23_deq, F23_din, F23_dot, F23_emp, F23_full, F23_cnt);
MRE2 #(1, `MERGW) F24(CLK, frst, F24_enq, F24_deq, F24_din, F24_dot, F24_emp, F24_full, F24_cnt);
MRE2 #(1, `MERGW) F25(CLK, frst, F25_enq, F25_deq, F25_din, F25_dot, F25_emp, F25_full, F25_cnt);
MRE2 #(1, `MERGW) F26(CLK, frst, F26_enq, F26_deq, F26_din, F26_dot, F26_emp, F26_full, F26_cnt);
MRE2 #(1, `MERGW) F27(CLK, frst, F27_enq, F27_deq, F27_din, F27_dot, F27_emp, F27_full, F27_cnt);
MRE2 #(1, `MERGW) F28(CLK, frst, F28_enq, F28_deq, F28_din, F28_dot, F28_emp, F28_full, F28_cnt);
MRE2 #(1, `MERGW) F29(CLK, frst, F29_enq, F29_deq, F29_din, F29_dot, F29_emp, F29_full, F29_cnt);
MRE2 #(1, `MERGW) F30(CLK, frst, F30_enq, F30_deq, F30_din, F30_dot, F30_emp, F30_full, F30_cnt);
MRE2 #(1, `MERGW) F31(CLK, frst, F31_enq, F31_deq, F31_din, F31_dot, F31_emp, F31_full, F31_cnt);
SCELL #(`SORTW, `M_LOG) S01(CLK, frst, !F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL #(`SORTW, `M_LOG) S02(CLK, frst, !F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL #(`SORTW, `M_LOG) S03(CLK, frst, !F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
SCELL #(`SORTW, `M_LOG) S04(CLK, frst, !F08_emp, !F09_emp, F08_deq, F09_deq, F08_dot, F09_dot, F04_full, F04_din, F04_enq);
SCELL #(`SORTW, `M_LOG) S05(CLK, frst, !F10_emp, !F11_emp, F10_deq, F11_deq, F10_dot, F11_dot, F05_full, F05_din, F05_enq);
SCELL #(`SORTW, `M_LOG) S06(CLK, frst, !F12_emp, !F13_emp, F12_deq, F13_deq, F12_dot, F13_dot, F06_full, F06_din, F06_enq);
SCELL #(`SORTW, `M_LOG) S07(CLK, frst, !F14_emp, !F15_emp, F14_deq, F15_deq, F14_dot, F15_dot, F07_full, F07_din, F07_enq);
SCELL #(`SORTW, `M_LOG) S08(CLK, frst, !F16_emp, !F17_emp, F16_deq, F17_deq, F16_dot, F17_dot, F08_full, F08_din, F08_enq);
SCELL #(`SORTW, `M_LOG) S09(CLK, frst, !F18_emp, !F19_emp, F18_deq, F19_deq, F18_dot, F19_dot, F09_full, F09_din, F09_enq);
SCELL #(`SORTW, `M_LOG) S10(CLK, frst, !F20_emp, !F21_emp, F20_deq, F21_deq, F20_dot, F21_dot, F10_full, F10_din, F10_enq);
SCELL #(`SORTW, `M_LOG) S11(CLK, frst, !F22_emp, !F23_emp, F22_deq, F23_deq, F22_dot, F23_dot, F11_full, F11_din, F11_enq);
SCELL #(`SORTW, `M_LOG) S12(CLK, frst, !F24_emp, !F25_emp, F24_deq, F25_deq, F24_dot, F25_dot, F12_full, F12_din, F12_enq);
SCELL #(`SORTW, `M_LOG) S13(CLK, frst, !F26_emp, !F27_emp, F26_deq, F27_deq, F26_dot, F27_dot, F13_full, F13_din, F13_enq);
SCELL #(`SORTW, `M_LOG) S14(CLK, frst, !F28_emp, !F29_emp, F28_deq, F29_deq, F28_dot, F29_dot, F14_full, F14_din, F14_enq);
SCELL #(`SORTW, `M_LOG) S15(CLK, frst, !F30_emp, !F31_emp, F30_deq, F31_deq, F30_dot, F31_dot, F15_full, F15_din, F15_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`MERGW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [1:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 3);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule
/***** Sorting Network *****/
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire [`SORT_WAY:0] DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg [`SORT_WAY:0] DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg [`SORT_WAY:0] DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg [`SORT_WAY:0] pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester B for data
reg [`SORT_WAY:0] pcB; // pipeline regester B for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester C for data
reg [`SORT_WAY:0] pcC; // pipeline regester C for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester D for data
reg [`SORT_WAY:0] pcD; // pipeline regester D for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester E for data
reg [`SORT_WAY:0] pcE; // pipeline regester E for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester F for data
reg [`SORT_WAY:0] pcF; // pipeline regester F for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester G for data
reg [`SORT_WAY:0] pcG; // pipeline regester G for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester H for data
reg [`SORT_WAY:0] pcH; // pipeline regester H for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester I for data
reg [`SORT_WAY:0] pcI; // pipeline regester I for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** An SRL-based FIFO *****/
/******************************************************************************/
module SRL_FIFO #(parameter FIFO_SIZE = 4, // size in log scale, 4 for 16 entry
parameter FIFO_WIDTH = 64) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
input wire [`DRAMW-1:0] rx_data,
input wire rx_data_valid,
output wire rx_wait,
input wire chnl_tx_data_ren,
input wire chnl_tx_data_valid,
output wire [`MERGW-1:0] rslt,
output wire rslt_ready);
function [1-1:0] mux1;
input [1-1:0] a;
input [1-1:0] b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [16-1:0] mux16;
input [16-1:0] a;
input [16-1:0] b;
input sel;
begin
case (sel)
1'b0: mux16 = a;
1'b1: mux16 = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
/**********************************************************************************************/
wire [`DRAMW-1:0] OB_dot;
wire OB_req;
wire OB_full;
assign d_din = OB_dot;
(* mark_debug = "true" *) reg [`DRAMW-1:0] dout_t;
reg [`DRAMW-1:0] dout_ta;
reg [`DRAMW-1:0] dout_tb;
reg [`DRAMW-1:0] dout_tc;
reg [`DRAMW-1:0] dout_td;
reg [`DRAMW-1:0] dout_te;
reg [`DRAMW-1:0] dout_tf;
(* mark_debug = "true" *) reg doen_t;
reg doen_ta;
reg doen_tb; //
reg doen_tc; //
reg doen_td; //
reg doen_te; //
reg doen_tf; //
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
(* mark_debug = "true" *) reg [`SORT_WAY-1:0] req_t; //
reg [`SORT_WAY-1:0] req_ta; //
reg [`SORT_WAY-1:0] req_tb; //
reg [`SORT_WAY-1:0] req_pzero;
wire [`SORT_WAY-1:0] im_req;
wire [`SORT_WAY-1:0] rxw;
reg [31:0] elem; // sorted elements in a phase
(* mark_debug = "true" *) reg [`PHASE_W] phase; //
reg pchange; // phase_change to reset some registers
reg iter_done; //
reg [31:0] ecnt; // sorted elements in an iteration
reg irst; // INBUF reset
reg frst; // sort-tree FIFO reset
reg phase_zero;
reg last_phase;
reg RST;
always @(posedge CLK) RST <= RST_IN;
/**********************************************************************************************/
wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15;
wire [1:0] ib00_req, ib01_req, ib02_req, ib03_req, ib04_req, ib05_req, ib06_req, ib07_req, ib08_req, ib09_req, ib10_req, ib11_req, ib12_req, ib13_req, ib14_req, ib15_req;
(* mark_debug = "true" *) wire rsltbuf_enq;
(* mark_debug = "true" *) wire rsltbuf_deq;
wire rsltbuf_emp;
wire rsltbuf_ful;
(* mark_debug = "true" *) wire [4:0] rsltbuf_cnt;
wire F01_emp;
wire F01_deq = mux1((~|{F01_emp,OB_full}), (~|{F01_emp,rsltbuf_ful}), last_phase);
(* mark_debug = "true" *) wire [`MERGW-1:0] F01_dot;
wire [`MERGW*`SORT_WAY-1:0] s_din = {d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15};
wire [`SORT_WAY-1:0] enq;
wire [`SORT_WAY-1:0] s_ful;
wire [`DRAMW-1:0] stnet_dout;
wire [`SORT_WAY:0] stnet_douten;
SORTINGNETWORK sortingnetwork(CLK, RST, {req_t, doen_t}, dout_t, stnet_dout, stnet_douten);
always @(posedge CLK) begin
if (RST) req_pzero <= 1;
else if (doen_tc) req_pzero <= {req_pzero[`SORT_WAY-2:0],req_pzero[`SORT_WAY-1]};
end
assign im_req = mux16(req_tb, req_pzero, phase_zero);
INMOD2 im00(CLK, RST, dout_tc, doen_tc & im_req[0], s_ful[0], rxw[0], d00, enq[0], ib00_req);
INMOD2 im01(CLK, RST, dout_tc, doen_tc & im_req[1], s_ful[1], rxw[1], d01, enq[1], ib01_req);
INMOD2 im02(CLK, RST, dout_tc, doen_tc & im_req[2], s_ful[2], rxw[2], d02, enq[2], ib02_req);
INMOD2 im03(CLK, RST, dout_tc, doen_tc & im_req[3], s_ful[3], rxw[3], d03, enq[3], ib03_req);
INMOD2 im04(CLK, RST, dout_td, doen_td & im_req[4], s_ful[4], rxw[4], d04, enq[4], ib04_req);
INMOD2 im05(CLK, RST, dout_td, doen_td & im_req[5], s_ful[5], rxw[5], d05, enq[5], ib05_req);
INMOD2 im06(CLK, RST, dout_td, doen_td & im_req[6], s_ful[6], rxw[6], d06, enq[6], ib06_req);
INMOD2 im07(CLK, RST, dout_td, doen_td & im_req[7], s_ful[7], rxw[7], d07, enq[7], ib07_req);
INMOD2 im08(CLK, RST, dout_te, doen_te & im_req[8], s_ful[8], rxw[8], d08, enq[8], ib08_req);
INMOD2 im09(CLK, RST, dout_te, doen_te & im_req[9], s_ful[9], rxw[9], d09, enq[9], ib09_req);
INMOD2 im10(CLK, RST, dout_te, doen_te & im_req[10], s_ful[10], rxw[10], d10, enq[10], ib10_req);
INMOD2 im11(CLK, RST, dout_te, doen_te & im_req[11], s_ful[11], rxw[11], d11, enq[11], ib11_req);
INMOD2 im12(CLK, RST, dout_tf, doen_tf & im_req[12], s_ful[12], rxw[12], d12, enq[12], ib12_req);
INMOD2 im13(CLK, RST, dout_tf, doen_tf & im_req[13], s_ful[13], rxw[13], d13, enq[13], ib13_req);
INMOD2 im14(CLK, RST, dout_tf, doen_tf & im_req[14], s_ful[14], rxw[14], d14, enq[14], ib14_req);
INMOD2 im15(CLK, RST, dout_tf, doen_tf & im_req[15], s_ful[15], rxw[15], d15, enq[15], ib15_req);
assign rx_wait = |rxw;
STREE stree(CLK, RST, irst, frst, phase, s_din, enq, s_ful, F01_deq, F01_dot, F01_emp);
wire OB_deq = d_w;
OTMOD ob(CLK, RST, (!last_phase && F01_deq), F01_dot, OB_deq, OB_dot, OB_full, OB_req);
assign rsltbuf_enq = last_phase && F01_deq;
assign rsltbuf_deq = chnl_tx_data_ren && chnl_tx_data_valid;
SRL_FIFO #(4, `MERGW) rsltbuf(CLK, RST, rsltbuf_enq, rsltbuf_deq, F01_dot,
rslt, rsltbuf_emp, rsltbuf_ful, rsltbuf_cnt);
assign rslt_ready = !rsltbuf_emp;
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
reg [31:0] w_addr; //
reg [2:0] state; // state
reg [31:0] radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h, radr_i, radr_j, radr_k, radr_l, radr_m, radr_n, radr_o, radr_p;
(* mark_debug = "true" *) reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h, cnt_i, cnt_j, cnt_k, cnt_l, cnt_m, cnt_n, cnt_o, cnt_p;
reg c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h, c_i, c_j, c_k, c_l, c_m, c_n, c_o, c_p; // counter is full ?
always @(posedge CLK) begin
if (RST || pchange) begin
if (RST) state <= 0;
if (RST) {d_req, d_initadr, d_blocks} <= 0;
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, phase[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
radr_e <= ((`SELM_PER_WAY>>3)*4);
radr_f <= ((`SELM_PER_WAY>>3)*5);
radr_g <= ((`SELM_PER_WAY>>3)*6);
radr_h <= ((`SELM_PER_WAY>>3)*7);
radr_i <= ((`SELM_PER_WAY>>3)*8);
radr_j <= ((`SELM_PER_WAY>>3)*9);
radr_k <= ((`SELM_PER_WAY>>3)*10);
radr_l <= ((`SELM_PER_WAY>>3)*11);
radr_m <= ((`SELM_PER_WAY>>3)*12);
radr_n <= ((`SELM_PER_WAY>>3)*13);
radr_o <= ((`SELM_PER_WAY>>3)*14);
radr_p <= ((`SELM_PER_WAY>>3)*15);
{cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h, cnt_i, cnt_j, cnt_k, cnt_l, cnt_m, cnt_n, cnt_o, cnt_p} <= 0;
{c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h, c_i, c_j, c_k, c_l, c_m, c_n, c_o, c_p} <= 0;
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
state <= !(phase_zero);
if (d_req != 0) d_req <= 0;
else if (!d_busy) begin
if (OB_req) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr; //
w_addr <= w_addr + (`D_WS); // address for the next write
end
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req[1] && !c_a) begin req<=16'h0001; state<=3; end // first priority
else if (ib01_req[1] && !c_b) begin req<=16'h0002; state<=3; end //
else if (ib02_req[1] && !c_c) begin req<=16'h0004; state<=3; end //
else if (ib03_req[1] && !c_d) begin req<=16'h0008; state<=3; end //
else if (ib04_req[1] && !c_e) begin req<=16'h0010; state<=3; end //
else if (ib05_req[1] && !c_f) begin req<=16'h0020; state<=3; end //
else if (ib06_req[1] && !c_g) begin req<=16'h0040; state<=3; end //
else if (ib07_req[1] && !c_h) begin req<=16'h0080; state<=3; end //
else if (ib08_req[1] && !c_i) begin req<=16'h0100; state<=3; end //
else if (ib09_req[1] && !c_j) begin req<=16'h0200; state<=3; end //
else if (ib10_req[1] && !c_k) begin req<=16'h0400; state<=3; end //
else if (ib11_req[1] && !c_l) begin req<=16'h0800; state<=3; end //
else if (ib12_req[1] && !c_m) begin req<=16'h1000; state<=3; end //
else if (ib13_req[1] && !c_n) begin req<=16'h2000; state<=3; end //
else if (ib14_req[1] && !c_o) begin req<=16'h4000; state<=3; end //
else if (ib15_req[1] && !c_p) begin req<=16'h8000; state<=3; end //
else state<=2;
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req[0] && !c_a) begin req<=16'h0001; state<=3; end // second priority
else if (ib01_req[0] && !c_b) begin req<=16'h0002; state<=3; end //
else if (ib02_req[0] && !c_c) begin req<=16'h0004; state<=3; end //
else if (ib03_req[0] && !c_d) begin req<=16'h0008; state<=3; end //
else if (ib04_req[0] && !c_e) begin req<=16'h0010; state<=3; end //
else if (ib05_req[0] && !c_f) begin req<=16'h0020; state<=3; end //
else if (ib06_req[0] && !c_g) begin req<=16'h0040; state<=3; end //
else if (ib07_req[0] && !c_h) begin req<=16'h0080; state<=3; end //
else if (ib08_req[0] && !c_i) begin req<=16'h0100; state<=3; end //
else if (ib09_req[0] && !c_j) begin req<=16'h0200; state<=3; end //
else if (ib10_req[0] && !c_k) begin req<=16'h0400; state<=3; end //
else if (ib11_req[0] && !c_l) begin req<=16'h0800; state<=3; end //
else if (ib12_req[0] && !c_m) begin req<=16'h1000; state<=3; end //
else if (ib13_req[0] && !c_n) begin req<=16'h2000; state<=3; end //
else if (ib14_req[0] && !c_o) begin req<=16'h4000; state<=3; end //
else if (ib15_req[0] && !c_p) begin req<=16'h8000; state<=3; end //
else if (OB_req) begin state<=4; end // WRITE
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
case (req)
16'h0001: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase[0]);
radr_a <= radr_a+(`D_RS);
cnt_a <= cnt_a+1;
c_a <= (cnt_a>=`WAY_CN_);
end
16'h0002: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase[0]);
radr_b <= radr_b+(`D_RS);
cnt_b <= cnt_b+1;
c_b <= (cnt_b>=`WAY_CN_);
end
16'h0004: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase[0]);
radr_c <= radr_c+(`D_RS);
cnt_c <= cnt_c+1;
c_c <= (cnt_c>=`WAY_CN_);
end
16'h0008: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase[0]);
radr_d <= radr_d+(`D_RS);
cnt_d <= cnt_d+1;
c_d <= (cnt_d>=`WAY_CN_);
end
16'h0010: begin
d_initadr <= mux32(radr_e, (radr_e | (`SORT_ELM>>1)), phase[0]);
radr_e <= radr_e+(`D_RS);
cnt_e <= cnt_e+1;
c_e <= (cnt_e>=`WAY_CN_);
end
16'h0020: begin
d_initadr <= mux32(radr_f, (radr_f | (`SORT_ELM>>1)), phase[0]);
radr_f <= radr_f+(`D_RS);
cnt_f <= cnt_f+1;
c_f <= (cnt_f>=`WAY_CN_);
end
16'h0040: begin
d_initadr <= mux32(radr_g, (radr_g | (`SORT_ELM>>1)), phase[0]);
radr_g <= radr_g+(`D_RS);
cnt_g <= cnt_g+1;
c_g <= (cnt_g>=`WAY_CN_);
end
16'h0080: begin
d_initadr <= mux32(radr_h, (radr_h | (`SORT_ELM>>1)), phase[0]);
radr_h <= radr_h+(`D_RS);
cnt_h <= cnt_h+1;
c_h <= (cnt_h>=`WAY_CN_);
end
16'h0100: begin
d_initadr <= mux32(radr_i, (radr_i | (`SORT_ELM>>1)), phase[0]);
radr_i <= radr_i+(`D_RS);
cnt_i <= cnt_i+1;
c_i <= (cnt_i>=`WAY_CN_);
end
16'h0200: begin
d_initadr <= mux32(radr_j, (radr_j | (`SORT_ELM>>1)), phase[0]);
radr_j <= radr_j+(`D_RS);
cnt_j <= cnt_j+1;
c_j <= (cnt_j>=`WAY_CN_);
end
16'h0400: begin
d_initadr <= mux32(radr_k, (radr_k | (`SORT_ELM>>1)), phase[0]);
radr_k <= radr_k+(`D_RS);
cnt_k <= cnt_k+1;
c_k <= (cnt_k>=`WAY_CN_);
end
16'h0800: begin
d_initadr <= mux32(radr_l, (radr_l | (`SORT_ELM>>1)), phase[0]);
radr_l <= radr_l+(`D_RS);
cnt_l <= cnt_l+1;
c_l <= (cnt_l>=`WAY_CN_);
end
16'h1000: begin
d_initadr <= mux32(radr_m, (radr_m | (`SORT_ELM>>1)), phase[0]);
radr_m <= radr_m+(`D_RS);
cnt_m <= cnt_m+1;
c_m <= (cnt_m>=`WAY_CN_);
end
16'h2000: begin
d_initadr <= mux32(radr_n, (radr_n | (`SORT_ELM>>1)), phase[0]);
radr_n <= radr_n+(`D_RS);
cnt_n <= cnt_n+1;
c_n <= (cnt_n>=`WAY_CN_);
end
16'h4000: begin
d_initadr <= mux32(radr_o, (radr_o | (`SORT_ELM>>1)), phase[0]);
radr_o <= radr_o+(`D_RS);
cnt_o <= cnt_o+1;
c_o <= (cnt_o>=`WAY_CN_);
end
16'h8000: begin
d_initadr <= mux32(radr_p, (radr_p | (`SORT_ELM>>1)), phase[0]);
radr_p <= radr_p+(`D_RS);
cnt_p <= cnt_p+1;
c_p <= (cnt_p>=`WAY_CN_);
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_t <= req;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr; //
w_addr <= w_addr + (`D_WS); // address for the next write
end
end
////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
/**********************************************************************************************/
always @(posedge CLK) begin
dout_t <= mux512(d_dout, rx_data, phase_zero);
doen_t <= mux1(d_douten, rx_data_valid, phase_zero);
// Stage 0
////////////////////////////////////
dout_ta <= stnet_dout;
dout_tb <= stnet_dout;
doen_ta <= stnet_douten[0];
doen_tb <= stnet_douten[0];
req_ta <= stnet_douten[`SORT_WAY:1];
// Stage 1
////////////////////////////////////
dout_tc <= dout_ta;
dout_td <= dout_ta;
dout_te <= dout_tb;
dout_tf <= dout_tb;
doen_tc <= doen_ta;
doen_td <= doen_ta;
doen_te <= doen_tb;
doen_tf <= doen_tb;
req_tb <= req_ta;
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RST) begin
phase <= 0;
end else begin
if (elem==`SORT_ELM) phase <= phase + 1;
end
end
// for elem
// ###########################################################################
always @(posedge CLK) begin
if (RST) begin
elem <= 0;
end else begin
case ({OB_deq, (elem==`SORT_ELM)})
2'b01: elem <= 0;
2'b10: elem <= elem + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done <= (ecnt==8);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange <= (elem==`SORT_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst <= (ecnt==8) || pchange;
// for frst
// ###########################################################################
always @(posedge CLK) frst <= RST || (ecnt==8) || (elem==`SORT_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RST || iter_done || pchange) begin
ecnt <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase * `WAY_LOG));
end else begin
if (ecnt!=0 && F01_deq) ecnt <= ecnt - 4;
end
end
// for phase zero
// ###########################################################################
always @(posedge CLK) phase_zero <= (phase == 0);
// for last phase
// ###########################################################################
always @(posedge CLK) last_phase <= (phase == `LAST_PHASE);
// for debug
// ###########################################################################
(* mark_debug = "true" *) reg [31:0] dcnt;
always @(posedge CLK) begin
if (RST) begin
dcnt <= 0;
end else begin
case ({F01_deq, (dcnt==`SORT_ELM)})
2'b01: dcnt <= 0;
2'b10: dcnt <= dcnt + 4;
endcase
end
end
endmodule // CORE
/**************************************************************************************************/
`default_nettype wire
|
// --------------------------------------------------
//
// Fake implementation specific memory
//
// Sample implementation specific memory with test ports
// and 2-clock delay on output after read-enable asserted.
//
// --------------------------------------------------
module mem_16nm_ram8x64
(
input wire clk,
input wire mem_wr_en,
input wire [2:0] mem_wr_addr,
input wire [63:0] mem_wr_data,
input wire mem_rd_en,
input wire [2:0] mem_rd_addr,
output wire [63:0] mem_rd_data,
input wire bist_clk,
input wire bist_en,
input wire [2:0] bist_addr,
input wire [63:0] bist_wr_data,
output wire [63:0] bist_rd_data
);
// The memory declaration
reg [63:0] memory [7:0];
reg [63:0] mem_rd_data_i;
always @ (posedge clk) begin
if( mem_wr_en ) begin
memory[mem_wr_addr] <= #0 mem_wr_data;
end
if( mem_rd_en ) begin
mem_rd_data_i <= #0 memory[mem_rd_addr];
end
end
always @ (posedge clk) begin
mem_rd_data <= #0 mem_rd_data_i;
end
// Bist fake logic
always @ (posedge bist_clk ) begin
bist_rd_data <= #0 bist_wr_data;
end
endmodule
|
// file: clk_200_400.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___400.000______0.000______50.0_______85.815_____89.971
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________200.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_200_400,clk_wiz_v3_3,{component_name=clk_200_400,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clk_200_400
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (2.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
//Date : Tue Oct 17 19:42:11 2017
//Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
//Command : generate_target ip_design_wrapper.bd
//Design : ip_design_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module ip_design_wrapper
(BCLK,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FCLK_CLK1,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GPIO_tri_io,
IIC_0_scl_io,
IIC_0_sda_io,
LEDs_out,
LRCLK,
SDATA_I,
SDATA_O,
btns_5bits_tri_i,
sws_8bits_tri_i);
output BCLK;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
output FCLK_CLK1;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [1:0]GPIO_tri_io;
inout IIC_0_scl_io;
inout IIC_0_sda_io;
output [7:0]LEDs_out;
output LRCLK;
input SDATA_I;
output SDATA_O;
input [4:0]btns_5bits_tri_i;
input [7:0]sws_8bits_tri_i;
wire BCLK;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FCLK_CLK1;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [0:0]GPIO_tri_i_0;
wire [1:1]GPIO_tri_i_1;
wire [0:0]GPIO_tri_io_0;
wire [1:1]GPIO_tri_io_1;
wire [0:0]GPIO_tri_o_0;
wire [1:1]GPIO_tri_o_1;
wire [0:0]GPIO_tri_t_0;
wire [1:1]GPIO_tri_t_1;
wire IIC_0_scl_i;
wire IIC_0_scl_io;
wire IIC_0_scl_o;
wire IIC_0_scl_t;
wire IIC_0_sda_i;
wire IIC_0_sda_io;
wire IIC_0_sda_o;
wire IIC_0_sda_t;
wire [7:0]LEDs_out;
wire LRCLK;
wire SDATA_I;
wire SDATA_O;
wire [4:0]btns_5bits_tri_i;
wire [7:0]sws_8bits_tri_i;
IOBUF GPIO_tri_iobuf_0
(.I(GPIO_tri_o_0),
.IO(GPIO_tri_io[0]),
.O(GPIO_tri_i_0),
.T(GPIO_tri_t_0));
IOBUF GPIO_tri_iobuf_1
(.I(GPIO_tri_o_1),
.IO(GPIO_tri_io[1]),
.O(GPIO_tri_i_1),
.T(GPIO_tri_t_1));
IOBUF IIC_0_scl_iobuf
(.I(IIC_0_scl_o),
.IO(IIC_0_scl_io),
.O(IIC_0_scl_i),
.T(IIC_0_scl_t));
IOBUF IIC_0_sda_iobuf
(.I(IIC_0_sda_o),
.IO(IIC_0_sda_io),
.O(IIC_0_sda_i),
.T(IIC_0_sda_t));
ip_design ip_design_i
(.BCLK(BCLK),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FCLK_CLK1(FCLK_CLK1),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.GPIO_tri_i({GPIO_tri_i_1,GPIO_tri_i_0}),
.GPIO_tri_o({GPIO_tri_o_1,GPIO_tri_o_0}),
.GPIO_tri_t({GPIO_tri_t_1,GPIO_tri_t_0}),
.IIC_0_scl_i(IIC_0_scl_i),
.IIC_0_scl_o(IIC_0_scl_o),
.IIC_0_scl_t(IIC_0_scl_t),
.IIC_0_sda_i(IIC_0_sda_i),
.IIC_0_sda_o(IIC_0_sda_o),
.IIC_0_sda_t(IIC_0_sda_t),
.LEDs_out(LEDs_out),
.LRCLK(LRCLK),
.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.btns_5bits_tri_i(btns_5bits_tri_i),
.sws_8bits_tri_i(sws_8bits_tri_i));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_SYMBOL_V
`define SKY130_FD_SC_LP__DFSBP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_SYMBOL_V
|
`timescale 1ns/1ns
module sram_if_tb;
reg clk, rst;
initial begin
clk <= 0;
rst <= 1;
#105;
rst <= 0;
#10000
$display("test_tb done");
$finish;
end
always begin
#10 clk = ~clk;
end
reg [3:0] addr;
reg wen;
reg [31:0] wdata;
wire [31:0] rdata;
reg [2:0] st;
always @(posedge clk) begin
if (rst) begin
st <= 0;
addr <= 0;
wen <= 0;
wdata <= 0;
end else begin
case (st)
0: begin
addr <= 7;
wdata <= 5;
wen <= 1;
st <= 1;
end
1: begin
addr <= 8;
wdata <= 6;
wen <= 1;
st <= 2;
end
2: begin
addr <= 7;
wen <= 0;
st <= 3;
end
3: begin
addr <= 8;
if (rdata !== 5) begin
$display("ASSERTION FAILURE %x", rdata);
end
st <= 4;
end
4: begin
if (rdata !== 6) begin
$display("ASSERTION FAILURE %x", rdata);
end
st <= 5;
end
5: begin
end
endcase
end
end
mod_main m(.clk(clk), .rst(rst), .s_addr(addr), .s_wen(wen), .s_rdata(rdata), .s_wdata(wdata));
endmodule // sram_if_tb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR4BB_PP_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_PP_SYMBOL_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_16x512.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_16x512 (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [8:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.clocken0 (clken),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x512.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x512.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x512.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x512.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x512_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x512_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_2_V
`define SKY130_FD_SC_LS__TAPMET1_2_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog wrapper for tapmet1 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapmet1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapmet1_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapmet1 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapmet1_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapmet1 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_2_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:57:32 09/24/2013
// Design Name: Debounce
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_debounce.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Debounce
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_debounce;
// Inputs
reg clock;
reg reset;
reg [1:0] write_data_selector;
// Outputs
wire reset_sync;
wire [1:0] write_data_selector_sync;
// Instantiate the Unit Under Test (UUT)
Debounce uut (
.clock(clock),
.reset(reset),
.write_data_selector(write_data_selector),
.reset_sync(reset_sync),
.write_data_selector_sync(write_data_selector_sync)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
write_data_selector = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
// Date : Tue Mar 01 14:57:36 2016
// Host : Dries007Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/v_ram/v_ram_sim_netlist.v
// Design : v_ram
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "v_ram,blk_mem_gen_v8_3_1,{}" *) (* core_generation_info = "v_ram,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=v_ram.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=76800,C_READ_DEPTH_A=76800,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=76800,C_READ_DEPTH_B=76800,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=26,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.2184 mW}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_3_1,Vivado 2015.4" *)
(* NotValidForBitStream *)
module v_ram
(clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [16:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [16:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [11:0]doutb;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [11:0]dina;
wire [11:0]doutb;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_douta_UNCONNECTED;
wire [16:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [16:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "17" *)
(* C_ADDRB_WIDTH = "17" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "26" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 16.2184 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "v_ram.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "1" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "76800" *)
(* C_READ_DEPTH_B = "76800" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "76800" *)
(* C_WRITE_DEPTH_B = "76800" *)
(* C_WRITE_MODE_A = "NO_CHANGE" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
v_ram_blk_mem_gen_v8_3_1 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(NLW_U0_douta_UNCONNECTED[11:0]),
.doutb(doutb),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[16:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[16:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module v_ram_blk_mem_gen_generic_cstr
(doutb,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [11:0]doutb;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [11:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [11:0]dina;
wire [11:0]doutb;
wire ram_doutb;
wire ram_ena;
wire ram_enb;
wire \ramloop[10].ram.r_n_0 ;
wire \ramloop[10].ram.r_n_1 ;
wire \ramloop[10].ram.r_n_2 ;
wire \ramloop[10].ram.r_n_3 ;
wire \ramloop[10].ram.r_n_4 ;
wire \ramloop[10].ram.r_n_5 ;
wire \ramloop[10].ram.r_n_6 ;
wire \ramloop[10].ram.r_n_7 ;
wire \ramloop[10].ram.r_n_8 ;
wire \ramloop[11].ram.r_n_0 ;
wire \ramloop[11].ram.r_n_1 ;
wire \ramloop[11].ram.r_n_2 ;
wire \ramloop[11].ram.r_n_3 ;
wire \ramloop[11].ram.r_n_4 ;
wire \ramloop[11].ram.r_n_5 ;
wire \ramloop[11].ram.r_n_6 ;
wire \ramloop[11].ram.r_n_7 ;
wire \ramloop[11].ram.r_n_8 ;
wire \ramloop[12].ram.r_n_0 ;
wire \ramloop[12].ram.r_n_1 ;
wire \ramloop[12].ram.r_n_2 ;
wire \ramloop[12].ram.r_n_3 ;
wire \ramloop[12].ram.r_n_4 ;
wire \ramloop[12].ram.r_n_5 ;
wire \ramloop[12].ram.r_n_6 ;
wire \ramloop[12].ram.r_n_7 ;
wire \ramloop[12].ram.r_n_8 ;
wire \ramloop[13].ram.r_n_0 ;
wire \ramloop[13].ram.r_n_1 ;
wire \ramloop[13].ram.r_n_2 ;
wire \ramloop[13].ram.r_n_3 ;
wire \ramloop[13].ram.r_n_4 ;
wire \ramloop[13].ram.r_n_5 ;
wire \ramloop[13].ram.r_n_6 ;
wire \ramloop[13].ram.r_n_7 ;
wire \ramloop[13].ram.r_n_8 ;
wire \ramloop[14].ram.r_n_0 ;
wire \ramloop[14].ram.r_n_1 ;
wire \ramloop[14].ram.r_n_2 ;
wire \ramloop[14].ram.r_n_3 ;
wire \ramloop[14].ram.r_n_4 ;
wire \ramloop[14].ram.r_n_5 ;
wire \ramloop[14].ram.r_n_6 ;
wire \ramloop[14].ram.r_n_7 ;
wire \ramloop[14].ram.r_n_8 ;
wire \ramloop[15].ram.r_n_0 ;
wire \ramloop[15].ram.r_n_1 ;
wire \ramloop[15].ram.r_n_2 ;
wire \ramloop[15].ram.r_n_3 ;
wire \ramloop[15].ram.r_n_4 ;
wire \ramloop[15].ram.r_n_5 ;
wire \ramloop[15].ram.r_n_6 ;
wire \ramloop[15].ram.r_n_7 ;
wire \ramloop[15].ram.r_n_8 ;
wire \ramloop[16].ram.r_n_0 ;
wire \ramloop[16].ram.r_n_1 ;
wire \ramloop[16].ram.r_n_2 ;
wire \ramloop[16].ram.r_n_3 ;
wire \ramloop[16].ram.r_n_4 ;
wire \ramloop[16].ram.r_n_5 ;
wire \ramloop[16].ram.r_n_6 ;
wire \ramloop[16].ram.r_n_7 ;
wire \ramloop[16].ram.r_n_8 ;
wire \ramloop[17].ram.r_n_0 ;
wire \ramloop[17].ram.r_n_1 ;
wire \ramloop[17].ram.r_n_2 ;
wire \ramloop[17].ram.r_n_3 ;
wire \ramloop[17].ram.r_n_4 ;
wire \ramloop[17].ram.r_n_5 ;
wire \ramloop[17].ram.r_n_6 ;
wire \ramloop[17].ram.r_n_7 ;
wire \ramloop[17].ram.r_n_8 ;
wire \ramloop[18].ram.r_n_0 ;
wire \ramloop[18].ram.r_n_1 ;
wire \ramloop[18].ram.r_n_2 ;
wire \ramloop[18].ram.r_n_3 ;
wire \ramloop[18].ram.r_n_4 ;
wire \ramloop[18].ram.r_n_5 ;
wire \ramloop[18].ram.r_n_6 ;
wire \ramloop[18].ram.r_n_7 ;
wire \ramloop[18].ram.r_n_8 ;
wire \ramloop[19].ram.r_n_0 ;
wire \ramloop[19].ram.r_n_1 ;
wire \ramloop[19].ram.r_n_2 ;
wire \ramloop[19].ram.r_n_3 ;
wire \ramloop[19].ram.r_n_4 ;
wire \ramloop[19].ram.r_n_5 ;
wire \ramloop[19].ram.r_n_6 ;
wire \ramloop[19].ram.r_n_7 ;
wire \ramloop[19].ram.r_n_8 ;
wire \ramloop[1].ram.r_n_0 ;
wire \ramloop[20].ram.r_n_0 ;
wire \ramloop[20].ram.r_n_1 ;
wire \ramloop[20].ram.r_n_2 ;
wire \ramloop[20].ram.r_n_3 ;
wire \ramloop[20].ram.r_n_4 ;
wire \ramloop[20].ram.r_n_5 ;
wire \ramloop[20].ram.r_n_6 ;
wire \ramloop[20].ram.r_n_7 ;
wire \ramloop[20].ram.r_n_8 ;
wire \ramloop[21].ram.r_n_0 ;
wire \ramloop[21].ram.r_n_1 ;
wire \ramloop[21].ram.r_n_2 ;
wire \ramloop[21].ram.r_n_3 ;
wire \ramloop[21].ram.r_n_4 ;
wire \ramloop[21].ram.r_n_5 ;
wire \ramloop[21].ram.r_n_6 ;
wire \ramloop[21].ram.r_n_7 ;
wire \ramloop[21].ram.r_n_8 ;
wire \ramloop[22].ram.r_n_0 ;
wire \ramloop[22].ram.r_n_1 ;
wire \ramloop[22].ram.r_n_2 ;
wire \ramloop[22].ram.r_n_3 ;
wire \ramloop[22].ram.r_n_4 ;
wire \ramloop[22].ram.r_n_5 ;
wire \ramloop[22].ram.r_n_6 ;
wire \ramloop[22].ram.r_n_7 ;
wire \ramloop[22].ram.r_n_8 ;
wire \ramloop[23].ram.r_n_0 ;
wire \ramloop[23].ram.r_n_1 ;
wire \ramloop[23].ram.r_n_2 ;
wire \ramloop[23].ram.r_n_3 ;
wire \ramloop[23].ram.r_n_4 ;
wire \ramloop[23].ram.r_n_5 ;
wire \ramloop[23].ram.r_n_6 ;
wire \ramloop[23].ram.r_n_7 ;
wire \ramloop[23].ram.r_n_8 ;
wire \ramloop[2].ram.r_n_0 ;
wire \ramloop[2].ram.r_n_1 ;
wire \ramloop[2].ram.r_n_2 ;
wire \ramloop[3].ram.r_n_0 ;
wire \ramloop[3].ram.r_n_1 ;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_1 ;
wire \ramloop[5].ram.r_n_2 ;
wire \ramloop[5].ram.r_n_3 ;
wire \ramloop[5].ram.r_n_4 ;
wire \ramloop[5].ram.r_n_5 ;
wire \ramloop[5].ram.r_n_6 ;
wire \ramloop[5].ram.r_n_7 ;
wire \ramloop[5].ram.r_n_8 ;
wire \ramloop[6].ram.r_n_0 ;
wire \ramloop[6].ram.r_n_1 ;
wire \ramloop[6].ram.r_n_2 ;
wire \ramloop[6].ram.r_n_3 ;
wire \ramloop[6].ram.r_n_4 ;
wire \ramloop[6].ram.r_n_5 ;
wire \ramloop[6].ram.r_n_6 ;
wire \ramloop[6].ram.r_n_7 ;
wire \ramloop[6].ram.r_n_8 ;
wire \ramloop[7].ram.r_n_0 ;
wire \ramloop[7].ram.r_n_1 ;
wire \ramloop[7].ram.r_n_2 ;
wire \ramloop[7].ram.r_n_3 ;
wire \ramloop[7].ram.r_n_4 ;
wire \ramloop[7].ram.r_n_5 ;
wire \ramloop[7].ram.r_n_6 ;
wire \ramloop[7].ram.r_n_7 ;
wire \ramloop[7].ram.r_n_8 ;
wire \ramloop[8].ram.r_n_0 ;
wire \ramloop[8].ram.r_n_1 ;
wire \ramloop[8].ram.r_n_2 ;
wire \ramloop[8].ram.r_n_3 ;
wire \ramloop[8].ram.r_n_4 ;
wire \ramloop[8].ram.r_n_5 ;
wire \ramloop[8].ram.r_n_6 ;
wire \ramloop[8].ram.r_n_7 ;
wire \ramloop[8].ram.r_n_8 ;
wire \ramloop[9].ram.r_n_0 ;
wire \ramloop[9].ram.r_n_1 ;
wire \ramloop[9].ram.r_n_2 ;
wire \ramloop[9].ram.r_n_3 ;
wire \ramloop[9].ram.r_n_4 ;
wire \ramloop[9].ram.r_n_5 ;
wire \ramloop[9].ram.r_n_6 ;
wire \ramloop[9].ram.r_n_7 ;
wire \ramloop[9].ram.r_n_8 ;
wire [0:0]wea;
v_ram_blk_mem_gen_mux__parameterized0 \has_mux_b.B
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T (\ramloop[2].ram.r_n_2 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 (\ramloop[4].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ({\ramloop[14].ram.r_n_0 ,\ramloop[14].ram.r_n_1 ,\ramloop[14].ram.r_n_2 ,\ramloop[14].ram.r_n_3 ,\ramloop[14].ram.r_n_4 ,\ramloop[14].ram.r_n_5 ,\ramloop[14].ram.r_n_6 ,\ramloop[14].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ({\ramloop[13].ram.r_n_0 ,\ramloop[13].ram.r_n_1 ,\ramloop[13].ram.r_n_2 ,\ramloop[13].ram.r_n_3 ,\ramloop[13].ram.r_n_4 ,\ramloop[13].ram.r_n_5 ,\ramloop[13].ram.r_n_6 ,\ramloop[13].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ({\ramloop[20].ram.r_n_0 ,\ramloop[20].ram.r_n_1 ,\ramloop[20].ram.r_n_2 ,\ramloop[20].ram.r_n_3 ,\ramloop[20].ram.r_n_4 ,\ramloop[20].ram.r_n_5 ,\ramloop[20].ram.r_n_6 ,\ramloop[20].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ({\ramloop[19].ram.r_n_0 ,\ramloop[19].ram.r_n_1 ,\ramloop[19].ram.r_n_2 ,\ramloop[19].ram.r_n_3 ,\ramloop[19].ram.r_n_4 ,\ramloop[19].ram.r_n_5 ,\ramloop[19].ram.r_n_6 ,\ramloop[19].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ({\ramloop[18].ram.r_n_0 ,\ramloop[18].ram.r_n_1 ,\ramloop[18].ram.r_n_2 ,\ramloop[18].ram.r_n_3 ,\ramloop[18].ram.r_n_4 ,\ramloop[18].ram.r_n_5 ,\ramloop[18].ram.r_n_6 ,\ramloop[18].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ({\ramloop[17].ram.r_n_0 ,\ramloop[17].ram.r_n_1 ,\ramloop[17].ram.r_n_2 ,\ramloop[17].ram.r_n_3 ,\ramloop[17].ram.r_n_4 ,\ramloop[17].ram.r_n_5 ,\ramloop[17].ram.r_n_6 ,\ramloop[17].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ({\ramloop[23].ram.r_n_0 ,\ramloop[23].ram.r_n_1 ,\ramloop[23].ram.r_n_2 ,\ramloop[23].ram.r_n_3 ,\ramloop[23].ram.r_n_4 ,\ramloop[23].ram.r_n_5 ,\ramloop[23].ram.r_n_6 ,\ramloop[23].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ({\ramloop[22].ram.r_n_0 ,\ramloop[22].ram.r_n_1 ,\ramloop[22].ram.r_n_2 ,\ramloop[22].ram.r_n_3 ,\ramloop[22].ram.r_n_4 ,\ramloop[22].ram.r_n_5 ,\ramloop[22].ram.r_n_6 ,\ramloop[22].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ({\ramloop[21].ram.r_n_0 ,\ramloop[21].ram.r_n_1 ,\ramloop[21].ram.r_n_2 ,\ramloop[21].ram.r_n_3 ,\ramloop[21].ram.r_n_4 ,\ramloop[21].ram.r_n_5 ,\ramloop[21].ram.r_n_6 ,\ramloop[21].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 (\ramloop[7].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 (\ramloop[6].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21 (\ramloop[5].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22 (\ramloop[12].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23 (\ramloop[11].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24 (\ramloop[10].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25 (\ramloop[9].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26 (\ramloop[16].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27 (\ramloop[15].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28 (\ramloop[14].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29 (\ramloop[13].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30 (\ramloop[20].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31 (\ramloop[19].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32 (\ramloop[18].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33 (\ramloop[17].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34 (\ramloop[23].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35 (\ramloop[22].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36 (\ramloop[21].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ({\ramloop[12].ram.r_n_0 ,\ramloop[12].ram.r_n_1 ,\ramloop[12].ram.r_n_2 ,\ramloop[12].ram.r_n_3 ,\ramloop[12].ram.r_n_4 ,\ramloop[12].ram.r_n_5 ,\ramloop[12].ram.r_n_6 ,\ramloop[12].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ({\ramloop[11].ram.r_n_0 ,\ramloop[11].ram.r_n_1 ,\ramloop[11].ram.r_n_2 ,\ramloop[11].ram.r_n_3 ,\ramloop[11].ram.r_n_4 ,\ramloop[11].ram.r_n_5 ,\ramloop[11].ram.r_n_6 ,\ramloop[11].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ({\ramloop[10].ram.r_n_0 ,\ramloop[10].ram.r_n_1 ,\ramloop[10].ram.r_n_2 ,\ramloop[10].ram.r_n_3 ,\ramloop[10].ram.r_n_4 ,\ramloop[10].ram.r_n_5 ,\ramloop[10].ram.r_n_6 ,\ramloop[10].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ({\ramloop[16].ram.r_n_0 ,\ramloop[16].ram.r_n_1 ,\ramloop[16].ram.r_n_2 ,\ramloop[16].ram.r_n_3 ,\ramloop[16].ram.r_n_4 ,\ramloop[16].ram.r_n_5 ,\ramloop[16].ram.r_n_6 ,\ramloop[16].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ({\ramloop[15].ram.r_n_0 ,\ramloop[15].ram.r_n_1 ,\ramloop[15].ram.r_n_2 ,\ramloop[15].ram.r_n_3 ,\ramloop[15].ram.r_n_4 ,\ramloop[15].ram.r_n_5 ,\ramloop[15].ram.r_n_6 ,\ramloop[15].ram.r_n_7 }),
.DOBDO(\ramloop[1].ram.r_n_0 ),
.DOPBDOP(\ramloop[8].ram.r_n_8 ),
.DOUTB(ram_doutb),
.addrb(addrb[16:12]),
.clkb(clkb),
.doutb(doutb));
v_ram_blk_mem_gen_prim_width \ramloop[0].ram.r
(.DOUTB(ram_doutb),
.ENA(\ramloop[2].ram.r_n_0 ),
.ENB(\ramloop[2].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[0]));
v_ram_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[10].ram.r_n_0 ,\ramloop[10].ram.r_n_1 ,\ramloop[10].ram.r_n_2 ,\ramloop[10].ram.r_n_3 ,\ramloop[10].ram.r_n_4 ,\ramloop[10].ram.r_n_5 ,\ramloop[10].ram.r_n_6 ,\ramloop[10].ram.r_n_7 }),
.\doutb[11] (\ramloop[10].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[11].ram.r_n_0 ,\ramloop[11].ram.r_n_1 ,\ramloop[11].ram.r_n_2 ,\ramloop[11].ram.r_n_3 ,\ramloop[11].ram.r_n_4 ,\ramloop[11].ram.r_n_5 ,\ramloop[11].ram.r_n_6 ,\ramloop[11].ram.r_n_7 }),
.\doutb[11] (\ramloop[11].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[12].ram.r_n_0 ,\ramloop[12].ram.r_n_1 ,\ramloop[12].ram.r_n_2 ,\ramloop[12].ram.r_n_3 ,\ramloop[12].ram.r_n_4 ,\ramloop[12].ram.r_n_5 ,\ramloop[12].ram.r_n_6 ,\ramloop[12].ram.r_n_7 }),
.\doutb[11] (\ramloop[12].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[13].ram.r_n_0 ,\ramloop[13].ram.r_n_1 ,\ramloop[13].ram.r_n_2 ,\ramloop[13].ram.r_n_3 ,\ramloop[13].ram.r_n_4 ,\ramloop[13].ram.r_n_5 ,\ramloop[13].ram.r_n_6 ,\ramloop[13].ram.r_n_7 }),
.\doutb[11] (\ramloop[13].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[14].ram.r_n_0 ,\ramloop[14].ram.r_n_1 ,\ramloop[14].ram.r_n_2 ,\ramloop[14].ram.r_n_3 ,\ramloop[14].ram.r_n_4 ,\ramloop[14].ram.r_n_5 ,\ramloop[14].ram.r_n_6 ,\ramloop[14].ram.r_n_7 }),
.\doutb[11] (\ramloop[14].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized14 \ramloop[15].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[15].ram.r_n_0 ,\ramloop[15].ram.r_n_1 ,\ramloop[15].ram.r_n_2 ,\ramloop[15].ram.r_n_3 ,\ramloop[15].ram.r_n_4 ,\ramloop[15].ram.r_n_5 ,\ramloop[15].ram.r_n_6 ,\ramloop[15].ram.r_n_7 }),
.\doutb[11] (\ramloop[15].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized15 \ramloop[16].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[16].ram.r_n_0 ,\ramloop[16].ram.r_n_1 ,\ramloop[16].ram.r_n_2 ,\ramloop[16].ram.r_n_3 ,\ramloop[16].ram.r_n_4 ,\ramloop[16].ram.r_n_5 ,\ramloop[16].ram.r_n_6 ,\ramloop[16].ram.r_n_7 }),
.\doutb[11] (\ramloop[16].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized16 \ramloop[17].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[17].ram.r_n_0 ,\ramloop[17].ram.r_n_1 ,\ramloop[17].ram.r_n_2 ,\ramloop[17].ram.r_n_3 ,\ramloop[17].ram.r_n_4 ,\ramloop[17].ram.r_n_5 ,\ramloop[17].ram.r_n_6 ,\ramloop[17].ram.r_n_7 }),
.\doutb[11] (\ramloop[17].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized17 \ramloop[18].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[18].ram.r_n_0 ,\ramloop[18].ram.r_n_1 ,\ramloop[18].ram.r_n_2 ,\ramloop[18].ram.r_n_3 ,\ramloop[18].ram.r_n_4 ,\ramloop[18].ram.r_n_5 ,\ramloop[18].ram.r_n_6 ,\ramloop[18].ram.r_n_7 }),
.\doutb[11] (\ramloop[18].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized18 \ramloop[19].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[19].ram.r_n_0 ,\ramloop[19].ram.r_n_1 ,\ramloop[19].ram.r_n_2 ,\ramloop[19].ram.r_n_3 ,\ramloop[19].ram.r_n_4 ,\ramloop[19].ram.r_n_5 ,\ramloop[19].ram.r_n_6 ,\ramloop[19].ram.r_n_7 }),
.\doutb[11] (\ramloop[19].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.DOBDO(\ramloop[1].ram.r_n_0 ),
.addra(addra[13:0]),
.addrb(addrb[13:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[0]),
.ram_ena(ram_ena),
.ram_enb(ram_enb));
v_ram_blk_mem_gen_prim_width__parameterized19 \ramloop[20].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[20].ram.r_n_0 ,\ramloop[20].ram.r_n_1 ,\ramloop[20].ram.r_n_2 ,\ramloop[20].ram.r_n_3 ,\ramloop[20].ram.r_n_4 ,\ramloop[20].ram.r_n_5 ,\ramloop[20].ram.r_n_6 ,\ramloop[20].ram.r_n_7 }),
.\doutb[11] (\ramloop[20].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized20 \ramloop[21].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[21].ram.r_n_0 ,\ramloop[21].ram.r_n_1 ,\ramloop[21].ram.r_n_2 ,\ramloop[21].ram.r_n_3 ,\ramloop[21].ram.r_n_4 ,\ramloop[21].ram.r_n_5 ,\ramloop[21].ram.r_n_6 ,\ramloop[21].ram.r_n_7 }),
.\doutb[11] (\ramloop[21].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized21 \ramloop[22].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[22].ram.r_n_0 ,\ramloop[22].ram.r_n_1 ,\ramloop[22].ram.r_n_2 ,\ramloop[22].ram.r_n_3 ,\ramloop[22].ram.r_n_4 ,\ramloop[22].ram.r_n_5 ,\ramloop[22].ram.r_n_6 ,\ramloop[22].ram.r_n_7 }),
.\doutb[11] (\ramloop[22].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized22 \ramloop[23].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[23].ram.r_n_0 ,\ramloop[23].ram.r_n_1 ,\ramloop[23].ram.r_n_2 ,\ramloop[23].ram.r_n_3 ,\ramloop[23].ram.r_n_4 ,\ramloop[23].ram.r_n_5 ,\ramloop[23].ram.r_n_6 ,\ramloop[23].ram.r_n_7 }),
.\doutb[11] (\ramloop[23].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.DOUTB(\ramloop[2].ram.r_n_2 ),
.ENA(\ramloop[2].ram.r_n_0 ),
.ENB(\ramloop[2].ram.r_n_1 ),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[1]),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2:1]),
.\doutb[2] ({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 }),
.ram_ena(ram_ena),
.ram_enb(ram_enb),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.DOUTB(\ramloop[4].ram.r_n_0 ),
.ENA(\ramloop[2].ram.r_n_0 ),
.ENB(\ramloop[2].ram.r_n_1 ),
.addra(addra[15:0]),
.addrb(addrb[15:0]),
.clka(clka),
.clkb(clkb),
.dina(dina[2]));
v_ram_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\doutb[11] (\ramloop[5].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\doutb[11] (\ramloop[6].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.\doutb[11] (\ramloop[7].ram.r_n_8 ),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.DOPBDOP(\ramloop[8].ram.r_n_8 ),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }),
.wea(wea));
v_ram_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:3]),
.\doutb[10] ({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }),
.\doutb[11] (\ramloop[9].ram.r_n_8 ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module v_ram_blk_mem_gen_mux__parameterized0
(doutb,
DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
addrb,
clkb,
DOUTB,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ,
DOPBDOP,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36 );
output [11:0]doutb;
input [0:0]DOBDO;
input [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [4:0]addrb;
input clkb;
input [0:0]DOUTB;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ;
input [0:0]DOPBDOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ;
wire [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ;
wire [0:0]DOBDO;
wire [0:0]DOPBDOP;
wire [0:0]DOUTB;
wire [4:0]addrb;
wire clkb;
wire [11:0]doutb;
wire \doutb[0]_INST_0_i_1_n_0 ;
wire \doutb[10]_INST_0_i_1_n_0 ;
wire \doutb[10]_INST_0_i_2_n_0 ;
wire \doutb[10]_INST_0_i_3_n_0 ;
wire \doutb[10]_INST_0_i_4_n_0 ;
wire \doutb[10]_INST_0_i_5_n_0 ;
wire \doutb[10]_INST_0_i_6_n_0 ;
wire \doutb[10]_INST_0_i_7_n_0 ;
wire \doutb[11]_INST_0_i_1_n_0 ;
wire \doutb[11]_INST_0_i_2_n_0 ;
wire \doutb[11]_INST_0_i_3_n_0 ;
wire \doutb[11]_INST_0_i_4_n_0 ;
wire \doutb[11]_INST_0_i_5_n_0 ;
wire \doutb[11]_INST_0_i_6_n_0 ;
wire \doutb[11]_INST_0_i_7_n_0 ;
wire \doutb[1]_INST_0_i_1_n_0 ;
wire \doutb[2]_INST_0_i_1_n_0 ;
wire \doutb[3]_INST_0_i_1_n_0 ;
wire \doutb[3]_INST_0_i_2_n_0 ;
wire \doutb[3]_INST_0_i_3_n_0 ;
wire \doutb[3]_INST_0_i_4_n_0 ;
wire \doutb[3]_INST_0_i_5_n_0 ;
wire \doutb[3]_INST_0_i_6_n_0 ;
wire \doutb[3]_INST_0_i_7_n_0 ;
wire \doutb[4]_INST_0_i_1_n_0 ;
wire \doutb[4]_INST_0_i_2_n_0 ;
wire \doutb[4]_INST_0_i_3_n_0 ;
wire \doutb[4]_INST_0_i_4_n_0 ;
wire \doutb[4]_INST_0_i_5_n_0 ;
wire \doutb[4]_INST_0_i_6_n_0 ;
wire \doutb[4]_INST_0_i_7_n_0 ;
wire \doutb[5]_INST_0_i_1_n_0 ;
wire \doutb[5]_INST_0_i_2_n_0 ;
wire \doutb[5]_INST_0_i_3_n_0 ;
wire \doutb[5]_INST_0_i_4_n_0 ;
wire \doutb[5]_INST_0_i_5_n_0 ;
wire \doutb[5]_INST_0_i_6_n_0 ;
wire \doutb[5]_INST_0_i_7_n_0 ;
wire \doutb[6]_INST_0_i_1_n_0 ;
wire \doutb[6]_INST_0_i_2_n_0 ;
wire \doutb[6]_INST_0_i_3_n_0 ;
wire \doutb[6]_INST_0_i_4_n_0 ;
wire \doutb[6]_INST_0_i_5_n_0 ;
wire \doutb[6]_INST_0_i_6_n_0 ;
wire \doutb[6]_INST_0_i_7_n_0 ;
wire \doutb[7]_INST_0_i_1_n_0 ;
wire \doutb[7]_INST_0_i_2_n_0 ;
wire \doutb[7]_INST_0_i_3_n_0 ;
wire \doutb[7]_INST_0_i_4_n_0 ;
wire \doutb[7]_INST_0_i_5_n_0 ;
wire \doutb[7]_INST_0_i_6_n_0 ;
wire \doutb[7]_INST_0_i_7_n_0 ;
wire \doutb[8]_INST_0_i_1_n_0 ;
wire \doutb[8]_INST_0_i_2_n_0 ;
wire \doutb[8]_INST_0_i_3_n_0 ;
wire \doutb[8]_INST_0_i_4_n_0 ;
wire \doutb[8]_INST_0_i_5_n_0 ;
wire \doutb[8]_INST_0_i_6_n_0 ;
wire \doutb[8]_INST_0_i_7_n_0 ;
wire \doutb[9]_INST_0_i_1_n_0 ;
wire \doutb[9]_INST_0_i_2_n_0 ;
wire \doutb[9]_INST_0_i_3_n_0 ;
wire \doutb[9]_INST_0_i_4_n_0 ;
wire \doutb[9]_INST_0_i_5_n_0 ;
wire \doutb[9]_INST_0_i_6_n_0 ;
wire \doutb[9]_INST_0_i_7_n_0 ;
wire [4:0]sel_pipe;
wire [4:0]sel_pipe_d1;
MUXF7 \doutb[0]_INST_0
(.I0(DOUTB),
.I1(\doutb[0]_INST_0_i_1_n_0 ),
.O(doutb[0]),
.S(sel_pipe_d1[4]));
LUT3 #(
.INIT(8'h04))
\doutb[0]_INST_0_i_1
(.I0(sel_pipe_d1[2]),
.I1(DOBDO),
.I2(sel_pipe_d1[3]),
.O(\doutb[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[10]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[10]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[10]_INST_0_i_2_n_0 ),
.I5(\doutb[10]_INST_0_i_3_n_0 ),
.O(doutb[10]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[10]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [7]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [7]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [7]),
.O(\doutb[10]_INST_0_i_1_n_0 ));
MUXF7 \doutb[10]_INST_0_i_2
(.I0(\doutb[10]_INST_0_i_4_n_0 ),
.I1(\doutb[10]_INST_0_i_5_n_0 ),
.O(\doutb[10]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[10]_INST_0_i_3
(.I0(\doutb[10]_INST_0_i_6_n_0 ),
.I1(\doutb[10]_INST_0_i_7_n_0 ),
.O(\doutb[10]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[10]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [7]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [7]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [7]),
.O(\doutb[10]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[10]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [7]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [7]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [7]),
.O(\doutb[10]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[10]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [7]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [7]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [7]),
.O(\doutb[10]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[10]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [7]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [7]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [7]),
.O(\doutb[10]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[11]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[11]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[11]_INST_0_i_2_n_0 ),
.I5(\doutb[11]_INST_0_i_3_n_0 ),
.O(doutb[11]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[11]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34 ),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35 ),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36 ),
.O(\doutb[11]_INST_0_i_1_n_0 ));
MUXF7 \doutb[11]_INST_0_i_2
(.I0(\doutb[11]_INST_0_i_4_n_0 ),
.I1(\doutb[11]_INST_0_i_5_n_0 ),
.O(\doutb[11]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[11]_INST_0_i_3
(.I0(\doutb[11]_INST_0_i_6_n_0 ),
.I1(\doutb[11]_INST_0_i_7_n_0 ),
.O(\doutb[11]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[11]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27 ),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28 ),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29 ),
.O(\doutb[11]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[11]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31 ),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32 ),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33 ),
.O(\doutb[11]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[11]_INST_0_i_6
(.I0(DOPBDOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21 ),
.O(\doutb[11]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[11]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22 ),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23 ),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24 ),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25 ),
.O(\doutb[11]_INST_0_i_7_n_0 ));
MUXF7 \doutb[1]_INST_0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T ),
.I1(\doutb[1]_INST_0_i_1_n_0 ),
.O(doutb[1]),
.S(sel_pipe_d1[4]));
LUT3 #(
.INIT(8'h04))
\doutb[1]_INST_0_i_1
(.I0(sel_pipe_d1[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I2(sel_pipe_d1[3]),
.O(\doutb[1]_INST_0_i_1_n_0 ));
MUXF7 \doutb[2]_INST_0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0 ),
.I1(\doutb[2]_INST_0_i_1_n_0 ),
.O(doutb[2]),
.S(sel_pipe_d1[4]));
LUT3 #(
.INIT(8'h04))
\doutb[2]_INST_0_i_1
(.I0(sel_pipe_d1[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I2(sel_pipe_d1[3]),
.O(\doutb[2]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[3]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[3]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[3]_INST_0_i_2_n_0 ),
.I5(\doutb[3]_INST_0_i_3_n_0 ),
.O(doutb[3]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[3]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [0]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [0]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [0]),
.O(\doutb[3]_INST_0_i_1_n_0 ));
MUXF7 \doutb[3]_INST_0_i_2
(.I0(\doutb[3]_INST_0_i_4_n_0 ),
.I1(\doutb[3]_INST_0_i_5_n_0 ),
.O(\doutb[3]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[3]_INST_0_i_3
(.I0(\doutb[3]_INST_0_i_6_n_0 ),
.I1(\doutb[3]_INST_0_i_7_n_0 ),
.O(\doutb[3]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[3]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [0]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [0]),
.O(\doutb[3]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[3]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [0]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [0]),
.O(\doutb[3]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[3]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [0]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [0]),
.O(\doutb[3]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[3]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [0]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [0]),
.O(\doutb[3]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[4]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[4]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[4]_INST_0_i_2_n_0 ),
.I5(\doutb[4]_INST_0_i_3_n_0 ),
.O(doutb[4]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[4]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [1]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [1]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [1]),
.O(\doutb[4]_INST_0_i_1_n_0 ));
MUXF7 \doutb[4]_INST_0_i_2
(.I0(\doutb[4]_INST_0_i_4_n_0 ),
.I1(\doutb[4]_INST_0_i_5_n_0 ),
.O(\doutb[4]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[4]_INST_0_i_3
(.I0(\doutb[4]_INST_0_i_6_n_0 ),
.I1(\doutb[4]_INST_0_i_7_n_0 ),
.O(\doutb[4]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[4]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [1]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [1]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [1]),
.O(\doutb[4]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[4]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [1]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [1]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [1]),
.O(\doutb[4]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[4]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [1]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [1]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [1]),
.O(\doutb[4]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[4]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [1]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [1]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [1]),
.O(\doutb[4]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[5]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[5]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[5]_INST_0_i_2_n_0 ),
.I5(\doutb[5]_INST_0_i_3_n_0 ),
.O(doutb[5]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[5]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [2]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [2]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [2]),
.O(\doutb[5]_INST_0_i_1_n_0 ));
MUXF7 \doutb[5]_INST_0_i_2
(.I0(\doutb[5]_INST_0_i_4_n_0 ),
.I1(\doutb[5]_INST_0_i_5_n_0 ),
.O(\doutb[5]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[5]_INST_0_i_3
(.I0(\doutb[5]_INST_0_i_6_n_0 ),
.I1(\doutb[5]_INST_0_i_7_n_0 ),
.O(\doutb[5]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[5]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [2]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [2]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [2]),
.O(\doutb[5]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[5]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [2]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [2]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [2]),
.O(\doutb[5]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[5]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [2]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [2]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [2]),
.O(\doutb[5]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[5]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [2]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [2]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [2]),
.O(\doutb[5]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[6]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[6]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[6]_INST_0_i_2_n_0 ),
.I5(\doutb[6]_INST_0_i_3_n_0 ),
.O(doutb[6]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[6]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [3]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [3]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [3]),
.O(\doutb[6]_INST_0_i_1_n_0 ));
MUXF7 \doutb[6]_INST_0_i_2
(.I0(\doutb[6]_INST_0_i_4_n_0 ),
.I1(\doutb[6]_INST_0_i_5_n_0 ),
.O(\doutb[6]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[6]_INST_0_i_3
(.I0(\doutb[6]_INST_0_i_6_n_0 ),
.I1(\doutb[6]_INST_0_i_7_n_0 ),
.O(\doutb[6]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[6]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [3]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [3]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [3]),
.O(\doutb[6]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[6]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [3]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [3]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [3]),
.O(\doutb[6]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[6]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [3]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [3]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [3]),
.O(\doutb[6]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[6]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [3]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [3]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [3]),
.O(\doutb[6]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[7]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[7]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[7]_INST_0_i_2_n_0 ),
.I5(\doutb[7]_INST_0_i_3_n_0 ),
.O(doutb[7]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[7]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [4]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [4]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [4]),
.O(\doutb[7]_INST_0_i_1_n_0 ));
MUXF7 \doutb[7]_INST_0_i_2
(.I0(\doutb[7]_INST_0_i_4_n_0 ),
.I1(\doutb[7]_INST_0_i_5_n_0 ),
.O(\doutb[7]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[7]_INST_0_i_3
(.I0(\doutb[7]_INST_0_i_6_n_0 ),
.I1(\doutb[7]_INST_0_i_7_n_0 ),
.O(\doutb[7]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[7]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [4]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [4]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [4]),
.O(\doutb[7]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[7]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [4]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [4]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [4]),
.O(\doutb[7]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[7]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [4]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [4]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [4]),
.O(\doutb[7]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[7]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [4]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [4]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [4]),
.O(\doutb[7]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[8]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[8]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[8]_INST_0_i_2_n_0 ),
.I5(\doutb[8]_INST_0_i_3_n_0 ),
.O(doutb[8]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[8]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [5]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [5]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [5]),
.O(\doutb[8]_INST_0_i_1_n_0 ));
MUXF7 \doutb[8]_INST_0_i_2
(.I0(\doutb[8]_INST_0_i_4_n_0 ),
.I1(\doutb[8]_INST_0_i_5_n_0 ),
.O(\doutb[8]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[8]_INST_0_i_3
(.I0(\doutb[8]_INST_0_i_6_n_0 ),
.I1(\doutb[8]_INST_0_i_7_n_0 ),
.O(\doutb[8]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[8]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [5]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [5]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [5]),
.O(\doutb[8]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[8]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [5]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [5]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [5]),
.O(\doutb[8]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[8]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [5]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [5]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [5]),
.O(\doutb[8]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[8]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [5]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [5]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [5]),
.O(\doutb[8]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h10FF105510AA1000))
\doutb[9]_INST_0
(.I0(sel_pipe_d1[3]),
.I1(sel_pipe_d1[2]),
.I2(\doutb[9]_INST_0_i_1_n_0 ),
.I3(sel_pipe_d1[4]),
.I4(\doutb[9]_INST_0_i_2_n_0 ),
.I5(\doutb[9]_INST_0_i_3_n_0 ),
.O(doutb[9]));
LUT5 #(
.INIT(32'h30BB3088))
\doutb[9]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [6]),
.I1(sel_pipe_d1[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 [6]),
.I3(sel_pipe_d1[0]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 [6]),
.O(\doutb[9]_INST_0_i_1_n_0 ));
MUXF7 \doutb[9]_INST_0_i_2
(.I0(\doutb[9]_INST_0_i_4_n_0 ),
.I1(\doutb[9]_INST_0_i_5_n_0 ),
.O(\doutb[9]_INST_0_i_2_n_0 ),
.S(sel_pipe_d1[2]));
MUXF7 \doutb[9]_INST_0_i_3
(.I0(\doutb[9]_INST_0_i_6_n_0 ),
.I1(\doutb[9]_INST_0_i_7_n_0 ),
.O(\doutb[9]_INST_0_i_3_n_0 ),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[9]_INST_0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 [6]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 [6]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 [6]),
.O(\doutb[9]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[9]_INST_0_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 [6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [6]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [6]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [6]),
.O(\doutb[9]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[9]_INST_0_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [6]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [6]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 [6]),
.O(\doutb[9]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\doutb[9]_INST_0_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [6]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [6]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [6]),
.O(\doutb[9]_INST_0_i_7_n_0 ));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[2]),
.Q(sel_pipe_d1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[3]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[3]),
.Q(sel_pipe_d1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[4]
(.C(clkb),
.CE(1'b1),
.D(sel_pipe[4]),
.Q(sel_pipe_d1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clkb),
.CE(1'b1),
.D(addrb[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clkb),
.CE(1'b1),
.D(addrb[1]),
.Q(sel_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]
(.C(clkb),
.CE(1'b1),
.D(addrb[2]),
.Q(sel_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]
(.C(clkb),
.CE(1'b1),
.D(addrb[3]),
.Q(sel_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]
(.C(clkb),
.CE(1'b1),
.D(addrb[4]),
.Q(sel_pipe[4]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width
(DOUTB,
clka,
clkb,
ENA,
ENB,
addra,
addrb,
dina);
output [0:0]DOUTB;
input clka;
input clkb;
input ENA;
input ENB;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
v_ram_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized0
(DOBDO,
clka,
clkb,
ram_ena,
ram_enb,
addra,
addrb,
dina);
output [0:0]DOBDO;
input clka;
input clkb;
input ram_ena;
input ram_enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
wire [0:0]DOBDO;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire ram_ena;
wire ram_enb;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.DOBDO(DOBDO),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.ram_ena(ram_ena),
.ram_enb(ram_enb));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized1
(ENA,
ENB,
DOUTB,
addra,
wea,
addrb,
clka,
clkb,
dina);
output ENA;
output ENB;
output [0:0]DOUTB;
input [16:0]addra;
input [0:0]wea;
input [16:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized10
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized10 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized11
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized11 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized12
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized12 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized13
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized13 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized14
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized14 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized15
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized15 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized16
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized16 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized17
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized17 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized18
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized18 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized19
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized19 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized2
(\doutb[2] ,
ram_ena,
ram_enb,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [1:0]\doutb[2] ;
output ram_ena;
output ram_enb;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [1:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]\doutb[2] ;
wire ram_ena;
wire ram_enb;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[2] (\doutb[2] ),
.ram_ena(ram_ena),
.ram_enb(ram_enb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized20
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized20 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized21
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized21 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized22
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized22 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized3
(DOUTB,
clka,
clkb,
ENA,
ENB,
addra,
addrb,
dina);
output [0:0]DOUTB;
input clka;
input clkb;
input ENA;
input ENB;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized3 \prim_init.ram
(.DOUTB(DOUTB),
.ENA(ENA),
.ENB(ENB),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized4
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized4 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized5
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized5 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized6
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized6 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized7
(\doutb[10] ,
DOPBDOP,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]DOPBDOP;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [0:0]DOPBDOP;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized7 \prim_init.ram
(.DOPBDOP(DOPBDOP),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized8
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized8 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module v_ram_blk_mem_gen_prim_width__parameterized9
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]wea;
v_ram_blk_mem_gen_prim_wrapper_init__parameterized9 \prim_init.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.\doutb[10] (\doutb[10] ),
.\doutb[11] (\doutb[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init
(DOUTB,
clka,
clkb,
ENA,
ENB,
addra,
addrb,
dina);
output [0:0]DOUTB;
input clka;
input clkb;
input ENA;
input ENB;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized0
(DOBDO,
clka,
clkb,
ram_ena,
ram_enb,
addra,
addrb,
dina);
output [0:0]DOBDO;
input clka;
input clkb;
input ram_ena;
input ram_enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
wire [0:0]DOBDO;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire ram_ena;
wire ram_enb;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:1],DOBDO}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ram_ena),
.ENBWREN(ram_enb),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized1
(ENA,
ENB,
DOUTB,
addra,
wea,
addrb,
clka,
clkb,
dina);
output ENA;
output ENB;
output [0:0]DOUTB;
input [16:0]addra;
input [0:0]wea;
input [16:0]addrb;
input clka;
input clkb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra[15:0]),
.ADDRBWRADDR(addrb[15:0]),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1
(.I0(addra[16]),
.I1(wea),
.O(ENA));
LUT1 #(
.INIT(2'h1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2
(.I0(addrb[16]),
.O(ENB));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized10
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [6:6]ena_array;
wire [6:6]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__5
(.I0(addra[14]),
.I1(wea),
.I2(addra[15]),
.I3(addra[12]),
.I4(addra[16]),
.I5(addra[13]),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__5
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[12]),
.I3(addrb[13]),
.I4(addrb[14]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized11
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [7:7]ena_array;
wire [7:7]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0008000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__6
(.I0(addra[12]),
.I1(addra[13]),
.I2(addra[16]),
.I3(addra[15]),
.I4(wea),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h10000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__6
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[14]),
.I3(addrb[12]),
.I4(addrb[13]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized12
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [8:8]ena_array;
wire [8:8]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000008))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__7
(.I0(addra[15]),
.I1(wea),
.I2(addra[12]),
.I3(addra[13]),
.I4(addra[16]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__7
(.I0(addrb[16]),
.I1(addrb[14]),
.I2(addrb[15]),
.I3(addrb[12]),
.I4(addrb[13]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized13
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [9:9]ena_array;
wire [9:9]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__8
(.I0(addra[12]),
.I1(wea),
.I2(addra[13]),
.I3(addra[14]),
.I4(addra[16]),
.I5(addra[15]),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__8
(.I0(addrb[16]),
.I1(addrb[14]),
.I2(addrb[13]),
.I3(addrb[12]),
.I4(addrb[15]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized14
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [10:10]ena_array;
wire [10:10]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__9
(.I0(addra[15]),
.I1(wea),
.I2(addra[12]),
.I3(addra[14]),
.I4(addra[16]),
.I5(addra[13]),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__9
(.I0(addrb[16]),
.I1(addrb[14]),
.I2(addrb[12]),
.I3(addrb[13]),
.I4(addrb[15]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized15
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [11:11]ena_array;
wire [11:11]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0008000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__10
(.I0(addra[12]),
.I1(addra[13]),
.I2(addra[16]),
.I3(addra[14]),
.I4(wea),
.I5(addra[15]),
.O(ena_array));
LUT5 #(
.INIT(32'h10000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__10
(.I0(addrb[16]),
.I1(addrb[14]),
.I2(addrb[15]),
.I3(addrb[12]),
.I4(addrb[13]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized16
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [12:12]ena_array;
wire [12:12]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__11
(.I0(addra[15]),
.I1(wea),
.I2(addra[12]),
.I3(addra[13]),
.I4(addra[16]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__11
(.I0(addrb[16]),
.I1(addrb[13]),
.I2(addrb[12]),
.I3(addrb[14]),
.I4(addrb[15]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized17
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [13:13]ena_array;
wire [13:13]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0008000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__12
(.I0(addra[12]),
.I1(addra[15]),
.I2(addra[16]),
.I3(addra[13]),
.I4(wea),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h10000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__12
(.I0(addrb[16]),
.I1(addrb[13]),
.I2(addrb[15]),
.I3(addrb[12]),
.I4(addrb[14]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized18
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [14:14]ena_array;
wire [14:14]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0008000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__13
(.I0(addra[15]),
.I1(addra[13]),
.I2(addra[16]),
.I3(addra[12]),
.I4(wea),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h10000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__13
(.I0(addrb[16]),
.I1(addrb[12]),
.I2(addrb[15]),
.I3(addrb[13]),
.I4(addrb[14]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized19
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [15:15]ena_array;
wire [15:15]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0800000000000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__14
(.I0(wea),
.I1(addra[12]),
.I2(addra[16]),
.I3(addra[13]),
.I4(addra[15]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h40000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__14
(.I0(addrb[16]),
.I1(addrb[15]),
.I2(addrb[14]),
.I3(addrb[12]),
.I4(addrb[13]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized2
(\doutb[2] ,
ram_ena,
ram_enb,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [1:0]\doutb[2] ;
output ram_ena;
output ram_enb;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [1:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]\doutb[2] ;
wire ram_ena;
wire ram_enb;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
LUT4 #(
.INIT(16'h0008))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1
(.I0(wea),
.I1(addra[16]),
.I2(addra[15]),
.I3(addra[14]),
.O(ram_ena));
LUT3 #(
.INIT(8'h10))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2
(.I0(addrb[15]),
.I1(addrb[14]),
.I2(addrb[16]),
.O(ram_enb));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[13:0],1'b1}),
.ADDRBWRADDR({1'b1,addrb[13:0],1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],\doutb[2] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_ena),
.ENBWREN(ram_enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized20
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [16:16]ena_array;
wire [16:16]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000008))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__15
(.I0(wea),
.I1(addra[16]),
.I2(addra[15]),
.I3(addra[12]),
.I4(addra[13]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__15
(.I0(addrb[15]),
.I1(addrb[14]),
.I2(addrb[16]),
.I3(addrb[12]),
.I4(addrb[13]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized21
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [17:17]ena_array;
wire [17:17]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__16
(.I0(addra[12]),
.I1(addra[16]),
.I2(addra[15]),
.I3(addra[13]),
.I4(addra[14]),
.I5(wea),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__16
(.I0(addrb[15]),
.I1(addrb[14]),
.I2(addrb[13]),
.I3(addrb[12]),
.I4(addrb[16]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized22
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [18:18]ena_array;
wire [18:18]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__17
(.I0(wea),
.I1(addra[16]),
.I2(addra[15]),
.I3(addra[12]),
.I4(addra[14]),
.I5(addra[13]),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__17
(.I0(addrb[15]),
.I1(addrb[14]),
.I2(addrb[12]),
.I3(addrb[13]),
.I4(addrb[16]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized3
(DOUTB,
clka,
clkb,
ENA,
ENB,
addra,
addrb,
dina);
output [0:0]DOUTB;
input clka;
input clkb;
input ENA;
input ENB;
input [15:0]addra;
input [15:0]addrb;
input [0:0]dina;
wire CASCADEINA;
wire CASCADEINB;
wire [0:0]DOUTB;
wire ENA;
wire ENB;
wire [15:0]addra;
wire [15:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED ;
wire [31:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("LOWER"),
.RAM_EXTENSION_B("LOWER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(CASCADEINA),
.CASCADEOUTB(CASCADEINB),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED [31:0]),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("UPPER"),
.RAM_EXTENSION_B("UPPER"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED [31:1],DOUTB}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ENA),
.ENBWREN(ENB),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized4
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000002))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wea),
.I1(addra[16]),
.I2(addra[13]),
.I3(addra[12]),
.I4(addra[15]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h00000001))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[12]),
.I3(addrb[13]),
.I4(addrb[14]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized5
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [1:1]ena_array;
wire [1:1]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000008))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0
(.I0(addra[12]),
.I1(wea),
.I2(addra[15]),
.I3(addra[13]),
.I4(addra[16]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[12]),
.I3(addrb[13]),
.I4(addrb[14]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized6
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [2:2]ena_array;
wire [2:2]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000008))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1
(.I0(addra[13]),
.I1(wea),
.I2(addra[15]),
.I3(addra[12]),
.I4(addra[16]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[13]),
.I3(addrb[12]),
.I4(addrb[14]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized7
(\doutb[10] ,
DOPBDOP,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]DOPBDOP;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [0:0]DOPBDOP;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [3:3]ena_array;
wire [3:3]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__2
(.I0(addra[12]),
.I1(wea),
.I2(addra[15]),
.I3(addra[14]),
.I4(addra[16]),
.I5(addra[13]),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__2
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[14]),
.I3(addrb[12]),
.I4(addrb[13]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized8
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [4:4]ena_array;
wire [4:4]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000008))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__3
(.I0(addra[14]),
.I1(wea),
.I2(addra[15]),
.I3(addra[13]),
.I4(addra[16]),
.I5(addra[12]),
.O(ena_array));
LUT5 #(
.INIT(32'h00000010))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__3
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[14]),
.I3(addrb[12]),
.I4(addrb[13]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module v_ram_blk_mem_gen_prim_wrapper_init__parameterized9
(\doutb[10] ,
\doutb[11] ,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [7:0]\doutb[10] ;
output [0:0]\doutb[11] ;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [8:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [7:0]\doutb[10] ;
wire [0:0]\doutb[11] ;
wire [5:5]ena_array;
wire [5:5]enb_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\doutb[10] }),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\doutb[11] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000800000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__4
(.I0(addra[12]),
.I1(wea),
.I2(addra[15]),
.I3(addra[13]),
.I4(addra[16]),
.I5(addra[14]),
.O(ena_array));
LUT5 #(
.INIT(32'h01000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__4
(.I0(addrb[15]),
.I1(addrb[16]),
.I2(addrb[13]),
.I3(addrb[12]),
.I4(addrb[14]),
.O(enb_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module v_ram_blk_mem_gen_top
(doutb,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [11:0]doutb;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [11:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [11:0]dina;
wire [11:0]doutb;
wire [0:0]wea;
v_ram_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "17" *) (* C_ADDRB_WIDTH = "17" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "26" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 16.2184 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "v_ram.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "76800" *) (* C_READ_DEPTH_B = "76800" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "1" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "76800" *) (* C_WRITE_DEPTH_B = "76800" *) (* C_WRITE_MODE_A = "NO_CHANGE" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_1" *) (* downgradeipidentifiedwarnings = "yes" *)
module v_ram_blk_mem_gen_v8_3_1
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [16:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [16:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [16:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [16:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [11:0]dina;
wire [11:0]dinb;
wire [11:0]doutb;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [11:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign douta[11] = \<const0> ;
assign douta[10] = \<const0> ;
assign douta[9] = \<const0> ;
assign douta[8] = \<const0> ;
assign douta[7] = \<const0> ;
assign douta[6] = \<const0> ;
assign douta[5] = \<const0> ;
assign douta[4] = \<const0> ;
assign douta[3] = \<const0> ;
assign douta[2] = \<const0> ;
assign douta[1] = \<const0> ;
assign douta[0] = \<const0> ;
assign rdaddrecc[16] = \<const0> ;
assign rdaddrecc[15] = \<const0> ;
assign rdaddrecc[14] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[16] = \<const0> ;
assign s_axi_rdaddrecc[15] = \<const0> ;
assign s_axi_rdaddrecc[14] = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
v_ram_blk_mem_gen_v8_3_1_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1_synth" *)
module v_ram_blk_mem_gen_v8_3_1_synth
(doutb,
clka,
clkb,
addra,
addrb,
dina,
wea);
output [11:0]doutb;
input clka;
input clkb;
input [16:0]addra;
input [16:0]addrb;
input [11:0]dina;
input [0:0]wea;
wire [16:0]addra;
wire [16:0]addrb;
wire clka;
wire clkb;
wire [11:0]dina;
wire [11:0]doutb;
wire [0:0]wea;
v_ram_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 04:58:12 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_auto_pc_0 -prefix
// design_1_auto_pc_0_ design_1_auto_pc_0_stub.v
// Design : design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
module design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
//`include "processor.h"
`default_nettype none
`include "common.h"
module l1_data_cache(
input wire iCLOCK,
input wire inRESET,
//Remove
input wire iREMOVE,
input wire iCACHE_FLASH,
//IOSR
input wire iSYSINFO_IOSR_VALID,
input wire [31:0] iSYSINFO_IOSR,
/****************************************
Load/Store Module
****************************************/
//Load Store -> Cache
input wire iLDST_REQ,
output wire oLDST_BUSY,
input wire [1:0] iLDST_ORDER,
input wire [3:0] iLDST_MASK,
input wire iLDST_RW,
input wire [31:0] iLDST_TID,
input wire [1:0] iLDST_MMUMOD,
input wire [31:0] iLDST_PDT,
input wire [31:0] iLDST_ADDR,
input wire [31:0] iLDST_DATA,
//Cache -> Load Store
output wire oLDST_VALID,
output wire oLDST_PAGEFAULT,
output wire [13:0] oLDST_MMU_FLAGS,
output wire [31:0] oLDST_DATA,
/****************************************
Data Memory
****************************************/
//Req
output wire oDATA_REQ,
input wire iDATA_LOCK,
output wire [1:0] oDATA_ORDER,
output wire [3:0] oDATA_MASK, //
output wire oDATA_RW, //0=Write 1=Read
output wire [13:0] oDATA_TID,
output wire [1:0] oDATA_MMUMOD,
output wire [31:0] oDATA_PDT,
output wire [31:0] oDATA_ADDR,
//This -> Data RAM
output wire [31:0] oDATA_DATA,
//Data RAM -> This
input wire iDATA_VALID,
input wire iDATA_PAGEFAULT,
input wire [27:0] iDATA_MMU_FLAGS,
input wire [63:0] iDATA_DATA,
/****************************************
IO
****************************************/
//Req
output wire oIO_REQ,
input wire iIO_BUSY,
output wire [1:0] oIO_ORDER,
output wire oIO_RW, //0=Write 1=Read
output wire [31:0] oIO_ADDR,
//Write
output wire [31:0] oIO_DATA,
//Rec
input wire iIO_VALID,
input wire [31:0] iIO_DATA
);
//IO Start Address Buffer
reg b_io_startaddr_valid;
reg [31:0] b_io_startaddr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_io_startaddr_valid <= 1'b0;
b_io_startaddr <= {32{1'b0}};
end
else begin
`ifdef MIST1032SA_IOSTART_ADDR_OPTION
b_io_startaddr_valid <= 1'b1;
b_io_startaddr <= `MIST1032SA_IOSTART_ADDR_OPTION;
`else
if(iSYSINFO_IOSR_VALID)begin
b_io_startaddr_valid <= 1'b1;
b_io_startaddr <= iSYSINFO_IOSR;
end
`endif
end
end
wire data_request_lock = iDATA_LOCK;
wire io_request_lock = iIO_BUSY;
wire data_request = iLDST_REQ && !(iLDST_ADDR >= b_io_startaddr);
wire io_request = iLDST_REQ && (iLDST_ADDR >= b_io_startaddr);
/****************************************
Instruction Access
****************************************/
localparam L_PARAM_IDLE = 3'h0;
localparam L_PARAM_MEMREQ = 3'h1;
localparam L_PARAM_MEMGET = 3'h2;
localparam L_PARAM_OUTDATA = 3'h3;
localparam L_PARAM_WR_MEMREQ = 3'h4;
localparam L_PARAM_WR_MEMGET = 3'h5;
localparam L_PARAM_WR_OUTDATA = 3'h6;
//Controlor
reg [2:0] b_req_main_state;
reg [3:0] b_req_state;
reg [3:0] b_get_state;
reg b_req_valid;
reg [1:0] b_req_order;
reg [3:0] b_req_mask;
reg b_req_rw;
reg [13:0] b_req_tid;
reg [1:0] b_req_mmumod;
reg [31:0] b_req_pdt;
reg [31:0] b_req_addr;
reg [31:0] b_req_data;
reg [31:0] b_mem_result_data;
reg [13:0] b_mem_result_mmu_flags;
//Cache
reg b_cache_req_valid;
reg [1:0] b_cache_req_order;
reg [3:0] b_cache_req_mask;
reg b_cache_req_rw;
reg [13:0] b_cache_req_tid;
reg [1:0] b_cache_req_mmumod;
reg [31:0] b_cache_req_pdt;
reg [31:0] b_cache_req_addr;
reg [31:0] b_cache_req_data;
reg [511:0] b_cache_result_data;
reg [255:0] b_cache_result_mmu_flags;
reg b_pagefault;
wire cache_req_busy;
wire cache_result_valid;
wire cache_result_hit;
wire [31:0] cache_result_data;
wire [13:0] cache_result_mmu_flags;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_main_state <= 3'b0;
b_req_state <= 4'h0;
b_get_state <= 4'h0;
b_req_valid <= 1'b0;
b_req_order <= 2'h0;
b_req_mask <= 4'h0;
b_req_rw <= 12'b0;
b_req_tid <= 14'h0;
b_req_mmumod <= 2'h0;
b_req_pdt <= 32'h0;
b_req_addr <= {32{1'b0}};
b_req_data <= 32'h0;
b_mem_result_data <= 32'h0;
b_mem_result_mmu_flags <= 14'h0;
//Cache
b_cache_req_valid <= 1'b0;
b_cache_req_order <= 2'h0;
b_cache_req_mask <= 4'h0;
b_cache_req_rw <= 1'b0;
b_cache_req_tid <= 14'h0;
b_cache_req_mmumod <= 2'h0;
b_cache_req_pdt <= 32'h0;
b_cache_req_addr <= 32'h0;
b_cache_req_data <= 32'h0;
b_cache_result_data <= 512'h0;
b_cache_result_mmu_flags <= 256'h0;
b_pagefault <= 1'b0;
end
else begin
//Memory State
case(b_req_main_state)
L_PARAM_IDLE: //Idle
begin
//Read
if(cache_result_valid && !cache_result_hit)begin
b_req_main_state <= L_PARAM_MEMREQ;
end
//Write
else if(b_cache_req_rw && /*b_req_valid*/b_cache_req_valid)begin
b_req_main_state <= L_PARAM_WR_MEMREQ;
end
if(!data_request_lock && data_request && !cache_req_busy)begin
b_cache_req_valid <= iLDST_REQ;
b_cache_req_order <= iLDST_ORDER;
b_cache_req_mask <= iLDST_MASK;
b_cache_req_rw <= iLDST_RW;
b_cache_req_tid <= iLDST_TID;
b_cache_req_mmumod <= iLDST_MMUMOD;
b_cache_req_pdt <= iLDST_PDT;
b_cache_req_addr <= iLDST_ADDR;
b_cache_req_data <= iLDST_DATA;
end
b_req_valid <= b_cache_req_valid;
b_req_order <= b_cache_req_order;
b_req_mask <= b_cache_req_mask;
b_req_rw <= b_cache_req_rw;
b_req_tid <= b_cache_req_tid;
b_req_mmumod <= b_cache_req_mmumod;
b_req_pdt <= b_cache_req_pdt;
b_req_addr <= b_cache_req_addr;
b_req_data <= b_cache_req_data;
b_pagefault <= 1'b0;
end
L_PARAM_MEMREQ: //Request State
begin
//Cache ON
`ifdef MIST1032SA_DATA_L1_CACHE
if(iDATA_VALID && iDATA_PAGEFAULT)begin
//Pagefault
b_req_state <= 4'h0;
b_req_main_state <= L_PARAM_OUTDATA;
b_pagefault <= 1'b1;
end
//IO Address Check --iranai?
else if(b_io_startaddr-32'h4 <= {b_req_addr[31:6], b_req_state[2:0], 3'h0})begin
b_req_main_state <= L_PARAM_MEMGET;
b_req_state <= 4'h0;
end
//Next State Check
else if(b_req_state == 4'h7 && !data_request_lock)begin
b_req_main_state <= L_PARAM_MEMGET;
b_req_state <= 4'h0;
end
//Request
else if(!data_request_lock) begin
b_req_state <= b_req_state + 4'h1;
end
//Get Check
if(iDATA_VALID)begin
b_get_state <= b_get_state + 4'h1;
b_cache_result_data <= {iDATA_DATA, b_cache_result_data[511:64]};
b_cache_result_mmu_flags <= {2'h0, iDATA_MMU_FLAGS[27:14], 2'h0, iDATA_MMU_FLAGS[13:0], b_cache_result_mmu_flags[255:31]};
if(b_req_addr[5:3] == b_get_state[3:0])begin
if(!b_req_addr[2])begin
b_mem_result_data <= iDATA_DATA[31:0];
b_mem_result_mmu_flags <= iDATA_MMU_FLAGS[13:0];
end
else begin
b_mem_result_data <= iDATA_DATA[63:32];
b_mem_result_mmu_flags <= iDATA_MMU_FLAGS[27:14];
end
end
end
//Cache OFF
`else
if(!data_request_lock)begin
b_req_main_state <= L_PARAM_MEMGET;
b_req_state <= 4'h0;
end
`endif
end
L_PARAM_MEMGET: //Get Wait State
begin
//Cache ON
`ifdef MIST1032SA_DATA_L1_CACHE
if(iDATA_VALID)begin
//Latch Data
b_cache_result_data <= {iDATA_DATA, b_cache_result_data[511:64]};
b_cache_result_mmu_flags <= {2'h0, iDATA_MMU_FLAGS[27:14], 2'h0, iDATA_MMU_FLAGS[13:0], b_cache_result_mmu_flags[255:31]};
if(b_req_addr[5:3] == b_get_state[3:0])begin
if(!b_req_addr[2])begin
b_mem_result_data <= iDATA_DATA[31:0];
b_mem_result_mmu_flags <= iDATA_MMU_FLAGS[13:0];
end
else begin
b_mem_result_data <= iDATA_DATA[63:32];
b_mem_result_mmu_flags <= iDATA_MMU_FLAGS[27:14];
end
end
//State Check
if(iDATA_VALID && iDATA_PAGEFAULT)begin
//Pagefault
b_get_state <= 4'h0;
b_req_main_state <= L_PARAM_OUTDATA;
b_pagefault <= 1'b1;
end
if(b_get_state == 4'h7)begin
b_get_state <= 4'h0;
b_req_main_state <= L_PARAM_OUTDATA;
end
//IO Address Check --iranai?
else if(b_io_startaddr-32'h4 <= {b_req_addr[31:6], b_get_state[2:0], 3'h0})begin
b_get_state <= 4'h0;
b_req_main_state <= L_PARAM_OUTDATA;
end
else begin
b_get_state <= b_get_state + 4'h1;
end
end
`else
//Cache OFF
if(iDATA_VALID)begin
b_get_state <= 4'h0;
b_pagefault <= iDATA_PAGEFAULT;
b_req_main_state <= L_PARAM_OUTDATA;
if(!b_req_addr[2])begin
b_mem_result_data <= iDATA_DATA[31:0];
b_mem_result_mmu_flags <= iDATA_MMU_FLAGS[13:0];
end
else begin
b_mem_result_data <= iDATA_DATA[63:32];
b_mem_result_mmu_flags <= iDATA_MMU_FLAGS[27:14];
end
end
`endif
end
L_PARAM_OUTDATA:
begin
b_req_main_state <= L_PARAM_IDLE;
b_req_valid <= 1'b0;
b_cache_req_valid <= 1'b0;
end
//Write
L_PARAM_WR_MEMREQ:
begin
if(!data_request_lock)begin
b_req_main_state <= L_PARAM_WR_MEMGET;
end
end
L_PARAM_WR_MEMGET:
begin
if(iDATA_VALID)begin
b_req_main_state <= L_PARAM_WR_OUTDATA;
end
end
L_PARAM_WR_OUTDATA:
begin
b_req_main_state <= L_PARAM_IDLE;
b_req_valid <= 1'b0;
b_cache_req_valid <= 1'b0;
end
endcase
end
end
/*
//Cache Hit Counter
wire [6:0] cache_hit_counter;
l1_data_cache_counter L1_CACHE_HIT_COUNTER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Hit Infomation
.iCACHE_VALID(cache_result_valid),
.iCACHE_HIT(cache_result_hit),
//Infomation
.oINFO_COUNT(cache_hit_counter)
);
*/
`ifdef MIST1032SA_DATA_L1_CACHE
l1_data_cache_64entry_4way_line64b_bus_8b CACHE_MODULE(
/********************************
System
********************************/
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Remove
.iREMOVE(iCACHE_FLASH),
/********************************
Search
********************************/
//Search Request
.iRD_REQ((b_req_main_state == L_PARAM_IDLE) && !data_request_lock && data_request && !iLDST_RW),
.oRD_BUSY(cache_req_busy),
.iRD_ADDR({iLDST_ADDR[31:2], 2'h0}), //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
//Search Output Result
.oRD_VALID(cache_result_valid),
.oRD_HIT(cache_result_hit),
.iRD_BUSY(b_req_main_state != L_PARAM_IDLE),
.oRD_DATA(cache_result_data),
.oRD_MMU_FLAGS(cache_result_mmu_flags),
/********************************
Upload
********************************/
.iUP_REQ((b_req_main_state == L_PARAM_WR_MEMREQ) && !data_request_lock),
.oUP_BUSY(),
.iUP_ORDER(b_req_order),
.iUP_MASK(b_req_mask),
.iUP_ADDR(b_req_addr),
.iUP_DATA(b_req_data),
/********************************
Write Request
********************************/
.iWR_REQ((b_req_main_state == L_PARAM_OUTDATA) && !b_pagefault),
.oWR_BUSY(),
.iWR_ADDR({b_req_addr[31:6], 6'h0}), //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
.iWR_DATA(b_cache_result_data),
.iWR_MMU_FLAGS(b_cache_result_mmu_flags)
);
`else
l1_data_cache_64entry_4way_line64b_bus_8b_damy CACHE_MODULE_DAMY(
/********************************
System
********************************/
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Remove
.iREMOVE(iCACHE_FLASH),
/********************************
Search
********************************/
//Search Request
.iRD_REQ((b_req_main_state == L_PARAM_IDLE) && !data_request_lock && data_request && !iLDST_RW),
.oRD_BUSY(cache_req_busy),
.iRD_ADDR({iLDST_ADDR[31:3], 3'h0}), //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
//Search Output Result
.oRD_VALID(cache_result_valid),
.oRD_HIT(cache_result_hit),
.iRD_BUSY(b_req_main_state != L_PARAM_IDLE),
.oRD_DATA(cache_result_data),
.oRD_MMU_FLAGS(cache_result_mmu_flags),
/********************************
Upload
********************************/
.iUP_REQ((b_req_main_state == L_PARAM_WR_MEMREQ) && !data_request_lock),
.oUP_BUSY(),
.iUP_ORDER(b_req_order),
.iUP_MASK(b_req_mask),
.iUP_ADDR(b_req_addr),
.iUP_DATA(b_req_data),
/********************************
Write Request
********************************/
.iWR_REQ(1'b0),
.oWR_BUSY(),
.iWR_ADDR(32'h0), //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
.iWR_DATA({512{1'b0}}),
.iWR_MMU_FLAGS(256'h000000)
);
`endif
reg next_data_valid;
reg [31:0] next_data_data;
reg [13:0] next_data_mmu_flags;
always @* begin
if(b_req_main_state == L_PARAM_OUTDATA || b_req_main_state == L_PARAM_WR_OUTDATA)begin
next_data_valid = 1'b1;
next_data_data = b_mem_result_data;
next_data_mmu_flags = b_mem_result_mmu_flags;
end
else begin
next_data_valid = cache_result_valid && cache_result_hit;
next_data_data = cache_result_data;
next_data_mmu_flags = cache_result_mmu_flags;
end
end
/*************************
Outpu Assign
*************************/
//Memory
assign oDATA_REQ = (b_req_main_state == L_PARAM_MEMREQ) || (b_req_main_state == L_PARAM_WR_MEMREQ);
assign oDATA_ORDER = b_req_order;
assign oDATA_MASK = b_req_mask;
assign oDATA_RW = (b_req_main_state == L_PARAM_MEMREQ)? b_req_rw : 1'b1;
assign oDATA_TID = b_req_tid;
assign oDATA_MMUMOD = b_req_mmumod;
assign oDATA_PDT = b_req_pdt;
`ifdef MIST1032SA_DATA_L1_CACHE
//Cache ON
assign oDATA_ADDR = (b_req_main_state == L_PARAM_WR_MEMREQ)? b_req_addr : {b_req_addr[31:6], b_req_state[2:0], 3'h0};
`else
//Cache OFF
assign oDATA_ADDR = (b_req_main_state == L_PARAM_WR_MEMREQ)? b_req_addr : {b_req_addr[31:3], 1'b0, b_req_addr[1:0]};
`endif
assign oDATA_DATA = b_req_data;
assign oLDST_BUSY = !b_io_startaddr_valid || data_request_lock || io_request_lock || cache_req_busy || (b_req_main_state != L_PARAM_IDLE) || (cache_result_valid && !cache_result_hit);
//IO
assign oIO_REQ = io_request;
assign oIO_ORDER = 2'h2;
assign oIO_RW = iLDST_RW; //0=Write 1=Read
assign oIO_ADDR = iLDST_ADDR - b_io_startaddr;
//Write
assign oIO_DATA = iLDST_DATA;
//This -> Load Store Module
assign oLDST_VALID = next_data_valid || iIO_VALID;
assign oLDST_PAGEFAULT = b_pagefault;
assign oLDST_MMU_FLAGS = next_data_mmu_flags;
assign oLDST_DATA = (iIO_VALID)? iIO_DATA : next_data_data;
endmodule
`default_nettype wire
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: spu.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: Stream Processing Unit for Sparc Core
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
module spu (///*AUTOARG*/
short_si0,short_so0,short_si1,short_so1,si1,so1,
/*outputs*/
spu_ifu_err_addr_w2,
spu_ifu_mamem_err_w1,
spu_ifu_int_w2,
spu_lsu_ldxa_illgl_va_w2,
spu_ifu_ttype_w2,
spu_ifu_ttype_vld_w2,
spu_ifu_ttype_tid_w2,
spu_lsu_ldst_pckt,
spu_mul_req_vld,
spu_mul_areg_shf,
spu_mul_areg_rst,
spu_mul_acc,
spu_mul_op1_data,
spu_mul_op2_data,
spu_lsu_ldxa_data_w2,
spu_lsu_ldxa_data_vld_w2,
spu_lsu_ldxa_tid_w2,
spu_lsu_stxa_ack,
spu_lsu_stxa_ack_tid,
spu_mul_mulres_lshft,
spu_tlu_rsrv_illgl_m,
spu_ifu_corr_err_w2,
spu_ifu_unc_err_w1,
spu_lsu_unc_error_w2,
/*inputs*/
const_cpuid,
cpx_spu_data_cx,
lsu_spu_ldst_ack,
mul_spu_ack,
mul_spu_shf_ack,
mul_data_out,
lsu_spu_asi_state_e,
ifu_spu_inst_vld_w,
ifu_lsu_ld_inst_e,
ifu_lsu_st_inst_e,
ifu_lsu_alt_space_e,
ifu_tlu_thrid_e,
exu_lsu_ldst_va_e,
exu_lsu_rs3_data_e,
ifu_spu_trap_ack,
lsu_spu_stb_empty,
lsu_spu_strm_ack_cmplt,
lsu_spu_early_flush_g,
tlu_spu_flush_w,
ifu_spu_flush_w,
exu_spu_rsrv_data_e,
ifu_spu_nceen,
lsu_mamem_mrgn,
mem_write_disable,
mux_drive_disable,
mem_bypass,
se,
sehold,
grst_l,
arst_l,
rclk) ;
// ------------------------------------------------------------------
///*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input si1,short_si0,short_si1,se;
input rclk ;
input grst_l ;
input arst_l ;
input mem_write_disable ;
input mux_drive_disable ;
input sehold ;
input tlu_spu_flush_w;
input ifu_spu_flush_w;
input [2:0] const_cpuid;
input [134:0] cpx_spu_data_cx;
input lsu_spu_ldst_ack;
input mul_spu_ack;
input mul_spu_shf_ack;
input [63:0] mul_data_out;
input [7:0] lsu_spu_asi_state_e;
input ifu_spu_inst_vld_w;
input ifu_lsu_ld_inst_e;
input ifu_lsu_st_inst_e;
input ifu_lsu_alt_space_e;
input [1:0] ifu_tlu_thrid_e;
input [7:0] exu_lsu_ldst_va_e;
input [63:0] exu_lsu_rs3_data_e;
input ifu_spu_trap_ack;
input [3:0] lsu_spu_stb_empty;
input [1:0] lsu_spu_strm_ack_cmplt;
input lsu_spu_early_flush_g;
input [2:0] exu_spu_rsrv_data_e;
input [3:0] ifu_spu_nceen;
input [3:0] lsu_mamem_mrgn;
input mem_bypass;
// End of automatics
// ------------------------------------------------------------------
///*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output so1,short_so1,short_so0;
output spu_ifu_ttype_w2;
output spu_ifu_ttype_vld_w2;
output [1:0] spu_ifu_ttype_tid_w2;
// ------------------------------
output [123:0] spu_lsu_ldst_pckt;
output spu_mul_req_vld;
output spu_mul_areg_shf;
output spu_mul_areg_rst;
output spu_mul_acc;
output [63:0] spu_mul_op1_data;
output [63:0] spu_mul_op2_data;
output [63:0] spu_lsu_ldxa_data_w2;
output spu_lsu_ldxa_data_vld_w2;
output [1:0] spu_lsu_ldxa_tid_w2;
output spu_lsu_stxa_ack;
output [1:0] spu_lsu_stxa_ack_tid;
output spu_mul_mulres_lshft;
output spu_tlu_rsrv_illgl_m;
output spu_ifu_corr_err_w2;
output spu_ifu_unc_err_w1;
output spu_lsu_unc_error_w2;
output [39:4] spu_ifu_err_addr_w2;
output spu_ifu_mamem_err_w1;
output spu_ifu_int_w2;
output spu_lsu_ldxa_illgl_va_w2;
// End of automatics
// ------------------------------------------------------------------
// ------------------------------------------------------------------
// ------------------------------------------------------------------
wire [123:0] spu_lsu_ldst_pckt;
wire [65:0] spu_madp_evedata;
wire [65:0] spu_madp_odddata;
wire [7:1] spu_maaddr_memindx;
wire [3:0] spu_maaddr_mamem_eveodd_sel_l;
wire [2:0] spu_mactl_memmxsel_l;
wire [38:3] spu_madp_mpa_addr_out;
wire [63:0] spu_mul_op1_data;
wire [63:0] spu_mul_op2_data;
wire [3:0] spu_mared_data_sel_l;
wire [63:0] spu_madp_store_data;
// ------------------------------------
wire [4:0] spu_maaddr_mpa_incr_val;
// --------------------------------------------------------------
wire spu_madp_perr;
wire [2:0] spu_mamul_oprnd1_mxsel_l; // From spu_ctl of spu_ctl.v
wire [1:0] spu_ctl_ldxa_tid_w2;
wire [3:0] spu_lsurpt1_stb_empty;
wire spu_ctl_ldxa_data_vld_w2,
spu_mactl_madp_parflop_wen,
spu_mactl_force_perr,
spu_mactl_memeve_wen,
spu_mactl_memodd_wen,
spu_mactl_mamem_ren,
spu_mactl_mamem_wen,
spu_mamul_oprnd1_wen,
spu_mactl_mem_reset_l,
spu_madp_m_eq_n,
spu_madp_m_lt_n,
spu_madp_cout_oprnd_sub_mod,
spu_madp_e_eq_one,
spu_mamul_oprnd2_wen,
spu_mamul_oprnd2_bypass,
spu_mared_rdn_wen,
spu_mared_cin_oprnd_sub_mod,
spu_maexp_e_data_wen,
spu_maexp_shift_e,
spu_maaddr_mpa_addrinc,
spu_maaddr_mpa_wen,
spu_mactl_mpa_sel,
spu_mactl_ldop,
spu_ctl_ldxa_illgl_va_w;
wire [63:0] spu_lsurpt1_rs3_data_g2;
wire [134:0] spu_lsurpt1_cpx_data;
wire [134:0] spu_lsurpt2_cpx_data;
wire [122:0] spu_lsurpt1_ldst_pckt;
wire [63:0] spu_lsurpt1_ldxa_data;
wire spu_wen_pcx_wen, spu_wen_pcx_7170_sel;
wire [1:0] spu_ifu_ttype_tid_w;
wire spu_lsu_unc_error_w;
wire [65:0] spu_mamem_rd_eve_data;
wire [65:0] spu_mamem_rd_odd_data;
wire [122:104] spu_wen_pckt_req;
wire [63:0] spu_madp_ldxa_data;
wire [1:0] spu_lsu_stxa_ack_tid_ctl;
wire [3:0] spu_mactl_ldxa_data_w_sel_l;
wire spu_mactl_ldxa_data_w_select;
wire spu_mactl_mpa_wen;
wire spu_mactl_maaddr_wen;
wire spu_mactl_manp_wen;
wire spu_wen_maln_wen;
wire [13:0] spu_mactl_mactl_reg;
wire [47:0] spu_madp_maaddr_reg;
wire scan1_1;
// End of automatics
/****************************************************************************/
spu_lsurpt spu_lsurpt2 (///*AUTOINST*/
// Outputs
.spu_lsurpt_ldxa_data_out (spu_lsu_ldxa_data_w2[63:0]),
.spu_lsurpt_ldst_pckt_out (spu_lsu_ldst_pckt[122:0]),
.spu_lsurpt_cpx_data_out (spu_lsurpt2_cpx_data[134:0]),
// Inputs
.spu_lsurpt_ldxa_data_in (spu_lsurpt1_ldxa_data[63:0]),
.spu_lsurpt_ldst_pckt_in (spu_lsurpt1_ldst_pckt[122:0]),
.spu_lsurpt_cpx_data_in (cpx_spu_data_cx[134:0]));
/****************************************************************************/
spu_lsurpt1 spu_lsurpt1 (///*AUTOINST*/
// Outputs
.so (scan1_1),
.spu_lsu_ldst_pckt (spu_lsurpt1_ldst_pckt[122:0]),
.spu_lsu_ldxa_data_w2 (spu_lsurpt1_ldxa_data[63:0]),
.spu_lsu_ldxa_data_vld_w2 (spu_lsu_ldxa_data_vld_w2),
.spu_lsu_ldxa_tid_w2 (spu_lsu_ldxa_tid_w2[1:0]),
.spu_lsu_ldxa_illgl_va_w2 (spu_lsu_ldxa_illgl_va_w2),
.spu_lsurpt1_rs3_data_g2 (spu_lsurpt1_rs3_data_g2[63:0]),
.spu_lsurpt1_stb_empty (spu_lsurpt1_stb_empty[3:0]),
.spu_lsurpt_cpx_data_out (spu_lsurpt1_cpx_data[134:0]),
.spu_ifu_ttype_tid_w2 (spu_ifu_ttype_tid_w2[1:0]),
.spu_ifu_err_addr_w2 (spu_ifu_err_addr_w2[39:4]),
.spu_lsu_unc_error_w2 (spu_lsu_unc_error_w2),
.spu_lsu_stxa_ack_tid (spu_lsu_stxa_ack_tid[1:0]),
// Inputs
.spu_ifu_ttype_tid_w (spu_ifu_ttype_tid_w[1:0]),
.spu_lsu_unc_error_w (spu_lsu_unc_error_w),
.exu_lsu_rs3_data_e (exu_lsu_rs3_data_e[63:0]),
.spu_ctl_ldxa_illgl_va_w (spu_ctl_ldxa_illgl_va_w),
.spu_ldstreq_pcx ({spu_wen_pckt_req[122:104],1'b0,spu_madp_mpa_addr_out[38:3],
3'b000,spu_madp_store_data[63:0]}),
.spu_madp_ldxa_data (spu_madp_ldxa_data[63:0]),
.spu_ctl_ldxa_data_vld_w2 (spu_ctl_ldxa_data_vld_w2),
.spu_ctl_ldxa_tid_w2 (spu_ctl_ldxa_tid_w2[1:0]),
.lsu_spu_stb_empty (lsu_spu_stb_empty[3:0]),
.spu_lsurpt_cpx_data_in (spu_lsurpt2_cpx_data[134:0]),
.spu_wen_pcx_wen (spu_wen_pcx_wen),
.spu_wen_pcx_7170_sel (spu_wen_pcx_7170_sel),
.spu_lsu_stxa_ack_tid_ctl (spu_lsu_stxa_ack_tid_ctl[1:0]),
//.tmb_l (testmode_l),
.se (se),
.si (si1),
.reset_l (spu_mactl_mem_reset_l),
.rclk (rclk));
/****************************************************************************/
// -------------------------------------------------------------------------
// ------------------------ MA STUFF ---------------------------------------
bw_r_idct spu_mamem (
.rdtag_w3_y ({spu_mamem_rd_eve_data[65],spu_mamem_rd_eve_data[63:32]}),
.rdtag_w2_y ({spu_mamem_rd_eve_data[64],spu_mamem_rd_eve_data[31:0]}),
.rdtag_w1_y ({spu_mamem_rd_odd_data[65],spu_mamem_rd_odd_data[63:32]}),
.rdtag_w0_y ({spu_mamem_rd_odd_data[64],spu_mamem_rd_odd_data[31:0]}),
.wrtag_w3_y ({spu_madp_evedata[65],spu_madp_evedata[63:32]}),
.wrtag_w2_y ({spu_madp_evedata[64],spu_madp_evedata[31:0]}),
.wrtag_w1_y ({spu_madp_odddata[65],spu_madp_odddata[63:32]}),
.wrtag_w0_y ({spu_madp_odddata[64],spu_madp_odddata[31:0]}),
/*AUTOINST*/
// Outputs
.so (short_so0),
// Inputs
.rst_tri_en (mem_write_disable),
.rclk (rclk),
.se (se),
.si (short_si0),
.reset_l (arst_l),
.sehold (sehold),
.index0_x (spu_maaddr_memindx[7:1]),
.index1_x (7'b0000000),
.index_sel_x (1'b0),
.dec_wrway_x ({spu_mactl_memeve_wen,spu_mactl_memeve_wen,
spu_mactl_memodd_wen,spu_mactl_memodd_wen}),
.rdreq_x (spu_mactl_mamem_ren),
.wrreq_x (spu_mactl_mamem_wen),
.adj (lsu_mamem_mrgn[3:0]));
// -------------------------------------------------------------------------
spu_madp spu_madp (///*AUTOINST*/
// Outputs
.spu_madp_evedata (spu_madp_evedata[65:0]),
.spu_madp_odddata (spu_madp_odddata[65:0]),
.spu_mul_op2_data (spu_mul_op2_data[63:0]),
.spu_madp_m_eq_n (spu_madp_m_eq_n),
.spu_madp_m_lt_n (spu_madp_m_lt_n),
.spu_madp_store_data (spu_madp_store_data[63:0]),
.spu_madp_cout_oprnd_sub_mod (spu_madp_cout_oprnd_sub_mod),
.spu_madp_e_eq_one (spu_madp_e_eq_one),
.spu_madp_mpa_addr_out (spu_madp_mpa_addr_out[38:3]),
.spu_madp_perr (spu_madp_perr),
.spu_mul_op1_data (spu_mul_op1_data[63:0]),
.spu_madp_ldxa_data (spu_madp_ldxa_data[63:0]),
.spu_madp_maaddr_reg (spu_madp_maaddr_reg[47:0]),
.so (short_so1),
// Inputs
.spu_mamul_oprnd1_mxsel_l (spu_mamul_oprnd1_mxsel_l[2:0]),
.spu_mamul_oprnd1_wen (spu_mamul_oprnd1_wen),
.spu_maaddr_mamem_eveodd_sel_l (spu_maaddr_mamem_eveodd_sel_l[3:0]),
.spu_mamem_rd_eve_data (spu_mamem_rd_eve_data[65:0]),
.spu_mamem_rd_odd_data (spu_mamem_rd_odd_data[65:0]),
.mul_data_out (mul_data_out[63:0]),
.spu_mamul_oprnd2_wen (spu_mamul_oprnd2_wen),
.spu_mamul_oprnd2_bypass (spu_mamul_oprnd2_bypass),
.spu_mared_data_sel_l (spu_mared_data_sel_l[3:0]),
.spu_mared_rdn_wen (spu_mared_rdn_wen),
.spu_mared_cin_oprnd_sub_mod (spu_mared_cin_oprnd_sub_mod),
.spu_maexp_e_data_wen (spu_maexp_e_data_wen),
.spu_maexp_shift_e (spu_maexp_shift_e),
.spu_maaddr_mpa_addrinc (spu_maaddr_mpa_addrinc),
.spu_maaddr_mpa_incr_val (spu_maaddr_mpa_incr_val[4:0]),
.spu_mactl_mpa_sel (spu_mactl_mpa_sel),
.spu_mactl_ldop (spu_mactl_ldop),
.spu_mactl_madp_parflop_wen (spu_mactl_madp_parflop_wen),
.spu_mactl_memmxsel_l (spu_mactl_memmxsel_l[2:0]),
.spu_mactl_force_perr (spu_mactl_force_perr),
.spu_maaddr_mpa_wen (spu_maaddr_mpa_wen),
.spu_mactl_mactl_reg (spu_mactl_mactl_reg[13:0]),
.spu_mactl_ldxa_data_w_sel_l (spu_mactl_ldxa_data_w_sel_l[3:0]),
.spu_mactl_ldxa_data_w_select (spu_mactl_ldxa_data_w_select),
.spu_mactl_mpa_wen (spu_mactl_mpa_wen),
.spu_mactl_maaddr_wen (spu_mactl_maaddr_wen),
.spu_mactl_manp_wen (spu_mactl_manp_wen),
.exu_spu_st_rs3_data_g2 (spu_lsurpt1_rs3_data_g2[63:0]),
.spu_wen_maln_wen (spu_wen_maln_wen),
.lsu_spu_vload_data (spu_lsurpt1_cpx_data[127:0]),
.se (se),
.si (short_si1),
.sehold (sehold),
.rclk (rclk));
//---------------------------------------------------
//--------------SPU CONTROL BLOCK--------------------
spu_ctl spu_ctl (
/*AUTOINST*/
// Outputs
.spu_wen_ldst_pcx_vld (spu_lsu_ldst_pckt[123]),
.spu_mul_mulres_lshft (spu_mul_mulres_lshft),
.spu_maaddr_mpa_wen (spu_maaddr_mpa_wen),
.spu_mamul_oprnd2_bypass (spu_mamul_oprnd2_bypass),
.spu_mactl_ldop (spu_mactl_ldop),
.so (so1),
.spu_ifu_ttype_tid_w (spu_ifu_ttype_tid_w[1:0]),
.spu_ifu_ttype_vld_w2 (spu_ifu_ttype_vld_w2),
.spu_ifu_ttype_w2 (spu_ifu_ttype_w2),
.spu_lsu_ldxa_data_vld_w2 (spu_ctl_ldxa_data_vld_w2),
.spu_lsu_ldxa_tid_w2 (spu_ctl_ldxa_tid_w2[1:0]),
.spu_lsu_stxa_ack (spu_lsu_stxa_ack),
.spu_lsu_stxa_ack_tid (spu_lsu_stxa_ack_tid_ctl[1:0]),
.spu_maaddr_memindx (spu_maaddr_memindx[7:1]),
.spu_maaddr_mamem_eveodd_sel_l (spu_maaddr_mamem_eveodd_sel_l[3:0]),
.spu_maaddr_mpa_addrinc (spu_maaddr_mpa_addrinc),
.spu_maaddr_mpa_incr_val (spu_maaddr_mpa_incr_val[4:0]),
.spu_mactl_force_perr (spu_mactl_force_perr),
.spu_mactl_madp_parflop_wen (spu_mactl_madp_parflop_wen),
.spu_mactl_mamem_ren (spu_mactl_mamem_ren),
.spu_mactl_mamem_wen (spu_mactl_mamem_wen),
.spu_mactl_memeve_wen (spu_mactl_memeve_wen),
.spu_mactl_memmxsel_l (spu_mactl_memmxsel_l[2:0]),
.spu_mactl_memodd_wen (spu_mactl_memodd_wen),
.spu_mactl_mpa_sel (spu_mactl_mpa_sel),
.spu_maexp_e_data_wen (spu_maexp_e_data_wen),
.spu_maexp_shift_e (spu_maexp_shift_e),
.spu_mamul_oprnd1_mxsel_l (spu_mamul_oprnd1_mxsel_l[2:0]),
.spu_mamul_oprnd1_wen (spu_mamul_oprnd1_wen),
.spu_mamul_oprnd2_wen (spu_mamul_oprnd2_wen),
.spu_mared_cin_oprnd_sub_mod (spu_mared_cin_oprnd_sub_mod),
.spu_mared_data_sel_l (spu_mared_data_sel_l[3:0]),
.spu_mared_rdn_wen (spu_mared_rdn_wen),
.spu_mul_acc (spu_mul_acc),
.spu_mul_areg_rst (spu_mul_areg_rst),
.spu_mul_areg_shf (spu_mul_areg_shf),
.spu_mul_req_vld (spu_mul_req_vld),
.spu_tlu_rsrv_illgl_m (spu_tlu_rsrv_illgl_m),
.spu_ifu_corr_err_w2 (spu_ifu_corr_err_w2),
.spu_ifu_unc_err_w (spu_ifu_unc_err_w1),
.spu_lsu_unc_error_w (spu_lsu_unc_error_w),
.spu_ifu_mamem_err_w (spu_ifu_mamem_err_w1),
.spu_ifu_int_w2 (spu_ifu_int_w2),
.spu_lsu_ldxa_illgl_va_w2 (spu_ctl_ldxa_illgl_va_w),
.spu_mactl_mem_reset_l (spu_mactl_mem_reset_l),
.spu_mactl_ldxa_data_w_sel_l (spu_mactl_ldxa_data_w_sel_l[3:0]),
.spu_mactl_ldxa_data_w_select (spu_mactl_ldxa_data_w_select),
.spu_mactl_mpa_wen (spu_mactl_mpa_wen),
.spu_mactl_maaddr_wen (spu_mactl_maaddr_wen),
.spu_mactl_manp_wen (spu_mactl_manp_wen),
.spu_wen_maln_wen (spu_wen_maln_wen),
.spu_mactl_mactl_reg (spu_mactl_mactl_reg[13:0]),
// Inputs
.spu_madp_maaddr_reg (spu_madp_maaddr_reg[47:0]),
.sehold (sehold),
.mem_bypass (mem_bypass),
.mux_drive_disable (mux_drive_disable),
.tlu_spu_flush_w (tlu_spu_flush_w),
.ifu_spu_flush_w (ifu_spu_flush_w),
.lsu_spu_stb_empty (spu_lsurpt1_stb_empty[3:0]),
.lsu_spu_strm_ack_cmplt (lsu_spu_strm_ack_cmplt[1:0]),
.cpx_spu_data_cx (spu_lsurpt1_cpx_data[134:128]),
.spu_wen_pckt_req (spu_wen_pckt_req[122:104]),
.lsu_spu_ldst_ack (lsu_spu_ldst_ack),
.ifu_spu_trap_ack (ifu_spu_trap_ack),
.lsu_tlu_st_rs3_data_g (spu_lsurpt1_rs3_data_g2[13:0]),
.spu_lsurpt1_rsrv_data_e (exu_spu_rsrv_data_e[2:0]),
.spu_madp_mpa_addr (spu_madp_mpa_addr_out[3:3]),
.mul_data_out (mul_data_out[0:0]),
.rclk (rclk),
.exu_lsu_ldst_va_e (exu_lsu_ldst_va_e[7:0]),
.ifu_lsu_alt_space_e (ifu_lsu_alt_space_e),
.ifu_lsu_ld_inst_e (ifu_lsu_ld_inst_e),
.ifu_lsu_st_inst_e (ifu_lsu_st_inst_e),
.ifu_spu_inst_vld_w (ifu_spu_inst_vld_w),
.ifu_tlu_thrid_e (ifu_tlu_thrid_e[1:0]),
.lsu_spu_asi_state_e (lsu_spu_asi_state_e[7:0]),
.mul_spu_ack (mul_spu_ack),
.mul_spu_shf_ack (mul_spu_shf_ack),
.grst_l (grst_l),
.arst_l (arst_l),
.se (se),
.si (scan1_1),
.spu_wen_pcx_wen (spu_wen_pcx_wen),
.spu_wen_pcx_7170_sel (spu_wen_pcx_7170_sel),
.cpuid (const_cpuid[2:0]),
.ifu_spu_nceen (ifu_spu_nceen[3:0]),
.spu_madp_cout_oprnd_sub_mod (spu_madp_cout_oprnd_sub_mod),
.spu_madp_e_eq_one (spu_madp_e_eq_one),
.spu_madp_m_eq_n (spu_madp_m_eq_n),
.spu_madp_m_lt_n (spu_madp_m_lt_n),
.spu_madp_perr (spu_madp_perr),
.lsu_spu_early_flush_g (lsu_spu_early_flush_g));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A21OI_BEHAVIORAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Tue Nov 8 02:13:32 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire intAS, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537,
n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, n548,
n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559,
n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, n570,
n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n618, n619, n620, n621, n622, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n729, n730, n731, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n775,
n776, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n805, n806, n807, n808, n809, n810,
n811, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1070, n1071, n1072, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2840, n2841, n2842, n2843, n2844, n2845, n2846,
n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856,
n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866,
n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876;
wire [31:0] intDX;
wire [31:0] intDY;
wire [30:0] DMP;
wire [30:1] DmP;
wire [3:0] exp_oper_result;
wire [4:1] LZA_output;
wire [23:0] Add_Subt_result;
wire [25:4] Sgf_normalized_result;
wire [8:5] Exp_Operation_Module_Data_S;
wire [25:16] Add_Subt_Sgf_module_S_to_D;
wire [47:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n738), .CK(clk),
.RN(n2868), .Q(Add_Subt_result[4]), .QN(n2767) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n737), .CK(clk),
.RN(n828), .Q(Add_Subt_result[3]), .QN(n2797) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n2863),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[40]), .QN(n2766) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n2856),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[37]), .QN(n2760) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n2852),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[36]), .QN(n2761) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n2852),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[35]), .QN(n2762) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n2855),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[30]), .QN(n2768) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n2856),
.QN(n1397) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n2852),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[28]), .QN(n1449) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n2863),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n2853),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[44]), .QN(n2729) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n2852),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[43]), .QN(n2723) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n2855),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[46]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n2851),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[45]), .QN(n2722) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n721), .CK(clk),
.RN(n2862), .Q(Sgf_normalized_result[18]), .QN(n2743) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n585), .CK(clk), .RN(
n1427), .Q(DMP[24]), .QN(n2740) );
DFFRX2TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n574), .CK(clk), .RN(
n2863), .Q(DMP[13]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n560), .CK(clk), .RN(
n829), .Q(DMP[30]), .QN(n2736) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n551), .CK(clk), .RN(
n2855), .Q(DmP[22]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n550), .CK(clk), .RN(
n825), .Q(DmP[21]), .QN(n1453) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n545), .CK(clk), .RN(
n2855), .Q(DmP[16]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n544), .CK(clk), .RN(
n2855), .Q(DmP[15]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n539), .CK(clk), .RN(
n2856), .Q(DmP[10]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n535), .CK(clk), .RN(
n2855), .Q(DmP[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n680),
.CK(clk), .RN(n1427), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n679),
.CK(clk), .RN(n2849), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n678),
.CK(clk), .RN(n2849), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n677),
.CK(clk), .RN(n2849), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n676),
.CK(clk), .RN(n2849), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n675),
.CK(clk), .RN(n2849), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n674),
.CK(clk), .RN(n2849), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n673),
.CK(clk), .RN(n2849), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n672),
.CK(clk), .RN(n2849), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n671),
.CK(clk), .RN(n2849), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n670),
.CK(clk), .RN(n2849), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n669),
.CK(clk), .RN(n2869), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n668),
.CK(clk), .RN(n2870), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n667),
.CK(clk), .RN(n2866), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n666),
.CK(clk), .RN(n2870), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n665),
.CK(clk), .RN(n2869), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n664),
.CK(clk), .RN(n2866), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n663),
.CK(clk), .RN(n2869), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n662),
.CK(clk), .RN(n2870), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n661),
.CK(clk), .RN(n2866), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n660),
.CK(clk), .RN(n2869), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n659),
.CK(clk), .RN(n2870), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n689),
.CK(clk), .RN(n2870), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n688),
.CK(clk), .RN(n2866), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n687),
.CK(clk), .RN(n2869), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n686),
.CK(clk), .RN(n2870), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n685),
.CK(clk), .RN(n2866), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n684),
.CK(clk), .RN(n2869), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n682),
.CK(clk), .RN(n2866), .Q(final_result_ieee[30]) );
DFFSX2TS R_33 ( .D(Add_Subt_Sgf_module_S_to_D[21]), .CK(clk), .SN(n2852),
.Q(n2826) );
DFFSX2TS R_39 ( .D(Add_Subt_Sgf_module_S_to_D[20]), .CK(clk), .SN(n2866),
.Q(n2820) );
DFFSX2TS R_45 ( .D(Add_Subt_Sgf_module_S_to_D[19]), .CK(clk), .SN(n2860),
.Q(n2814) );
DFFSX2TS R_48 ( .D(Add_Subt_Sgf_module_S_to_D[25]), .CK(clk), .SN(n2853),
.Q(n2811) );
DFFSX2TS R_51 ( .D(Add_Subt_Sgf_module_S_to_D[24]), .CK(clk), .SN(n2852),
.Q(n2808) );
DFFRXLTS R_26 ( .D(overflow_flag), .CK(clk), .RN(n1428), .Q(n2832) );
DFFSX2TS R_27 ( .D(n1442), .CK(clk), .SN(n1444), .Q(n2831) );
DFFRX2TS R_17 ( .D(n694), .CK(clk), .RN(n1427), .Q(n2835) );
DFFSX2TS R_12 ( .D(n1442), .CK(clk), .SN(n829), .Q(n2840) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n765), .CK(clk),
.RN(n2863), .Q(Sgf_normalized_result[25]), .QN(n2742) );
DFFRX2TS R_49 ( .D(n733), .CK(clk), .RN(n2868), .Q(n2810) );
DFFRX4TS XRegister_Q_reg_17_ ( .D(n642), .CK(clk), .RN(n1440), .Q(intDX[17]),
.QN(n1379) );
DFFRX4TS XRegister_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n2862), .Q(intDX[2]),
.QN(n1299) );
DFFRX4TS XRegister_Q_reg_14_ ( .D(n639), .CK(clk), .RN(n1437), .Q(intDX[14])
);
DFFRX4TS XRegister_Q_reg_10_ ( .D(n635), .CK(clk), .RN(n2863), .Q(intDX[10])
);
DFFRX4TS XRegister_Q_reg_18_ ( .D(n643), .CK(clk), .RN(n1438), .Q(intDX[18]),
.QN(n1289) );
DFFRX4TS XRegister_Q_reg_8_ ( .D(n633), .CK(clk), .RN(n2861), .Q(intDX[8])
);
DFFRX4TS XRegister_Q_reg_26_ ( .D(n651), .CK(clk), .RN(n2869), .Q(intDX[26])
);
DFFRX4TS XRegister_Q_reg_3_ ( .D(n628), .CK(clk), .RN(n2862), .Q(intDX[3]),
.QN(n1271) );
DFFRX4TS XRegister_Q_reg_0_ ( .D(n625), .CK(clk), .RN(n2862), .Q(intDX[0]),
.QN(n1411) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n749), .CK(clk),
.RN(n2860), .Q(Add_Subt_result[15]), .QN(n2763) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n741), .CK(clk),
.RN(n2851), .Q(Add_Subt_result[7]), .QN(n2758) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n739), .CK(clk),
.RN(n2868), .Q(Add_Subt_result[5]), .QN(n2730) );
DFFSX4TS R_50 ( .D(n2848), .CK(clk), .SN(n2850), .Q(n2809) );
DFFRX4TS YRegister_Q_reg_28_ ( .D(n620), .CK(clk), .RN(n2867), .Q(intDY[28]),
.QN(n2792) );
DFFRX4TS YRegister_Q_reg_26_ ( .D(n618), .CK(clk), .RN(n2864), .Q(intDY[26]),
.QN(n2785) );
DFFRX4TS YRegister_Q_reg_30_ ( .D(n622), .CK(clk), .RN(n2860), .Q(intDY[30]),
.QN(n1635) );
DFFRX4TS YRegister_Q_reg_1_ ( .D(n593), .CK(clk), .RN(n2860), .Q(intDY[1]),
.QN(n2772) );
DFFRX4TS YRegister_Q_reg_7_ ( .D(n599), .CK(clk), .RN(n2861), .Q(intDY[7]),
.QN(n2780) );
DFFRX4TS YRegister_Q_reg_3_ ( .D(n595), .CK(clk), .RN(n2862), .Q(intDY[3]),
.QN(n2790) );
DFFRX2TS R_34 ( .D(n755), .CK(clk), .RN(n2851), .Q(n2825) );
DFFRX4TS YRegister_Q_reg_9_ ( .D(n601), .CK(clk), .RN(n2861), .Q(intDY[9]),
.QN(n2773) );
DFFRX4TS YRegister_Q_reg_19_ ( .D(n611), .CK(clk), .RN(n2865), .Q(intDY[19]),
.QN(n2788) );
DFFRX4TS YRegister_Q_reg_2_ ( .D(n594), .CK(clk), .RN(n2862), .Q(intDY[2]),
.QN(n2784) );
DFFRX4TS YRegister_Q_reg_15_ ( .D(n607), .CK(clk), .RN(n2868), .Q(intDY[15]),
.QN(n2778) );
DFFRX4TS XRegister_Q_reg_30_ ( .D(n655), .CK(clk), .RN(n2860), .Q(intDX[30]),
.QN(n1401) );
DFFRX4TS YRegister_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n2867), .Q(intDY[23]),
.QN(n2775) );
DFFSX4TS R_41 ( .D(n2848), .CK(clk), .SN(n2850), .Q(n2818) );
DFFRX4TS XRegister_Q_reg_11_ ( .D(n636), .CK(clk), .RN(n2865), .Q(intDX[11]),
.QN(n1294) );
DFFRX4TS YRegister_Q_reg_14_ ( .D(n606), .CK(clk), .RN(n2865), .Q(intDY[14]),
.QN(n2771) );
DFFRX4TS YRegister_Q_reg_5_ ( .D(n597), .CK(clk), .RN(n2861), .Q(intDY[5]),
.QN(n2791) );
DFFRX4TS YRegister_Q_reg_10_ ( .D(n602), .CK(clk), .RN(n2863), .Q(intDY[10]),
.QN(n2786) );
DFFRX4TS YRegister_Q_reg_18_ ( .D(n610), .CK(clk), .RN(n2865), .Q(intDY[18]),
.QN(n2795) );
DFFRX4TS YRegister_Q_reg_20_ ( .D(n612), .CK(clk), .RN(n2867), .Q(intDY[20]),
.QN(n2794) );
DFFRX4TS YRegister_Q_reg_21_ ( .D(n613), .CK(clk), .RN(n2864), .Q(intDY[21]),
.QN(n2776) );
DFFRX4TS YRegister_Q_reg_24_ ( .D(n616), .CK(clk), .RN(n2864), .Q(intDY[24]),
.QN(n2769) );
DFFSX4TS R_35 ( .D(n2848), .CK(clk), .SN(n2850), .Q(n2824) );
DFFRX4TS YRegister_Q_reg_17_ ( .D(n609), .CK(clk), .RN(n2863), .Q(intDY[17]),
.QN(n2777) );
DFFRX4TS YRegister_Q_reg_12_ ( .D(n604), .CK(clk), .RN(n2864), .Q(intDY[12]),
.QN(n2782) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n713), .CK(clk),
.RN(n2851), .Q(Sgf_normalized_result[10]), .QN(n2755) );
DFFSX4TS R_15 ( .D(n1442), .CK(clk), .SN(n1428), .Q(n2837) );
DFFRX4TS XRegister_Q_reg_25_ ( .D(n650), .CK(clk), .RN(n2864), .Q(intDX[25]),
.QN(n1321) );
DFFRX4TS YRegister_Q_reg_0_ ( .D(n592), .CK(clk), .RN(n2862), .Q(intDY[0])
);
DFFRHQX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n657),
.CK(clk), .RN(n1438), .Q(final_result_ieee[31]) );
DFFRHQX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n681),
.CK(clk), .RN(n2857), .Q(final_result_ieee[0]) );
DFFRHQX8TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n735), .CK(clk),
.RN(n1439), .Q(Add_Subt_result[1]) );
DFFSX4TS R_56 ( .D(n830), .CK(clk), .SN(n1444), .Q(n2803), .QN(n1390) );
DFFRHQX8TS YRegister_Q_reg_16_ ( .D(n608), .CK(clk), .RN(n1439), .Q(
intDY[16]) );
DFFSHQX8TS YRegister_Q_reg_25_ ( .D(n1634), .CK(clk), .SN(n1437), .Q(n2793)
);
DFFSX4TS R_53 ( .D(n2848), .CK(clk), .SN(n2850), .Q(n2806) );
DFFSRHQX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .SN(1'b1),
.RN(n1438), .Q(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n528), .CK(clk),
.SN(1'b1), .RN(n1439), .Q(DmP[30]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n561), .CK(clk),
.SN(1'b1), .RN(n1437), .Q(DMP[0]) );
DFFSRHQX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .SN(1'b1),
.RN(n1440), .Q(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n570), .CK(clk),
.SN(1'b1), .RN(n1430), .Q(DMP[9]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n569), .CK(clk),
.SN(1'b1), .RN(n1439), .Q(DMP[8]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n568), .CK(clk),
.SN(1'b1), .RN(n1430), .Q(DMP[7]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n566), .CK(clk),
.SN(1'b1), .RN(n1431), .Q(DMP[5]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n564), .CK(clk),
.SN(1'b1), .RN(n1438), .Q(DMP[3]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n553), .CK(clk),
.SN(1'b1), .RN(n1430), .Q(DmP[24]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n541), .CK(clk),
.SN(1'b1), .RN(n1439), .Q(DmP[12]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n538), .CK(clk),
.SN(1'b1), .RN(n1432), .Q(DmP[9]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n536), .CK(clk),
.SN(1'b1), .RN(n1438), .Q(DmP[7]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n554), .CK(clk),
.SN(1'b1), .RN(n1440), .Q(DmP[25]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n552), .CK(clk),
.SN(1'b1), .RN(n1432), .Q(DmP[23]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n540), .CK(clk),
.SN(1'b1), .RN(n1439), .Q(DmP[11]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n567), .CK(clk),
.SN(1'b1), .RN(n1437), .Q(DMP[6]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n565), .CK(clk),
.SN(1'b1), .RN(n1440), .Q(DMP[4]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n542), .CK(clk),
.SN(1'b1), .RN(n1432), .Q(DmP[13]) );
DFFSRHQX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .SN(1'b1),
.RN(n1439), .Q(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n581), .CK(clk),
.SN(1'b1), .RN(n1437), .Q(DMP[20]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n582), .CK(clk),
.SN(1'b1), .RN(n1432), .Q(DMP[21]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n534), .CK(clk),
.SN(1'b1), .RN(n1438), .Q(DmP[5]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n583), .CK(clk),
.SN(1'b1), .RN(n1430), .Q(DMP[22]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n533), .CK(clk),
.SN(1'b1), .RN(n1437), .Q(DmP[4]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n557), .CK(clk),
.SN(1'b1), .RN(n1432), .Q(DmP[28]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n556), .CK(clk),
.SN(1'b1), .RN(n1437), .Q(DmP[27]) );
DFFSRHQX4TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n558), .CK(clk),
.SN(1'b1), .RN(n1438), .Q(DmP[29]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n576), .CK(clk),
.SN(1'b1), .RN(n1440), .Q(DMP[15]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n580), .CK(clk),
.SN(1'b1), .RN(n1432), .Q(DMP[19]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n579), .CK(clk),
.SN(1'b1), .RN(n1439), .Q(DMP[18]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n575), .CK(clk),
.SN(1'b1), .RN(n1437), .Q(DMP[14]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n573), .CK(clk),
.SN(1'b1), .RN(n1440), .Q(DMP[12]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n571), .CK(clk),
.SN(1'b1), .RN(n1432), .Q(DMP[10]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n578), .CK(clk),
.SN(1'b1), .RN(n1430), .Q(DMP[17]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n572), .CK(clk),
.SN(1'b1), .RN(n1439), .Q(DMP[11]) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n577), .CK(clk),
.SN(1'b1), .RN(n1438), .Q(DMP[16]) );
DFFSRHQX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .SN(1'b1),
.RN(n1432), .Q(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFSX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n1211), .CK(
clk), .SN(n1432), .Q(n2733), .QN(n2721) );
DFFRHQX2TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n724), .CK(clk),
.RN(n1437), .Q(Sgf_normalized_result[21]) );
DFFSRHQX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .SN(1'b1),
.RN(n1430), .Q(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n719), .CK(clk),
.RN(n2856), .Q(Sgf_normalized_result[16]), .QN(n2751) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n723), .CK(clk),
.RN(n2852), .Q(Sgf_normalized_result[20]), .QN(n2749) );
DFFRX4TS XRegister_Q_reg_27_ ( .D(n652), .CK(clk), .RN(n2867), .Q(intDX[27]),
.QN(n799) );
DFFRX4TS XRegister_Q_reg_29_ ( .D(n654), .CK(clk), .RN(n2857), .Q(intDX[29]),
.QN(n1400) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n743), .CK(clk),
.RN(n2859), .Q(Add_Subt_result[9]), .QN(n2757) );
DFFRX4TS XRegister_Q_reg_22_ ( .D(n647), .CK(clk), .RN(n2867), .Q(intDX[22])
);
DFFRX4TS XRegister_Q_reg_6_ ( .D(n631), .CK(clk), .RN(n2861), .Q(intDX[6])
);
DFFRX4TS XRegister_Q_reg_4_ ( .D(n629), .CK(clk), .RN(n2862), .Q(intDX[4])
);
DFFRX4TS YRegister_Q_reg_11_ ( .D(n603), .CK(clk), .RN(n2868), .Q(intDY[11]),
.QN(n2779) );
DFFRX4TS XRegister_Q_reg_16_ ( .D(n641), .CK(clk), .RN(n2868), .Q(intDX[16])
);
DFFRX4TS R_55 ( .D(n752), .CK(clk), .RN(n2859), .Q(n2804) );
DFFRX4TS YRegister_Q_reg_29_ ( .D(n621), .CK(clk), .RN(n2864), .Q(intDY[29]),
.QN(n2781) );
DFFRX4TS YRegister_Q_reg_27_ ( .D(n619), .CK(clk), .RN(n2862), .Q(intDY[27]),
.QN(n2774) );
DFFRX4TS YRegister_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n2861), .Q(intDY[6]),
.QN(n2787) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n740), .CK(clk),
.RN(n2868), .Q(Add_Subt_result[6]), .QN(n2801) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n725), .CK(clk),
.RN(n2853), .Q(Sgf_normalized_result[22]), .QN(n2748) );
DFFRX4TS YRegister_Q_reg_4_ ( .D(n596), .CK(clk), .RN(n2862), .Q(intDY[4]),
.QN(n2783) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n726), .CK(clk),
.RN(n2853), .Q(Sgf_normalized_result[23]), .QN(n2747) );
DFFRX4TS YRegister_Q_reg_22_ ( .D(n614), .CK(clk), .RN(n2857), .Q(intDY[22]),
.QN(n2770) );
DFFSX2TS R_36 ( .D(Add_Subt_Sgf_module_S_to_D[17]), .CK(clk), .SN(n1444),
.Q(n2823) );
DFFRX4TS YRegister_Q_reg_13_ ( .D(n605), .CK(clk), .RN(n2863), .Q(intDY[13]),
.QN(n2789) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n698), .CK(clk), .RN(
n1440), .Q(exp_oper_result[1]), .QN(n2727) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n590), .CK(clk), .RN(
n828), .Q(DMP[29]), .QN(n2737) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n530), .CK(clk), .RN(
n825), .Q(DmP[1]) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n549), .CK(clk), .RN(
n2855), .Q(DmP[20]) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n547), .CK(clk), .RN(
n2855), .Q(DmP[18]) );
DFFSX4TS R_38 ( .D(n830), .CK(clk), .SN(n1444), .Q(n2821) );
DFFSX4TS R_32 ( .D(n1426), .CK(clk), .SN(n1444), .Q(n2827) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n696), .CK(clk), .RN(
n1427), .Q(exp_oper_result[3]), .QN(n2728) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n709), .CK(clk),
.RN(n2851), .Q(n1417) );
DFFRX4TS R_14 ( .D(n1235), .CK(clk), .RN(n1427), .Q(n2838) );
DFFSX4TS R_13 ( .D(n1421), .CK(clk), .SN(n1428), .QN(n852) );
DFFRHQX8TS Sel_B_Q_reg_0_ ( .D(n701), .CK(clk), .RN(n656), .Q(n1416) );
DFFRHQX8TS R_29 ( .D(n2830), .CK(clk), .RN(n656), .Q(n1415) );
DFFRHQX8TS Sel_B_Q_reg_1_ ( .D(n700), .CK(clk), .RN(n656), .Q(n1413) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n717), .CK(clk),
.RN(n2870), .Q(Sgf_normalized_result[14]), .QN(n2752) );
DFFSX4TS R_16 ( .D(Exp_Operation_Module_Data_S[5]), .CK(clk), .SN(n1428),
.Q(n2836) );
DFFSX4TS R_18 ( .D(n2286), .CK(clk), .SN(n1428), .Q(n2834) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n718), .CK(clk),
.RN(n2853), .Q(Sgf_normalized_result[15]) );
DFFSX1TS R_3 ( .D(n2876), .CK(clk), .SN(n1427), .Q(n2845) );
DFFSRHQX8TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .SN(1'b1),
.RN(n1430), .Q(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRHQX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n2853),
.Q(n1359) );
DFFRHQX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n2852),
.Q(n1346) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n736), .CK(clk),
.RN(n828), .Q(Add_Subt_result[2]), .QN(n2731) );
DFFRHQX8TS FS_Module_state_reg_reg_3_ ( .D(n763), .CK(clk), .RN(n2857), .Q(
n1324) );
DFFSRHQX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n2796),
.CK(clk), .SN(1'b1), .RN(n1431), .Q(LZA_output[4]) );
DFFSRHQX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .SN(1'b1),
.RN(n1440), .Q(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFSHQX8TS R_23 ( .D(n2732), .CK(clk), .SN(n656), .Q(n1322) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n708), .CK(clk),
.RN(n2850), .Q(n1318) );
DFFRHQX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n757), .CK(clk), .RN(n823), .Q(Add_Subt_result[23]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n710), .CK(clk),
.RN(n2851), .Q(Sgf_normalized_result[7]), .QN(n2734) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n707), .CK(clk),
.RN(n2850), .Q(Sgf_normalized_result[4]), .QN(n2735) );
DFFRHQX2TS XRegister_Q_reg_1_ ( .D(n626), .CK(clk), .RN(n2860), .Q(n1307) );
DFFRHQX4TS XRegister_Q_reg_20_ ( .D(n645), .CK(clk), .RN(n2864), .Q(n1305)
);
DFFRHQX8TS XRegister_Q_reg_19_ ( .D(n644), .CK(clk), .RN(n2868), .Q(n1301)
);
DFFRHQX8TS FS_Module_state_reg_reg_1_ ( .D(n761), .CK(clk), .RN(n2857), .Q(
n1295) );
DFFSHQX8TS R_28 ( .D(n2732), .CK(clk), .SN(n656), .Q(n1292) );
DFFSHQX8TS R_9 ( .D(n2843), .CK(clk), .SN(n1438), .Q(n1290) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n727), .CK(clk),
.RN(n2863), .Q(Sgf_normalized_result[24]), .QN(n2746) );
DFFRHQX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n748), .CK(clk), .RN(n1444), .Q(n1283) );
DFFSX2TS R_30 ( .D(Add_Subt_Sgf_module_S_to_D[16]), .CK(clk), .SN(n1444),
.Q(n2829) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n529), .CK(clk),
.RN(n825), .Q(n1279) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n704), .CK(clk),
.RN(n2859), .Q(n1273) );
DFFRHQX2TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n706), .CK(clk),
.RN(n2850), .Q(n1269) );
DFFRHQX8TS Sel_C_Q_reg_0_ ( .D(n759), .CK(clk), .RN(n656), .Q(n1263) );
DFFSX1TS R_5 ( .D(n2875), .CK(clk), .SN(n1428), .Q(n2844) );
DFFSX2TS R_62 ( .D(n1539), .CK(clk), .SN(n823), .Q(n1258) );
DFFSX2TS R_66 ( .D(n1577), .CK(clk), .SN(n829), .Q(n1254) );
DFFSX2TS R_65 ( .D(n1442), .CK(clk), .SN(n829), .Q(n1255) );
DFFSX2TS R_64 ( .D(n1576), .CK(clk), .SN(n829), .Q(n1256) );
DFFRX1TS R_46 ( .D(n753), .CK(clk), .RN(n2867), .Q(n2813) );
DFFRX2TS R_40 ( .D(n754), .CK(clk), .RN(n2851), .Q(n2819) );
DFFRX2TS R_52 ( .D(n758), .CK(clk), .RN(n2851), .Q(n2807) );
DFFRX2TS R_37 ( .D(n751), .CK(clk), .RN(n2859), .Q(n2822) );
DFFRX2TS R_31 ( .D(n750), .CK(clk), .RN(n2859), .Q(n2828) );
DFFRX2TS R_43 ( .D(n1092), .CK(clk), .RN(n2865), .Q(n2816) );
DFFSX2TS R_77 ( .D(Exp_Operation_Module_Data_S[8]), .CK(clk), .SN(n823), .Q(
n1242) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n722), .CK(clk),
.RN(n2869), .Q(Sgf_normalized_result[19]), .QN(n2750) );
DFFRX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n731), .CK(
clk), .RN(n2850), .Q(LZA_output[1]) );
DFFRHQX8TS YRegister_Q_reg_8_ ( .D(n600), .CK(clk), .RN(n2861), .Q(n1239) );
DFFRHQX8TS R_8 ( .D(n760), .CK(clk), .RN(n1427), .Q(n1237) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n746), .CK(clk),
.RN(n2859), .Q(Add_Subt_result[12]), .QN(n2759) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n747), .CK(clk),
.RN(n2859), .Q(Add_Subt_result[13]), .QN(n2799) );
DFFRHQX8TS XRegister_Q_reg_7_ ( .D(n632), .CK(clk), .RN(n2861), .Q(n1236) );
DFFSX2TS R_54 ( .D(Add_Subt_Sgf_module_S_to_D[18]), .CK(clk), .SN(n1444),
.Q(n2805) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n742), .CK(clk),
.RN(n2859), .Q(Add_Subt_result[8]), .QN(n2802) );
DFFRHQX2TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n730), .CK(
clk), .RN(n829), .Q(n1315) );
DFFRHQX8TS FS_Module_state_reg_reg_0_ ( .D(n762), .CK(clk), .RN(n2860), .Q(
n1330) );
DFFRX4TS XRegister_Q_reg_24_ ( .D(n649), .CK(clk), .RN(n2857), .Q(intDX[24]),
.QN(n1234) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n720), .CK(clk),
.RN(n2869), .Q(Sgf_normalized_result[17]), .QN(n2744) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n589), .CK(clk), .RN(
n828), .Q(DMP[28]), .QN(n2738) );
DFFRX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n729), .CK(
clk), .RN(n2865), .Q(LZA_output[3]), .QN(n2798) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n699), .CK(clk), .RN(
n1427), .Q(exp_oper_result[0]), .QN(n2725) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n697), .CK(clk), .RN(
n2856), .Q(exp_oper_result[2]), .QN(n2726) );
DFFRHQX4TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n764), .CK(
clk), .RN(n2867), .Q(n1329) );
DFFSHQX8TS R_22 ( .D(n2833), .CK(clk), .SN(n1440), .Q(n2872) );
DFFSX4TS R_44 ( .D(n1425), .CK(clk), .SN(n2852), .Q(n2815) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n714), .CK(clk),
.RN(n826), .Q(Sgf_normalized_result[11]), .QN(n2754) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n712), .CK(clk),
.RN(n2851), .Q(Sgf_normalized_result[9]), .QN(n2756) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n562), .CK(clk), .RN(
n2850), .Q(DMP[1]) );
DFFSX2TS R_42 ( .D(Add_Subt_Sgf_module_S_to_D[22]), .CK(clk), .SN(n2853),
.Q(n2817) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n546), .CK(clk), .RN(
n824), .Q(DmP[17]) );
DFFRX4TS R_67 ( .D(n1276), .CK(clk), .RN(n824), .Q(n1253) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n715), .CK(clk),
.RN(n824), .Q(Sgf_normalized_result[12]), .QN(n2753) );
DFFRX4TS R_68 ( .D(n1802), .CK(clk), .RN(n826), .Q(n1252) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n826),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n543), .CK(clk), .RN(
n2855), .Q(DmP[14]) );
DFFRHQX8TS XRegister_Q_reg_13_ ( .D(n638), .CK(clk), .RN(n823), .Q(n1309) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n716), .CK(clk),
.RN(n2870), .Q(Sgf_normalized_result[13]), .QN(n2745) );
DFFRHQX2TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n559), .CK(clk),
.RN(n2860), .Q(n816) );
DFFRHQX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n703), .CK(clk),
.RN(n2850), .Q(n814) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n548), .CK(clk), .RN(
n2855), .Q(DmP[19]) );
DFFRHQX4TS XRegister_Q_reg_21_ ( .D(n646), .CK(clk), .RN(n2857), .Q(n809) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n586), .CK(clk), .RN(
n1428), .Q(DMP[25]), .QN(n2739) );
DFFSRHQX4TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n563), .CK(clk),
.SN(1'b1), .RN(n1431), .Q(DMP[2]) );
DFFRHQX2TS XRegister_Q_reg_28_ ( .D(n653), .CK(clk), .RN(n2864), .Q(n801) );
DFFRX2TS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n584), .CK(clk), .RN(
n1427), .Q(DMP[23]), .QN(n2741) );
DFFSX4TS R_47 ( .D(n2848), .CK(clk), .SN(n2852), .Q(n2812) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n705), .CK(clk),
.RN(n1444), .Q(n1314) );
DFFSRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n711), .CK(clk),
.SN(1'b1), .RN(n1440), .Q(Sgf_normalized_result[8]) );
DFFRHQX4TS XRegister_Q_reg_5_ ( .D(n630), .CK(clk), .RN(n2861), .Q(n1304) );
DFFRHQX4TS XRegister_Q_reg_12_ ( .D(n637), .CK(clk), .RN(n2865), .Q(n1260)
);
DFFRHQX4TS XRegister_Q_reg_9_ ( .D(n634), .CK(clk), .RN(n2861), .Q(n1303) );
DFFRHQX4TS XRegister_Q_reg_15_ ( .D(n640), .CK(clk), .RN(n1430), .Q(
intDX[15]) );
DFFRHQX4TS XRegister_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n2864), .Q(n1327)
);
DFFRX2TS R_11 ( .D(n693), .CK(clk), .RN(n828), .Q(n2841) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n744), .CK(clk),
.RN(n2859), .Q(Add_Subt_result[10]), .QN(n2724) );
DFFSX1TS R_10 ( .D(Exp_Operation_Module_Data_S[6]), .CK(clk), .SN(n829), .Q(
n2842) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n588), .CK(clk),
.RN(n1428), .Q(n807) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n555), .CK(clk),
.RN(n2865), .Q(n1226) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n587), .CK(clk),
.RN(n1428), .Q(n820) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n745), .CK(clk),
.RN(n2859), .Q(Add_Subt_result[11]), .QN(n2800) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n531), .CK(clk),
.RN(n826), .Q(n1280) );
DFFSRHQX2TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n537), .CK(clk),
.SN(1'b1), .RN(n1437), .Q(DmP[8]) );
DFFSX2TS R_61 ( .D(n2260), .CK(clk), .SN(n1431), .Q(n1259) );
DFFRX2TS R_63 ( .D(n2260), .CK(clk), .RN(n1431), .Q(n1257) );
DFFRHQX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n734), .CK(clk),
.RN(n823), .Q(Add_Subt_result[0]) );
DFFRX1TS R_0 ( .D(n1369), .CK(clk), .RN(n2860), .Q(intDY[31]), .QN(n1398) );
DFFRX1TS R_1 ( .D(n1387), .CK(clk), .RN(n2860), .Q(intAS), .QN(n1370) );
DFFRX1TS R_69 ( .D(n1277), .CK(clk), .RN(n824), .Q(n1251) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n825),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[47]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n2853),
.QN(n1451) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n2853),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[41]), .QN(n2765) );
DFFRX2TS R_21 ( .D(n624), .CK(clk), .RN(n1431), .Q(intDX[31]), .QN(n1399) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n2853),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[42]), .QN(n2764) );
DFFRX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n683),
.CK(clk), .RN(n2870), .Q(final_result_ieee[29]) );
DFFSX1TS R_20 ( .D(n2846), .CK(clk), .SN(n1439), .Q(n2871) );
CLKINVX2TS U868 ( .A(n827), .Y(n828) );
CLKINVX2TS U869 ( .A(n2854), .Y(n825) );
CLKINVX2TS U870 ( .A(n2854), .Y(n824) );
CLKINVX2TS U871 ( .A(n2854), .Y(n826) );
CLKBUFX2TS U872 ( .A(n1431), .Y(n823) );
CLKMX2X2TS U873 ( .A(Data_Y[0]), .B(n885), .S0(n1448), .Y(n592) );
CLKINVX3TS U874 ( .A(rst), .Y(n1428) );
INVX2TS U875 ( .A(n827), .Y(n829) );
NAND3X2TS U876 ( .A(n1797), .B(n1799), .C(n1798), .Y(n587) );
NAND3X4TS U877 ( .A(n2344), .B(n2343), .C(n2342), .Y(n575) );
NAND3X4TS U878 ( .A(n2333), .B(n2332), .C(n2331), .Y(n544) );
NAND2X1TS U879 ( .A(n2573), .B(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n2032) );
NAND2X1TS U880 ( .A(n2625), .B(n2562), .Y(n2053) );
AND2X4TS U881 ( .A(n1433), .B(n801), .Y(n802) );
NAND2X1TS U882 ( .A(n2573), .B(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1887) );
NAND2X2TS U883 ( .A(n1350), .B(n873), .Y(n2342) );
NAND2X1TS U884 ( .A(n2509), .B(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1888) );
NAND2X1TS U885 ( .A(n2509), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n2446) );
NAND2X1TS U886 ( .A(n2573), .B(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .Y(n2453) );
NAND2X4TS U887 ( .A(n859), .B(n873), .Y(n2312) );
NAND2X4TS U888 ( .A(n849), .B(n1443), .Y(n1990) );
NAND2X2TS U889 ( .A(n1233), .B(intDX[25]), .Y(n2318) );
NAND2X4TS U890 ( .A(n908), .B(intDY[16]), .Y(n2355) );
NAND2X2TS U891 ( .A(n971), .B(n790), .Y(n2600) );
NAND2X2TS U892 ( .A(n908), .B(intDY[17]), .Y(n2361) );
AOI22X1TS U893 ( .A0(n2555), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n2554), .B1(
Sgf_normalized_result[23]), .Y(n2070) );
NAND2X2TS U894 ( .A(n1488), .B(n833), .Y(n1141) );
NAND2X1TS U895 ( .A(n2625), .B(n2591), .Y(n1682) );
NAND2X1TS U896 ( .A(n2848), .B(n1300), .Y(n2189) );
NAND2X1TS U897 ( .A(n1425), .B(Add_Subt_result[10]), .Y(n1532) );
NAND2X1TS U898 ( .A(n2610), .B(DMP[0]), .Y(n2608) );
NAND2X1TS U899 ( .A(n2610), .B(DMP[6]), .Y(n2366) );
NAND2X1TS U900 ( .A(n2334), .B(DMP[21]), .Y(n2127) );
NAND2X1TS U901 ( .A(n2610), .B(DMP[4]), .Y(n2369) );
NAND2X1TS U902 ( .A(n2597), .B(DmP[9]), .Y(n2326) );
OR2X2TS U903 ( .A(n2579), .B(n1983), .Y(n1993) );
NAND2X1TS U904 ( .A(n2626), .B(n833), .Y(n1966) );
NAND2XLTS U905 ( .A(n2334), .B(n1280), .Y(n1804) );
NAND2X4TS U906 ( .A(n1028), .B(n1392), .Y(n1620) );
NAND2X1TS U907 ( .A(n2524), .B(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n2525) );
NAND2X1TS U908 ( .A(n2571), .B(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n2530) );
NAND2X1TS U909 ( .A(n2574), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n2575) );
NAND2X1TS U910 ( .A(n2574), .B(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n2001) );
NAND2X1TS U911 ( .A(n2597), .B(DmP[8]), .Y(n2298) );
NAND2X1TS U912 ( .A(n2509), .B(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .Y(n2436) );
INVX2TS U913 ( .A(rst), .Y(n1431) );
INVX3TS U914 ( .A(n1371), .Y(n2401) );
CLKAND2X2TS U915 ( .A(n2597), .B(DmP[23]), .Y(n805) );
NAND2X1TS U916 ( .A(n863), .B(n2205), .Y(n2206) );
NAND2XLTS U917 ( .A(n2273), .B(n2272), .Y(n2274) );
NAND2X1TS U918 ( .A(n1491), .B(n2584), .Y(n2067) );
NAND2X1TS U919 ( .A(n2571), .B(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n2472) );
OA22X2TS U920 ( .A0(n1238), .A1(n2764), .B0(n1265), .B1(n1347), .Y(n2495) );
NAND2XLTS U921 ( .A(n2535), .B(DMP[23]), .Y(n2136) );
NAND2XLTS U922 ( .A(n2334), .B(n1279), .Y(n2073) );
NAND2X2TS U923 ( .A(n1353), .B(intDY[14]), .Y(n2314) );
OR2X2TS U924 ( .A(n1008), .B(n1007), .Y(n1363) );
INVX2TS U925 ( .A(n1371), .Y(n2399) );
NAND2X1TS U926 ( .A(n2556), .B(n2528), .Y(n2430) );
NAND2X6TS U927 ( .A(n859), .B(intDX[18]), .Y(n2114) );
AOI22X1TS U928 ( .A0(n836), .A1(n1359), .B0(n2524), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .Y(n2071) );
CLKAND2X2TS U929 ( .A(n1641), .B(n2200), .Y(n2201) );
NAND3X2TS U930 ( .A(n1028), .B(n1044), .C(n1175), .Y(n1170) );
CLKAND2X2TS U931 ( .A(n2151), .B(n1382), .Y(n822) );
XOR2X2TS U932 ( .A(n1367), .B(n1394), .Y(n1332) );
NAND2XLTS U933 ( .A(n2597), .B(DmP[11]), .Y(n2323) );
NAND2XLTS U934 ( .A(n2597), .B(DmP[7]), .Y(n2320) );
NAND2XLTS U935 ( .A(n2597), .B(DmP[12]), .Y(n2301) );
NAND2X2TS U936 ( .A(n971), .B(intDY[6]), .Y(n2367) );
NAND2X2TS U937 ( .A(n971), .B(intDY[4]), .Y(n2370) );
NAND2XLTS U938 ( .A(n2358), .B(DMP[20]), .Y(n2352) );
AOI21X2TS U939 ( .A0(n2572), .A1(Sgf_normalized_result[12]), .B0(n2452), .Y(
n2442) );
NAND2X2TS U940 ( .A(n1350), .B(intDX[22]), .Y(n2123) );
AOI21X2TS U941 ( .A0(n2572), .A1(Sgf_normalized_result[17]), .B0(n2452), .Y(
n2034) );
NAND2XLTS U942 ( .A(n2395), .B(n1217), .Y(n1213) );
NAND2X2TS U943 ( .A(n1357), .B(intDY[28]), .Y(n1876) );
NAND2X2TS U944 ( .A(n971), .B(intDY[3]), .Y(n2382) );
AOI21X2TS U945 ( .A0(n2572), .A1(Sgf_normalized_result[11]), .B0(n2452), .Y(
n2447) );
AOI21X2TS U946 ( .A0(n2572), .A1(Sgf_normalized_result[10]), .B0(n2452), .Y(
n2455) );
OR2X2TS U947 ( .A(n2579), .B(n1681), .Y(n2064) );
NAND3X2TS U948 ( .A(n1182), .B(n863), .C(n1175), .Y(n1174) );
NAND2X2TS U949 ( .A(n2638), .B(n2641), .Y(n1900) );
OR2X2TS U950 ( .A(n2579), .B(n1372), .Y(n2283) );
NAND2X2TS U951 ( .A(n1233), .B(intDX[4]), .Y(n2089) );
NAND2X2TS U952 ( .A(n1349), .B(n790), .Y(n1797) );
AOI2BB2X2TS U953 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[32]), .B1(
n2509), .A0N(n2508), .A1N(n2766), .Y(n2512) );
OAI21X2TS U954 ( .A0(n2582), .A1(n2583), .B0(n835), .Y(n1553) );
NOR2X1TS U955 ( .A(n1172), .B(n2194), .Y(n1171) );
AOI22X1TS U956 ( .A0(n2555), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n2554), .B1(
Sgf_normalized_result[25]), .Y(n2553) );
NAND2X2TS U957 ( .A(n2571), .B(n1454), .Y(n2478) );
NAND2X4TS U958 ( .A(n908), .B(intDY[14]), .Y(n2344) );
AOI22X2TS U959 ( .A0(n836), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n2524), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n2003) );
NAND2X2TS U960 ( .A(n1488), .B(n2639), .Y(n2618) );
INVX2TS U961 ( .A(n2858), .Y(n827) );
CLKINVX1TS U962 ( .A(n1235), .Y(n1246) );
NAND2X4TS U963 ( .A(n849), .B(n834), .Y(n1185) );
INVX2TS U964 ( .A(n2863), .Y(n2854) );
BUFX3TS U965 ( .A(n2294), .Y(n2338) );
BUFX4TS U966 ( .A(n2294), .Y(n2597) );
NOR2X2TS U967 ( .A(n2193), .B(n1173), .Y(n1172) );
INVX6TS U968 ( .A(n1372), .Y(n2639) );
INVX12TS U969 ( .A(n1238), .Y(n836) );
NAND2X2TS U970 ( .A(n1066), .B(n1999), .Y(n2000) );
INVX2TS U971 ( .A(n1917), .Y(n985) );
BUFX6TS U972 ( .A(n1233), .Y(n783) );
BUFX16TS U973 ( .A(n930), .Y(n911) );
NAND2XLTS U974 ( .A(n2610), .B(DMP[9]), .Y(n2378) );
NAND2XLTS U975 ( .A(n2610), .B(DMP[3]), .Y(n2381) );
CLKBUFX2TS U976 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(
n1454) );
NAND2X1TS U977 ( .A(n1637), .B(n2457), .Y(n2421) );
INVX2TS U978 ( .A(n1282), .Y(n2221) );
INVX8TS U979 ( .A(n2110), .Y(n2571) );
CLKINVX1TS U980 ( .A(n2208), .Y(n2210) );
NOR2X4TS U981 ( .A(n1871), .B(n2398), .Y(n2100) );
BUFX4TS U982 ( .A(n1430), .Y(n2863) );
INVX1TS U983 ( .A(n2395), .Y(n866) );
AND2X2TS U984 ( .A(n2254), .B(n2255), .Y(n1342) );
INVX6TS U985 ( .A(n2110), .Y(n2524) );
CLKBUFX2TS U986 ( .A(n2857), .Y(n2858) );
CLKAND2X2TS U987 ( .A(n2193), .B(n1179), .Y(n1178) );
BUFX3TS U988 ( .A(intDX[26]), .Y(n790) );
NOR2X2TS U989 ( .A(n991), .B(n945), .Y(n944) );
CLKBUFX2TS U990 ( .A(intDX[14]), .Y(n873) );
CLKBUFX2TS U991 ( .A(intDX[16]), .Y(n795) );
AND2X4TS U992 ( .A(n1176), .B(n1628), .Y(n1175) );
NOR2X2TS U993 ( .A(n2236), .B(n2230), .Y(n2232) );
INVX6TS U994 ( .A(n1197), .Y(n1354) );
NAND2X1TS U995 ( .A(n2518), .B(n832), .Y(n2519) );
NOR2X2TS U996 ( .A(n2269), .B(n2268), .Y(n2271) );
AND2X4TS U997 ( .A(n2239), .B(n2241), .Y(n1612) );
CLKAND2X2TS U998 ( .A(n1643), .B(n1629), .Y(n1313) );
NAND2X1TS U999 ( .A(n2460), .B(n2459), .Y(n2461) );
NAND4XLTS U1000 ( .A(n1442), .B(n2412), .C(n1830), .D(n2411), .Y(n1872) );
INVX6TS U1001 ( .A(n1050), .Y(n2644) );
NAND2BX1TS U1002 ( .AN(n1945), .B(n1946), .Y(n2668) );
INVX1TS U1003 ( .A(n1241), .Y(n2209) );
NAND2X4TS U1004 ( .A(n1981), .B(n1980), .Y(n2518) );
AND2X6TS U1005 ( .A(n1540), .B(n992), .Y(n991) );
INVX6TS U1006 ( .A(n2202), .Y(n1182) );
AND2X6TS U1007 ( .A(n1464), .B(n1538), .Y(n846) );
BUFX3TS U1008 ( .A(n2294), .Y(n2358) );
INVX2TS U1009 ( .A(n2204), .Y(n863) );
INVX2TS U1010 ( .A(n2267), .Y(n2269) );
INVX6TS U1011 ( .A(n1372), .Y(n2589) );
INVX2TS U1012 ( .A(n1224), .Y(n1891) );
NOR2BX1TS U1013 ( .AN(n1505), .B(n1370), .Y(n1502) );
INVX4TS U1014 ( .A(n1372), .Y(n2584) );
NOR2X4TS U1015 ( .A(n1550), .B(n1223), .Y(n1549) );
NOR2X6TS U1016 ( .A(n2384), .B(n1869), .Y(n1871) );
NOR2X6TS U1017 ( .A(n1367), .B(n1485), .Y(n1484) );
AOI2BB2X2TS U1018 ( .B0(n959), .B1(Add_Subt_result[11]), .A0N(n957), .A1N(
n1668), .Y(n958) );
NAND2X4TS U1019 ( .A(n1166), .B(n1653), .Y(n1551) );
BUFX3TS U1020 ( .A(n1371), .Y(n2398) );
NOR2X1TS U1021 ( .A(n2208), .B(n2197), .Y(n2199) );
NOR2X4TS U1022 ( .A(n1687), .B(n988), .Y(n987) );
NAND2X2TS U1023 ( .A(n1020), .B(Add_Subt_result[6]), .Y(n1987) );
NAND2X2TS U1024 ( .A(n1446), .B(n752), .Y(n1978) );
INVX2TS U1025 ( .A(n1483), .Y(n1414) );
NOR2X6TS U1026 ( .A(n870), .B(n1060), .Y(n1059) );
NAND2X2TS U1027 ( .A(n2542), .B(n751), .Y(n1676) );
NAND2X1TS U1028 ( .A(n2043), .B(DmP[10]), .Y(n1123) );
NAND2X2TS U1029 ( .A(n1122), .B(n755), .Y(n1140) );
NAND2X2TS U1030 ( .A(n2542), .B(n752), .Y(n1672) );
NAND2X2TS U1031 ( .A(n959), .B(Add_Subt_result[15]), .Y(n1962) );
NAND2X2TS U1032 ( .A(n959), .B(Add_Subt_result[5]), .Y(n887) );
NAND2X2TS U1033 ( .A(ready), .B(n1828), .Y(n2412) );
NOR2X6TS U1034 ( .A(n2007), .B(n941), .Y(n1394) );
NAND2X2TS U1035 ( .A(n1050), .B(n865), .Y(n1052) );
INVX6TS U1036 ( .A(n1371), .Y(n2674) );
NAND2X2TS U1037 ( .A(n2243), .B(n753), .Y(n1961) );
BUFX6TS U1038 ( .A(n2675), .Y(n1339) );
AOI21X2TS U1039 ( .A0(n1560), .A1(n1639), .B0(n2228), .Y(n2229) );
NOR2X2TS U1040 ( .A(n2450), .B(n1071), .Y(n787) );
AOI2BB2X2TS U1041 ( .B0(n1207), .B1(n1206), .A0N(n2276), .A1N(n2730), .Y(
n1208) );
AOI22X2TS U1042 ( .A0(n1122), .A1(n752), .B0(n1003), .B1(DmP[5]), .Y(n2079)
);
NOR2X4TS U1043 ( .A(n1005), .B(n1189), .Y(n1004) );
AND2X4TS U1044 ( .A(n1913), .B(n1219), .Y(n848) );
INVX6TS U1045 ( .A(n1999), .Y(n2554) );
NOR2X4TS U1046 ( .A(n2268), .B(n2204), .Y(n1044) );
AND3X4TS U1047 ( .A(n1167), .B(n750), .C(n1244), .Y(n1287) );
AOI22X2TS U1048 ( .A0(n532), .A1(n2540), .B0(n1122), .B1(n758), .Y(n2545) );
NAND2X2TS U1049 ( .A(n2056), .B(DmP[17]), .Y(n1986) );
NAND2X4TS U1050 ( .A(n921), .B(n1946), .Y(n938) );
INVX8TS U1051 ( .A(n1586), .Y(n2449) );
INVX6TS U1052 ( .A(n2219), .Y(n2236) );
INVX2TS U1053 ( .A(n997), .Y(n1913) );
INVX2TS U1054 ( .A(n1885), .Y(n1829) );
AND2X2TS U1055 ( .A(n2542), .B(n755), .Y(n1388) );
BUFX6TS U1056 ( .A(n1032), .Y(n921) );
OR2X6TS U1057 ( .A(n1644), .B(n861), .Y(n1485) );
AND2X2TS U1058 ( .A(n1587), .B(n1084), .Y(n1380) );
INVX4TS U1059 ( .A(n1275), .Y(n1483) );
NOR2BX2TS U1060 ( .AN(n2243), .B(n2802), .Y(n1224) );
NAND2X2TS U1061 ( .A(n758), .B(n960), .Y(n1980) );
BUFX3TS U1062 ( .A(n1929), .Y(n1542) );
CLKAND2X2TS U1063 ( .A(n1446), .B(Add_Subt_result[12]), .Y(n1663) );
OR2X4TS U1064 ( .A(n2282), .B(n1671), .Y(n1372) );
CLKINVX2TS U1065 ( .A(n2216), .Y(n2237) );
NAND2X6TS U1066 ( .A(n1494), .B(n1376), .Y(n1493) );
NOR2X1TS U1067 ( .A(n816), .B(r_mode[1]), .Y(n2095) );
NAND2X6TS U1068 ( .A(n2020), .B(n1362), .Y(n2022) );
OR3X2TS U1069 ( .A(n1253), .B(n1252), .C(n1251), .Y(n532) );
OAI21X1TS U1070 ( .A0(Add_Subt_result[1]), .A1(n1652), .B0(n2731), .Y(n1653)
);
NOR2X1TS U1071 ( .A(n817), .B(r_mode[0]), .Y(n2096) );
BUFX2TS U1072 ( .A(n1407), .Y(n878) );
BUFX3TS U1073 ( .A(n1375), .Y(n1534) );
CLKAND2X2TS U1074 ( .A(n1914), .B(n1222), .Y(n1221) );
INVX2TS U1075 ( .A(n2007), .Y(n942) );
CLKAND2X2TS U1076 ( .A(n2487), .B(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n1019) );
INVX1TS U1077 ( .A(ack_FSM), .Y(n1828) );
BUFX3TS U1078 ( .A(n1131), .Y(n1130) );
AOI22X2TS U1079 ( .A0(n1122), .A1(Add_Subt_result[23]), .B0(n1003), .B1(
n1279), .Y(n2247) );
NAND2X2TS U1080 ( .A(n1629), .B(n1628), .Y(n1623) );
NAND2X4TS U1081 ( .A(n1607), .B(n1024), .Y(n1023) );
NAND2BX2TS U1082 ( .AN(n989), .B(n858), .Y(n988) );
NAND2X1TS U1083 ( .A(n2043), .B(n1280), .Y(n1139) );
OR2X2TS U1084 ( .A(n1107), .B(n2767), .Y(n1526) );
OR3X4TS U1085 ( .A(n751), .B(n750), .C(n2763), .Y(n1312) );
NAND2X2TS U1086 ( .A(n959), .B(Add_Subt_result[4]), .Y(n1061) );
INVX2TS U1087 ( .A(n1540), .Y(n1109) );
BUFX8TS U1088 ( .A(n2056), .Y(n1003) );
NAND2X2TS U1089 ( .A(n2542), .B(Add_Subt_result[11]), .Y(n2077) );
OR2X2TS U1090 ( .A(n1492), .B(n733), .Y(n1344) );
BUFX4TS U1091 ( .A(n1566), .Y(n1298) );
NOR2X6TS U1092 ( .A(n2431), .B(n1065), .Y(n1586) );
NAND2X4TS U1093 ( .A(n1999), .B(n1009), .Y(n2426) );
NAND2XLTS U1094 ( .A(n2799), .B(n2759), .Y(n989) );
NAND2X2TS U1095 ( .A(n960), .B(Add_Subt_result[23]), .Y(n1984) );
NAND2X2TS U1096 ( .A(n2195), .B(n1645), .Y(n2196) );
BUFX4TS U1097 ( .A(n1160), .Y(n888) );
NAND2X2TS U1098 ( .A(n1446), .B(n751), .Y(n1190) );
NAND2X6TS U1099 ( .A(n1975), .B(n1974), .Y(n2581) );
NAND2X2TS U1100 ( .A(n959), .B(Add_Subt_result[7]), .Y(n1103) );
INVX4TS U1101 ( .A(n2261), .Y(n2273) );
NAND2X4TS U1102 ( .A(n1150), .B(n1153), .Y(n1147) );
NOR3X2TS U1103 ( .A(n1310), .B(n752), .C(n1284), .Y(n1650) );
OR2X2TS U1104 ( .A(n2216), .B(n1089), .Y(n1086) );
OR2X2TS U1105 ( .A(n1543), .B(Add_Subt_result[0]), .Y(n1345) );
AND2X4TS U1106 ( .A(n1680), .B(n2282), .Y(n2503) );
AND2X4TS U1107 ( .A(n951), .B(n1846), .Y(n1868) );
NAND2X4TS U1108 ( .A(n2262), .B(n1479), .Y(n1465) );
NAND2BX2TS U1109 ( .AN(n1668), .B(n750), .Y(n1129) );
INVX6TS U1110 ( .A(n1994), .Y(n1995) );
NOR2X2TS U1111 ( .A(n1107), .B(n1284), .Y(n1011) );
NAND2X2TS U1112 ( .A(n1122), .B(n1537), .Y(n1124) );
NOR2X2TS U1113 ( .A(n999), .B(n858), .Y(n996) );
INVX4TS U1114 ( .A(n1505), .Y(n1333) );
CLKINVX6TS U1115 ( .A(n1378), .Y(n1629) );
INVX12TS U1116 ( .A(n1983), .Y(n2640) );
NOR2X4TS U1117 ( .A(n2187), .B(n2268), .Y(n1047) );
INVX2TS U1118 ( .A(n2177), .Y(n1480) );
INVX2TS U1119 ( .A(n1107), .Y(n1128) );
INVX6TS U1120 ( .A(n1244), .Y(n751) );
INVX6TS U1121 ( .A(n1131), .Y(n2580) );
INVX2TS U1122 ( .A(n2252), .Y(n2254) );
OR2X6TS U1123 ( .A(n2483), .B(n1680), .Y(n1983) );
CLKINVX6TS U1124 ( .A(n1909), .Y(n2278) );
INVX6TS U1125 ( .A(n1667), .Y(n2540) );
INVX4TS U1126 ( .A(n1971), .Y(n2043) );
INVX8TS U1127 ( .A(n2602), .Y(n865) );
AOI22X2TS U1128 ( .A0(n1104), .A1(Add_Subt_result[3]), .B0(DmP[20]), .B1(
n1264), .Y(n1975) );
BUFX12TS U1129 ( .A(n854), .Y(n1122) );
AND2X4TS U1130 ( .A(n1021), .B(n1300), .Y(n1376) );
INVX2TS U1131 ( .A(n1089), .Y(n1088) );
NAND2X4TS U1132 ( .A(n1815), .B(n1816), .Y(n2255) );
INVX4TS U1133 ( .A(n1065), .Y(n2432) );
NAND2X4TS U1134 ( .A(n1210), .B(n2797), .Y(n949) );
OR2X1TS U1135 ( .A(n867), .B(n1106), .Y(n1105) );
NOR2X2TS U1136 ( .A(n789), .B(n1330), .Y(n1646) );
NOR2X2TS U1137 ( .A(n1864), .B(n1863), .Y(n1865) );
CLKINVX1TS U1138 ( .A(DmP[14]), .Y(n1126) );
NAND2X8TS U1139 ( .A(n2219), .B(n2177), .Y(n2268) );
INVX4TS U1140 ( .A(n2008), .Y(n1587) );
INVX6TS U1141 ( .A(n1914), .Y(n858) );
NAND2X1TS U1142 ( .A(n1825), .B(n1595), .Y(n2015) );
BUFX6TS U1143 ( .A(n2431), .Y(n1021) );
NAND3X4TS U1144 ( .A(n1210), .B(n1654), .C(n1655), .Y(n2276) );
NAND2X6TS U1145 ( .A(n1036), .B(n1523), .Y(n2215) );
INVX4TS U1146 ( .A(n1659), .Y(n999) );
NOR2X6TS U1147 ( .A(n2190), .B(n2204), .Y(n2267) );
NAND2X6TS U1148 ( .A(n1908), .B(n1906), .Y(n1909) );
CLKAND2X2TS U1149 ( .A(n1820), .B(DmP[30]), .Y(n1821) );
BUFX3TS U1150 ( .A(n1237), .Y(n789) );
XOR2X1TS U1151 ( .A(intDY[3]), .B(n1271), .Y(n1835) );
NAND2X4TS U1152 ( .A(n1814), .B(n1813), .Y(n2019) );
INVX6TS U1153 ( .A(n2282), .Y(n2483) );
XNOR2X1TS U1154 ( .A(intDY[10]), .B(intDX[10]), .Y(n1833) );
NAND2X4TS U1155 ( .A(n1382), .B(n2272), .Y(n2185) );
XNOR2X1TS U1156 ( .A(n788), .B(intDX[2]), .Y(n1834) );
INVX2TS U1157 ( .A(n1886), .Y(n1882) );
NAND2X4TS U1158 ( .A(n1811), .B(n1665), .Y(n1671) );
NOR2X6TS U1159 ( .A(n2178), .B(n2179), .Y(n2204) );
NAND2X6TS U1160 ( .A(n1666), .B(n1809), .Y(n2282) );
INVX6TS U1161 ( .A(n2014), .Y(n1509) );
CLKINVX6TS U1162 ( .A(n2159), .Y(n1555) );
INVX2TS U1163 ( .A(n2233), .Y(n1558) );
NAND2X4TS U1164 ( .A(n2184), .B(n2183), .Y(n2272) );
AND2X4TS U1165 ( .A(n2164), .B(n2163), .Y(n2228) );
BUFX8TS U1166 ( .A(n2014), .Y(n782) );
XNOR2X1TS U1167 ( .A(intDY[13]), .B(n1309), .Y(n1836) );
XNOR2X1TS U1168 ( .A(intDY[7]), .B(n1236), .Y(n1832) );
XNOR2X1TS U1169 ( .A(intDY[23]), .B(n1327), .Y(n1857) );
XNOR2X1TS U1170 ( .A(intDY[5]), .B(n1304), .Y(n1831) );
INVX4TS U1171 ( .A(n2098), .Y(n1997) );
XNOR2X2TS U1172 ( .A(intDY[27]), .B(intDX[27]), .Y(n1849) );
XNOR2X2TS U1173 ( .A(intDY[17]), .B(intDX[17]), .Y(n1859) );
XNOR2X2TS U1174 ( .A(intDY[24]), .B(intDX[24]), .Y(n1856) );
XNOR2X2TS U1175 ( .A(intDY[11]), .B(intDX[11]), .Y(n1842) );
NAND2X2TS U1176 ( .A(n1161), .B(n2147), .Y(n965) );
XNOR2X2TS U1177 ( .A(n2315), .B(intDX[25]), .Y(n1847) );
XNOR2X1TS U1178 ( .A(intDY[30]), .B(intDX[30]), .Y(n1850) );
XNOR2X1TS U1179 ( .A(intDY[14]), .B(intDX[14]), .Y(n1843) );
INVX12TS U1180 ( .A(n1035), .Y(n2177) );
NAND2X4TS U1181 ( .A(n1374), .B(n1639), .Y(n2168) );
INVX12TS U1182 ( .A(n1104), .Y(n1009) );
NAND3X4TS U1183 ( .A(n1906), .B(n1914), .C(n1660), .Y(n1111) );
NAND2X6TS U1184 ( .A(n1472), .B(n2195), .Y(n1241) );
NAND2X2TS U1185 ( .A(n2162), .B(n2161), .Y(n2240) );
OR2X2TS U1186 ( .A(n821), .B(n1822), .Y(n933) );
NAND2X6TS U1187 ( .A(n1870), .B(n1368), .Y(n1885) );
INVX3TS U1188 ( .A(n2149), .Y(n1475) );
NAND2X6TS U1189 ( .A(n1953), .B(n923), .Y(n1616) );
NOR2X6TS U1190 ( .A(n1296), .B(n1291), .Y(n2098) );
NAND2X2TS U1191 ( .A(n1950), .B(n1949), .Y(n2147) );
INVX6TS U1192 ( .A(n2176), .Y(n1076) );
INVX2TS U1193 ( .A(n893), .Y(n1291) );
OR2X6TS U1194 ( .A(n2166), .B(n2165), .Y(n1374) );
AND2X6TS U1195 ( .A(n1943), .B(n1944), .Y(n1945) );
OAI2BB1X2TS U1196 ( .A0N(n868), .A1N(n2739), .B0(n1600), .Y(n1599) );
INVX4TS U1197 ( .A(n2148), .Y(n1951) );
CLKAND2X2TS U1198 ( .A(n1635), .B(intDX[30]), .Y(n1778) );
NOR2X4TS U1199 ( .A(n1331), .B(n893), .Y(n1870) );
NAND2X4TS U1200 ( .A(n1820), .B(n1226), .Y(n1806) );
INVX2TS U1201 ( .A(n2665), .Y(n1164) );
NAND2X2TS U1202 ( .A(n2175), .B(n2174), .Y(n2200) );
NOR2X6TS U1203 ( .A(n1037), .B(n1606), .Y(n1160) );
OAI21X2TS U1204 ( .A0(n1758), .A1(n1487), .B0(n1486), .Y(n1764) );
NAND2X6TS U1205 ( .A(n1744), .B(n1774), .Y(n1747) );
INVX2TS U1206 ( .A(n1595), .Y(n1602) );
NAND2BX2TS U1207 ( .AN(n808), .B(n860), .Y(n1083) );
CLKINVX1TS U1208 ( .A(n820), .Y(n821) );
NAND2X1TS U1209 ( .A(n2775), .B(n1327), .Y(n1759) );
BUFX3TS U1210 ( .A(n1295), .Y(n883) );
INVX4TS U1211 ( .A(n2158), .Y(n1477) );
CLKMX2X4TS U1212 ( .A(Sgf_normalized_result[19]), .B(DMP[17]), .S0(n1633),
.Y(n2161) );
MX2X2TS U1213 ( .A(Sgf_normalized_result[21]), .B(DMP[19]), .S0(n1293), .Y(
n2165) );
NAND2X2TS U1214 ( .A(n2794), .B(n1305), .Y(n1487) );
CLKMX2X4TS U1215 ( .A(Sgf_normalized_result[20]), .B(DMP[18]), .S0(n1293),
.Y(n2163) );
OR2X4TS U1216 ( .A(n1234), .B(intDY[24]), .Y(n1768) );
OR2X4TS U1217 ( .A(n1635), .B(intDX[30]), .Y(n1779) );
NOR2X6TS U1218 ( .A(n1944), .B(n1943), .Y(n2667) );
CLKMX2X2TS U1219 ( .A(Sgf_normalized_result[24]), .B(DMP[22]), .S0(n1293),
.Y(n2183) );
NAND2X2TS U1220 ( .A(n2776), .B(n809), .Y(n1486) );
NOR2X2TS U1221 ( .A(n1742), .B(n1769), .Y(n1744) );
NOR2X4TS U1222 ( .A(n1536), .B(n1585), .Y(n1055) );
CLKINVX1TS U1223 ( .A(n807), .Y(n808) );
INVX6TS U1224 ( .A(n1642), .Y(n1037) );
CLKMX2X4TS U1225 ( .A(Sgf_normalized_result[13]), .B(DMP[11]), .S0(n1293),
.Y(n1949) );
INVX2TS U1226 ( .A(n2173), .Y(n1471) );
NOR2X4TS U1227 ( .A(n2775), .B(n1327), .Y(n1761) );
CLKMX2X4TS U1228 ( .A(Sgf_normalized_result[10]), .B(DMP[8]), .S0(n1633),
.Y(n1939) );
CLKMX2X4TS U1229 ( .A(Sgf_normalized_result[9]), .B(DMP[7]), .S0(n1633), .Y(
n1938) );
INVX6TS U1230 ( .A(n2457), .Y(n864) );
INVX4TS U1231 ( .A(n2793), .Y(n2315) );
CLKMX2X4TS U1232 ( .A(Sgf_normalized_result[12]), .B(DMP[10]), .S0(n1293),
.Y(n1943) );
CLKMX2X2TS U1233 ( .A(Sgf_normalized_result[14]), .B(DMP[12]), .S0(n1292),
.Y(n2169) );
INVX4TS U1234 ( .A(n1283), .Y(n1284) );
INVX3TS U1235 ( .A(n1822), .Y(n860) );
NOR2X6TS U1236 ( .A(n2776), .B(n809), .Y(n1758) );
CLKINVX2TS U1237 ( .A(n2174), .Y(n1470) );
NOR2X2TS U1238 ( .A(n1556), .B(n2749), .Y(n2156) );
NOR2X4TS U1239 ( .A(n912), .B(n892), .Y(n1585) );
INVX3TS U1240 ( .A(n1300), .Y(n1064) );
INVX4TS U1241 ( .A(n2459), .Y(n929) );
OR2X6TS U1242 ( .A(intDY[0]), .B(n1411), .Y(n1268) );
BUFX6TS U1243 ( .A(n1292), .Y(n1293) );
CLKMX2X4TS U1244 ( .A(n1417), .B(DMP[4]), .S0(n1633), .Y(n1930) );
NOR2X4TS U1245 ( .A(n2771), .B(intDX[14]), .Y(n1715) );
MX2X2TS U1246 ( .A(Sgf_normalized_result[16]), .B(DMP[14]), .S0(n1633), .Y(
n2173) );
INVX2TS U1247 ( .A(n1557), .Y(n1935) );
INVX4TS U1248 ( .A(n1922), .Y(n1193) );
INVX4TS U1249 ( .A(n1921), .Y(n1529) );
OR2X4TS U1250 ( .A(n2754), .B(n1541), .Y(n1285) );
INVX8TS U1251 ( .A(n2827), .Y(n983) );
NOR2X2TS U1252 ( .A(n2756), .B(n1541), .Y(n1404) );
OR2X4TS U1253 ( .A(n2755), .B(n1934), .Y(n1038) );
OR2X4TS U1254 ( .A(intDY[2]), .B(n1299), .Y(n1695) );
NOR2X6TS U1255 ( .A(n2780), .B(n1236), .Y(n1707) );
NOR2X2TS U1256 ( .A(n1274), .B(n2394), .Y(n2414) );
OR2X4TS U1257 ( .A(intDY[1]), .B(n1308), .Y(n1692) );
CLKINVX3TS U1258 ( .A(n1923), .Y(n1192) );
NOR2X4TS U1259 ( .A(n1541), .B(n1933), .Y(n1402) );
BUFX4TS U1260 ( .A(n1307), .Y(n1297) );
NAND2X4TS U1261 ( .A(n1054), .B(n1053), .Y(n1923) );
OR2X4TS U1262 ( .A(n2744), .B(n1556), .Y(n1278) );
OR2X4TS U1263 ( .A(n2404), .B(n918), .Y(n1638) );
NOR2X2TS U1264 ( .A(n1274), .B(n1934), .Y(n1565) );
BUFX8TS U1265 ( .A(n1033), .Y(n917) );
NAND2X2TS U1266 ( .A(n1262), .B(n1269), .Y(n1053) );
INVX2TS U1267 ( .A(n1318), .Y(n1319) );
INVX8TS U1268 ( .A(n1415), .Y(n1031) );
NAND2X4TS U1269 ( .A(n1926), .B(n1925), .Y(n2601) );
INVX16TS U1270 ( .A(n1197), .Y(n1356) );
NAND2X6TS U1271 ( .A(n963), .B(n1630), .Y(n962) );
NAND2X4TS U1272 ( .A(n2474), .B(n2528), .Y(n2479) );
NAND4X2TS U1273 ( .A(n1843), .B(n1842), .C(n1841), .D(n1840), .Y(n1844) );
OR2X8TS U1274 ( .A(n2449), .B(n2426), .Y(n2434) );
INVX16TS U1275 ( .A(n1492), .Y(n960) );
NAND3X6TS U1276 ( .A(n2371), .B(n2372), .C(n2373), .Y(n569) );
NAND4X2TS U1277 ( .A(n2473), .B(n2472), .C(n2471), .D(n2470), .Y(n716) );
NAND3X6TS U1278 ( .A(n2297), .B(n2298), .C(n2299), .Y(n537) );
NAND2X4TS U1279 ( .A(n911), .B(intDX[8]), .Y(n2299) );
NAND4X4TS U1280 ( .A(n2035), .B(n2034), .C(n2033), .D(n2032), .Y(n720) );
NOR4X4TS U1281 ( .A(n1287), .B(n1215), .C(n1216), .D(n848), .Y(n1214) );
NAND3X4TS U1282 ( .A(n2285), .B(n2284), .C(n2283), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI2BB2X2TS U1283 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[36]),
.B1(n2509), .A0N(n2508), .A1N(n2729), .Y(n2497) );
NAND2X8TS U1284 ( .A(n2487), .B(n2528), .Y(n2508) );
NAND4X4TS U1285 ( .A(n1850), .B(n1849), .C(n1848), .D(n1847), .Y(n1854) );
XNOR2X2TS U1286 ( .A(intDY[28]), .B(n801), .Y(n1848) );
BUFX20TS U1287 ( .A(n2541), .Y(n959) );
BUFX20TS U1288 ( .A(n2541), .Y(n1446) );
OR2X4TS U1289 ( .A(n2583), .B(n2516), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
MX2X4TS U1290 ( .A(n1339), .B(exp_oper_result[0]), .S0(n1442), .Y(n699) );
AOI22X2TS U1291 ( .A0(n2475), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n2554), .B1(
Sgf_normalized_result[8]), .Y(n2531) );
NAND3X8TS U1292 ( .A(n1891), .B(n1059), .C(n1140), .Y(n1201) );
NAND2X2TS U1293 ( .A(n2487), .B(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1070) );
NAND4X2TS U1294 ( .A(n2430), .B(n2429), .C(n2428), .D(n2427), .Y(n704) );
NAND4X4TS U1295 ( .A(n2623), .B(n2622), .C(n2621), .D(n2620), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
MXI2X8TS U1296 ( .A(n2518), .B(n1982), .S0(n2580), .Y(n2579) );
NAND2X4TS U1297 ( .A(n971), .B(intDY[10]), .Y(n2350) );
NAND3X4TS U1298 ( .A(n2600), .B(n2599), .C(n2598), .Y(n555) );
NOR3X6TS U1299 ( .A(n956), .B(n955), .C(n954), .Y(n953) );
NAND3X6TS U1300 ( .A(n1875), .B(n1873), .C(n1874), .Y(n556) );
NAND3X6TS U1301 ( .A(n2092), .B(n2090), .C(n2091), .Y(n558) );
AOI22X2TS U1302 ( .A0(n836), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n2573), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .Y(n2498) );
NAND4X4TS U1303 ( .A(n2443), .B(n2442), .C(n2441), .D(n2440), .Y(n715) );
NAND2X4TS U1304 ( .A(n2356), .B(n907), .Y(n573) );
NAND4X8TS U1305 ( .A(n1679), .B(n1678), .C(n1677), .D(n1676), .Y(n2625) );
BUFX16TS U1306 ( .A(n1353), .Y(n794) );
NAND2X4TS U1307 ( .A(n1201), .B(n2637), .Y(n1903) );
NAND2X2TS U1308 ( .A(n2631), .B(n2589), .Y(n2595) );
NAND3X4TS U1309 ( .A(n2086), .B(n2085), .C(n2084), .Y(n534) );
NAND4X4TS U1310 ( .A(n1890), .B(n1889), .C(n1888), .D(n1887), .Y(n719) );
NAND2X4TS U1311 ( .A(n2523), .B(n1994), .Y(n1890) );
NAND4X2TS U1312 ( .A(n1839), .B(n1838), .C(n1837), .D(n1836), .Y(n1845) );
NAND3X6TS U1313 ( .A(n2143), .B(n2142), .C(n2141), .Y(n563) );
NAND2X4TS U1314 ( .A(n1017), .B(n788), .Y(n2143) );
NAND2BX4TS U1315 ( .AN(n2522), .B(n2521), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OR2X8TS U1316 ( .A(n2444), .B(n2452), .Y(n2464) );
OR2X8TS U1317 ( .A(n2439), .B(n2452), .Y(n2469) );
OR2X8TS U1318 ( .A(n2451), .B(n2452), .Y(n2474) );
AOI21X4TS U1319 ( .A0(n2572), .A1(Sgf_normalized_result[16]), .B0(n2452),
.Y(n1889) );
NAND4X6TS U1320 ( .A(n2567), .B(n2566), .C(n2565), .D(n2564), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
INVX16TS U1321 ( .A(n1668), .Y(n2542) );
INVX16TS U1322 ( .A(n2434), .Y(n2509) );
NAND3X4TS U1323 ( .A(n2527), .B(n2526), .C(n2525), .Y(n712) );
NAND3X6TS U1324 ( .A(n2134), .B(n2133), .C(n2132), .Y(n576) );
NAND3X4TS U1325 ( .A(n2104), .B(n2103), .C(n2102), .Y(n572) );
NAND2X4TS U1326 ( .A(n1357), .B(n1239), .Y(n2297) );
NAND2X4TS U1327 ( .A(n1357), .B(intDX[8]), .Y(n2371) );
OR3X4TS U1328 ( .A(n2507), .B(n2583), .C(n2506), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
CLKINVX6TS U1329 ( .A(n2025), .Y(n947) );
NAND2X2TS U1330 ( .A(n2615), .B(n2589), .Y(n2054) );
NAND2X2TS U1331 ( .A(n2615), .B(n1443), .Y(n2596) );
OAI21X4TS U1332 ( .A0(n2106), .A1(n2871), .B0(n2105), .Y(n559) );
AOI22X4TS U1333 ( .A0(n1122), .A1(Add_Subt_result[12]), .B0(n2056), .B1(
DmP[11]), .Y(n1679) );
NAND2X4TS U1334 ( .A(n2540), .B(DmP[19]), .Y(n1525) );
AOI21X2TS U1335 ( .A0(n1187), .A1(n1973), .B0(n862), .Y(n1184) );
CLKINVX12TS U1336 ( .A(n862), .Y(n1443) );
AOI22X2TS U1337 ( .A0(n1020), .A1(n1283), .B0(n1003), .B1(DmP[9]), .Y(n1670)
);
NAND2X4TS U1338 ( .A(n2529), .B(n2528), .Y(n2532) );
NAND2X4TS U1339 ( .A(n2556), .B(n1994), .Y(n2558) );
NAND2X8TS U1340 ( .A(n960), .B(n1092), .Y(n1974) );
NAND4X8TS U1341 ( .A(n1989), .B(n1988), .C(n1987), .D(n1986), .Y(n2585) );
MX2X4TS U1342 ( .A(Data_X[25]), .B(intDX[25]), .S0(n1447), .Y(n650) );
NAND3X6TS U1343 ( .A(n2089), .B(n2088), .C(n2087), .Y(n533) );
BUFX20TS U1344 ( .A(n854), .Y(n1020) );
INVX16TS U1345 ( .A(n1543), .Y(n1104) );
NAND2X4TS U1346 ( .A(n2464), .B(n1994), .Y(n2448) );
NAND2X8TS U1347 ( .A(n1326), .B(n1134), .Y(n2642) );
NOR2X8TS U1348 ( .A(n1136), .B(n1135), .Y(n1134) );
OR2X4TS U1349 ( .A(n2485), .B(n2583), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
AND4X8TS U1350 ( .A(n2245), .B(n2247), .C(n2244), .D(n2246), .Y(n1008) );
NAND4BBX4TS U1351 ( .AN(n1365), .BN(n1495), .C(n2492), .D(n2491), .Y(n707)
);
INVX16TS U1352 ( .A(n1195), .Y(n1131) );
INVX16TS U1353 ( .A(n950), .Y(n1195) );
NAND2X4TS U1354 ( .A(n1097), .B(n1096), .Y(n730) );
NAND2X8TS U1355 ( .A(n1166), .B(n1169), .Y(n2028) );
INVX16TS U1356 ( .A(n1265), .Y(n2573) );
INVX12TS U1357 ( .A(n1093), .Y(n1210) );
NAND2X4TS U1358 ( .A(n776), .B(n1260), .Y(n2356) );
NAND3X6TS U1359 ( .A(n985), .B(n994), .C(n986), .Y(n1918) );
MX2X4TS U1360 ( .A(n2658), .B(Add_Subt_result[8]), .S0(n2848), .Y(n742) );
NAND2X4TS U1361 ( .A(n1350), .B(intDX[24]), .Y(n2362) );
NAND3X6TS U1362 ( .A(n2279), .B(n2280), .C(n1385), .Y(n1099) );
OR2X8TS U1363 ( .A(n1687), .B(n1548), .Y(n1385) );
NAND3X6TS U1364 ( .A(n2374), .B(n2375), .C(n2376), .Y(n566) );
NAND2X4TS U1365 ( .A(n794), .B(n1304), .Y(n2374) );
INVX12TS U1366 ( .A(n1614), .Y(n1613) );
NOR4X4TS U1367 ( .A(n1854), .B(n1853), .C(n1852), .D(n1851), .Y(n1866) );
NAND4X8TS U1368 ( .A(n1895), .B(n1360), .C(n1893), .D(n1894), .Y(n2561) );
NAND2X8TS U1369 ( .A(n2382), .B(n779), .Y(n564) );
NAND2X8TS U1370 ( .A(n1543), .B(n867), .Y(n1492) );
INVX16TS U1371 ( .A(n862), .Y(n2614) );
NAND2X4TS U1372 ( .A(n794), .B(intDY[26]), .Y(n2598) );
AND2X8TS U1373 ( .A(n2378), .B(n2379), .Y(n1384) );
NAND2X4TS U1374 ( .A(n1017), .B(intDY[9]), .Y(n2379) );
NAND2X8TS U1375 ( .A(n1087), .B(n1086), .Y(n1614) );
NAND2X4TS U1376 ( .A(n911), .B(intDY[24]), .Y(n2364) );
NAND2X2TS U1377 ( .A(n911), .B(intDY[18]), .Y(n2347) );
NAND3X6TS U1378 ( .A(n1230), .B(n2075), .C(n1231), .Y(n550) );
NAND3X4TS U1379 ( .A(n2114), .B(n2115), .C(n2116), .Y(n547) );
NAND3X6TS U1380 ( .A(n2318), .B(n2317), .C(n2316), .Y(n554) );
NAND2X4TS U1381 ( .A(n776), .B(n2315), .Y(n2316) );
NAND3BX4TS U1382 ( .AN(n818), .B(n1801), .C(n1800), .Y(n586) );
NAND2X4TS U1383 ( .A(n781), .B(intDX[15]), .Y(n2132) );
BUFX20TS U1384 ( .A(n1355), .Y(n781) );
NAND2X8TS U1385 ( .A(n1524), .B(n1004), .Y(n1186) );
NAND2X4TS U1386 ( .A(n776), .B(intDY[4]), .Y(n2087) );
BUFX20TS U1387 ( .A(n1351), .Y(n776) );
BUFX20TS U1388 ( .A(n972), .Y(n971) );
NAND3X4TS U1389 ( .A(n2117), .B(n2118), .C(n2119), .Y(n549) );
NAND2X4TS U1390 ( .A(n859), .B(n1305), .Y(n2117) );
AND2X6TS U1391 ( .A(n1352), .B(intDX[29]), .Y(n1232) );
NAND3X6TS U1392 ( .A(n1036), .B(n1523), .C(n1088), .Y(n1087) );
NAND2X6TS U1393 ( .A(n859), .B(intDX[15]), .Y(n2331) );
BUFX20TS U1394 ( .A(n2093), .Y(n2848) );
NAND2X4TS U1395 ( .A(n1358), .B(intDY[29]), .Y(n2090) );
AOI2BB2X2TS U1396 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[35]),
.B1(n2499), .A0N(n2508), .A1N(n2723), .Y(n2494) );
AOI2BB2X4TS U1397 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[34]),
.B1(n2499), .A0N(n2508), .A1N(n2764), .Y(n2492) );
AOI2BB2X2TS U1398 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[37]),
.B1(n2499), .A0N(n2508), .A1N(n2722), .Y(n2501) );
NAND2X4TS U1399 ( .A(n1355), .B(intDY[27]), .Y(n1873) );
INVX16TS U1400 ( .A(n1197), .Y(n1355) );
AOI22X2TS U1401 ( .A0(n2555), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(n2554), .B1(
Sgf_normalized_result[21]), .Y(n2002) );
AOI22X2TS U1402 ( .A0(n2475), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n2555), .B1(n1452), .Y(n2490) );
AOI22X2TS U1403 ( .A0(n2555), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n2554), .B1(
Sgf_normalized_result[24]), .Y(n2559) );
AOI22X2TS U1404 ( .A0(n2555), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n2572), .B1(
Sgf_normalized_result[19]), .Y(n2005) );
NAND3X6TS U1405 ( .A(n2355), .B(n2354), .C(n2353), .Y(n577) );
NAND2X6TS U1406 ( .A(n778), .B(n795), .Y(n2353) );
NAND3X6TS U1407 ( .A(n2425), .B(n2424), .C(n2423), .Y(n2556) );
NAND2BX4TS U1408 ( .AN(n1066), .B(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .Y(n2425) );
NAND3X6TS U1409 ( .A(n2131), .B(n2130), .C(n2129), .Y(n580) );
NAND2X6TS U1410 ( .A(n781), .B(n1301), .Y(n2129) );
NAND2X4TS U1411 ( .A(intDY[13]), .B(n1233), .Y(n2146) );
NAND2X4TS U1412 ( .A(n1233), .B(intDX[27]), .Y(n1875) );
NAND2X4TS U1413 ( .A(n1233), .B(intDX[29]), .Y(n2092) );
NAND2X6TS U1414 ( .A(n1040), .B(n1947), .Y(n939) );
INVX6TS U1415 ( .A(n800), .Y(n2330) );
NAND2X4TS U1416 ( .A(n1044), .B(n1028), .Y(n1561) );
BUFX12TS U1417 ( .A(n1353), .Y(n775) );
NAND2X4TS U1418 ( .A(n2377), .B(n1384), .Y(n570) );
NAND2X8TS U1419 ( .A(n1155), .B(n1937), .Y(n2656) );
NAND2X2TS U1420 ( .A(n1350), .B(n1236), .Y(n2138) );
NAND3X6TS U1421 ( .A(n2138), .B(n2139), .C(n2140), .Y(n568) );
OR2X8TS U1422 ( .A(n1568), .B(n1930), .Y(n1375) );
NAND2X8TS U1423 ( .A(n1535), .B(n1932), .Y(n1958) );
INVX12TS U1424 ( .A(n1413), .Y(n1601) );
AND2X8TS U1425 ( .A(n1433), .B(intDY[20]), .Y(n803) );
NAND2X2TS U1426 ( .A(n1349), .B(n885), .Y(n2072) );
OAI22X2TS U1427 ( .A0(n2450), .A1(n2760), .B0(n2449), .B1(n2722), .Y(n2451)
);
OAI22X4TS U1428 ( .A0(n1910), .A1(n1909), .B0(n1908), .B1(n1907), .Y(n1917)
);
AND2X4TS U1429 ( .A(n1350), .B(intDY[3]), .Y(n1277) );
NAND4X4TS U1430 ( .A(n2479), .B(n2478), .C(n2477), .D(n2476), .Y(n718) );
AND2X8TS U1431 ( .A(n1288), .B(n1375), .Y(n1389) );
BUFX12TS U1432 ( .A(n1356), .Y(n778) );
CLKINVX2TS U1433 ( .A(n2651), .Y(n2652) );
INVX16TS U1434 ( .A(n1288), .Y(n1407) );
NAND2X4TS U1435 ( .A(n971), .B(intDY[15]), .Y(n2134) );
NAND2X4TS U1436 ( .A(n1433), .B(intDY[1]), .Y(n2613) );
NAND3X6TS U1437 ( .A(n2613), .B(n2612), .C(n2611), .Y(n562) );
NAND2X4TS U1438 ( .A(n971), .B(n1304), .Y(n2086) );
NAND2X6TS U1439 ( .A(n2786), .B(intDX[10]), .Y(n1723) );
NOR2X8TS U1440 ( .A(n1541), .B(n1314), .Y(n1570) );
AND2X8TS U1441 ( .A(n1433), .B(n1309), .Y(n800) );
AND2X8TS U1442 ( .A(n2380), .B(n2381), .Y(n779) );
NAND3BX4TS U1443 ( .AN(n802), .B(n1876), .C(n1877), .Y(n557) );
INVX6TS U1444 ( .A(n1810), .Y(n1159) );
NAND2X8TS U1445 ( .A(n780), .B(n2251), .Y(n1580) );
NAND2X8TS U1446 ( .A(n797), .B(n1510), .Y(n780) );
NAND2X8TS U1447 ( .A(n1031), .B(n1030), .Y(n1033) );
INVX12TS U1448 ( .A(n2872), .Y(n1030) );
BUFX12TS U1449 ( .A(n918), .Y(n784) );
NAND2X6TS U1450 ( .A(n1701), .B(n1709), .Y(n1712) );
NOR2X8TS U1451 ( .A(n1700), .B(n1707), .Y(n1709) );
OAI21X4TS U1452 ( .A0(n852), .A1(n2837), .B0(n785), .Y(n695) );
NAND2X6TS U1453 ( .A(n2837), .B(n2838), .Y(n785) );
NAND2X6TS U1454 ( .A(n2837), .B(n2838), .Y(n1072) );
NAND2X8TS U1455 ( .A(n786), .B(n1331), .Y(n902) );
NAND2X8TS U1456 ( .A(n792), .B(n1146), .Y(n786) );
NAND2X4TS U1457 ( .A(n1357), .B(intDY[6]), .Y(n2305) );
NOR2X8TS U1458 ( .A(n1067), .B(n2432), .Y(n2487) );
AND2X8TS U1459 ( .A(n1354), .B(intDX[25]), .Y(n818) );
OAI2BB1X4TS U1460 ( .A0N(n1235), .A1N(n1822), .B0(n1083), .Y(n1085) );
NAND3X6TS U1461 ( .A(n2364), .B(n2362), .C(n2363), .Y(n585) );
NAND2X4TS U1462 ( .A(n1433), .B(n1297), .Y(n2109) );
NAND3BX4TS U1463 ( .AN(n787), .B(n2433), .C(n1070), .Y(n2550) );
NAND2X2TS U1464 ( .A(n775), .B(intDY[9]), .Y(n2325) );
NAND2X8TS U1465 ( .A(n973), .B(n974), .Y(n1788) );
BUFX6TS U1466 ( .A(intDY[2]), .Y(n788) );
INVX12TS U1467 ( .A(n1630), .Y(n1039) );
NAND2X8TS U1468 ( .A(n1615), .B(n1616), .Y(n1630) );
INVX16TS U1469 ( .A(n1197), .Y(n1358) );
INVX8TS U1470 ( .A(n793), .Y(n792) );
NOR2X6TS U1471 ( .A(n1772), .B(n1743), .Y(n1774) );
NAND2X6TS U1472 ( .A(n1597), .B(n2021), .Y(n1575) );
NAND2X2TS U1473 ( .A(n1356), .B(n791), .Y(n2380) );
NAND2X4TS U1474 ( .A(n1358), .B(intDY[10]), .Y(n2311) );
NAND3X6TS U1475 ( .A(n2309), .B(n2310), .C(n2311), .Y(n539) );
NAND2X2TS U1476 ( .A(n775), .B(n809), .Y(n2126) );
CLKBUFX2TS U1477 ( .A(intDX[3]), .Y(n791) );
NOR2X6TS U1478 ( .A(n1704), .B(n1699), .Y(n1701) );
NAND2X8TS U1479 ( .A(n1325), .B(n1328), .Y(n793) );
NAND2X8TS U1480 ( .A(n1002), .B(n1810), .Y(n950) );
INVX16TS U1481 ( .A(n1528), .Y(n1820) );
NAND2X8TS U1482 ( .A(n1202), .B(n1601), .Y(n1528) );
NAND2X4TS U1483 ( .A(n1434), .B(intDY[23]), .Y(n2137) );
AOI2BB2X4TS U1484 ( .B0(n2076), .B1(DmP[6]), .A0N(n1107), .A1N(n1244), .Y(
n1892) );
OAI2BB1X4TS U1485 ( .A0N(n1691), .A1N(n2395), .B0(n1690), .Y(n729) );
NAND2X4TS U1486 ( .A(n1349), .B(n1297), .Y(n2611) );
INVX6TS U1487 ( .A(n1057), .Y(n1034) );
NOR2X6TS U1488 ( .A(n1766), .B(n1753), .Y(n1754) );
NAND2X8TS U1489 ( .A(n1045), .B(n1084), .Y(n1275) );
NOR2X8TS U1490 ( .A(n796), .B(n2602), .Y(n923) );
NAND3X8TS U1491 ( .A(n2603), .B(n1375), .C(n1288), .Y(n796) );
NOR2X8TS U1492 ( .A(n2781), .B(intDX[29]), .Y(n1777) );
CLKINVX12TS U1493 ( .A(n1074), .Y(n1523) );
NAND3X8TS U1494 ( .A(n1597), .B(n1819), .C(n2021), .Y(n797) );
NOR2X4TS U1495 ( .A(n2743), .B(n1556), .Y(n1478) );
OAI21X4TS U1496 ( .A0(n2202), .A1(n2269), .B0(n1466), .Y(n2270) );
NAND2X4TS U1497 ( .A(intDY[22]), .B(n783), .Y(n2125) );
NAND3X6TS U1498 ( .A(n2125), .B(n2124), .C(n2123), .Y(n583) );
NAND2X4TS U1499 ( .A(n911), .B(n1301), .Y(n2339) );
BUFX4TS U1500 ( .A(n1455), .Y(n1167) );
XOR2X4TS U1501 ( .A(n1341), .B(n2022), .Y(n798) );
AND2X8TS U1502 ( .A(intDY[27]), .B(n799), .Y(n1772) );
NOR2X6TS U1503 ( .A(n1367), .B(n1594), .Y(n1049) );
AND2X4TS U1504 ( .A(n1626), .B(n1643), .Y(n1392) );
NAND2X8TS U1505 ( .A(n1643), .B(n1645), .Y(n2208) );
NAND3X6TS U1506 ( .A(n2146), .B(n2145), .C(n2144), .Y(n574) );
NAND2X4TS U1507 ( .A(n1350), .B(n1309), .Y(n2144) );
INVX4TS U1508 ( .A(n1604), .Y(n1603) );
NOR2X8TS U1509 ( .A(n1817), .B(n909), .Y(n2256) );
NAND2X4TS U1510 ( .A(n1358), .B(intDX[2]), .Y(n2141) );
NAND2X2TS U1511 ( .A(n930), .B(n2315), .Y(n1801) );
NAND3BX2TS U1512 ( .AN(n803), .B(n2351), .C(n2352), .Y(n581) );
AOI22X2TS U1513 ( .A0(n2573), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(n2572), .B1(
Sgf_normalized_result[20]), .Y(n2569) );
BUFX20TS U1514 ( .A(n972), .Y(n1434) );
NAND4X4TS U1515 ( .A(n2063), .B(n2064), .C(n2062), .D(n2061), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
NAND2X6TS U1516 ( .A(n849), .B(n2589), .Y(n2061) );
NAND3X8TS U1517 ( .A(n1976), .B(n1490), .C(n1978), .Y(n849) );
OR3X6TS U1518 ( .A(n810), .B(n805), .C(n806), .Y(n552) );
AND2X4TS U1519 ( .A(n1349), .B(intDY[23]), .Y(n806) );
INVX16TS U1520 ( .A(n906), .Y(n1353) );
INVX12TS U1521 ( .A(n2215), .Y(n2238) );
NAND3X4TS U1522 ( .A(n2337), .B(n2336), .C(n2335), .Y(n546) );
BUFX20TS U1523 ( .A(n972), .Y(n1433) );
MX2X4TS U1524 ( .A(n2419), .B(Add_Subt_result[1]), .S0(n1425), .Y(n735) );
XOR2X1TS U1525 ( .A(n2418), .B(n1027), .Y(n2419) );
NAND3X4TS U1526 ( .A(n2109), .B(n2108), .C(n2107), .Y(n530) );
AND2X4TS U1527 ( .A(n1017), .B(n1327), .Y(n810) );
NAND3BX2TS U1528 ( .AN(n811), .B(n2295), .C(n2296), .Y(n553) );
AND2X4TS U1529 ( .A(n1017), .B(intDX[24]), .Y(n811) );
NAND2X2TS U1530 ( .A(n1358), .B(intDY[5]), .Y(n2084) );
NAND3X4TS U1531 ( .A(n2339), .B(n2340), .C(n2341), .Y(n548) );
NOR2X6TS U1532 ( .A(n1693), .B(n1696), .Y(n1698) );
INVX8TS U1533 ( .A(n1825), .Y(n813) );
NAND2X4TS U1534 ( .A(n911), .B(intDX[10]), .Y(n2309) );
NAND4X4TS U1535 ( .A(n2468), .B(n2467), .C(n2466), .D(n2465), .Y(n717) );
NAND2X4TS U1536 ( .A(n2464), .B(n2528), .Y(n2468) );
NAND4X2TS U1537 ( .A(n2448), .B(n2447), .C(n2446), .D(n2445), .Y(n714) );
NOR2X8TS U1538 ( .A(n1590), .B(n1420), .Y(n1589) );
INVX4TS U1539 ( .A(n814), .Y(n815) );
INVX6TS U1540 ( .A(n961), .Y(n1621) );
NAND2X4TS U1541 ( .A(n1433), .B(intDY[29]), .Y(n1793) );
INVX4TS U1542 ( .A(n816), .Y(n817) );
NAND2X2TS U1543 ( .A(n1353), .B(intDY[22]), .Y(n2293) );
NAND2X2TS U1544 ( .A(n1353), .B(intDY[17]), .Y(n2337) );
NAND4X4TS U1545 ( .A(n2039), .B(n2038), .C(n2037), .D(n2036), .Y(n2631) );
INVX16TS U1546 ( .A(n890), .Y(n1377) );
XNOR2X4TS U1547 ( .A(n2253), .B(n1342), .Y(Exp_Operation_Module_Data_S[5])
);
BUFX12TS U1548 ( .A(n972), .Y(n1017) );
NAND3BX4TS U1549 ( .AN(n819), .B(n1804), .C(n1803), .Y(n531) );
AND2X4TS U1550 ( .A(n908), .B(intDX[2]), .Y(n819) );
XOR2X4TS U1551 ( .A(n1078), .B(n822), .Y(Add_Subt_Sgf_module_S_to_D[25]) );
NAND2X8TS U1552 ( .A(n1511), .B(n2013), .Y(n872) );
INVX8TS U1553 ( .A(n2012), .Y(n1362) );
BUFX16TS U1554 ( .A(n2847), .Y(n830) );
BUFX16TS U1555 ( .A(n2847), .Y(n1425) );
BUFX20TS U1556 ( .A(n2093), .Y(n2847) );
AOI2BB2X2TS U1557 ( .B0(n2076), .B1(DmP[16]), .A0N(n1107), .A1N(n2758), .Y(
n1674) );
AOI2BB2X2TS U1558 ( .B0(n2076), .B1(DmP[10]), .A0N(n2799), .A1N(n1107), .Y(
n2041) );
BUFX20TS U1559 ( .A(n1107), .Y(n1121) );
INVX16TS U1560 ( .A(n2640), .Y(n831) );
INVX12TS U1561 ( .A(n831), .Y(n832) );
INVX4TS U1562 ( .A(n831), .Y(n833) );
INVX2TS U1563 ( .A(n831), .Y(n834) );
INVX2TS U1564 ( .A(n831), .Y(n835) );
AOI22X2TS U1565 ( .A0(n2475), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .B0(n2554), .B1(
Sgf_normalized_result[9]), .Y(n2526) );
AOI22X2TS U1566 ( .A0(n836), .A1(n1346), .B0(n2571), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .Y(n2570) );
AOI22X2TS U1567 ( .A0(n2475), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n2524), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n2006) );
AO22X4TS U1568 ( .A0(n2475), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(n2573), .B1(n1450), .Y(n1365) );
NAND2X2TS U1569 ( .A(n836), .B(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .Y(n2477) );
NAND2X2TS U1570 ( .A(n2475), .B(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n2466) );
AOI2BB2X2TS U1571 ( .B0(n1445), .B1(n1144), .A0N(n2398), .A1N(
final_result_ieee[29]), .Y(n683) );
NAND3X4TS U1572 ( .A(n2312), .B(n2313), .C(n2314), .Y(n543) );
INVX2TS U1573 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[26]), .Y(n1071) );
INVX2TS U1574 ( .A(n1239), .Y(n1240) );
NOR2X4TS U1575 ( .A(n1721), .B(n1717), .Y(n1719) );
NAND2X4TS U1576 ( .A(n2262), .B(n2186), .Y(n1024) );
INVX2TS U1577 ( .A(n867), .Y(n1194) );
CLKMX2X4TS U1578 ( .A(Sgf_normalized_result[11]), .B(DMP[9]), .S0(n1633),
.Y(n1942) );
INVX2TS U1579 ( .A(n2821), .Y(n1205) );
OR2X2TS U1580 ( .A(n2205), .B(n1425), .Y(n1173) );
INVX2TS U1581 ( .A(n2268), .Y(n2203) );
NAND2X1TS U1582 ( .A(n1642), .B(n1266), .Y(n2657) );
NAND2X2TS U1583 ( .A(n1640), .B(n2240), .Y(n2241) );
NAND2X1TS U1584 ( .A(n2509), .B(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n2033) );
INVX2TS U1585 ( .A(n1307), .Y(n1308) );
NAND2X1TS U1586 ( .A(n2574), .B(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n2568) );
NAND2X1TS U1587 ( .A(n2597), .B(DmP[13]), .Y(n2329) );
NAND2X1TS U1588 ( .A(n2597), .B(DmP[25]), .Y(n2317) );
NAND2X1TS U1589 ( .A(n2585), .B(n2562), .Y(n2066) );
INVX2TS U1590 ( .A(n693), .Y(n1144) );
NAND2X2TS U1591 ( .A(n1491), .B(n2641), .Y(n2620) );
AND2X4TS U1592 ( .A(n1003), .B(DmP[15]), .Y(n847) );
NAND2X2TS U1593 ( .A(n2542), .B(Add_Subt_result[12]), .Y(n850) );
AND2X8TS U1594 ( .A(n1564), .B(n2167), .Y(n851) );
BUFX20TS U1595 ( .A(n930), .Y(n908) );
AND2X4TS U1596 ( .A(n1020), .B(Add_Subt_result[8]), .Y(n853) );
AND2X8TS U1597 ( .A(n1104), .B(n1195), .Y(n854) );
NAND2X6TS U1598 ( .A(n1296), .B(n1325), .Y(n1063) );
MX2X4TS U1599 ( .A(Data_X[17]), .B(intDX[17]), .S0(n1513), .Y(n642) );
NAND2X4TS U1600 ( .A(n859), .B(intDX[17]), .Y(n2335) );
NAND2X8TS U1601 ( .A(n1196), .B(n1200), .Y(n1199) );
NAND2X6TS U1602 ( .A(n1741), .B(n1740), .Y(n1200) );
NAND2X8TS U1603 ( .A(n1199), .B(n1198), .Y(n974) );
NAND2X4TS U1604 ( .A(n2790), .B(intDX[3]), .Y(n1694) );
NOR2X2TS U1605 ( .A(n1262), .B(n2747), .Y(n2152) );
NAND2X2TS U1606 ( .A(n1201), .B(n2591), .Y(n2248) );
NAND2X2TS U1607 ( .A(n2561), .B(n2562), .Y(n2549) );
NAND4X4TS U1608 ( .A(n1214), .B(n1218), .C(n1551), .D(n1549), .Y(n1212) );
INVX2TS U1609 ( .A(n878), .Y(n1270) );
INVX3TS U1610 ( .A(n2193), .Y(n1176) );
INVX2TS U1611 ( .A(n1892), .Y(n870) );
INVX3TS U1612 ( .A(n2643), .Y(n1954) );
AND2X6TS U1613 ( .A(n2192), .B(n2191), .Y(n2193) );
INVX2TS U1614 ( .A(n1952), .Y(n1323) );
NAND2X6TS U1615 ( .A(n969), .B(n1994), .Y(n2110) );
NAND2X4TS U1616 ( .A(n1595), .B(n1825), .Y(n1281) );
AND2X2TS U1617 ( .A(n2535), .B(DmP[30]), .Y(n1228) );
INVX3TS U1618 ( .A(n949), .Y(n948) );
INVX4TS U1619 ( .A(n2276), .Y(n968) );
INVX3TS U1620 ( .A(n1945), .Y(n937) );
INVX2TS U1621 ( .A(n1210), .Y(n1108) );
OR3X4TS U1622 ( .A(n1500), .B(n1499), .C(n1498), .Y(n1369) );
BUFX20TS U1623 ( .A(n913), .Y(n857) );
NAND2X4TS U1624 ( .A(n1157), .B(n1156), .Y(n1642) );
AOI21X2TS U1625 ( .A0(n1661), .A1(n1243), .B0(Add_Subt_result[23]), .Y(n1662) );
NAND2X1TS U1626 ( .A(n2395), .B(n1316), .Y(n1096) );
NAND2X2TS U1627 ( .A(n1247), .B(n754), .Y(n1661) );
INVX2TS U1628 ( .A(n754), .Y(n1249) );
BUFX20TS U1629 ( .A(n1290), .Y(n893) );
AND2X2TS U1630 ( .A(n2758), .B(Add_Subt_result[6]), .Y(n1219) );
CLKAND2X2TS U1631 ( .A(n2757), .B(Add_Subt_result[8]), .Y(n1222) );
INVX2TS U1632 ( .A(add_subt), .Y(n1514) );
INVX2TS U1633 ( .A(Data_Y[31]), .Y(n1515) );
NAND2X4TS U1634 ( .A(n1182), .B(n863), .Y(n1181) );
NAND2X2TS U1635 ( .A(n2590), .B(n835), .Y(n2594) );
NAND2X2TS U1636 ( .A(n2625), .B(n2639), .Y(n2629) );
MX2X2TS U1637 ( .A(n1918), .B(LZA_output[1]), .S0(n2395), .Y(n731) );
NOR2X4TS U1638 ( .A(n1495), .B(n1019), .Y(n1018) );
NOR2X2TS U1639 ( .A(n2579), .B(n862), .Y(n2588) );
INVX2TS U1640 ( .A(n1936), .Y(n1042) );
INVX2TS U1641 ( .A(n2589), .Y(n1007) );
INVX4TS U1642 ( .A(n2225), .Y(n2226) );
INVX3TS U1643 ( .A(n2668), .Y(n1317) );
INVX3TS U1644 ( .A(n995), .Y(n994) );
NOR2X4TS U1645 ( .A(n2196), .B(n1623), .Y(n1622) );
NAND2X4TS U1646 ( .A(n2216), .B(n1640), .Y(n2225) );
NAND2X2TS U1647 ( .A(n1442), .B(n692), .Y(n1577) );
INVX8TS U1648 ( .A(n857), .Y(n1825) );
NOR2X4TS U1649 ( .A(n997), .B(n1654), .Y(n995) );
INVX3TS U1650 ( .A(n993), .Y(n992) );
BUFX3TS U1651 ( .A(n2656), .Y(n1266) );
NOR2X4TS U1652 ( .A(n1687), .B(n1537), .Y(n1915) );
INVX8TS U1653 ( .A(n1928), .Y(n2603) );
INVX4TS U1654 ( .A(n1555), .Y(n1089) );
INVX2TS U1655 ( .A(n2212), .Y(n2197) );
NAND2X6TS U1656 ( .A(n1922), .B(n1921), .Y(n2457) );
NAND2X2TS U1657 ( .A(n1426), .B(Add_Subt_result[12]), .Y(n894) );
NAND2X2TS U1658 ( .A(n830), .B(n880), .Y(n879) );
INVX4TS U1659 ( .A(n1157), .Y(n1155) );
MXI2X1TS U1660 ( .A(n1300), .B(n1202), .S0(n2672), .Y(n701) );
INVX6TS U1661 ( .A(n1569), .Y(n1922) );
BUFX6TS U1662 ( .A(n1926), .Y(n896) );
INVX2TS U1663 ( .A(n1496), .Y(n1499) );
INVX2TS U1664 ( .A(n2151), .Y(n2266) );
OR2X4TS U1665 ( .A(overflow_flag), .B(underflow_flag), .Y(n1373) );
INVX1TS U1666 ( .A(n2097), .Y(n1830) );
OR2X6TS U1667 ( .A(n2728), .B(n860), .Y(n932) );
BUFX8TS U1668 ( .A(n1528), .Y(n912) );
INVX4TS U1669 ( .A(n2157), .Y(n1476) );
INVX8TS U1670 ( .A(n1934), .Y(n868) );
BUFX16TS U1671 ( .A(n1934), .Y(n1822) );
INVX12TS U1672 ( .A(n2394), .Y(n1556) );
MX2X4TS U1673 ( .A(Sgf_normalized_result[22]), .B(DMP[20]), .S0(n1293), .Y(
n2178) );
INVX2TS U1674 ( .A(n1301), .Y(n1302) );
INVX2TS U1675 ( .A(DmP[24]), .Y(n892) );
INVX4TS U1676 ( .A(n2733), .Y(n940) );
INVX2TS U1677 ( .A(n2800), .Y(n880) );
INVX2TS U1678 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n1364) );
INVX4TS U1679 ( .A(n1273), .Y(n1274) );
NAND2X2TS U1680 ( .A(n2803), .B(n2804), .Y(n1145) );
INVX2TS U1681 ( .A(Data_X[31]), .Y(n1516) );
INVX2TS U1682 ( .A(Data_X[29]), .Y(n1522) );
INVX2TS U1683 ( .A(Data_Y[29]), .Y(n1519) );
INVX2TS U1684 ( .A(Data_X[30]), .Y(n1517) );
INVX2TS U1685 ( .A(Data_Y[1]), .Y(n1518) );
INVX2TS U1686 ( .A(Data_Y[30]), .Y(n1520) );
NAND2X6TS U1687 ( .A(n1591), .B(n2560), .Y(n1590) );
NAND3X2TS U1688 ( .A(n2609), .B(n2608), .C(n2607), .Y(n561) );
NAND2X2TS U1689 ( .A(n2590), .B(n2591), .Y(n2052) );
MX2X2TS U1690 ( .A(n2029), .B(LZA_output[4]), .S0(n2395), .Y(n2796) );
NAND2X4TS U1691 ( .A(n908), .B(intDY[28]), .Y(n1791) );
NAND2X4TS U1692 ( .A(n1098), .B(n866), .Y(n1097) );
INVX6TS U1693 ( .A(n1008), .Y(n1006) );
INVX3TS U1694 ( .A(n1380), .Y(n1340) );
NOR2X4TS U1695 ( .A(n1001), .B(n1663), .Y(n1000) );
NAND4X4TS U1696 ( .A(n887), .B(n1899), .C(n1898), .D(n886), .Y(n2638) );
NAND2X4TS U1697 ( .A(n2077), .B(n1103), .Y(n1102) );
NAND2X4TS U1698 ( .A(n1896), .B(n1137), .Y(n1136) );
NAND2X4TS U1699 ( .A(n1139), .B(n1061), .Y(n1060) );
NAND3X4TS U1700 ( .A(n1125), .B(n1124), .C(n1129), .Y(n1001) );
BUFX20TS U1701 ( .A(n930), .Y(n859) );
NAND2X4TS U1702 ( .A(n1343), .B(n1130), .Y(n2060) );
NAND2X4TS U1703 ( .A(n1190), .B(n1526), .Y(n1189) );
XOR2X2TS U1704 ( .A(n2462), .B(n2461), .Y(n2463) );
NOR2X4TS U1705 ( .A(n1629), .B(n1627), .Y(n1625) );
INVX4TS U1706 ( .A(n2025), .Y(n1550) );
NAND2X4TS U1707 ( .A(n1122), .B(n753), .Y(n1137) );
INVX2TS U1708 ( .A(n1627), .Y(n1626) );
INVX4TS U1709 ( .A(n1688), .Y(n1218) );
INVX6TS U1710 ( .A(n1298), .Y(n2651) );
INVX3TS U1711 ( .A(n888), .Y(n2659) );
INVX2TS U1712 ( .A(n760), .Y(n2843) );
AND2X4TS U1713 ( .A(n1631), .B(n2188), .Y(n1607) );
NAND2X4TS U1714 ( .A(n1603), .B(n1823), .Y(n2009) );
CLKMX2X3TS U1715 ( .A(Data_Y[13]), .B(intDY[13]), .S0(n1435), .Y(n605) );
CLKMX2X3TS U1716 ( .A(Data_Y[6]), .B(intDY[6]), .S0(n1429), .Y(n598) );
CLKMX2X3TS U1717 ( .A(Data_X[11]), .B(intDX[11]), .S0(n1429), .Y(n636) );
CLKMX2X3TS U1718 ( .A(Data_Y[10]), .B(intDY[10]), .S0(n1429), .Y(n602) );
CLKMX2X3TS U1719 ( .A(Data_Y[4]), .B(intDY[4]), .S0(n1429), .Y(n596) );
CLKMX2X3TS U1720 ( .A(Data_Y[26]), .B(intDY[26]), .S0(n1436), .Y(n618) );
CLKMX2X3TS U1721 ( .A(Data_Y[28]), .B(intDY[28]), .S0(n1435), .Y(n620) );
CLKMX2X3TS U1722 ( .A(Data_Y[27]), .B(intDY[27]), .S0(n1436), .Y(n619) );
INVX4TS U1723 ( .A(n2420), .Y(n2458) );
NAND2X6TS U1724 ( .A(n1160), .B(n1209), .Y(n1936) );
CLKMX2X3TS U1725 ( .A(Data_Y[20]), .B(intDY[20]), .S0(n1435), .Y(n612) );
CLKMX2X3TS U1726 ( .A(Data_Y[21]), .B(intDY[21]), .S0(n1429), .Y(n613) );
CLKMX2X3TS U1727 ( .A(Data_Y[9]), .B(intDY[9]), .S0(n1435), .Y(n601) );
CLKMX2X3TS U1728 ( .A(Data_Y[19]), .B(intDY[19]), .S0(n1429), .Y(n611) );
CLKMX2X3TS U1729 ( .A(Data_Y[24]), .B(intDY[24]), .S0(n1435), .Y(n616) );
CLKMX2X3TS U1730 ( .A(Data_X[2]), .B(intDX[2]), .S0(n1436), .Y(n627) );
CLKMX2X3TS U1731 ( .A(Data_Y[2]), .B(n788), .S0(n1435), .Y(n594) );
CLKMX2X3TS U1732 ( .A(Data_Y[12]), .B(intDY[12]), .S0(n1429), .Y(n604) );
CLKMX2X3TS U1733 ( .A(Data_X[4]), .B(intDX[4]), .S0(n1424), .Y(n629) );
CLKMX2X3TS U1734 ( .A(Data_X[21]), .B(n809), .S0(n1435), .Y(n646) );
CLKMX2X3TS U1735 ( .A(Data_Y[23]), .B(intDY[23]), .S0(n1429), .Y(n615) );
CLKMX2X3TS U1736 ( .A(Data_X[9]), .B(n1303), .S0(n1435), .Y(n634) );
CLKMX2X3TS U1737 ( .A(Data_X[12]), .B(n1260), .S0(n1436), .Y(n637) );
AND2X4TS U1738 ( .A(n854), .B(n754), .Y(n1133) );
CLKMX2X3TS U1739 ( .A(Data_X[14]), .B(n873), .S0(n1435), .Y(n639) );
CLKMX2X3TS U1740 ( .A(Data_X[20]), .B(n1305), .S0(n1436), .Y(n645) );
CLKMX2X3TS U1741 ( .A(Data_X[16]), .B(n795), .S0(n1513), .Y(n641) );
CLKMX2X3TS U1742 ( .A(Data_X[5]), .B(n1304), .S0(n1447), .Y(n630) );
NAND2X4TS U1743 ( .A(n2267), .B(n2273), .Y(n2264) );
CLKMX2X3TS U1744 ( .A(Data_X[7]), .B(n1236), .S0(n1436), .Y(n632) );
CLKMX2X3TS U1745 ( .A(Data_X[19]), .B(n1301), .S0(n1429), .Y(n644) );
NAND2X4TS U1746 ( .A(n2196), .B(n1628), .Y(n1627) );
CLKMX2X3TS U1747 ( .A(Data_X[23]), .B(n1327), .S0(n1429), .Y(n648) );
MXI2X2TS U1748 ( .A(Data_Y[25]), .B(n2315), .S0(n1447), .Y(n1634) );
AND2X8TS U1749 ( .A(n1344), .B(n1345), .Y(n1343) );
CLKMX2X3TS U1750 ( .A(Data_Y[8]), .B(n1239), .S0(n1424), .Y(n600) );
NAND2X2TS U1751 ( .A(n2535), .B(DMP[28]), .Y(n1790) );
CLKMX2X2TS U1752 ( .A(Data_X[0]), .B(intDX[0]), .S0(n1448), .Y(n625) );
INVX2TS U1753 ( .A(n2732), .Y(n2830) );
NAND2X2TS U1754 ( .A(n2216), .B(n1555), .Y(n2217) );
NOR2X2TS U1755 ( .A(n1180), .B(n1426), .Y(n1179) );
INVX6TS U1756 ( .A(n2168), .Y(n1559) );
BUFX20TS U1757 ( .A(n1448), .Y(n1429) );
NAND2X2TS U1758 ( .A(n865), .B(n1272), .Y(n2533) );
INVX4TS U1759 ( .A(n1916), .Y(n990) );
CLKMX2X3TS U1760 ( .A(Data_Y[3]), .B(intDY[3]), .S0(n1448), .Y(n595) );
XNOR2X1TS U1761 ( .A(n2403), .B(n2406), .Y(n2407) );
NAND2X1TS U1762 ( .A(n2334), .B(DmP[21]), .Y(n2075) );
BUFX20TS U1763 ( .A(n1448), .Y(n1435) );
BUFX20TS U1764 ( .A(n1448), .Y(n1436) );
INVX2TS U1765 ( .A(n1657), .Y(n1223) );
NOR2X4TS U1766 ( .A(n1109), .B(n1108), .Y(n1207) );
NOR2X4TS U1767 ( .A(n2026), .B(n2027), .Y(n945) );
BUFX8TS U1768 ( .A(n2294), .Y(n2334) );
BUFX12TS U1769 ( .A(n2673), .Y(n2402) );
BUFX12TS U1770 ( .A(n2673), .Y(n2400) );
BUFX8TS U1771 ( .A(n2554), .Y(n2572) );
BUFX12TS U1772 ( .A(n2673), .Y(n1445) );
NAND3X4TS U1773 ( .A(n2278), .B(n1658), .C(n996), .Y(n2026) );
INVX2TS U1774 ( .A(n2205), .Y(n1180) );
INVX2TS U1775 ( .A(n2147), .Y(n1306) );
INVX2TS U1776 ( .A(n1538), .Y(n2188) );
NAND2X4TS U1777 ( .A(n2393), .B(n2392), .Y(n2410) );
OAI21X1TS U1778 ( .A0(n1425), .A1(n1330), .B0(n1264), .Y(n759) );
INVX6TS U1779 ( .A(n1015), .Y(n2184) );
INVX2TS U1780 ( .A(n1217), .Y(n1216) );
NAND2X2TS U1781 ( .A(n1426), .B(n1537), .Y(n934) );
INVX8TS U1782 ( .A(n1971), .Y(n2056) );
NOR2BX2TS U1783 ( .AN(n1505), .B(n1398), .Y(n1498) );
INVX2TS U1784 ( .A(n1489), .Y(n1544) );
NAND3X6TS U1785 ( .A(n1810), .B(n1002), .C(n1194), .Y(n1971) );
CLKAND2X2TS U1786 ( .A(n2847), .B(Add_Subt_result[15]), .Y(n1383) );
INVX4TS U1787 ( .A(n2847), .Y(n1628) );
AND4X6TS U1788 ( .A(n1833), .B(n1835), .C(n1834), .D(n952), .Y(n951) );
INVX16TS U1789 ( .A(n1368), .Y(n1505) );
CLKINVX2TS U1790 ( .A(overflow_flag), .Y(n2669) );
NAND2BX2TS U1791 ( .AN(n1506), .B(intDY[31]), .Y(n1496) );
NOR2X4TS U1792 ( .A(n1556), .B(n920), .Y(n919) );
OR2X4TS U1793 ( .A(n2737), .B(n1822), .Y(n1142) );
INVX8TS U1794 ( .A(n1110), .Y(n1250) );
NAND2X2TS U1795 ( .A(n2742), .B(n1262), .Y(n2151) );
AND3X4TS U1796 ( .A(n1832), .B(n1831), .C(n953), .Y(n952) );
INVX6TS U1797 ( .A(n1225), .Y(n750) );
NAND2BX2TS U1798 ( .AN(n868), .B(n2726), .Y(n1600) );
AND2X4TS U1799 ( .A(Sgf_normalized_result[15]), .B(n2394), .Y(n2153) );
INVX2TS U1800 ( .A(Add_Subt_result[15]), .Y(n957) );
NAND2X4TS U1801 ( .A(intDX[8]), .B(n1240), .Y(n1474) );
NOR2X6TS U1802 ( .A(n1296), .B(n893), .Y(n1919) );
NAND2X4TS U1803 ( .A(n2819), .B(n2818), .Y(n1117) );
BUFX6TS U1804 ( .A(Add_Subt_result[13]), .Y(n1537) );
INVX12TS U1805 ( .A(n1263), .Y(n1264) );
INVX3TS U1806 ( .A(Sgf_normalized_result[21]), .Y(n920) );
AND2X2TS U1807 ( .A(n2731), .B(Add_Subt_result[1]), .Y(n1169) );
INVX3TS U1808 ( .A(n2815), .Y(n1091) );
INVX2TS U1809 ( .A(n1417), .Y(n1418) );
BUFX16TS U1810 ( .A(n1292), .Y(n1633) );
INVX2TS U1811 ( .A(DmP[9]), .Y(n1106) );
NAND2X4TS U1812 ( .A(n981), .B(n2189), .Y(n764) );
NAND3X6TS U1813 ( .A(n877), .B(n1620), .C(n876), .Y(n749) );
XOR2X2TS U1814 ( .A(n1826), .B(n1825), .Y(Exp_Operation_Module_Data_S[8]) );
NAND3X4TS U1815 ( .A(n1391), .B(n1609), .C(n1611), .Y(
Add_Subt_Sgf_module_S_to_D[19]) );
NAND3X4TS U1816 ( .A(n1185), .B(n1979), .C(n1183), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
NAND4X2TS U1817 ( .A(n1363), .B(n2249), .C(n2248), .D(n2250), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
NAND2X6TS U1818 ( .A(n1574), .B(n942), .Y(n1593) );
NAND3X4TS U1819 ( .A(n2350), .B(n2349), .C(n2348), .Y(n571) );
NAND3BX2TS U1820 ( .AN(n2588), .B(n2587), .C(n1553), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
MX2X2TS U1821 ( .A(n2606), .B(Add_Subt_result[5]), .S0(n1426), .Y(n739) );
NAND2X4TS U1822 ( .A(n1201), .B(n2639), .Y(n1138) );
NAND3X4TS U1823 ( .A(n1791), .B(n1790), .C(n1789), .Y(n589) );
NAND2X4TS U1824 ( .A(n1006), .B(n2614), .Y(n2565) );
INVX8TS U1825 ( .A(n1563), .Y(n2202) );
NAND2X4TS U1826 ( .A(n1006), .B(n2591), .Y(n2548) );
NAND2X6TS U1827 ( .A(n1123), .B(n1000), .Y(n2590) );
NAND2X4TS U1828 ( .A(n2523), .B(n2528), .Y(n2527) );
NAND2X6TS U1829 ( .A(n1101), .B(n2079), .Y(n1488) );
NAND2X4TS U1830 ( .A(n1201), .B(n2562), .Y(n2566) );
NAND2X4TS U1831 ( .A(n1491), .B(n833), .Y(n2627) );
NOR2X4TS U1832 ( .A(n2078), .B(n1102), .Y(n1101) );
NAND2X4TS U1833 ( .A(n859), .B(intDY[27]), .Y(n2122) );
OR2X4TS U1834 ( .A(n2482), .B(n2583), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
INVX8TS U1835 ( .A(n1154), .Y(n1152) );
NAND2X6TS U1836 ( .A(n1018), .B(n1884), .Y(n2523) );
MX2X2TS U1837 ( .A(n2534), .B(Add_Subt_result[4]), .S0(n2848), .Y(n738) );
NAND2X4TS U1838 ( .A(n908), .B(intDY[19]), .Y(n2131) );
NAND2X4TS U1839 ( .A(n1212), .B(n1213), .Y(n1211) );
NAND2X4TS U1840 ( .A(n908), .B(intDY[11]), .Y(n2104) );
NOR2X4TS U1841 ( .A(n847), .B(n1388), .Y(n1524) );
OAI22X2TS U1842 ( .A0(n2484), .A1(n1130), .B0(n2483), .B1(n2515), .Y(n2485)
);
MX2X2TS U1843 ( .A(n2463), .B(Add_Subt_result[3]), .S0(n1425), .Y(n737) );
NAND2X6TS U1844 ( .A(n1187), .B(n1973), .Y(n1491) );
NAND2X6TS U1845 ( .A(n872), .B(n1819), .Y(n1510) );
NAND2X4TS U1846 ( .A(n1052), .B(n1272), .Y(n1051) );
NAND2X6TS U1847 ( .A(n1465), .B(n1631), .Y(n1464) );
NAND2X4TS U1848 ( .A(n1954), .B(n1534), .Y(n1957) );
OR2X4TS U1849 ( .A(n1625), .B(n1383), .Y(n1624) );
OR2X4TS U1850 ( .A(n1011), .B(n1010), .Y(n2078) );
NAND3X6TS U1851 ( .A(n1670), .B(n958), .C(n1669), .Y(n2592) );
NAND2X2TS U1852 ( .A(n2542), .B(Add_Subt_result[7]), .Y(n1360) );
INVX8TS U1853 ( .A(n1362), .Y(n1150) );
NAND2X2TS U1854 ( .A(n2010), .B(n2009), .Y(n1286) );
MX2X2TS U1855 ( .A(n2422), .B(Add_Subt_result[2]), .S0(n1425), .Y(n736) );
NAND2X6TS U1856 ( .A(n1587), .B(n1366), .Y(n1644) );
NAND3X6TS U1857 ( .A(n2280), .B(n2028), .C(n1168), .Y(n1689) );
OA21X2TS U1858 ( .A0(n2209), .A1(n2197), .B0(n2211), .Y(n2198) );
BUFX8TS U1859 ( .A(n1446), .Y(n1406) );
NAND2X2TS U1860 ( .A(n959), .B(Add_Subt_result[6]), .Y(n1326) );
NAND2X6TS U1861 ( .A(n1281), .B(n2018), .Y(n1508) );
NOR3X6TS U1862 ( .A(n991), .B(n990), .C(n987), .Y(n986) );
NAND2X6TS U1863 ( .A(n1998), .B(n1300), .Y(n2515) );
INVX12TS U1864 ( .A(n1681), .Y(n2591) );
INVX8TS U1865 ( .A(n1481), .Y(n1479) );
XNOR2X2TS U1866 ( .A(n2421), .B(n2458), .Y(n2422) );
CLKMX2X3TS U1867 ( .A(Data_X[27]), .B(intDX[27]), .S0(n1447), .Y(n652) );
NAND2X6TS U1868 ( .A(n1075), .B(n1641), .Y(n869) );
CLKMX2X3TS U1869 ( .A(Data_X[28]), .B(n801), .S0(n1424), .Y(n653) );
INVX4TS U1870 ( .A(n2185), .Y(n1631) );
NAND2X6TS U1871 ( .A(n1916), .B(n1385), .Y(n1688) );
MXI2X2TS U1872 ( .A(n1521), .B(n1308), .S0(n1447), .Y(n626) );
CLKMX2X3TS U1873 ( .A(Data_Y[11]), .B(intDY[11]), .S0(n1447), .Y(n603) );
MXI2X2TS U1874 ( .A(n1522), .B(n1400), .S0(n1447), .Y(n654) );
NAND2X4TS U1875 ( .A(n2517), .B(n1131), .Y(n1989) );
CLKMX2X3TS U1876 ( .A(Data_Y[16]), .B(intDY[16]), .S0(n1513), .Y(n608) );
INVX6TS U1877 ( .A(n2387), .Y(n1494) );
MX2X2TS U1878 ( .A(n2407), .B(Add_Subt_result[0]), .S0(n1425), .Y(n734) );
CLKMX2X3TS U1879 ( .A(Data_X[22]), .B(intDX[22]), .S0(n1424), .Y(n647) );
NAND2X4TS U1880 ( .A(n2023), .B(n2387), .Y(n1998) );
CLKMX2X3TS U1881 ( .A(Data_X[15]), .B(intDX[15]), .S0(n1424), .Y(n640) );
INVX8TS U1882 ( .A(n2503), .Y(n1681) );
CLKINVX6TS U1883 ( .A(n2254), .Y(n861) );
NAND2X6TS U1884 ( .A(n1560), .B(n1559), .Y(n1564) );
NAND2X4TS U1885 ( .A(n1982), .B(n1131), .Y(n1973) );
AND2X2TS U1886 ( .A(n2604), .B(n2603), .Y(n2605) );
CLKMX2X3TS U1887 ( .A(Data_X[13]), .B(n1309), .S0(n1513), .Y(n638) );
AO22X2TS U1888 ( .A0(n2402), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[6]), .B1(n2399), .Y(n675) );
AO22X2TS U1889 ( .A0(n1445), .A1(n1269), .B0(final_result_ieee[1]), .B1(
n2399), .Y(n680) );
AO22X2TS U1890 ( .A0(n2402), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[10]), .B1(n2401), .Y(n671) );
NAND3X4TS U1891 ( .A(n1167), .B(n1904), .C(n1310), .Y(n1168) );
INVX6TS U1892 ( .A(n2211), .Y(n1075) );
AO22X2TS U1893 ( .A0(n2400), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[2]), .B1(n2399), .Y(n679) );
AO22X2TS U1894 ( .A0(n2400), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[9]), .B1(n2401), .Y(n672) );
AND2X2TS U1895 ( .A(n2665), .B(n2664), .Y(n2666) );
NAND2X2TS U1896 ( .A(n1639), .B(n2222), .Y(n2223) );
NAND2X6TS U1897 ( .A(n1641), .B(n2212), .Y(n2176) );
AND2X4TS U1898 ( .A(n2334), .B(n532), .Y(n1802) );
AO22X2TS U1899 ( .A0(n1445), .A1(n1318), .B0(final_result_ieee[3]), .B1(
n2399), .Y(n678) );
AO22X2TS U1900 ( .A0(n1445), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[8]), .B1(n2401), .Y(n673) );
AO22X2TS U1901 ( .A0(n2402), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[5]), .B1(n2399), .Y(n676) );
NAND2X6TS U1902 ( .A(n1985), .B(n1984), .Y(n2517) );
AND2X2TS U1903 ( .A(n2358), .B(DMP[12]), .Y(n2357) );
AO22X2TS U1904 ( .A0(n2400), .A1(n1417), .B0(final_result_ieee[4]), .B1(
n2399), .Y(n677) );
AO22X2TS U1905 ( .A0(n2400), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[7]), .B1(n2401), .Y(n674) );
INVX2TS U1906 ( .A(n1422), .Y(n1412) );
BUFX12TS U1907 ( .A(n2286), .Y(n1442) );
INVX12TS U1908 ( .A(n2637), .Y(n862) );
BUFX8TS U1909 ( .A(n2294), .Y(n2535) );
AND2X4TS U1910 ( .A(n2410), .B(n2394), .Y(n2732) );
NAND3X6TS U1911 ( .A(n1658), .B(n2278), .C(n998), .Y(n997) );
NAND2X6TS U1912 ( .A(n1640), .B(n2159), .Y(n2160) );
INVX2TS U1913 ( .A(n2663), .Y(n2664) );
NAND2X2TS U1914 ( .A(n2396), .B(n2408), .Y(n700) );
BUFX8TS U1915 ( .A(n2294), .Y(n2610) );
BUFX8TS U1916 ( .A(n2554), .Y(n2510) );
NOR2X6TS U1917 ( .A(n1996), .B(n1827), .Y(n2286) );
INVX2TS U1918 ( .A(n2228), .Y(n2222) );
NAND2X6TS U1919 ( .A(n1529), .B(n1193), .Y(n1637) );
NOR2X6TS U1920 ( .A(n2663), .B(n2653), .Y(n1165) );
NAND2X6TS U1921 ( .A(n2179), .B(n2178), .Y(n2205) );
INVX12TS U1922 ( .A(n2426), .Y(n2528) );
INVX2TS U1923 ( .A(n2660), .Y(n2654) );
NAND2X2TS U1924 ( .A(n1538), .B(n2404), .Y(n2405) );
NAND2X6TS U1925 ( .A(n1057), .B(n1471), .Y(n2212) );
NAND2X2TS U1926 ( .A(n1374), .B(n2233), .Y(n2234) );
NAND2X6TS U1927 ( .A(n1506), .B(n1333), .Y(n2397) );
INVX6TS U1928 ( .A(n2175), .Y(n1058) );
AND2X2TS U1929 ( .A(n830), .B(Add_Subt_result[23]), .Y(n2194) );
NOR2X6TS U1930 ( .A(n1489), .B(n893), .Y(n1996) );
AND2X4TS U1931 ( .A(n1879), .B(n1806), .Y(n1337) );
NAND2X6TS U1932 ( .A(n2403), .B(n1638), .Y(n1027) );
INVX6TS U1933 ( .A(n1739), .Y(n1196) );
NAND2X4TS U1934 ( .A(n1930), .B(n1568), .Y(n1956) );
INVX8TS U1935 ( .A(n1671), .Y(n1680) );
NAND2X4TS U1936 ( .A(n2166), .B(n2165), .Y(n2233) );
NOR3X4TS U1937 ( .A(n1501), .B(n1515), .C(n1505), .Y(n1500) );
NAND2X4TS U1938 ( .A(n2395), .B(n2721), .Y(n1217) );
NAND2X6TS U1939 ( .A(n933), .B(n932), .Y(n1813) );
NOR3X6TS U1940 ( .A(n999), .B(n858), .C(n2024), .Y(n998) );
BUFX20TS U1941 ( .A(n2847), .Y(n1426) );
NAND2X8TS U1942 ( .A(LZA_output[1]), .B(n1377), .Y(n1809) );
NAND2X4TS U1943 ( .A(n1368), .B(n1331), .Y(n1489) );
NAND2X2TS U1944 ( .A(n1820), .B(DmP[28]), .Y(n1808) );
INVX4TS U1945 ( .A(n1250), .Y(n753) );
INVX12TS U1946 ( .A(n966), .Y(n752) );
MX2X4TS U1947 ( .A(Sgf_normalized_result[23]), .B(DMP[21]), .S0(n1293), .Y(
n2180) );
NAND2X6TS U1948 ( .A(n910), .B(n1716), .Y(n1737) );
INVX2TS U1949 ( .A(n1937), .Y(n1156) );
INVX2TS U1950 ( .A(n733), .Y(n1248) );
MX2X4TS U1951 ( .A(Sgf_normalized_result[4]), .B(DMP[2]), .S0(n1633), .Y(
n1925) );
MX2X4TS U1952 ( .A(Sgf_normalized_result[18]), .B(DMP[16]), .S0(n1633), .Y(
n2157) );
MX2X4TS U1953 ( .A(Sgf_normalized_result[17]), .B(DMP[15]), .S0(n1633), .Y(
n2174) );
MX2X4TS U1954 ( .A(Sgf_normalized_result[8]), .B(DMP[6]), .S0(n1633), .Y(
n1937) );
OR2X4TS U1955 ( .A(n2315), .B(n1321), .Y(n1320) );
INVX4TS U1956 ( .A(n692), .Y(n1245) );
INVX4TS U1957 ( .A(n1654), .Y(n1912) );
INVX12TS U1958 ( .A(n943), .Y(n1914) );
BUFX16TS U1959 ( .A(n1328), .Y(n1300) );
NAND2X4TS U1960 ( .A(n2810), .B(n2809), .Y(n1113) );
CLKBUFX2TS U1961 ( .A(n1315), .Y(n1316) );
NAND2X4TS U1962 ( .A(n2825), .B(n2824), .Y(n1119) );
NAND2X4TS U1963 ( .A(n2795), .B(intDX[18]), .Y(n1458) );
INVX12TS U1964 ( .A(n1264), .Y(n867) );
INVX2TS U1965 ( .A(n2757), .Y(n1127) );
NAND2X2TS U1966 ( .A(n1242), .B(n1259), .Y(n2873) );
NAND2X2TS U1967 ( .A(n1258), .B(n1257), .Y(n2874) );
INVX12TS U1968 ( .A(n1324), .Y(n1325) );
INVX2TS U1969 ( .A(n2797), .Y(n1206) );
AND2X2TS U1970 ( .A(n2730), .B(Add_Subt_result[4]), .Y(n1656) );
INVX2TS U1971 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[31]), .Y(n1880) );
NOR2X4TS U1972 ( .A(n2769), .B(intDX[24]), .Y(n1742) );
OR2X2TS U1973 ( .A(Add_Subt_result[3]), .B(Add_Subt_result[2]), .Y(n1911) );
NAND2X4TS U1974 ( .A(n2805), .B(n1390), .Y(n967) );
MX2X4TS U1975 ( .A(Sgf_normalized_result[15]), .B(DMP[13]), .S0(n1292), .Y(
n2171) );
NAND2X4TS U1976 ( .A(n2807), .B(n2806), .Y(n1115) );
INVX2TS U1977 ( .A(Data_X[1]), .Y(n1521) );
INVX16TS U1978 ( .A(n906), .Y(n1352) );
NAND2X8TS U1979 ( .A(n1028), .B(n1047), .Y(n1012) );
NAND2X8TS U1980 ( .A(n869), .B(n2200), .Y(n1074) );
INVX8TS U1981 ( .A(n2186), .Y(n1481) );
NAND2X4TS U1982 ( .A(n1941), .B(n1942), .Y(n2665) );
XNOR2X4TS U1983 ( .A(n1285), .B(n1014), .Y(n1941) );
NOR2X6TS U1984 ( .A(n2187), .B(n2188), .Y(n1468) );
INVX16TS U1985 ( .A(n1033), .Y(n1016) );
NOR2X8TS U1986 ( .A(n1403), .B(n1938), .Y(n1606) );
XOR2X4TS U1987 ( .A(n1404), .B(n918), .Y(n1403) );
BUFX6TS U1988 ( .A(n1325), .Y(n871) );
NAND2X6TS U1989 ( .A(n1566), .B(n1209), .Y(n1162) );
NOR2X2TS U1990 ( .A(n2580), .B(n1105), .Y(n1010) );
INVX12TS U1991 ( .A(n2431), .Y(n1067) );
XOR2X4TS U1992 ( .A(n874), .B(n2201), .Y(Add_Subt_Sgf_module_S_to_D[17]) );
NAND2X8TS U1993 ( .A(n1046), .B(n2198), .Y(n874) );
INVX12TS U1994 ( .A(n875), .Y(n1238) );
NOR2X8TS U1995 ( .A(n1995), .B(n2450), .Y(n875) );
NAND3X6TS U1996 ( .A(n1081), .B(n1079), .C(n1080), .Y(n1078) );
NOR2BX4TS U1997 ( .AN(n1618), .B(n1624), .Y(n876) );
NAND2X8TS U1998 ( .A(n1621), .B(n1622), .Y(n877) );
NAND3X6TS U1999 ( .A(n939), .B(n938), .C(n937), .Y(n936) );
OAI21X4TS U2000 ( .A0(n881), .A1(n830), .B0(n879), .Y(n745) );
XOR2X4TS U2001 ( .A(n889), .B(n2666), .Y(n881) );
NAND2X8TS U2002 ( .A(n1022), .B(n1878), .Y(n2431) );
NOR2X6TS U2003 ( .A(n2277), .B(n1310), .Y(n1658) );
AOI21X4TS U2004 ( .A0(n1698), .A1(n884), .B0(n1697), .Y(n1713) );
OAI21X4TS U2005 ( .A0(n1268), .A1(n1267), .B0(n1692), .Y(n884) );
NAND3X4TS U2006 ( .A(n1141), .B(n1138), .C(n1132), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
NOR2X4TS U2007 ( .A(n2783), .B(intDX[4]), .Y(n1699) );
BUFX6TS U2008 ( .A(intDY[0]), .Y(n885) );
NAND2X4TS U2009 ( .A(n2529), .B(n1994), .Y(n2035) );
AOI21X4TS U2010 ( .A0(n1003), .A1(n532), .B0(n1133), .Y(n886) );
AOI2BB2X4TS U2011 ( .B0(n969), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .A0N(n1066), .A1N(
n2768), .Y(n2031) );
NAND2X6TS U2012 ( .A(n2787), .B(intDX[6]), .Y(n1706) );
NAND3X2TS U2013 ( .A(n2532), .B(n2531), .C(n2530), .Y(n711) );
OR2X8TS U2014 ( .A(n2734), .B(n1934), .Y(n1554) );
NAND2X2TS U2015 ( .A(n2212), .B(n2211), .Y(n2213) );
BUFX20TS U2016 ( .A(n1029), .Y(n1028) );
BUFX20TS U2017 ( .A(n972), .Y(n1233) );
NOR2X8TS U2018 ( .A(n2787), .B(intDX[6]), .Y(n1700) );
AOI21X4TS U2019 ( .A0(n1040), .A1(n2662), .B0(n2661), .Y(n889) );
NAND2X8TS U2020 ( .A(n1377), .B(n1315), .Y(n1810) );
NAND2X8TS U2021 ( .A(n1601), .B(n1416), .Y(n890) );
NOR2X8TS U2022 ( .A(n1153), .B(n1150), .Y(n1149) );
NAND2X8TS U2023 ( .A(n2013), .B(n782), .Y(n1153) );
NOR2X8TS U2024 ( .A(n2793), .B(intDX[25]), .Y(n1769) );
NAND2X6TS U2025 ( .A(n2783), .B(intDX[4]), .Y(n1703) );
CLKBUFX2TS U2026 ( .A(n1324), .Y(n891) );
CLKINVX12TS U2027 ( .A(n1027), .Y(n1026) );
NOR2X8TS U2028 ( .A(n1085), .B(n1578), .Y(n2008) );
NAND3X6TS U2029 ( .A(n1181), .B(n1561), .C(n1178), .Y(n1177) );
NAND4X4TS U2030 ( .A(n1177), .B(n1174), .C(n1171), .D(n1170), .Y(n757) );
NAND2X8TS U2031 ( .A(n901), .B(n1328), .Y(n900) );
INVX12TS U2032 ( .A(n922), .Y(n1288) );
MX2X4TS U2033 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n1415), .Y(
n1932) );
OAI21X4TS U2034 ( .A0(n895), .A1(n1426), .B0(n894), .Y(n746) );
XOR2X4TS U2035 ( .A(n1041), .B(n1317), .Y(n895) );
NAND2X6TS U2036 ( .A(n695), .B(n1820), .Y(n1022) );
AND2X2TS U2037 ( .A(n1508), .B(n2016), .Y(n1341) );
NOR2X8TS U2038 ( .A(n1195), .B(n1009), .Y(n1100) );
NAND2X4TS U2039 ( .A(n2469), .B(n1994), .Y(n2443) );
AOI21X4TS U2040 ( .A0(n897), .A1(n1774), .B0(n1773), .Y(n1783) );
OAI21X4TS U2041 ( .A0(n1768), .A1(n1769), .B0(n1320), .Y(n897) );
NAND2X4TS U2042 ( .A(n1091), .B(n2817), .Y(n1095) );
NAND2X8TS U2043 ( .A(n1076), .B(n1241), .Y(n1036) );
CLKINVX12TS U2044 ( .A(n898), .Y(n901) );
NAND3X8TS U2045 ( .A(n1324), .B(n1290), .C(n1295), .Y(n898) );
INVX12TS U2046 ( .A(n1295), .Y(n1296) );
NAND2X8TS U2047 ( .A(n902), .B(n899), .Y(n913) );
NAND2X8TS U2048 ( .A(n900), .B(n1330), .Y(n899) );
BUFX20TS U2049 ( .A(n931), .Y(n906) );
INVX12TS U2050 ( .A(n1197), .Y(n1349) );
NAND2X8TS U2051 ( .A(n2383), .B(n1788), .Y(n931) );
AOI21X4TS U2052 ( .A0(n859), .A1(intDY[12]), .B0(n2357), .Y(n907) );
XNOR2X4TS U2053 ( .A(n913), .B(n1605), .Y(n909) );
NAND2X2TS U2054 ( .A(n909), .B(n1817), .Y(n2257) );
AOI21X4TS U2055 ( .A0(n910), .A1(n1735), .B0(n1734), .Y(n1736) );
NOR2X8TS U2056 ( .A(n1715), .B(n1733), .Y(n910) );
INVX12TS U2057 ( .A(n1416), .Y(n1202) );
NAND3X8TS U2058 ( .A(n851), .B(n915), .C(n914), .Y(n1563) );
NAND3X8TS U2059 ( .A(n2177), .B(n1241), .C(n1076), .Y(n914) );
OR2X8TS U2060 ( .A(n1523), .B(n1035), .Y(n915) );
BUFX12TS U2061 ( .A(n1563), .Y(n916) );
BUFX20TS U2062 ( .A(n1016), .Y(n918) );
XNOR2X4TS U2063 ( .A(n919), .B(n917), .Y(n2166) );
AOI21X4TS U2064 ( .A0(n1032), .A1(n2149), .B0(n965), .Y(n964) );
NAND2X8TS U2065 ( .A(n1162), .B(n1163), .Y(n1032) );
NAND4X8TS U2066 ( .A(n1026), .B(n2416), .C(n2460), .D(n1637), .Y(n927) );
NOR2X8TS U2067 ( .A(n1931), .B(n1932), .Y(n922) );
NAND2X8TS U2068 ( .A(n927), .B(n928), .Y(n1953) );
OR2X8TS U2069 ( .A(n2415), .B(n2414), .Y(n2416) );
AOI21X4TS U2070 ( .A0(n864), .A1(n2460), .B0(n929), .Y(n928) );
NAND2X8TS U2071 ( .A(n1191), .B(n1192), .Y(n2460) );
BUFX16TS U2072 ( .A(n1423), .Y(n930) );
NOR2X8TS U2073 ( .A(n1788), .B(n2294), .Y(n1423) );
INVX16TS U2074 ( .A(n1330), .Y(n1331) );
OAI21X4TS U2075 ( .A0(n935), .A1(n1426), .B0(n934), .Y(n747) );
XNOR2X4TS U2076 ( .A(n936), .B(n1323), .Y(n935) );
AOI21X4TS U2077 ( .A0(n940), .A1(n1377), .B0(n1664), .Y(n1811) );
INVX2TS U2078 ( .A(n1366), .Y(n941) );
OR2X8TS U2079 ( .A(Add_Subt_result[10]), .B(Add_Subt_result[11]), .Y(n943)
);
NAND4BX4TS U2080 ( .AN(n995), .B(n946), .C(n944), .D(n2028), .Y(n2029) );
AOI21X4TS U2081 ( .A0(n1166), .A1(Add_Subt_result[0]), .B0(n947), .Y(n946)
);
AND2X8TS U2082 ( .A(n1540), .B(n948), .Y(n1166) );
NAND2X8TS U2083 ( .A(n1820), .B(exp_oper_result[2]), .Y(n1002) );
XOR2X4TS U2084 ( .A(intDX[8]), .B(n1239), .Y(n954) );
XOR2X4TS U2085 ( .A(intDY[6]), .B(intDX[6]), .Y(n955) );
XOR2X4TS U2086 ( .A(intDY[4]), .B(intDX[4]), .Y(n956) );
NOR2X8TS U2087 ( .A(n1131), .B(n1492), .Y(n2541) );
INVX12TS U2088 ( .A(n1668), .Y(n2243) );
NAND2X8TS U2089 ( .A(n1131), .B(n960), .Y(n1668) );
BUFX20TS U2090 ( .A(n1029), .Y(n961) );
NAND2X8TS U2091 ( .A(n964), .B(n962), .Y(n1029) );
NOR2X8TS U2092 ( .A(n1475), .B(n1936), .Y(n963) );
AND2X8TS U2093 ( .A(n1547), .B(n966), .Y(n1659) );
AND2X8TS U2094 ( .A(n967), .B(n1145), .Y(n966) );
NAND2X8TS U2095 ( .A(n968), .B(n1656), .Y(n2025) );
BUFX20TS U2096 ( .A(n1586), .Y(n969) );
INVX16TS U2097 ( .A(n970), .Y(n1994) );
NAND2X8TS U2098 ( .A(n1999), .B(n1104), .Y(n970) );
NAND2X8TS U2099 ( .A(n1885), .B(n1886), .Y(n1999) );
BUFX20TS U2100 ( .A(n1423), .Y(n972) );
AOI21X4TS U2101 ( .A0(n1785), .A1(n1786), .B0(n1784), .Y(n973) );
NAND3X6TS U2102 ( .A(n979), .B(n977), .C(n975), .Y(n981) );
NAND2X4TS U2103 ( .A(n1012), .B(n976), .Y(n975) );
AOI21X4TS U2104 ( .A0(n916), .A1(n1632), .B0(n1023), .Y(n976) );
NOR2X8TS U2105 ( .A(n846), .B(n978), .Y(n977) );
NAND2X8TS U2106 ( .A(n1025), .B(n1628), .Y(n978) );
NAND2X8TS U2107 ( .A(n980), .B(n1538), .Y(n979) );
CLKINVX12TS U2108 ( .A(n1012), .Y(n980) );
OAI22X4TS U2109 ( .A0(n2829), .A1(n2827), .B0(n2828), .B1(n983), .Y(n1225)
);
OAI2BB1X4TS U2110 ( .A0N(n983), .A1N(n2829), .B0(n982), .Y(n984) );
NAND2BX4TS U2111 ( .AN(n983), .B(n2828), .Y(n982) );
NOR2X8TS U2112 ( .A(n984), .B(Add_Subt_result[15]), .Y(n1647) );
NAND2X8TS U2113 ( .A(n1210), .B(n1911), .Y(n993) );
AND2X8TS U2114 ( .A(n1655), .B(n1651), .Y(n1540) );
NAND2X8TS U2115 ( .A(n1648), .B(n1455), .Y(n1687) );
OAI2BB1X4TS U2116 ( .A0N(n1003), .A1N(DmP[4]), .B0(n1897), .Y(n1135) );
AOI21X4TS U2117 ( .A0(n2641), .A1(n1186), .B0(n1184), .Y(n1183) );
NAND2BX4TS U2118 ( .AN(n853), .B(n1525), .Y(n1005) );
AND2X6TS U2119 ( .A(n2581), .B(n1131), .Y(n1393) );
BUFX12TS U2120 ( .A(n1016), .Y(n1013) );
BUFX20TS U2121 ( .A(n1016), .Y(n1014) );
XNOR2X4TS U2122 ( .A(n1048), .B(n917), .Y(n1617) );
XOR2X4TS U2123 ( .A(n1570), .B(n1016), .Y(n1569) );
XNOR2X4TS U2124 ( .A(n1043), .B(n1016), .Y(n1926) );
XOR2X4TS U2125 ( .A(n2156), .B(n1014), .Y(n2164) );
XOR2X4TS U2126 ( .A(n1948), .B(n918), .Y(n1950) );
XNOR2X4TS U2127 ( .A(n1405), .B(n784), .Y(n2179) );
XOR2X4TS U2128 ( .A(n1935), .B(n784), .Y(n1944) );
XNOR2X4TS U2129 ( .A(n2150), .B(n1014), .Y(n1015) );
NAND2BX2TS U2130 ( .AN(n1416), .B(exp_oper_result[0]), .Y(n1665) );
OAI2BB1X4TS U2131 ( .A0N(DmP[23]), .A1N(n1202), .B0(n1811), .Y(n1812) );
INVX12TS U2132 ( .A(n2486), .Y(n1495) );
NAND3X8TS U2133 ( .A(n1469), .B(n1468), .C(n1467), .Y(n1025) );
NAND2X8TS U2134 ( .A(n2416), .B(n1026), .Y(n2420) );
XOR2X4TS U2135 ( .A(n1028), .B(n1313), .Y(n1410) );
AOI21X4TS U2136 ( .A0(n1040), .A1(n1042), .B0(n921), .Y(n1041) );
NAND2X8TS U2137 ( .A(n1034), .B(n2173), .Y(n2211) );
XNOR2X4TS U2138 ( .A(n1014), .B(n2154), .Y(n1057) );
NAND4X8TS U2139 ( .A(n2216), .B(n1374), .C(n1640), .D(n1639), .Y(n1035) );
NAND2X8TS U2140 ( .A(n2160), .B(n2240), .Y(n1560) );
CLKINVX1TS U2141 ( .A(n1606), .Y(n1636) );
NOR2X8TS U2142 ( .A(n2663), .B(n2660), .Y(n1209) );
NOR2X8TS U2143 ( .A(n1940), .B(n1939), .Y(n2660) );
NOR2X8TS U2144 ( .A(n1941), .B(n1942), .Y(n2663) );
XNOR2X4TS U2145 ( .A(n1038), .B(n1013), .Y(n1940) );
INVX16TS U2146 ( .A(n1039), .Y(n1040) );
OR2X8TS U2147 ( .A(n2735), .B(n1541), .Y(n1043) );
OR2X8TS U2148 ( .A(n2008), .B(n2019), .Y(n1045) );
NAND2X8TS U2149 ( .A(n961), .B(n2199), .Y(n1046) );
AND2X8TS U2150 ( .A(n1269), .B(n868), .Y(n1048) );
NOR2X8TS U2151 ( .A(n1049), .B(n1414), .Y(n2253) );
INVX12TS U2152 ( .A(n1158), .Y(n1367) );
NAND2X8TS U2153 ( .A(n1575), .B(n1348), .Y(n1158) );
MXI2X2TS U2154 ( .A(n2560), .B(n2727), .S0(n1442), .Y(n698) );
BUFX12TS U2155 ( .A(n1953), .Y(n1050) );
XOR2X4TS U2156 ( .A(n1051), .B(n2605), .Y(n2606) );
NAND2BX4TS U2157 ( .AN(n1262), .B(DMP[1]), .Y(n1054) );
XOR2X4TS U2158 ( .A(n857), .B(n1055), .Y(n1598) );
NOR2X8TS U2159 ( .A(n1381), .B(n1598), .Y(n2012) );
OAI2BB1X4TS U2160 ( .A0N(n860), .A1N(n2740), .B0(n1056), .Y(n1381) );
NAND2BX4TS U2161 ( .AN(n860), .B(n2727), .Y(n1056) );
AO22X4TS U2162 ( .A0(n2741), .A1(n868), .B0(n1934), .B1(n2725), .Y(n1595) );
NAND2X8TS U2163 ( .A(n1058), .B(n1470), .Y(n1641) );
INVX12TS U2164 ( .A(n1063), .Y(n1368) );
NAND2X8TS U2165 ( .A(n1064), .B(n1062), .Y(n1543) );
NOR2X8TS U2166 ( .A(n1063), .B(n1805), .Y(n1062) );
BUFX16TS U2167 ( .A(n2450), .Y(n1066) );
NAND2X8TS U2168 ( .A(n1067), .B(n1065), .Y(n2450) );
AND2X8TS U2169 ( .A(n1879), .B(n1068), .Y(n1065) );
NAND2X4TS U2170 ( .A(exp_oper_result[3]), .B(n1820), .Y(n1068) );
NAND2X4TS U2171 ( .A(n1377), .B(LZA_output[3]), .Y(n1879) );
OAI21X4TS U2172 ( .A0(n2837), .A1(n852), .B0(n1072), .Y(n1235) );
INVX16TS U2173 ( .A(n1077), .Y(n1265) );
NOR2X6TS U2174 ( .A(n2426), .B(n2450), .Y(n1077) );
NAND2X4TS U2175 ( .A(n1409), .B(n916), .Y(n1079) );
AOI21X4TS U2176 ( .A0(n2262), .A1(n2273), .B0(n2263), .Y(n1080) );
NAND2X8TS U2177 ( .A(n961), .B(n2265), .Y(n1081) );
NAND2X4TS U2178 ( .A(n1578), .B(n1085), .Y(n1084) );
OR2X8TS U2179 ( .A(n1583), .B(n1599), .Y(n2013) );
XNOR2X4TS U2180 ( .A(n1090), .B(n913), .Y(n1583) );
NAND2BX4TS U2181 ( .AN(n1159), .B(n1584), .Y(n1090) );
BUFX6TS U2182 ( .A(n756), .Y(n1092) );
NAND4X4TS U2183 ( .A(n1244), .B(n1659), .C(n1647), .D(n1908), .Y(n1093) );
NOR2X8TS U2184 ( .A(n1204), .B(n1203), .Y(n1244) );
NOR2X8TS U2185 ( .A(n756), .B(Add_Subt_result[23]), .Y(n1908) );
NAND2X8TS U2186 ( .A(n1095), .B(n1094), .Y(n756) );
NAND2X4TS U2187 ( .A(n2815), .B(n2816), .Y(n1094) );
NAND4BX4TS U2188 ( .AN(n1099), .B(n1549), .C(n1208), .D(n1551), .Y(n1098) );
INVX16TS U2189 ( .A(n1100), .Y(n1107) );
AOI2BB2X2TS U2190 ( .B0(n1406), .B1(Add_Subt_result[1]), .A0N(n1249), .A1N(
n1121), .Y(n2544) );
INVX12TS U2191 ( .A(n1667), .Y(n2076) );
OR2X8TS U2192 ( .A(n1195), .B(n867), .Y(n1667) );
NOR2X8TS U2193 ( .A(n2277), .B(n1111), .Y(n1655) );
NOR2X8TS U2194 ( .A(n758), .B(n733), .Y(n1906) );
NAND2X8TS U2195 ( .A(n1113), .B(n1112), .Y(n733) );
NAND2BX4TS U2196 ( .AN(n2809), .B(n2811), .Y(n1112) );
NAND2X8TS U2197 ( .A(n1115), .B(n1114), .Y(n758) );
NAND2BX4TS U2198 ( .AN(n2806), .B(n2808), .Y(n1114) );
NAND2X8TS U2199 ( .A(n1250), .B(n1905), .Y(n2277) );
NOR2X8TS U2200 ( .A(n755), .B(n754), .Y(n1905) );
NAND2X8TS U2201 ( .A(n1117), .B(n1116), .Y(n754) );
NAND2BX4TS U2202 ( .AN(n2818), .B(n2820), .Y(n1116) );
NAND2X8TS U2203 ( .A(n1119), .B(n1118), .Y(n755) );
NAND2BX4TS U2204 ( .AN(n2824), .B(n2826), .Y(n1118) );
AO21X4TS U2205 ( .A0(n2813), .A1(n2812), .B0(n1120), .Y(n1110) );
NOR2BX4TS U2206 ( .AN(n2814), .B(n2812), .Y(n1120) );
AOI2BB2X4TS U2207 ( .B0(n1128), .B1(n1127), .A0N(n1667), .A1N(n1126), .Y(
n1125) );
AOI2BB2X4TS U2208 ( .B0(n2586), .B1(n1443), .A0N(n1130), .A1N(n2281), .Y(
n2285) );
AOI21X4TS U2209 ( .A0(n2481), .A1(n2480), .B0(n1130), .Y(n2482) );
AOI21X4TS U2210 ( .A0(n2520), .A1(n2519), .B0(n1130), .Y(n2522) );
AOI21X4TS U2211 ( .A0(n2505), .A1(n2504), .B0(n1130), .Y(n2507) );
AOI22X4TS U2212 ( .A0(n2642), .A1(n2641), .B0(n2637), .B1(n2638), .Y(n1132)
);
NAND2X8TS U2213 ( .A(n1143), .B(n1142), .Y(n1817) );
NAND2X8TS U2214 ( .A(n693), .B(n1822), .Y(n1143) );
NAND4X8TS U2215 ( .A(n798), .B(n1339), .C(n1588), .D(n2287), .Y(n2288) );
XNOR2X4TS U2216 ( .A(n1341), .B(n2022), .Y(n2560) );
NOR2X8TS U2217 ( .A(n1805), .B(n1295), .Y(n1146) );
NAND2X8TS U2218 ( .A(n1263), .B(n1237), .Y(n1805) );
NAND3X8TS U2219 ( .A(n1151), .B(n1148), .C(n1147), .Y(n1588) );
NAND2X8TS U2220 ( .A(n1154), .B(n1149), .Y(n1148) );
NAND2X8TS U2221 ( .A(n1152), .B(n1153), .Y(n1151) );
NAND2X8TS U2222 ( .A(n2021), .B(n2020), .Y(n1154) );
INVX8TS U2223 ( .A(n2011), .Y(n2020) );
NAND2X8TS U2224 ( .A(n1508), .B(n2016), .Y(n2021) );
XNOR2X4TS U2225 ( .A(n1013), .B(n1402), .Y(n1157) );
NAND2X4TS U2226 ( .A(n1366), .B(n1158), .Y(n1574) );
NAND2X8TS U2227 ( .A(n1583), .B(n1599), .Y(n2014) );
AOI21X4TS U2228 ( .A0(n1040), .A1(n888), .B0(n2652), .Y(n2655) );
OAI21X4TS U2229 ( .A0(n1606), .A1(n2656), .B0(n2649), .Y(n1566) );
NAND2X8TS U2230 ( .A(n1945), .B(n1951), .Y(n1161) );
NOR2X8TS U2231 ( .A(n2667), .B(n2148), .Y(n2149) );
NOR2X8TS U2232 ( .A(n1950), .B(n1949), .Y(n2148) );
NOR2X8TS U2233 ( .A(n1165), .B(n1164), .Y(n1163) );
NOR2X8TS U2234 ( .A(n1909), .B(n2277), .Y(n1455) );
AOI21X4TS U2235 ( .A0(n959), .A1(n750), .B0(n1188), .Y(n1187) );
OAI2BB1X4TS U2236 ( .A0N(Add_Subt_result[9]), .A1N(n1020), .B0(n1972), .Y(
n1188) );
NOR2X4TS U2237 ( .A(n815), .B(n1934), .Y(n1920) );
INVX8TS U2238 ( .A(n1617), .Y(n1191) );
NAND2X4TS U2239 ( .A(n1923), .B(n1617), .Y(n2459) );
BUFX20TS U2240 ( .A(n931), .Y(n1197) );
AND2X8TS U2241 ( .A(n1786), .B(n1754), .Y(n1198) );
NOR2BX4TS U2242 ( .AN(n2823), .B(n2821), .Y(n1203) );
NOR2BX4TS U2243 ( .AN(n2822), .B(n1205), .Y(n1204) );
AO21X4TS U2244 ( .A0(n1915), .A1(n1221), .B0(n1220), .Y(n1215) );
OA21X4TS U2245 ( .A0(n1662), .A1(n758), .B0(n1248), .Y(n1220) );
NAND2X4TS U2246 ( .A(n971), .B(intDY[7]), .Y(n2140) );
NAND2X4TS U2247 ( .A(n971), .B(intDY[5]), .Y(n2376) );
NAND2X4TS U2248 ( .A(n908), .B(n1239), .Y(n2373) );
MX2X6TS U2249 ( .A(n2842), .B(n2841), .S0(n2840), .Y(n693) );
NAND2X2TS U2250 ( .A(n1350), .B(intDX[0]), .Y(n2607) );
OR3X6TS U2251 ( .A(n1227), .B(n1228), .C(n1229), .Y(n528) );
AND2X4TS U2252 ( .A(n1433), .B(intDX[30]), .Y(n1227) );
AND2X4TS U2253 ( .A(n1351), .B(intDY[30]), .Y(n1229) );
NAND2X2TS U2254 ( .A(n1352), .B(intDY[18]), .Y(n2116) );
NAND2X2TS U2255 ( .A(n1352), .B(intDY[1]), .Y(n2107) );
NAND2X2TS U2256 ( .A(n1352), .B(intDY[20]), .Y(n2119) );
NAND2X4TS U2257 ( .A(n809), .B(n1233), .Y(n1230) );
NAND2X4TS U2258 ( .A(n1351), .B(intDY[21]), .Y(n1231) );
CLKINVX12TS U2259 ( .A(n906), .Y(n1351) );
NAND3BX4TS U2260 ( .AN(n1232), .B(n1792), .C(n1793), .Y(n590) );
NAND2X4TS U2261 ( .A(intDY[30]), .B(n1434), .Y(n1796) );
NOR2X8TS U2262 ( .A(n2790), .B(intDX[3]), .Y(n1696) );
NAND4X2TS U2263 ( .A(n2456), .B(n2455), .C(n2454), .D(n2453), .Y(n713) );
NAND2X2TS U2264 ( .A(n2474), .B(n1994), .Y(n2456) );
NAND4X6TS U2265 ( .A(n1964), .B(n1963), .C(n1962), .D(n1961), .Y(n2626) );
AOI2BB2X4TS U2266 ( .B0(n2076), .B1(DmP[17]), .A0N(n1121), .A1N(n2801), .Y(
n1963) );
INVX16TS U2267 ( .A(n1238), .Y(n2475) );
NAND2X2TS U2268 ( .A(n1349), .B(intDX[27]), .Y(n2120) );
MXI2X4TS U2269 ( .A(n2583), .B(n2586), .S0(n2639), .Y(n2521) );
AND2X8TS U2270 ( .A(n1598), .B(n1381), .Y(n2011) );
INVX4TS U2271 ( .A(n752), .Y(n1904) );
AOI21X2TS U2272 ( .A0(n2010), .A1(n1512), .B0(n1824), .Y(n1826) );
CLKAND2X2TS U2273 ( .A(n2258), .B(n2257), .Y(n1335) );
NAND2X2TS U2274 ( .A(n1355), .B(intDY[15]), .Y(n2333) );
NOR2X4TS U2275 ( .A(n2750), .B(n1556), .Y(n2155) );
INVX2TS U2276 ( .A(n756), .Y(n1243) );
OAI21X4TS U2277 ( .A0(n1256), .A1(n1255), .B0(n1254), .Y(n692) );
OAI2BB1X4TS U2278 ( .A0N(n2831), .A1N(n2832), .B0(n1545), .Y(overflow_flag)
);
NOR2BX4TS U2279 ( .AN(n1242), .B(n2831), .Y(n1546) );
NOR2BX4TS U2280 ( .AN(n2845), .B(n1546), .Y(n1545) );
INVX2TS U2281 ( .A(n755), .Y(n1247) );
AOI21X4TS U2282 ( .A0(n1028), .A1(n2271), .B0(n2270), .Y(n2275) );
AND3X4TS U2283 ( .A(n2844), .B(n2874), .C(n2873), .Y(underflow_flag) );
NOR2X8TS U2284 ( .A(n1718), .B(n1724), .Y(n1726) );
NOR2X8TS U2285 ( .A(n2786), .B(intDX[10]), .Y(n1718) );
CLKINVX12TS U2286 ( .A(n906), .Y(n1350) );
INVX8TS U2287 ( .A(n1415), .Y(n1261) );
INVX16TS U2288 ( .A(n1261), .Y(n1262) );
OAI21X4TS U2289 ( .A0(Exp_Operation_Module_Data_S[6]), .A1(
Exp_Operation_Module_Data_S[5]), .B0(n2260), .Y(n2875) );
NOR2X8TS U2290 ( .A(n2777), .B(intDX[17]), .Y(n1756) );
NOR2X8TS U2291 ( .A(n1925), .B(n896), .Y(n2602) );
OAI21X4TS U2292 ( .A0(n1777), .A1(n1776), .B0(n1775), .Y(n1780) );
NAND2X2TS U2293 ( .A(n1352), .B(intDX[30]), .Y(n1794) );
INVX2TS U2294 ( .A(n2788), .Y(n1457) );
XOR2X4TS U2295 ( .A(n1512), .B(n1286), .Y(n1576) );
NAND2X2TS U2296 ( .A(n896), .B(n1925), .Y(n1272) );
OR2X8TS U2297 ( .A(n1028), .B(n1608), .Y(n1391) );
NOR2X4TS U2298 ( .A(n2772), .B(n1297), .Y(n1267) );
AOI2BB2X4TS U2299 ( .B0(n1433), .B1(n2384), .A0N(n1399), .A1N(n1422), .Y(
n2106) );
NAND2X2TS U2300 ( .A(n1352), .B(intDY[16]), .Y(n2308) );
NAND4X2TS U2301 ( .A(n1862), .B(n1861), .C(n1860), .D(n1859), .Y(n1863) );
XNOR2X4TS U2302 ( .A(n913), .B(n1808), .Y(n1816) );
NAND2X4TS U2303 ( .A(n1349), .B(intDY[19]), .Y(n2341) );
NAND2X4TS U2304 ( .A(n1940), .B(n1939), .Y(n2653) );
AND2X4TS U2305 ( .A(n1433), .B(n791), .Y(n1276) );
XNOR2X4TS U2306 ( .A(n1278), .B(n1014), .Y(n2175) );
AOI22X2TS U2307 ( .A0(n1343), .A1(n2614), .B0(n2518), .B1(n2584), .Y(n2484)
);
NAND2BX4TS U2308 ( .AN(n2236), .B(n2226), .Y(n1282) );
NOR3BX2TS U2309 ( .AN(n1284), .B(Add_Subt_result[12]), .C(
Add_Subt_result[13]), .Y(n1547) );
AND2X8TS U2310 ( .A(intDY[18]), .B(n1289), .Y(n1459) );
AND2X8TS U2311 ( .A(intDY[11]), .B(n1294), .Y(n1724) );
NOR2X4TS U2312 ( .A(n1751), .B(n1756), .Y(n1752) );
NOR2X2TS U2313 ( .A(n1755), .B(intDX[16]), .Y(n1751) );
BUFX12TS U2314 ( .A(n1329), .Y(n1328) );
MXI2X2TS U2315 ( .A(n1300), .B(n1413), .S0(n2395), .Y(n2396) );
OAI21X4TS U2316 ( .A0(n1733), .A1(n1732), .B0(n1731), .Y(n1734) );
NAND2X2TS U2317 ( .A(n2778), .B(intDX[15]), .Y(n1731) );
NOR2X6TS U2318 ( .A(n2778), .B(intDX[15]), .Y(n1733) );
OR2X4TS U2319 ( .A(n2148), .B(n1306), .Y(n1952) );
OAI21X4TS U2320 ( .A0(n1730), .A1(n1729), .B0(n1728), .Y(n1735) );
NAND2X4TS U2321 ( .A(n883), .B(n2386), .Y(n2408) );
OAI21X4TS U2322 ( .A0(n1724), .A1(n1723), .B0(n1722), .Y(n1725) );
NAND2X8TS U2323 ( .A(n1580), .B(n1581), .Y(n1512) );
NAND2X2TS U2324 ( .A(n1488), .B(n2641), .Y(n2080) );
NOR2X1TS U2325 ( .A(n1262), .B(n2746), .Y(n2150) );
CLKMX2X4TS U2326 ( .A(DMP[3]), .B(n1318), .S0(n1262), .Y(n1927) );
NAND2X8TS U2327 ( .A(n1244), .B(n1647), .Y(n1310) );
OAI21X4TS U2328 ( .A0(n1704), .A1(n1703), .B0(n1702), .Y(n1710) );
NOR2X8TS U2329 ( .A(n1747), .B(n1782), .Y(n1786) );
OAI2BB1X4TS U2330 ( .A0N(n1311), .A1N(n1312), .B0(n1905), .Y(n1910) );
AND2X4TS U2331 ( .A(n1250), .B(n1904), .Y(n1311) );
NAND2X2TS U2332 ( .A(n2781), .B(intDX[29]), .Y(n1775) );
XOR2X1TS U2333 ( .A(intDY[29]), .B(intDX[29]), .Y(n1851) );
NAND2X2TS U2334 ( .A(n961), .B(n1612), .Y(n1611) );
NOR2X4TS U2335 ( .A(n2784), .B(intDX[2]), .Y(n1693) );
NAND2X4TS U2336 ( .A(n2771), .B(intDX[14]), .Y(n1732) );
NAND4X2TS U2337 ( .A(n2438), .B(n2437), .C(n2436), .D(n2435), .Y(n703) );
NAND4X2TS U2338 ( .A(n2083), .B(n2082), .C(n2080), .D(n2081), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
NAND2X2TS U2339 ( .A(n2780), .B(n1236), .Y(n1705) );
OAI21X4TS U2340 ( .A0(n1707), .A1(n1706), .B0(n1705), .Y(n1708) );
NAND2X2TS U2341 ( .A(n2779), .B(intDX[11]), .Y(n1722) );
OAI21X4TS U2342 ( .A0(n1767), .A1(n1766), .B0(n1765), .Y(n1785) );
AOI21X4TS U2343 ( .A0(n1764), .A1(n1763), .B0(n1762), .Y(n1765) );
NAND3X4TS U2344 ( .A(n1589), .B(n2290), .C(n1576), .Y(n1539) );
INVX16TS U2345 ( .A(n1322), .Y(n1934) );
XNOR2X2TS U2346 ( .A(intDY[21]), .B(n809), .Y(n1855) );
CLKMX2X4TS U2347 ( .A(DMP[0]), .B(n1314), .S0(n1262), .Y(n1921) );
NAND2X2TS U2348 ( .A(n2774), .B(intDX[27]), .Y(n1770) );
OAI21X4TS U2349 ( .A0(n1772), .A1(n1771), .B0(n1770), .Y(n1773) );
NAND2X2TS U2350 ( .A(n2792), .B(n801), .Y(n1776) );
NOR2X4TS U2351 ( .A(n2792), .B(n801), .Y(n1745) );
NAND2X4TS U2352 ( .A(n1349), .B(n801), .Y(n1789) );
NAND2X4TS U2353 ( .A(n1186), .B(n835), .Y(n2621) );
NAND4X2TS U2354 ( .A(n2593), .B(n2595), .C(n2594), .D(n2596), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
NOR2X6TS U2355 ( .A(n2184), .B(n2183), .Y(n2261) );
INVX8TS U2356 ( .A(n1466), .Y(n2262) );
NOR2X6TS U2357 ( .A(n2788), .B(n1301), .Y(n1460) );
INVX2TS U2358 ( .A(DmP[29]), .Y(n1527) );
INVX2TS U2359 ( .A(DmP[13]), .Y(n1361) );
NAND2X4TS U2360 ( .A(n1970), .B(n1969), .Y(n1982) );
NAND2X1TS U2361 ( .A(n1330), .B(n891), .Y(n1552) );
NOR3X2TS U2362 ( .A(n2096), .B(n2095), .C(n2094), .Y(n2393) );
NAND3X2TS U2363 ( .A(n1480), .B(n1564), .C(n2167), .Y(n1467) );
INVX2TS U2364 ( .A(n2187), .Y(n1632) );
NAND2X4TS U2365 ( .A(n849), .B(n2591), .Y(n2065) );
NAND4X4TS U2366 ( .A(n2047), .B(n2046), .C(n2045), .D(n2044), .Y(n2615) );
NAND2X2TS U2367 ( .A(n1020), .B(Add_Subt_result[4]), .Y(n2058) );
INVX6TS U2368 ( .A(n1983), .Y(n2562) );
NAND2X2TS U2369 ( .A(n2773), .B(n1303), .Y(n1473) );
INVX2TS U2370 ( .A(n2777), .Y(n1462) );
NAND2X2TS U2371 ( .A(intDX[16]), .B(n1755), .Y(n1463) );
INVX4TS U2372 ( .A(n1809), .Y(n1536) );
NAND2X4TS U2373 ( .A(n1807), .B(n1878), .Y(n1582) );
NAND2X2TS U2374 ( .A(n1820), .B(DmP[27]), .Y(n1807) );
NAND2X2TS U2375 ( .A(n1820), .B(DmP[25]), .Y(n1584) );
NOR2X6TS U2376 ( .A(n1883), .B(n1882), .Y(n2387) );
INVX4TS U2377 ( .A(n2251), .Y(n1594) );
OAI22X2TS U2378 ( .A0(n1066), .A1(n2761), .B0(n2449), .B1(n2729), .Y(n2444)
);
NAND2BX2TS U2379 ( .AN(n1506), .B(intAS), .Y(n1497) );
OAI22X2TS U2380 ( .A0(n1066), .A1(n2762), .B0(n2449), .B1(n2723), .Y(n2439)
);
INVX2TS U2381 ( .A(n2190), .Y(n2192) );
INVX2TS U2382 ( .A(n1643), .Y(n1619) );
INVX2TS U2383 ( .A(n2272), .Y(n2263) );
INVX2TS U2384 ( .A(n2264), .Y(n1409) );
NOR2X4TS U2385 ( .A(n2239), .B(n2241), .Y(n1610) );
NAND2X2TS U2386 ( .A(n959), .B(Add_Subt_result[8]), .Y(n2040) );
MXI2X1TS U2387 ( .A(n1519), .B(n2781), .S0(n1513), .Y(n621) );
MXI2X1TS U2388 ( .A(n1518), .B(n2772), .S0(n1424), .Y(n593) );
NAND2X2TS U2389 ( .A(n2791), .B(n1304), .Y(n1702) );
AND2X4TS U2390 ( .A(n1866), .B(n1865), .Y(n1867) );
NOR2X4TS U2391 ( .A(n2667), .B(n1936), .Y(n1947) );
NOR2X4TS U2392 ( .A(n2660), .B(n2659), .Y(n2662) );
INVX2TS U2393 ( .A(n1956), .Y(n1573) );
INVX2TS U2394 ( .A(n1397), .Y(n1441) );
NAND2BX1TS U2395 ( .AN(n1537), .B(n1649), .Y(n1548) );
INVX2TS U2396 ( .A(n1497), .Y(n1503) );
NOR3X4TS U2397 ( .A(n1501), .B(n1514), .C(n1505), .Y(n1504) );
NAND4X2TS U2398 ( .A(n2578), .B(n2577), .C(n2576), .D(n2575), .Y(n725) );
NAND2X2TS U2399 ( .A(n1956), .B(n1534), .Y(n2645) );
NAND2X1TS U2400 ( .A(n2592), .B(n2591), .Y(n2593) );
NAND2X2TS U2401 ( .A(n2535), .B(DmP[29]), .Y(n2091) );
NAND2X2TS U2402 ( .A(n2535), .B(DmP[27]), .Y(n1874) );
NAND2X2TS U2403 ( .A(n2535), .B(DmP[28]), .Y(n1877) );
NAND2X2TS U2404 ( .A(n2334), .B(DMP[22]), .Y(n2124) );
NAND2X1TS U2405 ( .A(n1358), .B(intDX[4]), .Y(n2368) );
NAND2X2TS U2406 ( .A(n778), .B(intDX[6]), .Y(n2365) );
NAND2X2TS U2407 ( .A(n2597), .B(DmP[24]), .Y(n2296) );
NAND2X2TS U2408 ( .A(n2610), .B(DMP[5]), .Y(n2375) );
NAND2X2TS U2409 ( .A(n2610), .B(DMP[7]), .Y(n2139) );
NAND2X2TS U2410 ( .A(n2610), .B(DMP[8]), .Y(n2372) );
NAND2X1TS U2411 ( .A(n1351), .B(n1303), .Y(n2377) );
MXI2X1TS U2412 ( .A(n1517), .B(n1401), .S0(n1424), .Y(n655) );
MXI2X1TS U2413 ( .A(n1520), .B(n1635), .S0(n1513), .Y(n622) );
NAND4BX2TS U2414 ( .AN(n2413), .B(n2412), .C(n2411), .D(n2410), .Y(n761) );
NAND2X1TS U2415 ( .A(n2338), .B(DmP[6]), .Y(n2304) );
NAND2X1TS U2416 ( .A(n2338), .B(DmP[10]), .Y(n2310) );
NAND2X1TS U2417 ( .A(n2338), .B(DmP[14]), .Y(n2313) );
NAND2X1TS U2418 ( .A(n2338), .B(DmP[15]), .Y(n2332) );
NAND2X1TS U2419 ( .A(n2338), .B(DmP[16]), .Y(n2307) );
NAND2X1TS U2420 ( .A(n2338), .B(DmP[19]), .Y(n2340) );
NAND2X1TS U2421 ( .A(n2338), .B(DmP[22]), .Y(n2292) );
NAND2X2TS U2422 ( .A(n2597), .B(n1226), .Y(n2599) );
NAND2X2TS U2423 ( .A(n2610), .B(DMP[1]), .Y(n2612) );
NAND2X1TS U2424 ( .A(n2535), .B(DMP[24]), .Y(n2363) );
NAND2X1TS U2425 ( .A(n2535), .B(DMP[25]), .Y(n1800) );
NAND2X1TS U2426 ( .A(n2535), .B(n820), .Y(n1798) );
NAND2X1TS U2427 ( .A(n2535), .B(n807), .Y(n2121) );
NAND2X2TS U2428 ( .A(n2561), .B(n2591), .Y(n2567) );
NAND4X2TS U2429 ( .A(n2051), .B(n2049), .C(n2048), .D(n2050), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
NAND2X2TS U2430 ( .A(n2615), .B(n2641), .Y(n2048) );
CLKINVX3TS U2431 ( .A(rst), .Y(n1427) );
BUFX3TS U2432 ( .A(n2857), .Y(n2859) );
MXI2X2TS U2433 ( .A(n2515), .B(n2514), .S0(n2639), .Y(n2516) );
OA22X4TS U2434 ( .A0(n1009), .A1(n2731), .B0(n1453), .B1(n867), .Y(n1985) );
NAND2X4TS U2435 ( .A(n1938), .B(n1403), .Y(n2649) );
NOR2X6TS U2436 ( .A(n2791), .B(n1304), .Y(n1704) );
NOR2X4TS U2437 ( .A(n1240), .B(intDX[8]), .Y(n1717) );
CLKMX2X3TS U2438 ( .A(Data_X[6]), .B(intDX[6]), .S0(n1513), .Y(n631) );
BUFX12TS U2439 ( .A(n918), .Y(n1538) );
NAND2X6TS U2440 ( .A(n813), .B(n1602), .Y(n2016) );
OR2X4TS U2441 ( .A(n2675), .B(n2023), .Y(n1592) );
XNOR2X4TS U2442 ( .A(n2259), .B(n1335), .Y(n1334) );
NAND2X2TS U2443 ( .A(n871), .B(n1331), .Y(n1787) );
NAND2X4TS U2444 ( .A(n1406), .B(Add_Subt_result[9]), .Y(n2037) );
XNOR2X4TS U2445 ( .A(n2259), .B(n1335), .Y(Exp_Operation_Module_Data_S[6])
);
NAND2X2TS U2446 ( .A(n1446), .B(n1283), .Y(n1673) );
OR2X8TS U2447 ( .A(n2515), .B(n2000), .Y(n2576) );
CLKBUFX2TS U2448 ( .A(n2018), .Y(n1338) );
XNOR2X4TS U2449 ( .A(n2253), .B(n1342), .Y(n1336) );
XNOR2X4TS U2450 ( .A(n857), .B(n1337), .Y(n1814) );
NOR3X6TS U2451 ( .A(n1576), .B(n2288), .C(n2290), .Y(n2289) );
XNOR2X4TS U2452 ( .A(n1593), .B(n1340), .Y(n1420) );
INVX2TS U2453 ( .A(n1346), .Y(n1347) );
AND2X8TS U2454 ( .A(n1511), .B(n2013), .Y(n1348) );
CLKINVX12TS U2455 ( .A(n1197), .Y(n1357) );
AOI22X4TS U2456 ( .A0(DmP[1]), .A1(n2043), .B0(n1020), .B1(n1092), .Y(n1895)
);
NAND4X4TS U2457 ( .A(n1903), .B(n1900), .C(n1902), .D(n1901), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
NAND2X2TS U2458 ( .A(n2626), .B(n2637), .Y(n2623) );
NAND2X2TS U2459 ( .A(n2626), .B(n2639), .Y(n1979) );
OA22X2TS U2460 ( .A0(n1364), .A1(n2434), .B0(n2508), .B1(n2765), .Y(n2489)
);
INVX4TS U2461 ( .A(n2434), .Y(n2499) );
AOI2BB2X4TS U2462 ( .B0(n1122), .B1(Add_Subt_result[10]), .A0N(n1361), .A1N(
n1971), .Y(n1964) );
NAND2X2TS U2463 ( .A(n960), .B(n754), .Y(n1969) );
NAND2X4TS U2464 ( .A(n2642), .B(n834), .Y(n1901) );
OA22X2TS U2465 ( .A0(n1238), .A1(n1451), .B0(n2110), .B1(n1364), .Y(n2578)
);
NAND2X2TS U2466 ( .A(n2642), .B(n2637), .Y(n2083) );
NAND2X2TS U2467 ( .A(n2632), .B(n2614), .Y(n2619) );
NAND4X4TS U2468 ( .A(n2042), .B(n2041), .C(n850), .D(n2040), .Y(n2632) );
NAND2X2TS U2469 ( .A(n959), .B(n753), .Y(n1988) );
AOI22X2TS U2470 ( .A0(n836), .A1(n1454), .B0(n2555), .B1(n1441), .Y(n2502)
);
NAND2X4TS U2471 ( .A(n1919), .B(n871), .Y(n2093) );
NOR2X2TS U2472 ( .A(n871), .B(n1330), .Y(n2385) );
OAI21X1TS U2473 ( .A0(n2847), .A1(n1331), .B0(n1448), .Y(n2409) );
OR2X6TS U2474 ( .A(n1814), .B(n1813), .Y(n1366) );
NOR2X4TS U2475 ( .A(n1331), .B(n789), .Y(n1506) );
CLKINVX3TS U2476 ( .A(rst), .Y(n1430) );
INVX2TS U2477 ( .A(n1506), .Y(n1501) );
NAND2X4TS U2478 ( .A(n865), .B(n2603), .Y(n2643) );
BUFX3TS U2479 ( .A(n2865), .Y(n2857) );
AND2X8TS U2480 ( .A(n2097), .B(n1870), .Y(n1371) );
BUFX20TS U2481 ( .A(n1448), .Y(n1447) );
BUFX20TS U2482 ( .A(n1448), .Y(n1424) );
BUFX12TS U2483 ( .A(n1448), .Y(n1513) );
AND2X8TS U2484 ( .A(n2170), .B(n2169), .Y(n1378) );
XNOR2X4TS U2485 ( .A(n2182), .B(n1538), .Y(n1382) );
AND2X4TS U2486 ( .A(n1919), .B(n2385), .Y(ready) );
NAND3X6TS U2487 ( .A(n1494), .B(n1376), .C(n2432), .Y(n2486) );
OR3X6TS U2488 ( .A(n1504), .B(n1503), .C(n1502), .Y(n1387) );
NOR2X6TS U2489 ( .A(n2261), .B(n2266), .Y(n2186) );
AND2X2TS U2490 ( .A(n2654), .B(n2653), .Y(n1395) );
AND2X2TS U2491 ( .A(n2649), .B(n1636), .Y(n1396) );
INVX2TS U2492 ( .A(n1560), .Y(n2227) );
NAND2BX4TS U2493 ( .AN(n2748), .B(n2394), .Y(n1405) );
NAND2X2TS U2494 ( .A(n2016), .B(n2015), .Y(n2017) );
MXI2X4TS U2495 ( .A(n2836), .B(n2835), .S0(n2834), .Y(n1408) );
MX2X2TS U2496 ( .A(n1588), .B(exp_oper_result[2]), .S0(n1442), .Y(n697) );
NOR2X4TS U2497 ( .A(n1748), .B(n1758), .Y(n1750) );
OAI2BB1X4TS U2498 ( .A0N(n1628), .A1N(n1410), .B0(n2242), .Y(n748) );
NOR2X4TS U2499 ( .A(n1556), .B(n2751), .Y(n2154) );
NOR2X4TS U2500 ( .A(n1541), .B(n1418), .Y(n1924) );
NAND2X8TS U2501 ( .A(n2012), .B(n2014), .Y(n1511) );
NAND2X2TS U2502 ( .A(n2415), .B(n2414), .Y(n2417) );
AOI2BB2X2TS U2503 ( .B0(n1352), .B1(intDX[31]), .A0N(n817), .A1N(n1412), .Y(
n2105) );
NAND2X2TS U2504 ( .A(n2638), .B(n2639), .Y(n2082) );
NAND2X2TS U2505 ( .A(n2632), .B(n2639), .Y(n2050) );
NAND2X2TS U2506 ( .A(n2626), .B(n2641), .Y(n2628) );
OAI21X2TS U2507 ( .A0(n2255), .A1(n2256), .B0(n2257), .Y(n1818) );
NAND2X6TS U2508 ( .A(n1746), .B(n1779), .Y(n1782) );
NAND2X4TS U2509 ( .A(n1650), .B(n1455), .Y(n1916) );
XOR2X4TS U2510 ( .A(n918), .B(n1419), .Y(n1567) );
NOR2X2TS U2511 ( .A(n1319), .B(n1934), .Y(n1419) );
NAND2X2TS U2512 ( .A(n2789), .B(n1309), .Y(n1728) );
NOR2X6TS U2513 ( .A(n2789), .B(n1309), .Y(n1730) );
BUFX4TS U2514 ( .A(n1931), .Y(n1535) );
NOR2X4TS U2515 ( .A(n1885), .B(n1264), .Y(n1883) );
NAND2X2TS U2516 ( .A(n2785), .B(intDX[26]), .Y(n1771) );
NOR2X4TS U2517 ( .A(n2785), .B(intDX[26]), .Y(n1743) );
AOI22X2TS U2518 ( .A0(n1343), .A1(n832), .B0(n2581), .B1(n2584), .Y(n2480)
);
AOI21X4TS U2519 ( .A0(n1709), .A1(n1710), .B0(n1708), .Y(n1711) );
OR2X4TS U2520 ( .A(n912), .B(n1527), .Y(n1605) );
NAND2X2TS U2521 ( .A(n2631), .B(n2637), .Y(n2051) );
AOI21X4TS U2522 ( .A0(n1780), .A1(n1779), .B0(n1778), .Y(n1781) );
NOR2X2TS U2523 ( .A(n2794), .B(n1305), .Y(n1748) );
NAND2X2TS U2524 ( .A(n2782), .B(n1260), .Y(n1729) );
NOR2X2TS U2525 ( .A(n2782), .B(n1260), .Y(n1714) );
NOR2X4TS U2526 ( .A(n2264), .B(n2268), .Y(n2265) );
XOR2X4TS U2527 ( .A(n1593), .B(n1380), .Y(n1421) );
NAND2X2TS U2528 ( .A(n2586), .B(n2562), .Y(n2063) );
MXI2X4TS U2529 ( .A(n1332), .B(n2728), .S0(n1442), .Y(n696) );
NAND2X4TS U2530 ( .A(n1377), .B(LZA_output[4]), .Y(n1878) );
MX2X4TS U2531 ( .A(Data_X[3]), .B(n791), .S0(n1435), .Y(n628) );
BUFX20TS U2532 ( .A(n2397), .Y(n1448) );
AOI22X2TS U2533 ( .A0(n1280), .A1(n2540), .B0(n1122), .B1(n733), .Y(n2538)
);
BUFX4TS U2534 ( .A(n2294), .Y(n1422) );
NOR2X8TS U2535 ( .A(n1997), .B(n1787), .Y(n2383) );
INVX3TS U2536 ( .A(rst), .Y(n1440) );
NAND2X2TS U2537 ( .A(n830), .B(Add_Subt_result[9]), .Y(n1530) );
NAND2X2TS U2538 ( .A(n1426), .B(n1283), .Y(n2242) );
NAND2X2TS U2539 ( .A(n1357), .B(intDX[10]), .Y(n2348) );
CLKINVX3TS U2540 ( .A(rst), .Y(n1432) );
INVX3TS U2541 ( .A(rst), .Y(n1437) );
INVX3TS U2542 ( .A(rst), .Y(n1438) );
INVX3TS U2543 ( .A(rst), .Y(n1439) );
MX2X4TS U2544 ( .A(n2647), .B(Add_Subt_result[6]), .S0(n2848), .Y(n740) );
MX2X4TS U2545 ( .A(n1960), .B(Add_Subt_result[7]), .S0(n2848), .Y(n741) );
INVX2TS U2546 ( .A(rst), .Y(n1444) );
AOI2BB2X2TS U2547 ( .B0(n1445), .B1(n1245), .A0N(n2398), .A1N(
final_result_ieee[30]), .Y(n682) );
AO22X2TS U2548 ( .A0(n1445), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[13]), .B1(n2401), .Y(n668) );
AO22X2TS U2549 ( .A0(n2402), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[11]), .B1(n2401), .Y(n670) );
AO22X2TS U2550 ( .A0(n2400), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[12]), .B1(n2401), .Y(n669) );
AO22X2TS U2551 ( .A0(n2400), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[15]), .B1(n2401), .Y(n666) );
AO22X2TS U2552 ( .A0(n1445), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[16]), .B1(n2674), .Y(n665) );
AO22X2TS U2553 ( .A0(n2402), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[17]), .B1(n2401), .Y(n664) );
AO22X2TS U2554 ( .A0(n2400), .A1(Sgf_normalized_result[21]), .B0(
final_result_ieee[19]), .B1(n2674), .Y(n662) );
AO22X2TS U2555 ( .A0(n1445), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[18]), .B1(n2674), .Y(n663) );
AO22X2TS U2556 ( .A0(n1445), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[14]), .B1(n2401), .Y(n667) );
AO22X2TS U2557 ( .A0(n2402), .A1(Sgf_normalized_result[23]), .B0(
final_result_ieee[21]), .B1(n2674), .Y(n660) );
AO22X2TS U2558 ( .A0(n2400), .A1(Sgf_normalized_result[24]), .B0(
final_result_ieee[22]), .B1(n2674), .Y(n659) );
AO22X2TS U2559 ( .A0(n2402), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[20]), .B1(n2674), .Y(n661) );
NAND2X2TS U2560 ( .A(n1349), .B(intDX[17]), .Y(n2359) );
NAND2X2TS U2561 ( .A(n1357), .B(intDX[18]), .Y(n2345) );
NAND2X2TS U2562 ( .A(n1358), .B(intDX[11]), .Y(n2102) );
NAND2X2TS U2563 ( .A(n1446), .B(Add_Subt_result[10]), .Y(n2045) );
NAND2X2TS U2564 ( .A(n1446), .B(Add_Subt_result[3]), .Y(n1893) );
INVX2TS U2565 ( .A(n1449), .Y(n1450) );
INVX2TS U2566 ( .A(n1451), .Y(n1452) );
OAI21X1TS U2567 ( .A0(n2388), .A1(n2098), .B0(n891), .Y(n2099) );
NAND2X1TS U2568 ( .A(n2338), .B(DmP[18]), .Y(n2115) );
AOI22X2TS U2569 ( .A0(n1104), .A1(Add_Subt_result[5]), .B0(DmP[18]), .B1(
n1264), .Y(n1970) );
NAND2X1TS U2570 ( .A(n2338), .B(DmP[20]), .Y(n2118) );
NAND2X1TS U2571 ( .A(n2334), .B(DmP[1]), .Y(n2108) );
AOI22X2TS U2572 ( .A0(n2475), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n2555), .B1(n1359), .Y(n2513) );
NAND2X2TS U2573 ( .A(n2509), .B(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n2441) );
MXI2X4TS U2574 ( .A(n1516), .B(n1399), .S0(n1513), .Y(n624) );
NOR2X8TS U2575 ( .A(n2011), .B(n1509), .Y(n1597) );
AOI22X2TS U2576 ( .A0(n2591), .A1(n2517), .B0(n2581), .B1(n2614), .Y(n2520)
);
NOR2X6TS U2577 ( .A(n1815), .B(n1816), .Y(n2252) );
NOR2X8TS U2578 ( .A(n2208), .B(n2176), .Y(n2219) );
AOI22X2TS U2579 ( .A0(n832), .A1(n2517), .B0(n2581), .B1(n2503), .Y(n2281)
);
NOR2X4TS U2580 ( .A(n1737), .B(n1720), .Y(n1740) );
AOI21X4TS U2581 ( .A0(n1461), .A1(n1757), .B0(n1456), .Y(n1767) );
OAI22X4TS U2582 ( .A0(n1460), .A1(n1458), .B0(n1457), .B1(n1302), .Y(n1456)
);
NOR2X8TS U2583 ( .A(n1460), .B(n1459), .Y(n1757) );
OAI22X4TS U2584 ( .A0(n1756), .A1(n1463), .B0(n1462), .B1(n1379), .Y(n1461)
);
OA21X4TS U2585 ( .A0(n2190), .A1(n2205), .B0(n2191), .Y(n1466) );
NAND2X4TS U2586 ( .A(n2238), .B(n851), .Y(n1469) );
NAND2X2TS U2587 ( .A(n2172), .B(n2171), .Y(n2195) );
NAND2X8TS U2588 ( .A(n1378), .B(n1645), .Y(n1472) );
OAI21X4TS U2589 ( .A0(n1721), .A1(n1474), .B0(n1473), .Y(n1727) );
NAND2X8TS U2590 ( .A(n1477), .B(n1476), .Y(n2216) );
XOR2X4TS U2591 ( .A(n1478), .B(n1014), .Y(n2158) );
NAND2X8TS U2592 ( .A(n2267), .B(n1479), .Y(n2187) );
NOR2X8TS U2593 ( .A(n1484), .B(n1482), .Y(n2259) );
OAI21X4TS U2594 ( .A0(n1483), .A1(n861), .B0(n2255), .Y(n1482) );
NAND2X1TS U2595 ( .A(n1488), .B(n2637), .Y(n2636) );
NOR2BX4TS U2596 ( .AN(n1977), .B(n1393), .Y(n1490) );
INVX12TS U2597 ( .A(n1493), .Y(n2452) );
NAND2X1TS U2598 ( .A(n1506), .B(n2097), .Y(n2391) );
NOR2X8TS U2599 ( .A(n2252), .B(n2256), .Y(n1819) );
NAND2X2TS U2600 ( .A(n2583), .B(n2282), .Y(n2284) );
OAI21X4TS U2601 ( .A0(n1531), .A1(n830), .B0(n1530), .Y(n743) );
XOR2X4TS U2602 ( .A(n2650), .B(n1396), .Y(n1531) );
OAI21X4TS U2603 ( .A0(n1533), .A1(n830), .B0(n1532), .Y(n744) );
XOR2X4TS U2604 ( .A(n2655), .B(n1395), .Y(n1533) );
OR2X8TS U2605 ( .A(n1613), .B(n2241), .Y(n1608) );
AOI22X2TS U2606 ( .A0(DmP[12]), .A1(n2043), .B0(n1020), .B1(
Add_Subt_result[11]), .Y(n1675) );
NAND2X2TS U2607 ( .A(n1186), .B(n2589), .Y(n1992) );
NAND4X2TS U2608 ( .A(n2576), .B(n2553), .C(n2552), .D(n2551), .Y(n765) );
INVX2TS U2609 ( .A(n1542), .Y(n1955) );
OR2X4TS U2610 ( .A(n1687), .B(n1686), .Y(n2280) );
MXI2X4TS U2611 ( .A(n2736), .B(n1245), .S0(n1822), .Y(n1823) );
NAND2X2TS U2612 ( .A(n2624), .B(n2637), .Y(n2630) );
MXI2X4TS U2613 ( .A(n2738), .B(n1408), .S0(n1822), .Y(n1815) );
INVX16TS U2614 ( .A(n1265), .Y(n2555) );
NAND4X2TS U2615 ( .A(n2576), .B(n2559), .C(n2558), .D(n2557), .Y(n727) );
NAND2X2TS U2616 ( .A(n2517), .B(n2589), .Y(n2504) );
NAND2X2TS U2617 ( .A(n1446), .B(n755), .Y(n2059) );
AOI22X2TS U2618 ( .A0(DmP[6]), .A1(n2043), .B0(n1020), .B1(n751), .Y(n2042)
);
BUFX20TS U2619 ( .A(n1934), .Y(n1541) );
OR2X8TS U2620 ( .A(n2172), .B(n2171), .Y(n1645) );
NAND2X2TS U2621 ( .A(n2563), .B(n2589), .Y(n2564) );
NAND4X2TS U2622 ( .A(n2636), .B(n2635), .C(n2634), .D(n2633), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
NAND2X2TS U2623 ( .A(n2590), .B(n2589), .Y(n1967) );
NAND2X4TS U2624 ( .A(n2097), .B(n1646), .Y(n2395) );
AOI2BB2X4TS U2625 ( .B0(n2540), .B1(DmP[4]), .A0N(n1250), .A1N(n1121), .Y(
n2246) );
NAND2X8TS U2626 ( .A(n2097), .B(n1881), .Y(n1886) );
NAND4BX2TS U2627 ( .AN(n1495), .B(n2498), .C(n2497), .D(n2496), .Y(n709) );
NAND2X2TS U2628 ( .A(n2561), .B(n2589), .Y(n1902) );
NAND2X2TS U2629 ( .A(n2624), .B(n2639), .Y(n2622) );
NOR2X6TS U2630 ( .A(n1761), .B(n1749), .Y(n1763) );
NOR2X4TS U2631 ( .A(n815), .B(n2394), .Y(n2404) );
OAI21X4TS U2632 ( .A0(n1783), .A1(n1782), .B0(n1781), .Y(n1784) );
NAND2X2TS U2633 ( .A(n2243), .B(n1283), .Y(n2044) );
OAI21X4TS U2634 ( .A0(n1738), .A1(n1737), .B0(n1736), .Y(n1739) );
NAND2X2TS U2635 ( .A(n2631), .B(n2641), .Y(n2616) );
AOI2BB2X4TS U2636 ( .B0(n2540), .B1(DmP[11]), .A0N(n1121), .A1N(n2759), .Y(
n2038) );
NOR2X2TS U2637 ( .A(n1262), .B(n2745), .Y(n1948) );
NOR2X8TS U2638 ( .A(n2180), .B(n2181), .Y(n2190) );
NAND2X4TS U2639 ( .A(n1719), .B(n1726), .Y(n1720) );
NAND2X4TS U2640 ( .A(n2770), .B(intDX[22]), .Y(n1760) );
NAND4BX2TS U2641 ( .AN(n1495), .B(n2513), .C(n2512), .D(n2511), .Y(n705) );
AOI21X4TS U2642 ( .A0(n1275), .A1(n1819), .B0(n1818), .Y(n1581) );
NAND2X2TS U2643 ( .A(n2243), .B(Add_Subt_result[9]), .Y(n1898) );
NAND2X2TS U2644 ( .A(n2542), .B(Add_Subt_result[10]), .Y(n1896) );
OAI21X4TS U2645 ( .A0(beg_FSM), .A1(n656), .B0(n2412), .Y(n2388) );
NAND2X6TS U2646 ( .A(n1544), .B(n893), .Y(n656) );
AOI2BB2X4TS U2647 ( .B0(n1996), .B1(n867), .A0N(n1997), .A1N(n1552), .Y(
n2023) );
NOR2X8TS U2648 ( .A(n2515), .B(n2580), .Y(n2583) );
XNOR2X4TS U2649 ( .A(n1554), .B(n1016), .Y(n1931) );
AND2X8TS U2650 ( .A(n2158), .B(n2157), .Y(n2159) );
NAND2BX4TS U2651 ( .AN(n2753), .B(n2394), .Y(n1557) );
AOI21X4TS U2652 ( .A0(n1374), .A1(n2228), .B0(n1558), .Y(n2167) );
OR2X8TS U2653 ( .A(n2164), .B(n2163), .Y(n1639) );
XNOR2X4TS U2654 ( .A(n784), .B(n1562), .Y(n2170) );
NAND2BX4TS U2655 ( .AN(n2752), .B(n2394), .Y(n1562) );
XOR2X4TS U2656 ( .A(n2153), .B(n1013), .Y(n2172) );
XOR2X4TS U2657 ( .A(n1013), .B(n1565), .Y(n2415) );
OAI21X4TS U2658 ( .A0(n2601), .A1(n1928), .B0(n2604), .Y(n1929) );
NAND2X4TS U2659 ( .A(n1567), .B(n1927), .Y(n2604) );
NOR2X8TS U2660 ( .A(n1567), .B(n1927), .Y(n1928) );
XOR2X4TS U2661 ( .A(n1014), .B(n1924), .Y(n1568) );
XNOR2X4TS U2662 ( .A(n1571), .B(n1959), .Y(n1960) );
OAI21X4TS U2663 ( .A0(n1957), .A1(n2644), .B0(n1572), .Y(n1571) );
AOI21X4TS U2664 ( .A0(n1542), .A1(n1534), .B0(n1573), .Y(n1572) );
XOR2X4TS U2665 ( .A(n857), .B(n1582), .Y(n1578) );
XOR2X4TS U2666 ( .A(n1367), .B(n1394), .Y(n2290) );
XNOR2X4TS U2667 ( .A(n813), .B(n1821), .Y(n1604) );
XOR2X4TS U2668 ( .A(n857), .B(n1812), .Y(n2018) );
NOR2X8TS U2669 ( .A(n1592), .B(n1588), .Y(n1591) );
AOI21X4TS U2670 ( .A0(n1389), .A1(n1929), .B0(n1596), .Y(n1615) );
OAI21X4TS U2671 ( .A0(n1407), .A1(n1956), .B0(n1958), .Y(n1596) );
XOR2X4TS U2672 ( .A(n2152), .B(n1538), .Y(n2181) );
NAND3X2TS U2673 ( .A(n2538), .B(n2537), .C(n2536), .Y(n2539) );
NAND4X2TS U2674 ( .A(n2630), .B(n2629), .C(n2628), .D(n2627), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
NAND4X4TS U2675 ( .A(n2289), .B(n1334), .C(n1336), .D(n1421), .Y(n2876) );
NAND2BX4TS U2676 ( .AN(n1823), .B(n1604), .Y(n2010) );
INVX2TS U2677 ( .A(n1266), .Y(n2648) );
OAI22X4TS U2678 ( .A0(n1613), .A1(n1610), .B0(n2241), .B1(n1614), .Y(n1609)
);
NAND2X2TS U2679 ( .A(n1622), .B(n1619), .Y(n1618) );
AOI21X4TS U2680 ( .A0(n961), .A1(n2219), .B0(n2215), .Y(n2218) );
AOI21X4TS U2681 ( .A0(n961), .A1(n2221), .B0(n2220), .Y(n2224) );
AOI21X4TS U2682 ( .A0(n961), .A1(n2203), .B0(n1182), .Y(n2207) );
AOI21X4TS U2683 ( .A0(n1028), .A1(n2210), .B0(n1241), .Y(n2214) );
AOI21X4TS U2684 ( .A0(n961), .A1(n2232), .B0(n2231), .Y(n2235) );
NOR2X4TS U2685 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[8]), .Y(n1660)
);
OAI21X4TS U2686 ( .A0(n1713), .A1(n1712), .B0(n1711), .Y(n1741) );
AOI2BB2X2TS U2687 ( .B0(n969), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .A0N(n2450), .A1N(
n1880), .Y(n1884) );
AOI22X2TS U2688 ( .A0(n1343), .A1(n2503), .B0(n2518), .B1(n2614), .Y(n2505)
);
NOR2X8TS U2689 ( .A(n2674), .B(n1373), .Y(n2673) );
NOR2X4TS U2690 ( .A(n2773), .B(n1303), .Y(n1721) );
NAND2X2TS U2691 ( .A(n1446), .B(n1537), .Y(n1677) );
XOR2X4TS U2692 ( .A(n2644), .B(n2533), .Y(n2534) );
AOI22X2TS U2693 ( .A0(n1443), .A1(n2517), .B0(n2518), .B1(n2503), .Y(n2481)
);
INVX8TS U2694 ( .A(n1644), .Y(n2251) );
NAND4X2TS U2695 ( .A(n2549), .B(n2548), .C(n2547), .D(n2546), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND4X2TS U2696 ( .A(n2616), .B(n2618), .C(n2617), .D(n2619), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
NOR2X4TS U2697 ( .A(n2770), .B(intDX[22]), .Y(n1749) );
AOI2BB2X2TS U2698 ( .B0(n1446), .B1(Add_Subt_result[0]), .A0N(n1107), .A1N(
n1247), .Y(n2537) );
AOI2BB2X4TS U2699 ( .B0(n2076), .B1(DmP[7]), .A0N(n1107), .A1N(n1225), .Y(
n1899) );
AOI2BB2X4TS U2700 ( .B0(n2076), .B1(DmP[13]), .A0N(n1121), .A1N(n2724), .Y(
n1669) );
AOI2BB2X4TS U2701 ( .B0(n2076), .B1(DmP[5]), .A0N(n1121), .A1N(n1904), .Y(
n1894) );
AOI2BB2X4TS U2702 ( .B0(n2540), .B1(DmP[8]), .A0N(n1107), .A1N(n2763), .Y(
n1897) );
AOI2BB2X4TS U2703 ( .B0(n2076), .B1(DmP[15]), .A0N(n1121), .A1N(n2802), .Y(
n1678) );
AOI2BB2X4TS U2704 ( .B0(n2540), .B1(DmP[12]), .A0N(n1121), .A1N(n2800), .Y(
n2046) );
AOI22X2TS U2705 ( .A0(DmP[8]), .A1(n2043), .B0(n1020), .B1(
Add_Subt_result[15]), .Y(n2047) );
AOI22X2TS U2706 ( .A0(n1104), .A1(Add_Subt_result[1]), .B0(DmP[22]), .B1(
n1264), .Y(n1981) );
NAND4X6TS U2707 ( .A(n2060), .B(n2059), .C(n2058), .D(n2057), .Y(n2586) );
NAND2X2TS U2708 ( .A(n2056), .B(DmP[14]), .Y(n1972) );
NAND2X2TS U2709 ( .A(n2385), .B(n893), .Y(n2672) );
NAND4X4TS U2710 ( .A(n1675), .B(n1674), .C(n1673), .D(n1672), .Y(n2624) );
NAND4BX2TS U2711 ( .AN(n2409), .B(n1422), .C(n2408), .D(n2674), .Y(n2413) );
BUFX20TS U2712 ( .A(n1322), .Y(n2394) );
NAND4X2TS U2713 ( .A(n2570), .B(n2569), .C(n2576), .D(n2568), .Y(n723) );
AOI22X2TS U2714 ( .A0(DmP[7]), .A1(n2056), .B0(n1020), .B1(n750), .Y(n2039)
);
NAND2X2TS U2715 ( .A(n2243), .B(n1537), .Y(n2036) );
BUFX3TS U2716 ( .A(n2870), .Y(n2869) );
CLKBUFX2TS U2717 ( .A(n2866), .Y(n2856) );
OR2X8TS U2718 ( .A(n2162), .B(n2161), .Y(n1640) );
OR2X8TS U2719 ( .A(n2170), .B(n2169), .Y(n1643) );
INVX2TS U2720 ( .A(intDY[16]), .Y(n1755) );
INVX2TS U2721 ( .A(Sgf_normalized_result[8]), .Y(n1933) );
NAND2X4TS U2722 ( .A(n2181), .B(n2180), .Y(n2191) );
NAND2X4TS U2723 ( .A(n2226), .B(n1639), .Y(n2230) );
NAND2X2TS U2724 ( .A(n2417), .B(n2416), .Y(n2418) );
NAND2X1TS U2725 ( .A(n1270), .B(n1958), .Y(n1959) );
NAND2X1TS U2726 ( .A(n2573), .B(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n2445) );
NAND2X1TS U2727 ( .A(n2509), .B(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n2454) );
NAND2X1TS U2728 ( .A(n2509), .B(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .Y(n2428) );
NOR2X8TS U2730 ( .A(n871), .B(n883), .Y(n2097) );
NOR3X4TS U2731 ( .A(n1310), .B(n752), .C(n1283), .Y(n1648) );
OAI21X1TS U2732 ( .A0(Add_Subt_result[11]), .A1(n2724), .B0(n2759), .Y(n1649) );
NOR2X8TS U2733 ( .A(Add_Subt_result[7]), .B(Add_Subt_result[6]), .Y(n1654)
);
NOR3X1TS U2734 ( .A(n1912), .B(Add_Subt_result[5]), .C(Add_Subt_result[4]),
.Y(n1651) );
INVX2TS U2735 ( .A(Add_Subt_result[0]), .Y(n1652) );
NAND2X1TS U2736 ( .A(n1455), .B(n752), .Y(n1657) );
INVX2TS U2737 ( .A(n1660), .Y(n2024) );
NOR2X2TS U2782 ( .A(n1601), .B(n1416), .Y(n1664) );
NAND2X4TS U2783 ( .A(n1820), .B(exp_oper_result[1]), .Y(n1666) );
NOR2X8TS U2784 ( .A(n2282), .B(n1680), .Y(n2637) );
NAND2X2TS U2785 ( .A(n2590), .B(n1443), .Y(n1685) );
NAND2X1TS U2786 ( .A(n2592), .B(n2589), .Y(n1684) );
NAND2X2TS U2787 ( .A(n2624), .B(n833), .Y(n1683) );
NAND4X2TS U2788 ( .A(n1685), .B(n1684), .C(n1683), .D(n1682), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
INVX2TS U2789 ( .A(n2798), .Y(n1691) );
NOR2X1TS U2790 ( .A(Add_Subt_result[11]), .B(n1537), .Y(n1686) );
OAI21X4TS U2791 ( .A0(n1689), .A1(n1688), .B0(n866), .Y(n1690) );
OAI21X4TS U2792 ( .A0(n1696), .A1(n1695), .B0(n1694), .Y(n1697) );
NOR2X4TS U2793 ( .A(n1714), .B(n1730), .Y(n1716) );
AOI21X4TS U2794 ( .A0(n1727), .A1(n1726), .B0(n1725), .Y(n1738) );
NOR2X6TS U2795 ( .A(n1745), .B(n1777), .Y(n1746) );
NAND2X4TS U2796 ( .A(n1750), .B(n1763), .Y(n1766) );
NAND2X2TS U2797 ( .A(n1752), .B(n1757), .Y(n1753) );
OAI21X2TS U2798 ( .A0(n1761), .A1(n1760), .B0(n1759), .Y(n1762) );
INVX16TS U2799 ( .A(n2383), .Y(n2294) );
NAND2X1TS U2800 ( .A(n1422), .B(DMP[29]), .Y(n1792) );
NAND2X1TS U2801 ( .A(n1422), .B(DMP[30]), .Y(n1795) );
NAND3X2TS U2802 ( .A(n1796), .B(n1795), .C(n1794), .Y(n560) );
NAND2X1TS U2803 ( .A(n930), .B(intDY[26]), .Y(n1799) );
NAND2X1TS U2804 ( .A(n1353), .B(n788), .Y(n1803) );
CLKMX2X2TS U2805 ( .A(n2836), .B(n2835), .S0(n2834), .Y(n694) );
INVX2TS U2806 ( .A(n2009), .Y(n1824) );
NOR2X4TS U2807 ( .A(n1997), .B(n1331), .Y(n1827) );
NAND2X2TS U2808 ( .A(n1829), .B(n1264), .Y(n2411) );
XNOR2X1TS U2809 ( .A(intDY[18]), .B(intDX[18]), .Y(n1839) );
XNOR2X1TS U2810 ( .A(intDY[15]), .B(intDX[15]), .Y(n1838) );
XNOR2X1TS U2811 ( .A(intDY[16]), .B(intDX[16]), .Y(n1837) );
XNOR2X1TS U2812 ( .A(intDY[12]), .B(n1260), .Y(n1841) );
XNOR2X1TS U2813 ( .A(intDY[9]), .B(n1303), .Y(n1840) );
NOR2X2TS U2814 ( .A(n1845), .B(n1844), .Y(n1846) );
XOR2X1TS U2815 ( .A(intDX[0]), .B(n885), .Y(n1853) );
XOR2X1TS U2816 ( .A(intDY[1]), .B(n1297), .Y(n1852) );
XNOR2X1TS U2817 ( .A(intDY[26]), .B(intDX[26]), .Y(n1858) );
NAND4X2TS U2818 ( .A(n1858), .B(n1857), .C(n1856), .D(n1855), .Y(n1864) );
XNOR2X1TS U2819 ( .A(intDY[22]), .B(intDX[22]), .Y(n1862) );
XNOR2X1TS U2820 ( .A(intDY[19]), .B(n1301), .Y(n1861) );
XNOR2X1TS U2821 ( .A(intDY[20]), .B(n1305), .Y(n1860) );
NAND2X8TS U2822 ( .A(n1868), .B(n1867), .Y(n2384) );
NAND2X1TS U2823 ( .A(n1030), .B(n2383), .Y(n1869) );
NAND2BX4TS U2824 ( .AN(n1872), .B(n2100), .Y(n760) );
NOR2X2TS U2825 ( .A(n893), .B(n1330), .Y(n1881) );
INVX8TS U2826 ( .A(n1681), .Y(n2641) );
INVX2TS U2827 ( .A(n1906), .Y(n1907) );
XOR2X4TS U2828 ( .A(n1014), .B(n1920), .Y(n2403) );
INVX2TS U2829 ( .A(n2667), .Y(n1946) );
NAND2X1TS U2830 ( .A(n2625), .B(n2637), .Y(n1968) );
NAND2X1TS U2831 ( .A(n2624), .B(n2641), .Y(n1965) );
NAND4X2TS U2832 ( .A(n1965), .B(n1967), .C(n1966), .D(n1968), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
NAND2X1TS U2833 ( .A(n854), .B(Add_Subt_result[7]), .Y(n1977) );
NAND2X1TS U2834 ( .A(n2056), .B(DmP[16]), .Y(n1976) );
NAND2X1TS U2835 ( .A(n2585), .B(n2591), .Y(n1991) );
NAND4X2TS U2836 ( .A(n1993), .B(n1990), .C(n1991), .D(n1992), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AND2X8TS U2837 ( .A(n2487), .B(n1994), .Y(n2574) );
NAND4X2TS U2838 ( .A(n2003), .B(n2002), .C(n2576), .D(n2001), .Y(n724) );
NAND2X1TS U2839 ( .A(n2574), .B(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .Y(n2004) );
NAND4X2TS U2840 ( .A(n2006), .B(n2005), .C(n2576), .D(n2004), .Y(n722) );
INVX2TS U2841 ( .A(n2019), .Y(n2007) );
XNOR2X4TS U2842 ( .A(n2017), .B(n1338), .Y(n2675) );
NAND2X4TS U2843 ( .A(n2023), .B(underflow_flag), .Y(n2260) );
NOR2X1TS U2844 ( .A(n2024), .B(Add_Subt_result[5]), .Y(n2027) );
NAND2X1TS U2845 ( .A(n2487), .B(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n2030) );
NAND3X4TS U2846 ( .A(n2031), .B(n2486), .C(n2030), .Y(n2529) );
NAND2X2TS U2847 ( .A(n2592), .B(n2562), .Y(n2049) );
NAND2X2TS U2848 ( .A(n2592), .B(n2614), .Y(n2055) );
NAND4X2TS U2849 ( .A(n2052), .B(n2054), .C(n2053), .D(n2055), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
NAND2X1TS U2850 ( .A(n2056), .B(DmP[19]), .Y(n2057) );
NAND2X2TS U2851 ( .A(n2585), .B(n1443), .Y(n2062) );
NAND2X2TS U2852 ( .A(n1186), .B(n1443), .Y(n2068) );
NAND4X2TS U2853 ( .A(n2068), .B(n2067), .C(n2066), .D(n2065), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
NAND2X1TS U2854 ( .A(n2574), .B(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n2069) );
NAND4X2TS U2855 ( .A(n2071), .B(n2070), .C(n2576), .D(n2069), .Y(n726) );
NAND2X1TS U2856 ( .A(n1433), .B(intDX[0]), .Y(n2074) );
NAND3X2TS U2857 ( .A(n2074), .B(n2073), .C(n2072), .Y(n529) );
NAND2X2TS U2858 ( .A(n2632), .B(n834), .Y(n2081) );
NAND2X2TS U2859 ( .A(n2334), .B(DmP[5]), .Y(n2085) );
NAND2X2TS U2860 ( .A(n2334), .B(DmP[4]), .Y(n2088) );
OAI2BB2X1TS U2861 ( .B0(n814), .B1(n1273), .A0N(r_mode[0]), .A1N(r_mode[1]),
.Y(n2094) );
OAI21X1TS U2862 ( .A0(n2393), .A1(n2391), .B0(n2847), .Y(n2101) );
NAND4BX2TS U2863 ( .AN(n2101), .B(n2100), .C(n2387), .D(n2099), .Y(n763) );
NAND2X2TS U2864 ( .A(n2358), .B(DMP[11]), .Y(n2103) );
AOI22X1TS U2865 ( .A0(n2475), .A1(n1441), .B0(n2571), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n2113) );
AOI22X1TS U2866 ( .A0(n2555), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n2554), .B1(
Sgf_normalized_result[18]), .Y(n2112) );
NAND2X1TS U2867 ( .A(n2574), .B(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n2111) );
NAND4X2TS U2868 ( .A(n2113), .B(n2112), .C(n2576), .D(n2111), .Y(n721) );
NAND3X2TS U2869 ( .A(n2120), .B(n2122), .C(n2121), .Y(n588) );
NAND2X1TS U2870 ( .A(n1434), .B(intDY[21]), .Y(n2128) );
NAND3X2TS U2871 ( .A(n2128), .B(n2127), .C(n2126), .Y(n582) );
NAND2X2TS U2872 ( .A(n2358), .B(DMP[19]), .Y(n2130) );
NAND2X2TS U2873 ( .A(n2338), .B(DMP[15]), .Y(n2133) );
NAND2X2TS U2874 ( .A(n1355), .B(n1327), .Y(n2135) );
NAND3X2TS U2875 ( .A(n2135), .B(n2136), .C(n2137), .Y(n584) );
NAND2X2TS U2876 ( .A(n2610), .B(DMP[2]), .Y(n2142) );
NAND2X2TS U2877 ( .A(n2358), .B(DMP[13]), .Y(n2145) );
XOR2X4TS U2878 ( .A(n1014), .B(n2155), .Y(n2162) );
NOR2X1TS U2879 ( .A(n1262), .B(n2742), .Y(n2182) );
XOR2X4TS U2880 ( .A(n2207), .B(n2206), .Y(Add_Subt_Sgf_module_S_to_D[22]) );
XOR2X4TS U2881 ( .A(n2214), .B(n2213), .Y(Add_Subt_Sgf_module_S_to_D[16]) );
XOR2X4TS U2882 ( .A(n2218), .B(n2217), .Y(Add_Subt_Sgf_module_S_to_D[18]) );
OAI21X4TS U2883 ( .A0(n2238), .A1(n2225), .B0(n2227), .Y(n2220) );
XOR2X4TS U2884 ( .A(n2224), .B(n2223), .Y(Add_Subt_Sgf_module_S_to_D[20]) );
OAI21X4TS U2885 ( .A0(n2238), .A1(n2230), .B0(n2229), .Y(n2231) );
XOR2X4TS U2886 ( .A(n2235), .B(n2234), .Y(Add_Subt_Sgf_module_S_to_D[21]) );
NOR2X8TS U2887 ( .A(n2236), .B(n2237), .Y(n2239) );
NAND2X2TS U2888 ( .A(n2561), .B(n2614), .Y(n2250) );
NAND2X2TS U2889 ( .A(n2638), .B(n835), .Y(n2249) );
NAND2X1TS U2890 ( .A(n959), .B(Add_Subt_result[2]), .Y(n2245) );
NAND2X1TS U2891 ( .A(n2243), .B(Add_Subt_result[6]), .Y(n2244) );
INVX2TS U2892 ( .A(n2256), .Y(n2258) );
XOR2X4TS U2893 ( .A(n2275), .B(n2274), .Y(Add_Subt_Sgf_module_S_to_D[24]) );
NAND2X1TS U2894 ( .A(n2278), .B(n2277), .Y(n2279) );
CLKINVX1TS U2895 ( .A(n2286), .Y(n2287) );
NAND2X1TS U2896 ( .A(n930), .B(intDX[22]), .Y(n2291) );
NAND3X2TS U2897 ( .A(n2291), .B(n2292), .C(n2293), .Y(n551) );
NAND2X1TS U2898 ( .A(n1356), .B(intDY[24]), .Y(n2295) );
NAND2X1TS U2899 ( .A(n1434), .B(n1260), .Y(n2302) );
NAND2X1TS U2900 ( .A(n1351), .B(intDY[12]), .Y(n2300) );
NAND3X2TS U2901 ( .A(n2302), .B(n2300), .C(n2301), .Y(n541) );
NAND2X1TS U2902 ( .A(n930), .B(intDX[6]), .Y(n2303) );
NAND3X2TS U2903 ( .A(n2303), .B(n2304), .C(n2305), .Y(n535) );
NAND2X1TS U2904 ( .A(n972), .B(n795), .Y(n2306) );
NAND3X2TS U2905 ( .A(n2306), .B(n2307), .C(n2308), .Y(n545) );
NAND2X1TS U2906 ( .A(n1434), .B(n1236), .Y(n2321) );
NAND2X1TS U2907 ( .A(n1355), .B(intDY[7]), .Y(n2319) );
NAND3X2TS U2908 ( .A(n2321), .B(n2319), .C(n2320), .Y(n536) );
NAND2X1TS U2909 ( .A(n1434), .B(intDX[11]), .Y(n2324) );
NAND2X1TS U2910 ( .A(n1356), .B(intDY[11]), .Y(n2322) );
NAND3X2TS U2911 ( .A(n2324), .B(n2322), .C(n2323), .Y(n540) );
NAND2X1TS U2912 ( .A(n1434), .B(n1303), .Y(n2327) );
NAND3X2TS U2913 ( .A(n2327), .B(n2326), .C(n2325), .Y(n538) );
NAND2X1TS U2914 ( .A(n1353), .B(intDY[13]), .Y(n2328) );
NAND3X2TS U2915 ( .A(n2330), .B(n2328), .C(n2329), .Y(n542) );
NAND2X2TS U2916 ( .A(n2334), .B(DmP[17]), .Y(n2336) );
NAND2X2TS U2917 ( .A(n2358), .B(DMP[14]), .Y(n2343) );
NAND2X2TS U2918 ( .A(n2358), .B(DMP[18]), .Y(n2346) );
NAND3X2TS U2919 ( .A(n2347), .B(n2346), .C(n2345), .Y(n579) );
NAND2X2TS U2920 ( .A(n2358), .B(DMP[10]), .Y(n2349) );
NAND2X1TS U2921 ( .A(n1356), .B(n1305), .Y(n2351) );
NAND2X2TS U2922 ( .A(n2358), .B(DMP[16]), .Y(n2354) );
NAND2X2TS U2923 ( .A(n2358), .B(DMP[17]), .Y(n2360) );
NAND3X2TS U2924 ( .A(n2361), .B(n2360), .C(n2359), .Y(n578) );
NAND3X2TS U2925 ( .A(n2365), .B(n2366), .C(n2367), .Y(n567) );
NAND3X2TS U2926 ( .A(n2368), .B(n2369), .C(n2370), .Y(n565) );
OAI21X4TS U2927 ( .A0(n2384), .A1(n2872), .B0(n2383), .Y(n2390) );
INVX2TS U2928 ( .A(n2672), .Y(n2386) );
AND4X1TS U2929 ( .A(n2387), .B(n1489), .C(n2408), .D(n2391), .Y(n2389) );
AOI21X2TS U2930 ( .A0(n2390), .A1(n2389), .B0(n2388), .Y(n762) );
BUFX3TS U2931 ( .A(n1438), .Y(n2865) );
BUFX3TS U2932 ( .A(n2865), .Y(n2868) );
BUFX3TS U2933 ( .A(n2857), .Y(n2864) );
BUFX3TS U2934 ( .A(n2864), .Y(n2867) );
BUFX3TS U2935 ( .A(n2867), .Y(n2866) );
BUFX3TS U2936 ( .A(n2866), .Y(n2855) );
BUFX3TS U2937 ( .A(n2868), .Y(n2850) );
BUFX3TS U2938 ( .A(n2856), .Y(n2862) );
BUFX3TS U2939 ( .A(n1432), .Y(n2861) );
BUFX3TS U2940 ( .A(n2868), .Y(n2851) );
BUFX3TS U2941 ( .A(n2851), .Y(n2860) );
BUFX3TS U2942 ( .A(n2867), .Y(n2853) );
BUFX3TS U2943 ( .A(n2866), .Y(n2870) );
BUFX3TS U2944 ( .A(n2867), .Y(n2852) );
INVX2TS U2945 ( .A(n2391), .Y(n2392) );
CLKMX2X3TS U2946 ( .A(Data_Y[5]), .B(intDY[5]), .S0(n1447), .Y(n597) );
CLKMX2X3TS U2947 ( .A(Data_Y[7]), .B(intDY[7]), .S0(n1513), .Y(n599) );
CLKMX2X3TS U2948 ( .A(Data_Y[15]), .B(intDY[15]), .S0(n1424), .Y(n607) );
CLKMX2X3TS U2949 ( .A(Data_Y[18]), .B(intDY[18]), .S0(n1447), .Y(n610) );
CLKMX2X3TS U2950 ( .A(Data_Y[22]), .B(intDY[22]), .S0(n1447), .Y(n614) );
CLKMX2X3TS U2951 ( .A(Data_Y[17]), .B(intDY[17]), .S0(n1424), .Y(n609) );
CLKMX2X3TS U2952 ( .A(Data_Y[14]), .B(intDY[14]), .S0(n1513), .Y(n606) );
CLKMX2X3TS U2953 ( .A(Data_X[26]), .B(n790), .S0(n1436), .Y(n651) );
CLKMX2X3TS U2954 ( .A(Data_X[18]), .B(intDX[18]), .S0(n1424), .Y(n643) );
CLKMX2X3TS U2955 ( .A(Data_X[24]), .B(intDX[24]), .S0(n1436), .Y(n649) );
CLKMX2X3TS U2956 ( .A(Data_X[8]), .B(intDX[8]), .S0(n1436), .Y(n633) );
CLKMX2X3TS U2957 ( .A(Data_X[10]), .B(intDX[10]), .S0(n1436), .Y(n635) );
AOI2BB2X1TS U2958 ( .B0(n2400), .B1(n1408), .A0N(n1371), .A1N(
final_result_ieee[28]), .Y(n684) );
AOI2BB2X1TS U2959 ( .B0(n2402), .B1(n1246), .A0N(n2398), .A1N(
final_result_ieee[27]), .Y(n685) );
AOI2BB2X1TS U2960 ( .B0(n1445), .B1(n2725), .A0N(n2398), .A1N(
final_result_ieee[23]), .Y(n689) );
AOI2BB2X1TS U2961 ( .B0(n2400), .B1(n2726), .A0N(n2398), .A1N(
final_result_ieee[25]), .Y(n687) );
AOI2BB2X1TS U2962 ( .B0(n2402), .B1(n2728), .A0N(n1371), .A1N(
final_result_ieee[26]), .Y(n686) );
AOI2BB2X1TS U2963 ( .B0(n2402), .B1(n2727), .A0N(n1371), .A1N(
final_result_ieee[24]), .Y(n688) );
NAND2X2TS U2964 ( .A(n1638), .B(n2405), .Y(n2406) );
XNOR2X4TS U2965 ( .A(n1369), .B(n1387), .Y(n2846) );
XOR2X1TS U2966 ( .A(n2846), .B(n624), .Y(n2833) );
NAND2X1TS U2967 ( .A(n2487), .B(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n2424) );
NAND3X1TS U2968 ( .A(n2432), .B(n1021), .C(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n2423) );
NAND2X1TS U2969 ( .A(n836), .B(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n2429) );
NAND2X1TS U2970 ( .A(n2510), .B(n1273), .Y(n2427) );
NAND2X1TS U2971 ( .A(n2475), .B(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n2438) );
NAND3X1TS U2972 ( .A(n2432), .B(n1021), .C(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n2433) );
NAND2X2TS U2973 ( .A(n2550), .B(n2528), .Y(n2437) );
NAND2X1TS U2974 ( .A(n2510), .B(n814), .Y(n2435) );
NAND2X2TS U2975 ( .A(n2573), .B(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n2440) );
AOI21X4TS U2976 ( .A0(n2458), .A1(n1637), .B0(n864), .Y(n2462) );
NAND2X2TS U2977 ( .A(n2524), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n2467) );
NAND2X1TS U2978 ( .A(n2510), .B(Sgf_normalized_result[14]), .Y(n2465) );
NAND2X2TS U2979 ( .A(n2469), .B(n2528), .Y(n2473) );
NAND2X1TS U2980 ( .A(n2554), .B(Sgf_normalized_result[13]), .Y(n2471) );
NAND2X1TS U2981 ( .A(n836), .B(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n2470) );
NAND2X1TS U2982 ( .A(n2510), .B(Sgf_normalized_result[15]), .Y(n2476) );
NAND2X1TS U2983 ( .A(n2510), .B(n1269), .Y(n2488) );
NAND4BX2TS U2984 ( .AN(n1495), .B(n2490), .C(n2489), .D(n2488), .Y(n706) );
NAND2X1TS U2985 ( .A(n2510), .B(Sgf_normalized_result[4]), .Y(n2491) );
NAND2X1TS U2986 ( .A(n2510), .B(n1318), .Y(n2493) );
NAND4BX2TS U2987 ( .AN(n1495), .B(n2495), .C(n2494), .D(n2493), .Y(n708) );
NAND2X1TS U2988 ( .A(n2510), .B(n1417), .Y(n2496) );
NAND2X1TS U2989 ( .A(n2510), .B(Sgf_normalized_result[7]), .Y(n2500) );
NAND4BX2TS U2990 ( .AN(n1495), .B(n2502), .C(n2501), .D(n2500), .Y(n710) );
NOR2X1TS U2991 ( .A(n2515), .B(n1983), .Y(n2506) );
NAND2X1TS U2992 ( .A(n2510), .B(n1314), .Y(n2511) );
NAND2X1TS U2993 ( .A(n1343), .B(n2580), .Y(n2514) );
NAND2X1TS U2994 ( .A(n2542), .B(Add_Subt_result[4]), .Y(n2536) );
NAND2X1TS U2995 ( .A(n2539), .B(n2584), .Y(n2547) );
NAND2X1TS U2996 ( .A(n2542), .B(Add_Subt_result[5]), .Y(n2543) );
NAND3X4TS U2997 ( .A(n2545), .B(n2544), .C(n2543), .Y(n2563) );
NAND2X2TS U2998 ( .A(n2563), .B(n2614), .Y(n2546) );
NAND2X1TS U2999 ( .A(n2550), .B(n1994), .Y(n2552) );
NAND2X1TS U3000 ( .A(n2571), .B(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .Y(n2551) );
NAND2X1TS U3001 ( .A(n2571), .B(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .Y(n2557) );
AOI22X1TS U3002 ( .A0(n2573), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n2572), .B1(
Sgf_normalized_result[22]), .Y(n2577) );
AND2X2TS U3003 ( .A(n2581), .B(n2580), .Y(n2582) );
AOI22X4TS U3004 ( .A0(n2591), .A1(n2586), .B0(n2585), .B1(n2584), .Y(n2587)
);
NAND2X2TS U3005 ( .A(n1433), .B(n885), .Y(n2609) );
NAND2X2TS U3006 ( .A(n2615), .B(n833), .Y(n2617) );
NAND2X1TS U3007 ( .A(n2642), .B(n2639), .Y(n2635) );
NAND2X2TS U3008 ( .A(n2631), .B(n834), .Y(n2634) );
NAND2X1TS U3009 ( .A(n2632), .B(n2641), .Y(n2633) );
OAI21X4TS U3010 ( .A0(n2644), .A1(n2643), .B0(n1955), .Y(n2646) );
XNOR2X4TS U3011 ( .A(n2646), .B(n2645), .Y(n2647) );
AOI21X4TS U3012 ( .A0(n1040), .A1(n1642), .B0(n2648), .Y(n2650) );
XNOR2X4TS U3013 ( .A(n1040), .B(n2657), .Y(n2658) );
OAI21X4TS U3014 ( .A0(n2651), .A1(n2660), .B0(n2653), .Y(n2661) );
BUFX3TS U3015 ( .A(n2869), .Y(n2849) );
OAI21X1TS U3016 ( .A0(underflow_flag), .A1(n816), .B0(n2669), .Y(n2671) );
INVX2TS U3017 ( .A(final_result_ieee[31]), .Y(n2670) );
MXI2X1TS U3018 ( .A(n2671), .B(n2670), .S0(n2674), .Y(n657) );
AO22X2TS U3019 ( .A0(n2673), .A1(n1314), .B0(final_result_ieee[0]), .B1(
n2674), .Y(n681) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk1.tcl_syn.sdf");
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/sensorfsm.v:3" *)
module \$paramod\SensorFSM\DataWidth=8 (Reset_n_i, Clk_i, Enable_i, CpuIntr_o, SensorValue_o, MeasureFSM_Start_o, MeasureFSM_Done_i, MeasureFSM_Error_i, MeasureFSM_Byte0_i, MeasureFSM_Byte1_i, ParamThreshold_i, ParamCounterPresetH_i, ParamCounterPresetL_i);
(* src = "../../verilog/sensorfsm.v:146" *)
wire [31:0] \$0\SensorFSM_Timer[31:0] ;
(* src = "../../verilog/sensorfsm.v:169" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$3\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:60" *)
wire \$5\SensorFSM_TimerPreset[0:0] ;
wire \$procmux$195_CMP ;
wire \$procmux$202_CMP ;
wire \$procmux$207_CMP ;
wire \$procmux$210_CMP ;
wire [31:0] \$procmux$62_Y ;
(* src = "../../verilog/sensorfsm.v:160" *)
wire [31:0] \$sub$../../verilog/sensorfsm.v:160$51_Y ;
(* src = "../../verilog/sensorfsm.v:42" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/sensorfsm.v:7" *)
input Clk_i;
(* src = "../../verilog/sensorfsm.v:10" *)
output CpuIntr_o;
(* src = "../../verilog/sensorfsm.v:184" *)
wire [16:0] DiffAB;
(* src = "../../verilog/sensorfsm.v:185" *)
wire [15:0] DiffBA;
(* src = "../../verilog/sensorfsm.v:9" *)
input Enable_i;
(* src = "../../verilog/sensorfsm.v:16" *)
input [7:0] MeasureFSM_Byte0_i;
(* src = "../../verilog/sensorfsm.v:17" *)
input [7:0] MeasureFSM_Byte1_i;
(* src = "../../verilog/sensorfsm.v:14" *)
input MeasureFSM_Done_i;
(* src = "../../verilog/sensorfsm.v:15" *)
input MeasureFSM_Error_i;
(* src = "../../verilog/sensorfsm.v:13" *)
output MeasureFSM_Start_o;
(* src = "../../verilog/sensorfsm.v:20" *)
input [15:0] ParamCounterPresetH_i;
(* src = "../../verilog/sensorfsm.v:21" *)
input [15:0] ParamCounterPresetL_i;
(* src = "../../verilog/sensorfsm.v:19" *)
input [15:0] ParamThreshold_i;
(* src = "../../verilog/sensorfsm.v:6" *)
input Reset_n_i;
(* src = "../../verilog/sensorfsm.v:35" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/sensorfsm.v:36" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/sensorfsm.v:144" *)
wire [31:0] SensorFSM_Timer;
(* src = "../../verilog/sensorfsm.v:34" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/sensorfsm.v:32" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/sensorfsm.v:33" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/sensorfsm.v:40" *)
wire [15:0] SensorValue;
(* src = "../../verilog/sensorfsm.v:11" *)
output [15:0] SensorValue_o;
(* src = "../../verilog/sensorfsm.v:41" *)
wire [15:0] Word0;
(* src = "../../verilog/sensorfsm.v:165" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/sensorfsm.v:165$52 (
.A(SensorFSM_Timer),
.B(0),
.Y(SensorFSM_TimerOvfl)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/sensorfsm.v:30" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000101),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000100),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000011),
.STATE_NUM(32'b00000000000000000000000000000101),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(15'b011001010100000),
.TRANS_NUM(32'b00000000000000000000000000001100),
.TRANS_TABLE(180'b100zzzzz01100010110zzz101101000111zzz10100100011zzzz00000100010z101z1000010010z001z0110010010zz00z0100010010zz1zz0010010001zzzz10010000001zzzz00000000000zzzz10111000000zzzz00001000)
) \$fsm$\SensorFSM_State$2836 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SensorFSM_TimerOvfl, SensorFSM_DiffTooLarge, MeasureFSM_Error_i, MeasureFSM_Done_i, Enable_i }),
.CTRL_OUT({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP , \$procmux$195_CMP })
);
(* src = "../../verilog/sensorfsm.v:190" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/sensorfsm.v:190$59 (
.A(AbsDiffResult),
.B(ParamThreshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/sensorfsm.v:146" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$2816 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[31:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/sensorfsm.v:169" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2817 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$194 (
.A(1'b0),
.B({ MeasureFSM_Error_i, 1'b1 }),
.S({ \$procmux$202_CMP , \$procmux$195_CMP }),
.Y(CpuIntr_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$227 (
.A(\$procmux$207_CMP ),
.B(\$2\MeasureFSM_Start_o[0:0] ),
.Y(MeasureFSM_Start_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$243 (
.A(\$procmux$202_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$285 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$306 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$210_CMP , \$procmux$207_CMP , \$procmux$202_CMP }),
.Y(SensorFSM_TimerPreset)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$356 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$397 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\MeasureFSM_Start_o[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$482 (
.A(\$3\SensorFSM_StoreNewValue[0:0] ),
.B(1'b0),
.S(MeasureFSM_Error_i),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$526 (
.A(\$4\SensorFSM_TimerPreset[0:0] ),
.B(MeasureFSM_Error_i),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$613 (
.A(MeasureFSM_Done_i),
.B(SensorFSM_DiffTooLarge),
.Y(\$3\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$62 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/sensorfsm.v:160$51_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$62_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$65 (
.A(\$procmux$62_Y ),
.B({ ParamCounterPresetH_i, ParamCounterPresetL_i }),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[31:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$659 (
.A(1'b1),
.B(\$5\SensorFSM_TimerPreset[0:0] ),
.S(MeasureFSM_Done_i),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$68 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$705 (
.A(SensorFSM_DiffTooLarge),
.Y(\$5\SensorFSM_TimerPreset[0:0] )
);
(* src = "../../verilog/sensorfsm.v:160" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/sensorfsm.v:160$51 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/sensorfsm.v:160$51_Y )
);
(* src = "../../verilog/sensorfsm.v:186" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/sensorfsm.v:186$56 (
.A({ 1'b0, MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/sensorfsm.v:187" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:187$57 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.Y(DiffBA)
);
(* src = "../../verilog/sensorfsm.v:188" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/sensorfsm.v:188$58 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SensorValue = { MeasureFSM_Byte1_i, MeasureFSM_Byte0_i };
assign SensorValue_o = Word0;
endmodule
(* src = "../../verilog/i2cfsm.v:3" *)
module I2CFSM(Reset_n_i, Clk_i, Start_i, Done_o, Error_o, Byte0_o, Byte1_o, I2C_ReceiveSend_n_o, I2C_ReadCount_o, I2C_StartProcess_o, I2C_Busy_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_Data_o, I2C_Data_i, I2C_Error_i, ParamCounterPresetH_i, ParamCounterPresetL_i);
(* src = "../../verilog/i2cfsm.v:241" *)
wire [7:0] \$0\Byte0_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:241" *)
wire [7:0] \$0\Byte1_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:271" *)
wire [31:0] \$0\I2C_FSM_Timer[31:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$2\I2C_FIFOReadNext_o[0:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$2\I2C_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$2\I2C_FSM_TimerPreset[0:0] ;
(* src = "../../verilog/i2cfsm.v:98" *)
wire \$4\I2C_FSM_TimerEnable[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2832 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2834 ;
wire \$procmux$1152_CMP ;
wire \$procmux$1153_CMP ;
wire \$procmux$1156_CMP ;
wire \$procmux$1157_CMP ;
wire \$procmux$1158_CMP ;
wire \$procmux$1161_CMP ;
wire \$procmux$1166_CMP ;
wire \$procmux$1167_CMP ;
wire \$procmux$1168_CMP ;
wire \$procmux$1169_CMP ;
wire \$procmux$1172_CMP ;
wire [31:0] \$procmux$803_Y ;
(* src = "../../verilog/i2cfsm.v:285" *)
wire [31:0] \$sub$../../verilog/i2cfsm.v:285$14_Y ;
(* src = "../../verilog/i2cfsm.v:10" *)
output [7:0] Byte0_o;
(* src = "../../verilog/i2cfsm.v:11" *)
output [7:0] Byte1_o;
(* src = "../../verilog/i2cfsm.v:5" *)
input Clk_i;
(* src = "../../verilog/i2cfsm.v:8" *)
output Done_o;
(* src = "../../verilog/i2cfsm.v:9" *)
output Error_o;
(* src = "../../verilog/i2cfsm.v:17" *)
input I2C_Busy_i;
(* src = "../../verilog/i2cfsm.v:22" *)
input [7:0] I2C_Data_i;
(* src = "../../verilog/i2cfsm.v:21" *)
output [7:0] I2C_Data_o;
(* src = "../../verilog/i2cfsm.v:24" *)
input I2C_Error_i;
(* src = "../../verilog/i2cfsm.v:19" *)
output I2C_FIFOReadNext_o;
(* src = "../../verilog/i2cfsm.v:20" *)
output I2C_FIFOWrite_o;
(* src = "../../verilog/i2cfsm.v:269" *)
wire [31:0] I2C_FSM_Timer;
(* src = "../../verilog/i2cfsm.v:78" *)
wire I2C_FSM_TimerEnable;
(* src = "../../verilog/i2cfsm.v:76" *)
wire I2C_FSM_TimerOvfl;
(* src = "../../verilog/i2cfsm.v:77" *)
wire I2C_FSM_TimerPreset;
(* src = "../../verilog/i2cfsm.v:80" *)
wire I2C_FSM_Wr0;
(* src = "../../verilog/i2cfsm.v:79" *)
wire I2C_FSM_Wr1;
(* src = "../../verilog/i2cfsm.v:15" *)
output [7:0] I2C_ReadCount_o;
(* src = "../../verilog/i2cfsm.v:14" *)
output I2C_ReceiveSend_n_o;
(* src = "../../verilog/i2cfsm.v:16" *)
output I2C_StartProcess_o;
(* src = "../../verilog/i2cfsm.v:26" *)
input [15:0] ParamCounterPresetH_i;
(* src = "../../verilog/i2cfsm.v:27" *)
input [15:0] ParamCounterPresetL_i;
(* src = "../../verilog/i2cfsm.v:4" *)
input Reset_n_i;
(* src = "../../verilog/i2cfsm.v:7" *)
input Start_i;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2827 (
.A({ \$procmux$1153_CMP , \$procmux$1152_CMP }),
.Y(I2C_ReceiveSend_n_o)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2831 (
.A({ \$procmux$1167_CMP , \$procmux$1157_CMP , \$procmux$1153_CMP }),
.Y(I2C_StartProcess_o)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2833 (
.A({ \$procmux$1172_CMP , \$procmux$1161_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2832 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2835 (
.A({ \$procmux$1169_CMP , \$procmux$1168_CMP , \$procmux$1158_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2834 )
);
(* src = "../../verilog/i2cfsm.v:290" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/i2cfsm.v:290$15 (
.A(I2C_FSM_Timer),
.B(0),
.Y(I2C_FSM_TimerOvfl)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/i2cfsm.v:74" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000100),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000001101),
.NAME("\\I2C_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000100),
.STATE_NUM(32'b00000000000000000000000000001101),
.STATE_NUM_LOG2(32'b00000000000000000000000000000100),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(52'b0111101100110101100100010110101000101100010010000000),
.TRANS_NUM(32'b00000000000000000000000000010011),
.TRANS_TABLE(475'b1100zzzz000100000000010001011zzzz001110000000000001010zzzz001000000100000001001z0zz100100000001000001001z1zz011000000001000001000zzzz010100000000000100111zzzz010000010000000000110zzzz110000000000100000101zzz0101100000000000010101zzz1010100000000000010100zzzz101000001000000000011zzzz000001000000000000010zz00100100000010000000010zz01001000000010000000010zz1z000000000010000000001zzz0100000000000001000001zzz10001000000000010000001zzz0111001000000000000000zzz00000010000000000)
) \$fsm$\I2C_FSM_State$2843 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ Start_i, I2C_FSM_TimerOvfl, I2C_Error_i, I2C_Busy_i }),
.CTRL_OUT({ I2C_FSM_Wr0, Done_o, \$procmux$1172_CMP , \$procmux$1169_CMP , \$procmux$1168_CMP , \$procmux$1167_CMP , \$procmux$1166_CMP , \$procmux$1161_CMP , \$procmux$1158_CMP , \$procmux$1157_CMP , \$procmux$1156_CMP , \$procmux$1153_CMP , \$procmux$1152_CMP })
);
(* src = "../../verilog/i2cfsm.v:241" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2819 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0_o[7:0] ),
.Q(Byte0_o)
);
(* src = "../../verilog/i2cfsm.v:241" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2820 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1_o[7:0] ),
.Q(Byte1_o)
);
(* src = "../../verilog/i2cfsm.v:271" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$2821 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\I2C_FSM_Timer[31:0] ),
.Q(I2C_FSM_Timer)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1192 (
.A(\$procmux$1166_CMP ),
.B(I2C_Error_i),
.Y(Error_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1202 (
.A(1'b0),
.B({ \$2\I2C_FIFOReadNext_o[0:0] , 1'b1 }),
.S({ \$procmux$1152_CMP , I2C_FSM_Wr0 }),
.Y(I2C_FIFOReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1241 (
.A(1'b0),
.B({ \$2\I2C_FSM_TimerEnable[0:0] , \$4\I2C_FSM_TimerEnable[0:0] }),
.S({ \$procmux$1166_CMP , \$procmux$1161_CMP }),
.Y(I2C_FSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1268 (
.A(1'b1),
.B({ \$2\I2C_FSM_TimerPreset[0:0] , I2C_FSM_TimerOvfl }),
.S({ \$procmux$1166_CMP , \$procmux$1161_CMP }),
.Y(I2C_FSM_TimerPreset)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1313 (
.A(\$procmux$1152_CMP ),
.B(\$2\I2C_FIFOReadNext_o[0:0] ),
.Y(I2C_FSM_Wr1)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1340 (
.A(8'b00000000),
.B(8'b00000010),
.S(I2C_ReceiveSend_n_o),
.Y(I2C_ReadCount_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000100),
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$1425 (
.A(8'b00000000),
.B(52465809),
.S({ \$procmux$1169_CMP , \$procmux$1168_CMP , \$auto$opt_reduce.cc:126:opt_mux$2832 , \$procmux$1156_CMP }),
.Y(I2C_Data_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000100),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1452 (
.A(1'b0),
.B({ Start_i, I2C_FSM_TimerOvfl, 1'b1, \$2\I2C_FIFOReadNext_o[0:0] }),
.S({ \$procmux$1172_CMP , \$procmux$1161_CMP , \$auto$opt_reduce.cc:126:opt_mux$2834 , \$procmux$1156_CMP }),
.Y(I2C_FIFOWrite_o)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1598 (
.A(\$2\I2C_FIFOReadNext_o[0:0] ),
.B(1'b0),
.S(I2C_Error_i),
.Y(\$2\I2C_FSM_TimerEnable[0:0] )
);
\$or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1626 (
.A(I2C_Busy_i),
.B(I2C_Error_i),
.Y(\$2\I2C_FSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1766 (
.A(I2C_Busy_i),
.Y(\$2\I2C_FIFOReadNext_o[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1876 (
.A(I2C_FSM_TimerOvfl),
.Y(\$4\I2C_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$793 (
.A(Byte0_o),
.B(I2C_Data_i),
.S(I2C_FSM_Wr0),
.Y(\$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$800 (
.A(Byte1_o),
.B(I2C_Data_i),
.S(I2C_FSM_Wr1),
.Y(\$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$803 (
.A(I2C_FSM_Timer),
.B(\$sub$../../verilog/i2cfsm.v:285$14_Y ),
.S(I2C_FSM_TimerEnable),
.Y(\$procmux$803_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$806 (
.A(\$procmux$803_Y ),
.B({ ParamCounterPresetH_i, ParamCounterPresetL_i }),
.S(I2C_FSM_TimerPreset),
.Y(\$0\I2C_FSM_Timer[31:0] )
);
(* src = "../../verilog/i2cfsm.v:285" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/i2cfsm.v:285$14 (
.A(I2C_FSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/i2cfsm.v:285$14_Y )
);
endmodule
(* src = "../../verilog/slowadt7410.v:1" *)
module SlowADT7410(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, I2C_ReceiveSend_n_o, I2C_ReadCount_o, I2C_StartProcess_o, I2C_Busy_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_Data_o, I2C_Data_i, I2C_Error_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, WaitCounterPresetH_i, WaitCounterPresetL_i);
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/slowadt7410.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/slowadt7410.v:9" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/slowadt7410.v:7" *)
input Enable_i;
(* src = "../../verilog/slowadt7410.v:45" *)
wire [7:0] I2CFSM_Byte0_s;
(* src = "../../verilog/slowadt7410.v:46" *)
wire [7:0] I2CFSM_Byte1_s;
(* src = "../../verilog/slowadt7410.v:43" *)
wire I2CFSM_Done_s;
(* src = "../../verilog/slowadt7410.v:44" *)
wire I2CFSM_Error_s;
(* src = "../../verilog/slowadt7410.v:42" *)
wire I2CFSM_Start_s;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Busy" *)
(* src = "../../verilog/slowadt7410.v:17" *)
input I2C_Busy_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataOut" *)
(* src = "../../verilog/slowadt7410.v:25" *)
input [7:0] I2C_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataIn" *)
(* src = "../../verilog/slowadt7410.v:23" *)
output [7:0] I2C_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Error" *)
(* src = "../../verilog/slowadt7410.v:27" *)
input I2C_Error_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOReadNext" *)
(* src = "../../verilog/slowadt7410.v:19" *)
output I2C_FIFOReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOWrite" *)
(* src = "../../verilog/slowadt7410.v:21" *)
output I2C_FIFOWrite_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_ReadCount" *)
(* src = "../../verilog/slowadt7410.v:13" *)
output [7:0] I2C_ReadCount_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_ReceiveSend_n" *)
(* src = "../../verilog/slowadt7410.v:11" *)
output I2C_ReceiveSend_n_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_StartProcess" *)
(* src = "../../verilog/slowadt7410.v:15" *)
output I2C_StartProcess_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/slowadt7410.v:29" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/slowadt7410.v:31" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/slowadt7410.v:3" *)
input Reset_n_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/slowadt7410.v:33" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/slowadt7410.v:35" *)
input [15:0] Threshold_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "WaitCounterPresetH_i" *)
(* src = "../../verilog/slowadt7410.v:37" *)
input [15:0] WaitCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "WaitCounterPresetL_i" *)
(* src = "../../verilog/slowadt7410.v:39" *)
input [15:0] WaitCounterPresetL_i;
(* src = "../../verilog/slowadt7410.v:48" *)
I2CFSM I2CFSM_1 (
.Byte0_o(I2CFSM_Byte0_s),
.Byte1_o(I2CFSM_Byte1_s),
.Clk_i(Clk_i),
.Done_o(I2CFSM_Done_s),
.Error_o(I2CFSM_Error_s),
.I2C_Busy_i(I2C_Busy_i),
.I2C_Data_i(I2C_Data_i),
.I2C_Data_o(I2C_Data_o),
.I2C_Error_i(I2C_Error_i),
.I2C_FIFOReadNext_o(I2C_FIFOReadNext_o),
.I2C_FIFOWrite_o(I2C_FIFOWrite_o),
.I2C_ReadCount_o(I2C_ReadCount_o),
.I2C_ReceiveSend_n_o(I2C_ReceiveSend_n_o),
.I2C_StartProcess_o(I2C_StartProcess_o),
.ParamCounterPresetH_i(WaitCounterPresetH_i),
.ParamCounterPresetL_i(WaitCounterPresetL_i),
.Reset_n_i(Reset_n_i),
.Start_i(I2CFSM_Start_s)
);
(* src = "../../verilog/slowadt7410.v:75" *)
\$paramod\SensorFSM\DataWidth=8 SensorFSM_1 (
.Clk_i(Clk_i),
.CpuIntr_o(CpuIntr_o),
.Enable_i(Enable_i),
.MeasureFSM_Byte0_i(I2CFSM_Byte0_s),
.MeasureFSM_Byte1_i(I2CFSM_Byte1_s),
.MeasureFSM_Done_i(I2CFSM_Done_s),
.MeasureFSM_Error_i(I2CFSM_Error_s),
.MeasureFSM_Start_o(I2CFSM_Start_s),
.ParamCounterPresetH_i(PeriodCounterPresetH_i),
.ParamCounterPresetL_i(PeriodCounterPresetL_i),
.ParamThreshold_i(Threshold_i),
.Reset_n_i(Reset_n_i),
.SensorValue_o(SensorValue_o)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_LP_V
`define SKY130_FD_SC_LP__DLRTP_LP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_lp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_lp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_LP_V
|
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// By modifying the value of SW we change the incrementing speed
// of a counter that is used to drive the on-board LEDs. The two switches
// and the value of each bit of the counter are fed by way of DATA_IN to the logic analyzer.
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module demo(input CLK, input [1:0] SW, input serial_in, output serial_out, output reg [5:0] LED=0);
wire [15:0] DATA_IN;
wire [15:0] TXD;
wire [7:0] RXD;
wire TXD_DONE_2;
reg FF;
reg [31:0] divcount=0;
reg led_increment_enable;
assign DATA_IN[1:0]=SW;
assign DATA_IN[7:2]=LED;
assign DATA_IN[15:8]=0;
always@(posedge CLK)
if(led_increment_enable)
divcount <= 0;
else
divcount <= divcount+1;
always @*
case(SW)
0: led_increment_enable=(divcount == 2**0);
1: led_increment_enable=(divcount == 2**22);
2: led_increment_enable=(divcount == 2**25);
3: led_increment_enable=(divcount == 2**28);
endcase
always@(posedge CLK) if(led_increment_enable) LED<=LED+1;
AssembledLogicAnalyzer LA(
.CLK(CLK),
.RXD_START(RXD_START),
.RXD(RXD),
.TXD_DONE(TXD_DONE),
.DATA_IN(DATA_IN),
.TXD_ENABLE(TXD_ENABLE),
.TXD(TXD)
);
always@(posedge CLK) FF<=TXD_DONE_2;
assign TXD_DONE=(~FF)&TXD_DONE_2; //whether this is needed or not depends on your chosen communication module
uart SERIAL(
.clk(CLK),
.rx(serial_in),
.tx(serial_out),
.par_en(1'b0),
.tx_req(TXD_ENABLE),
.tx_end(TXD_DONE_2),
.tx_data(TXD[7:0]),
.rx_ready(RXD_START),
.rx_data(RXD)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:17:32 09/04/2013
// Design Name:
// Module Name: FSM_semaforo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Semaforo(clk, reset, Sensor_Sync, WR, Prog_Sync, expire, WR_Reset, interval, start_timer, Rm, Ym, Gm, Rs, Ys, Gs, Walk);
//Definicion de las variables
input clk, Prog_Sync, WR, expire, Sensor_Sync, reset;
output WR_Reset, Rm, Ym, Gm, Rs, Ys, Gs, Walk, start_timer;
output reg [1:0] interval;
reg [3:0] state;
//Definimos todos los estados de la FSM
parameter STATE_0 = 0;
parameter STATE_1 = 1;
parameter STATE_2 = 2;
parameter STATE_3 = 3;
parameter STATE_4 = 4;
parameter STATE_5 = 5;
parameter STATE_6 = 6;
parameter STATE_7 = 7;
parameter STATE_8 = 8;
parameter STATE_9 = 9;
parameter STATE_10 = 10;
parameter STATE_11 = 11;
parameter STATE_12 = 12;
parameter STATE_13 = 13;
parameter STATE_14 = 14;
parameter STATE_15 = 15;
always@(posedge clk or posedge reset)
begin
if (reset) //Si se presiona el reset, se reinicia al estado 0
begin
state <= STATE_0;
end
else if (Prog_Sync) //Si se presona Prog_Sync se reinicia al estado 0
begin
state <= STATE_0;
end
else
begin
case(state)//Se va recorriendo estado por estado
STATE_0:
begin
interval <= 2'b00;
state <= STATE_1;
end
STATE_1:
begin
interval <= 2'b00;
if (expire & !Sensor_Sync)
state <= STATE_2;
else if (expire & Sensor_Sync)
state <= STATE_10;
else
state <= STATE_1;
end
STATE_2:
begin
interval <= 2'b00;
state <= STATE_3;
end
STATE_3:
begin
interval <= 2'b00;
if (expire)
state <= STATE_4;
else
state <= STATE_3;
end
STATE_4:
begin
interval <= 2'b10;
state <= STATE_5;
end
STATE_5:
begin
interval <= 2'b10;
if (expire & WR)
state <= STATE_12;
else if (expire & !WR)
state <= STATE_6;
else
state <= STATE_5;
end
STATE_6:
begin
interval <= 2'b01;
state <= STATE_7;
end
STATE_7:
begin
interval <= 2'b01;
if (expire & Sensor_Sync)
state <= STATE_14;
else if (expire & !Sensor_Sync)
state <= STATE_8;
else
state <= STATE_7;
end
STATE_8:
begin
interval <= 2'b10;
state <= STATE_9;
end
STATE_9:
begin
interval <= 2'b10;
if (expire)
state <= STATE_0;
else
state <= STATE_9;
end
STATE_10:
begin
interval <= 2'b01;
state <= STATE_11;
end
STATE_11:
begin
interval <= 2'b01;
if (expire)
state <= STATE_4;
else
state <= STATE_11;
end
STATE_12:
begin
interval <= 2'b01;
state <= STATE_13;
end
STATE_13:
begin
interval <= 2'b01;
if (expire)
state <= STATE_6;
else
state <= STATE_13;
end
STATE_14:
begin
interval <= 2'b01;
state <= STATE_15;
end
STATE_15:
begin
interval <= 2'b01;
if(expire)
state <= STATE_8;
else
state <= STATE_15;
end
default:
begin
state <= STATE_0;
interval <= 2'b00;
end
endcase
end
end
//Se define el valor de la salida para casa ciclo de reloj
assign start_timer = (state == STATE_1 || state == STATE_3 || state == STATE_5 || state == STATE_7 || state == STATE_9 || state == STATE_11 || state == STATE_13 || state == STATE_15);
assign Rm = (state == STATE_7 || state == STATE_9 || state == STATE_13 || state == STATE_15);
assign Ym = (state == STATE_5);
assign Gm = (state == STATE_1 || state == STATE_3 || state == STATE_11);
assign Rs = (state == STATE_1 || state == STATE_3 || state == STATE_5 || state == STATE_11 || state == STATE_13);
assign Ys = (state == STATE_9);
assign Gs = (state == STATE_7 || state == STATE_15);
assign Walk = (state == STATE_13);
assign WR_Reset = (state == STATE_12);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_SYMBOL_V
`define SKY130_FD_SC_LS__DLYGATE4SD1_SYMBOL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD1_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CONB_BLACKBOX_V
`define SKY130_FD_SC_LS__CONB_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__conb (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CONB_BLACKBOX_V
|
// **********************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/fifo/infer_blkram.v,v 1.14 2014/09/06 02:19:55 bpoladian Exp $
// **********************
// Description:
//
// This module infers Dual ported Xilinx Block RAM.
// **********************
// $Log: infer_blkram.v,v $
// Revision 1.14 2014/09/06 02:19:55 bpoladian
// Add define to prevent using read enable for better timing.
//
// Revision 1.13 2014/08/24 00:40:37 neal
// Made infer_blkram instances do an extra write and read before the first valid one.
//
// Revision 1.12 2014/07/24 17:54:53 neal
// Added simulation notes about un-registered RAMs.
//
// Revision 1.11 2014/07/08 15:20:02 neal
// Added optional output register with REGCE to rams.
// Added option to use RAM's output register.
// Added checksums to all async fifos (enabled by define).
//
// Revision 1.10 2013/09/25 00:20:06 claudiug
// fixed inference synthesis attributes for altera (assume stratix V)
//
// Revision 1.9 2013/06/29 01:31:58 claudiug
// added registered RAM behavior (disabled by default)
//
// Revision 1.8 2013/02/22 19:55:59 claudiug
// blockrams are not instantiated as fifos if no FIFO parameter is specified
//
// Revision 1.7 2012/05/11 02:34:07 bpoladian
// Force synchronous operation when ONELOCK is active.
//
// Revision 1.6 2011/10/06 17:51:58 bpoladian
// Prevent verilator tracing.
//
// Revision 1.5 2011/09/29 19:53:43 neal
// Fixed XST warnings.
//
// Revision 1.4 2010/11/16 03:12:16 bpoladian
// Added read enable port for blockram.
//
// Revision 1.3 2010/01/07 19:49:10 bpoladian
// Added new XST-style synthesis constraint.
//
// Revision 1.2 2008/04/11 01:38:02 bpoladian
// Ran dos2unix. Removed comments on `else and `endif lines.
//
// Revision 1.1 2007/06/13 17:54:39 jperry
// copied from timelogic area. Not sure where this stuff will go in the end.
//
// Revision 1.3 2007/04/24 18:14:55 neal
// Removed the reset from the BlockRAM output of the FIFO. The data output from the FIFO will now be unknown at the beginning of time, until it has been written to completely.
//
// Revision 1.2 2007/02/15 18:28:08 neal
// Made the parameters UPPER CASE.
//
// Revision 1.1 2007/02/05 17:11:30 jperry
// initial async FIFO files. Copied, modified from dn_fpgacode/FIFO. This may be cleaned up later.
//
// Revision 1.3 2006/07/17 20:56:56Z jthurkettle
// test
// **********************
/*verilator tracing_off*/
`ifdef INCL_INFER_BLKRAM_V
`else
`define INCL_INFER_BLKRAM_V
//This was broken out from fifo_unidir_block.v
// infer a RAM, registered reads.
module infer_blkram #(
parameter D_WIDTH = 32,
parameter ADDR_WIDTH = 5,
parameter FIFO = 1'bx, //not in use in this module but used in infer_blkram_7series instantiation
parameter ONECLOCK = 0,
parameter REGRAM = 0, // mimic registered RAM behavior
parameter MODE = "READ_FIRST",// only applicable if ONECLOCK==1
`ifdef NO_BRAM_READ_ENABLE
parameter USE_READ_ENABLE = 0
`else
parameter USE_READ_ENABLE = 1
`endif
) (
`ifdef ENABLE_ECC_DEBUG
input ecc_rst, // only used for resetting ecc_error (7series).
`endif // ENABLE_ECC_DEBUG
output reg [D_WIDTH - 1:0] o,
input we,
input wclk,
input re,
input reg_ce, // register enable when REGRAM==1
input rclk,
input [D_WIDTH - 1:0] d,
input [ADDR_WIDTH - 1:0] raddr,
input [ADDR_WIDTH - 1:0] waddr
);
`ifdef ALTERA
(* ramstyle = "M20K" *) reg [D_WIDTH - 1:0] mem [(1 << ADDR_WIDTH) - 1:0];
`else
(* ram_style = "block" *) reg [D_WIDTH - 1:0] mem [(1 << ADDR_WIDTH) - 1:0] /* synthesis syn_ramstyle = block_ram */;
`endif
initial begin
if (REGRAM==0) begin
$display("NOTE: %m using REGRAM=%d",REGRAM);
end
end
reg [D_WIDTH-1:0] o_nonreg;
reg re_d;
always @(posedge rclk) begin
re_d <= re;
end
generate
if(ONECLOCK==1) begin : gen_synchronous
always @(posedge wclk) begin
if (we)
mem[waddr] <= d;
if (REGRAM) begin
if (re)
o_nonreg <= mem[raddr];
if (reg_ce)
o <= o_nonreg;
end else if (USE_READ_ENABLE) begin
if (re) begin
o <= mem[raddr];
end
end else begin
o <= mem[raddr];
end
end
end else begin : gen_asynchronous
always @(posedge wclk) begin
if (we)
mem[waddr] <= d;
end
always @(posedge rclk) begin
if (REGRAM) begin
if (re)
o_nonreg <= mem[raddr];
if (reg_ce)
o <= o_nonreg;
end else if (USE_READ_ENABLE) begin
if (re) begin
o <= mem[raddr];
end
end else begin
o <= mem[raddr];
end
end
end
endgenerate
endmodule
`endif
/*verilator tracing_on*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFBBN_FUNCTIONAL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr/sky130_fd_sc_ms__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ms__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O41A_BEHAVIORAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_BEHAVIORAL_PP_V |
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
integer cnt;
`ifdef OVL_SYNTHESIS
`else
initial begin
cnt=0;
end
`endif
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_push;
wire valid_pop;
assign valid_push = ~((^push) ^ (^push));
assign valid_pop = ~((^pop) ^ (^pop));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
if ({push!=0,pop!=0} == 2'b10) begin // push
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("fifo_push covered");
end
end
`endif // OVL_COVER_ON
if ((cnt + push) > depth) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo overflow detected");
`endif // OVL_ASSERT_ON
end
else begin
cnt <= cnt + push;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if ((cnt + push) == depth) begin
ovl_cover_t("fifo_full covered");
end
end //corner coverage
end
`endif // OVL_COVER_ON
end
end
else if ({push!=0,pop!=0} == 2'b01) begin // pop
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("fifo_pop covered");
end
end
`endif // OVL_COVER_ON
if (cnt < pop) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo underflow detected");
`endif // OVL_ASSERT_ON
end
else begin
cnt <= cnt - pop;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if ((cnt - pop) == 0) begin
ovl_cover_t("fifo_empty covered");
end
end //corner coverage
end
`endif // OVL_COVER_ON
end
end
else if ({push!=0,pop!=0} == 2'b11) begin // push & pop
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
ovl_cover_t("fifo_simultaneous_push_pop covered");
end
end
`endif// OVL_COVER_ON
if (!simultaneous_push_pop) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Illegal simultaneous push pop detected");
`endif
end
else begin
if ((cnt + push - pop) > depth) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo overflow detected due to simultaneous push pop operations");
`endif
end
else if ((cnt + push) < pop) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo underflow detected due to simultaneous push pop operations");
`endif
end
else begin
cnt <= cnt + push - pop;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if ((cnt + push - pop) == depth) begin
ovl_cover_t("fifo_full covered");
end
else if ((cnt + push - pop) == 0) begin
ovl_cover_t("fifo_empty covered");
end
end //corner coverage
end
`endif // OVL_COVER_ON
end
end
end
end
else begin
cnt <= 0;
end
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @ (posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_push == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"push contains X or Z");
end
end
always @ (posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_pop == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"pop contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_SHARED_CODE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_PP_V
/**
* srdlstp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_psa_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, SET_B, SLEEP_B, KAPWR, VGND, VPWR);
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_SYMBOL_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_tx.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2006/01/19 14:07:53 maverickist
// verification is complete.
//
// Revision 1.2 2005/12/16 06:44:14 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module MAC_tx(
input Reset ,
input Clk ,
input Clk_user ,
//PHY interface
output [7:0] TxD ,
output TxEn ,
input CRS ,
//RMON
output [2:0] Tx_pkt_type_rmon ,
output [15:0] Tx_pkt_length_rmon ,
output Tx_apply_rmon ,
output [2:0] Tx_pkt_err_type_rmon,
//user interface
output Tx_mac_wa ,
input Tx_mac_wr ,
input [31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
input Tx_mac_sop ,
input Tx_mac_eop ,
//host interface
input [4:0] Tx_Hwmark ,
input [4:0] Tx_Lwmark ,
input pause_frame_send_en ,
input [15:0] pause_quanta_set ,
input MAC_tx_add_en ,
input FullDuplex ,
input [3:0] MaxRetry ,
input [5:0] IFGset ,
input [7:0] MAC_add_prom_data ,
input [2:0] MAC_add_prom_add ,
input MAC_add_prom_wr ,
input tx_pause_en ,
input xoff_cpu ,
input xon_cpu ,
//MAC_rx_flow ,
input [15:0] pause_quanta ,
input pause_quanta_val
);
//******************************************************************************
//internal signals
//******************************************************************************
//CRC_gen Interface
wire CRC_init ;
wire[7:0] Frame_data ;
wire Data_en ;
wire CRC_rd ;
wire CRC_end ;
wire[7:0] CRC_out ;
//Ramdon_gen interface
wire Random_init ;
wire[3:0] RetryCnt ;
wire Random_time_meet ;//levle hight indicate random time passed away
//flow control
wire pause_apply ;
wire pause_quanta_sub ;
wire xoff_gen ;
wire xoff_gen_complete ;
wire xon_gen ;
wire xon_gen_complete ;
//MAC_rx_FF
wire[7:0] Fifo_data ;
wire Fifo_rd ;
wire Fifo_eop ;
wire Fifo_da ;
wire Fifo_rd_finish ;
wire Fifo_rd_retry ;
wire Fifo_ra ;
wire Fifo_data_err_empty ;
wire Fifo_data_err_full ;
//MAC_tx_addr_add
wire MAC_tx_addr_init ;
wire MAC_tx_addr_rd ;
wire[7:0] MAC_tx_addr_data ;
//******************************************************************************
//instantiation
//******************************************************************************
MAC_tx_ctrl U_MAC_tx_ctrl(
.Reset (Reset ),
.Clk (Clk ),
//CRC_gen Interface (//CRC_gen Interface ),
.CRC_init (CRC_init ),
.Frame_data (Frame_data ),
.Data_en (Data_en ),
.CRC_rd (CRC_rd ),
.CRC_end (CRC_end ),
.CRC_out (CRC_out ),
//Ramdon_gen interfac (//Ramdon_gen interfac ),
.Random_init (Random_init ),
.RetryCnt (RetryCnt ),
.Random_time_meet (Random_time_meet ),
//flow control (//flow control ),
.pause_apply (pause_apply ),
.pause_quanta_sub (pause_quanta_sub ),
.xoff_gen (xoff_gen ),
.xoff_gen_complete (xoff_gen_complete ),
.xon_gen (xon_gen ),
.xon_gen_complete (xon_gen_complete ),
//MAC_tx_FF (//MAC_tx_FF ),
.Fifo_data (Fifo_data ),
.Fifo_rd (Fifo_rd ),
.Fifo_eop (Fifo_eop ),
.Fifo_da (Fifo_da ),
.Fifo_rd_finish (Fifo_rd_finish ),
.Fifo_rd_retry (Fifo_rd_retry ),
.Fifo_ra (Fifo_ra ),
.Fifo_data_err_empty (Fifo_data_err_empty ),
.Fifo_data_err_full (Fifo_data_err_full ),
//RMII (//RMII ),
.TxD (TxD ),
.TxEn (TxEn ),
.CRS (CRS ),
//MAC_tx_addr_add (//MAC_tx_addr_add ),
.MAC_tx_addr_rd (MAC_tx_addr_rd ),
.MAC_tx_addr_data (MAC_tx_addr_data ),
.MAC_tx_addr_init (MAC_tx_addr_init ),
//RMON (//RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//CPU (//CPU ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset )
);
CRC_gen U_CRC_gen(
.Reset (Reset ),
.Clk (Clk ),
.Init (CRC_init ),
.Frame_data (Frame_data ),
.Data_en (Data_en ),
.CRC_rd (CRC_rd ),
.CRC_out (CRC_out ),
.CRC_end (CRC_end )
);
flow_ctrl U_flow_ctrl(
.Reset (Reset ),
.Clk (Clk ),
//host processor (//host processor ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//MAC_rx_flow (//MAC_rx_flow ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val ),
//MAC_tx_ctrl (//MAC_tx_ctrl ),
.pause_apply (pause_apply ),
.pause_quanta_sub (pause_quanta_sub ),
.xoff_gen (xoff_gen ),
.xoff_gen_complete (xoff_gen_complete ),
.xon_gen (xon_gen ),
.xon_gen_complete (xon_gen_complete )
);
`ifdef MAC_SOURCE_REPLACE_EN
MAC_tx_addr_add U_MAC_tx_addr_add(
.Reset (Reset ),
.Clk (Clk ),
.MAC_tx_addr_rd (MAC_tx_addr_rd ),
.MAC_tx_addr_init (MAC_tx_addr_init ),
.MAC_tx_addr_data (MAC_tx_addr_data ),
//CPU (//CPU ),
.MAC_add_prom_data (MAC_add_prom_data ),
.MAC_add_prom_add (MAC_add_prom_add ),
.MAC_add_prom_wr (MAC_add_prom_wr )
);
`else
assign MAC_tx_addr_data=0;
`endif
MAC_tx_FF U_MAC_tx_FF(
.Reset (Reset ),
.Clk_MAC (Clk ),
.Clk_SYS (Clk_user ),
//MAC_rx_ctrl interf (//MAC_rx_ctrl interf ),
.Fifo_data (Fifo_data ),
.Fifo_rd (Fifo_rd ),
.Fifo_rd_finish (Fifo_rd_finish ),
.Fifo_rd_retry (Fifo_rd_retry ),
.Fifo_eop (Fifo_eop ),
.Fifo_da (Fifo_da ),
.Fifo_ra (Fifo_ra ),
.Fifo_data_err_empty (Fifo_data_err_empty ),
.Fifo_data_err_full (Fifo_data_err_full ),
//user interface (//user interface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop ),
//host interface (//host interface ),
.FullDuplex (FullDuplex ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark )
);
Ramdon_gen U_Ramdon_gen(
.Reset (Reset ),
.Clk (Clk ),
.Init (Random_init ),
.RetryCnt (RetryCnt ),
.Random_time_meet (Random_time_meet )
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
wire not1_out_qn ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_PP_V |
module reg_read(in, readAdd1, readAdd2, regValue1, regValue2, equalValue, write, writeAdd, writeR7, inR7, clk, reset);
output [15:0] regValue1, regValue2;
output equalValue;
input [15:0] in, inR7;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, writeR7, clk, reset;
register_file rfile(.clk(clk), .out1(regValue1), .out2(regValue2), .readAdd1(readAdd1), .readAdd2(readAdd2), .write(write), .writeAdd(writeAdd), .writeR7(writeR7), .inR7(inR7), .in(in), .reset(reset));
equal eqCheck(.in1(regValue1), .in2(regValue2), .out(equalValue));
endmodule
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, writeR7, inR7, in, reset); // Modify to include R7 effects
output [15:0] out1, out2;
input [15:0] in, inR7;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset, writeR7;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
decode8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
or a7(writeLines[7], writeR7, ~writeLinesInit[7]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, inR7, writeLines[7], reset);
//register16 r7(clk, data7, (writeR7==1'b1)?inR7:in, ~(writeLines[7] & (~write + ~writeR7)), reset);
endmodule
module equal(in1, in2, out);
output out;
input [15:0] in1, in2;
assign out = (in1==in2);
endmodule
module decode8(selectInput, out); // 8-output decoder
output reg [7:0] out;
input [2:0] selectInput;
always@(selectInput) begin
case(selectInput)
0: out = 8'b00000001;
1: out = 8'b00000010;
2: out = 8'b00000100;
3: out = 8'b00001000;
4: out = 8'b00010000;
5: out = 8'b00100000;
6: out = 8'b01000000;
7: out = 8'b10000000;
endcase
end
endmodule
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
module mux16x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux16x2(data0, data1, selectInput, out); // 2-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1;
input selectInput;
always@(data0 or data1 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
endcase
end
endmodule
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register3(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [2:0] out;
input [2:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 3'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register2(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [1:0] out;
input [1:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 2'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register1(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule |
// This module is a counter for credits, that every decimation_p
// credits it would assert token_o signal once.
// It also supports a ready_i signal which declares when it can
// assert token_o. For normal use it could be set to one.
`include "bsg_defines.v"
module bsg_credit_to_token #( parameter `BSG_INV_PARAM(decimation_p )
, parameter `BSG_INV_PARAM(max_val_p )
)
( input clk_i
, input reset_i
, input credit_i
, input ready_i
, output token_o
);
localparam counter_width_lp = `BSG_WIDTH(max_val_p);
localparam step_width_lp = `BSG_WIDTH(decimation_p);
logic [counter_width_lp-1:0] count;
logic [step_width_lp-1:0] up,down;
logic token_ready, token_almost_ready;
bsg_counter_up_down_variable #(.max_val_p(max_val_p)
,.init_val_p(0)
,.max_step_p(decimation_p)
) credit_counter
( .clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(up)
, .down_i(down)
, .count_o(count)
);
// counting the number of credits, and each token would decrease the count
// by deciation_p.
assign up = {{(step_width_lp-1){1'b0}},credit_i};
assign down = token_o ? step_width_lp'($unsigned(decimation_p)) : step_width_lp'(0);
// if count is one less than decimation_p but credit_i is also asserted and
// ready signal is high, we don't need to wait for next time ready_i signal
// is asserted and we can send a token. In this condition count would be set
// to zero using down and up signal.
assign token_ready = (count >= decimation_p);
assign token_almost_ready = (count >= $unsigned(decimation_p-1));
assign token_o = ready_i & (token_ready | (token_almost_ready & credit_i));
endmodule
`BSG_ABSTRACT_MODULE(bsg_credit_to_token)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR3B_FUNCTIONAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_4_V
`define SKY130_FD_SC_HDLL__A21BOI_4_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_4_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_dmac (
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
// Interrupt
output reg irq,
// Master AXI interface
input m_dest_axi_aclk,
input m_dest_axi_aresetn,
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Write address
output [31:0] m_axi_awaddr,
output [ 7:0] m_axi_awlen,
output [ 2:0] m_axi_awsize,
output [ 1:0] m_axi_awburst,
output [ 2:0] m_axi_awprot,
output [ 3:0] m_axi_awcache,
output m_axi_awvalid,
input m_axi_awready,
// Write data
output [C_M_DEST_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_DEST_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
// Write response
input m_axi_bvalid,
input [ 1:0] m_axi_bresp,
output m_axi_bready,
// Read address
input m_axi_arready,
output m_axi_arvalid,
output [31:0] m_axi_araddr,
output [ 7:0] m_axi_arlen,
output [ 2:0] m_axi_arsize,
output [ 1:0] m_axi_arburst,
output [ 2:0] m_axi_arprot,
output [ 3:0] m_axi_arcache,
// Read data and response
input [C_M_DEST_AXI_DATA_WIDTH-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input [ 1:0] m_axi_rresp,
// Slave streaming AXI interface
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [C_M_DEST_AXI_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
// Master streaming AXI interface
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [C_M_DEST_AXI_DATA_WIDTH-1:0] m_axis_data,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [C_M_DEST_AXI_DATA_WIDTH-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
// Input FIFO interface
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [C_M_DEST_AXI_DATA_WIDTH-1:0] fifo_rd_dout,
output fifo_rd_underflow
);
parameter PCORE_ID = 0;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
parameter C_M_DEST_AXI_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_LENGTH_WIDTH = 14;
parameter C_2D_TRANSFER = 1;
parameter C_CLKS_ASYNC_REQ_SRC = 1;
parameter C_CLKS_ASYNC_SRC_DEST = 1;
parameter C_CLKS_ASYNC_DEST_REQ = 1;
parameter C_AXI_SLICE_DEST = 0;
parameter C_AXI_SLICE_SRC = 0;
parameter C_SYNC_TRANSFER_START = 0;
parameter C_CYCLIC = 1;
parameter C_DMA_TYPE_DEST = DMA_TYPE_AXI_MM;
parameter C_DMA_TYPE_SRC = DMA_TYPE_FIFO;
localparam DMA_TYPE_AXI_MM = 0;
localparam DMA_TYPE_AXI_STREAM = 1;
localparam DMA_TYPE_FIFO = 2;
localparam PCORE_VERSION = 'h00040061;
localparam DMA_ADDR_WIDTH = 32 - C_ADDR_ALIGN_BITS;
localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
// Register interface signals
reg [31:0] up_rdata = 'd0;
wire up_wr;
wire up_sel;
wire [31:0] up_wdata;
wire [13:0] up_addr;
wire up_write;
// Scratch register
reg [31:0] up_scratch = 'h00;
// Control bits
reg up_enable = 'h00;
reg up_pause = 'h00;
// Start and end of transfer
wire up_eot; // Asserted for one cycle when a transfer has been completed
wire up_sot; // Asserted for one cycle when a transfer has been queued
// Interupt handling
reg [1:0] up_irq_mask = 'h3;
reg [1:0] up_irq_source = 'h0;
wire [1:0] up_irq_pending;
wire [1:0] up_irq_trigger;
wire [1:0] up_irq_source_clear;
// DMA transfer signals
reg up_dma_req_valid = 1'b0;
wire up_dma_req_ready;
reg [1:0] up_transfer_id;
reg [1:0] up_transfer_id_eot;
reg [3:0] up_transfer_done_bitmap;
reg [31:C_ADDR_ALIGN_BITS] up_dma_dest_address = 'h00;
reg [31:C_ADDR_ALIGN_BITS] up_dma_src_address = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
wire up_dma_sync_transfer_start = C_SYNC_TRANSFER_START ? 1'b1 : 1'b0;
// ID signals from the DMAC, just for debugging
wire [2:0] dest_request_id;
wire [2:0] dest_data_id;
wire [2:0] dest_address_id;
wire [2:0] dest_response_id;
wire [2:0] src_request_id;
wire [2:0] src_data_id;
wire [2:0] src_address_id;
wire [2:0] src_response_id;
wire [7:0] dbg_status;
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wr(up_wr),
.up_sel(up_sel),
.up_addr(up_addr),
.up_wdata(up_wdata),
.up_rdata(up_rdata),
.up_ack(up_sel)
);
// IRQ handling
assign up_irq_pending = ~up_irq_mask & up_irq_source;
assign up_irq_trigger = {up_eot, up_sot};
assign up_irq_source_clear = (up_write == 1'b1 && up_addr[11:0] == 12'h021) ? up_wdata[1:0] : 0;
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
end
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0) begin
up_irq_source <= 2'b00;
end else begin
up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
end
end
// Register Interface
assign up_write = up_wr & up_sel;
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0) begin
up_enable <= 'h00;
up_pause <= 'h00;
up_dma_src_address <= 'h00;
up_dma_dest_address <= 'h00;
up_dma_y_length <= 'h00;
up_dma_x_length <= 'h00;
up_dma_dest_stride <= 'h00;
up_dma_src_stride <= 'h00;
up_irq_mask <= 3'b11;
up_dma_req_valid <= 1'b0;
up_scratch <= 'h00;
end else begin
if (up_enable == 1'b1) begin
if (up_write && up_addr[11:0] == 12'h102) begin
up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
end else if (up_sot) begin
up_dma_req_valid <= 1'b0;
end
end else begin
up_dma_req_valid <= 1'b0;
end
if (up_write) begin
case (up_addr[11:0])
12'h002: up_scratch <= up_wdata;
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
12'h104: up_dma_dest_address <= up_wdata[31:C_ADDR_ALIGN_BITS];
12'h105: up_dma_src_address <= up_wdata[31:C_ADDR_ALIGN_BITS];
12'h106: up_dma_x_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h107: up_dma_y_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h108: up_dma_dest_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h109: up_dma_src_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
endcase
end
end
end
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0) begin
up_rdata <= 'h00;
end else begin
case (up_addr[11:0])
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= PCORE_ID;
12'h002: up_rdata <= up_scratch;
12'h020: up_rdata <= up_irq_mask;
12'h021: up_rdata <= up_irq_pending;
12'h022: up_rdata <= up_irq_source;
12'h100: up_rdata <= {up_pause, up_enable};
12'h101: up_rdata <= up_transfer_id;
12'h102: up_rdata <= up_dma_req_valid;
12'h103: up_rdata <= 'h00; // Flags
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{C_ADDR_ALIGN_BITS{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{C_ADDR_ALIGN_BITS{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
12'h107: up_rdata <= C_2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= C_2D_TRANSFER ? up_dma_dest_stride : 'h00;
12'h109: up_rdata <= C_2D_TRANSFER ? up_dma_src_stride : 'h00;
12'h10a: up_rdata <= up_transfer_done_bitmap;
12'h10b: up_rdata <= up_transfer_id_eot;
12'h10c: up_rdata <= 'h00; // Status
12'h10d: up_rdata <= m_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
12'h10e: up_rdata <= m_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
12'h110: up_rdata <= {dbg_status};
default: up_rdata <= 'h00;
endcase
end
end
// Request ID and Request done bitmap handling
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin
up_transfer_id <= 'h0;
up_transfer_id_eot <= 'h0;
up_transfer_done_bitmap <= 'h0;
end begin
if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
up_transfer_id <= up_transfer_id + 1'b1;
up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
end
if (up_eot == 1'b1) begin
up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
end
end
end
wire dma_req_valid;
wire dma_req_ready;
wire [31:C_ADDR_ALIGN_BITS] dma_req_dest_address;
wire [31:C_ADDR_ALIGN_BITS] dma_req_src_address;
wire [C_DMA_LENGTH_WIDTH-1:0] dma_req_length;
wire dma_req_eot;
wire dma_req_sync_transfer_start;
wire up_req_eot;
assign up_sot = C_CYCLIC ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
assign up_eot = C_CYCLIC ? 1'b0 : up_req_eot;
generate if (C_2D_TRANSFER == 1) begin
dmac_2d_transfer #(
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS)
) i_2d_transfer (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
.req_eot(up_req_eot),
.req_valid(up_dma_req_valid),
.req_ready(up_dma_req_ready),
.req_dest_address(up_dma_dest_address),
.req_src_address(up_dma_src_address),
.req_x_length(up_dma_x_length),
.req_y_length(up_dma_y_length),
.req_dest_stride(up_dma_dest_stride),
.req_src_stride(up_dma_src_stride),
.req_sync_transfer_start(up_dma_sync_transfer_start),
.out_req_valid(dma_req_valid),
.out_req_ready(dma_req_ready),
.out_req_dest_address(dma_req_dest_address),
.out_req_src_address(dma_req_src_address),
.out_req_length(dma_req_length),
.out_req_sync_transfer_start(dma_req_sync_transfer_start),
.out_eot(dma_req_eot)
);
end else begin
assign dma_req_valid = up_dma_req_valid;
assign up_dma_req_ready = dma_req_ready;
assign dma_req_dest_address = up_dma_dest_address;
assign dma_req_src_address = up_dma_src_address;
assign dma_req_length = up_dma_x_length;
assign dma_req_sync_transfer_start = up_dma_sync_transfer_start;
assign up_req_eot = dma_req_eot;
end endgenerate
dmac_request_arb #(
.C_ID_WIDTH(3),
.C_M_AXI_DATA_WIDTH(C_M_DEST_AXI_DATA_WIDTH),
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_DMA_TYPE_DEST(C_DMA_TYPE_DEST),
.C_DMA_TYPE_SRC(C_DMA_TYPE_SRC),
.C_CLKS_ASYNC_REQ_SRC(C_CLKS_ASYNC_REQ_SRC),
.C_CLKS_ASYNC_SRC_DEST(C_CLKS_ASYNC_SRC_DEST),
.C_CLKS_ASYNC_DEST_REQ(C_CLKS_ASYNC_DEST_REQ),
.C_AXI_SLICE_DEST(C_AXI_SLICE_DEST),
.C_AXI_SLICE_SRC(C_AXI_SLICE_SRC)
) i_request_arb (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
.enable(up_enable),
.pause(up_pause),
.req_valid(dma_req_valid),
.req_ready(dma_req_ready),
.req_dest_address(dma_req_dest_address),
.req_src_address(dma_req_src_address),
.req_length(dma_req_length),
.req_sync_transfer_start(dma_req_sync_transfer_start),
.eot(dma_req_eot),
.m_dest_axi_aclk(m_dest_axi_aclk),
.m_dest_axi_aresetn(m_dest_axi_aresetn),
.m_src_axi_aclk(m_src_axi_aclk),
.m_src_axi_aresetn(m_src_axi_aresetn),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awprot(m_axi_awprot),
.m_axi_awcache(m_axi_awcache),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wlast(m_axi_wlast),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bready(m_axi_bready),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arprot(m_axi_arprot),
.m_axi_arcache(m_axi_arcache),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rresp(m_axi_rresp),
.s_axis_aclk(s_axis_aclk),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user),
.m_axis_aclk(m_axis_aclk),
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_data(m_axis_data),
.fifo_wr_clk(fifo_wr_clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(fifo_wr_sync),
.fifo_rd_clk(fifo_rd_clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_dout(fifo_rd_dout),
.fifo_rd_underflow(fifo_rd_underflow),
// DBG
.dbg_dest_request_id(dest_request_id),
.dbg_dest_address_id(dest_address_id),
.dbg_dest_data_id(dest_data_id),
.dbg_dest_response_id(dest_response_id),
.dbg_src_request_id(src_request_id),
.dbg_src_address_id(src_address_id),
.dbg_src_data_id(src_data_id),
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O211AI_PP_SYMBOL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o211ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFXBP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_SYMBOL_V
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [23:0] SNES_ADDR, // requested address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK
);
wire [23:0] SRAM_SNES_ADDR;
/* static mapper:
menu (ROM in upper SRAM)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ~SNES_ROMSEL;
assign IS_SAVERAM = (!SNES_ADDR[22]
& &SNES_ADDR[21:20]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
);
assign SRAM_SNES_ADDR = (IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hC00000)
);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_SAVERAM;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_BLACKBOX_V
`define SKY130_FD_SC_MS__DFBBN_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BLACKBOX_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_2_V
`define SKY130_FD_SC_LP__NAND3_2_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__XNOR3_PP_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_PP_BLACKBOX_V
|
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Dec 16 2016
//Description: MBus Member Controller for PMU
// Structural verilog netlist using sc_x_hvt_tsmc180
//Update History: May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Combined the following three modules into one:
// lname_mbus_master_sleep_ctrl
// lname_mbus_master_wire_ctrl
// lname_mbus_member_addr_rf
// lname_mbus_int_ctrl
// Fixed potential hold-time violation in ext_int_dout & EXTERNAL_INT
// OLD: int_busy = WAKEUP_REQ & mbus_busy_b
// ext_int_dout and EXTERNAL_INT set to mbus_busy_b @ (posedge int_busy)
// NEW: int_busy = WAKEUP_REQ & mbus_busy_b & LRC_SLEEP
// ext_int_dout and EXTERNAL_INT set to 1 @ (posedge int_busy)
// Dec 16 2016 - Updated for MBus r04
// Fixed CIN glitch issue
// Now MBUS_BUSY_B is generated in mbus_node
// Apr 28 2017 - Updated for MBus r04p1
// More explicit isolation for SLEEP_REQ
// Added PMU DIN Glitch Filtering
// SLEEP_REQ* and MBUS_BUSY are isolated here, rather than in mbus_isolation.
//*******************************************************************************************
module lname_mbus_member_ctrl (
input RESETn,
// MBus Clock & Data
input CIN,
input DIN,
input COUT_FROM_BUS,
input DOUT_FROM_BUS,
output COUT,
output DOUT,
// Sleep & Wakeup Requests
input SLEEP_REQ,
input WAKEUP_REQ,
// Power-Gating Signals
output MBC_ISOLATE,
output MBC_ISOLATE_B,
output MBC_RESET,
output MBC_RESET_B,
output MBC_SLEEP,
output MBC_SLEEP_B,
// Handshaking with MBus Ctrl
input CLR_EXT_INT,
output EXTERNAL_INT,
// Short-Prefix
input ADDR_WR_EN,
input ADDR_CLR_B,
input [3:0] ADDR_IN,
output [3:0] ADDR_OUT,
output ADDR_VALID,
// Interface with PMU
input EN_GLITCH_FILT,
input PMU_ACTIVE,
output PMU_WAKEUP_REQ,
// Misc
input LRC_SLEEP,
input MBUS_BUSY
);
//****************************************************************************
// Internal Wire Declaration
//****************************************************************************
wire cin_b;
wire cin_buf;
wire mbc_sleep_b_int;
wire mbc_isolate_b_int;
wire mbc_reset_b_int;
wire next_mbc_isolate;
wire next_mbc_isolate_b;
wire sleep_req_isol;
wire sleep_req_b_isol;
wire mbc_isolate_int;
wire mbc_sleep_int;
wire goingsleep;
wire mbc_reset_int;
wire clr_ext_int_iso;
wire clr_ext_int_b;
wire RESETn_local;
wire RESETn_local2;
wire mbus_busy_b_isol;
wire int_busy;
wire int_busy_b;
wire ext_int_dout;
wire cout_from_bus_iso;
wire cout_int;
wire cout_unbuf;
wire dout_from_bus_iso;
wire dout_int_1;
wire dout_int_0;
wire dout_unbuf;
wire din_int;
wire setn_pmu_wakeup_req;
wire pmu_wakeup_req_unbuf;
wire addr_clr_b_iso;
wire [3:0] addr_in_iso;
wire RESETn_local3;
wire addr_update;
wire resetn_pmu_wakeup_req;
wire resetn_din_sampled;
wire din_sampled;
wire din_sampled_dly;
wire din_sampled_dly0;
wire din_sampled_dly1;
wire din_glitch_detected;
wire din_glitch_detected_b;
// ---------------------------------------------
// NOTE: Functional Relationship:
// ---------------------------------------------
// MBC_ISOLATE = mbc_isolate_int
// MBC_ISOLATE_B = mbc_isolate_b_int
// MBC_RESET = mbc_reset_int
// MBC_RESET_B = mbc_reset_b_int
// MBC_SLEEP = mbc_sleep_int
// MBC_SLEEP_B = mbc_sleep_b_int
// ---------------------------------------------
// clr_ext_int_b = ~clr_ext_int_iso
// ---------------------------------------------
//****************************************************************************
// GLOBAL
//****************************************************************************
// CIN Buffer
INVX1HVT INV_cin_b (.Y(cin_b), .A(CIN));
INVX2HVT INV_cin_buf (.Y(cin_buf), .A(cin_b));
//****************************************************************************
// SLEEP CONTROLLER
//****************************************************************************
//assign MBC_SLEEP_B = ~MBC_SLEEP;
INVX1HVT INV_mbc_sleep_b_int (.Y(mbc_sleep_b_int), .A(mbc_sleep_int));
INVX8HVT INV_MBC_SLEEP (.Y(MBC_SLEEP), .A(mbc_sleep_b_int));
INVX8HVT INV_MBC_SLEEP_B (.Y(MBC_SLEEP_B), .A(mbc_sleep_int));
//assign MBC_ISOLATE_B = ~MBC_ISOLATE;
INVX1HVT INV_mbc_isolate_b_int (.Y(mbc_isolate_b_int), .A(mbc_isolate_int));
INVX8HVT INV_MBC_ISOLATE (.Y(MBC_ISOLATE), .A(mbc_isolate_b_int));
INVX8HVT INV_MBC_ISOLATE_B (.Y(MBC_ISOLATE_B), .A(mbc_isolate_int));
//assign MBC_RESET_B = ~MBC_RESET;
INVX1HVT INV_mbc_reset_b_int (.Y(mbc_reset_b_int), .A(mbc_reset_int));
INVX8HVT INV_MBC_RESET (.Y(MBC_RESET), .A(mbc_reset_b_int));
INVX8HVT INV_MBC_RESET_B (.Y(MBC_RESET_B), .A(mbc_reset_int));
//assign next_mbc_isolate = goingsleep | sleep_req_isol | MBC_SLEEP;
INVX1HVT INV_next_mbc_isolate (.Y(next_mbc_isolate), .A(next_mbc_isolate_b));
NOR3X1HVT NOR3_next_mbc_isolate_b (.C(goingsleep), .B(sleep_req_isol), .A(mbc_sleep_int), .Y(next_mbc_isolate_b));
//assign sleep_req_isol = SLEEP_REQ & MBC_ISOLATE_B;
INVX1HVT INV_next_goingsleep (.Y(sleep_req_isol), .A(sleep_req_b_isol));
NAND2X1HVT NAND2_next_goingsleep_b (.Y(sleep_req_b_isol), .A(SLEEP_REQ), .B(mbc_isolate_b_int));
// goingsleep, mbc_sleep_int, mbc_isolate_int, mbc_reset_int
DFFSRX1HVT DFFSR_mbc_isolate_int (.SN(RESETn), .RN(1'b1), .CK(cin_buf), .Q(mbc_isolate_int), .D(next_mbc_isolate));
DFFSRX1HVT DFFSR_mbc_sleep_int (.SN(RESETn), .RN(1'b1), .CK(cin_buf), .Q(mbc_sleep_int), .D(goingsleep));
DFFSRX1HVT DFFSR_goingsleep (.SN(1'b1), .RN(RESETn), .CK(cin_buf), .Q(goingsleep), .D(sleep_req_isol));
DFFSRX1HVT DFFSR_mbc_reset_int (.SN(RESETn), .RN(1'b1), .CK(cin_b), .Q(mbc_reset_int), .D(mbc_isolate_int));
//****************************************************************************
// INTERRUPT CONTROLLER
//****************************************************************************
//wire clr_ext_int_b = ~(MBC_ISOLATE_B & CLR_EXT_INT);
AND2X1HVT AND2_clr_ext_int_iso (.Y(clr_ext_int_iso), .A(MBC_ISOLATE_B), .B(CLR_EXT_INT));
INVX1HVT INV_clr_ext_int_b (.Y(clr_ext_int_b), .A(clr_ext_int_iso));
//wire RESETn_local = RESETn & CIN;
AND2X1HVT AND2_RESETn_local (.Y(RESETn_local), .A(CIN), .B(RESETn));
//wire RESETn_local2 = RESETn & clr_ext_int_b;
AND2X1HVT AND2_RESETn_local2 (.Y(RESETn_local2), .A(clr_ext_int_b), .B(RESETn));
//wire mbus_busy_b_isol = ~(MBUS_BUSY & MBC_RESET_B);
NAND2X1HVT NAND2_mbus_busy_b_isol (.A(MBUS_BUSY), .B(mbc_reset_b_int), .Y(mbus_busy_b_isol));
//wire int_busy = (WAKEUP_REQ & mbus_busy_b_isol & LRC_SLEEP)
NAND3X1HVT NAND3_int_busy_b (.A(WAKEUP_REQ), .B(mbus_busy_b_isol), .C(LRC_SLEEP), .Y(int_busy_b));
INVX2HVT INV_int_busy (.Y(int_busy), .A(int_busy_b));
// ext_int_dout
DFFRX1HVT DFFR_ext_int_dout (.RN(RESETn_local), .CK(int_busy), .Q(ext_int_dout), .D(1'b1));
// EXTERNAL_INT
DFFRX1HVT DFFR_EXTERNAL_INT (.RN(RESETn_local2), .CK(int_busy), .Q(EXTERNAL_INT), .D(1'b1));
//****************************************************************************
// WIRE CONTROLLER
//****************************************************************************
// COUT
OR2X1HVT OR2_cout_from_bus_iso (.Y(cout_from_bus_iso), .A(COUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2GFX1HVT MUX2_cout_int (.S(MBC_ISOLATE), .A(cout_from_bus_iso), .Y(cout_int), .B(CIN));
MUX2GFX1HVT MUX2_cout_unbuf (.S(RESETn), .A(1'b1), .Y(cout_unbuf), .B(cout_int));
BUFX4HVT BUF_COUT (.A(cout_unbuf), .Y(COUT));
// DOUT
OR2X1HVT OR2_dout_from_bus_iso (.Y(dout_from_bus_iso), .A(DOUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2GFX1HVT MUX2_din_int (.S(PMU_ACTIVE), .A(1'b1), .B(DIN), .Y(din_int));
MUX2GFX1HVT MUX2_dout_int_1 (.S(MBC_ISOLATE), .A(dout_from_bus_iso), .B(din_int), .Y(dout_int_1));
MUX2GFX1HVT MUX2_dout_int_0 (.S(ext_int_dout), .A(dout_int_1), .Y(dout_int_0), .B(1'b0));
MUX2GFX1HVT MUX2_dout_unbuf (.S(RESETn), .A(1'b1), .Y(dout_unbuf), .B(dout_int_0));
BUFX4HVT BUF_DOUT (.A(dout_unbuf), .Y(DOUT));
// Interface with PMU w/ DIN glitch prevention
OR2X1HVT OR2_setn_pmu_wakeup_req (.A(DIN), .B(MBC_SLEEP_B), .Y(setn_pmu_wakeup_req));
DFFSRX1HVT DFFSR_pmu_wakeup_req_unbuf (.D(1'b0), .CK(MBC_SLEEP), .SN(setn_pmu_wakeup_req), .RN(resetn_pmu_wakeup_req), .Q(pmu_wakeup_req_unbuf));
BUFX4HVT BUF_PMU_WAKEUP_REQ (.A(pmu_wakeup_req_unbuf), .Y(PMU_WAKEUP_REQ));
DFFRX1HVT DFFR_din_sampled (.D(DIN), .CK(PMU_ACTIVE), .RN(resetn_din_sampled), .Q(din_sampled));
AND2X1HVT AND_din_sampled_masked (.A(EN_GLITCH_FILT), .B(PMU_WAKEUP_REQ), .Y(resetn_din_sampled));
BUFX1HVT BUF_din_sampled_dly0 (.A(din_sampled), .Y(din_sampled_dly0));
BUFX1HVT BUF_din_sampled_dly1 (.A(din_sampled_dly0), .Y(din_sampled_dly1));
BUFX1HVT BUF_din_sampled_dly (.A(din_sampled_dly1), .Y(din_sampled_dly));
NAND2X1HVT NAND2_din_glitch_detected_b(.A(PMU_ACTIVE), .B(din_sampled_dly), .Y(din_glitch_detected_b));
AND2X1HVT AND2_resetn_pmu_wakeup_req (.A(din_glitch_detected_b), .B(RESETn), .Y(resetn_pmu_wakeup_req));
//****************************************************************************
// SHORT-PREFIX ADDRESS REGISTER
//****************************************************************************
// Isolation
OR2X1HVT AND2_addr_clr_b_iso (.A(MBC_ISOLATE), .B(ADDR_CLR_B), .Y(addr_clr_b_iso));
AND2X1HVT AND2_addr_in_iso_0 (.A(MBC_ISOLATE_B), .B(ADDR_IN[0]), .Y(addr_in_iso[0]));
AND2X1HVT AND2_addr_in_iso_1 (.A(MBC_ISOLATE_B), .B(ADDR_IN[1]), .Y(addr_in_iso[1]));
AND2X1HVT AND2_addr_in_iso_2 (.A(MBC_ISOLATE_B), .B(ADDR_IN[2]), .Y(addr_in_iso[2]));
AND2X1HVT AND2_addr_in_iso_3 (.A(MBC_ISOLATE_B), .B(ADDR_IN[3]), .Y(addr_in_iso[3]));
//wire RESETn_local3 = (RESETn & ADDR_CLR_B);
AND2X1HVT AND2_RESETn_local3 (.A(RESETn), .B(addr_clr_b_iso), .Y(RESETn_local3));
//wire addr_update = (ADDR_WR_EN & (~MBC_ISOLATE));
AND2X1HVT AND2_addr_update (.A(MBC_ISOLATE_B), .B(ADDR_WR_EN), .Y(addr_update));
// ADDR_OUT, ADDR_VALID
DFFSX1HVT DFFS_ADDR_OUT_0 (.CK(addr_update), .D(addr_in_iso[0]), .SN(RESETn_local3), .Q(ADDR_OUT[0]));
DFFSX1HVT DFFS_ADDR_OUT_1 (.CK(addr_update), .D(addr_in_iso[1]), .SN(RESETn_local3), .Q(ADDR_OUT[1]));
DFFSX1HVT DFFS_ADDR_OUT_2 (.CK(addr_update), .D(addr_in_iso[2]), .SN(RESETn_local3), .Q(ADDR_OUT[2]));
DFFSX1HVT DFFS_ADDR_OUT_3 (.CK(addr_update), .D(addr_in_iso[3]), .SN(RESETn_local3), .Q(ADDR_OUT[3]));
DFFRX1HVT DFFR_ADDR_VALID (.CK(addr_update), .D(1'b1), .RN(RESETn_local3), .Q(ADDR_VALID));
endmodule // lname_mbus_member_ctrl
|
`default_nettype none
module square_root32_element #(
parameter P_IN_N = 4,
parameter P_DFF = 1
)(
input wire iCLOCK,
input wire inRESET,
//Input
input wire iDATA_REQ,
output wire oDATA_BUSY,
input wire [P_IN_N/2-1:0] iDATA_P,
input wire [31:0] iDATA_I,
//Output
output wire oDATA_VALID,
input wire iDATA_BUSY,
output wire [P_IN_N/2-1:0] oDATA_P,
output wire [31:0] oDATA_I
);
function [P_IN_N/2-1:0] func_cell_gen;
input [P_IN_N/2-1:0] func_data_p;
input [31:0] func_data_i;
reg [P_IN_N-1:0] func_pri_data;
begin
func_pri_data = func_data_p * func_data_p;
if(func_data_i[31:32-P_IN_N] >= func_pri_data)begin
func_cell_gen = func_data_p;
end
else begin
func_cell_gen = {func_data_p[P_IN_N/2-1:1], 1'b0};
end
end
endfunction
generate
if(P_DFF)begin
//D-FF Delay
reg b_buffer_req;
reg [P_IN_N/2-1:0] b_buffer_p;
reg [31:0] b_buffer_i;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_buffer_req <= 1'b0;
end
else if(iDATA_BUSY)begin
b_buffer_req <= b_buffer_req;
end
else begin
b_buffer_req <= iDATA_REQ;
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_buffer_p <= {P_IN_N/2{1'b0}};
end
else if(iDATA_BUSY)begin
b_buffer_p <= b_buffer_p;
end
else begin
b_buffer_p <= func_cell_gen(iDATA_P, iDATA_I);
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_buffer_i <= 32'h0;
end
else if(iDATA_BUSY)begin
b_buffer_i <= b_buffer_i;
end
else begin
b_buffer_i <= iDATA_I;
end
end
assign oDATA_VALID = b_buffer_req;
assign oDATA_P = b_buffer_p;
assign oDATA_I = b_buffer_i;
end
else begin
//Combination
assign oDATA_VALID = iDATA_REQ;
assign oDATA_P = func_cell_gen(iDATA_P, iDATA_I);
assign oDATA_I = iDATA_I;
end
endgenerate
assign oDATA_BUSY = iDATA_BUSY;
endmodule
`default_nettype wire
|
`ifndef _alu
`define _alu
module alu(
input [5:0] funct,
input [5:0] opcode,
input [31:0] a, b,
output reg [31:0] out,
output zero);
// control (opcode -> ...)
wire regdst;
wire [1:0] branch_s2;
wire memread;
wire memwrite;
wire memtoreg;
wire [1:0] aluop;
wire regwrite;
wire alusrc;
control ctl1(.branch(branch_s2),
/*AUTOINST*/
// Outputs
.regdst (regdst),
.memread (memread),
.memtoreg (memtoreg),
.aluop (aluop[1:0]),
.memwrite (memwrite),
.alusrc (alusrc),
.regwrite (regwrite),
// Inputs
.opcode (opcode[5:0])); //fixme: opcode may need be stored in rob/rs
// ALU control
wire [3:0] aluctl;
alu_control alu_ctl1(.aluop(aluop),
/*AUTOINST*/
// Outputs
.aluctl (aluctl[3:0]),
// Inputs
.funct (funct[5:0]));//fixme: funct may need be stored in rob/rs
wire [31:0] sub_ab;
wire [31:0] add_ab;
wire oflow_add;
wire oflow_sub;
wire oflow;
wire slt;
assign zero = (0 == out);
assign sub_ab = a - b;
assign add_ab = a + b;
// overflow occurs (with 2's complement numbers) when
// the operands have the same sign, but the sign of the result is
// different. The actual sign is the opposite of the result.
// It is also dependent on wheter addition or subtraction is performed.
assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0;
assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0;
assign oflow = (aluctl == 4'b0010) ? oflow_add : oflow_sub;
// set if less than, 2s compliment 32-bit numbers
assign slt = oflow_sub ? ~(a[31]) : a[31];
always @(*) begin
case (aluctl)
4'b0010: out <= add_ab; // a + b
4'b0000: out <= a & b; // and
4'b1100: out <= ~(a | b); // nor
4'b0001: out <= a | b; // or
4'b0111: out <= {{31{1'b0}}, slt}; // set if less than
4'b0110: out <= sub_ab; // a - b
4'b1101: out <= a ^ b; // xor
default: out <= 0;
endcase
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_SYMBOL_V
`define SKY130_FD_SC_LP__DLCLKP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_SYMBOL_V
|
(** * MoreCoq_J: CoqのTacticsについてもう少し*)
Require Export Poly_J.
(** This chapter introduces several more proof strategies and
tactics that, together, allow us to prove theorems about the
functional programs we have been writing. In particular, we'll
reason about functions that work with natural numbers and lists.
In particular, we will see:
- how to use auxiliary lemmas, in both forwards and backwards reasoning;
- how to reason about data constructors, which are injective and disjoint;
- how to create a strong induction hypotheses (and when
strengthening is required); and
- how to reason by case analysis.
*)
(** この章で、いくつかの証明戦略とタクティックを消化します。それによって、我々がこれまで書いてきた関数型プログラムについて、証明が容易になります。取り分け、自然数とリストについての関数について推論しやすくなるでしょう。
- 前向き推論と後ろ向き推論の両方において、補題(補助的な証明)の使い方。
- データコンストラクタについての推論をどのように行うか。 単射であったりお互いが素であることもあります。。
- 強力な帰納法の仮定の生成の仕方。(強力さが求められる場合に。)
- ケース分析による推論の仕方。
*)
(* ###################################################### *)
(** * The [apply] Tactic *)
(* We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
(** 証明をしていると、証明すべきゴールがコンテキスト中の仮定と同じであったり以前証明した補題と同じであることがしばしばあります。*)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
(* このような場合は、
"[rewrite -> eq2. reflexivity.]"
として証明を終えてきましたが、 [apply] タクティックを使えば一回で同じ結果が得られます。*)
apply eq2. Qed.
(* The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
(** また、 [apply] タクティックは、条件付きの仮定や補題にも使うことができます。適用するものに含意が含まれていれば、含意の前提部分が証明すべきサブゴールに加えられます。*)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(* You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** この証明で、 [apply] の代わりに [rewrite] を使って証明を終えられるか試してみると有益でしょう。*)
(* Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
(** [apply H] を使う典型的な例は、 [H] が [forall] で始まり、何らかの全称限量された変数を束縛している場合です。現在のゴールが [H] の帰結部と一致した場合には、変数に対応する適当な値を見つけてくれます。例えば、次の証明で [apply eq2] すると、 [eq2] 内の変数 [q] は [n] に、 [r] は [m] に具体化されます。*)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** 練習問題: ★★, optional (silly_ex) *)
(* Complete the following proof without using [simpl]. *)
(** 次の証明を [simpl] を使わずに完成させなさい。 *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
(** [apply] タクティックを使う場合には、適用する事実（の帰結部）が、ゴールと完全に一致していなければなりません。例えは、等式の左辺と右辺が入れ替わっているだけでも [apply] タクティックは使えません。*)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
(* ここでは[apply]が使えません。*)
Abort.
(* In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
(** そのような場合には [symmetry] タクティックを使って、ゴールの等式の左辺と右辺を入れ替えることができます。 *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will do a [simpl] step first. *)
(* 実際には、この [simpl] は必須ではありません。 [apply] は最初に [simpl] をします。 *)
apply H. Qed.
(** **** 練習問題: ★★★, recommended (apply_exercise1) *)
(* Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
(** ヒント: コンテスキト中の補題以外にも、以前に定義した補題を [apply] することができます。こんなときには [SearchAbout] を使うのでしたね。*)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(* Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied? *)
(** [apply] と [rewrite] の違いを簡単に説明しなさい。どちらもうまく使えるような場面はありますか？
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(* * The [apply ... with ...] Tactic *)
(** ** [apply ... with ...]タクティック *)
(* The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
(** 次の例は、[[a,b]]から[[e,f]]を得るためにrewriteを二回も使っており、少し要領が悪く思われます。 *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
(** このようなことがよくあるため、等式が推移的である事実を補題としておきます。 *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(* Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
(** そして、[trans_eq]をさきほどの証明に使ってみます。しかし、実際にやってみると[apply]タクティックに多少細工が必要なことがわかります。 *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
(* ここで単純に[apply trans_eq]とすると（その補題の結論をゴールにマッチすることで）[X]を[[nat]]に、[n]を[[a,b]]に、[o]を[[e,f]]にあてはめようとします。しかしこのマッチングでは、[m]に何をあてはめるかを決めることができません。そこで、[with (m:=[c,d])]を明示的に情報として追加することで[apply]を動かします。 *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(* Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** 実際には、このように名前[m]を[with]に与えるということはそれほど多くありません。Coqは多くの場合賢く振舞って、我々の要求を実現してくれます。ちなみにこの上の[apply]はapply trans_eq with [c,d]と書くこともできます。 *)
(** **** 練習問題: ★★★, recommended (apply_with_exercises) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(* * The [inversion] tactic *)
(** * [inversion] タクティック *)
(* Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** 自然数の定義を思い出してください。
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
この定義から、全ての数は二つの形式、コンストラクタ[O]で作られたか、コンストラクタ[S]に他の数値を与えて作られたかのどちらかであることは明白です。しかし両目を見開いてよく見ると、この定義（と、他のプログラミング言語で、データ型の定義がどのように働くか、という非形式的な理解）から、二つの暗黙的な事実が見つかります。
- コンストラクタ[S]が単射であること。つまり、[S n = S m]となるためのただ一つの方法は[n = m]であること。
- コンストラクタ[O]とコンストラクタ[S]は、互いに素であること。つまり、[O]はどんな[n]についても[S n]と等しくないということ。 *)
(* Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** 同じ原理が、全ての帰納的に定義された型にあてはまります。全てのコンストラクタは単射で、コンストラクタが違えば同じ値は生まれません。リストについて言えば[cons]コンストラクタは単射で、[nil]は全ての空でないリストと異なっています。[bool]型では、[true]と[false]は異なるものです（ただ、[true]も[false]も引数を取らないため、単射かどうか、という議論には意味がありません）。 *)
(* Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** Coqには、この性質を証明に利用する[inversion]というタクティックが用意されています。
[inversion]タクティックは、次のような場合に使います。コンテキストに以下のような形の仮定[H]（や過去に定義された補助定理）がある場合、
c a1 a2 ... an = d b1 b2 ... bm
これは、あるコンストラクタ[c]と[d]に、ある引数[a1 ... an]と[b1 ... bm]を与えて評価したものが等しいことを示していますが、
このような時、[inversion H]とすることで、この等式を"反転"し、そこに含まれている情報を以下のようなやり方で引き出します。
- もし[c]と[d]が同じコンストラクタの場合、すでに分かっているように、コンストラクタの単射性から、[a1 = b1], [a2 = b2]をが導かれます。
また、[inversion H]はこの事実をコンテキストに追加し、ゴールの置き換えに使えないかを試します。
- もし[c]と[d]が違うコンストラクタの場合、仮定[H]は矛盾していることになります。つまり、偽である前提がコンテキストに紛れ込んでいるということになり、これはどんなゴールも証明できてしまうことを意味します。このような場合、[inversion H]は現在のゴールが解決されたものとして、ゴールの一覧から取り除きます。 *)
(* The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
(** [inversion]タクティックは、このような一般的な説明を読むより、その動きを実際に見てもらったほうが簡単に理解できるでしょう。以下は[inversion]の使い方を見てもらい、理解するための練習を兼ねた定理の例です。 *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(* As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
(** 便利なように、[inversion]タクティックは、等式でつながった複合値を展開して、それぞれを対応する相手に結び付けてくれます。 *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** 練習問題: ★ (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** 練習問題: ★ (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
(** コンストラクタの単射性が、[forall (n m : nat), S n = S m -> n = m]を示している一方で、これを逆に適用することで、普通の等式の証明をすることができれば、これまで出てきたいくつかのケースにも使えるでしょう。 *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** 練習問題: ★★, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
(*二三の些細ではないけれどそれほど入り組んでもいない証明にクラスで一緒に、あるいは、練習として取り組んでみましょう。*)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(* ** Using Tactics on Hypotheses *)
(** ** タクティックを仮定に使用する *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
(** デフォルトでは、ほとんどのタクティックはゴールの式に作用するだけで、コンテキストの内容には手を付けません。しかしながら、ほとんどのタクティックは変数を付けることで同じ操作をコンテキストの式に行うことができます。
例えば、[simpl in H]というタクティックは、コンテキストの中の[H]と名前のついた仮定に対して簡約をします。 *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
(** 同様に、[apply L in H]というタクティックは、ある条件式[L] ([L1 -> L2]といった形の)を、コンテキストにある仮定[H]に適用します。しかし普通の[apply]と異なるのは、[apply L in H]が、[H]が[L1]とマッチすることを調べ、それに成功したらそれを[L2]に書き換えることです。
言い換えると、[apply L in H]は、"前向きの推論"の形をとっているといえます。それは、[L1 -> L2]が与えられ、仮定と[L1]がマッチしたら、仮定は[L2]と同じと考えてよい、ということです。逆に、[apply L]は"逆向きの推論"であると言えます。それは、[L1->L2]であることが分かっていて、今証明しようとしているものが[L2]なら、[L1]を証明すればよいとすることです。
以前やった証明の変種を挙げておきます。逆向きの推論ではなく、前向きの推論を進めましょう。 *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(* Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** 前向きの推論は、与えられたもの（前提や、すでに証明された定理）からスタートして、そのゴールを次々につなげていき、ゴールに達するまでそれを続けます。逆向きの証明は、ゴールからスタートし、そのゴールが結論となる前提を調べ、それを前提や証明済みの定理にたどりつくまで繰り返します。皆さんがこれまで（数学やコンピュータサイエンスの分野で）見てきた非形式的な証明は、おそらく前向きの証明であったのではないかと思います。一般にCoqでの証明は逆向きの推論となる傾向があります。しかし、状況によっては前向きの推論のほうが簡単で考えやすい、ということもあります。 *)
(** **** 練習問題: ★★★, recommended (plus_n_n_injective) *)
(* Practice using "in" variants in this exercise. *)
(** 先に述べた"in"を使って次の証明をしなさい。 *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Hint: use the plus_n_Sm lemma *)
(* ヒント: 補題plus_n_Smを使用します *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** * 帰納法の仮定の変更 *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
(**
ときどきCoqにおいて、帰納的な証明を実行する際に、仮定を展開することをコントロールすることが重要になることがあります。ゴールからコンテキストへ[induction]タクティックを使用する前に([intros]を使用して)仮定を移動する時は特に気をつける必要があります。例えば、[double]関数が単射である、すなわち、異なる引数で[double]を実行すれば異なる結果になるということ、を示したいとしましょう。
Theorem double_injective: forall n m, double n = double m -> n = m.
この証明を始める方法は少々デリケートです。
intros n. induction n.
で始めればうまくいきます。 しかし
intros n m. induction n.
で始めてしまうと、帰納段階の途中でつまってしまいます...
*)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* ここでつまってしまいました。 帰納法の仮定 [IHn']は n' = m' を与えてくれません。 -- 邪魔で余計なSがあります。 そのためゴールは証明不可能です。*)
Abort.
(* What went wrong? *)
(** 何がいけなかったのでしょうか? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(**
帰納法の仮定を導入した時点で [m] をコンテキストに導入してしまっていることが問題です。直感的に言うと、これはCoqに「ある特定の [n] と [m] について考えよう」と教えるようなものです。そのため、この特定の [n] と [m] について [double n = double m] ならば [n = m] を証明しなければなりません。
次のタクティックス [induction n] はCoqに「このゴールの [n] に関する帰納法で示します」と伝えます。 なので、命題
- [P n] = "[double n = double m] ならば [n = m]"
がすべての[n]について成り立つことを
- [P O]
(すなわち、"[double O = double m] ならば [O = m]")
- [P n -> P (S n)]
(すなわち、 "[double n = double m] ならば [n = m]" が成り立つならば "
[double (S n) = double m] ならば [S n = m]").
2つめの文を見ると、これは奇妙なことを言っています。 それによると特定の [m] について
- "[double n = double m] ならば [n = m]"
が成り立つならば
- "[double (S n) = double m] ならば [S n = m]".
が証明できることになります。
これがどう奇妙かを説明するために、特定の [m] 、例えば [5] について考えてみましょう。 するとこの文は
- [Q] = "[double n = 10] ならば [n = 5]"
が成り立つならば
- [R] = "[double (S n) = 10] ならば [S n = 5]".
が証明できると言っています。
しかし [Q] を知っていても、[R]を証明するのには何の役にたちません! (もし [Q] から [R] を示そうとすると「[double (S n) = 10]...を仮定すると...」のようなことを言わないといけませんが、これは途中でつまってしまいます。 [double (S n)] が [10] があることは、 [double n]が[10]であるかどうかについては何も教えてくれません。なので[Q] はここでは役にたちません。)
*)
(* To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** まとめると、[m]がすでにコンテキストにある状態で[n]に関する帰納法による証明がうまくいかないのは、すべての[n]と単一の[m]の関係を示そうとしてしまうかからです。*)
(* The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
(** [double_injective] のいい証明では、[induction]を[n]に対して使う時点では[m]をゴールに残しています。 *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
(* ゴールと帰納法の仮説の両方が変更されたことに注意してください。ゴールはもっと一般的な何かを証明するかどうかを我々に尋ねます。(たとえば、全ての[m]についての文を証明するとか)一方IHは、我々がIHを適用するとき、好きな[m]を選ぶことが出来るといった柔軟なものになります。
*)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
(*
ここで我々は特定の[m]を選び、[double n = double m]という仮定を導入します。[n]についてのケース分析を行っているので、[m]についてのケース分析が、それぞれの[n]のケースで必要になります。 *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
(* ここで、[destruct m]の二つ目のケースに我々はいます。[m']はこの時点のコンテキストのなかで言及されている[m']は実際、我々が言及を開始したものの一つ前のものです。もし、一般の[m]をIHの中で我々がたった今言及した[m']を用いてインスタンス化する(このインスタンス化は[apply]を実行することで自動的に行われるのですが)ならば、
我々が証明を終らせるために必要なものを確かに与えてくれるでしょう。なに書いてんだかさっぱり*)
apply IHn'. inversion eq. reflexivity. Qed.
(* What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** 帰納法によって証明しようとしていることが、限定的すぎないかに注意する必要があることを学びました。
もし[n]と[m]の性質に関する証明を[n]に関する帰納法で行ないたい場合は、[m]を一般的なままにしておく必要があるかもしれません。
*)
(* The proof of this theorem has to be treated similarly: *)
(* この定理の証明も同様の処理を行なう必要があります。*)
(** **** 練習問題: ★★, (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★, advanced (beq_nat_true_informal) *)
(* Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(** [beq_nat_true]の 非形式的な証明を可能な限り、数量子について明示的に行いなさい。*)
(* FILL IN HERE *)
(** [] *)
(* The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
(** この戦略がいつもそのまま使えるわけではありません。ときには、ちょっとした工夫が必要です。 例えば、[double_injective]を[n]ではなく[m]に関する帰納法で示したいとします。 *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
(* 以前と同じようにここでまた詰ります。*)
Abort.
(* The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** [m]に関する帰納法の問題点は、最初に[n]をintroしなければいけないことです。 (もし何も導入せずに[induction m]をしても、Coqは自動的に[n]をintroします!) *)
(* What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** どうしたらいいでしょうか? ありうる方法の一つは、補題の文を書き換えて[n]より先に[m]がくるようにすることです。
これはうまくいきますが、いい方法ではありません。
特定の証明戦略のために補題の文をめちゃくちゃにしたくありません。
補題の文はできるかぎり明確かつ自然な形であるべきです。*)
(* What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
(** その代わりに、いったんすべての限量変数を導入し、そのうちいくつかをコンテキストから取りゴールの先頭に置くことで、再び一般化します。これは[generalize dependent]タクティックスによって実現できます。 *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
(* ここで[n]はゴールに戻されて、[m]についての帰納法を行うことが出来、効率的に一般化されたIHを得られる。*)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(* Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(**
この定理の非形式な証明を見てみましょう。なお [n]を限量化したまま帰納法によって命題を証明する箇所は、形式的な証明では generalize dependent を使う箇所に対応します。
_Theorem_: すべての自然数 [n] と [m] について、 [double n = double m] ならば [n = m]。
_Proof_: [m]を[nat]とする。 [m]に関する帰納法によって、 すべての[n] に対して [double n = double m] ならば [n = m] を示す。
- 最初に [m = 0] と仮定し、[n] を [double n = double m] をみたす数とし、 [n = 0] を示す。
[m = 0]なので、[double]の定義より[double n = 0]。
[n] について2つの場合分けが考えれる。
[n = 0] ならば、それが示したいことなので、すでに終了している。
そうでなくて[n = S n']となる[n']が存在する場合、矛盾を導くことで証明する。
[double]の定義により[n = S (S (double n'))]だが、これは仮定 [dobule n = 0] と矛盾する。
- そうでない場合、[m = S m'] と仮定し、[n]は再び [double n = double m] をみたす数とする。 [n = S m']を示すために、 帰納法の仮定「 すべての数 [s] に対して [double s = double m']ならば[s = m']」を用いる。
[m = S m']と[double]の定義により、[double n = S (S (double m'))]。 [n]に関して2つの場合分けが考えられる。
[n = 0]ならば、定義により[double n = 0]となり、矛盾を導ける。
なので、[n = S n']となる[n']があると仮定すると、再び[double]の定義により、
[S (S (double n')) = S (S (double m'))]。 ここでinversionにより[double n' = dobule m']。
帰納法の仮定を[n']をあてはめることで、[n' = m']という結論を導ける。
[S n' = n]かつ[S m' = m]なので、これにより示せる。 []
*)
(* Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
(** [inversion]と一般的な帰納法の仮定の適切な使用法をもう一つ示しておきましょう。これは既に上で証明した事実の遠回りして述べています。余分な等式があることで、等式の推論とこれまでに見て来たタクティックの練習になります。*)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(* It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
(** 上記の定理を証明するために、nとeqをコンテキストに上げてから始めてみたくなるかもしれません。しかし、これは、十分に強力でない帰納法の仮定につながります。上記の証明を次の(失敗する)試みとくらべてみましょう。
*)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* IH が適用出来ない! *)
(* As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** doubleの例で見たように、問題は、[l]についての帰納法を始める前に、[n]をコンテキストに導入することです。そのため帰納法の仮定はある特定の[n]という名前の数に特化されてしまいました。しかし帰納法の場合には、他の数[n']についての帰納法の仮定を使えることが必要になります。 帰納法の仮定の一般化された形式を保ち続けることで、我々は柔軟に扱えるようになります。
*)
(** **** 練習問題: ★★★ (gen_dep_practice) *)
(* Prove this by induction on [l]. *)
(** [l]に関する帰納法で以下を示しなさい。 *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★, advanced, optional (index_after_last_informal) *)
(* Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** 練習問題: ★★★, optional (index_after_last_informal) *)
(** [index_after_last]のCoqによる証明に対応する非形式的な証明を書きなさい。
_Theorem_: すべてのSet [X], リスト [l : list X], 自然数[n]に対して、[length l = n] ならば [index (S n) l = None]。
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** 練習問題: ★★★, optional (gen_dep_practice_more) *)
(* Prove this by induction on [l]. *)
(** [l]に関する帰納法で証明しなさい。 *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★, optional (app_length_cons) *)
(* Prove this by induction on [l1], without using [app_length]. *)
(** [l1]に関する帰納法を用いて証明しなさい。また、[app_length]は使用しないこと *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★★, optional (app_length_twice) *)
(* Prove this by induction on [l], without using app_length. *)
(** [l]に関する帰納法を用いて証明しなさい。また、app_lengthは使用しないこと *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★, optional (double_induction) *)
(* Prove the following principle of induction over two naturals. *)
(** 次の二つの自然数についての帰納法の原理を証明しなさい *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** * [destruct]を複合式で使う *)
(* We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
(** ここまで[destruct]タクティックがいくつかの変数の値についてケース分析を行う例をたくさん見てきました。しかし時には、ある式の結果についてケース分析をすることで証明を行う必要があります。このような場合にも[destruct]タクティックが使えます。.
例を見てください。 *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(* After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** 上の証明で[sillyfun]を展開すると、[if (beq_nat n 3) then ... else ...]で行き詰まることがわかります。そこで、[n]が[3]である場合とそうでない場合とに[destruct (beq_nat n 3)]を使って二つのケースに分け、証明を行います。
一般的に、[destruct]タクティックは任意の計算の結果のケース分析を行うために使用されます。もし[e]が式で、その式の型が帰納的に定義された型[T]であるような場合、[T]のそれぞれのコンストラクタ[c]について、[destruct e]は[e]のすべての文節に対応するサブゴールを生成し、、起こりえる全ての（ゴールやコンテキストにある）eの状態をコンストラクタcで網羅的に置き換えます。
*)
(** **** 練習問題: ★ (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★, optional (combine_split) *)
(* Complete the proof below *)
(** 以下の証明を完成させなさい。 *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** 時折、(変数でない)複合式をdestructで置き換えする場合に、証明に必要な情報が失われてしまうことがあります。*)
(* For example, suppose
we define a function [sillyfun1] like this: *)
(**例えば、関数[sillyfun1]を次のように定義したとします。 *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(* And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
(** そしてCoqを使いよく観察することで、[sillyfun1 n]が、[n]が奇数のときだけ[true]となりうることを示したいとします。先ほど[sillyfun]でやった証明を参考に類推すると、証明はこんな風に始まるのが自然に思えます。 *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* 手詰まり... *)
Abort.
(* We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
(** しかし証明はここで手詰まりになってしまいます。なぜなら、[destruct]を使ったことで、コンテキストからゴールまでたどりつくのに必要な情報がなくなってしまったからです。
[destruct]は[beq_nat n 3]の結果起こる事象を全て投げ捨ててしまいますが、我々はそのうち少なくとも一つは残してもらわないと証明が進みません。このケースで必要なのは[beq_nat n 3 = true]で、ここから[n = 3]は明らかで、ここから[n]が奇数であることが導かれます。
実際のところやりたいことは[destruct]を[beq_nat n 3]に直接使ってこの式の結果起こることを全て置き換えてしまうことではなく、置き換えと同時にコンテキストに我々が今いるケースと等しいこと示す等式のレコードを追加してくれることです。
[eqn:]という限定子があれば、そのような等式を導入することが出来ます。(名前は何でもいいんですが)
*)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* ここで、コンテキストに新しい変数[e3]と、[e3 = beq_nat n 3]という仮定が追加されます。こうしてから[destruct e3]とすると... *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* 推論している関数本体の2番目のケースに来た時、[eqn:]をもう一度同様に使用して、証明を終らせることが出来ます。*)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** 練習問題: ★★ (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★ (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(* * Review *)
(** * まとめ *)
(* We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(** ここまでに、たくさんの基本的なタクティックを見てきました。これだけあればしばらくの間は困らずに済むはずです。この先数回のレクチャーで2～3新しいものが出てきますが、その先ではさらに強力な「自動化されたタクティック」を紹介していきます。それを使うと、多くの低レベルな作業をCoqに処理してもらうことができます。しかし基本的に、皆さんはもう必要なことを知っていると考えていいでしょう。
ここまでに出てきたタクティックの一覧です
- [intros]:
仮定や変数をゴールからコンテキストに移す
- [reflexivity]:
証明を完了させる（ゴールが[e = e]という形になっている場合）
- [apply]:
仮定、補助定理、コンストラクタを使ってゴールを証明する
- [apply... in H]:
仮定、補助定理、コンストラクタを使ってゴールを証明する（前向きの証明）
- [apply... with...]:
パターンマッチだけで決定できなかった変数を、特定の値に明示的に結びつける
- [simpl]:
ゴールの式を簡約する
- [simpl in H]:
ゴール、もしくは仮定Hの式を簡約する
- [rewrite]:
等式の形をした仮定（もしくは定理）を使い、ゴールを書き換える
- [rewrite ... in H]:
等式の形をした仮定（もしくは定理）を使い、ゴールや仮定を書き換える
- [unfold]:
定義された定数を、ゴールの右側の式で置き換える
- [unfold... in H]:
定義された定数を、ゴールや仮定の右側の式で置き換える
- [destruct... as...]:
帰納的に定義された型の値について、ケースごとに解析する
- [destruct... eqn:...]:
等式に名前を導入して、コンテキストに追加する。ケースごとの分析結果を記録する。
- [induction... as...]:
機能的に定義された型の値に帰納法を適用する
- [inversion]:
コンストラクタの単射性と独立性を利用して証明を行う
- [assert (e) as H]:
定義した補助定理(e)をHという名前でコンテキストに導入する
- [generalize dependent x]:
変数[x](とそれに依存する全て)をコンテキストからゴールの式中の明示的な仮説に戻す。
*)
(* ###################################################### *)
(* * Additional Exercises *)
(** * さらなる練習問題 *)
(** **** 練習問題: ★★★ (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★, advanced, optional (beq_nat_sym_informal) *)
(* この補題のあなたの形式的な証明に対応する非形式的な証明を与えなさい:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** 練習問題: ★★★, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★, advanced (split_combine) *)
(* We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
(* 思考練習: 我々はすでに、全ての型のリストのペアでcombineがsplitの逆関数であることを証明しました。ではその逆の「splitはcombineの逆関数である」を示すことはできるでしょうか？
下記の[split]が[combine]の逆関数であることを述べる[split_combine_statement]の定義を完成させなさい。それから、その性質が正しいことを証明しなさい。（なるべくintrosを使うタイミングを遅らせ、帰納法の仮定を一般化させておくといいでしょう。 )
ヒント: split combine l1 l2 = (l1,l2)がtrueとなるl1、l2の条件は何でしょう？ *)
Definition split_combine_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem split_combine : split_combine_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★ (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★, advanced (filter_exercise) *)
(* This one is a bit challenging. Pay attention to the form of your IH. *)
(** この問題は少し難しいかもしれません。上に上げる仮説の形に注意してください。*)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** 練習問題: ★★★★, advanced (forall_exists_challenge) *)
(** 二つの再帰関数[forallb]、[existsb]を定義しなさい。[forallb]は、リストの全ての要素が与えられた条件を満たしているかどうかを返します。:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
二つめのexistsbは、リストのなかに与えられた述語を満たす要素が一つ以上あるかどうかをチェックします。:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
次に[existsb']を再帰関数としてではなく、[forallb]と[negb]を使って定義しなさい。.
そして、[existsb']と[existsb]が同じ振る舞いをすることを証明しなさい。
*)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 16:01:37 -0500 (Wed, 31 Dec 2014) $ *)
|
// TOOL: vlog2tf
// DATE: Wed May 28 10:38:34 2014
// TITLE: Lattice Semiconductor Corporation
// MODULE: Section5_Top
// DESIGN: Section5_Top
// FILENAME: Section5_Top_tf.v
// PROJECT: Unknown
// VERSION: 2.0
// This file is auto generated by the Diamond
`timescale 1 ms / 1 ms
// Define Module for Test Fixture
module Section5_Top_tf();
// Inputs
reg DigitalLDir;
reg DigitalRDir;
reg reset_n;
// Outputs
wire [3:0] outputs;
// Bidirs
// Instantiate the UUT
// Please check and add your parameters manually
Section5_Top UUT (
.DigitalLDir(DigitalLDir),
.DigitalRDir(DigitalRDir),
.reset_n(reset_n),
.outputs(outputs)
);
// Initialize Inputs
// You can add your stimulus here
initial begin
DigitalLDir = 1; DigitalRDir = 1; reset_n = 1;
#1 DigitalLDir = 1; DigitalRDir = 1; reset_n = 0;
#1 DigitalLDir = 1; DigitalRDir = 1; reset_n = 1;
#100 DigitalLDir = 1; DigitalRDir = 0; reset_n = 1;
#500 DigitalLDir = 1; DigitalRDir = 1; reset_n = 1;
end
endmodule // Section5_Top_tf |
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : alu_puf
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// This is an ALU based PUF. Implements two adders that operate on the same operands
// concurrently and produce results. The result signals are passed through pdl_puf
// for tuning assymetric routing delay using pdls and responses are computed based on
// which signal is faster for each bit of response.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module AluPuf(CHALLENGE, RESPONSE, trigger, reset, a, b);
output [15:0] RESPONSE;
input [127:0] CHALLENGE;
input trigger;
input reset;
input wire [15:0] a;
input wire [15:0] b;
wire [127:0] CHALLENGE;
wire [15:0] RESPONSE;
(* KEEP = "TRUE" *)
reg [15:0] a1;
reg [15:0] a2;
reg [15:0] b1;
reg [15:0] b2;
wire [15:0] c1;
wire [15:0] c2;
always @ (posedge trigger) begin
a1 <= a;
a2 <= a;
b1 <= b;
b2 <= b;
end
(* KEEP="TRUE" *)
assign c1 = (trigger==1)?(a1+b1):0;
assign c2 = (trigger==1)?(a2+b2):0;
(* KEEP_HIERARCHY="TRUE" *)
pdl_puf puf1 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[0]), .s2(c2[0]), .reset(reset), .o(RESPONSE[0]));
pdl_puf puf2 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[1]), .s2(c2[1]), .reset(reset), .o(RESPONSE[1]));
pdl_puf puf3 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[2]), .s2(c2[2]), .reset(reset), .o(RESPONSE[2]));
pdl_puf puf4 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[3]), .s2(c2[3]), .reset(reset), .o(RESPONSE[3]));
pdl_puf puf5 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[4]), .s2(c2[4]), .reset(reset), .o(RESPONSE[4]));
pdl_puf puf6 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[5]), .s2(c2[5]), .reset(reset), .o(RESPONSE[5]));
pdl_puf puf7 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[6]), .s2(c2[6]), .reset(reset), .o(RESPONSE[6]));
pdl_puf puf8 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[7]), .s2(c2[7]), .reset(reset), .o(RESPONSE[7]));
pdl_puf puf9 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[8]), .s2(c2[8]), .reset(reset), .o(RESPONSE[8]));
pdl_puf puf10 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[9]), .s2(c2[9]), .reset(reset), .o(RESPONSE[9]));
pdl_puf puf11 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[10]), .s2(c2[10]), .reset(reset), .o(RESPONSE[10]));
pdl_puf puf12 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[11]), .s2(c2[11]), .reset(reset), .o(RESPONSE[11]));
pdl_puf puf13 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[12]), .s2(c2[12]), .reset(reset), .o(RESPONSE[12]));
pdl_puf puf14 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[13]), .s2(c2[13]), .reset(reset), .o(RESPONSE[13]));
pdl_puf puf15 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[14]), .s2(c2[14]), .reset(reset), .o(RESPONSE[14]));
pdl_puf puf16 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[15]), .s2(c2[15]), .reset(reset), .o(RESPONSE[15]));
endmodule
|
// Generator : SpinalHDL v1.4.0 git head : ecb5a80b713566f417ea3ea061f9969e73770a7f
// Date : 12/09/2020, 16:28:00
// Component : VexRiscv
`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
`define Src2CtrlEnum_defaultEncoding_type [1:0]
`define Src2CtrlEnum_defaultEncoding_RS 2'b00
`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
`define Src2CtrlEnum_defaultEncoding_PC 2'b11
`define ShiftCtrlEnum_defaultEncoding_type [1:0]
`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
`define Src1CtrlEnum_defaultEncoding_type [1:0]
`define Src1CtrlEnum_defaultEncoding_RS 2'b00
`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
`define BranchCtrlEnum_defaultEncoding_type [1:0]
`define BranchCtrlEnum_defaultEncoding_INC 2'b00
`define BranchCtrlEnum_defaultEncoding_B 2'b01
`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
`define AluCtrlEnum_defaultEncoding_type [1:0]
`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
`define EnvCtrlEnum_defaultEncoding_type [0:0]
`define EnvCtrlEnum_defaultEncoding_NONE 1'b0
`define EnvCtrlEnum_defaultEncoding_XRET 1'b1
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:0] io_occupancy,
input clk,
input reset
);
wire _zz_4_;
wire [0:0] _zz_5_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [32:0] _zz_2_;
reg [32:0] _zz_3_;
assign _zz_4_ = (! empty);
assign _zz_5_ = _zz_2_[0 : 0];
always @ (*) begin
_zz_1_ = 1'b0;
if(pushing)begin
_zz_1_ = 1'b1;
end
end
always @ (*) begin
pushPtr_willIncrement = 1'b0;
if(pushing)begin
pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
pushPtr_willClear = 1'b0;
if(io_flush)begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = 1'b1;
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @ (*) begin
popPtr_willIncrement = 1'b0;
if(popping)begin
popPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
popPtr_willClear = 1'b0;
if(io_flush)begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = 1'b1;
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
assign ptrMatch = 1'b1;
assign empty = (ptrMatch && (! risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (! full);
always @ (*) begin
if(_zz_4_)begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign _zz_2_ = _zz_3_;
always @ (*) begin
if(_zz_4_)begin
io_pop_payload_error = _zz_5_[0];
end else begin
io_pop_payload_error = io_push_payload_error;
end
end
always @ (*) begin
if(_zz_4_)begin
io_pop_payload_inst = _zz_2_[32 : 1];
end else begin
io_pop_payload_inst = io_push_payload_inst;
end
end
assign io_occupancy = (risingOccupancy && ptrMatch);
always @ (posedge clk or posedge reset) begin
if (reset) begin
risingOccupancy <= 1'b0;
end else begin
if((pushing != popping))begin
risingOccupancy <= pushing;
end
if(io_flush)begin
risingOccupancy <= 1'b0;
end
end
end
always @ (posedge clk) begin
if(_zz_1_)begin
_zz_3_ <= {io_push_payload_inst,io_push_payload_error};
end
end
endmodule
module VexRiscv (
output iBus_cmd_valid,
input iBus_cmd_ready,
output [31:0] iBus_cmd_payload_pc,
input iBus_rsp_valid,
input iBus_rsp_payload_error,
input [31:0] iBus_rsp_payload_inst,
input timerInterrupt,
input externalInterrupt,
input softwareInterrupt,
output dBus_cmd_valid,
input dBus_cmd_ready,
output dBus_cmd_payload_wr,
output [31:0] dBus_cmd_payload_address,
output [31:0] dBus_cmd_payload_data,
output [1:0] dBus_cmd_payload_size,
input dBus_rsp_ready,
input dBus_rsp_error,
input [31:0] dBus_rsp_data,
input clk,
input reset
);
wire _zz_159_;
wire _zz_160_;
reg [31:0] _zz_161_;
reg [31:0] _zz_162_;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;
wire _zz_163_;
wire _zz_164_;
wire _zz_165_;
wire _zz_166_;
wire _zz_167_;
wire _zz_168_;
wire _zz_169_;
wire _zz_170_;
wire _zz_171_;
wire _zz_172_;
wire [1:0] _zz_173_;
wire _zz_174_;
wire _zz_175_;
wire _zz_176_;
wire _zz_177_;
wire _zz_178_;
wire _zz_179_;
wire _zz_180_;
wire _zz_181_;
wire _zz_182_;
wire _zz_183_;
wire _zz_184_;
wire _zz_185_;
wire _zz_186_;
wire _zz_187_;
wire [4:0] _zz_188_;
wire [1:0] _zz_189_;
wire [1:0] _zz_190_;
wire [1:0] _zz_191_;
wire _zz_192_;
wire [0:0] _zz_193_;
wire [2:0] _zz_194_;
wire [31:0] _zz_195_;
wire [0:0] _zz_196_;
wire [0:0] _zz_197_;
wire [0:0] _zz_198_;
wire [0:0] _zz_199_;
wire [0:0] _zz_200_;
wire [0:0] _zz_201_;
wire [0:0] _zz_202_;
wire [0:0] _zz_203_;
wire [0:0] _zz_204_;
wire [0:0] _zz_205_;
wire [0:0] _zz_206_;
wire [32:0] _zz_207_;
wire [31:0] _zz_208_;
wire [32:0] _zz_209_;
wire [0:0] _zz_210_;
wire [0:0] _zz_211_;
wire [0:0] _zz_212_;
wire [1:0] _zz_213_;
wire [1:0] _zz_214_;
wire [2:0] _zz_215_;
wire [31:0] _zz_216_;
wire [2:0] _zz_217_;
wire [31:0] _zz_218_;
wire [31:0] _zz_219_;
wire [11:0] _zz_220_;
wire [11:0] _zz_221_;
wire [2:0] _zz_222_;
wire [0:0] _zz_223_;
wire [2:0] _zz_224_;
wire [0:0] _zz_225_;
wire [2:0] _zz_226_;
wire [0:0] _zz_227_;
wire [2:0] _zz_228_;
wire [0:0] _zz_229_;
wire [2:0] _zz_230_;
wire [4:0] _zz_231_;
wire [11:0] _zz_232_;
wire [11:0] _zz_233_;
wire [31:0] _zz_234_;
wire [31:0] _zz_235_;
wire [31:0] _zz_236_;
wire [31:0] _zz_237_;
wire [31:0] _zz_238_;
wire [31:0] _zz_239_;
wire [31:0] _zz_240_;
wire [0:0] _zz_241_;
wire [4:0] _zz_242_;
wire [34:0] _zz_243_;
wire [34:0] _zz_244_;
wire [32:0] _zz_245_;
wire [34:0] _zz_246_;
wire [33:0] _zz_247_;
wire [34:0] _zz_248_;
wire [33:0] _zz_249_;
wire [32:0] _zz_250_;
wire [34:0] _zz_251_;
wire [32:0] _zz_252_;
wire [0:0] _zz_253_;
wire [4:0] _zz_254_;
wire [32:0] _zz_255_;
wire [31:0] _zz_256_;
wire [31:0] _zz_257_;
wire [32:0] _zz_258_;
wire [32:0] _zz_259_;
wire [31:0] _zz_260_;
wire [31:0] _zz_261_;
wire [32:0] _zz_262_;
wire [32:0] _zz_263_;
wire [32:0] _zz_264_;
wire [32:0] _zz_265_;
wire [0:0] _zz_266_;
wire [32:0] _zz_267_;
wire [0:0] _zz_268_;
wire [32:0] _zz_269_;
wire [0:0] _zz_270_;
wire [31:0] _zz_271_;
wire [19:0] _zz_272_;
wire [11:0] _zz_273_;
wire [11:0] _zz_274_;
wire [0:0] _zz_275_;
wire [0:0] _zz_276_;
wire [0:0] _zz_277_;
wire [0:0] _zz_278_;
wire [0:0] _zz_279_;
wire [0:0] _zz_280_;
wire _zz_281_;
wire _zz_282_;
wire _zz_283_;
wire _zz_284_;
wire [6:0] _zz_285_;
wire [4:0] _zz_286_;
wire _zz_287_;
wire [4:0] _zz_288_;
wire [31:0] _zz_289_;
wire [31:0] _zz_290_;
wire _zz_291_;
wire [0:0] _zz_292_;
wire [0:0] _zz_293_;
wire _zz_294_;
wire [0:0] _zz_295_;
wire [0:0] _zz_296_;
wire [1:0] _zz_297_;
wire [1:0] _zz_298_;
wire _zz_299_;
wire [0:0] _zz_300_;
wire [22:0] _zz_301_;
wire [31:0] _zz_302_;
wire [31:0] _zz_303_;
wire [31:0] _zz_304_;
wire [31:0] _zz_305_;
wire [31:0] _zz_306_;
wire [31:0] _zz_307_;
wire [31:0] _zz_308_;
wire [31:0] _zz_309_;
wire _zz_310_;
wire [0:0] _zz_311_;
wire [0:0] _zz_312_;
wire _zz_313_;
wire [0:0] _zz_314_;
wire [19:0] _zz_315_;
wire _zz_316_;
wire _zz_317_;
wire _zz_318_;
wire _zz_319_;
wire _zz_320_;
wire [0:0] _zz_321_;
wire [0:0] _zz_322_;
wire _zz_323_;
wire [0:0] _zz_324_;
wire [15:0] _zz_325_;
wire [31:0] _zz_326_;
wire [0:0] _zz_327_;
wire [3:0] _zz_328_;
wire [0:0] _zz_329_;
wire [0:0] _zz_330_;
wire [1:0] _zz_331_;
wire [1:0] _zz_332_;
wire _zz_333_;
wire [0:0] _zz_334_;
wire [12:0] _zz_335_;
wire [31:0] _zz_336_;
wire [31:0] _zz_337_;
wire [31:0] _zz_338_;
wire _zz_339_;
wire [0:0] _zz_340_;
wire [0:0] _zz_341_;
wire [31:0] _zz_342_;
wire [31:0] _zz_343_;
wire [31:0] _zz_344_;
wire [31:0] _zz_345_;
wire [31:0] _zz_346_;
wire [31:0] _zz_347_;
wire [0:0] _zz_348_;
wire [1:0] _zz_349_;
wire [1:0] _zz_350_;
wire [1:0] _zz_351_;
wire _zz_352_;
wire [0:0] _zz_353_;
wire [9:0] _zz_354_;
wire [31:0] _zz_355_;
wire [31:0] _zz_356_;
wire [31:0] _zz_357_;
wire [31:0] _zz_358_;
wire [31:0] _zz_359_;
wire [31:0] _zz_360_;
wire [31:0] _zz_361_;
wire _zz_362_;
wire _zz_363_;
wire _zz_364_;
wire [0:0] _zz_365_;
wire [0:0] _zz_366_;
wire [0:0] _zz_367_;
wire [0:0] _zz_368_;
wire _zz_369_;
wire [0:0] _zz_370_;
wire [7:0] _zz_371_;
wire [31:0] _zz_372_;
wire [31:0] _zz_373_;
wire _zz_374_;
wire _zz_375_;
wire [0:0] _zz_376_;
wire [1:0] _zz_377_;
wire [1:0] _zz_378_;
wire [1:0] _zz_379_;
wire _zz_380_;
wire [0:0] _zz_381_;
wire [4:0] _zz_382_;
wire [31:0] _zz_383_;
wire [31:0] _zz_384_;
wire [31:0] _zz_385_;
wire [31:0] _zz_386_;
wire [31:0] _zz_387_;
wire [31:0] _zz_388_;
wire [31:0] _zz_389_;
wire [31:0] _zz_390_;
wire [31:0] _zz_391_;
wire _zz_392_;
wire [2:0] _zz_393_;
wire [2:0] _zz_394_;
wire _zz_395_;
wire [0:0] _zz_396_;
wire [1:0] _zz_397_;
wire [31:0] _zz_398_;
wire _zz_399_;
wire _zz_400_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_1_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_2_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_3_;
wire decode_MEMORY_ENABLE;
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_4_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_5_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_6_;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_7_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_9_;
wire decode_IS_MUL;
wire decode_MEMORY_STORE;
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_10_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_11_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_12_;
wire decode_IS_CSR;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire decode_IS_RS1_SIGNED;
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_13_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_14_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_15_;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire [31:0] memory_PC;
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_16_;
wire `AluCtrlEnum_defaultEncoding_type _zz_17_;
wire `AluCtrlEnum_defaultEncoding_type _zz_18_;
wire decode_SRC2_FORCE_ZERO;
wire `EnvCtrlEnum_defaultEncoding_type _zz_19_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_20_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_21_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_22_;
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_23_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_24_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_25_;
wire decode_SRC_LESS_UNSIGNED;
wire decode_IS_RS2_SIGNED;
wire decode_IS_DIV;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_26_;
wire execute_IS_RS1_SIGNED;
wire [31:0] execute_RS1;
wire execute_IS_DIV;
wire execute_IS_MUL;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire memory_IS_MUL;
wire decode_RS2_USE;
wire decode_RS1_USE;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] execute_SHIFT_RIGHT;
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_27_;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_28_;
wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_29_;
wire execute_IS_RVC;
wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_30_;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_31_;
wire [31:0] execute_SRC2;
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_32_;
wire [31:0] _zz_33_;
wire [31:0] _zz_34_;
wire _zz_35_;
reg _zz_36_;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire `Src2CtrlEnum_defaultEncoding_type _zz_37_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_38_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_39_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_40_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_41_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_42_;
wire `AluCtrlEnum_defaultEncoding_type _zz_43_;
reg [31:0] _zz_44_;
wire [31:0] execute_SRC1;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_45_;
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_46_;
wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_47_;
reg [31:0] _zz_48_;
wire [31:0] memory_INSTRUCTION;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire [31:0] memory_MEMORY_READ_DATA;
wire memory_MEMORY_STORE;
wire memory_MEMORY_ENABLE;
wire [31:0] execute_SRC_ADD;
wire [31:0] execute_RS2;
wire [31:0] execute_INSTRUCTION;
wire execute_MEMORY_STORE;
wire execute_MEMORY_ENABLE;
wire execute_ALIGNEMENT_FAULT;
reg [31:0] _zz_49_;
wire [31:0] decode_PC;
wire [31:0] decode_INSTRUCTION;
wire decode_IS_RVC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
wire decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
wire decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
wire execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
wire writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusSimplePlugin_fetcherHalt;
reg IBusSimplePlugin_incomingInstruction;
wire IBusSimplePlugin_pcValids_0;
wire IBusSimplePlugin_pcValids_1;
wire IBusSimplePlugin_pcValids_2;
wire IBusSimplePlugin_pcValids_3;
wire CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
wire IBusSimplePlugin_externalFlush;
wire IBusSimplePlugin_jump_pcLoad_valid;
wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
wire [1:0] _zz_50_;
wire IBusSimplePlugin_fetchPc_output_valid;
wire IBusSimplePlugin_fetchPc_output_ready;
wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusSimplePlugin_fetchPc_correction;
reg IBusSimplePlugin_fetchPc_correctionReg;
wire IBusSimplePlugin_fetchPc_corrected;
reg IBusSimplePlugin_fetchPc_pcRegPropagate;
reg IBusSimplePlugin_fetchPc_booted;
reg IBusSimplePlugin_fetchPc_inc;
reg [31:0] IBusSimplePlugin_fetchPc_pc;
reg IBusSimplePlugin_fetchPc_flushed;
reg IBusSimplePlugin_decodePc_flushed;
reg [31:0] IBusSimplePlugin_decodePc_pcReg /* verilator public */ ;
wire [31:0] IBusSimplePlugin_decodePc_pcPlus;
wire IBusSimplePlugin_decodePc_injectedDecode;
wire IBusSimplePlugin_iBusRsp_redoFetch;
wire IBusSimplePlugin_iBusRsp_stages_0_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_0_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_0_halt;
wire IBusSimplePlugin_iBusRsp_stages_1_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_1_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload;
reg IBusSimplePlugin_iBusRsp_stages_1_halt;
wire IBusSimplePlugin_iBusRsp_stages_2_input_valid;
wire IBusSimplePlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_2_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_2_halt;
wire _zz_51_;
wire _zz_52_;
wire _zz_53_;
wire IBusSimplePlugin_iBusRsp_flush;
wire _zz_54_;
wire _zz_55_;
reg _zz_56_;
wire _zz_57_;
reg _zz_58_;
reg [31:0] _zz_59_;
reg IBusSimplePlugin_iBusRsp_readyForError;
wire IBusSimplePlugin_iBusRsp_output_valid;
wire IBusSimplePlugin_iBusRsp_output_ready;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc;
wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
wire IBusSimplePlugin_iBusRsp_output_payload_isRvc;
wire IBusSimplePlugin_decompressor_input_valid;
wire IBusSimplePlugin_decompressor_input_ready;
wire [31:0] IBusSimplePlugin_decompressor_input_payload_pc;
wire IBusSimplePlugin_decompressor_input_payload_rsp_error;
wire [31:0] IBusSimplePlugin_decompressor_input_payload_rsp_inst;
wire IBusSimplePlugin_decompressor_input_payload_isRvc;
wire IBusSimplePlugin_decompressor_output_valid;
wire IBusSimplePlugin_decompressor_output_ready;
wire [31:0] IBusSimplePlugin_decompressor_output_payload_pc;
wire IBusSimplePlugin_decompressor_output_payload_rsp_error;
wire [31:0] IBusSimplePlugin_decompressor_output_payload_rsp_inst;
wire IBusSimplePlugin_decompressor_output_payload_isRvc;
wire IBusSimplePlugin_decompressor_flushNext;
wire IBusSimplePlugin_decompressor_consumeCurrent;
reg IBusSimplePlugin_decompressor_bufferValid;
reg [15:0] IBusSimplePlugin_decompressor_bufferData;
wire IBusSimplePlugin_decompressor_isInputLowRvc;
wire IBusSimplePlugin_decompressor_isInputHighRvc;
reg IBusSimplePlugin_decompressor_throw2BytesReg;
wire IBusSimplePlugin_decompressor_throw2Bytes;
wire IBusSimplePlugin_decompressor_unaligned;
wire [31:0] IBusSimplePlugin_decompressor_raw;
wire IBusSimplePlugin_decompressor_isRvc;
wire [15:0] _zz_60_;
reg [31:0] IBusSimplePlugin_decompressor_decompressed;
wire [4:0] _zz_61_;
wire [4:0] _zz_62_;
wire [11:0] _zz_63_;
wire _zz_64_;
reg [11:0] _zz_65_;
wire _zz_66_;
reg [9:0] _zz_67_;
wire [20:0] _zz_68_;
wire _zz_69_;
reg [14:0] _zz_70_;
wire _zz_71_;
reg [2:0] _zz_72_;
wire _zz_73_;
reg [9:0] _zz_74_;
wire [20:0] _zz_75_;
wire _zz_76_;
reg [4:0] _zz_77_;
wire [12:0] _zz_78_;
wire [4:0] _zz_79_;
wire [4:0] _zz_80_;
wire [4:0] _zz_81_;
wire _zz_82_;
reg [2:0] _zz_83_;
reg [2:0] _zz_84_;
wire _zz_85_;
reg [6:0] _zz_86_;
wire IBusSimplePlugin_decompressor_bufferFill;
wire IBusSimplePlugin_injector_decodeInput_valid;
wire IBusSimplePlugin_injector_decodeInput_ready;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
wire IBusSimplePlugin_injector_decodeInput_payload_isRvc;
reg _zz_87_;
reg [31:0] _zz_88_;
reg _zz_89_;
reg [31:0] _zz_90_;
reg _zz_91_;
reg IBusSimplePlugin_injector_nextPcCalc_valids_0;
reg IBusSimplePlugin_injector_nextPcCalc_valids_1;
reg IBusSimplePlugin_injector_nextPcCalc_valids_2;
reg IBusSimplePlugin_injector_nextPcCalc_valids_3;
reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode;
wire IBusSimplePlugin_cmd_valid;
wire IBusSimplePlugin_cmd_ready;
wire [31:0] IBusSimplePlugin_cmd_payload_pc;
wire IBusSimplePlugin_pending_inc;
wire IBusSimplePlugin_pending_dec;
reg [2:0] IBusSimplePlugin_pending_value;
wire [2:0] IBusSimplePlugin_pending_next;
wire IBusSimplePlugin_cmdFork_canEmit;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst;
reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter;
wire IBusSimplePlugin_rspJoin_rspBuffer_flush;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc;
reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
wire IBusSimplePlugin_rspJoin_join_valid;
wire IBusSimplePlugin_rspJoin_join_ready;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc;
wire IBusSimplePlugin_rspJoin_join_payload_rsp_error;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
wire IBusSimplePlugin_rspJoin_join_payload_isRvc;
wire IBusSimplePlugin_rspJoin_exceptionDetected;
wire _zz_92_;
wire _zz_93_;
reg execute_DBusSimplePlugin_skipCmd;
reg [31:0] _zz_94_;
reg [3:0] _zz_95_;
wire [3:0] execute_DBusSimplePlugin_formalMask;
reg [31:0] memory_DBusSimplePlugin_rspShifted;
wire _zz_96_;
reg [31:0] _zz_97_;
wire _zz_98_;
reg [31:0] _zz_99_;
reg [31:0] memory_DBusSimplePlugin_rspFormated;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
wire [1:0] CsrPlugin_mtvec_mode;
wire [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_100_;
wire _zz_101_;
wire _zz_102_;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire CsrPlugin_exception;
wire CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
reg CsrPlugin_pipelineLiberator_done;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException;
wire [1:0] CsrPlugin_targetPrivilege;
wire [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
reg execute_CsrPlugin_wfiWake;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire [31:0] execute_CsrPlugin_readData;
wire execute_CsrPlugin_writeInstruction;
wire execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
reg [31:0] execute_CsrPlugin_writeData;
wire [11:0] execute_CsrPlugin_csrAddress;
wire [28:0] _zz_103_;
wire _zz_104_;
wire _zz_105_;
wire _zz_106_;
wire _zz_107_;
wire _zz_108_;
wire _zz_109_;
wire _zz_110_;
wire `AluCtrlEnum_defaultEncoding_type _zz_111_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_112_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_113_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_114_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_115_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_116_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_117_;
wire [3:0] decode_RegFilePlugin_regFileReadAddress1;
wire [3:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
wire [3:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_118_;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_119_;
reg [31:0] _zz_120_;
wire _zz_121_;
reg [19:0] _zz_122_;
wire _zz_123_;
reg [19:0] _zz_124_;
reg [31:0] _zz_125_;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_126_;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_127_;
reg _zz_128_;
reg _zz_129_;
reg _zz_130_;
reg [4:0] _zz_131_;
reg [31:0] _zz_132_;
wire _zz_133_;
wire _zz_134_;
wire _zz_135_;
wire _zz_136_;
wire _zz_137_;
wire _zz_138_;
reg [32:0] memory_MulDivIterativePlugin_rs1;
reg [31:0] memory_MulDivIterativePlugin_rs2;
reg [64:0] memory_MulDivIterativePlugin_accumulator;
wire memory_MulDivIterativePlugin_frontendOk;
reg memory_MulDivIterativePlugin_mul_counter_willIncrement;
reg memory_MulDivIterativePlugin_mul_counter_willClear;
reg [4:0] memory_MulDivIterativePlugin_mul_counter_valueNext;
reg [4:0] memory_MulDivIterativePlugin_mul_counter_value;
wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc;
wire memory_MulDivIterativePlugin_mul_counter_willOverflow;
reg memory_MulDivIterativePlugin_div_needRevert;
reg memory_MulDivIterativePlugin_div_counter_willIncrement;
reg memory_MulDivIterativePlugin_div_counter_willClear;
reg [4:0] memory_MulDivIterativePlugin_div_counter_valueNext;
reg [4:0] memory_MulDivIterativePlugin_div_counter_value;
wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc;
wire memory_MulDivIterativePlugin_div_counter_willOverflow;
reg memory_MulDivIterativePlugin_div_done;
reg [31:0] memory_MulDivIterativePlugin_div_result;
wire [31:0] _zz_139_;
wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted;
wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder;
wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator;
wire [32:0] memory_MulDivIterativePlugin_div_stage_1_remainderShifted;
wire [32:0] memory_MulDivIterativePlugin_div_stage_1_remainderMinusDenominator;
wire [31:0] memory_MulDivIterativePlugin_div_stage_1_outRemainder;
wire [31:0] memory_MulDivIterativePlugin_div_stage_1_outNumerator;
wire [31:0] _zz_140_;
wire _zz_141_;
wire _zz_142_;
reg [32:0] _zz_143_;
wire execute_BranchPlugin_eq;
wire [2:0] _zz_144_;
reg _zz_145_;
reg _zz_146_;
wire [31:0] execute_BranchPlugin_branch_src1;
wire _zz_147_;
reg [10:0] _zz_148_;
wire _zz_149_;
reg [19:0] _zz_150_;
wire _zz_151_;
reg [18:0] _zz_152_;
reg [31:0] _zz_153_;
wire [31:0] execute_BranchPlugin_branch_src2;
wire [31:0] execute_BranchPlugin_branchAdder;
reg [31:0] decode_to_execute_RS1;
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
reg decode_to_execute_IS_DIV;
reg execute_to_memory_IS_DIV;
reg decode_to_execute_IS_RVC;
reg decode_to_execute_IS_RS2_SIGNED;
reg decode_to_execute_SRC_USE_SUB_LESS;
reg decode_to_execute_SRC_LESS_UNSIGNED;
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
reg decode_to_execute_SRC2_FORCE_ZERO;
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
reg decode_to_execute_REGFILE_WRITE_VALID;
reg execute_to_memory_REGFILE_WRITE_VALID;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_to_execute_PC;
reg [31:0] execute_to_memory_PC;
reg [31:0] memory_to_writeBack_PC;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
reg decode_to_execute_IS_RS1_SIGNED;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
reg decode_to_execute_IS_CSR;
reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
reg decode_to_execute_MEMORY_STORE;
reg execute_to_memory_MEMORY_STORE;
reg [31:0] decode_to_execute_INSTRUCTION;
reg [31:0] execute_to_memory_INSTRUCTION;
reg [31:0] memory_to_writeBack_INSTRUCTION;
reg decode_to_execute_IS_MUL;
reg execute_to_memory_IS_MUL;
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
reg decode_to_execute_CSR_WRITE_OPCODE;
reg decode_to_execute_CSR_READ_OPCODE;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
reg decode_to_execute_MEMORY_ENABLE;
reg execute_to_memory_MEMORY_ENABLE;
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
reg [31:0] decode_to_execute_RS2;
reg execute_CsrPlugin_csr_768;
reg execute_CsrPlugin_csr_836;
reg execute_CsrPlugin_csr_772;
reg execute_CsrPlugin_csr_832;
reg execute_CsrPlugin_csr_834;
reg [31:0] _zz_154_;
reg [31:0] _zz_155_;
reg [31:0] _zz_156_;
reg [31:0] _zz_157_;
reg [31:0] _zz_158_;
`ifndef SYNTHESIS
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_1__string;
reg [39:0] _zz_2__string;
reg [39:0] _zz_3__string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_4__string;
reg [23:0] _zz_5__string;
reg [23:0] _zz_6__string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_7__string;
reg [71:0] _zz_8__string;
reg [71:0] _zz_9__string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_10__string;
reg [95:0] _zz_11__string;
reg [95:0] _zz_12__string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_13__string;
reg [31:0] _zz_14__string;
reg [31:0] _zz_15__string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_16__string;
reg [63:0] _zz_17__string;
reg [63:0] _zz_18__string;
reg [31:0] _zz_19__string;
reg [31:0] _zz_20__string;
reg [31:0] _zz_21__string;
reg [31:0] _zz_22__string;
reg [31:0] decode_ENV_CTRL_string;
reg [31:0] _zz_23__string;
reg [31:0] _zz_24__string;
reg [31:0] _zz_25__string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_26__string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_27__string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_29__string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_30__string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_31__string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_32__string;
reg [23:0] _zz_37__string;
reg [39:0] _zz_38__string;
reg [31:0] _zz_39__string;
reg [95:0] _zz_40__string;
reg [31:0] _zz_41__string;
reg [71:0] _zz_42__string;
reg [63:0] _zz_43__string;
reg [31:0] memory_ENV_CTRL_string;
reg [31:0] _zz_45__string;
reg [31:0] execute_ENV_CTRL_string;
reg [31:0] _zz_46__string;
reg [31:0] writeBack_ENV_CTRL_string;
reg [31:0] _zz_47__string;
reg [63:0] _zz_111__string;
reg [71:0] _zz_112__string;
reg [31:0] _zz_113__string;
reg [95:0] _zz_114__string;
reg [31:0] _zz_115__string;
reg [39:0] _zz_116__string;
reg [23:0] _zz_117__string;
reg [31:0] decode_to_execute_ENV_CTRL_string;
reg [31:0] execute_to_memory_ENV_CTRL_string;
reg [31:0] memory_to_writeBack_ENV_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
`endif
reg [31:0] RegFilePlugin_regFile [0:15] /* verilator public */ ;
assign _zz_163_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign _zz_164_ = 1'b1;
assign _zz_165_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign _zz_166_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign _zz_167_ = (execute_arbitration_isValid && execute_IS_CSR);
assign _zz_168_ = (memory_arbitration_isValid && memory_IS_MUL);
assign _zz_169_ = (memory_arbitration_isValid && memory_IS_DIV);
assign _zz_170_ = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc));
assign _zz_171_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign _zz_172_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
assign _zz_173_ = writeBack_INSTRUCTION[29 : 28];
assign _zz_174_ = (IBusSimplePlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt));
assign _zz_175_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign _zz_176_ = (1'b0 || (! 1'b1));
assign _zz_177_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign _zz_178_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign _zz_179_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign _zz_180_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign _zz_181_ = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done));
assign _zz_182_ = (! memory_arbitration_isStuck);
assign _zz_183_ = (IBusSimplePlugin_decompressor_output_ready && IBusSimplePlugin_decompressor_input_valid);
assign _zz_184_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11)));
assign _zz_185_ = ((_zz_100_ && 1'b1) && (! 1'b0));
assign _zz_186_ = ((_zz_101_ && 1'b1) && (! 1'b0));
assign _zz_187_ = ((_zz_102_ && 1'b1) && (! 1'b0));
assign _zz_188_ = {_zz_60_[1 : 0],_zz_60_[15 : 13]};
assign _zz_189_ = _zz_60_[6 : 5];
assign _zz_190_ = _zz_60_[11 : 10];
assign _zz_191_ = memory_INSTRUCTION[13 : 12];
assign _zz_192_ = execute_INSTRUCTION[13];
assign _zz_193_ = _zz_103_[18 : 18];
assign _zz_194_ = (decode_IS_RVC ? (3'b010) : (3'b100));
assign _zz_195_ = {29'd0, _zz_194_};
assign _zz_196_ = _zz_103_[1 : 1];
assign _zz_197_ = _zz_103_[19 : 19];
assign _zz_198_ = _zz_103_[25 : 25];
assign _zz_199_ = _zz_103_[21 : 21];
assign _zz_200_ = _zz_103_[4 : 4];
assign _zz_201_ = _zz_103_[5 : 5];
assign _zz_202_ = _zz_103_[16 : 16];
assign _zz_203_ = _zz_103_[6 : 6];
assign _zz_204_ = _zz_103_[0 : 0];
assign _zz_205_ = _zz_103_[7 : 7];
assign _zz_206_ = _zz_103_[28 : 28];
assign _zz_207_ = ($signed(_zz_209_) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_208_ = _zz_207_[31 : 0];
assign _zz_209_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz_210_ = _zz_103_[13 : 13];
assign _zz_211_ = _zz_103_[24 : 24];
assign _zz_212_ = _zz_103_[17 : 17];
assign _zz_213_ = (_zz_50_ & (~ _zz_214_));
assign _zz_214_ = (_zz_50_ - (2'b01));
assign _zz_215_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)};
assign _zz_216_ = {29'd0, _zz_215_};
assign _zz_217_ = (decode_IS_RVC ? (3'b010) : (3'b100));
assign _zz_218_ = {29'd0, _zz_217_};
assign _zz_219_ = {{_zz_70_,_zz_60_[6 : 2]},12'h0};
assign _zz_220_ = {{{(4'b0000),_zz_60_[8 : 7]},_zz_60_[12 : 9]},(2'b00)};
assign _zz_221_ = {{{(4'b0000),_zz_60_[8 : 7]},_zz_60_[12 : 9]},(2'b00)};
assign _zz_222_ = (IBusSimplePlugin_pending_value + _zz_224_);
assign _zz_223_ = IBusSimplePlugin_pending_inc;
assign _zz_224_ = {2'd0, _zz_223_};
assign _zz_225_ = IBusSimplePlugin_pending_dec;
assign _zz_226_ = {2'd0, _zz_225_};
assign _zz_227_ = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != (3'b000)));
assign _zz_228_ = {2'd0, _zz_227_};
assign _zz_229_ = execute_SRC_LESS;
assign _zz_230_ = (execute_IS_RVC ? (3'b010) : (3'b100));
assign _zz_231_ = execute_INSTRUCTION[19 : 15];
assign _zz_232_ = execute_INSTRUCTION[31 : 20];
assign _zz_233_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_234_ = ($signed(_zz_235_) + $signed(_zz_238_));
assign _zz_235_ = ($signed(_zz_236_) + $signed(_zz_237_));
assign _zz_236_ = execute_SRC1;
assign _zz_237_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_238_ = (execute_SRC_USE_SUB_LESS ? _zz_239_ : _zz_240_);
assign _zz_239_ = 32'h00000001;
assign _zz_240_ = 32'h0;
assign _zz_241_ = memory_MulDivIterativePlugin_mul_counter_willIncrement;
assign _zz_242_ = {4'd0, _zz_241_};
assign _zz_243_ = (_zz_244_ + _zz_251_);
assign _zz_244_ = (_zz_246_ + _zz_248_);
assign _zz_245_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0);
assign _zz_246_ = {{2{_zz_245_[32]}}, _zz_245_};
assign _zz_247_ = (memory_MulDivIterativePlugin_rs2[1] ? _zz_249_ : 34'h0);
assign _zz_248_ = {{1{_zz_247_[33]}}, _zz_247_};
assign _zz_249_ = ({1'd0,memory_MulDivIterativePlugin_rs1} <<< 1);
assign _zz_250_ = _zz_252_;
assign _zz_251_ = {{2{_zz_250_[32]}}, _zz_250_};
assign _zz_252_ = (memory_MulDivIterativePlugin_accumulator >>> 32);
assign _zz_253_ = memory_MulDivIterativePlugin_div_counter_willIncrement;
assign _zz_254_ = {4'd0, _zz_253_};
assign _zz_255_ = {1'd0, memory_MulDivIterativePlugin_rs2};
assign _zz_256_ = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_257_ = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0];
assign _zz_258_ = {_zz_139_,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_259_ = {1'd0, memory_MulDivIterativePlugin_rs2};
assign _zz_260_ = memory_MulDivIterativePlugin_div_stage_1_remainderMinusDenominator[31:0];
assign _zz_261_ = memory_MulDivIterativePlugin_div_stage_1_remainderShifted[31:0];
assign _zz_262_ = {memory_MulDivIterativePlugin_div_stage_0_outNumerator,(! memory_MulDivIterativePlugin_div_stage_1_remainderMinusDenominator[32])};
assign _zz_263_ = _zz_264_;
assign _zz_264_ = _zz_265_;
assign _zz_265_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_140_) : _zz_140_)} + _zz_267_);
assign _zz_266_ = memory_MulDivIterativePlugin_div_needRevert;
assign _zz_267_ = {32'd0, _zz_266_};
assign _zz_268_ = _zz_142_;
assign _zz_269_ = {32'd0, _zz_268_};
assign _zz_270_ = _zz_141_;
assign _zz_271_ = {31'd0, _zz_270_};
assign _zz_272_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_273_ = execute_INSTRUCTION[31 : 20];
assign _zz_274_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_275_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_276_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_277_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_278_ = execute_CsrPlugin_writeData[11 : 11];
assign _zz_279_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_280_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_281_ = 1'b1;
assign _zz_282_ = 1'b1;
assign _zz_283_ = (_zz_60_[11 : 10] == (2'b01));
assign _zz_284_ = ((_zz_60_[11 : 10] == (2'b11)) && (_zz_60_[6 : 5] == (2'b00)));
assign _zz_285_ = 7'h0;
assign _zz_286_ = _zz_60_[6 : 2];
assign _zz_287_ = _zz_60_[12];
assign _zz_288_ = _zz_60_[11 : 7];
assign _zz_289_ = (decode_INSTRUCTION & 32'h00000044);
assign _zz_290_ = 32'h0;
assign _zz_291_ = ((decode_INSTRUCTION & 32'h00000018) == 32'h0);
assign _zz_292_ = _zz_104_;
assign _zz_293_ = ((decode_INSTRUCTION & _zz_302_) == 32'h00001000);
assign _zz_294_ = ((decode_INSTRUCTION & 32'h00000070) == 32'h00000020);
assign _zz_295_ = _zz_110_;
assign _zz_296_ = ((decode_INSTRUCTION & _zz_303_) == 32'h0);
assign _zz_297_ = {(_zz_304_ == _zz_305_),(_zz_306_ == _zz_307_)};
assign _zz_298_ = (2'b00);
assign _zz_299_ = ((_zz_308_ == _zz_309_) != (1'b0));
assign _zz_300_ = (_zz_310_ != (1'b0));
assign _zz_301_ = {(_zz_311_ != _zz_312_),{_zz_313_,{_zz_314_,_zz_315_}}};
assign _zz_302_ = 32'h00005004;
assign _zz_303_ = 32'h00000020;
assign _zz_304_ = (decode_INSTRUCTION & 32'h00001050);
assign _zz_305_ = 32'h00001050;
assign _zz_306_ = (decode_INSTRUCTION & 32'h00002050);
assign _zz_307_ = 32'h00002050;
assign _zz_308_ = (decode_INSTRUCTION & 32'h00000064);
assign _zz_309_ = 32'h00000024;
assign _zz_310_ = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000);
assign _zz_311_ = _zz_106_;
assign _zz_312_ = (1'b0);
assign _zz_313_ = ({_zz_110_,{_zz_316_,_zz_317_}} != (3'b000));
assign _zz_314_ = ({_zz_318_,_zz_319_} != (2'b00));
assign _zz_315_ = {(_zz_320_ != (1'b0)),{(_zz_321_ != _zz_322_),{_zz_323_,{_zz_324_,_zz_325_}}}};
assign _zz_316_ = ((decode_INSTRUCTION & 32'h00000030) == 32'h00000010);
assign _zz_317_ = ((decode_INSTRUCTION & 32'h02000060) == 32'h00000020);
assign _zz_318_ = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040);
assign _zz_319_ = ((decode_INSTRUCTION & 32'h00003040) == 32'h00000040);
assign _zz_320_ = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020);
assign _zz_321_ = ((decode_INSTRUCTION & _zz_326_) == 32'h0);
assign _zz_322_ = (1'b0);
assign _zz_323_ = ({_zz_109_,{_zz_327_,_zz_328_}} != 6'h0);
assign _zz_324_ = ({_zz_329_,_zz_330_} != (2'b00));
assign _zz_325_ = {(_zz_331_ != _zz_332_),{_zz_333_,{_zz_334_,_zz_335_}}};
assign _zz_326_ = 32'h00000058;
assign _zz_327_ = ((decode_INSTRUCTION & _zz_336_) == 32'h00001010);
assign _zz_328_ = {(_zz_337_ == _zz_338_),{_zz_339_,{_zz_340_,_zz_341_}}};
assign _zz_329_ = ((decode_INSTRUCTION & _zz_342_) == 32'h00002000);
assign _zz_330_ = ((decode_INSTRUCTION & _zz_343_) == 32'h00001000);
assign _zz_331_ = {_zz_109_,(_zz_344_ == _zz_345_)};
assign _zz_332_ = (2'b00);
assign _zz_333_ = ((_zz_346_ == _zz_347_) != (1'b0));
assign _zz_334_ = ({_zz_348_,_zz_349_} != (3'b000));
assign _zz_335_ = {(_zz_350_ != _zz_351_),{_zz_352_,{_zz_353_,_zz_354_}}};
assign _zz_336_ = 32'h00001010;
assign _zz_337_ = (decode_INSTRUCTION & 32'h00002010);
assign _zz_338_ = 32'h00002010;
assign _zz_339_ = ((decode_INSTRUCTION & _zz_355_) == 32'h00000010);
assign _zz_340_ = (_zz_356_ == _zz_357_);
assign _zz_341_ = (_zz_358_ == _zz_359_);
assign _zz_342_ = 32'h00002010;
assign _zz_343_ = 32'h00005000;
assign _zz_344_ = (decode_INSTRUCTION & 32'h0000001c);
assign _zz_345_ = 32'h00000004;
assign _zz_346_ = (decode_INSTRUCTION & 32'h00000058);
assign _zz_347_ = 32'h00000040;
assign _zz_348_ = (_zz_360_ == _zz_361_);
assign _zz_349_ = {_zz_362_,_zz_363_};
assign _zz_350_ = {_zz_364_,_zz_108_};
assign _zz_351_ = (2'b00);
assign _zz_352_ = ({_zz_365_,_zz_366_} != (2'b00));
assign _zz_353_ = (_zz_367_ != _zz_368_);
assign _zz_354_ = {_zz_369_,{_zz_370_,_zz_371_}};
assign _zz_355_ = 32'h00000050;
assign _zz_356_ = (decode_INSTRUCTION & 32'h0000000c);
assign _zz_357_ = 32'h00000004;
assign _zz_358_ = (decode_INSTRUCTION & 32'h00000028);
assign _zz_359_ = 32'h0;
assign _zz_360_ = (decode_INSTRUCTION & 32'h00000044);
assign _zz_361_ = 32'h00000040;
assign _zz_362_ = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010);
assign _zz_363_ = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030);
assign _zz_364_ = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004);
assign _zz_365_ = ((decode_INSTRUCTION & _zz_372_) == 32'h00000004);
assign _zz_366_ = _zz_108_;
assign _zz_367_ = ((decode_INSTRUCTION & _zz_373_) == 32'h00000050);
assign _zz_368_ = (1'b0);
assign _zz_369_ = ({_zz_374_,_zz_375_} != (2'b00));
assign _zz_370_ = ({_zz_376_,_zz_377_} != (3'b000));
assign _zz_371_ = {(_zz_378_ != _zz_379_),{_zz_380_,{_zz_381_,_zz_382_}}};
assign _zz_372_ = 32'h00000044;
assign _zz_373_ = 32'h00003050;
assign _zz_374_ = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010);
assign _zz_375_ = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020);
assign _zz_376_ = ((decode_INSTRUCTION & _zz_383_) == 32'h40001010);
assign _zz_377_ = {(_zz_384_ == _zz_385_),(_zz_386_ == _zz_387_)};
assign _zz_378_ = {(_zz_388_ == _zz_389_),(_zz_390_ == _zz_391_)};
assign _zz_379_ = (2'b00);
assign _zz_380_ = ({_zz_107_,_zz_105_} != (2'b00));
assign _zz_381_ = (_zz_392_ != (1'b0));
assign _zz_382_ = {(_zz_393_ != _zz_394_),{_zz_395_,{_zz_396_,_zz_397_}}};
assign _zz_383_ = 32'h40003054;
assign _zz_384_ = (decode_INSTRUCTION & 32'h00007034);
assign _zz_385_ = 32'h00001010;
assign _zz_386_ = (decode_INSTRUCTION & 32'h02007054);
assign _zz_387_ = 32'h00001010;
assign _zz_388_ = (decode_INSTRUCTION & 32'h00000034);
assign _zz_389_ = 32'h00000020;
assign _zz_390_ = (decode_INSTRUCTION & 32'h00000064);
assign _zz_391_ = 32'h00000020;
assign _zz_392_ = ((decode_INSTRUCTION & 32'h0) == 32'h0);
assign _zz_393_ = {_zz_107_,{_zz_106_,_zz_105_}};
assign _zz_394_ = (3'b000);
assign _zz_395_ = (((decode_INSTRUCTION & _zz_398_) == 32'h00004000) != (1'b0));
assign _zz_396_ = (_zz_104_ != (1'b0));
assign _zz_397_ = {(_zz_399_ != (1'b0)),(_zz_400_ != (1'b0))};
assign _zz_398_ = 32'h00004004;
assign _zz_399_ = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030);
assign _zz_400_ = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
always @ (posedge clk) begin
if(_zz_281_) begin
_zz_161_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @ (posedge clk) begin
if(_zz_282_) begin
_zz_162_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @ (posedge clk) begin
if(_zz_36_) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c (
.io_push_valid (iBus_rsp_valid ), //i
.io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o
.io_push_payload_error (iBus_rsp_payload_error ), //i
.io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i
.io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o
.io_pop_ready (_zz_159_ ), //i
.io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o
.io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o
.io_flush (_zz_160_ ), //i
.io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_1_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_1__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_1__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_1__string = "AND_1";
default : _zz_1__string = "?????";
endcase
end
always @(*) begin
case(_zz_2_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_2__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_2__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_2__string = "AND_1";
default : _zz_2__string = "?????";
endcase
end
always @(*) begin
case(_zz_3_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_3__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_3__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_3__string = "AND_1";
default : _zz_3__string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_4_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC ";
default : _zz_4__string = "???";
endcase
end
always @(*) begin
case(_zz_5_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC ";
default : _zz_5__string = "???";
endcase
end
always @(*) begin
case(_zz_6_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC ";
default : _zz_6__string = "???";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_7_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7__string = "SRA_1 ";
default : _zz_7__string = "?????????";
endcase
end
always @(*) begin
case(_zz_8_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 ";
default : _zz_8__string = "?????????";
endcase
end
always @(*) begin
case(_zz_9_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9__string = "SRA_1 ";
default : _zz_9__string = "?????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_10_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_10__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_10__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_10__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_10__string = "URS1 ";
default : _zz_10__string = "????????????";
endcase
end
always @(*) begin
case(_zz_11_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1 ";
default : _zz_11__string = "????????????";
endcase
end
always @(*) begin
case(_zz_12_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 ";
default : _zz_12__string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_13_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR";
default : _zz_13__string = "????";
endcase
end
always @(*) begin
case(_zz_14_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR";
default : _zz_14__string = "????";
endcase
end
always @(*) begin
case(_zz_15_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR";
default : _zz_15__string = "????";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_16_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_16__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_16__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_16__string = "BITWISE ";
default : _zz_16__string = "????????";
endcase
end
always @(*) begin
case(_zz_17_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE ";
default : _zz_17__string = "????????";
endcase
end
always @(*) begin
case(_zz_18_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE ";
default : _zz_18__string = "????????";
endcase
end
always @(*) begin
case(_zz_19_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET";
default : _zz_19__string = "????";
endcase
end
always @(*) begin
case(_zz_20_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET";
default : _zz_20__string = "????";
endcase
end
always @(*) begin
case(_zz_21_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET";
default : _zz_21__string = "????";
endcase
end
always @(*) begin
case(_zz_22_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_22__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_22__string = "XRET";
default : _zz_22__string = "????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET";
default : decode_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_23_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_23__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_23__string = "XRET";
default : _zz_23__string = "????";
endcase
end
always @(*) begin
case(_zz_24_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET";
default : _zz_24__string = "????";
endcase
end
always @(*) begin
case(_zz_25_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET";
default : _zz_25__string = "????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_26_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_26__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_26__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_26__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_26__string = "JALR";
default : _zz_26__string = "????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_27_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_27__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_27__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_27__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_27__string = "SRA_1 ";
default : _zz_27__string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_29_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_29__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_29__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_29__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_29__string = "PC ";
default : _zz_29__string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_30_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_30__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_30__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_30__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_30__string = "URS1 ";
default : _zz_30__string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_31_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_31__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_31__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_31__string = "BITWISE ";
default : _zz_31__string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_32_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_32__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_32__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_32__string = "AND_1";
default : _zz_32__string = "?????";
endcase
end
always @(*) begin
case(_zz_37_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_37__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_37__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_37__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_37__string = "PC ";
default : _zz_37__string = "???";
endcase
end
always @(*) begin
case(_zz_38_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_38__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_38__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_38__string = "AND_1";
default : _zz_38__string = "?????";
endcase
end
always @(*) begin
case(_zz_39_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR";
default : _zz_39__string = "????";
endcase
end
always @(*) begin
case(_zz_40_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_40__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_40__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_40__string = "URS1 ";
default : _zz_40__string = "????????????";
endcase
end
always @(*) begin
case(_zz_41_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_41__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_41__string = "XRET";
default : _zz_41__string = "????";
endcase
end
always @(*) begin
case(_zz_42_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42__string = "SRA_1 ";
default : _zz_42__string = "?????????";
endcase
end
always @(*) begin
case(_zz_43_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_43__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_43__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_43__string = "BITWISE ";
default : _zz_43__string = "????????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET";
default : memory_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_45_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_45__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_45__string = "XRET";
default : _zz_45__string = "????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET";
default : execute_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_46_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_46__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_46__string = "XRET";
default : _zz_46__string = "????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET";
default : writeBack_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_47_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_47__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_47__string = "XRET";
default : _zz_47__string = "????";
endcase
end
always @(*) begin
case(_zz_111_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_111__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_111__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_111__string = "BITWISE ";
default : _zz_111__string = "????????";
endcase
end
always @(*) begin
case(_zz_112_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_112__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_112__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_112__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_112__string = "SRA_1 ";
default : _zz_112__string = "?????????";
endcase
end
always @(*) begin
case(_zz_113_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_113__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_113__string = "XRET";
default : _zz_113__string = "????";
endcase
end
always @(*) begin
case(_zz_114_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_114__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_114__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_114__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_114__string = "URS1 ";
default : _zz_114__string = "????????????";
endcase
end
always @(*) begin
case(_zz_115_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_115__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_115__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_115__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_115__string = "JALR";
default : _zz_115__string = "????";
endcase
end
always @(*) begin
case(_zz_116_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_116__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_116__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_116__string = "AND_1";
default : _zz_116__string = "?????";
endcase
end
always @(*) begin
case(_zz_117_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_117__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_117__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_117__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_117__string = "PC ";
default : _zz_117__string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET";
default : decode_to_execute_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET";
default : execute_to_memory_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET";
default : memory_to_writeBack_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
`endif
assign decode_ALU_BITWISE_CTRL = _zz_1_;
assign _zz_2_ = _zz_3_;
assign decode_MEMORY_ENABLE = _zz_193_[0];
assign decode_SRC2_CTRL = _zz_4_;
assign _zz_5_ = _zz_6_;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_195_);
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_SHIFT_CTRL = _zz_7_;
assign _zz_8_ = _zz_9_;
assign decode_IS_MUL = _zz_196_[0];
assign decode_MEMORY_STORE = _zz_197_[0];
assign decode_SRC1_CTRL = _zz_10_;
assign _zz_11_ = _zz_12_;
assign decode_IS_CSR = _zz_198_[0];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_199_[0];
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign execute_REGFILE_WRITE_DATA = _zz_119_;
assign decode_IS_RS1_SIGNED = _zz_200_[0];
assign decode_BRANCH_CTRL = _zz_13_;
assign _zz_14_ = _zz_15_;
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_201_[0];
assign memory_PC = execute_to_memory_PC;
assign decode_ALU_CTRL = _zz_16_;
assign _zz_17_ = _zz_18_;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign _zz_19_ = _zz_20_;
assign _zz_21_ = _zz_22_;
assign decode_ENV_CTRL = _zz_23_;
assign _zz_24_ = _zz_25_;
assign decode_SRC_LESS_UNSIGNED = _zz_202_[0];
assign decode_IS_RS2_SIGNED = _zz_203_[0];
assign decode_IS_DIV = _zz_204_[0];
assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0];
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
assign execute_BRANCH_DO = _zz_146_;
assign execute_PC = decode_to_execute_PC;
assign execute_BRANCH_CTRL = _zz_26_;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign decode_RS2_USE = _zz_205_[0];
assign decode_RS1_USE = _zz_206_[0];
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(_zz_130_)begin
if((_zz_131_ == decode_INSTRUCTION[24 : 20]))begin
decode_RS2 = _zz_132_;
end
end
if(_zz_163_)begin
if(_zz_164_)begin
if(_zz_134_)begin
decode_RS2 = _zz_33_;
end
end
end
if(_zz_165_)begin
if(memory_BYPASSABLE_MEMORY_STAGE)begin
if(_zz_136_)begin
decode_RS2 = _zz_48_;
end
end
end
if(_zz_166_)begin
if(execute_BYPASSABLE_EXECUTE_STAGE)begin
if(_zz_138_)begin
decode_RS2 = _zz_44_;
end
end
end
end
always @ (*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(_zz_130_)begin
if((_zz_131_ == decode_INSTRUCTION[19 : 15]))begin
decode_RS1 = _zz_132_;
end
end
if(_zz_163_)begin
if(_zz_164_)begin
if(_zz_133_)begin
decode_RS1 = _zz_33_;
end
end
end
if(_zz_165_)begin
if(memory_BYPASSABLE_MEMORY_STAGE)begin
if(_zz_135_)begin
decode_RS1 = _zz_48_;
end
end
end
if(_zz_166_)begin
if(execute_BYPASSABLE_EXECUTE_STAGE)begin
if(_zz_137_)begin
decode_RS1 = _zz_44_;
end
end
end
end
assign execute_SHIFT_RIGHT = _zz_208_;
assign execute_SHIFT_CTRL = _zz_27_;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_28_ = execute_PC;
assign execute_SRC2_CTRL = _zz_29_;
assign execute_IS_RVC = decode_to_execute_IS_RVC;
assign execute_SRC1_CTRL = _zz_30_;
assign decode_SRC_USE_SUB_LESS = _zz_210_[0];
assign decode_SRC_ADD_ZERO = _zz_211_[0];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_31_;
assign execute_SRC2 = _zz_125_;
assign execute_ALU_BITWISE_CTRL = _zz_32_;
assign _zz_33_ = writeBack_REGFILE_WRITE_DATA;
assign _zz_34_ = writeBack_INSTRUCTION;
assign _zz_35_ = writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
_zz_36_ = 1'b0;
if(lastStageRegFileWrite_valid)begin
_zz_36_ = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_decompressor_output_payload_rsp_inst);
always @ (*) begin
decode_REGFILE_WRITE_VALID = _zz_212_[0];
if((decode_INSTRUCTION[11 : 7] == 5'h0))begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
if(decode_INSTRUCTION[11])begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
always @ (*) begin
_zz_44_ = execute_REGFILE_WRITE_DATA;
if(_zz_167_)begin
_zz_44_ = execute_CsrPlugin_readData;
end
if(execute_arbitration_isValid)begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
_zz_44_ = _zz_127_;
end
`ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin
_zz_44_ = execute_SHIFT_RIGHT;
end
default : begin
end
endcase
end
end
assign execute_SRC1 = _zz_120_;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_45_;
assign execute_ENV_CTRL = _zz_46_;
assign writeBack_ENV_CTRL = _zz_47_;
always @ (*) begin
_zz_48_ = memory_REGFILE_WRITE_DATA;
if((memory_arbitration_isValid && memory_MEMORY_ENABLE))begin
_zz_48_ = memory_DBusSimplePlugin_rspFormated;
end
if(_zz_168_)begin
_zz_48_ = ((memory_INSTRUCTION[13 : 12] == (2'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]);
end
if(_zz_169_)begin
_zz_48_ = memory_MulDivIterativePlugin_div_result;
end
end
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
assign memory_MEMORY_READ_DATA = dBus_rsp_data;
assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_ALIGNEMENT_FAULT = 1'b0;
always @ (*) begin
_zz_49_ = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid)begin
_zz_49_ = BranchPlugin_jumpInterface_payload;
end
end
assign decode_PC = IBusSimplePlugin_decodePc_pcReg;
assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
assign decode_IS_RVC = IBusSimplePlugin_injector_decodeInput_payload_isRvc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
assign decode_arbitration_haltItself = 1'b0;
always @ (*) begin
decode_arbitration_haltByOther = 1'b0;
if(CsrPlugin_pipelineLiberator_active)begin
decode_arbitration_haltByOther = 1'b1;
end
if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin
decode_arbitration_haltByOther = 1'b1;
end
if((decode_arbitration_isValid && (_zz_128_ || _zz_129_)))begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @ (*) begin
decode_arbitration_removeIt = 1'b0;
if(decode_arbitration_isFlushed)begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
assign decode_arbitration_flushNext = 1'b0;
always @ (*) begin
execute_arbitration_haltItself = 1'b0;
if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_93_)))begin
execute_arbitration_haltItself = 1'b1;
end
if(_zz_167_)begin
if(execute_CsrPlugin_blockedBySideEffects)begin
execute_arbitration_haltItself = 1'b1;
end
end
end
assign execute_arbitration_haltByOther = 1'b0;
always @ (*) begin
execute_arbitration_removeIt = 1'b0;
if(execute_arbitration_isFlushed)begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @ (*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid)begin
execute_arbitration_flushNext = 1'b1;
end
end
always @ (*) begin
memory_arbitration_haltItself = 1'b0;
if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin
memory_arbitration_haltItself = 1'b1;
end
if(_zz_168_)begin
if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin
memory_arbitration_haltItself = 1'b1;
end
if(_zz_170_)begin
memory_arbitration_haltItself = 1'b1;
end
end
if(_zz_169_)begin
if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @ (*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed)begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
assign writeBack_arbitration_haltItself = 1'b0;
assign writeBack_arbitration_haltByOther = 1'b0;
always @ (*) begin
writeBack_arbitration_removeIt = 1'b0;
if(writeBack_arbitration_isFlushed)begin
writeBack_arbitration_removeIt = 1'b1;
end
end
assign writeBack_arbitration_flushIt = 1'b0;
always @ (*) begin
writeBack_arbitration_flushNext = 1'b0;
if(_zz_171_)begin
writeBack_arbitration_flushNext = 1'b1;
end
if(_zz_172_)begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @ (*) begin
IBusSimplePlugin_fetcherHalt = 1'b0;
if(_zz_171_)begin
IBusSimplePlugin_fetcherHalt = 1'b1;
end
if(_zz_172_)begin
IBusSimplePlugin_fetcherHalt = 1'b1;
end
end
always @ (*) begin
IBusSimplePlugin_incomingInstruction = 1'b0;
if((IBusSimplePlugin_iBusRsp_stages_1_input_valid || IBusSimplePlugin_iBusRsp_stages_2_input_valid))begin
IBusSimplePlugin_incomingInstruction = 1'b1;
end
if(IBusSimplePlugin_injector_decodeInput_valid)begin
IBusSimplePlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_inWfi = 1'b0;
assign CsrPlugin_thirdPartyWake = 1'b0;
always @ (*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(_zz_171_)begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(_zz_172_)begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @ (*) begin
CsrPlugin_jumpInterface_payload = 32'h0;
if(_zz_171_)begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
end
if(_zz_172_)begin
case(_zz_173_)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000));
assign IBusSimplePlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid} != (2'b00));
assign _zz_50_ = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid};
assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_213_[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload);
always @ (*) begin
IBusSimplePlugin_fetchPc_correction = 1'b0;
if(IBusSimplePlugin_jump_pcLoad_valid)begin
IBusSimplePlugin_fetchPc_correction = 1'b1;
end
end
assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg);
always @ (*) begin
IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin
IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
always @ (*) begin
IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_216_);
if(IBusSimplePlugin_fetchPc_inc)begin
IBusSimplePlugin_fetchPc_pc[1] = 1'b0;
end
if(IBusSimplePlugin_jump_pcLoad_valid)begin
IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload;
end
IBusSimplePlugin_fetchPc_pc[0] = 1'b0;
end
always @ (*) begin
IBusSimplePlugin_fetchPc_flushed = 1'b0;
if(IBusSimplePlugin_jump_pcLoad_valid)begin
IBusSimplePlugin_fetchPc_flushed = 1'b1;
end
end
assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted);
assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc;
always @ (*) begin
IBusSimplePlugin_decodePc_flushed = 1'b0;
if(_zz_174_)begin
IBusSimplePlugin_decodePc_flushed = 1'b1;
end
end
assign IBusSimplePlugin_decodePc_pcPlus = (IBusSimplePlugin_decodePc_pcReg + _zz_218_);
assign IBusSimplePlugin_decodePc_injectedDecode = 1'b0;
assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0;
assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid;
assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready;
assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload;
assign IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;
assign _zz_51_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt);
assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_51_);
assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_51_);
assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload;
always @ (*) begin
IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0;
if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin
IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_52_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt);
assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_52_);
assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_52_);
assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload;
assign IBusSimplePlugin_iBusRsp_stages_2_halt = 1'b0;
assign _zz_53_ = (! IBusSimplePlugin_iBusRsp_stages_2_halt);
assign IBusSimplePlugin_iBusRsp_stages_2_input_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_ready && _zz_53_);
assign IBusSimplePlugin_iBusRsp_stages_2_output_valid = (IBusSimplePlugin_iBusRsp_stages_2_input_valid && _zz_53_);
assign IBusSimplePlugin_iBusRsp_stages_2_output_payload = IBusSimplePlugin_iBusRsp_stages_2_input_payload;
assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch);
assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_54_;
assign _zz_54_ = ((1'b0 && (! _zz_55_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready);
assign _zz_55_ = _zz_56_;
assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_55_;
assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg;
assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_57_)) || IBusSimplePlugin_iBusRsp_stages_2_input_ready);
assign _zz_57_ = _zz_58_;
assign IBusSimplePlugin_iBusRsp_stages_2_input_valid = _zz_57_;
assign IBusSimplePlugin_iBusRsp_stages_2_input_payload = _zz_59_;
always @ (*) begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b1;
if(IBusSimplePlugin_injector_decodeInput_valid)begin
IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
end
end
assign IBusSimplePlugin_decompressor_input_valid = (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_iBusRsp_redoFetch));
assign IBusSimplePlugin_decompressor_input_payload_pc = IBusSimplePlugin_iBusRsp_output_payload_pc;
assign IBusSimplePlugin_decompressor_input_payload_rsp_error = IBusSimplePlugin_iBusRsp_output_payload_rsp_error;
assign IBusSimplePlugin_decompressor_input_payload_rsp_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
assign IBusSimplePlugin_decompressor_input_payload_isRvc = IBusSimplePlugin_iBusRsp_output_payload_isRvc;
assign IBusSimplePlugin_iBusRsp_output_ready = IBusSimplePlugin_decompressor_input_ready;
assign IBusSimplePlugin_decompressor_flushNext = 1'b0;
assign IBusSimplePlugin_decompressor_consumeCurrent = 1'b0;
assign IBusSimplePlugin_decompressor_isInputLowRvc = (IBusSimplePlugin_decompressor_input_payload_rsp_inst[1 : 0] != (2'b11));
assign IBusSimplePlugin_decompressor_isInputHighRvc = (IBusSimplePlugin_decompressor_input_payload_rsp_inst[17 : 16] != (2'b11));
assign IBusSimplePlugin_decompressor_throw2Bytes = (IBusSimplePlugin_decompressor_throw2BytesReg || IBusSimplePlugin_decompressor_input_payload_pc[1]);
assign IBusSimplePlugin_decompressor_unaligned = (IBusSimplePlugin_decompressor_throw2Bytes || IBusSimplePlugin_decompressor_bufferValid);
assign IBusSimplePlugin_decompressor_raw = (IBusSimplePlugin_decompressor_bufferValid ? {IBusSimplePlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusSimplePlugin_decompressor_bufferData} : {IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusSimplePlugin_decompressor_throw2Bytes ? IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusSimplePlugin_decompressor_input_payload_rsp_inst[15 : 0])});
assign IBusSimplePlugin_decompressor_isRvc = (IBusSimplePlugin_decompressor_raw[1 : 0] != (2'b11));
assign _zz_60_ = IBusSimplePlugin_decompressor_raw[15 : 0];
always @ (*) begin
IBusSimplePlugin_decompressor_decompressed = 32'h0;
case(_zz_188_)
5'b00000 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{{{(2'b00),_zz_60_[10 : 7]},_zz_60_[12 : 11]},_zz_60_[5]},_zz_60_[6]},(2'b00)},5'h02},(3'b000)},_zz_62_},7'h13};
end
5'b00010 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{_zz_63_,_zz_61_},(3'b010)},_zz_62_},7'h03};
end
5'b00110 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_63_[11 : 5],_zz_62_},_zz_61_},(3'b010)},_zz_63_[4 : 0]},7'h23};
end
5'b01000 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{_zz_65_,_zz_60_[11 : 7]},(3'b000)},_zz_60_[11 : 7]},7'h13};
end
5'b01001 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_68_[20],_zz_68_[10 : 1]},_zz_68_[11]},_zz_68_[19 : 12]},_zz_80_},7'h6f};
end
5'b01010 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{_zz_65_,5'h0},(3'b000)},_zz_60_[11 : 7]},7'h13};
end
5'b01011 : begin
IBusSimplePlugin_decompressor_decompressed = ((_zz_60_[11 : 7] == 5'h02) ? {{{{{{{{{_zz_72_,_zz_60_[4 : 3]},_zz_60_[5]},_zz_60_[2]},_zz_60_[6]},(4'b0000)},_zz_60_[11 : 7]},(3'b000)},_zz_60_[11 : 7]},7'h13} : {{_zz_219_[31 : 12],_zz_60_[11 : 7]},7'h37});
end
5'b01100 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{((_zz_60_[11 : 10] == (2'b10)) ? _zz_86_ : {{(1'b0),(_zz_283_ || _zz_284_)},5'h0}),(((! _zz_60_[11]) || _zz_82_) ? _zz_60_[6 : 2] : _zz_62_)},_zz_61_},_zz_84_},_zz_61_},(_zz_82_ ? 7'h13 : 7'h33)};
end
5'b01101 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_75_[20],_zz_75_[10 : 1]},_zz_75_[11]},_zz_75_[19 : 12]},_zz_79_},7'h6f};
end
5'b01110 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_78_[12],_zz_78_[10 : 5]},_zz_79_},_zz_61_},(3'b000)},_zz_78_[4 : 1]},_zz_78_[11]},7'h63};
end
5'b01111 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_78_[12],_zz_78_[10 : 5]},_zz_79_},_zz_61_},(3'b001)},_zz_78_[4 : 1]},_zz_78_[11]},7'h63};
end
5'b10000 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{7'h0,_zz_60_[6 : 2]},_zz_60_[11 : 7]},(3'b001)},_zz_60_[11 : 7]},7'h13};
end
5'b10010 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{{{{(4'b0000),_zz_60_[3 : 2]},_zz_60_[12]},_zz_60_[6 : 4]},(2'b00)},_zz_81_},(3'b010)},_zz_60_[11 : 7]},7'h03};
end
5'b10100 : begin
IBusSimplePlugin_decompressor_decompressed = ((_zz_60_[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_60_[6 : 2] == 5'h0) ? {{{{12'h0,_zz_60_[11 : 7]},(3'b000)},(_zz_60_[12] ? _zz_80_ : _zz_79_)},7'h67} : {{{{{_zz_285_,_zz_286_},(_zz_287_ ? _zz_288_ : _zz_79_)},(3'b000)},_zz_60_[11 : 7]},7'h33}));
end
5'b10110 : begin
IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_220_[11 : 5],_zz_60_[6 : 2]},_zz_81_},(3'b010)},_zz_221_[4 : 0]},7'h23};
end
default : begin
end
endcase
end
assign _zz_61_ = {(2'b01),_zz_60_[9 : 7]};
assign _zz_62_ = {(2'b01),_zz_60_[4 : 2]};
assign _zz_63_ = {{{{5'h0,_zz_60_[5]},_zz_60_[12 : 10]},_zz_60_[6]},(2'b00)};
assign _zz_64_ = _zz_60_[12];
always @ (*) begin
_zz_65_[11] = _zz_64_;
_zz_65_[10] = _zz_64_;
_zz_65_[9] = _zz_64_;
_zz_65_[8] = _zz_64_;
_zz_65_[7] = _zz_64_;
_zz_65_[6] = _zz_64_;
_zz_65_[5] = _zz_64_;
_zz_65_[4 : 0] = _zz_60_[6 : 2];
end
assign _zz_66_ = _zz_60_[12];
always @ (*) begin
_zz_67_[9] = _zz_66_;
_zz_67_[8] = _zz_66_;
_zz_67_[7] = _zz_66_;
_zz_67_[6] = _zz_66_;
_zz_67_[5] = _zz_66_;
_zz_67_[4] = _zz_66_;
_zz_67_[3] = _zz_66_;
_zz_67_[2] = _zz_66_;
_zz_67_[1] = _zz_66_;
_zz_67_[0] = _zz_66_;
end
assign _zz_68_ = {{{{{{{{_zz_67_,_zz_60_[8]},_zz_60_[10 : 9]},_zz_60_[6]},_zz_60_[7]},_zz_60_[2]},_zz_60_[11]},_zz_60_[5 : 3]},(1'b0)};
assign _zz_69_ = _zz_60_[12];
always @ (*) begin
_zz_70_[14] = _zz_69_;
_zz_70_[13] = _zz_69_;
_zz_70_[12] = _zz_69_;
_zz_70_[11] = _zz_69_;
_zz_70_[10] = _zz_69_;
_zz_70_[9] = _zz_69_;
_zz_70_[8] = _zz_69_;
_zz_70_[7] = _zz_69_;
_zz_70_[6] = _zz_69_;
_zz_70_[5] = _zz_69_;
_zz_70_[4] = _zz_69_;
_zz_70_[3] = _zz_69_;
_zz_70_[2] = _zz_69_;
_zz_70_[1] = _zz_69_;
_zz_70_[0] = _zz_69_;
end
assign _zz_71_ = _zz_60_[12];
always @ (*) begin
_zz_72_[2] = _zz_71_;
_zz_72_[1] = _zz_71_;
_zz_72_[0] = _zz_71_;
end
assign _zz_73_ = _zz_60_[12];
always @ (*) begin
_zz_74_[9] = _zz_73_;
_zz_74_[8] = _zz_73_;
_zz_74_[7] = _zz_73_;
_zz_74_[6] = _zz_73_;
_zz_74_[5] = _zz_73_;
_zz_74_[4] = _zz_73_;
_zz_74_[3] = _zz_73_;
_zz_74_[2] = _zz_73_;
_zz_74_[1] = _zz_73_;
_zz_74_[0] = _zz_73_;
end
assign _zz_75_ = {{{{{{{{_zz_74_,_zz_60_[8]},_zz_60_[10 : 9]},_zz_60_[6]},_zz_60_[7]},_zz_60_[2]},_zz_60_[11]},_zz_60_[5 : 3]},(1'b0)};
assign _zz_76_ = _zz_60_[12];
always @ (*) begin
_zz_77_[4] = _zz_76_;
_zz_77_[3] = _zz_76_;
_zz_77_[2] = _zz_76_;
_zz_77_[1] = _zz_76_;
_zz_77_[0] = _zz_76_;
end
assign _zz_78_ = {{{{{_zz_77_,_zz_60_[6 : 5]},_zz_60_[2]},_zz_60_[11 : 10]},_zz_60_[4 : 3]},(1'b0)};
assign _zz_79_ = 5'h0;
assign _zz_80_ = 5'h01;
assign _zz_81_ = 5'h02;
assign _zz_82_ = (_zz_60_[11 : 10] != (2'b11));
always @ (*) begin
case(_zz_189_)
2'b00 : begin
_zz_83_ = (3'b000);
end
2'b01 : begin
_zz_83_ = (3'b100);
end
2'b10 : begin
_zz_83_ = (3'b110);
end
default : begin
_zz_83_ = (3'b111);
end
endcase
end
always @ (*) begin
case(_zz_190_)
2'b00 : begin
_zz_84_ = (3'b101);
end
2'b01 : begin
_zz_84_ = (3'b101);
end
2'b10 : begin
_zz_84_ = (3'b111);
end
default : begin
_zz_84_ = _zz_83_;
end
endcase
end
assign _zz_85_ = _zz_60_[12];
always @ (*) begin
_zz_86_[6] = _zz_85_;
_zz_86_[5] = _zz_85_;
_zz_86_[4] = _zz_85_;
_zz_86_[3] = _zz_85_;
_zz_86_[2] = _zz_85_;
_zz_86_[1] = _zz_85_;
_zz_86_[0] = _zz_85_;
end
assign IBusSimplePlugin_decompressor_output_valid = (IBusSimplePlugin_decompressor_input_valid && (! ((IBusSimplePlugin_decompressor_throw2Bytes && (! IBusSimplePlugin_decompressor_bufferValid)) && (! IBusSimplePlugin_decompressor_isInputHighRvc))));
assign IBusSimplePlugin_decompressor_output_payload_pc = IBusSimplePlugin_decompressor_input_payload_pc;
assign IBusSimplePlugin_decompressor_output_payload_isRvc = IBusSimplePlugin_decompressor_isRvc;
assign IBusSimplePlugin_decompressor_output_payload_rsp_inst = (IBusSimplePlugin_decompressor_isRvc ? IBusSimplePlugin_decompressor_decompressed : IBusSimplePlugin_decompressor_raw);
assign IBusSimplePlugin_decompressor_input_ready = (IBusSimplePlugin_decompressor_output_ready && (((! IBusSimplePlugin_iBusRsp_stages_2_input_valid) || IBusSimplePlugin_decompressor_flushNext) || ((! (IBusSimplePlugin_decompressor_bufferValid && IBusSimplePlugin_decompressor_isInputHighRvc)) && (! (((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && IBusSimplePlugin_decompressor_isInputHighRvc)))));
assign IBusSimplePlugin_decompressor_bufferFill = (((((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && (! IBusSimplePlugin_decompressor_isInputHighRvc)) || (IBusSimplePlugin_decompressor_bufferValid && (! IBusSimplePlugin_decompressor_isInputHighRvc))) || ((IBusSimplePlugin_decompressor_throw2Bytes && (! IBusSimplePlugin_decompressor_isRvc)) && (! IBusSimplePlugin_decompressor_isInputHighRvc)));
assign IBusSimplePlugin_decompressor_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready);
assign IBusSimplePlugin_injector_decodeInput_valid = _zz_87_;
assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_88_;
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_89_;
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_90_;
assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_91_;
assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_0;
assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_1;
assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_2;
assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_3;
assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid;
assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid;
assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready;
assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc;
assign IBusSimplePlugin_pending_next = (_zz_222_ - _zz_226_);
assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && (IBusSimplePlugin_pending_value != (3'b111)));
assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_cmdFork_canEmit);
assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready);
assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_1_input_payload[31 : 2],(2'b00)};
assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != (3'b000)) || IBusSimplePlugin_iBusRsp_flush);
assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == (3'b000)));
assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
assign _zz_159_ = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush);
assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_159_);
assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_2_output_payload;
always @ (*) begin
IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error;
if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin
IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0;
end
end
assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst;
assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0;
assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_2_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid);
assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc;
assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
assign IBusSimplePlugin_iBusRsp_stages_2_output_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready);
assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready);
assign _zz_92_ = (! IBusSimplePlugin_rspJoin_exceptionDetected);
assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_92_);
assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_92_);
assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc;
assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error;
assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc;
assign _zz_93_ = 1'b0;
always @ (*) begin
execute_DBusSimplePlugin_skipCmd = 1'b0;
if(execute_ALIGNEMENT_FAULT)begin
execute_DBusSimplePlugin_skipCmd = 1'b1;
end
end
assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_93_));
assign dBus_cmd_payload_wr = execute_MEMORY_STORE;
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_94_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_94_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_94_ = execute_RS2[31 : 0];
end
endcase
end
assign dBus_cmd_payload_data = _zz_94_;
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_95_ = (4'b0001);
end
2'b01 : begin
_zz_95_ = (4'b0011);
end
default : begin
_zz_95_ = (4'b1111);
end
endcase
end
assign execute_DBusSimplePlugin_formalMask = (_zz_95_ <<< dBus_cmd_payload_address[1 : 0]);
assign dBus_cmd_payload_address = execute_SRC_ADD;
always @ (*) begin
memory_DBusSimplePlugin_rspShifted = memory_MEMORY_READ_DATA;
case(memory_MEMORY_ADDRESS_LOW)
2'b01 : begin
memory_DBusSimplePlugin_rspShifted[7 : 0] = memory_MEMORY_READ_DATA[15 : 8];
end
2'b10 : begin
memory_DBusSimplePlugin_rspShifted[15 : 0] = memory_MEMORY_READ_DATA[31 : 16];
end
2'b11 : begin
memory_DBusSimplePlugin_rspShifted[7 : 0] = memory_MEMORY_READ_DATA[31 : 24];
end
default : begin
end
endcase
end
assign _zz_96_ = (memory_DBusSimplePlugin_rspShifted[7] && (! memory_INSTRUCTION[14]));
always @ (*) begin
_zz_97_[31] = _zz_96_;
_zz_97_[30] = _zz_96_;
_zz_97_[29] = _zz_96_;
_zz_97_[28] = _zz_96_;
_zz_97_[27] = _zz_96_;
_zz_97_[26] = _zz_96_;
_zz_97_[25] = _zz_96_;
_zz_97_[24] = _zz_96_;
_zz_97_[23] = _zz_96_;
_zz_97_[22] = _zz_96_;
_zz_97_[21] = _zz_96_;
_zz_97_[20] = _zz_96_;
_zz_97_[19] = _zz_96_;
_zz_97_[18] = _zz_96_;
_zz_97_[17] = _zz_96_;
_zz_97_[16] = _zz_96_;
_zz_97_[15] = _zz_96_;
_zz_97_[14] = _zz_96_;
_zz_97_[13] = _zz_96_;
_zz_97_[12] = _zz_96_;
_zz_97_[11] = _zz_96_;
_zz_97_[10] = _zz_96_;
_zz_97_[9] = _zz_96_;
_zz_97_[8] = _zz_96_;
_zz_97_[7 : 0] = memory_DBusSimplePlugin_rspShifted[7 : 0];
end
assign _zz_98_ = (memory_DBusSimplePlugin_rspShifted[15] && (! memory_INSTRUCTION[14]));
always @ (*) begin
_zz_99_[31] = _zz_98_;
_zz_99_[30] = _zz_98_;
_zz_99_[29] = _zz_98_;
_zz_99_[28] = _zz_98_;
_zz_99_[27] = _zz_98_;
_zz_99_[26] = _zz_98_;
_zz_99_[25] = _zz_98_;
_zz_99_[24] = _zz_98_;
_zz_99_[23] = _zz_98_;
_zz_99_[22] = _zz_98_;
_zz_99_[21] = _zz_98_;
_zz_99_[20] = _zz_98_;
_zz_99_[19] = _zz_98_;
_zz_99_[18] = _zz_98_;
_zz_99_[17] = _zz_98_;
_zz_99_[16] = _zz_98_;
_zz_99_[15 : 0] = memory_DBusSimplePlugin_rspShifted[15 : 0];
end
always @ (*) begin
case(_zz_191_)
2'b00 : begin
memory_DBusSimplePlugin_rspFormated = _zz_97_;
end
2'b01 : begin
memory_DBusSimplePlugin_rspFormated = _zz_99_;
end
default : begin
memory_DBusSimplePlugin_rspFormated = memory_DBusSimplePlugin_rspShifted;
end
endcase
end
always @ (*) begin
CsrPlugin_privilege = (2'b11);
if(CsrPlugin_forceMachineWire)begin
CsrPlugin_privilege = (2'b11);
end
end
assign CsrPlugin_misa_base = (2'b01);
assign CsrPlugin_misa_extensions = 26'h0000042;
assign CsrPlugin_mtvec_mode = (2'b00);
assign CsrPlugin_mtvec_base = 30'h00000001;
assign _zz_100_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_101_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_102_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exception = 1'b0;
assign CsrPlugin_lastStageWasWfi = 1'b0;
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
always @ (*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(CsrPlugin_hadException)begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
assign CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
assign CsrPlugin_trapCause = CsrPlugin_interrupt_code;
always @ (*) begin
CsrPlugin_xtvec_mode = (2'bxx);
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @ (*) begin
CsrPlugin_xtvec_base = 30'h0;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00));
always @ (*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_768)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834)begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @ (*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
always @ (*) begin
case(_zz_192_)
1'b0 : begin
execute_CsrPlugin_writeData = execute_SRC1;
end
default : begin
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign _zz_104_ = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz_105_ = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000);
assign _zz_106_ = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000);
assign _zz_107_ = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000);
assign _zz_108_ = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_109_ = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_110_ = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_103_ = {({(_zz_289_ == _zz_290_),{_zz_291_,{_zz_292_,_zz_293_}}} != (4'b0000)),{({_zz_110_,_zz_294_} != (2'b00)),{({_zz_295_,_zz_296_} != (2'b00)),{(_zz_297_ != _zz_298_),{_zz_299_,{_zz_300_,_zz_301_}}}}}};
assign _zz_111_ = _zz_103_[3 : 2];
assign _zz_43_ = _zz_111_;
assign _zz_112_ = _zz_103_[9 : 8];
assign _zz_42_ = _zz_112_;
assign _zz_113_ = _zz_103_[10 : 10];
assign _zz_41_ = _zz_113_;
assign _zz_114_ = _zz_103_[12 : 11];
assign _zz_40_ = _zz_114_;
assign _zz_115_ = _zz_103_[15 : 14];
assign _zz_39_ = _zz_115_;
assign _zz_116_ = _zz_103_[23 : 22];
assign _zz_38_ = _zz_116_;
assign _zz_117_ = _zz_103_[27 : 26];
assign _zz_37_ = _zz_117_;
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[18 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[23 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_161_;
assign decode_RegFilePlugin_rs2Data = _zz_162_;
always @ (*) begin
lastStageRegFileWrite_valid = (_zz_35_ && writeBack_arbitration_isFiring);
if(_zz_118_)begin
lastStageRegFileWrite_valid = 1'b1;
end
end
assign lastStageRegFileWrite_payload_address = _zz_34_[10 : 7];
assign lastStageRegFileWrite_payload_data = _zz_33_;
always @ (*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @ (*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_BITWISE : begin
_zz_119_ = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
_zz_119_ = {31'd0, _zz_229_};
end
default : begin
_zz_119_ = execute_SRC_ADD_SUB;
end
endcase
end
always @ (*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : begin
_zz_120_ = execute_RS1;
end
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
_zz_120_ = {29'd0, _zz_230_};
end
`Src1CtrlEnum_defaultEncoding_IMU : begin
_zz_120_ = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_120_ = {27'd0, _zz_231_};
end
endcase
end
assign _zz_121_ = _zz_232_[11];
always @ (*) begin
_zz_122_[19] = _zz_121_;
_zz_122_[18] = _zz_121_;
_zz_122_[17] = _zz_121_;
_zz_122_[16] = _zz_121_;
_zz_122_[15] = _zz_121_;
_zz_122_[14] = _zz_121_;
_zz_122_[13] = _zz_121_;
_zz_122_[12] = _zz_121_;
_zz_122_[11] = _zz_121_;
_zz_122_[10] = _zz_121_;
_zz_122_[9] = _zz_121_;
_zz_122_[8] = _zz_121_;
_zz_122_[7] = _zz_121_;
_zz_122_[6] = _zz_121_;
_zz_122_[5] = _zz_121_;
_zz_122_[4] = _zz_121_;
_zz_122_[3] = _zz_121_;
_zz_122_[2] = _zz_121_;
_zz_122_[1] = _zz_121_;
_zz_122_[0] = _zz_121_;
end
assign _zz_123_ = _zz_233_[11];
always @ (*) begin
_zz_124_[19] = _zz_123_;
_zz_124_[18] = _zz_123_;
_zz_124_[17] = _zz_123_;
_zz_124_[16] = _zz_123_;
_zz_124_[15] = _zz_123_;
_zz_124_[14] = _zz_123_;
_zz_124_[13] = _zz_123_;
_zz_124_[12] = _zz_123_;
_zz_124_[11] = _zz_123_;
_zz_124_[10] = _zz_123_;
_zz_124_[9] = _zz_123_;
_zz_124_[8] = _zz_123_;
_zz_124_[7] = _zz_123_;
_zz_124_[6] = _zz_123_;
_zz_124_[5] = _zz_123_;
_zz_124_[4] = _zz_123_;
_zz_124_[3] = _zz_123_;
_zz_124_[2] = _zz_123_;
_zz_124_[1] = _zz_123_;
_zz_124_[0] = _zz_123_;
end
always @ (*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : begin
_zz_125_ = execute_RS2;
end
`Src2CtrlEnum_defaultEncoding_IMI : begin
_zz_125_ = {_zz_122_,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_defaultEncoding_IMS : begin
_zz_125_ = {_zz_124_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_125_ = _zz_28_;
end
endcase
end
always @ (*) begin
execute_SrcPlugin_addSub = _zz_234_;
if(execute_SRC2_FORCE_ZERO)begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @ (*) begin
_zz_126_[0] = execute_SRC1[31];
_zz_126_[1] = execute_SRC1[30];
_zz_126_[2] = execute_SRC1[29];
_zz_126_[3] = execute_SRC1[28];
_zz_126_[4] = execute_SRC1[27];
_zz_126_[5] = execute_SRC1[26];
_zz_126_[6] = execute_SRC1[25];
_zz_126_[7] = execute_SRC1[24];
_zz_126_[8] = execute_SRC1[23];
_zz_126_[9] = execute_SRC1[22];
_zz_126_[10] = execute_SRC1[21];
_zz_126_[11] = execute_SRC1[20];
_zz_126_[12] = execute_SRC1[19];
_zz_126_[13] = execute_SRC1[18];
_zz_126_[14] = execute_SRC1[17];
_zz_126_[15] = execute_SRC1[16];
_zz_126_[16] = execute_SRC1[15];
_zz_126_[17] = execute_SRC1[14];
_zz_126_[18] = execute_SRC1[13];
_zz_126_[19] = execute_SRC1[12];
_zz_126_[20] = execute_SRC1[11];
_zz_126_[21] = execute_SRC1[10];
_zz_126_[22] = execute_SRC1[9];
_zz_126_[23] = execute_SRC1[8];
_zz_126_[24] = execute_SRC1[7];
_zz_126_[25] = execute_SRC1[6];
_zz_126_[26] = execute_SRC1[5];
_zz_126_[27] = execute_SRC1[4];
_zz_126_[28] = execute_SRC1[3];
_zz_126_[29] = execute_SRC1[2];
_zz_126_[30] = execute_SRC1[1];
_zz_126_[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_126_ : execute_SRC1);
always @ (*) begin
_zz_127_[0] = execute_SHIFT_RIGHT[31];
_zz_127_[1] = execute_SHIFT_RIGHT[30];
_zz_127_[2] = execute_SHIFT_RIGHT[29];
_zz_127_[3] = execute_SHIFT_RIGHT[28];
_zz_127_[4] = execute_SHIFT_RIGHT[27];
_zz_127_[5] = execute_SHIFT_RIGHT[26];
_zz_127_[6] = execute_SHIFT_RIGHT[25];
_zz_127_[7] = execute_SHIFT_RIGHT[24];
_zz_127_[8] = execute_SHIFT_RIGHT[23];
_zz_127_[9] = execute_SHIFT_RIGHT[22];
_zz_127_[10] = execute_SHIFT_RIGHT[21];
_zz_127_[11] = execute_SHIFT_RIGHT[20];
_zz_127_[12] = execute_SHIFT_RIGHT[19];
_zz_127_[13] = execute_SHIFT_RIGHT[18];
_zz_127_[14] = execute_SHIFT_RIGHT[17];
_zz_127_[15] = execute_SHIFT_RIGHT[16];
_zz_127_[16] = execute_SHIFT_RIGHT[15];
_zz_127_[17] = execute_SHIFT_RIGHT[14];
_zz_127_[18] = execute_SHIFT_RIGHT[13];
_zz_127_[19] = execute_SHIFT_RIGHT[12];
_zz_127_[20] = execute_SHIFT_RIGHT[11];
_zz_127_[21] = execute_SHIFT_RIGHT[10];
_zz_127_[22] = execute_SHIFT_RIGHT[9];
_zz_127_[23] = execute_SHIFT_RIGHT[8];
_zz_127_[24] = execute_SHIFT_RIGHT[7];
_zz_127_[25] = execute_SHIFT_RIGHT[6];
_zz_127_[26] = execute_SHIFT_RIGHT[5];
_zz_127_[27] = execute_SHIFT_RIGHT[4];
_zz_127_[28] = execute_SHIFT_RIGHT[3];
_zz_127_[29] = execute_SHIFT_RIGHT[2];
_zz_127_[30] = execute_SHIFT_RIGHT[1];
_zz_127_[31] = execute_SHIFT_RIGHT[0];
end
always @ (*) begin
_zz_128_ = 1'b0;
if(_zz_175_)begin
if(_zz_176_)begin
if(_zz_133_)begin
_zz_128_ = 1'b1;
end
end
end
if(_zz_177_)begin
if(_zz_178_)begin
if(_zz_135_)begin
_zz_128_ = 1'b1;
end
end
end
if(_zz_179_)begin
if(_zz_180_)begin
if(_zz_137_)begin
_zz_128_ = 1'b1;
end
end
end
if((! decode_RS1_USE))begin
_zz_128_ = 1'b0;
end
end
always @ (*) begin
_zz_129_ = 1'b0;
if(_zz_175_)begin
if(_zz_176_)begin
if(_zz_134_)begin
_zz_129_ = 1'b1;
end
end
end
if(_zz_177_)begin
if(_zz_178_)begin
if(_zz_136_)begin
_zz_129_ = 1'b1;
end
end
end
if(_zz_179_)begin
if(_zz_180_)begin
if(_zz_138_)begin
_zz_129_ = 1'b1;
end
end
end
if((! decode_RS2_USE))begin
_zz_129_ = 1'b0;
end
end
assign _zz_133_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_134_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_135_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_136_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_137_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_138_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign memory_MulDivIterativePlugin_frontendOk = 1'b1;
always @ (*) begin
memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0;
if(_zz_168_)begin
if(_zz_170_)begin
memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1;
end
end
end
always @ (*) begin
memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0;
if((! memory_arbitration_isStuck))begin
memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1;
end
end
assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 5'h10);
assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement);
always @ (*) begin
if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin
memory_MulDivIterativePlugin_mul_counter_valueNext = 5'h0;
end else begin
memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_242_);
end
if(memory_MulDivIterativePlugin_mul_counter_willClear)begin
memory_MulDivIterativePlugin_mul_counter_valueNext = 5'h0;
end
end
always @ (*) begin
memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0;
if(_zz_169_)begin
if(_zz_181_)begin
memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @ (*) begin
memory_MulDivIterativePlugin_div_counter_willClear = 1'b0;
if(_zz_182_)begin
memory_MulDivIterativePlugin_div_counter_willClear = 1'b1;
end
end
assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 5'h11);
assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement);
always @ (*) begin
if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin
memory_MulDivIterativePlugin_div_counter_valueNext = 5'h0;
end else begin
memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_254_);
end
if(memory_MulDivIterativePlugin_div_counter_willClear)begin
memory_MulDivIterativePlugin_div_counter_valueNext = 5'h0;
end
end
assign _zz_139_ = memory_MulDivIterativePlugin_rs1[31 : 0];
assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_139_[31]};
assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_255_);
assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_256_ : _zz_257_);
assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_258_[31:0];
assign memory_MulDivIterativePlugin_div_stage_1_remainderShifted = {memory_MulDivIterativePlugin_div_stage_0_outRemainder,memory_MulDivIterativePlugin_div_stage_0_outNumerator[31]};
assign memory_MulDivIterativePlugin_div_stage_1_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_1_remainderShifted - _zz_259_);
assign memory_MulDivIterativePlugin_div_stage_1_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_1_remainderMinusDenominator[32]) ? _zz_260_ : _zz_261_);
assign memory_MulDivIterativePlugin_div_stage_1_outNumerator = _zz_262_[31:0];
assign _zz_140_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]);
assign _zz_141_ = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_142_ = ((execute_IS_MUL && _zz_141_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @ (*) begin
_zz_143_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_143_[31 : 0] = execute_RS1;
end
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign _zz_144_ = execute_INSTRUCTION[14 : 12];
always @ (*) begin
if((_zz_144_ == (3'b000))) begin
_zz_145_ = execute_BranchPlugin_eq;
end else if((_zz_144_ == (3'b001))) begin
_zz_145_ = (! execute_BranchPlugin_eq);
end else if((((_zz_144_ & (3'b101)) == (3'b101)))) begin
_zz_145_ = (! execute_SRC_LESS);
end else begin
_zz_145_ = execute_SRC_LESS;
end
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : begin
_zz_146_ = 1'b0;
end
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_146_ = 1'b1;
end
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_146_ = 1'b1;
end
default : begin
_zz_146_ = _zz_145_;
end
endcase
end
assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
assign _zz_147_ = _zz_272_[19];
always @ (*) begin
_zz_148_[10] = _zz_147_;
_zz_148_[9] = _zz_147_;
_zz_148_[8] = _zz_147_;
_zz_148_[7] = _zz_147_;
_zz_148_[6] = _zz_147_;
_zz_148_[5] = _zz_147_;
_zz_148_[4] = _zz_147_;
_zz_148_[3] = _zz_147_;
_zz_148_[2] = _zz_147_;
_zz_148_[1] = _zz_147_;
_zz_148_[0] = _zz_147_;
end
assign _zz_149_ = _zz_273_[11];
always @ (*) begin
_zz_150_[19] = _zz_149_;
_zz_150_[18] = _zz_149_;
_zz_150_[17] = _zz_149_;
_zz_150_[16] = _zz_149_;
_zz_150_[15] = _zz_149_;
_zz_150_[14] = _zz_149_;
_zz_150_[13] = _zz_149_;
_zz_150_[12] = _zz_149_;
_zz_150_[11] = _zz_149_;
_zz_150_[10] = _zz_149_;
_zz_150_[9] = _zz_149_;
_zz_150_[8] = _zz_149_;
_zz_150_[7] = _zz_149_;
_zz_150_[6] = _zz_149_;
_zz_150_[5] = _zz_149_;
_zz_150_[4] = _zz_149_;
_zz_150_[3] = _zz_149_;
_zz_150_[2] = _zz_149_;
_zz_150_[1] = _zz_149_;
_zz_150_[0] = _zz_149_;
end
assign _zz_151_ = _zz_274_[11];
always @ (*) begin
_zz_152_[18] = _zz_151_;
_zz_152_[17] = _zz_151_;
_zz_152_[16] = _zz_151_;
_zz_152_[15] = _zz_151_;
_zz_152_[14] = _zz_151_;
_zz_152_[13] = _zz_151_;
_zz_152_[12] = _zz_151_;
_zz_152_[11] = _zz_151_;
_zz_152_[10] = _zz_151_;
_zz_152_[9] = _zz_151_;
_zz_152_[8] = _zz_151_;
_zz_152_[7] = _zz_151_;
_zz_152_[6] = _zz_151_;
_zz_152_[5] = _zz_151_;
_zz_152_[4] = _zz_151_;
_zz_152_[3] = _zz_151_;
_zz_152_[2] = _zz_151_;
_zz_152_[1] = _zz_151_;
_zz_152_[0] = _zz_151_;
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_153_ = {{_zz_148_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
end
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_153_ = {_zz_150_,execute_INSTRUCTION[31 : 20]};
end
default : begin
_zz_153_ = {{_zz_152_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
end
endcase
end
assign execute_BranchPlugin_branch_src2 = _zz_153_;
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
assign _zz_25_ = decode_ENV_CTRL;
assign _zz_22_ = execute_ENV_CTRL;
assign _zz_20_ = memory_ENV_CTRL;
assign _zz_23_ = _zz_41_;
assign _zz_46_ = decode_to_execute_ENV_CTRL;
assign _zz_45_ = execute_to_memory_ENV_CTRL;
assign _zz_47_ = memory_to_writeBack_ENV_CTRL;
assign _zz_18_ = decode_ALU_CTRL;
assign _zz_16_ = _zz_43_;
assign _zz_31_ = decode_to_execute_ALU_CTRL;
assign _zz_15_ = decode_BRANCH_CTRL;
assign _zz_13_ = _zz_39_;
assign _zz_26_ = decode_to_execute_BRANCH_CTRL;
assign _zz_12_ = decode_SRC1_CTRL;
assign _zz_10_ = _zz_40_;
assign _zz_30_ = decode_to_execute_SRC1_CTRL;
assign _zz_9_ = decode_SHIFT_CTRL;
assign _zz_7_ = _zz_42_;
assign _zz_27_ = decode_to_execute_SHIFT_CTRL;
assign _zz_6_ = decode_SRC2_CTRL;
assign _zz_4_ = _zz_37_;
assign _zz_29_ = decode_to_execute_SRC2_CTRL;
assign _zz_3_ = decode_ALU_BITWISE_CTRL;
assign _zz_1_ = _zz_38_;
assign _zz_32_ = decode_to_execute_ALU_BITWISE_CTRL;
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000)));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000)));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00)));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0)));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
always @ (*) begin
_zz_154_ = 32'h0;
if(execute_CsrPlugin_csr_768)begin
_zz_154_[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_154_[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_154_[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @ (*) begin
_zz_155_ = 32'h0;
if(execute_CsrPlugin_csr_836)begin
_zz_155_[11 : 11] = CsrPlugin_mip_MEIP;
_zz_155_[7 : 7] = CsrPlugin_mip_MTIP;
_zz_155_[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @ (*) begin
_zz_156_ = 32'h0;
if(execute_CsrPlugin_csr_772)begin
_zz_156_[11 : 11] = CsrPlugin_mie_MEIE;
_zz_156_[7 : 7] = CsrPlugin_mie_MTIE;
_zz_156_[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @ (*) begin
_zz_157_ = 32'h0;
if(execute_CsrPlugin_csr_832)begin
_zz_157_[31 : 0] = CsrPlugin_mscratch;
end
end
always @ (*) begin
_zz_158_ = 32'h0;
if(execute_CsrPlugin_csr_834)begin
_zz_158_[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_158_[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
assign execute_CsrPlugin_readData = (((_zz_154_ | _zz_155_) | (_zz_156_ | _zz_157_)) | _zz_158_);
assign _zz_160_ = 1'b0;
always @ (posedge clk or posedge reset) begin
if (reset) begin
IBusSimplePlugin_fetchPc_pcReg <= 32'h0;
IBusSimplePlugin_fetchPc_correctionReg <= 1'b0;
IBusSimplePlugin_fetchPc_booted <= 1'b0;
IBusSimplePlugin_fetchPc_inc <= 1'b0;
IBusSimplePlugin_decodePc_pcReg <= 32'h0;
_zz_56_ <= 1'b0;
_zz_58_ <= 1'b0;
IBusSimplePlugin_decompressor_bufferValid <= 1'b0;
IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0;
_zz_87_ <= 1'b0;
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusSimplePlugin_pending_value <= (3'b000);
IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (3'b000);
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= (2'b11);
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
_zz_118_ <= 1'b1;
_zz_130_ <= 1'b0;
memory_MulDivIterativePlugin_mul_counter_value <= 5'h0;
memory_MulDivIterativePlugin_div_counter_value <= 5'h0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0;
memory_to_writeBack_INSTRUCTION <= 32'h0;
end else begin
if(IBusSimplePlugin_fetchPc_correction)begin
IBusSimplePlugin_fetchPc_correctionReg <= 1'b1;
end
if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin
IBusSimplePlugin_fetchPc_correctionReg <= 1'b0;
end
IBusSimplePlugin_fetchPc_booted <= 1'b1;
if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin
IBusSimplePlugin_fetchPc_inc <= 1'b0;
end
if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin
IBusSimplePlugin_fetchPc_inc <= 1'b1;
end
if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin
IBusSimplePlugin_fetchPc_inc <= 1'b0;
end
if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin
IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc;
end
if((decode_arbitration_isFiring && (! IBusSimplePlugin_decodePc_injectedDecode)))begin
IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_decodePc_pcPlus;
end
if(_zz_174_)begin
IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_jump_pcLoad_payload;
end
if(IBusSimplePlugin_iBusRsp_flush)begin
_zz_56_ <= 1'b0;
end
if(_zz_54_)begin
_zz_56_ <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusSimplePlugin_iBusRsp_flush)begin
_zz_58_ <= 1'b0;
end
if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin
_zz_58_ <= (IBusSimplePlugin_iBusRsp_stages_1_output_valid && (! IBusSimplePlugin_iBusRsp_flush));
end
if((IBusSimplePlugin_decompressor_output_valid && IBusSimplePlugin_decompressor_output_ready))begin
IBusSimplePlugin_decompressor_throw2BytesReg <= ((((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && IBusSimplePlugin_decompressor_isInputHighRvc) || (IBusSimplePlugin_decompressor_bufferValid && IBusSimplePlugin_decompressor_isInputHighRvc));
end
if((IBusSimplePlugin_decompressor_output_ready && IBusSimplePlugin_decompressor_input_valid))begin
IBusSimplePlugin_decompressor_bufferValid <= 1'b0;
end
if(_zz_183_)begin
if(IBusSimplePlugin_decompressor_bufferFill)begin
IBusSimplePlugin_decompressor_bufferValid <= 1'b1;
end
end
if((IBusSimplePlugin_externalFlush || IBusSimplePlugin_decompressor_consumeCurrent))begin
IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0;
IBusSimplePlugin_decompressor_bufferValid <= 1'b0;
end
if(decode_arbitration_removeIt)begin
_zz_87_ <= 1'b0;
end
if(IBusSimplePlugin_decompressor_output_ready)begin
_zz_87_ <= (IBusSimplePlugin_decompressor_output_valid && (! IBusSimplePlugin_externalFlush));
end
if((! 1'b0))begin
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusSimplePlugin_decodePc_flushed)begin
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if((! execute_arbitration_isStuck))begin
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0;
end
if(IBusSimplePlugin_decodePc_flushed)begin
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if((! memory_arbitration_isStuck))begin
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1;
end
if(IBusSimplePlugin_decodePc_flushed)begin
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if((! writeBack_arbitration_isStuck))begin
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2;
end
if(IBusSimplePlugin_decodePc_flushed)begin
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next;
IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_228_);
if(IBusSimplePlugin_iBusRsp_flush)begin
IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= IBusSimplePlugin_pending_next;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(_zz_184_)begin
if(_zz_185_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(_zz_186_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(_zz_187_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
if(CsrPlugin_pipelineLiberator_active)begin
if((! execute_arbitration_isStuck))begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if((! memory_arbitration_isStuck))begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if((! writeBack_arbitration_isStuck))begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump)begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(_zz_171_)begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(_zz_172_)begin
case(_zz_173_)
2'b11 : begin
CsrPlugin_mstatus_MPP <= (2'b00);
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_102_,{_zz_101_,_zz_100_}} != (3'b000)) || CsrPlugin_thirdPartyWake);
_zz_118_ <= 1'b0;
_zz_130_ <= (_zz_35_ && writeBack_arbitration_isFiring);
memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext;
memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext;
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_48_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
execute_arbitration_isValid <= 1'b0;
end
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
memory_arbitration_isValid <= 1'b0;
end
if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
writeBack_arbitration_isValid <= 1'b0;
end
if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_768)begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
CsrPlugin_mstatus_MPIE <= _zz_275_[0];
CsrPlugin_mstatus_MIE <= _zz_276_[0];
end
end
if(execute_CsrPlugin_csr_772)begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mie_MEIE <= _zz_278_[0];
CsrPlugin_mie_MTIE <= _zz_279_[0];
CsrPlugin_mie_MSIE <= _zz_280_[0];
end
end
end
end
always @ (posedge clk) begin
if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin
_zz_59_ <= IBusSimplePlugin_iBusRsp_stages_1_output_payload;
end
if(_zz_183_)begin
IBusSimplePlugin_decompressor_bufferData <= IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16];
end
if(IBusSimplePlugin_decompressor_output_ready)begin
_zz_88_ <= IBusSimplePlugin_decompressor_output_payload_pc;
_zz_89_ <= IBusSimplePlugin_decompressor_output_payload_rsp_error;
_zz_90_ <= IBusSimplePlugin_decompressor_output_payload_rsp_inst;
_zz_91_ <= IBusSimplePlugin_decompressor_output_payload_isRvc;
end
if(IBusSimplePlugin_injector_decodeInput_ready)begin
IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_decompressor_raw;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck)))
`else
if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
$display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend");
$finish;
end
`endif
`endif
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring)begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_184_)begin
if(_zz_185_)begin
CsrPlugin_interrupt_code <= (4'b0111);
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
end
if(_zz_186_)begin
CsrPlugin_interrupt_code <= (4'b0011);
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
end
if(_zz_187_)begin
CsrPlugin_interrupt_code <= (4'b1011);
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
end
end
if(_zz_171_)begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= decode_PC;
end
default : begin
end
endcase
end
_zz_131_ <= _zz_34_[11 : 7];
_zz_132_ <= _zz_33_;
if(_zz_168_)begin
if(_zz_170_)begin
memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 2);
memory_MulDivIterativePlugin_accumulator <= ({_zz_243_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 2);
end
end
if((memory_MulDivIterativePlugin_div_counter_value == 5'h10))begin
memory_MulDivIterativePlugin_div_done <= 1'b1;
end
if((! memory_arbitration_isStuck))begin
memory_MulDivIterativePlugin_div_done <= 1'b0;
end
if(_zz_169_)begin
if(_zz_181_)begin
memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_1_outNumerator;
memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_1_outRemainder;
if((memory_MulDivIterativePlugin_div_counter_value == 5'h10))begin
memory_MulDivIterativePlugin_div_result <= _zz_263_[31:0];
end
end
end
if(_zz_182_)begin
memory_MulDivIterativePlugin_accumulator <= 65'h0;
memory_MulDivIterativePlugin_rs1 <= ((_zz_142_ ? (~ _zz_143_) : _zz_143_) + _zz_269_);
memory_MulDivIterativePlugin_rs2 <= ((_zz_141_ ? (~ execute_RS2) : execute_RS2) + _zz_271_);
memory_MulDivIterativePlugin_div_needRevert <= ((_zz_142_ ^ (_zz_141_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS1 <= decode_RS1;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RVC <= decode_IS_RVC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ENV_CTRL <= _zz_24_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_ENV_CTRL <= _zz_21_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_ENV_CTRL <= _zz_19_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_CTRL <= _zz_17_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_PC <= decode_PC;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_PC <= _zz_28_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_PC <= memory_PC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BRANCH_CTRL <= _zz_14_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_44_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC1_CTRL <= _zz_11_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SHIFT_CTRL <= _zz_8_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_49_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2_CTRL <= _zz_5_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_2_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS2 <= decode_RS2;
end
if((! execute_arbitration_isStuck))begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if((! execute_arbitration_isStuck))begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if((! execute_arbitration_isStuck))begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if((! execute_arbitration_isStuck))begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if((! execute_arbitration_isStuck))begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(execute_CsrPlugin_csr_836)begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mip_MSIP <= _zz_277_[0];
end
end
if(execute_CsrPlugin_csr_832)begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0];
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O31AI_BEHAVIORAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_BEHAVIORAL_V |
//
// bsg_fifo_1r1w_small_hardened
//
// bsg_fifo with 1 read and 1 write, used for smaller fifos
// No bubble between packets, has 1-cycle latency
//
// This fifo instantiates bsg_mem_1r1w_sync memory, which has synchronous read
// Data writes into both sync_mem and w_data_bypass_reg when sync_mem is empty,
// so that it can be available on read side in next cycle.
// Only read from sync_mem when sync_mem is not empty
//
// input handshake protocol (based on ready_THEN_valid_p parameter):
// valid-and-ready or
// ready-then-valid
//
// output protocol is valid-yumi (like typical fifo)
// aka valid-then-ready
//
//
`include "bsg_defines.v"
module bsg_fifo_1r1w_small_hardened #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter ready_THEN_valid_p = 0
)
( input clk_i
, input reset_i
, input v_i
, output ready_o
, input [width_p-1:0] data_i
, output v_o
, output [width_p-1:0] data_o
, input yumi_i
);
wire deque = yumi_i;
wire v_o_tmp;
assign v_o = v_o_tmp;
// vivado bug prohibits declaring wire inside of generate block
wire enque;
logic ready_lo;
if (ready_THEN_valid_p)
begin: rtv
assign enque = v_i;
end
else
begin: rav
assign enque = v_i & ready_lo;
end
localparam ptr_width_lp = `BSG_SAFE_CLOG2(els_p);
// one read pointer, one write pointer;
logic [ptr_width_lp-1:0] rptr_r, wptr_r;
logic full, empty;
// rptr_n is one cycle earlier than rptr_r
logic [ptr_width_lp-1:0] rptr_n;
// avoid reading and writing same address in mem_1r1w_sync
logic [width_p-1:0] data_o_mem, data_o_reg;
logic read_write_same_addr_n;
logic write_bypass_r, write_bypass_n;
bsg_fifo_tracker #(.els_p(els_p)
) fts
(.clk_i
,.reset_i
,.enq_i (enque)
,.deq_i (deque)
,.wptr_r_o (wptr_r)
,.rptr_r_o (rptr_r)
,.rptr_n_o (rptr_n)
,.full_o (full)
,.empty_o (empty)
);
// sync read
bsg_mem_1r1w_sync #(.width_p (width_p)
,.els_p (els_p )
// MBT: this should be zero
,.read_write_same_addr_p(0)
,.disable_collision_warning_p(0)
,.harden_p(1)
) mem_1r1w_sync
(.clk_i
,.reset_i
,.w_v_i (enque )
,.w_addr_i (wptr_r )
,.w_data_i (data_i )
,.r_v_i (~read_write_same_addr_n)
,.r_addr_i (rptr_n )
,.r_data_o (data_o_mem)
);
// w_data bypass register, avoid reading and writing same address in memory
bsg_dff_en #(.width_p(width_p)) bypass_reg
(.clk_i
,.data_i(data_i)
,.en_i (write_bypass_n)
,.data_o(data_o_reg)
);
// Read from bypass register when read_write_same_addr happens last cycle
assign data_o = (write_bypass_r)? data_o_reg : data_o_mem;
// When fifo is empty, read_write_same_addr_n must be 1
//
// Proof: When empty==1, v_o==0, then yumi_i==0, deque==0,
// then rptr_n==rptr_r. Since rptr_r==wprt_r (definition of empty),
// rptr_n==wptr_r, so read_write_same_addr_n==1.
//
// As a result, (v_o_tmp & ~read_write_same_addr_n) is equivalent to (~read_write_same_addr_n).
assign read_write_same_addr_n = (wptr_r == rptr_n);
// When enque==1 and read/write address are same, write to bypass register
// A copy of data is written into mem_1r1w_sync in same cycle
assign write_bypass_n = enque & read_write_same_addr_n;
always_ff @(posedge clk_i)
write_bypass_r <= write_bypass_n;
// during reset, we keep ready low
// even though fifo is empty
//assign ready_lo = ~full & ~reset_i;
assign ready_lo = ~full;
assign ready_o = ready_lo;
assign v_o_tmp = ~empty;
//synopsys translate_off
always_ff @ (negedge clk_i)
begin
if (ready_THEN_valid_p & full & v_i & ~reset_i)
$display("%m error: enque full fifo at time %t", $time);
if (empty & yumi_i & ~reset_i)
$display("%m error: deque empty fifo at time %t", $time);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_small_hardened)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:32:24 04/24/2018
// Design Name:
// Module Name: sa1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sa1(
input RST,
input CLK,
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
// MMIO interface
//input ENABLE,
input SNES_READ,
input SNES_WRITE,
input SNES_RD_start,
input SNES_RD_end,
input SNES_WR_start,
input SNES_WR_end,
input SNES_cycle_end,
input [23:0] SNES_ADDR,
input [7:0] DATA_IN,
output DATA_ENABLE,
output [7:0] DATA_OUT,
// ROM interface
input ROM_BUS_RDY,
output ROM_BUS_RRQ,
output ROM_BUS_WRQ,
output ROM_BUS_WORD,
output [23:0] ROM_BUS_ADDR,
input [15:0] ROM_BUS_RDDATA,
output [15:0] ROM_BUS_WRDATA,
output ROM_HIT,
// RAM interface
input RAM_BUS_RDY,
output RAM_BUS_RRQ,
output RAM_BUS_WRQ,
output RAM_BUS_WORD,
output [23:0] RAM_BUS_ADDR,
input [7:0] RAM_BUS_RDDATA,
output [7:0] RAM_BUS_WRDATA,
output RAM_HIT,
// address map
output [4:0] BMAPS_SBM,
output [15:0] SNV,
output [15:0] SIV,
output SCNT_NVSW,
output SCNT_IVSW,
output DMA_CC1_EN,
output [11:0] XXB_OUT,
output [3:0] XXB_EN_OUT,
output IRQ,
input SPEED,
// State debug read interface
input [11:0] PGM_ADDR, // [11:0]
output [7:0] PGM_DATA, // [7:0]
// config interface
input [7:0] reg_group_in,
input [7:0] reg_index_in,
input [7:0] reg_value_in,
input [7:0] reg_invmask_in,
input reg_we_in,
input [7:0] reg_read_in,
output [7:0] config_data_out,
// config interface
output DBG
);
//-------------------------------------------------------------------
// NOTES
//-------------------------------------------------------------------
// This is a cycle-approximate implementation of the sa1 chip. The sa1
// is a 65c816 core running at ~10.74 MHz. It can serve as an off-load
// engine/accelerator or a peer to the host snes cpu.
//
// There are base 65c816 as well as custom features available to the sa1
// with varying levels of implementation. Several features have been left
// out in order to make development easier and fit basic functionality on
// the fpga.
//
// [x] full native 65c816 instruction set. (not fully debugged)
// [x] host and slave mmio support for reset and other basic functionality
// [x] host and slave access to bram (cart ram) and iram.
// [_] 65c816 emulation mode. (known holes in emulation execution)
// [x] dma/normal
// [x] dma/cc
// [x] host interrupts
// [x] host interrupt vectors
// [x] sa1 interrupts
// [_] counters
// [x] bcd mode/math (overflow likely not set correctly)
// [x] rom address mapping
// [x] ram address mapping
// [x] multiply/divide
// [x] mac support for multiply
// [_] full mdr support
// [x] variable length data/fixed
// [x] variable length data/auto
//-------------------------------------------------------------------
// DEFINES
//-------------------------------------------------------------------
//`define DEBUG
`define DEBUG_IRAM
`define DEBUG_MMIO
//`define DEBUG_EXT
//`define DEBUG_MMC
//`define DEBUG_EXE
//`define DEBUG_DMA
`define DMA_ENABLE
`define DMA_NORMAL_ENABLE
`define DMA_TYPE1_ENABLE
`define DMA_TYPE2_ENABLE
`define VBD_ENABLE
`define BCD_ENABLE
`define EXE_FAST_FETCH
`define EXE_FAST_MOVE
// temporaries
integer i;
wire pipeline_advance;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
`define BCD_A_CARRY(m,c,s) (~m & (c | (s[3] & (s[2] | s[1])))) // add 6
`define BCD_S_CARRY(m,c,s) (m & ~c) // sub 6
function [4:0] bcd_adder;
input mode;
input carry;
input [3:0] sum;
begin
// mode=0 (add) +6 (5'b00110) if > 0x09
// mode=1 (sub) -6 (5'b11010) if < 0x10
bcd_adder = {`BCD_S_CARRY(mode,carry,sum),`BCD_S_CARRY(mode,carry,sum),`BCD_A_CARRY(mode,carry,sum),(`BCD_A_CARRY(mode,carry,sum) | `BCD_S_CARRY(mode,carry,sum)),1'b0};
end
endfunction
//-------------------------------------------------------------------
// INPUTS
//-------------------------------------------------------------------
reg [7:0] data_in_r;
reg [23:0] addr_in_r;
//reg enable_r;
reg [11:0] pgm_addr_r;
reg [23:0] SAVERAM_MASK_r; initial SAVERAM_MASK_r = 0;
reg [23:0] ROM_MASK_r; initial ROM_MASK_r = 0;
// TODO: battery backed iram support doesn't fit. For now, only let the snes access it.
reg iram_battery_r; initial iram_battery_r = 0;
always @(posedge CLK) begin
data_in_r <= DATA_IN;
addr_in_r <= SNES_ADDR;
//enable_r <= ENABLE;
pgm_addr_r <= PGM_ADDR;
SAVERAM_MASK_r <= SAVERAM_MASK;
ROM_MASK_r <= ROM_MASK;
// battery backed iram is encoded as a mask of 1 by the firmware.
iram_battery_r <= ~SAVERAM_MASK_r[1] & SAVERAM_MASK_r[0];
end
//-------------------------------------------------------------------
// ADDRESS MAP
//-------------------------------------------------------------------
wire sw46;
wire [6:0] cbm;
wire bbf;
reg [2:0] xxb[3:0];
wire [3:0] xxb_en;
// address map tests
`define IS_ROM(a) ((&a[23:22]) | (~a[22] & a[15])) // 00-3F/80-BF:8000-FFFF, C0-FF:0000-FFFF
//`define IS_SA1_IRAM(a) (~iram_battery_r & ~a[22] & ~a[15] & ~a[14] & ~^a[13:12] & ~a[11]) // 00-3F/80-BF:0/3000-0/37FF
`define IS_SA1_IRAM(a) (~a[22] & ~a[15] & ~a[14] & ~^a[13:12] & ~a[11]) // 00-3F/80-BF:0/3000-0/37FF
`define IS_CPU_IRAM(a) (~iram_battery_r & ~a[22] & ~a[15] & ~a[14] & &a[13:12] & ~a[11]) // 00-3F/80-BF:3000-37FF
//`define IS_SA1_BRAM(a) ((iram_battery_r & `IS_SA1_IRAM(a)) | (~sw46 & ~a[22] & ~a[15] & &a[14:13]) | (~a[23] & a[22] & ~a[21] & ~a[20])) // 00-3F/80-BF:6000-7FFF, 40-4F:0000-FFFF
`define IS_SA1_BRAM(a) ((~sw46 & ~a[22] & ~a[15] & &a[14:13]) | (~a[23] & a[22] & ~a[21] & ~a[20])) // 00-3F/80-BF:6000-7FFF, 40-4F:0000-FFFF
// NOTE: the following is only used for cc1 DMA
`define IS_CPU_BRAM(a) ((~a[22] & ~a[15] & &a[14:13]) | (~a[23] & a[22] & ~a[21] & ~a[20])) // 00-3F/80-BF:6000-7FFF, 40-4F:0000-FFFF
`define IS_MMIO(a) (~a[22] & ~a[15] & ~a[14] & a[13] & ~a[12] & ~a[11] & ~a[10] & a[9]) // 00-3F/80-BF:2200-23FF
`define IS_SA1_PRAM(a) ((sw46 & ~a[22] & ~a[15] & &a[14:13]) | (~a[23] & a[22] & a[21] & ~a[20])) // 00-3F/80-BF:6000-7FFF, 60-6F:0000-FFFF
`define MAP_ROM(a) ((a[22] ? {1'b0, xxb[a[21:20]], a[19:0]} : {1'b0, xxb_en[{a[23],a[21]}] ? xxb[{a[23],a[21]}] : {1'b0,a[23],a[21]}, a[20:16], a[14:0]}) & ROM_MASK_r)
`define MAP_IRAM(a) (a[10:0])
`define MAP_MMIO(a) (a[8:0])
//`define MAP_BRAM(a) (iram_battery_r ? `MAP_IRAM(a) : ((a[22] ? a[19:0] : {cbm[4:0],a[12:0]}) & SAVERAM_MASK_r))
`define MAP_BRAM(a) ((a[22] ? a[19:0] : {cbm[4:0],a[12:0]}) & SAVERAM_MASK_r)
`define MAP_PRAM(a) ((a[22] ? (bbf ? a[19:2] : a[19:1]) : (bbf ? {cbm[6:0],a[12:2]} : {cbm[6:0],a[12:1]})) & SAVERAM_MASK_r)
//-------------------------------------------------------------------
// PARAMETERS
//-------------------------------------------------------------------
parameter
// write
ADDR_CCNT = 9'h000,
ADDR_SIE = 9'h001,
ADDR_SIC = 9'h002,
ADDR_CRV = 9'h003, // $2
//
ADDR_CNV = 9'h005, // $2
//
ADDR_CIV = 9'h007, // $2
//
ADDR_SCNT = 9'h009,
ADDR_CIE = 9'h00A,
ADDR_CIC = 9'h00B,
ADDR_SNV = 9'h00C, // $2
//
ADDR_SIV = 9'h00E, // $2
//
ADDR_TMC = 9'h010,
ADDR_CTR = 9'h011,
ADDR_HCNT = 9'h012, // $2
//
ADDR_VCNT = 9'h014, // $2
//
ADDR_CXB = 9'h020,
ADDR_DXB = 9'h021,
ADDR_EXB = 9'h022,
ADDR_FXB = 9'h023,
ADDR_BMAPS = 9'h024,
ADDR_BMAP = 9'h025,
ADDR_SWBE = 9'h026,
ADDR_CWBE = 9'h027,
ADDR_BWPA = 9'h028,
ADDR_SIWP = 9'h029,
ADDR_CIWP = 9'h02A,
//
ADDR_DCNT = 9'h030,
ADDR_CDMA = 9'h031,
ADDR_DSA = 9'h032, // $3
//
//
ADDR_DDA = 9'h035, // $3
//
//
ADDR_DTC = 9'h038,
//
ADDR_BBF = 9'h03F,
ADDR_BRF = 9'h040, // $10
ADDR_BRF0 = 9'h040,
ADDR_BRF1 = 9'h041,
ADDR_BRF2 = 9'h042,
ADDR_BRF3 = 9'h043,
ADDR_BRF4 = 9'h044,
ADDR_BRF5 = 9'h045,
ADDR_BRF6 = 9'h046,
ADDR_BRF7 = 9'h047,
ADDR_BRF8 = 9'h048,
ADDR_BRF9 = 9'h049,
ADDR_BRFA = 9'h04A,
ADDR_BRFB = 9'h04B,
ADDR_BRFC = 9'h04C,
ADDR_BRFD = 9'h04D,
ADDR_BRFE = 9'h04E,
ADDR_BRFF = 9'h04F,
ADDR_MCNT = 9'h050,
ADDR_MA = 9'h051, // $2
//
ADDR_MB = 9'h053, // $2
//
ADDR_VBD = 9'h058,
ADDR_VDA = 9'h059 // $3
;
parameter
ADDR_SFR = 9'h100,
ADDR_CFR = 9'h101,
ADDR_HCR = 9'h102, // $2
ADDR_VCR = 9'h104, // $2
ADDR_MR = 9'h106, // $5
ADDR_OF = 9'h10B,
ADDR_VDP = 9'h10C, // $2
ADDR_VC = 9'h10E
;
//-------------------------------------------------------------------
// CONFIG
//-------------------------------------------------------------------
// C0 Control
// 0 - Go (1)
// 1 - MatchFullInst
// C1 StepControl
// [7:0] StepCount
// C2 BreakpointControl
// 0 - BreakOnInstRdByteWatch
// 1 - BreakOnDataRdByteWatch
// 2 - BreakOnDataWrByteWatch
// 3 - BreakOnInstRdAddrWatch
// 4 - BreakOnDataRdAddrWatch
// 5 - BreakOnDataWrAddrWatch
// 6 - BreakOnStop
// 7 - BreakOnError
// C3 ???
// C4 DataWatch
// [7:0] DataWatch
// C5-C7 AddrWatch (little endian)
// [23:0] AddrWatch
// breakpoint state
`ifdef DEBUG
reg brk_inst_rd_byte; initial brk_inst_rd_byte = 0;
reg brk_data_rd_byte; initial brk_data_rd_byte = 0;
reg brk_data_wr_byte; initial brk_data_wr_byte = 0;
reg brk_inst_rd_addr; initial brk_inst_rd_addr = 0;
reg brk_data_rd_addr; initial brk_data_rd_addr = 0;
reg brk_data_wr_addr; initial brk_data_wr_addr = 0;
reg brk_data; initial brk_data = 0;
reg brk_stop; initial brk_stop = 0;
reg brk_error; initial brk_error = 0;
parameter CONFIG_REGISTERS = 8;
reg [7:0] config_r[CONFIG_REGISTERS-1:0]; initial for (i = 0; i < CONFIG_REGISTERS; i = i + 1) config_r[i] = 8'h00;
always @(posedge CLK) begin
if (RST) begin
//for (i = 0; i < CONFIG_REGISTERS; i = i + 1) config_r[i] <= 8'h00;
end
else if (reg_we_in && (reg_group_in == 8'h03)) begin
if (reg_index_in < CONFIG_REGISTERS) config_r[reg_index_in] <= (config_r[reg_index_in] & reg_invmask_in) | (reg_value_in & ~reg_invmask_in);
end
else begin
config_r[0][0] <= config_r[0][0] & ~|(config_r[2] & {brk_error,brk_stop,brk_data_wr_addr,brk_data_rd_addr,brk_inst_rd_addr,brk_data_wr_byte,brk_data_rd_byte,brk_inst_rd_byte});
end
end
assign config_data_out = config_r[reg_read_in];
assign CONFIG_CONTROL_ENABLED = config_r[0][0];
assign CONFIG_CONTROL_MATCHPARTINST = config_r[0][1];
wire [7:0] CONFIG_STEP_COUNT = config_r[1];
wire [7:0] CONFIG_DATA_WATCH = config_r[4];
wire [23:0] CONFIG_ADDR_WATCH = {config_r[7],config_r[6],config_r[5]};
`else
wire [7:0] CONFIG_STEP_COUNT = 0;
assign CONFIG_CONTROL_ENABLED = 1;
assign CONFIG_CONTROL_MATCHPARTINST = 0;
`endif
//-------------------------------------------------------------------
// FLOPS
//-------------------------------------------------------------------
reg [23:0] debug_inst_addr_r;
reg [23:0] debug_inst_addr_prev_r;
reg [2:0] sa1_cycle_r; initial sa1_cycle_r = 0;
reg sa1_clock_en; initial sa1_clock_en = 0;
// step counter for pipelines
reg [7:0] stepcnt_r; initial stepcnt_r = 0;
reg step_r; initial step_r = 0;
wire sa1_clock_en_pre = sa1_cycle_r == 6;
always @(posedge CLK) begin
if (RST) begin
sa1_cycle_r <= 0;
sa1_clock_en <= 0;
end
else begin
sa1_cycle_r <= sa1_cycle_r + 1;
sa1_clock_en <= sa1_clock_en_pre;
end
end
reg [31:0] sa1_cycle_cnt_r; initial sa1_cycle_cnt_r = 0;
//-------------------------------------------------------------------
// STATE
//-------------------------------------------------------------------
// register state
reg [7:0] PBR_r; initial PBR_r = 0;
reg [15:0] PC_r; initial PC_r = 0;
reg [15:0] A_r; initial A_r = 0;
reg [15:0] X_r; initial X_r = 0;
reg [15:0] Y_r; initial Y_r = 0;
reg [15:0] S_r; initial S_r = 16'h01FF;
reg [15:0] D_r; initial D_r = 0;
reg [7:0] DBR_r; initial DBR_r = 0;
reg [7:0] P_r; initial P_r = 8'h34;
reg E_r; initial E_r = 1;
reg WAI_r; initial WAI_r = 0;
// write-only MMIO
reg [7:0] CCNT_r; initial CCNT_r = 8'h20;
reg [7:0] SIE_r; initial SIE_r = 0;
reg [7:0] SIC_r; initial SIC_r = 0;
reg [15:0] CRV_r; initial CRV_r = 0;
reg [15:0] CNV_r; initial CNV_r = 0;
reg [15:0] CIV_r; initial CIV_r = 0;
reg [7:0] SCNT_r; initial SCNT_r = 0;
reg [7:0] CIE_r; initial CIE_r = 0;
reg [7:0] CIC_r; initial CIC_r = 0;
reg [15:0] SNV_r; initial SNV_r = 0;
reg [15:0] SIV_r; initial SIV_r = 0;
reg [7:0] TMC_r; initial TMC_r = 0;
reg [7:0] CTR_r; initial CTR_r = 0;
reg [15:0] HCNT_r; initial HCNT_r = 0;
reg [15:0] VCNT_r; initial VCNT_r = 0;
reg [7:0] CXB_r; initial CXB_r = 0;
reg [7:0] DXB_r; initial DXB_r = 1;
reg [7:0] EXB_r; initial EXB_r = 2;
reg [7:0] FXB_r; initial FXB_r = 3;
reg [7:0] BMAPS_r;initial BMAPS_r= 0;
reg [7:0] BMAP_r; initial BMAP_r = 0;
reg [7:0] SWBE_r; initial SWBE_r = 0;
reg [7:0] CWBE_r; initial CWBE_r = 0;
reg [7:0] BWPA_r; initial BWPA_r = 8'hFF;
reg [7:0] SIWP_r; initial SIWP_r = 0;
reg [7:0] CIWP_r; initial CIWP_r = 0;
reg [7:0] DCNT_r; initial DCNT_r = 0;
reg [7:0] CDMA_r; initial CDMA_r = 0;
reg [23:0] DSA_r; initial DSA_r = 0;
reg [23:0] DDA_r; initial DDA_r = 0;
reg [15:0] DTC_r; initial DTC_r = 0;
reg [7:0] BBF_r; initial BBF_r = 0;
reg [7:0] BRF_r[15:0]; initial for (i = 0; i < 16; i = i + 1) BRF_r[i] = 0;
reg [7:0] MCNT_r; initial MCNT_r = 0;
reg [15:0] MA_r; initial MA_r = 0;
reg [15:0] MB_r; initial MB_r = 0;
reg [7:0] VBD_r; initial VBD_r = 0;
reg [23:0] VDA_r; initial VDA_r = 0;
// read-only through MMIO
reg [7:0] SFR_r; initial SFR_r = 0;
reg [7:0] CFR_r; initial CFR_r = 0;
reg [15:0] HCR_r; initial HCR_r = 0;
reg [15:0] VCR_r; initial VCR_r = 0;
reg [39:0] MR_r; initial MR_r = 0;
reg [7:0] OF_r; initial OF_r = 0;
reg [15:0] VDP_r; initial VDP_r = 0;
reg [7:0] VC_r; initial VC_r = 0;
// internal state
reg [15:0] hcounter_r; initial hcounter_r = 0;
reg [15:0] vcounter_r; initial vcounter_r = 0;
// Important parameters
`define P_C 0
`define P_Z 1
`define P_I 2
`define P_D 3
`define P_X 4
`define P_M 5
`define P_V 6
`define P_N 7
`define P_B 4
`define CCNT_SMEG 3:0
`define CCNT_SA1_NMI 4
`define CCNT_SA1_RESB 5
`define CCNT_SA1_RDYB 6
`define CCNT_SA1_IRQ 7
`define SIE_DMA_IRQEN 5
`define SIE_CPU_IRQEN 7
`define SIC_DMA_IRQCL 5
`define SIC_CPU_IRQCL 7
`define SCNT_CMEG 3:0
`define SCNT_NVSW 4
`define SCNT_IVSW 6
`define SCNT_CPU_IRQ 7
`define CIE_SA1_NMIEN 4
`define CIE_DMA_IRQEN 5
`define CIE_TMR_IRQEN 6
`define CIE_SA1_IRQEN 7
`define CIC_SA1_NMICL 4
`define CIC_DMA_IRQCL 5
`define CIC_TMR_IRQCL 6
`define CIC_SA1_IRQCL 7
`define TMC_HEN 0
`define TMC_VEN 1
`define TMC_HVSELB 7
`define CXB_CB 2:0
`define CXB_CBMODE 7
`define DXB_DB 2:0
`define DXB_DBMODE 7
`define EXB_EB 2:0
`define EXB_EBMODE 7
`define FXB_FB 2:0
`define FXB_FBMODE 7
`define BMAPS_SBM 4:0
`define BMAP_CBM 6:0
`define BMAP_SW46 7
`define SWBE_SWEN 7
`define CWBE_CWEN 7
`define BWPA_BWP 3:0
`define DCNT_SD 1:0
`define DCNT_DD 2
`define DCNT_CDSEL 4
`define DCNT_CDEN 5
`define DCNT_DPRIO 6
`define DCNT_DMAEN 7
`define CDMA_DMACB 1:0
`define CDMA_DMASIZE 4:2
`define CDMA_CHDEND 7
`define BBF_BBF 7
`define MCNT_MD 0
`define MCNT_ACM 1
`define VBD_VB 3:0
`define VBD_HL 7
`define SFR_DMA_IRQFL 5
`define SFR_CPU_IRQFL 7
`define CFR_SA1_NMIFL 4
`define CFR_DMA_IRQFL 5
`define CFR_TMR_IRQFL 6
`define CFR_SA1_IRQFL 7
`define DCNT_SRC 1:0
assign sw46 = BMAP_r[`BMAP_SW46];
assign cbm = BMAP_r[`BMAP_CBM];
assign bbf = BBF_r[`BBF_BBF];
always @(*) begin
xxb[0] = CXB_r[`CXB_CB];
xxb[1] = DXB_r[`DXB_DB];
xxb[2] = EXB_r[`EXB_EB];
xxb[3] = FXB_r[`FXB_FB];
end
assign xxb_en = {FXB_r[`FXB_FBMODE], EXB_r[`EXB_EBMODE], DXB_r[`DXB_DBMODE], CXB_r[`CXB_CBMODE]};
//-------------------------------------------------------------------
// PIPELINE IO
//-------------------------------------------------------------------
// mmc interface
reg exe_mmc_rd_r; initial exe_mmc_rd_r = 0;
reg exe_mmc_wr_r; initial exe_mmc_wr_r = 0;
reg exe_mmc_dpe_r; initial exe_mmc_dpe_r = 0;
reg [1:0] exe_mmc_byte_total_r; initial exe_mmc_byte_total_r = 0;
reg exe_mmc_long_r; initial exe_mmc_long_r = 0;
reg [31:0] exe_mmc_data_r;
reg dma_mmc_rd_rom_r; initial dma_mmc_rd_rom_r = 0;
reg dma_mmc_rd_bram_r; initial dma_mmc_rd_bram_r = 0;
reg dma_mmc_wr_bram_r; initial dma_mmc_wr_bram_r = 0;
reg dma_mmc_rd_iram_r; initial dma_mmc_rd_iram_r = 0;
reg dma_mmc_wr_iram_r; initial dma_mmc_wr_iram_r = 0;
reg [23:0] dma_mmc_rd_addr_r;
reg [23:0] dma_mmc_wr_addr_r;
reg [7:0] dma_mmc_data_r;
reg vbd_mmc_rd_r; initial vbd_mmc_rd_r = 0;
reg [23:0] vbd_mmc_addr_r;
//-------------------------------------------------------------------
// REGISTER/MMIO ACCESS
//-------------------------------------------------------------------
reg snes_data_enable_r; initial snes_data_enable_r = 0;
reg [7:0] data_out_r;
reg [7:0] snes_data_out_r; initial snes_data_out_r = 0;
reg [10:0] snes_iram_addr_r;
reg snes_writebuf_val_r; initial snes_writebuf_val_r = 0;
reg snes_writebuf_iram_r; initial snes_writebuf_iram_r = 0;
reg [10:0] snes_writebuf_addr_r;
reg [7:0] snes_writebuf_data_r;
reg [7:0] snes_writebuf_iram_data_r;
reg snes_mmio_active_r; initial snes_mmio_active_r = 0;
reg snes_iram_active_r; initial snes_iram_active_r = 0;
reg snes_readbuf_val_r; initial snes_readbuf_val_r = 0;
reg snes_readbuf_iram_r; initial snes_readbuf_iram_r = 0;
reg [8:0] snes_readbuf_mmio_addr_r;
reg snes_mmio_done_r; initial snes_mmio_done_r = 0;
wire [7:0] snes_iram_out;
reg [7:0] snes_iram_data_r;
reg [1:0] snes_mmio_delay_r; initial snes_mmio_delay_r = 0;
reg sa1_readbuf_val_r; initial sa1_readbuf_val_r = 0;
wire [8:0] sa1_mmio_addr;
wire [7:0] sa1_mmio_data;
wire sa1_mmio_write;
wire sa1_mmio_read;
reg [1:0] sa1_mmio_read_r; initial sa1_mmio_read_r = 0;
wire dma_mmc_cc1_en;
wire [6:0] dma_mmc_cc1_mask;
always @(posedge CLK) begin
// iram sees the address early so data is available.
// TODO: can this be single bit now?
// XXX if (~SNES_READ) snes_data_out_r <= snes_iram_active_r ? snes_iram_out : data_out_r;
// XXX if (snes_iram_active_r) snes_data_out_r <= snes_iram_out;
// XXX if (~snes_mmio_delay_r[1] & ~snes_mmio_done_r) snes_data_out_r <= snes_readbuf_iram_r ? snes_iram_data_r : data_out_r;
if (~snes_mmio_delay_r[1] & ~snes_mmio_done_r) snes_data_out_r <= snes_readbuf_iram_r ? snes_iram_out : data_out_r;
if (RST) begin
snes_data_enable_r <= 0;
data_out_r <= 0;
snes_writebuf_val_r <= 0;
snes_writebuf_iram_r <= 0;
snes_readbuf_val_r <= 0;
snes_readbuf_iram_r <= 0;
snes_mmio_active_r <= 0;
snes_iram_active_r <= 0;
snes_mmio_delay_r <= 0;
snes_mmio_done_r <= 0;
sa1_readbuf_val_r <= 0;
sa1_mmio_read_r <= 0;
// initialize registers on cart reset
CCNT_r <= 8'h20;
SIE_r <= 0;
SIC_r <= 0;
CRV_r <= 0;
CNV_r <= 0;
CIV_r <= 0;
SCNT_r <= 0;
CIE_r <= 0;
CIC_r <= 0;
SNV_r <= 0;
SIV_r <= 0;
TMC_r <= 0;
CTR_r <= 0;
//HCNT_r <= 0;
//VCNT_r <= 0;
CXB_r <= 0;
DXB_r <= 1;
EXB_r <= 2;
FXB_r <= 3;
BMAPS_r<= 0;
BMAP_r <= 0;
SWBE_r <= 0;
CWBE_r <= 0;
BWPA_r <= 8'hFF;
SIWP_r <= 0;
CIWP_r <= 0;
DCNT_r <= 0;
CDMA_r <= 0;
DSA_r <= 0;
//DDA_r <= 0;
DTC_r <= 0;
BBF_r <= 0;
//for (i = 0; i < 16; i = i + 1) BRF_r[i] <= 0;
MCNT_r <= 0;
MA_r <= 0;
MB_r <= 0;
VBD_r <= 0;
//VDA_r <= 0;
// DMA bit handled by DMA state machine
{SFR_r[7:6],SFR_r[4:0]} <= 0;
{CFR_r[7:6],CFR_r[4:0]} <= 0;
HCR_r <= 0;
VCR_r <= 0;
//MR_r <= 0;
//OF_r <= 0;
//VDP_r <= 0;
//VC_r <= 0;
end
else begin
sa1_mmio_read_r <= {sa1_mmio_read_r[0], sa1_mmio_read};
snes_mmio_delay_r[1:0] <= {snes_mmio_delay_r[0],snes_readbuf_val_r|snes_readbuf_iram_r};
snes_mmio_active_r <= `IS_MMIO(addr_in_r);
snes_iram_active_r <= `IS_CPU_IRAM(addr_in_r) | (`IS_CPU_BRAM(addr_in_r) & dma_mmc_cc1_en);
// Register Read
if (~SNES_READ & snes_mmio_active_r & ~snes_mmio_done_r) begin
snes_readbuf_val_r <= 1;
snes_readbuf_mmio_addr_r <= addr_in_r[8:0];
snes_mmio_done_r <= snes_mmio_delay_r[0];
sa1_readbuf_val_r <= 0;
end
else begin
snes_readbuf_val_r <= 0;
sa1_readbuf_val_r <= sa1_mmio_read;
if (SNES_READ) snes_mmio_done_r <= 0;
snes_readbuf_mmio_addr_r <= sa1_mmio_addr;
end
// "0" SNES_READ_IN
// 1 SNES_READ[0]
// 2 SNES_READ[1] -> ~SNES_READ
// 3 snes_readbuf_iram_r/addr
// 4 iram performs read
// 5 iram_out
// 6 snes_data_out_r
if (~SNES_READ & snes_iram_active_r) begin
snes_readbuf_iram_r <= 1;
end
else begin
snes_readbuf_iram_r <= 0;
end
// set both data and oe enable here
snes_data_enable_r <= (snes_iram_active_r & ~SNES_READ) | ((snes_iram_active_r | snes_mmio_active_r) & ~SNES_WRITE) | snes_mmio_delay_r[1] | snes_mmio_done_r;
// XXX snes_data_enable_r <= ((snes_iram_active | snes_mmio_active_r) & (~SNES_WRITE | ~SNES_READ));
// XXX snes_data_enable_r <= ((snes_iram_active_r | snes_mmio_active_r) & ~SNES_WRITE) | snes_mmio_delay_r[1] | snes_mmio_done_r;
// get address as early as possible so the read data is available when SNES_READ asserts
snes_iram_addr_r <= (`IS_CPU_BRAM(addr_in_r) & dma_mmc_cc1_en) ? {DDA_r[10:7],(DDA_r[6:0] & ~dma_mmc_cc1_mask) | (addr_in_r[6:0] & dma_mmc_cc1_mask)} : addr_in_r[10:0];
if (snes_readbuf_val_r | sa1_readbuf_val_r) begin
case (snes_readbuf_mmio_addr_r[8:0])
ADDR_SFR : data_out_r <= {SFR_r[`SFR_CPU_IRQFL], SCNT_r[`SCNT_IVSW], SFR_r[`SFR_DMA_IRQFL], SCNT_r[`SCNT_NVSW], SCNT_r[`SCNT_CMEG]};
ADDR_CFR : data_out_r <= {CFR_r[`CFR_SA1_IRQFL], CFR_r[`CFR_TMR_IRQFL], CFR_r[`CFR_DMA_IRQFL], CFR_r[`CFR_SA1_NMIFL], CCNT_r[`CCNT_SMEG]};
//ADDR_HCR : if (~data_enable_r) begin data_out_r <= hcounter_r[9:2]; HCR_r <= {2'h0,hcounter_r[15:2]}; VCR_r <= vcounter_r; end
//ADDR_HCR+1: data_out_r <= HCR_r[15:8];
//ADDR_VCR : data_out_r <= VCR_r[7:0];
//ADDR_VCR+1: data_out_r <= VCR_r[15:8];
ADDR_MR : data_out_r <= MR_r[7:0];
ADDR_MR+1 : data_out_r <= MR_r[15:8];
ADDR_MR+2 : data_out_r <= MR_r[23:16];
ADDR_MR+3 : data_out_r <= MR_r[31:24];
ADDR_MR+4 : data_out_r <= MR_r[39:32];
ADDR_OF : data_out_r <= OF_r;
ADDR_VDP : data_out_r <= VDP_r[7:0];
ADDR_VDP+1: data_out_r <= VDP_r[15:8];
ADDR_VC : data_out_r <= VC_r;
endcase
end
if (snes_readbuf_iram_r) begin
snes_iram_data_r <= snes_iram_out;
end
// Register Write Buffer.
if (SNES_WR_end & snes_mmio_active_r) begin
snes_writebuf_val_r <= 1;
snes_writebuf_addr_r <= {2'h0,addr_in_r[8:0]};
snes_writebuf_data_r <= data_in_r;
end
else begin
snes_writebuf_val_r <= sa1_mmio_write;
snes_writebuf_addr_r <= {2'h0,sa1_mmio_addr};
snes_writebuf_data_r <= sa1_mmio_data;
end
if (SNES_WR_end & `IS_CPU_IRAM(addr_in_r)) begin
snes_writebuf_iram_r <= 1;
snes_writebuf_iram_data_r <= data_in_r;
end
else begin
snes_writebuf_iram_r <= 0;
end
// TODO: can we move the interrupt controller logic outside of the MMIO operations to reduce code size and complexity?
if (snes_writebuf_val_r) begin
case (snes_writebuf_addr_r[8:0])
ADDR_CCNT : begin // 8'h00,
CCNT_r <= snes_writebuf_data_r;
if (snes_writebuf_data_r[`CCNT_SA1_IRQ]) begin
CFR_r[`CFR_SA1_IRQFL] <= 1;
if (CIE_r[`CIE_SA1_IRQEN]) CIC_r[`CIC_SA1_IRQCL] <= 0;
end
if (snes_writebuf_data_r[`CCNT_SA1_NMI]) begin
CFR_r[`CFR_SA1_NMIFL] <= 1;
if (CIE_r[`CIE_SA1_NMIEN]) CIC_r[`CIC_SA1_NMICL] <= 0;
end
end
ADDR_SIE : begin // 8'h01,
{SIE_r[`SIE_CPU_IRQEN],SIE_r[`SIE_DMA_IRQEN]} <= {snes_writebuf_data_r[`SIE_CPU_IRQEN],snes_writebuf_data_r[`SIE_DMA_IRQEN]};
if (~SIE_r[`SIE_CPU_IRQEN] & snes_writebuf_data_r[`SIE_CPU_IRQEN] & SFR_r[`SFR_CPU_IRQFL]) begin
SIC_r[`SIC_CPU_IRQCL] <= 0;
end
if (~SIE_r[`SIE_DMA_IRQEN] & snes_writebuf_data_r[`SIE_DMA_IRQEN] & SFR_r[`SFR_DMA_IRQFL]) begin
SIC_r[`SIC_DMA_IRQCL] <= 0;
end
end
ADDR_SIC : begin // 8'h02,
{SIC_r[`SIC_CPU_IRQCL],SIC_r[`SIC_DMA_IRQCL]} <= {snes_writebuf_data_r[`SIC_CPU_IRQCL],snes_writebuf_data_r[`SIC_DMA_IRQCL]};
//if (snes_writebuf_data_r[`SIC_DMA_IRQCL]) SFR_r[`SFR_DMA_IRQFL] <= 0;
if (snes_writebuf_data_r[`SIC_CPU_IRQCL]) SFR_r[`SFR_CPU_IRQFL] <= 0;
end
ADDR_CRV : CRV_r[7:0] <= snes_writebuf_data_r; // 8'h03, // $2
ADDR_CRV+1 : CRV_r[15:8] <= snes_writebuf_data_r; // 8'h03, // $2
ADDR_CNV : CNV_r[7:0] <= snes_writebuf_data_r; // 8'h05, // $2
ADDR_CNV+1 : CNV_r[15:8] <= snes_writebuf_data_r; // 8'h05, // $2
ADDR_CIV : CIV_r[7:0] <= snes_writebuf_data_r; // 8'h07, // $2
ADDR_CIV+1 : CIV_r[15:8] <= snes_writebuf_data_r; // 8'h07, // $2
ADDR_SCNT : begin // 8'h09,
{SCNT_r[7:6],SCNT_r[4:0]} <= {snes_writebuf_data_r[7:6],snes_writebuf_data_r[4:0]};
if (snes_writebuf_data_r[`SCNT_CPU_IRQ]) begin
SFR_r[`SFR_CPU_IRQFL] <= 1;
if (SIE_r[`SIE_CPU_IRQEN]) begin
SIC_r[`SIC_CPU_IRQCL] <= 0;
end
end
end
ADDR_CIE : begin // 8'h0A,
CIE_r[7:4] <= snes_writebuf_data_r[7:4];
if (~CIE_r[`CIE_SA1_IRQEN] & snes_writebuf_data_r[`CIE_SA1_IRQEN] & CFR_r[`CFR_SA1_IRQFL]) CIC_r[`CIC_SA1_IRQCL] <= 0;
if (~CIE_r[`CIE_TMR_IRQEN] & snes_writebuf_data_r[`CIE_TMR_IRQEN] & CFR_r[`CFR_TMR_IRQFL]) CIC_r[`CIC_TMR_IRQCL] <= 0;
if (~CIE_r[`CIE_DMA_IRQEN] & snes_writebuf_data_r[`CIE_DMA_IRQEN] & CFR_r[`CFR_DMA_IRQFL]) CIC_r[`CIC_DMA_IRQCL] <= 0;
if (~CIE_r[`CIE_SA1_NMIEN] & snes_writebuf_data_r[`CIE_SA1_NMIEN] & CFR_r[`CFR_SA1_NMIFL]) CIC_r[`CIC_SA1_NMICL] <= 0;
end
ADDR_CIC : begin // 8'h0B,
CIC_r[7:4] <= snes_writebuf_data_r[7:4];
if (snes_writebuf_data_r[`CIC_SA1_IRQCL]) CFR_r[`CFR_SA1_IRQFL] <= 0;
if (snes_writebuf_data_r[`CIC_TMR_IRQCL]) CFR_r[`CFR_TMR_IRQFL] <= 0;
//if (snes_writebuf_data_r[`CIC_DMA_IRQCL]) CFR_r[`CFR_DMA_IRQFL] <= 0;
if (snes_writebuf_data_r[`CIC_SA1_NMICL]) CFR_r[`CFR_SA1_NMIFL] <= 0;
end
ADDR_SNV : SNV_r[7:0] <= snes_writebuf_data_r; // 8'h0C, // $2
ADDR_SNV+1 : SNV_r[15:8] <= snes_writebuf_data_r; // 8'h0C, // $2
ADDR_SIV : SIV_r[7:0] <= snes_writebuf_data_r; // 8'h0E, // $2
ADDR_SIV+1 : SIV_r[15:8] <= snes_writebuf_data_r; // 8'h0E, // $2
ADDR_TMC : {TMC_r[`TMC_HVSELB],TMC_r[`TMC_VEN],TMC_r[`TMC_HEN]} <= {snes_writebuf_data_r[`TMC_HVSELB],snes_writebuf_data_r[`TMC_VEN],snes_writebuf_data_r[`TMC_HEN]}; // 8'h10,
//ADDR_CTR : // TODO: reset counters. Probably needs to be moved outside of this code // 8'h11,
//ADDR_HCNT : HCNT_r[7:0] <= snes_writebuf_data_r; // 8'h12, // $2
//ADDR_HCNT+1: HCNT_r[15:8] <= snes_writebuf_data_r; // 8'h12, // $2
//ADDR_VCNT : VCNT_r[7:0] <= snes_writebuf_data_r; // 8'h14, // $2
//ADDR_VCNT+1: VCNT_r[15:8] <= snes_writebuf_data_r; // 8'h14, // $2
ADDR_CXB : {CXB_r[`CXB_CBMODE],CXB_r[`CXB_CB]} <= {snes_writebuf_data_r[`CXB_CBMODE],snes_writebuf_data_r[`CXB_CB]}; // 8'h20,
ADDR_DXB : {DXB_r[`DXB_DBMODE],DXB_r[`DXB_DB]} <= {snes_writebuf_data_r[`DXB_DBMODE],snes_writebuf_data_r[`DXB_DB]}; // 8'h21,
ADDR_EXB : {EXB_r[`EXB_EBMODE],EXB_r[`EXB_EB]} <= {snes_writebuf_data_r[`EXB_EBMODE],snes_writebuf_data_r[`EXB_EB]}; // 8'h22,
ADDR_FXB : {FXB_r[`FXB_FBMODE],FXB_r[`FXB_FB]} <= {snes_writebuf_data_r[`FXB_FBMODE],snes_writebuf_data_r[`FXB_FB]}; // 8'h23,
ADDR_BMAPS : BMAPS_r[`BMAPS_SBM] <= snes_writebuf_data_r[`BMAPS_SBM]; // 8'h24,
ADDR_BMAP : BMAP_r <= snes_writebuf_data_r; // 8'h25,
ADDR_SWBE : SWBE_r[`SWBE_SWEN] <= snes_writebuf_data_r[`SWBE_SWEN]; // 8'h26,
ADDR_CWBE : CWBE_r[`CWBE_CWEN] <= snes_writebuf_data_r[`CWBE_CWEN]; // 8'h27,
ADDR_BWPA : BWPA_r[`BWPA_BWP] <= snes_writebuf_data_r[`BWPA_BWP]; // 8'h28,
ADDR_SIWP : SIWP_r <= snes_writebuf_data_r; // 8'h29,
ADDR_CIWP : CIWP_r <= snes_writebuf_data_r; // 8'h2A,
ADDR_DCNT : {DCNT_r[7:4],DCNT_r[2:0]} <= {snes_writebuf_data_r[7:4],snes_writebuf_data_r[2:0]}; // 8'h30,
ADDR_CDMA : {CDMA_r[`CDMA_CHDEND],CDMA_r[`CDMA_DMASIZE],CDMA_r[`CDMA_DMACB]} <= {snes_writebuf_data_r[`CDMA_CHDEND],snes_writebuf_data_r[`CDMA_DMASIZE],snes_writebuf_data_r[`CDMA_DMACB]}; // 8'h31,
ADDR_DSA : DSA_r[7:0] <= snes_writebuf_data_r; // 8'h32, // $3
ADDR_DSA+1 : DSA_r[15:8] <= snes_writebuf_data_r; // 8'h32, // $3
ADDR_DSA+2 : DSA_r[23:16] <= snes_writebuf_data_r; // 8'h32, // $3
ADDR_DDA : DDA_r[7:0] <= snes_writebuf_data_r; // 8'h35, // $3
ADDR_DDA+1 : DDA_r[15:8] <= snes_writebuf_data_r; // 8'h35, // $3
ADDR_DDA+2 : DDA_r[23:16] <= snes_writebuf_data_r; // 8'h35, // $3
ADDR_DTC : DTC_r[7:0] <= snes_writebuf_data_r; // 8'h38, // $2
ADDR_DTC+1 : DTC_r[15:8] <= snes_writebuf_data_r; // 8'h38, // $2
ADDR_BBF : BBF_r[`BBF_BBF] <= snes_writebuf_data_r[`BBF_BBF]; // 8'h3F,
ADDR_BRF+0 : BRF_r[0][7:0] <= snes_writebuf_data_r; // 8'h40,
ADDR_BRF+1 : BRF_r[1][7:0] <= snes_writebuf_data_r; // 8'h41,
ADDR_BRF+2 : BRF_r[2][7:0] <= snes_writebuf_data_r; // 8'h42,
ADDR_BRF+3 : BRF_r[3][7:0] <= snes_writebuf_data_r; // 8'h43,
ADDR_BRF+4 : BRF_r[4][7:0] <= snes_writebuf_data_r; // 8'h44,
ADDR_BRF+5 : BRF_r[5][7:0] <= snes_writebuf_data_r; // 8'h45,
ADDR_BRF+6 : BRF_r[6][7:0] <= snes_writebuf_data_r; // 8'h46,
ADDR_BRF+7 : BRF_r[7][7:0] <= snes_writebuf_data_r; // 8'h47,
ADDR_BRF+8 : BRF_r[8][7:0] <= snes_writebuf_data_r; // 8'h48,
ADDR_BRF+9 : BRF_r[9][7:0] <= snes_writebuf_data_r; // 8'h49,
ADDR_BRF+10: BRF_r[10][7:0] <= snes_writebuf_data_r; // 8'h4A,
ADDR_BRF+11: BRF_r[11][7:0] <= snes_writebuf_data_r; // 8'h4B,
ADDR_BRF+12: BRF_r[12][7:0] <= snes_writebuf_data_r; // 8'h4C,
ADDR_BRF+13: BRF_r[13][7:0] <= snes_writebuf_data_r; // 8'h4D,
ADDR_BRF+14: BRF_r[14][7:0] <= snes_writebuf_data_r; // 8'h4E,
ADDR_BRF+15: BRF_r[15][7:0] <= snes_writebuf_data_r; // 8'h4F,
ADDR_MCNT : {MCNT_r[`MCNT_ACM],MCNT_r[`MCNT_MD]} <= {snes_writebuf_data_r[`MCNT_ACM],snes_writebuf_data_r[`MCNT_MD]}; // 8'h50,
ADDR_MA : MA_r[7:0] <= snes_writebuf_data_r; // 8'h51, // $2
ADDR_MA+1 : MA_r[15:8] <= snes_writebuf_data_r; // 8'h51, // $2
ADDR_MB : MB_r[7:0] <= snes_writebuf_data_r; // 8'h53, // $2
ADDR_MB+1 : begin // 8'h53, // $2
if (~MCNT_r[`MCNT_ACM] & MCNT_r[`MCNT_MD]) MA_r <= 0;
MB_r <= 0;
end
ADDR_VBD : {VBD_r[`VBD_HL],VBD_r[`VBD_VB]} <= {snes_writebuf_data_r[`VBD_HL],snes_writebuf_data_r[`VBD_VB]}; // 8'h58,
default: begin end
endcase
end
end
end
//-------------------------------------------------------------------
// Math
//-------------------------------------------------------------------
wire [31:0] mult_out;
wire [15:0] divq_out;
wire [15:0] divr_out;
wire div_by_zero;
reg [1:0] math_md_r; initial math_md_r = 0;
reg [15:0] math_ma_r; initial math_ma_r = 0;
reg [15:0] math_mb_r; initial math_mb_r = 0;
reg math_val_r; initial math_val_r = 0;
reg math_acm_r; initial math_acm_r = 0;
reg math_init_r; initial math_init_r = 0;
`ifdef MK2
sa1_mult mult(
.clk(CLK),
.a(math_ma_r),
.b(math_mb_r),
.p(mult_out)
);
sa1_div div(
.clk(CLK),
.dividend(math_ma_r),
.divisor(math_mb_r),
.quotient(divq_out),
.fractional(divr_out)
);
`endif
`ifdef MK3
sa1_mult mult(
.clock(CLK),
.dataa(math_ma_r),
.datab(math_mb_r),
.result(mult_out)
);
sa1_div div(
.clock(CLK),
.numer(math_ma_r),
.denom(math_mb_r),
.quotient(divq_out),
.remain(divr_out)
);
`endif
reg [40:0] math_result;
always @(posedge CLK) begin
if (RST) begin
math_val_r <= 0;
math_acm_r <= 0;
math_init_r <= 0;
math_md_r <= 0;
math_ma_r <= 0;
math_mb_r <= 0;
MR_r <= 0;
OF_r <= 0;
end
else begin
if (snes_writebuf_val_r) begin
if (snes_writebuf_addr_r[8:0] == ADDR_MB+1) begin
if (~math_val_r) begin
// flop all inputs
math_md_r <= MCNT_r[1:0];
math_ma_r <= MA_r;
math_mb_r <= {snes_writebuf_data_r,MB_r[7:0]};
math_val_r <= 1;
end
end
else if (snes_writebuf_addr_r[8:0] == ADDR_MCNT) begin
math_init_r <= snes_writebuf_data_r[`MCNT_ACM];
end
// clear in case we get another write
math_acm_r <= 0;
end
else begin
if (math_val_r) math_acm_r <= 1;
else math_acm_r <= 0;
math_val_r <= 0;
math_init_r <= 0;
end
if (math_init_r) begin
MR_r <= 0;
end
// if we switch to ACM we need to avoid other math immediately
else if (MCNT_r[`MCNT_ACM]) begin
if (math_acm_r) begin
math_result[40:0] = {1'b0,MR_r} + {9'h00,mult_out};
MR_r <= math_result[39:0];
// set overflow
OF_r <= math_result[40];
end
end
// otherwise continue performing operation based on flopped MCNT
else if (math_md_r[`MCNT_MD]) begin
MR_r[39:32] <= 0;
MR_r[31:0] <= |math_mb_r ? {divr_out,divq_out} : 0;
end
else begin
MR_r[39:32] <= 0;
MR_r[31:0] <= mult_out;
end
end
end
//-------------------------------------------------------------------
// COMMON EXE STATE
//-------------------------------------------------------------------
`define GRP_PRI 0
`define GRP_RMW 1
`define GRP_CBR 2
`define GRP_JMP 3
`define GRP_PHS 4
`define GRP_PLL 5
`define GRP_CMP 6
`define GRP_STS 7
`define GRP_MOV 8
`define GRP_TXR 9
`define GRP_SPC 10
`define GRP_SMP 11
`define GRP_STK 12
`define GRP_XCH 13
`define GRP_TST 14
`define ADD_O16 0
`define ADD_DPR 1
`define ADD_PCR 2
`define ADD_SPL 3
`define ADD_SMI 4
`define ADD_SPR 5
`define BNK_PBR 0
`define BNK_DBR 1
`define BNK_ZRO 2
`define BNK_O24 3
`define MOD_X16 0
`define MOD_Y16 1
`define MOD_YPT 2
`define MOD_INV 3
`define ADD_STK 31:31
`define ADD_LNG 30:30
`define ADD_IND 29:29
`define ADD_IMM 28:28
`define ADD_MOD 27:26
`define ADD_ADD 25:23
`define ADD_BNK 22:21
`define DEC_GROUP 20:17
`define DEC_SIZE 16:15
`define DEC_LATENCY 14:11
`define DEC_PRC 10:9
`define DEC_SRC 8:6
`define DEC_DST 5:3
`define DEC_LOAD 2:2
`define DEC_STORE 1:1
`define DEC_CONTROL 0:0
`define PRC_B 0
`define PRC_M 1
`define PRC_X 2
`define PRC_W 3
`define REG_Z 0
`define REG_A 1
`define REG_X 2
`define REG_Y 3
`define REG_S 4
`define REG_D 5
`define REG_B 6
`define REG_P 7
`define SZE_1 0
`define SZE_2 1
`define SZE_3 2
`define SZE_4 3
parameter
ST_EXE_IDLE = 8'b00000001,
ST_EXE_FETCH = 8'b00000010,
ST_EXE_FETCH_END = 8'b00000100,
ST_EXE_ADDRESS = 8'b00001000,
ST_EXE_ADDRESS_END = 8'b00010000,
ST_EXE_EXECUTE = 8'b00100000,
ST_EXE_EXECUTE_END = 8'b01000000,
ST_EXE_WAIT = 8'b10000000,
ST_EXE_ALL = 8'b11111111;
reg [7:0] EXE_STATE; initial EXE_STATE = ST_EXE_IDLE;
reg [23:0] exe_fetch_addr_r; initial exe_fetch_addr_r = 0;
reg [31:0] exe_decode_r; initial exe_decode_r = 0;
wire exe_dec_add_stk = exe_decode_r[`ADD_STK];
wire exe_dec_add_imm = exe_decode_r[`ADD_IMM];
wire [1:0] exe_dec_add_bank = exe_decode_r[`ADD_BNK];
wire [2:0] exe_dec_add_base = exe_decode_r[`ADD_ADD];
wire [1:0] exe_dec_add_mod = exe_decode_r[`ADD_MOD];
wire exe_dec_add_indirect = exe_decode_r[`ADD_IND];
wire exe_dec_add_long = exe_decode_r[`ADD_LNG];
wire [3:0] exe_dec_grp = exe_decode_r[`DEC_GROUP];
//wire [6:0] exe_dec_inst = exe_decode_r[`DEC_OPCODE];
wire [1:0] exe_dec_size = exe_decode_r[`DEC_SIZE];
wire [3:0] exe_dec_lat = exe_decode_r[`DEC_LATENCY];
wire [1:0] exe_dec_prc = exe_decode_r[`DEC_PRC];
wire [2:0] exe_dec_src = exe_decode_r[`DEC_SRC];
wire [2:0] exe_dec_dst = exe_decode_r[`DEC_DST];
wire exe_dec_load = exe_decode_r[`DEC_LOAD];
wire exe_dec_store = exe_decode_r[`DEC_STORE];
wire exe_dec_ctl = exe_decode_r[`DEC_CONTROL];
wire exe_wai;
wire exe_mmc_int;
wire exe_fetch_byte_val;
wire exe_fetch_move;
wire [7:0] exe_fetch_byte;
wire [7:0] exe_fetch_data;
//-------------------------------------------------------------------
// COMMON PIPELINE
//-------------------------------------------------------------------
reg [3:0] exe_waitcnt_r; initial exe_waitcnt_r = 0;
reg [3:0] e2c_waitcnt_r; initial e2c_waitcnt_r = 0;
always @(posedge CLK) begin
if (RST) begin
exe_waitcnt_r <= 0;
step_r <= 0;
end
else begin
if (sa1_clock_en & |exe_waitcnt_r) exe_waitcnt_r <= exe_waitcnt_r + e2c_waitcnt_r - 1;
else exe_waitcnt_r <= exe_waitcnt_r + e2c_waitcnt_r;
// ok to advance to next instruction byte
step_r <= CONFIG_CONTROL_ENABLED || (stepcnt_r != CONFIG_STEP_COUNT);
if (pipeline_advance) stepcnt_r <= CONFIG_STEP_COUNT;
end
end
//-------------------------------------------------------------------
// IRAM
//-------------------------------------------------------------------
wire iram_wren;
wire [10:0] iram_addr;
wire [7:0] iram_din;
wire [7:0] iram_dout;
// TDP macro simplifies abritration between the snes and sa1. Also use
// spare cycles for debug reads.
wire snes_iram_wren = snes_writebuf_iram_r;
`ifdef DEBUG
wire [10:0] snes_iram_addr = snes_iram_active_r ? snes_iram_addr_r : pgm_addr_r[10:0];
`else
wire [10:0] snes_iram_addr = snes_iram_addr_r;
`endif
wire [7:0] snes_iram_din = snes_writebuf_iram_data_r;
wire [7:0] snes_iram_dout;
`ifdef MK2
sa1_iram iram (
.clka(CLK), // input clka
.wea(iram_wren), // input [0 : 0] wea
.addra(iram_addr), // input [10 : 0] addra
.dina(iram_din), // input [7 : 0] dina
.douta(iram_dout), // output [7 : 0] douta
.clkb(CLK), // input clkb
.web(snes_iram_wren), // input [0 : 0] web
.addrb(snes_iram_addr), // input [10 : 0] addrb
.dinb(snes_iram_din), // input [7 : 0] dinb
.doutb(snes_iram_dout) // output [7 : 0] doutb
);
`endif
`ifdef MK3
sa1_iram iram (
.clock(CLK), // input clka
.wren_a(iram_wren), // input [0 : 0] wea
.address_a(iram_addr), // input [10 : 0] addra
.data_a(iram_din), // input [7 : 0] dina
.q_a(iram_dout), // output [7 : 0] douta
.wren_b(snes_iram_wren), // input [0 : 0] web
.address_b(snes_iram_addr), // input [10 : 0] addrb
.data_b(snes_iram_din), // input [7 : 0] dinb
.q_b(snes_iram_dout) // output [7 : 0] doutb
);
`endif
assign snes_iram_out = snes_iram_dout;
//-------------------------------------------------------------------
// MMC PIPELINE
//-------------------------------------------------------------------
// Unified memory access. All requests are serialized and allowed
// to access as fast as the associated pipeline supports. This covers
// the following:
// sources: sa1, dma, vdp (TBD may be moved to main.v)
// targets: rom, bram, iram, mmio
//
// The unified state machine supports: single MDR, consolidated address map logic,
// priority scheduling.
//
// It's not clear whether there is a store buffer in the sa1 to overlap post store commit with
// instruction fetch (likely to rom) and other operations.
// To simplify the design don't support a store buffer unless we need the performance.
// The MDR and priority gets more complicated if we need to do parallel accesses to the different
// targets. NOTE: The ready check blocks all operations. The pipe is strictly in-order.
wire [31:0] exe_mmc_rddata;
wire [31:0] dma_mmc_rddata;
reg [7:0] MDR_r; initial MDR_r = 0;
// rom
reg rom_bus_rrq_r; initial rom_bus_rrq_r = 0;
reg [23:0] rom_bus_addr_r;
reg rom_bus_word_r;
// bram
reg ram_bus_rrq_r; initial ram_bus_rrq_r = 0;
reg ram_bus_wrq_r; initial ram_bus_wrq_r = 0;
reg [19:0] ram_bus_addr_r;
reg [7:0] ram_bus_data_r;
// iram
reg mmc_iram_state_r;
// mmio
// -
wire [23:0] exe_mmc_addr;
wire mmc_dma_end;
wire mmc_exe_end;
reg rom_bus_wrq_r; initial rom_bus_wrq_r = 0;
reg [15:0] rom_bus_data_r;
parameter
ST_MMC_IDLE = 8'b00000001,
ST_MMC_ROM = 8'b00000010,
ST_MMC_IRAM = 8'b00000100,
ST_MMC_MMIO = 8'b00001000,
ST_MMC_INV = 8'b00010000,
ST_MMC_EXE_END = 8'b00100000,
ST_MMC_DMA_END = 8'b01000000,
ST_MMC_VBD_END = 8'b10000000,
ST_MMC_ALL = 8'b11111111;
reg [7:0] MMC_STATE; initial MMC_STATE = ST_MMC_IDLE;
reg [7:0] mmc_state_end_r;
reg [23:0] mmc_addr_r;
reg [31:0] mmc_data_r; initial mmc_data_r = 0;
reg [31:0] mmc_wrdata_r; initial mmc_wrdata_r = 0;
reg mmc_wr_r; initial mmc_wr_r = 0;
reg mmc_dpe_r; initial mmc_dpe_r = 0;
reg [1:0] mmc_byte_r; initial mmc_byte_r = 0;
reg [1:0] mmc_byte_total_r; initial mmc_byte_total_r = 0;
reg mmc_long_r; initial mmc_long_r = 0;
reg mmc_rom_misaligned; initial mmc_rom_misaligned = 0;
always @(posedge CLK) begin
if (RST) begin
MMC_STATE <= ST_MMC_IDLE;
MDR_r <= 0;
mmc_long_r <= 0;
rom_bus_rrq_r <= 0;
rom_bus_wrq_r <= 0; // unused but good to init
end
else begin
case (MMC_STATE)
ST_MMC_IDLE: begin
// priority
// - vdp
// - dma (high pri)
// - exe
// - dma (low pri)
mmc_byte_r <= 0;
`ifdef VBD_ENABLE
if (vbd_mmc_rd_r) begin
mmc_byte_total_r <= 3;
mmc_dpe_r <= 0;
mmc_wr_r <= 0;
mmc_long_r <= 0;
rom_bus_rrq_r <= 1;
rom_bus_addr_r <= `MAP_ROM(vbd_mmc_addr_r);
rom_bus_word_r <= 1;
// TODO: ok to force aligned access?
mmc_rom_misaligned <= 0;
MMC_STATE <= ST_MMC_ROM;
mmc_state_end_r <= ST_MMC_VBD_END;
end
else
`endif
if (dma_mmc_rd_rom_r | dma_mmc_rd_iram_r | dma_mmc_wr_iram_r) begin
mmc_byte_total_r<= 0;
mmc_dpe_r <= 0;
mmc_wr_r <= dma_mmc_wr_iram_r;
mmc_long_r <= 0;
mmc_wrdata_r[7:0] <= dma_mmc_data_r;
// NOTE: could move this decode to DMA
if (dma_mmc_rd_rom_r/* & ROM_BUS_RDY*/) begin
rom_bus_rrq_r <= 1;
rom_bus_addr_r <= `MAP_ROM(dma_mmc_rd_addr_r);
rom_bus_word_r <= 1;
//mmc_addr_r <= `MAP_ROM(dma_mmc_addr_r);
mmc_rom_misaligned <= dma_mmc_rd_addr_r[0];
MMC_STATE <= ST_MMC_ROM;
end
else if (dma_mmc_rd_iram_r | dma_mmc_wr_iram_r) begin
mmc_iram_state_r <= 0;
mmc_addr_r <= `MAP_IRAM(dma_mmc_rd_iram_r ? dma_mmc_rd_addr_r : dma_mmc_wr_addr_r);
MMC_STATE <= ST_MMC_IRAM;
end
else begin
MMC_STATE <= ST_MMC_INV;
end
mmc_state_end_r <= ST_MMC_DMA_END;
end
// // save a cycle in fetch if we are going to rom.
// else if (EXE_STATE[clog2(ST_EXE_FETCH)] & ~exe_mmc_int & ~exe_fetch_byte_val & ~exe_fetch_move) begin
// mmc_byte_total_r <= exe_mmc_byte_total_r;
// mmc_dpe_r <= exe_mmc_dpe_r;
// mmc_wr_r <= 0;
// mmc_long_r <= exe_mmc_long_r;
//
// if (`IS_ROM(exe_fetch_addr_r)/* & ROM_BUS_RDY*/) begin
// rom_bus_rrq_r <= 1;
// rom_bus_addr_r <= `MAP_ROM(exe_fetch_addr_r);
// rom_bus_word_r <= 1;
// mmc_rom_misaligned <= exe_fetch_addr_r[0];
//
// MMC_STATE <= ST_MMC_ROM;
// end
//
// mmc_state_end_r <= ST_MMC_EXE_END;
// end
else if (exe_mmc_rd_r | exe_mmc_wr_r) begin
mmc_byte_total_r <= exe_mmc_byte_total_r;
mmc_dpe_r <= exe_mmc_dpe_r;
mmc_wr_r <= exe_mmc_wr_r;
mmc_long_r <= exe_mmc_long_r;
mmc_wrdata_r <= exe_mmc_data_r;
if (`IS_ROM(exe_mmc_addr)/* & ROM_BUS_RDY*/) begin
rom_bus_rrq_r <= ~exe_mmc_wr_r;
rom_bus_addr_r <= `MAP_ROM(exe_mmc_addr);
rom_bus_word_r <= 1;
//mmc_addr_r <= `MAP_ROM(exe_mmc_addr);
mmc_rom_misaligned <= exe_mmc_addr[0];
MMC_STATE <= exe_mmc_wr_r ? ST_MMC_INV : ST_MMC_ROM;
end
else if (`IS_SA1_IRAM(exe_mmc_addr)) begin
// avoid sa1 write to snes read conflict late in the cycle - NOTE: if we do an address compare we won't properly handle collisions on multi-byte operations.
// TODO: move this to the IRAM cycle, but need to be careful of write enable, state machine, etc state. The current fix may still miss multibyte operations.
mmc_iram_state_r <= 0;
mmc_addr_r <= `MAP_IRAM(exe_mmc_addr);
MMC_STATE <= ST_MMC_IRAM;
end
else if (`IS_MMIO(exe_mmc_addr)) begin
mmc_addr_r <= `MAP_MMIO(exe_mmc_addr);
MMC_STATE <= ST_MMC_MMIO;
end
else if (~`IS_SA1_BRAM(exe_mmc_addr) & ~`IS_SA1_PRAM(exe_mmc_addr)) begin
MMC_STATE <= ST_MMC_INV;
end
mmc_state_end_r <= ST_MMC_EXE_END;
end
end
ST_MMC_ROM: begin
rom_bus_rrq_r <= 0;
if (~rom_bus_rrq_r & ROM_BUS_RDY) begin
mmc_byte_r <= mmc_byte_r + (mmc_rom_misaligned ? 1 : 2);
// only the first request may be misaligned
mmc_rom_misaligned <= 0;
case (mmc_byte_r)
0: mmc_data_r[15: 0] <= ROM_BUS_RDDATA[15:0];
1: mmc_data_r[23: 8] <= ROM_BUS_RDDATA[15:0];
2: mmc_data_r[31:16] <= ROM_BUS_RDDATA[15:0];
3: mmc_data_r[31:24] <= ROM_BUS_RDDATA[7:0];
endcase
// TODO: doesn't work if we want 4 bytes back and misaligned
// TODO: fetch already handles misaligned. don't need both.
if ((mmc_rom_misaligned & mmc_byte_total_r[0]) | (~|mmc_byte_r & mmc_byte_total_r[1])) begin
rom_bus_rrq_r <= 1;
if (mmc_dpe_r) rom_bus_addr_r[7:0] <= {rom_bus_addr_r[7:1] + 1, 1'b0};
//else if (mmc_long_r) rom_bus_addr_r[23:0] <= {rom_bus_addr_r[23:1] + 1, 1'b0};
//else rom_bus_addr_r[15:0] <= {rom_bus_addr_r[15:1] + 1, 1'b0};
else rom_bus_addr_r[23:0] <= {rom_bus_addr_r[23:1] + 1, 1'b0};
end
else begin
MMC_STATE <= mmc_state_end_r;
end
end
end
ST_MMC_IRAM: begin
mmc_iram_state_r <= ~mmc_iram_state_r;
// writes are pipelined single cycle
if (mmc_wr_r | mmc_iram_state_r) begin
mmc_byte_r <= mmc_byte_r + 1;
case (mmc_byte_r)
0: mmc_data_r[ 7: 0] <= iram_dout[7:0];
1: mmc_data_r[15: 8] <= iram_dout[7:0];
2: mmc_data_r[23:16] <= iram_dout[7:0];
3: mmc_data_r[31:24] <= iram_dout[7:0];
endcase
mmc_wrdata_r <= {mmc_wrdata_r[7:0],mmc_wrdata_r[31:24],mmc_wrdata_r[23:16],mmc_wrdata_r[15:8]};
if (mmc_byte_r != mmc_byte_total_r) begin
if (mmc_dpe_r) mmc_addr_r[7:0] <= mmc_addr_r[7:0] + 1;
else mmc_addr_r[10:0] <= mmc_addr_r[10:0] + 1;
end
else begin
MMC_STATE <= mmc_state_end_r;
end
end
end
ST_MMC_MMIO: begin
if ((mmc_wr_r & sa1_mmio_write) | (~mmc_wr_r & sa1_mmio_read_r[1])) begin
mmc_byte_r <= mmc_byte_r + 1;
case (mmc_byte_r)
0: mmc_data_r[ 7: 0] <= data_out_r[7:0];
1: mmc_data_r[15: 8] <= data_out_r[7:0];
2: mmc_data_r[23:16] <= data_out_r[7:0];
3: mmc_data_r[31:23] <= data_out_r[7:0];
endcase
mmc_wrdata_r <= {mmc_wrdata_r[7:0],mmc_wrdata_r[31:24],mmc_wrdata_r[23:16],mmc_wrdata_r[15:8]};
if (mmc_byte_r != mmc_byte_total_r) begin
mmc_addr_r[7:0] <= mmc_addr_r[7:0] + 1;
end
else begin
MMC_STATE <= mmc_state_end_r;
end
end
end
ST_MMC_INV: begin
mmc_data_r <= {MDR_r,MDR_r,MDR_r,MDR_r};
MMC_STATE <= mmc_state_end_r;
end
`ifdef VBD_ENABLE
ST_MMC_VBD_END,
`endif
ST_MMC_EXE_END,
ST_MMC_DMA_END: begin
MMC_STATE <= ST_MMC_IDLE;
end
endcase
end
end
// bram/pram
// - exe
// - dma
parameter
ST_MMC_RAM_IDLE = 1'b0,
ST_MMC_RAM_WAIT = 1'b1;
reg MMC_RAM_STATE; initial MMC_RAM_STATE = ST_MMC_RAM_IDLE;
reg mmc_ram_exe_end_r; initial mmc_ram_exe_end_r = 0;
reg mmc_ram_dma_end_r; initial mmc_ram_dma_end_r = 0;
reg [1:0] mmc_ram_byte_r;
reg [1:0] mmc_ram_byte_total_r;
reg mmc_ram_dpe_r;
reg mmc_ram_wr_r;
reg mmc_ram_long_r;
reg [31:0] mmc_ram_rddata_r;
reg [31:0] mmc_ram_wrdata_r;
reg mmc_ram_pram_r;
reg [1:0] mmc_ram_pram_index_r; initial mmc_ram_pram_index_r = 0;
reg mmc_ram_dma_r;
reg mmc_ram_exe_r;
always @(posedge CLK) begin
if (RST) begin
mmc_ram_exe_end_r <= 0;
mmc_ram_dma_end_r <= 0;
ram_bus_rrq_r <= 0;
ram_bus_wrq_r <= 0;
MMC_RAM_STATE <= ST_MMC_RAM_IDLE;
end
else begin
case (MMC_RAM_STATE)
ST_MMC_RAM_IDLE: begin
mmc_ram_exe_end_r <= 0;
mmc_ram_dma_end_r <= 0;
mmc_ram_byte_r <= 0;
mmc_ram_dma_r <= 0;
mmc_ram_exe_r <= 0;
// bus must be available here
if ((dma_mmc_wr_bram_r | dma_mmc_rd_bram_r) & ~mmc_ram_dma_end_r) begin
ram_bus_rrq_r <= ~dma_mmc_wr_bram_r;
ram_bus_wrq_r <= dma_mmc_wr_bram_r;
ram_bus_addr_r <= `MAP_BRAM(dma_mmc_wr_bram_r ? dma_mmc_wr_addr_r : dma_mmc_rd_addr_r);
ram_bus_data_r <= dma_mmc_data_r[7:0];
mmc_ram_pram_r <= 0;
mmc_ram_byte_total_r <= 0;
mmc_ram_dpe_r <= 0;
mmc_ram_wr_r <= dma_mmc_wr_bram_r;
mmc_ram_long_r <= 0;
mmc_ram_wrdata_r[7:0] <= dma_mmc_data_r;
mmc_ram_dma_r <= 1;
MMC_RAM_STATE <= ST_MMC_RAM_WAIT;
end
else if ((exe_mmc_wr_r | exe_mmc_rd_r) & ~mmc_ram_exe_end_r) begin
mmc_ram_byte_total_r <= exe_mmc_byte_total_r;
mmc_ram_dpe_r <= exe_mmc_dpe_r;
mmc_ram_wr_r <= exe_mmc_wr_r;
mmc_ram_long_r <= exe_mmc_long_r;
mmc_ram_wrdata_r <= exe_mmc_data_r;
if (`IS_SA1_BRAM(exe_mmc_addr)/* & RAM_BUS_RDY*/) begin
ram_bus_rrq_r <= ~exe_mmc_wr_r;
ram_bus_wrq_r <= exe_mmc_wr_r;
ram_bus_addr_r <= `MAP_BRAM(exe_mmc_addr);
ram_bus_data_r <= exe_mmc_data_r[7:0];
mmc_ram_pram_r <= 0;
MMC_RAM_STATE <= ST_MMC_RAM_WAIT;
end
else if (`IS_SA1_PRAM(exe_mmc_addr)/* & RAM_BUS_RDY*/) begin
// PRAM is always RMW if we are writing
ram_bus_rrq_r <= 1;
ram_bus_addr_r <= `MAP_PRAM(exe_mmc_addr);
ram_bus_data_r <= exe_mmc_data_r[7:0];
mmc_ram_byte_total_r <= 0; // force 1 byte to avoid complexity of word write and interleaving data
mmc_ram_pram_r <= 1;
mmc_ram_pram_index_r <= exe_mmc_addr[1:0];
MMC_RAM_STATE <= ST_MMC_RAM_WAIT;
end
mmc_ram_exe_r <= 1;
end
end
ST_MMC_RAM_WAIT: begin
ram_bus_rrq_r <= 0;
ram_bus_wrq_r <= 0;
if (~ram_bus_rrq_r & ~ram_bus_wrq_r & RAM_BUS_RDY) begin
if (~mmc_ram_pram_r) begin
// don't increment byte location or shift write data if pram
mmc_ram_byte_r <= mmc_ram_byte_r + 1;
mmc_ram_wrdata_r <= {mmc_ram_wrdata_r[7:0],mmc_ram_wrdata_r[31:24],mmc_ram_wrdata_r[23:16],mmc_ram_wrdata_r[15:8]};
end
if (mmc_ram_pram_r) begin
// read data
case (mmc_ram_pram_index_r)
0: mmc_ram_rddata_r[7:0] <= bbf ? {6'h00,RAM_BUS_RDDATA[1:0]} : {4'h0,RAM_BUS_RDDATA[3:0]};
1: mmc_ram_rddata_r[7:0] <= bbf ? {6'h00,RAM_BUS_RDDATA[3:2]} : {4'h0,RAM_BUS_RDDATA[7:4]};
2: mmc_ram_rddata_r[7:0] <= bbf ? {6'h00,RAM_BUS_RDDATA[5:4]} : {4'h0,RAM_BUS_RDDATA[3:0]};
3: mmc_ram_rddata_r[7:0] <= bbf ? {6'h00,RAM_BUS_RDDATA[7:6]} : {4'h0,RAM_BUS_RDDATA[7:4]};
endcase
end
else begin
case (mmc_ram_byte_r)
0: mmc_ram_rddata_r[7 : 0] <= RAM_BUS_RDDATA[7:0];
1: mmc_ram_rddata_r[15: 8] <= RAM_BUS_RDDATA[7:0];
2: mmc_ram_rddata_r[23:16] <= RAM_BUS_RDDATA[7:0];
3: mmc_ram_rddata_r[31:24] <= RAM_BUS_RDDATA[7:0];
endcase
end
if (mmc_ram_pram_r & mmc_ram_wr_r) begin
// perform rmw
ram_bus_wrq_r <= 1;
mmc_ram_pram_r <= 0;
// TODO: assumes only one byte (value) is merged
case (mmc_ram_pram_index_r)
0: ram_bus_data_r[7:0] <= bbf ? {RAM_BUS_RDDATA[7:2],mmc_ram_wrdata_r[1:0] } : {RAM_BUS_RDDATA[7:4],mmc_ram_wrdata_r[3:0]};
1: ram_bus_data_r[7:0] <= bbf ? {RAM_BUS_RDDATA[7:4],mmc_ram_wrdata_r[1:0],RAM_BUS_RDDATA[1:0]} : {mmc_ram_wrdata_r[3:0],RAM_BUS_RDDATA[3:0]};
2: ram_bus_data_r[7:0] <= bbf ? {RAM_BUS_RDDATA[7:6],mmc_ram_wrdata_r[1:0],RAM_BUS_RDDATA[3:0]} : {RAM_BUS_RDDATA[7:4],mmc_ram_wrdata_r[3:0]};
3: ram_bus_data_r[7:0] <= bbf ? {mmc_ram_wrdata_r[1:0],RAM_BUS_RDDATA[5:0] } : {mmc_ram_wrdata_r[3:0],RAM_BUS_RDDATA[3:0]};
endcase
end
else if (mmc_ram_byte_r != mmc_ram_byte_total_r) begin
// stay in the same state and make a new request
ram_bus_rrq_r <= ~mmc_ram_wr_r;
ram_bus_wrq_r <= mmc_ram_wr_r;
if (mmc_ram_dpe_r) ram_bus_addr_r[7:0] <= ram_bus_addr_r[7:0] + 1;
//else if (mmc_long_r) ram_bus_addr_r[23:0] <= ram_bus_addr_r[23:0] + 1;
//else ram_bus_addr_r[15:0] <= ram_bus_addr_r[15:0] + 1;
else ram_bus_addr_r[19:0] <= ram_bus_addr_r[19:0] + 1;
ram_bus_data_r <= mmc_ram_wrdata_r[15:8];
end
else begin
{mmc_ram_dma_end_r,mmc_ram_exe_end_r} <= {mmc_ram_dma_r,mmc_ram_exe_r};
MMC_RAM_STATE <= ST_MMC_RAM_IDLE;
end
end
end
endcase
end
end
assign ROM_BUS_RRQ = rom_bus_rrq_r;
assign ROM_BUS_WRQ = 1'b0;
assign ROM_BUS_WORD = rom_bus_word_r;
assign ROM_BUS_ADDR = rom_bus_addr_r;
assign ROM_BUS_WRDATA = rom_bus_data_r;
assign RAM_BUS_RRQ = ram_bus_rrq_r;
assign RAM_BUS_WRQ = ram_bus_wrq_r;
assign RAM_BUS_WORD = 1'b0;
assign RAM_BUS_ADDR = {4'h0,ram_bus_addr_r};
assign RAM_BUS_WRDATA = ram_bus_data_r;
assign iram_wren = MMC_STATE[clog2(ST_MMC_IRAM)] & mmc_wr_r;
assign iram_addr = mmc_addr_r[10:0];
assign iram_din = mmc_wrdata_r[7:0];
assign sa1_mmio_addr = mmc_addr_r[8:0];
assign sa1_mmio_data = mmc_wrdata_r[7:0];
assign sa1_mmio_write = ~(SNES_WR_end & snes_mmio_active_r) & MMC_STATE[clog2(ST_MMC_MMIO)] & mmc_wr_r;
assign sa1_mmio_read = ~|sa1_mmio_read_r & ~(~SNES_READ & snes_mmio_active_r & ~snes_mmio_done_r) & MMC_STATE[clog2(ST_MMC_MMIO)] & ~mmc_wr_r;
assign exe_mmc_rddata = mmc_ram_exe_end_r ? mmc_ram_rddata_r : mmc_data_r;
assign dma_mmc_rddata = mmc_ram_dma_end_r ? mmc_ram_rddata_r : mmc_data_r;
assign mmc_exe_end = MMC_STATE[clog2(ST_MMC_EXE_END)] | mmc_ram_exe_end_r;
assign mmc_dma_end = MMC_STATE[clog2(ST_MMC_DMA_END)] | mmc_ram_dma_end_r;
//-------------------------------------------------------------------
// DMA Pipeline
//-------------------------------------------------------------------
// The DMA controller supports 2 general modes of operation: normal
// and character conversion (CC). CC can be broken down into type1
// (fully automatic) and type2 (semi-automatic). In an attempt to
// get this to fit in the fpga, as much code as re-used as possible.
// The main differences between the 2 modes are addressing/dataswizzle
// and triggers.
//
// normal - no character conversion. can trigger interrupt. dtc holds count. triggered by dda write.
// type1 - bram->iram character conversion. pixel to planar. 8x8 character. triggered by dda write and snes reads.
// type2 - brf->iram character conversion. pixel to planar. 8 pixels in lower or upper brf. triggered by brf writes.
parameter
ST_DMA_IDLE = 8'b00000001,
ST_DMA_NORMAL_READ = 8'b00000010,
ST_DMA_TYPE1_READ = 8'b00000100,
ST_DMA_TYPE2_READ = 8'b00001000,
ST_DMA_READ_END = 8'b00010000,
ST_DMA_TYPE1_WRITE = 8'b00100000,
ST_DMA_WRITE = 8'b01000000,
ST_DMA_WRITE_END = 8'b10000000,
ST_DMA_ALL = 8'b11111111;
reg [7:0] DMA_STATE; initial DMA_STATE = ST_DMA_IDLE;
reg dma_cc1_en_r; initial dma_cc1_en_r = 0;
reg dma_normal_pri_active_r; initial dma_normal_pri_active_r = 0;
reg dma_cc1_active_r; initial dma_cc1_active_r = 0;
reg [6:0] dma_cc1_imask_r;
`ifdef DMA_ENABLE
reg [7:0] dma_next_readstate_r; initial dma_next_readstate_r = 0;
reg [7:0] dma_next_writestate_r; initial dma_next_writestate_r = 0;
reg [23:0] dma_write_addr_r; initial dma_write_addr_r = 0;
reg [7:0] dma_data_r; initial dma_data_r = 0;
reg [7:0] dma_cc1_data_r[7:0];
reg dma_cc1_int_r;
reg [5:0] dma_cc1_mask_r;
reg [3:0] dma_cc1_bpp_r; // both bits per pixel and bytes per 8x8 character row
reg [8:0] dma_cc1_bpl_r; // bytes per line
reg [4:0] dma_cc1_size_mask_r; // characters per line
reg [4:0] dma_cc1_char_num_r; initial dma_cc1_char_num_r = 0;
reg [23:0] dma_cc1_addr_char_base_r;
reg [23:0] dma_cc1_addr_row_base_r;
reg [23:0] dma_cc1_addr_rd_r; // current read address
reg [10:0] dma_cc1_addr_wr_r; // current write address
reg [3:0] dma_cc2_line_r; initial dma_cc2_line_r = 0;
reg dma_normal_int_r; initial dma_normal_int_r = 0;
reg dma_normal_prefetch_val_r; initial dma_normal_prefetch_val_r = 0;
reg dma_normal_prefetch_found_r; initial dma_normal_prefetch_found_r = 0;
reg [7:0] dma_normal_prefetch_dat_r; initial dma_normal_prefetch_dat_r = 0;
reg [1:0] dma_normal_state_r; initial dma_normal_state_r = 0;
reg dma_trigger_normal_r; initial dma_trigger_normal_r = 0;
reg dma_start_type1_r; initial dma_start_type1_r = 0;
reg dma_trigger_type1_r; initial dma_trigger_type1_r = 0;
reg dma_trigger_type2_r; initial dma_trigger_type2_r = 0;
reg [2:0] dma_line_r; initial dma_line_r = 0;
reg [2:0] dma_byte_r; initial dma_byte_r = 0;
reg [2:0] dma_comp_r; initial dma_comp_r = 0;
reg [7:0] dma_cdma_r; initial dma_cdma_r = 0;
reg [7:0] dma_dcnt_r; initial dma_dcnt_r = 0;
reg [15:0] dma_dtc_r; initial dma_dtc_r = 0;
reg [23:0] dma_dsa_r; initial dma_dsa_r = 0;
reg [23:0] dma_dda_r; initial dma_dda_r = 0;
always @(posedge CLK) begin
if (RST) begin
DMA_STATE <= ST_DMA_IDLE;
dma_next_readstate_r <= ST_DMA_IDLE;
dma_next_writestate_r <= ST_DMA_IDLE;
dma_mmc_rd_rom_r <= 0;
dma_mmc_rd_bram_r <= 0;
dma_mmc_wr_bram_r <= 0;
dma_mmc_rd_iram_r <= 0;
dma_mmc_wr_iram_r <= 0;
dma_trigger_normal_r <= 0;
dma_start_type1_r <= 0;
dma_trigger_type1_r <= 0;
dma_trigger_type2_r <= 0;
dma_line_r <= 0;
dma_cc1_char_num_r <= 0;
dma_cc1_int_r <= 0;
dma_cc1_en_r <= 0;
dma_cc1_active_r <= 0;
dma_normal_pri_active_r <= 0;
dma_cc2_line_r <= 0;
dma_normal_int_r <= 0;
dma_normal_prefetch_val_r <= 0;
dma_normal_state_r <= 0;
SFR_r[`SFR_DMA_IRQFL] <= 0;
CFR_r[`CFR_DMA_IRQFL] <= 0;
end
else begin
// watch for triggers
dma_trigger_normal_r <= ( dma_dcnt_r[`DCNT_DMAEN]
&& ~dma_dcnt_r[`DCNT_CDEN]
&& ( (~dma_dcnt_r[1] && ~dma_dcnt_r[`DCNT_DD]) // iram
|| (~dma_dcnt_r[0] && dma_dcnt_r[`DCNT_DD]) // bram
)
&& ( (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == (ADDR_DDA+1) && ~dma_dcnt_r[`DCNT_DD]) // iram
|| (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == (ADDR_DDA+2) && dma_dcnt_r[`DCNT_DD]) // bram
)
);
dma_start_type1_r <= ( dma_dcnt_r[`DCNT_DMAEN]
&& dma_dcnt_r[`DCNT_CDEN]
&& dma_dcnt_r[`DCNT_CDSEL]
&& ( (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == (ADDR_DDA+1))
)
);
dma_trigger_type1_r <= ( dma_cc1_en_r
&& `IS_CPU_BRAM(addr_in_r)
//&& (addr_in_r[23:20] == 4'h4)
&& SNES_RD_start
&& ((addr_in_r[5:0] & dma_cc1_mask_r) == 0)
);
`ifdef DMA_TYPE2_ENABLE
dma_trigger_type2_r <= ( dma_dcnt_r[`DCNT_DMAEN]
&& dma_dcnt_r[`DCNT_CDEN]
&& ~dma_dcnt_r[`DCNT_CDSEL]
&& ( (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_BRF7)
|| (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_BRFF)
)
);
`else
dma_trigger_type2_r <= 0;
`endif
dma_comp_r <= {~|dma_cdma_r[1:0],~dma_cdma_r[1],1'b1};
dma_cc1_bpp_r <= {~|dma_cdma_r[1:0],dma_cdma_r[0],dma_cdma_r[1],1'b0};
case (dma_cdma_r[`CDMA_DMASIZE] + {dma_cdma_r[1]^~dma_cdma_r[0],dma_cdma_r[0]})
0: dma_cc1_bpl_r <= 9'b000000010;
1: dma_cc1_bpl_r <= 9'b000000100;
2: dma_cc1_bpl_r <= 9'b000001000;
3: dma_cc1_bpl_r <= 9'b000010000;
4: dma_cc1_bpl_r <= 9'b000100000;
5: dma_cc1_bpl_r <= 9'b001000000;
6: dma_cc1_bpl_r <= 9'b010000000;
7: dma_cc1_bpl_r <= 9'b100000000;
endcase
case (dma_cdma_r[`CDMA_DMASIZE])
0: dma_cc1_size_mask_r <= 1-1;
1: dma_cc1_size_mask_r <= 2-1;
2: dma_cc1_size_mask_r <= 4-1;
3: dma_cc1_size_mask_r <= 8-1;
4: dma_cc1_size_mask_r <= 16-1;
5: dma_cc1_size_mask_r <= 32-1;
endcase
// source is naturally aligned to full width (charSize * dmaSize). That makes addressing easier.
dma_cc1_mask_r <= {dma_comp_r,3'b111};
dma_cc1_imask_r <= {dma_comp_r,4'b1111};
// CC1 to SCPU (snes) interrupt
if (DMA_STATE[clog2(ST_DMA_IDLE)] & dma_cc1_int_r) SFR_r[`SFR_DMA_IRQFL] <= 1;
else if (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_SIC && snes_writebuf_data_r[`SIC_DMA_IRQCL]) SFR_r[`SFR_DMA_IRQFL] <= 0;
// normal to CCPU (sa1) interrupt
if (DMA_STATE[clog2(ST_DMA_IDLE)] & dma_normal_int_r) CFR_r[`CFR_DMA_IRQFL] <= 1;
else if (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_CIC && snes_writebuf_data_r[`CIC_DMA_IRQCL]) CFR_r[`CFR_DMA_IRQFL] <= 0;
if (dma_start_type1_r) dma_cc1_en_r <= 1;
else if (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_CDMA && snes_writebuf_data_r[`CDMA_CHDEND]) dma_cc1_en_r <= 0;
if (dma_trigger_type1_r) dma_cc1_active_r <= 1;
else if (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_CDMA && snes_writebuf_data_r[`CDMA_CHDEND]) dma_cc1_active_r <= 0;
// TODO: temporarily make DMA high priority to avoid races.
if ((dma_trigger_normal_r/* & dma_dcnt_r[`DCNT_DPRIO]*/) | dma_trigger_type2_r) dma_normal_pri_active_r <= 1;
else if (DMA_STATE[clog2(ST_DMA_IDLE)]) dma_normal_pri_active_r <= 0;
case (DMA_STATE)
ST_DMA_IDLE: begin
// clear line number
if (~dma_dcnt_r[`DCNT_DMAEN]) dma_cc2_line_r <= 0;
dma_cdma_r <= CDMA_r;
dma_dcnt_r <= DCNT_r;
dma_dtc_r <= DTC_r;
dma_dsa_r <= DSA_r;
dma_dda_r <= DDA_r;
dma_byte_r <= 0;
// will be 1 when we transition to idle after the first character.
dma_cc1_int_r <= dma_start_type1_r;
dma_normal_int_r <= 0;
dma_normal_prefetch_val_r <= 0;
if (dma_trigger_normal_r) begin
dma_normal_state_r <= 1;
DMA_STATE <= ST_DMA_NORMAL_READ;
end
else if (dma_start_type1_r) begin
// when we are only one character wide then bpp == bpl
dma_cc1_addr_char_base_r <= |dma_cc1_size_mask_r ? (DSA_r + dma_cc1_bpp_r) : (DSA_r + {dma_cc1_bpl_r,3'b000});
dma_cc1_addr_row_base_r <= DSA_r;
dma_cc1_addr_rd_r <= DSA_r;
dma_cc1_addr_wr_r <= DDA_r[10:0];
dma_cc1_char_num_r <= {4'b0000,dma_cc1_size_mask_r[0]};
dma_line_r <= 0;
DMA_STATE <= ST_DMA_TYPE1_READ;
end
else if (dma_trigger_type1_r) begin
// either we are in the same row and increment the base by the width of a character in bytes or take the current address
// which has incremented beyond the start of the next character by bpl-2*bpp
dma_cc1_addr_char_base_r <= (dma_cc1_char_num_r == dma_cc1_size_mask_r) ? (dma_cc1_addr_row_base_r + {dma_cc1_bpl_r,3'b000}) : (dma_cc1_addr_char_base_r + dma_cc1_bpp_r);
dma_cc1_addr_row_base_r <= |dma_cc1_char_num_r ? dma_cc1_addr_row_base_r : dma_cc1_addr_char_base_r;
dma_cc1_addr_rd_r <= dma_cc1_addr_char_base_r;
// toggle double buffer
dma_cc1_addr_wr_r[6:4] <= dma_cc1_addr_wr_r[6:4] ^ dma_cc1_bpp_r[3:1];
dma_cc1_char_num_r <= (dma_cc1_char_num_r + 1) & dma_cc1_size_mask_r;
DMA_STATE <= ST_DMA_TYPE1_READ;
end
else if (dma_trigger_type2_r) begin
DMA_STATE <= ST_DMA_TYPE2_READ;
end
end
`ifdef DMA_NORMAL_ENABLE
// normal
// read/write state
ST_DMA_NORMAL_READ: begin
dma_mmc_rd_rom_r <= dma_normal_state_r[0] & ~|dma_dcnt_r[1:0] & ~dma_normal_prefetch_val_r;
dma_mmc_rd_bram_r <= dma_normal_state_r[0] & dma_dcnt_r[0];
dma_mmc_rd_iram_r <= dma_normal_state_r[0] & dma_dcnt_r[1];
dma_mmc_wr_bram_r <= dma_normal_state_r[1] & dma_dcnt_r[`DCNT_DD];
dma_mmc_wr_iram_r <= dma_normal_state_r[1] & ~dma_dcnt_r[`DCNT_DD];
// adjust count on writes
if (dma_normal_state_r[0]) dma_dsa_r <= dma_dsa_r + 1;
if (dma_normal_state_r[1]) dma_dda_r <= dma_dda_r + 1;
if (dma_normal_state_r[1]) dma_dtc_r <= dma_dtc_r - 1;
dma_mmc_rd_addr_r <= {(dma_dsa_r[23:11] & {13{~dma_dcnt_r[1]}}), dma_dsa_r[10:0]};
dma_mmc_wr_addr_r <= {(dma_dda_r[23:11] & {13{dma_dcnt_r[`DCNT_DD]}}),dma_dda_r[10:0]};
dma_mmc_data_r[7:0] <= dma_data_r[7:0];
dma_normal_prefetch_found_r <= 0;
DMA_STATE <= ST_DMA_WRITE;
end
// new wait state
ST_DMA_WRITE: begin
// need to watch for both read and write ending and grab data from appropriate place
// FIXME: remove the hack that uses mmc_wr_r
if (dma_mmc_rd_bram_r & mmc_ram_dma_end_r) dma_data_r[7:0] <= mmc_ram_rddata_r[7:0];
else if (MMC_STATE[clog2(ST_MMC_DMA_END)] & ~mmc_wr_r) dma_data_r[7:0] <= mmc_data_r[7:0];
else if (dma_normal_prefetch_val_r) dma_data_r[7:0] <= dma_normal_prefetch_dat_r[7:0];
// store the next prefetch byte if it's to rom
if (dma_mmc_rd_rom_r & ~dma_normal_prefetch_val_r & ~dma_mmc_rd_addr_r[0] & MMC_STATE[clog2(ST_MMC_DMA_END)]) dma_normal_prefetch_found_r <= 1;
if (MMC_STATE[clog2(ST_MMC_DMA_END)]) dma_normal_prefetch_dat_r <= mmc_data_r[15:8];
// need to disambiguate between reads and writes for rom/iram
if (MMC_STATE[clog2(ST_MMC_DMA_END)]) dma_mmc_rd_rom_r <= 0;
if (MMC_STATE[clog2(ST_MMC_DMA_END)] & ~mmc_wr_r) dma_mmc_rd_iram_r <= 0;
if (MMC_STATE[clog2(ST_MMC_DMA_END)] & mmc_wr_r) dma_mmc_wr_iram_r <= 0;
if (mmc_ram_dma_end_r) dma_mmc_rd_bram_r <= 0;
if (mmc_ram_dma_end_r) dma_mmc_wr_bram_r <= 0;
dma_normal_state_r <= {1'b1, |dma_dtc_r[15:1]};
// look for all conditions done
if (~(dma_mmc_rd_rom_r | dma_mmc_rd_bram_r | dma_mmc_wr_bram_r | dma_mmc_rd_iram_r | dma_mmc_wr_iram_r)) begin
if (~|dma_dtc_r) dma_normal_int_r <= 1;
dma_normal_prefetch_val_r <= dma_normal_prefetch_found_r;
dma_normal_prefetch_found_r <= 0;
if (~|dma_dtc_r) DMA_STATE <= ST_DMA_IDLE;
else DMA_STATE <= ST_DMA_NORMAL_READ;
end
end
`endif
`ifdef DMA_TYPE1_ENABLE
// type1
ST_DMA_TYPE1_READ: begin
// only perform memory read for valid byte
//dma_cc1_rd_r <= ~|(dma_byte_r[1:0] & {dma_cdma_r[1],|dma_cdma_r[1:0]});
//dma_mmc_rd_r <= ~|(dma_byte_r[1:0] & {dma_cdma_r[1],|dma_cdma_r[1:0]}); // & ~dma_cc1_upper_r;
//{dma_mmc_rom_r,dma_mmc_iram_r,dma_mmc_bram_r} <= {1'b0,1'b0,1'b1};
dma_mmc_rd_bram_r <= ~|(dma_byte_r[1:0] & {dma_cdma_r[1],|dma_cdma_r[1:0]});
// address is for row and also include the byte of interest.
dma_mmc_rd_addr_r <= dma_cc1_addr_rd_r | (dma_cdma_r[1] ? {2'b00,dma_byte_r[2]} : dma_cdma_r[0] ? {1'b0,dma_byte_r[2:1]} : dma_byte_r[2:0]);
dma_byte_r <= dma_byte_r + 1;
// test for transition to write state
dma_next_readstate_r <= &dma_byte_r ? ST_DMA_TYPE1_WRITE : ST_DMA_TYPE1_READ;
DMA_STATE <= ST_DMA_READ_END;
end
ST_DMA_TYPE1_WRITE: begin
dma_mmc_wr_iram_r <= ~|(dma_byte_r & ~dma_comp_r);
//{dma_mmc_rom_r,dma_mmc_iram_r,dma_mmc_bram_r} <= {1'b0,1'b1,1'b0};
// calculate address
dma_mmc_wr_addr_r <= {13'h0000,dma_cc1_addr_wr_r} | {dma_byte_r[2:1],dma_line_r[2:0],dma_byte_r[0]};
dma_mmc_data_r <= {dma_cc1_data_r[0][dma_byte_r],
dma_cc1_data_r[1][dma_byte_r],
dma_cc1_data_r[2][dma_byte_r],
dma_cc1_data_r[3][dma_byte_r],
dma_cc1_data_r[4][dma_byte_r],
dma_cc1_data_r[5][dma_byte_r],
dma_cc1_data_r[6][dma_byte_r],
dma_cc1_data_r[7][dma_byte_r]
};
dma_byte_r <= dma_byte_r + 1;
// advance to the next byte
if (&dma_byte_r) begin
dma_line_r[2:0] <= dma_line_r[2:0] + 1;
dma_cc1_addr_rd_r <= dma_cc1_addr_rd_r + dma_cc1_bpl_r;
end
dma_next_writestate_r <= &dma_byte_r ? (&dma_line_r[2:0] ? ST_DMA_IDLE : ST_DMA_TYPE1_READ) : ST_DMA_TYPE1_WRITE;
DMA_STATE <= ST_DMA_WRITE_END;
end
`endif
`ifdef DMA_TYPE2_ENABLE
// type2
ST_DMA_TYPE2_READ: begin
dma_mmc_wr_iram_r <= ~|(dma_byte_r & ~dma_comp_r);
//{dma_mmc_rom_r,dma_mmc_iram_r,dma_mmc_bram_r} <= {1'b0,1'b1,1'b0};
// compose BRF to iram write
dma_mmc_wr_addr_r <= {13'h0000,
DDA_r[10:7],
(|dma_cdma_r[`CDMA_DMACB] ? DDA_r[6] : dma_cc2_line_r[3]),
(dma_cdma_r[1] ? DDA_r[5] : dma_cdma_r[0] ? dma_cc2_line_r[3] : dma_byte_r[2] ),
(dma_cdma_r[1] ? dma_cc2_line_r[3] : dma_byte_r[1] ),
dma_cc2_line_r[2:0],
dma_byte_r[0]
};
dma_mmc_data_r <= {dma_cc2_line_r[0] ? BRF_r[8][dma_byte_r] : BRF_r[0][dma_byte_r],
dma_cc2_line_r[0] ? BRF_r[9][dma_byte_r] : BRF_r[1][dma_byte_r],
dma_cc2_line_r[0] ? BRF_r[10][dma_byte_r] : BRF_r[2][dma_byte_r],
dma_cc2_line_r[0] ? BRF_r[11][dma_byte_r] : BRF_r[3][dma_byte_r],
dma_cc2_line_r[0] ? BRF_r[12][dma_byte_r] : BRF_r[4][dma_byte_r],
dma_cc2_line_r[0] ? BRF_r[13][dma_byte_r] : BRF_r[5][dma_byte_r],
dma_cc2_line_r[0] ? BRF_r[14][dma_byte_r] : BRF_r[6][dma_byte_r],
dma_cc2_line_r[0] ? BRF_r[15][dma_byte_r] : BRF_r[7][dma_byte_r]
};
dma_byte_r <= dma_byte_r + 1;
if (&dma_byte_r) dma_cc2_line_r <= dma_cc2_line_r + 1;
dma_next_writestate_r <= &dma_byte_r ? ST_DMA_IDLE : ST_DMA_TYPE2_READ;
DMA_STATE <= ST_DMA_WRITE_END;
end
`endif
ST_DMA_READ_END: begin
if (~dma_mmc_rd_bram_r) begin
//dma_normal_prefetch_val_r <= 0;
//dma_data_r <= dma_normal_prefetch_dat_r[7:0];
DMA_STATE <= dma_next_readstate_r;
//if (dma_cc1_rd_r) dma_cc1_upper_r <= 0;
end
else if (mmc_dma_end) begin
//dma_normal_prefetch_val_r <= ~dma_mmc_addr_r[0] & dma_mmc_rom_r;
dma_mmc_rd_bram_r <= 0;
dma_data_r <= dma_mmc_rddata[7:0];
DMA_STATE <= dma_next_readstate_r;
end
//dma_normal_prefetch_dat_r <= dma_mmc_rddata[15:8];
if (~dma_mmc_rd_bram_r | mmc_dma_end) begin
dma_cc1_data_r[7] <= dma_mmc_rd_bram_r ? dma_mmc_rddata[7:0]
: dma_cdma_r[0] ? {dma_cc1_data_r[7][3:0],dma_cc1_data_r[7][7:4]}
: {dma_cc1_data_r[7][1:0],dma_cc1_data_r[7][7:6],dma_cc1_data_r[7][5:4],dma_cc1_data_r[7][3:2]}
;
// shift older data
for (i = 0; i < 7; i = i + 1) dma_cc1_data_r[i] <= dma_cc1_data_r[i+1];
end
end
ST_DMA_WRITE_END: begin
if (~dma_mmc_wr_iram_r) begin
DMA_STATE <= dma_next_writestate_r;
end
else if (mmc_dma_end) begin
dma_mmc_wr_iram_r <= 0;
DMA_STATE <= dma_next_writestate_r;
end
end
endcase
end
end
`endif
assign dma_mmc_cc1_en = dma_cc1_en_r;
assign dma_mmc_cc1_mask = dma_cc1_imask_r;
//-------------------------------------------------------------------
// VBD Pipeline
//-------------------------------------------------------------------
// The variable bit data pipeline provides a programmable shifted/masked
// interface to rom data. It triggers on MMIO reads and writes.
//
// There are two modes of operation:
// fixed - write address, loop (data read, control write)
// auto - write address, write control, [not currently supported]
parameter
ST_VBD_IDLE = 8'b00000001,
ST_VBD_READ = 8'b00000010,
ST_VBD_READ_END = 8'b00000100,
ST_VBD_SHIFT = 8'b00001000,
ST_VBD_ALL = 8'b11111111;
reg [7:0] VBD_STATE; initial VBD_STATE = ST_VBD_IDLE;
reg [23:0] VBA_r; initial VBA_r = 0;
reg [4:0] vbd_temp;
reg [3:0] vbd_vbit_r; initial vbd_vbit_r = 0;
reg vbd_trigger_r; initial vbd_trigger_r = 0;
reg vbd_update_r; initial vbd_update_r = 0;
reg [31:0] vbd_data_r;
reg vbd_active_r; initial vbd_active_r = 0;
`ifdef VBD_ENABLE
always @(posedge CLK) begin
if (RST) begin
vbd_mmc_rd_r <= 0;
VDA_r <= 0;
VDP_r <= 0;
vbd_vbit_r <= 0;
vbd_trigger_r <= 0;
vbd_update_r <= 0;
vbd_active_r <= 0;
VBD_STATE <= ST_VBD_IDLE;
end
else begin
// watch for triggers
// HL=0 trigger on VBA+2 and every VBD write. HL=1 trigger on VDP+1 data read and every VBD write.
vbd_trigger_r <= (VBD_r[`VBD_HL] && sa1_mmio_read_r[1] && snes_readbuf_mmio_addr_r[8:0] == ADDR_VDP+1) || (snes_writebuf_val_r && ((~VBD_r[`VBD_HL] && snes_writebuf_addr_r[8:0] == ADDR_VDA+2) || snes_writebuf_addr_r[8:0] == ADDR_VBD));
// HL=0 update on VBD write. needs to sync'ed with trigger to get new register value. this is done by adding the extra READ stage. HL=1 update on data written to VDP
vbd_update_r <= (snes_writebuf_val_r && snes_writebuf_addr_r[8:0] == ADDR_VBD && ~snes_writebuf_data_r[`VBD_HL]) || (VBD_STATE[clog2(ST_VBD_SHIFT)] && VBD_r[`VBD_HL]);
case (VBD_STATE)
ST_VBD_IDLE: begin
if (vbd_update_r) begin
vbd_temp = {1'b0,vbd_vbit_r} + {~|VBD_r[`VBD_VB],VBD_r[`VBD_VB]};
vbd_vbit_r <= vbd_temp[3:0];
VDA_r <= VDA_r[23:0] + {vbd_temp[4],1'b0};
end
else if (snes_writebuf_val_r) begin
if (snes_writebuf_addr_r[8:0] == ADDR_VDA+0) VDA_r[7 : 0] <= snes_writebuf_data_r;
else if (snes_writebuf_addr_r[8:0] == ADDR_VDA+1) VDA_r[15: 8] <= snes_writebuf_data_r;
else if (snes_writebuf_addr_r[8:0] == ADDR_VDA+2) begin VDA_r[23:16] <= snes_writebuf_data_r; vbd_vbit_r <= 0; end
end
if (vbd_trigger_r) begin
vbd_active_r <= 1;
VBD_STATE <= ST_VBD_READ;
end
end
ST_VBD_READ: begin
vbd_mmc_rd_r <= 1;
vbd_mmc_addr_r <= VDA_r;
VBD_STATE <= ST_VBD_READ_END;
end
ST_VBD_READ_END: begin
if (MMC_STATE[clog2(ST_MMC_VBD_END)]) begin
vbd_mmc_rd_r <= 0;
// TODO: use wire to support new mmc
vbd_data_r[31:0] <= mmc_data_r[31:0];
VBD_STATE <= ST_VBD_SHIFT;
end
end
ST_VBD_SHIFT: begin
VDP_r[15:0] <= vbd_data_r[31:0] >> vbd_vbit_r;
vbd_active_r <= 0;
VBD_STATE <= ST_VBD_IDLE;
end
endcase
end
end
`endif
//-------------------------------------------------------------------
// DECODER
//-------------------------------------------------------------------
reg [15:0] REG[7:0];
reg [15:0] REGS[7:0];
always @(*) begin
REG[`REG_Z] = 16'h0000;
REG[`REG_A] = A_r;
REG[`REG_X] = X_r;
REG[`REG_Y] = Y_r;
REG[`REG_S] = S_r;
REG[`REG_D] = D_r;
REG[`REG_B] = {8'h00,DBR_r};
REG[`REG_P] = {8'h00,P_r};
end
always @(*) begin
REGS[`REG_Z] = 16'h0000;
REGS[`REG_A] = A_r;
REGS[`REG_X] = X_r;
REGS[`REG_Y] = Y_r;
REGS[`REG_S] = {8'h00,PBR_r};
REGS[`REG_D] = D_r;
REGS[`REG_B] = {8'h00,DBR_r};
REGS[`REG_P] = {8'h00,P_r};
end
// need to take from the input so we get a clock
//wire [7:0] dec_addr = MMC_STATE[clog2(ST_MMC_ROM)] ? ROM_BUS_RDDATA[7:0] : mmc_data_r[7:0];
wire [7:0] dec_addr = exe_mmc_int ? 8'h00 : exe_fetch_byte_val ? exe_fetch_byte[7:0] : mmc_exe_end ? exe_mmc_rddata[7:0] : exe_fetch_data[7:0];
wire [31:0] dec_data;
`ifdef MK2
dec_table dec (
.clka(CLK), // input clka
.addra(dec_addr), // input [7 : 0] addra
.douta(dec_data) // output [31 : 0] douta
);
`endif
`ifdef MK3
dec_table dec (
.clock(CLK), // input clock
.address(dec_addr), // input [7 : 0] address
.q(dec_data) // output [31 : 0] q
);
`endif
//-------------------------------------------------------------------
// Interrupt Controller
//-------------------------------------------------------------------
// The interrupt controller handles sa1 irq and nmi interrupts.
// Interrupts can be observed at cycle boundaries and can't be
// interrupted with the exception of a nmi interrupting a irq.
reg int_pending_r; initial int_pending_r = 0;
reg int_nmi_r; initial int_nmi_r = 0;
reg [15:0] int_vector_r; initial int_vector_r = 0;
reg int_rti_r; initial int_rti_r = 0;
wire int_wai;
// lots of races to handle:
// - RTI needs to clear nmi interrupt
// - WAI write from execute and clear from interrupt edge (while in WAI state). Should have common support in mmc for interrupt active.
// - Set/Clear interrupt flag in register state.
always @(posedge CLK) begin
int_rti_r <= exe_dec_grp == `GRP_SPC && exe_dec_add_stk && !exe_dec_store;
if (RST) begin
int_pending_r <= 0;
int_nmi_r <= 0;
WAI_r <= 0;
end
else begin
// WAI_r can only be set in EXE_WAIT for WAI
if (EXE_STATE[clog2(ST_EXE_WAIT)] & pipeline_advance) begin
// check current pending. taking an interrupt will block nmi and avoid duplicate irq.
// pending is only set during the interrupt (break opcode) execution
if (int_pending_r) begin
int_pending_r <= 0;
end
else if (int_rti_r) begin
// clear current nmi on rti. this is either already zero or must be a nmi so unconditionally clear
int_nmi_r <= 0;
end
// check NMI
else if (~int_nmi_r) begin
if (CIE_r[`CIE_SA1_NMIEN] & CFR_r[`CFR_SA1_NMIFL]) begin
int_pending_r <= 1;
int_nmi_r <= 1;
int_vector_r <= CNV_r;
end
// check IRQ
else if (~P_r[`P_I]) begin
// TODO: timer
// register based interrupts
if ((CIE_r[`CIE_SA1_IRQEN] & CFR_r[`CFR_SA1_IRQFL]) | (CIE_r[`CIE_DMA_IRQEN] & CFR_r[`CFR_DMA_IRQFL])) begin
int_pending_r <= 1;
int_vector_r <= CIV_r;
end
end
end
end
// WAI set/clear
if (WAI_r & (CFR_r[`CFR_SA1_IRQFL] | CFR_r[`CFR_DMA_IRQFL] | CFR_r[`CFR_SA1_NMIFL])) begin
WAI_r <= 0;
end
else if (exe_wai) begin
WAI_r <= 1;
end
end
end
assign exe_wai = EXE_STATE[clog2(ST_EXE_EXECUTE)] & int_wai;
assign exe_mmc_int = int_pending_r;
//-------------------------------------------------------------------
// BCD
//-------------------------------------------------------------------
`ifdef BCD_ENABLE
reg [15:0] bcd_a_r;
reg [15:0] bcd_b_r;
reg [15:0] bcd_o_r;
reg [3:0] bcd_c_r;
reg [1:0] bcd_cnt_r; initial bcd_cnt_r = 3;
reg bcd_state_r; initial bcd_state_r = 0;
reg bcd_done_r; initial bcd_done_r = 0;
reg bcd_m_r; initial bcd_m_r = 0;
// exe inputs
reg exe_bcd_val_r; initial exe_bcd_val_r = 0;
reg [15:0] exe_bcd_a_r; initial exe_bcd_a_r = 0;
reg [15:0] exe_bcd_b_r; initial exe_bcd_b_r = 0;
reg exe_bcd_c_r; initial exe_bcd_c_r = 0;
reg exe_bcd_m_r; initial exe_bcd_m_r = 0;
wire [4:0] bcd_result;
always @(posedge CLK) begin
if (RST) begin
bcd_state_r <= 0;
bcd_done_r <= 0;
bcd_cnt_r <= 3;
end
else begin
if (~bcd_state_r) begin
bcd_done_r <= 0;
if (exe_bcd_val_r) begin
bcd_a_r <= exe_bcd_a_r;
bcd_b_r <= exe_bcd_b_r;
bcd_c_r[3] <= exe_bcd_c_r;
bcd_m_r <= exe_bcd_m_r;
bcd_state_r <= 1;
end
end
else begin
bcd_a_r <= {bcd_a_r[3:0],bcd_a_r[15:4]};
bcd_b_r <= {bcd_b_r[3:0],bcd_b_r[15:4]};
bcd_o_r[11:0] <= bcd_o_r[15:4];
bcd_c_r[2:0] <= bcd_c_r[3:1];
{bcd_c_r[3],bcd_o_r[15:12]} <= bcd_result[4:0] + bcd_adder(bcd_m_r, bcd_result[4], bcd_result[3:0]);
bcd_cnt_r <= bcd_cnt_r - 1;
bcd_done_r <= ~|bcd_cnt_r;
bcd_state_r <= |bcd_cnt_r;
end
end
end
assign bcd_result = bcd_a_r[3:0] + bcd_b_r[3:0] + bcd_c_r[3];
`endif
//-------------------------------------------------------------------
// EXECUTION PIPELINE
//-------------------------------------------------------------------
reg [31:0] exe_data_r;
reg [15:0] exe_fetch_data_r;
reg [23:0] exe_addr_r; initial exe_addr_r = 0;
reg [23:0] exe_mmc_addr_r; initial exe_mmc_addr_r = 0;
reg [1:0] exe_opsize_r; initial exe_opsize_r = 0;
reg [7:0] exe_opcode_r; initial exe_opcode_r = 0;
reg [23:0] exe_operand_r; initial exe_operand_r = 0;
reg [1:0] exe_fetch_size_r; initial exe_fetch_size_r = 0;
reg [15:0] exe_src_r; initial exe_src_r = 16'h0BAD;
reg [15:0] exe_dst_r; initial exe_dst_r = 16'h0BAD;
reg exe_control_r; initial exe_control_r = 0;
reg exe_load_r; initial exe_load_r = 0;
reg exe_store_r; initial exe_store_r = 0;
reg exe_data_word_r; initial exe_data_word_r = 0;
reg [15:0] exe_nextpc_r; initial exe_nextpc_r = 0;
reg [15:0] exe_nextpc_addr_r; initial exe_nextpc_addr_r = 0;
reg [15:0] exe_add_post_r; initial exe_add_post_r = 0;
reg exe_dst_p_r; initial exe_dst_p_r = 0;
reg [23:0] exe_target_r; initial exe_target_r = 0;
reg [15:0] exe_mod_r; initial exe_mod_r = 0;
reg [15:0] exe_a_r; initial exe_a_r = 0;
reg [15:0] exe_x_r; initial exe_x_r = 0;
reg [15:0] exe_y_r; initial exe_y_r = 0;
reg [15:0] exe_s_r; initial exe_s_r = 16'h01FF;
reg [15:0] exe_d_r; initial exe_d_r = 0;
reg [7:0] exe_dbr_r; initial exe_dbr_r = 0;
reg [7:0] exe_pbr_r; initial exe_pbr_r = 0;
reg [7:0] exe_p_r; initial exe_p_r = 0;
reg exe_e_r; initial exe_e_r = 1;
reg exe_active_r; initial exe_active_r = 0;
reg exe_mmc_state_exe_end_r; initial exe_mmc_state_exe_end_r = 0;
reg exe_prefetch_val_r; initial exe_prefetch_val_r = 0;
reg [7:0] exe_prefetch_r; initial exe_prefetch_r = 0;
reg exe_move_val_r; initial exe_move_val_r = 0;
wire exe_dpe = ~|D_r[7:0] & E_r;
wire exe_data_word = |({~P_r[`P_X],~P_r[`P_M]}&dec_data[`DEC_PRC]) | &dec_data[`DEC_PRC];
wire exe_dec_imm16 = (|({~P_r[`P_X],~P_r[`P_M]}&dec_data[`DEC_PRC]) & dec_data[`ADD_IMM]);
// temporary
reg [16:0] exe_result;
reg [16:0] add_result;
always @(posedge CLK) begin
`ifdef BCD_ENABLE
// drive BCD inputs
exe_bcd_a_r <= exe_src_r[15:0];
// invert for SBC
exe_bcd_b_r <= exe_opcode_r[7] ? ~exe_data_r[15:0] : exe_data_r[15:0];
exe_bcd_c_r <= P_r[`P_C];
exe_bcd_m_r <= exe_opcode_r[7];
`endif
if (RST) begin
EXE_STATE <= ST_EXE_IDLE;
PBR_r <= 0;
PC_r <= 0;
A_r <= 0;
X_r <= 0;
Y_r <= 0;
S_r[15:8] <= 1;
D_r <= 0;
DBR_r <= 0;
P_r <= 8'h34;
E_r <= 1;
//exe_fetch_addr_r <= 0;
//exe_addr_r <= 0;
//exe_mmc_addr_r <= 0;
exe_opsize_r <= 0;
exe_fetch_size_r <= 0;
exe_opcode_r <= 0;
exe_operand_r <= 0;
exe_decode_r <= 0;
//exe_src_r <= 16'h0BAD;
//exe_dst_r <= 16'h0BAD;
exe_control_r <= 0;
exe_pbr_r <= 0;
exe_nextpc_r <= 0;
exe_nextpc_addr_r <= 0;
exe_add_post_r <= 0;
exe_mmc_rd_r <= 0;
exe_mmc_wr_r <= 0;
//exe_mmc_data_r<= 0;
exe_mmc_long_r<= 0;
exe_mmc_byte_total_r <= 0;
exe_mmc_state_exe_end_r <= 0;
exe_active_r <= 0;
exe_prefetch_val_r <= 0;
exe_move_val_r <= 0;
`ifdef BCD_ENABLE
exe_bcd_val_r <= 0;
`endif
e2c_waitcnt_r <= 0;
end
else begin
case (EXE_STATE)
ST_EXE_IDLE: begin
if (~CCNT_r[`CCNT_SA1_RESB] & sa1_clock_en) begin
{PBR_r,PC_r} <= {8'h00,CRV_r};
exe_fetch_addr_r <= {8'h00,CRV_r};
exe_fetch_size_r <= 0;
exe_mmc_byte_total_r <= 1;
exe_data_word_r <= 0;
exe_mmc_long_r <= 0;
exe_mmc_dpe_r <= 0;
exe_opsize_r <= 0;
exe_active_r <= 1;
EXE_STATE <= ST_EXE_FETCH;
end
exe_prefetch_val_r <= 0;
exe_move_val_r <= 0;
e2c_waitcnt_r <= 0;
end
// FETCH
ST_EXE_FETCH: begin
exe_mmc_rd_r <= ~(int_pending_r | exe_prefetch_val_r | exe_move_val_r);
// only tell the mmc about 1 byte if its to rom. It still returns 2 which we will use if aligned.
// TODO: why is this slower?
//exe_mmc_byte_total_r <= `IS_ROM(exe_fetch_addr_r) ? 0 : 1;
exe_mmc_byte_total_r <= 1;
exe_mmc_state_exe_end_r <= 0;
e2c_waitcnt_r <= 0;
exe_move_val_r <= 0;
// fast move skips fetch
if (exe_move_val_r & ~int_pending_r) begin
// reset some state that was modified
exe_opsize_r <= `SZE_3;
exe_control_r <= exe_decode_r[`DEC_CONTROL];
exe_load_r <= exe_decode_r[`DEC_LOAD];
exe_store_r <= exe_decode_r[`DEC_STORE];
EXE_STATE <= ST_EXE_ADDRESS;
end
else begin
EXE_STATE <= ST_EXE_FETCH_END;
end
end
ST_EXE_FETCH_END: begin
// always stop the read at END
if (mmc_exe_end) begin
exe_mmc_rd_r <= 0;
exe_fetch_data_r <= exe_mmc_rddata[15:0];
end
// TODO: fill in other data sources
exe_mmc_state_exe_end_r <= mmc_exe_end | int_pending_r | exe_prefetch_val_r;
// The decode rom takes an additional clock.
if (exe_mmc_state_exe_end_r) begin
//exe_fetch_data_r <= int_pending_r ? 8'h00 : exe_prefetch_val_r ? exe_prefetch_r : exe_fetch_data_r;
if (~|exe_opsize_r) begin
exe_opcode_r <= exe_mmc_int ? 8'h00 : exe_prefetch_val_r ? exe_prefetch_r : exe_fetch_data_r[7:0];
// word size only affects immediate for fetch
exe_opsize_r <= dec_data[`DEC_SIZE] ^ {2{exe_dec_imm16}};
exe_control_r <= dec_data[`DEC_CONTROL];
exe_load_r <= dec_data[`DEC_LOAD];
exe_store_r <= dec_data[`DEC_STORE];
exe_decode_r <= dec_data;
exe_data_word_r <= exe_data_word;
exe_nextpc_addr_r <= PC_r + dec_data[`DEC_SIZE] + (exe_dec_imm16 ? 2 : 1);
// FIXME: fix latencies once perf problems are resolved
e2c_waitcnt_r <= 0;
//e2c_waitcnt_r <= dec_data[`DEC_LATENCY];
// `define ADD_MOD 27:26
exe_mod_r <= dec_data[27] ? 16'h0000 : dec_data[26] ? Y_r[15:0] : X_r[15:0];
// record the current PC and previous PC
debug_inst_addr_r <= {PBR_r,PC_r};
debug_inst_addr_prev_r <= debug_inst_addr_r;
end
exe_a_r <= A_r;
exe_x_r <= X_r;
exe_y_r <= Y_r;
exe_s_r <= S_r;
exe_d_r <= D_r;
exe_dbr_r <= DBR_r;
exe_pbr_r <= PBR_r;
exe_p_r <= P_r;
exe_e_r <= E_r;
`ifdef EXE_FAST_FETCH
// next state, address, and prefetch logic.
if (~|exe_opsize_r) begin
// initial decode
// `define DEC_SIZE 16:15
exe_operand_r[7:0] <= exe_fetch_data_r[15:8];
if (dec_data[16] | exe_dec_imm16 | (exe_fetch_addr_r[0] & dec_data[15])) begin
// 3,4 bytes or 2 misaligned bytes
// fetch the remainder of the instruction
exe_fetch_addr_r[15:0] <= {exe_fetch_addr_r[15:1] + 1,1'b0};
// this represents the next total byte size we are going to get (e.g., 3 or 4)
exe_fetch_size_r <= {1'b0,~exe_fetch_addr_r[0]};
exe_prefetch_val_r <= 0;
EXE_STATE <= ST_EXE_FETCH;
end
else begin
// 1 byte or 2 aligned bytes
// prefetch is valid if aligned 1 byte
exe_prefetch_val_r <= ~exe_fetch_addr_r[0] && (dec_data[`DEC_SIZE] == `SZE_1);
exe_prefetch_r <= exe_fetch_data_r[15:8];
EXE_STATE <= ST_EXE_ADDRESS;
end
end
else begin
// remaining bytes
// we get here for 2 misaligned 3 aligned (2 valid) or misaligned (1 valid) bytes.
case (exe_fetch_size_r)
// have 1 byte
`SZE_1: exe_operand_r[15:0] <= exe_fetch_data_r[15:0];
// have 2 bytes
`SZE_2: exe_operand_r[23:8] <= exe_fetch_data_r[15:0];
// have 3 bytes
`SZE_3: exe_operand_r[23:16] <= exe_fetch_data_r[7:0];
// have 4 bytes. not possible
`SZE_4: exe_operand_r[23:0] <= 24'hBADBAD;
endcase
// the only case where this matters is 3->5 bytes
exe_fetch_size_r[1] <= ~exe_fetch_size_r[1];
if (&exe_opsize_r && (exe_fetch_size_r == `SZE_1)) begin
// 1->3 (need 4)
// continue with aligned fetch. must already be aligned
exe_fetch_addr_r[15:0] <= {exe_fetch_addr_r[15:1] + 1,1'b0};
exe_prefetch_val_r <= 0;
EXE_STATE <= ST_EXE_FETCH;
end
else begin
// fetch is complete. 1->2, 1->3, 2->3, 2->4, 3->4
// check if prefetch available (overfetch)
exe_prefetch_val_r <= exe_fetch_size_r[0] ^ exe_opsize_r[0];
exe_prefetch_r <= exe_fetch_data_r[15:8];
EXE_STATE <= ST_EXE_ADDRESS;
end
end
`else
// handle 1 byte at a time
exe_fetch_size_r <= exe_fetch_size_r + 1;
exe_fetch_addr_r <= exe_fetch_addr_r + 1;
case (exe_fetch_size_r)
`SZE_1: begin end
`SZE_2: exe_operand_r[7 : 0] <= exe_prefetch_val_r ? exe_prefetch_r : exe_fetch_data_r[7:0];
`SZE_3: exe_operand_r[15: 8] <= exe_prefetch_val_r ? exe_prefetch_r : exe_fetch_data_r[7:0];
`SZE_4: exe_operand_r[23:16] <= exe_prefetch_val_r ? exe_prefetch_r : exe_fetch_data_r[7:0];
endcase
// TODO: the memory controller actually returns 2 sequential bytes independent of source, but we still want to force alignment.
exe_prefetch_val_r <= ~exe_prefetch_val_r & (~exe_fetch_addr_r[0] | ~`IS_ROM(exe_fetch_addr_r));
exe_prefetch_r <= exe_fetch_data_r[15:8];
EXE_STATE <= ~|exe_opsize_r ? (~|dec_data[`DEC_SIZE] ? ST_EXE_ADDRESS : ST_EXE_FETCH) : (exe_fetch_size_r == exe_opsize_r ? ST_EXE_ADDRESS : ST_EXE_FETCH);
`endif
end
end
// ADDRESSING MODE
ST_EXE_ADDRESS: begin
e2c_waitcnt_r <= 0;
exe_mmc_rd_r <= exe_dec_add_indirect;
exe_mmc_long_r <= exe_dec_add_long;
exe_mmc_byte_total_r <= {exe_dec_add_long,~exe_dec_add_long};
exe_mmc_dpe_r <= 0;
exe_dst_r <= REG[exe_dec_dst];
exe_src_r <= REG[exe_dec_src];
add_result = {1'b0,exe_operand_r[15:0]} + {1'b0,exe_mod_r};
case (exe_dec_add_bank)
`BNK_PBR: exe_addr_r[23:16] <= PBR_r;
`BNK_DBR: exe_addr_r[23:16] <= DBR_r + add_result[16]; // this covers the 3 types: Absolute, AbsoluteIndexedX, AbsoluteIndexedY. Always in the form operand[15:0] + 0/X/Y
`BNK_ZRO: exe_addr_r[23:16] <= 8'h00;
`BNK_O24: exe_addr_r[23:16] <= exe_operand_r[23:16] + (exe_dec_add_mod == `MOD_X16 ? add_result[16] : 0); // need to carry address into upper bits for AbsoluteLongIndexedX
endcase
case (exe_dec_add_base)
`ADD_O16: exe_addr_r[15:0] <= add_result[15:0]; //exe_operand_r[15:0] + exe_mod_r;
`ADD_DPR: exe_addr_r[15:0] <= D_r + {8'h00,exe_operand_r[7:0]} + exe_mod_r;
`ADD_PCR: exe_addr_r[15:0] <= exe_nextpc_addr_r + {(exe_dec_add_long ? exe_operand_r[15:8] : {8{exe_operand_r[7]}}),exe_operand_r[7:0]} + exe_mod_r;
`ADD_SPL: exe_addr_r[15:0] <= S_r + 1 + exe_mod_r;
`ADD_SMI: exe_addr_r[15:0] <= S_r - exe_data_word_r + exe_mod_r;
`ADD_SPR: exe_addr_r[15:0] <= S_r + {8'h00,exe_operand_r[7:0]} + exe_mod_r;
endcase
// initialize the operand data as the immediate field.
exe_data_r[15:0] <= exe_dec_add_imm ? exe_operand_r[15:0] : REGS[exe_dec_src];
exe_add_post_r <= (exe_dec_add_mod == `MOD_YPT ? Y_r[15:0] : 0);
exe_dst_p_r <= exe_dec_dst == `REG_P;
exe_nextpc_r <= exe_nextpc_addr_r;
EXE_STATE <= exe_dec_add_indirect ? ST_EXE_ADDRESS_END : ST_EXE_EXECUTE;
end
ST_EXE_ADDRESS_END: begin
if (mmc_exe_end) begin
exe_mmc_rd_r <= 0;
// [3:2] catches the two JMP/JSR indirects which use PBR. All other indirects are long (full 24b address) or use DBR.
add_result = {1'b0,exe_mmc_rddata[15:0]} + {1'b0,exe_add_post_r};
exe_addr_r[23:16] <= exe_dec_add_long ? (exe_mmc_rddata[23:16] + add_result[16]) : (&exe_opcode_r[3:2]) ? PBR_r : DBR_r;
exe_addr_r[15:0] <= add_result[15:0];
EXE_STATE <= ST_EXE_EXECUTE;
end
end
// EXECUTE
ST_EXE_EXECUTE: begin
e2c_waitcnt_r <= 0;
// generic handler for load/store
if (exe_load_r | exe_store_r) begin
exe_mmc_rd_r <= exe_load_r;
exe_mmc_wr_r <= ~exe_load_r;
exe_mmc_addr_r <= exe_addr_r;
exe_mmc_byte_total_r <= exe_data_word_r;
EXE_STATE <= ST_EXE_EXECUTE_END;
end
else begin
EXE_STATE <= ST_EXE_WAIT;
end
// save target address since it will be overwritten by JSL/JSR
exe_target_r <= exe_addr_r;
case (exe_dec_grp)
`GRP_PRI: begin
// TODO: deal with D bit
exe_result[16] = 0;
case (exe_opcode_r[7:5])
0: exe_result[15:0] = exe_src_r | exe_data_r; // ORA
1: exe_result[15:0] = exe_src_r & exe_data_r; // AND
2: exe_result[15:0] = exe_src_r ^ exe_data_r; // EOR
3: begin
`ifdef BCD_ENABLE
if (P_r[`P_D]) begin
if (~exe_load_r) begin
exe_bcd_val_r <= |bcd_cnt_r & ~bcd_done_r;
if (~bcd_done_r) begin
// wait on bcd state machine if not done
exe_mmc_wr_r <= 0;
EXE_STATE <= ST_EXE_EXECUTE;
end
end
// NOTE: this won't set the overflow flag properly
exe_result[16:0] = exe_data_word_r ? {bcd_c_r[3],bcd_o_r[15:0]} : {8'h00,bcd_c_r[1],bcd_o_r[7:0]};
end
else
`endif
exe_result[16:0] = exe_data_word_r ? {1'b0,exe_src_r[15:0]} + {1'b0,exe_data_r[15:0]} + P_r[`P_C] : {9'h000,exe_src_r[7:0]} + {9'h000,exe_data_r[7:0]} + P_r[`P_C]; // ADC
end
//4: // STA
5: exe_result[15:0] = exe_data_r; // LDA
//6: // CMP
//7: exe_result[16:0] = exe_data_word_r ? {1'b0,exe_src_r[15:0]} + ~{1'b0,exe_data_r[15:0]} + P_r[`P_C] : {9'h000,exe_src_r[7:0]} + ~{9'h000,exe_data_r[7:0]} + P_r[`P_C];// SBC
7: begin
`ifdef BCD_ENABLE
if (P_r[`P_D]) begin
if (~exe_load_r) begin
exe_bcd_val_r <= |bcd_cnt_r & ~bcd_done_r;
if (~bcd_done_r) begin
// wait on bcd state machine if not done
exe_mmc_wr_r <= 0;
EXE_STATE <= ST_EXE_EXECUTE;
end
end
// NOTE: this won't set the overflow flag properly
exe_result[16:0] = exe_data_word_r ? {bcd_c_r[3],bcd_o_r[15:0]} : {8'h00,bcd_c_r[1],bcd_o_r[7:0]};
end
else
`endif
exe_result[16:0] = exe_data_word_r ? {1'b0,exe_src_r[15:0]} + {1'b0,~exe_data_r[15:0]} + P_r[`P_C] : {9'h000,exe_src_r[7:0]} + {9'h000,~exe_data_r[7:0]} + P_r[`P_C];// SBC
end
//default: exe_result[15:0] = 0;
endcase
exe_a_r <= {exe_data_word_r ? exe_result[15:8] : exe_src_r[15:8], exe_result[7:0]};
exe_p_r[`P_N] <= exe_data_word_r ? exe_result[15] : exe_result[7];
exe_p_r[`P_Z] <= exe_data_word_r ? ~|exe_result[15:0] : ~|exe_result[7:0];
if (&exe_opcode_r[6:5]) begin
// input data gets inverted for SBC
exe_p_r[`P_V] <= exe_data_word_r ? (~(exe_src_r[15] ^ exe_opcode_r[7] ^ exe_data_r[15]) & (exe_src_r[15] ^ exe_result[15])) : (~(exe_src_r[7] ^ exe_opcode_r[7] ^ exe_data_r[7]) & (exe_src_r[7] ^ exe_result[7]));
exe_p_r[`P_C] <= exe_data_word_r ? exe_result[16] : exe_result[8];
end
end
`GRP_RMW: begin
exe_result[16] = 0;
case (exe_opcode_r[7:5])
0: exe_result[16:0] = {exe_data_r[15:0],1'b0}; // ASL
1: exe_result[16:0] = {exe_data_r[15:0],P_r[`P_C]}; // ROL
2: exe_result[16:0] = exe_data_word_r ? {exe_data_r[0],1'b0,exe_data_r[15:1]} : {8'h00,exe_data_r[0],1'b0,exe_data_r[7:1]}; // LSR
3: exe_result[16:0] = exe_data_word_r ? {exe_data_r[0],P_r[`P_C],exe_data_r[15:1]} : {8'h00,exe_data_r[0],P_r[`P_C],exe_data_r[7:1]}; // ROR
//4: // STX,STY
//5: // -
6: exe_result[15:0] = exe_data_word_r ? (exe_data_r[15:0]-1) : (exe_data_r[7:0]-1); // DEC
7: exe_result[15:0] = exe_data_word_r ? (exe_data_r[15:0]+1) : (exe_data_r[7:0]+1); // INC
default: exe_result[15:0] = 0;
endcase
if (~exe_store_r) begin
exe_a_r <= {exe_data_word_r ? exe_result[15:8] : exe_src_r[15:8], exe_result[7:0]};
end
// data for store
exe_mmc_data_r[15:0] <= exe_result[15:0];
exe_p_r[`P_N] <= exe_data_word_r ? exe_result[15] : exe_result[7];
exe_p_r[`P_Z] <= exe_data_word_r ? ~|exe_result[15:0] : ~|exe_result[7:0];
if (~exe_opcode_r[7]) begin
exe_p_r[`P_C] <= exe_data_word_r ? exe_result[16] : exe_result[8];
end
end
`GRP_CBR: begin
exe_control_r <= exe_dec_src[2] ? ~P_r[{{2{exe_dec_src[1]}},exe_dec_src[0]}] : P_r[{{2{exe_dec_src[1]}},exe_dec_src[0]}];
end
`GRP_JMP: begin
if (exe_dec_add_stk) begin
// stack
if (exe_store_r) begin
// JSR,JSL
exe_mmc_addr_r <= {8'h00,(S_r - {exe_dec_add_long,~exe_dec_add_long})};
exe_mmc_data_r[23:16] <= PBR_r;
exe_mmc_data_r[15:0] <= exe_nextpc_r - 1;
exe_mmc_byte_total_r <= {exe_dec_add_long,~exe_dec_add_long};
exe_s_r <= S_r - {1'b1,exe_dec_add_long};
end
else begin
// RTS,RTL
exe_mmc_byte_total_r <= {exe_dec_add_long,~exe_dec_add_long};
exe_s_r <= S_r + {1'b1,exe_dec_add_long};
exe_target_r[23:16] <= exe_dec_add_long ? exe_data_r[23:16] : PBR_r;
exe_target_r[15:0] <= exe_data_r[15:0] + 1;
end
end
end
`GRP_PHS: begin
exe_mmc_data_r[15:0] <= exe_data_r[15:0];
if (exe_dec_add_stk) exe_s_r <= S_r - (exe_data_word_r ? 2 : 1);
EXE_STATE <= ST_EXE_EXECUTE_END;
end
`GRP_PLL: begin
case (exe_dec_dst)
//`REG_Z: if (P_r[`P_M]) exe_a_r[7:0] <= 0; else exe_a_r[15:0] <= 0;
`REG_A: if (exe_data_word_r) exe_a_r[15:0] <= exe_data_r[15:0]; else exe_a_r[7:0] <= exe_data_r[7:0];
`REG_X: if (exe_data_word_r) exe_x_r[15:0] <= exe_data_r[15:0]; else exe_x_r[7:0] <= exe_data_r[7:0];
`REG_Y: if (exe_data_word_r) exe_y_r[15:0] <= exe_data_r[15:0]; else exe_y_r[7:0] <= exe_data_r[7:0];
`REG_S: exe_s_r <= exe_data_r[15:0];
`REG_D: exe_d_r <= exe_data_r[15:0];
`REG_B: exe_dbr_r <= exe_data_r[7:0];
`REG_P: exe_p_r <= {exe_data_r[7:6],exe_data_r[5:4]|{2{E_r}},exe_data_r[3:0]};
default: begin end
endcase
if (~exe_dst_p_r) begin
exe_p_r[`P_N] <= exe_data_word_r ? exe_data_r[15] : exe_data_r[7];
exe_p_r[`P_Z] <= exe_data_word_r ? ~|exe_data_r[15:0] : ~|exe_data_r[7:0];
end
else if (exe_data_r[`P_X] | E_r) begin
exe_x_r[15:8] <= 0;
exe_y_r[15:8] <= 0;
end
if (exe_dec_add_stk) exe_s_r <= S_r + (exe_data_word_r ? 2 : 1);
end
`GRP_CMP: begin
if (~exe_opcode_r[6]) begin
// BIT
exe_result = exe_dst_r & exe_data_r;
// BIT with immediate operand doesn't set N or V
if (~exe_dec_add_imm) begin
exe_p_r[`P_V] <= exe_data_word_r ? exe_data_r[14] : exe_data_r[6];
exe_p_r[`P_N] <= exe_data_word_r ? exe_data_r[15] : exe_data_r[7];
end
exe_p_r[`P_Z] <= exe_data_word_r ? ~|exe_result[15:0] : ~|exe_result[7:0];
end
else begin
// CMP, CPX, CPY
if (exe_data_word_r) exe_result[16:0] = {1'b0,exe_dst_r[15:0]} - {1'b0,exe_data_r[15:0]};
else exe_result[8:0] = {1'b0,exe_dst_r[7:0]} - {1'b0,exe_data_r[7:0]};
exe_p_r[`P_N] <= exe_data_word_r ? exe_result[15] : exe_result[7];
exe_p_r[`P_Z] <= exe_data_word_r ? ~|exe_result[15:0] : ~|exe_result[7:0];
exe_p_r[`P_C] <= exe_data_word_r ? ~exe_result[16] : ~exe_result[8];
end
end
`GRP_STS: begin
if (exe_opcode_r[1]) begin
if (exe_opcode_r[5]) begin
// SEP
exe_p_r <= exe_p_r | exe_operand_r[7:0];
if (P_r[`P_X] | exe_operand_r[`P_X]) begin
exe_x_r[15:8] <= 0;
exe_y_r[15:8] <= 0;
end
end
else begin
// REP
exe_p_r <= exe_p_r & {~exe_operand_r[7:6],(~exe_operand_r[5:4])|{2{E_r}},~exe_operand_r[3:0]};
end
end
else begin
case (exe_opcode_r[7:6])
0: exe_p_r[`P_C] <= exe_opcode_r[5];
1: exe_p_r[`P_I] <= exe_opcode_r[5];
2: exe_p_r[`P_V] <= 0; // SEV does not exist and won't match with STS
3: exe_p_r[`P_D] <= exe_opcode_r[5];
endcase
end
end
`GRP_MOV: begin
// TODO: apply correct latency
exe_dbr_r <= exe_operand_r[7:0];
if (exe_load_r) begin
exe_mmc_addr_r <= {exe_operand_r[15:8], exe_src_r[15:0]};
end
else begin
exe_mmc_addr_r <= {exe_operand_r[7:0], exe_dst_r[15:0]};
end
// TODO: change this to use exe_data_word_r
if (P_r[`P_X]) begin
exe_x_r[7:0] <= exe_src_r[7:0] + (exe_opcode_r[4] ? 1 : -1);
exe_y_r[7:0] <= exe_dst_r[7:0] + (exe_opcode_r[4] ? 1 : -1);
end
else begin
exe_x_r[15:0] <= exe_src_r[15:0] + (exe_opcode_r[4] ? 1 : -1);
exe_y_r[15:0] <= exe_dst_r[15:0] + (exe_opcode_r[4] ? 1 : -1);
end
exe_a_r <= A_r - 1;
exe_control_r <= |A_r;
exe_target_r <= {PBR_r,PC_r};
exe_mmc_data_r[7:0] <= exe_data_r[7:0];
`ifdef EXE_FAST_MOVE
// someone could have the mov perform self modifying code on itself and break this. could qualify it as rom address to fix that.
exe_move_val_r <= |A_r & `IS_ROM(exe_fetch_addr_r); // assume that if last byte was in rom the whole thing was in rom
`endif
// END takes care of exit
EXE_STATE <= ST_EXE_EXECUTE_END;
end
`GRP_TXR: begin
exe_result[15:0] = {exe_data_word_r ? exe_src_r[15:8] : exe_dst_r[15:8], exe_src_r[7:0]};
// register output
case (exe_dec_dst)
`REG_A: exe_a_r[15:0] <= exe_result[15:0];
`REG_X: exe_x_r[15:0] <= exe_result[15:0];
`REG_Y: exe_y_r[15:0] <= exe_result[15:0];
`REG_S: exe_s_r[15:0] <= {E_r ? 8'h01 : exe_result[15:8],exe_result[7:0]};
`REG_D: exe_d_r[15:0] <= exe_result[15:0];
endcase
// condition codes
if (exe_dec_dst != `REG_S) begin
exe_p_r[`P_N] <= exe_data_word_r ? exe_result[15] : exe_result[7];
exe_p_r[`P_Z] <= exe_data_word_r ? ~|exe_result[15:0] : ~|exe_result[7:0];
end
end
`GRP_SMP: begin
if (~exe_data_word_r) begin
exe_result[7:0] = ((exe_opcode_r[4] & ~exe_opcode_r[5]) | (~exe_opcode_r[4] & (exe_opcode_r[6] ^ exe_opcode_r[1]))) ? exe_src_r[7:0] + 1 : exe_src_r[7:0] - 1;
// register output
if (exe_opcode_r[4]) exe_a_r[7:0] <= exe_result[7:0];
else if (exe_opcode_r[5] ^ exe_opcode_r[1]) exe_x_r[7:0] <= exe_result[7:0];
else exe_y_r[7:0] <= exe_result[7:0];
// condition codes
exe_p_r[`P_N] <= exe_result[7];
exe_p_r[`P_Z] <= ~|exe_result[7:0];
end
else begin
exe_result[15:0] = ((exe_opcode_r[4] & ~exe_opcode_r[5]) | (~exe_opcode_r[4] & (exe_opcode_r[6] ^ exe_opcode_r[1]))) ? exe_src_r[15:0] + 1 : (exe_src_r[15:0] - 1);
// register output
if (exe_opcode_r[4]) exe_a_r[15:0] <= exe_result[15:0];
else if (exe_opcode_r[5] ^ exe_opcode_r[1]) exe_x_r[15:0] <= exe_result[15:0];
else exe_y_r[15:0] <= exe_result[15:0];
// condition codes
exe_p_r[`P_N] <= exe_result[15];
exe_p_r[`P_Z] <= ~|exe_result[15:0];
end
end
`GRP_SPC: begin
// BRK, COP, STP, WAI, RTI
if (exe_opcode_r[7]^exe_opcode_r[6]) begin
// RTI
exe_target_r <= {(E_r ? exe_pbr_r : exe_data_r[31:24]),exe_data_r[23:8]};
exe_p_r <= exe_data_r[7:0];
exe_s_r <= S_r + {~E_r,E_r,E_r};
exe_mmc_byte_total_r <= {1'b1,~E_r};
if (exe_data_r[`P_X]) begin
exe_x_r[15:8] <= 0;
exe_y_r[15:8] <= 0;
end
end
else if (exe_opcode_r[6]) begin
// STP,WAI
exe_active_r <= ~exe_opcode_r[4];
end
else begin
// COP/BRK
if (exe_load_r) begin
// interrupt will read BRK vector from memory
exe_mmc_addr_r <= {16'h00FF,3'h7,E_r,E_r,1'b1,~exe_opcode_r[1],1'b0};
end
else begin
if (~int_pending_r) exe_target_r <= {8'h00,exe_data_r[15:0]};
else exe_target_r <= {8'h00,int_vector_r};
exe_s_r <= S_r - {~E_r,E_r,E_r};
exe_p_r[`P_I] <= 1;
exe_p_r[`P_D] <= 0;
exe_mmc_addr_r <= {8'h00,S_r - {1'b1,~E_r}};
exe_mmc_data_r <= {PBR_r,(int_pending_r ? PC_r[15:0] : exe_nextpc_r[15:0]),P_r};
exe_mmc_byte_total_r <= {1'b1,~E_r};
end
end
end
`GRP_STK: begin
// PEA, PER, PEI
// non-indirect will store data at stack address
// indirect will first load, return here, and update data to be stored
// need to update the address for PEI. The others already have the correct address.
if (~exe_load_r) exe_mmc_addr_r <= {8'h00,S_r-1};
exe_mmc_data_r[15:0] <= exe_opcode_r[1] ? (exe_nextpc_r[15:0] + exe_operand_r[15:0]) : exe_opcode_r[5] ? exe_operand_r[15:0] : exe_data_r[15:0];
exe_s_r <= S_r - 2;
end
`GRP_XCH: begin
if (exe_opcode_r[4]) begin
exe_p_r[`P_C] <= E_r;
exe_e_r <= P_r[`P_C];
if (P_r[`P_C]) begin
exe_p_r[`P_M] <= 1;
exe_p_r[`P_X] <= 1;
exe_x_r[15:8] <= 0;
exe_y_r[15:8] <= 0;
end
end
else begin
exe_result[15:0] = {exe_src_r[7:0],exe_src_r[15:8]};
// register output
exe_a_r[15:0] <= exe_result[15:0];
// condition codes
exe_p_r[`P_N] <= exe_result[7];
exe_p_r[`P_Z] <= ~|exe_result[7:0];
end
end
`GRP_TST: begin
case (exe_opcode_r[4])
0: exe_result = exe_data_r[15:0] | exe_src_r[15:0];
1: exe_result = exe_data_r[15:0] & ~exe_src_r[15:0];
endcase
exe_mmc_data_r[15:0] <= exe_result[15:0];
// TSB/TRB are unique in that the Z flag is only set based on the logical and of the memory location and A
exe_p_r[`P_Z] <= exe_data_word_r ? ~|(exe_data_r[15:0] & exe_src_r[15:0]) : ~|(exe_data_r[7:0] & exe_src_r[7:0]);
end
endcase
end
ST_EXE_EXECUTE_END: begin
e2c_waitcnt_r <= 0;
if (mmc_exe_end) begin
exe_mmc_rd_r <= 0;
exe_mmc_wr_r <= 0;
exe_load_r <= 0;
if (exe_load_r) exe_data_r <= exe_mmc_rddata;
// return to EXECUTE if there are still work to do
EXE_STATE <= exe_load_r ? ST_EXE_EXECUTE : ST_EXE_WAIT;
end
end
ST_EXE_WAIT: begin
e2c_waitcnt_r <= 0;
if (pipeline_advance) begin
{PBR_r,PC_r} <= exe_control_r ? exe_target_r : {exe_pbr_r,exe_nextpc_r};
exe_fetch_addr_r <= exe_control_r ? exe_target_r : {exe_pbr_r,exe_nextpc_r};
exe_fetch_size_r <= 0;
exe_mmc_byte_total_r <= 1;
// will be assigned properly on fast move
exe_opsize_r <= 0;
// TODO: resetting the following is really only useful debug.
exe_mmc_long_r <= 0;
exe_mmc_dpe_r <= 0;
if (~exe_move_val_r) begin
exe_opcode_r <= 0;
exe_operand_r <= 0;
end
// invalidate the prefetch on a taken control instruction
if (exe_control_r) exe_prefetch_val_r <= 0;
// write register state
A_r <= exe_a_r;
X_r <= exe_x_r;
Y_r <= exe_y_r;
S_r <= exe_s_r;
D_r <= exe_d_r;
DBR_r <= exe_dbr_r;
P_r <= exe_p_r;
E_r <= exe_e_r;
// reset internal PCs to help with debugging
exe_nextpc_r <= 0;
EXE_STATE <= (exe_active_r & ~CCNT_r[`CCNT_SA1_RESB]) ? ST_EXE_FETCH : ST_EXE_IDLE;
end
end
endcase
end
end
assign int_wai = (exe_opcode_r == 8'hCB);
assign exe_mmc_addr = EXE_STATE[clog2(ST_EXE_FETCH_END)] ? exe_fetch_addr_r : EXE_STATE[clog2(ST_EXE_ADDRESS_END)] ? exe_addr_r : exe_mmc_addr_r;
assign exe_fetch_byte_val = exe_prefetch_val_r;
assign exe_fetch_move = exe_move_val_r;
assign exe_fetch_byte = exe_prefetch_r;
assign exe_fetch_data = exe_fetch_data_r[7:0];
`ifdef DEBUG
// breakpoints
reg brk_inst_rd_rom_m1;
reg brk_inst_rd_ram_m1;
reg brk_data_rd_rom_m1;
reg brk_data_rd_ram_m1;
reg brk_data_wr_ram_m1;
reg [23:0] brk_addr_r;
always @(posedge CLK) begin
if (RST) begin
brk_inst_rd_rom_m1 <= 0;
brk_inst_rd_ram_m1 <= 0;
brk_data_rd_rom_m1 <= 0;
brk_data_rd_ram_m1 <= 0;
brk_data_wr_ram_m1 <= 0;
brk_inst_rd_byte <= 0;
brk_data_rd_byte <= 0;
brk_data_wr_byte <= 0;
brk_inst_rd_addr <= 0;
brk_data_rd_addr <= 0;
brk_data_wr_addr <= 0;
brk_stop <= 0;
brk_error <= 0;
brk_addr_r <= 0;
end
else begin
//brk_inst_rd_rom_m1 <= (|(ROM_STATE & ST_ROM_FETCH_RD)) && !rom_bus_rrq_r && ROM_BUS_RDY;
//brk_inst_rd_ram_m1 <= (|(RAM_STATE & ST_RAM_FETCH_RD)) && !ram_bus_rrq_r && RAM_BUS_RDY;
//brk_data_rd_rom_m1 <= (|(ROM_STATE & ST_ROM_DATA_RD)) && !rom_bus_rrq_r && ROM_BUS_RDY;
//brk_data_rd_ram_m1 <= (|(RAM_STATE & ST_RAM_DATA_RD)) && !ram_bus_rrq_r && RAM_BUS_RDY;
//brk_data_wr_ram_m1 <= (|(RAM_STATE & ST_RAM_DATA_WR)) && !ram_bus_wrq_r && RAM_BUS_RDY;
//brk_inst_rd_byte <= pipeline_advance ? 0 : brk_inst_rd_rom_m1 ? (rom_bus_data_r == CONFIG_DATA_WATCH) : brk_inst_rd_ram_m1 ? (ram_bus_data_r == CONFIG_DATA_WATCH) : brk_inst_rd_byte;
//brk_data_rd_byte <= pipeline_advance ? 0 : brk_data_rd_rom_m1 ? (rom_bus_data_r == CONFIG_DATA_WATCH) : brk_data_rd_ram_m1 ? (ram_bus_data_r == CONFIG_DATA_WATCH) : brk_data_rd_byte;
//brk_data_wr_byte <= pipeline_advance ? 0 : brk_data_wr_ram_m1 ? (RAMWRBUF_r == CONFIG_DATA_WATCH) : brk_data_wr_byte;
brk_inst_rd_addr <= (debug_inst_addr_r == brk_addr_r);
brk_data_rd_addr <= EXE_STATE[clog2(ST_EXE_EXECUTE_END)] && (exe_mmc_addr_r == brk_addr_r) && exe_mmc_rd_r && (!config_r[2][0] || mmc_data_r[7:0] == CONFIG_DATA_WATCH);
brk_data_wr_addr <= EXE_STATE[clog2(ST_EXE_EXECUTE_END)] && (exe_mmc_addr_r == brk_addr_r) && exe_mmc_wr_r && (!config_r[2][0] || exe_mmc_data_r[7:0] == CONFIG_DATA_WATCH);
brk_stop <= EXE_STATE[clog2(ST_EXE_EXECUTE)] && (exe_opcode_r == 8'hDB || exe_opcode_r == 8'hCB || int_pending_r);
brk_error <= EXE_STATE[clog2(ST_EXE_EXECUTE)] && (exe_opcode_r == 8'h00);
brk_addr_r <= CONFIG_ADDR_WATCH[23:0];
end
end
`endif
// performance counter
reg cycle_wait_r;
reg dma_active_r;
always @(posedge CLK) begin
dma_active_r <= dma_cc1_active_r | dma_normal_pri_active_r | vbd_active_r;
`ifdef DEBUG
if (sa1_clock_en & ~|exe_waitcnt_r & EXE_STATE[clog2(ST_EXE_WAIT)] & ~step_r) cycle_wait_r <= 1;
else if (pipeline_advance) cycle_wait_r <= 0;
if (RST) begin
sa1_cycle_cnt_r <= 0;
end
else if ((~EXE_STATE[clog2(ST_EXE_WAIT)] | ~cycle_wait_r) & ~EXE_STATE[clog2(ST_EXE_IDLE)]) begin
sa1_cycle_cnt_r <= sa1_cycle_cnt_r + 1;
end
`endif
end
assign pipeline_advance = sa1_clock_en & ~|exe_waitcnt_r & EXE_STATE[clog2(ST_EXE_WAIT)] & step_r & ~dma_active_r & ~WAI_r;
//-------------------------------------------------------------------
// DEBUG OUTPUT
//-------------------------------------------------------------------
`ifdef DEBUG
wire [7:0] dbg_reg_dout;
dbg_state state (
.clka(CLK), // input clka
//.wea(~addr_in_r[7] & SNES_WR_end & `IS_MMIO(addr_in_r)), // input [0 : 0] wea
//.addra(addr_in_r[6:0]), // input [6 : 0] addra
//.dina(data_in_r), // input [7 : 0] dina
.wea(~|snes_writebuf_addr_r[8:7] & snes_writebuf_val_r), // input [0 : 0] wea
.addra(snes_writebuf_addr_r[6:0]), // input [6 : 0] addra
.dina(snes_writebuf_data_r), // input [7 : 0] dina
.clkb(CLK), // input clkb
.addrb(pgm_addr_r[6:0]), // input [6 : 0] addrb
.doutb(dbg_reg_dout) // output [7 : 0] doutb
);
reg [7:0] pgmpre_out[3:0];
reg [7:0] pgmdata_out; //initial pgmdata_out_r = 0;
always @(posedge CLK) begin
if (~pgm_addr_r[11]) pgmdata_out <= pgmpre_out[pgm_addr_r[9:8]];
`ifdef DEBUG_IRAM
else if (~snes_writebuf_iram_r & ~snes_readbuf_iram_r) pgmdata_out <= snes_iram_dout;
`endif
if (~pgm_addr_r[11]) begin
case (pgm_addr_r[9:8])
2'h0: case (pgm_addr_r[7:0])
// 00-7F MMIO
ADDR_CCNT ,
ADDR_SIE ,
ADDR_SIC ,
ADDR_CRV ,
ADDR_CRV+1 ,
ADDR_CNV ,
ADDR_CNV+1 ,
ADDR_CIV ,
ADDR_CIV+1 ,
ADDR_SCNT ,
ADDR_CIE ,
ADDR_CIC ,
ADDR_SNV ,
ADDR_SNV+1 ,
ADDR_SIV ,
ADDR_SIV+1 ,
`ifdef DEBUG_MMIO
ADDR_TMC ,
ADDR_CTR ,
ADDR_HCNT ,
ADDR_HCNT+1,
ADDR_VCNT ,
ADDR_VCNT+1,
ADDR_CXB ,
ADDR_DXB ,
ADDR_EXB ,
ADDR_FXB ,
ADDR_BMAPS ,
ADDR_BMAP ,
ADDR_SWBE ,
ADDR_CWBE ,
ADDR_BWPA ,
ADDR_SIWP ,
ADDR_CIWP ,
ADDR_DCNT ,
ADDR_CDMA ,
ADDR_DSA ,
ADDR_DSA+1 ,
ADDR_DSA+2 ,
ADDR_DDA ,
ADDR_DDA+1 ,
ADDR_DDA+2 ,
ADDR_DTC ,
ADDR_BBF ,
ADDR_BRF0 ,
ADDR_BRF1 ,
ADDR_BRF2 ,
ADDR_BRF3 ,
ADDR_BRF4 ,
ADDR_BRF5 ,
ADDR_BRF6 ,
ADDR_BRF7 ,
ADDR_BRF8 ,
ADDR_BRF9 ,
ADDR_BRFA ,
ADDR_BRFB ,
ADDR_BRFC ,
ADDR_BRFD ,
ADDR_BRFE ,
ADDR_BRFF ,
ADDR_MCNT ,
ADDR_MA ,
ADDR_MA+1 ,
ADDR_MB ,
ADDR_MB+1 ,
ADDR_VBD ,
ADDR_VDA ,
ADDR_VDA+1 ,
ADDR_VDA+2 : pgmpre_out[0] <= dbg_reg_dout;
8'h60+ADDR_SFR : pgmpre_out[0] <= SFR_r;
8'h60+ADDR_CFR : pgmpre_out[0] <= CFR_r;
`endif
`ifdef DEBUG_EXT
8'h60+ADDR_HCR : pgmpre_out[0] <= HCR_r[7:0]; // $2
8'h60+ADDR_HCR+1 : pgmpre_out[0] <= HCR_r[15:8]; // $2
8'h60+ADDR_VCR : pgmpre_out[0] <= VCR_r[7:0]; // $2
8'h60+ADDR_VCR+1 : pgmpre_out[0] <= VCR_r[15:8]; // $2
8'h60+ADDR_MR : pgmpre_out[0] <= MR_r[7:0]; // $5
8'h60+ADDR_MR+1 : pgmpre_out[0] <= MR_r[15:8]; // $5
8'h60+ADDR_MR+2 : pgmpre_out[0] <= MR_r[23:16]; // $5
8'h60+ADDR_MR+3 : pgmpre_out[0] <= MR_r[31:24]; // $5
8'h60+ADDR_MR+4 : pgmpre_out[0] <= MR_r[39:32]; // $5
8'h60+ADDR_OF : pgmpre_out[0] <= OF_r;
8'h60+ADDR_VDP : pgmpre_out[0] <= VDP_r[7:0]; // $2
8'h60+ADDR_VDP+1 : pgmpre_out[0] <= VDP_r[15:8]; // $2
8'h60+ADDR_VC : pgmpre_out[0] <= VC_r;
`endif
// 80-9F ARCH STATE
8'h80 : pgmpre_out[0] <= A_r[7:0];
8'h81 : pgmpre_out[0] <= A_r[15:8];
8'h82 : pgmpre_out[0] <= X_r[7:0];
8'h83 : pgmpre_out[0] <= X_r[15:8];
8'h84 : pgmpre_out[0] <= Y_r[7:0];
8'h85 : pgmpre_out[0] <= Y_r[15:8];
8'h86 : pgmpre_out[0] <= S_r[7:0];
8'h87 : pgmpre_out[0] <= S_r[15:8];
8'h88 : pgmpre_out[0] <= D_r[7:0];
8'h89 : pgmpre_out[0] <= D_r[15:8];
8'h8A : pgmpre_out[0] <= PC_r[7:0];
8'h8B : pgmpre_out[0] <= PC_r[15:8];
8'h8C : pgmpre_out[0] <= PBR_r;
8'h8D : pgmpre_out[0] <= DBR_r;
8'h8E : pgmpre_out[0] <= P_r;
8'h8F : pgmpre_out[0] <= E_r;
8'h90 : pgmpre_out[0] <= MDR_r;
8'h91 : pgmpre_out[0] <= WAI_r;
`ifdef DEBUG_MMC
// A0-BF MMC
8'hA0 : pgmpre_out[0] <= MMC_STATE;
8'hA1 : pgmpre_out[0] <= mmc_addr_r[7:0];
8'hA2 : pgmpre_out[0] <= mmc_addr_r[15:8];
8'hA3 : pgmpre_out[0] <= mmc_addr_r[23:16];
8'hA4 : pgmpre_out[0] <= mmc_data_r[7:0];
8'hA5 : pgmpre_out[0] <= mmc_data_r[15:8];
8'hA6 : pgmpre_out[0] <= mmc_data_r[23:16];
8'hA7 : pgmpre_out[0] <= mmc_data_r[31:24];
8'hA8 : pgmpre_out[0] <= mmc_wr_r;
8'hA9 : pgmpre_out[0] <= mmc_byte_r;
8'hAA : pgmpre_out[0] <= mmc_byte_total_r;
8'hAB : pgmpre_out[0] <= mmc_long_r;
8'hAC : pgmpre_out[0] <= mmc_dpe_r;
8'hAD : pgmpre_out[0] <= mmc_state_end_r;
// 8'hB0 : pgmpre_out[0] <= exe_mmc_rd_r;
// 8'hB1 : pgmpre_out[0] <= exe_mmc_addr_r[7:0];
// 8'hB2 : pgmpre_out[0] <= exe_mmc_addr_r[15:8];
// 8'hB3 : pgmpre_out[0] <= exe_mmc_addr_r[23:16];
// 8'hB4 : pgmpre_out[0] <= exe_mmc_data_r[7:0];
// 8'hB5 : pgmpre_out[0] <= exe_mmc_data_r[15:8];
// 8'hB6 : pgmpre_out[0] <= exe_mmc_data_r[23:16];
// 8'hB7 : pgmpre_out[0] <= exe_mmc_data_r[31:24];
// 8'hB8 : pgmpre_out[0] <= exe_mmc_wr_r;
// 8'hB9 : pgmpre_out[0] <= exe_mmc_long_r;
// 8'hBA : pgmpre_out[0] <= exe_mmc_byte_total_r;
`else
`ifdef DEBUG_DMA
8'hA0 : pgmpre_out[0] <= DMA_STATE;
`ifdef DMA_ENABLE
8'hA1 : pgmpre_out[0] <= dma_next_readstate_r;
8'hA2 : pgmpre_out[0] <= dma_next_writestate_r;
8'hA3 : pgmpre_out[0] <= dma_cc1_bpp_r;
8'hA4 : pgmpre_out[0] <= dma_cc1_bpl_r[8:1]; // 0 always 0
8'hA5 : pgmpre_out[0] <= dma_cc1_size_mask_r;
8'hA6 : pgmpre_out[0] <= dma_cc1_char_num_r;
8'hA7 : pgmpre_out[0] <= dma_cc1_mask_r;
8'hA8 : pgmpre_out[0] <= dma_cc1_imask_r;
8'hA9 : pgmpre_out[0] <= dma_cc1_en_r;
8'hAA : pgmpre_out[0] <= dbg_dma_cc1_start_r;
8'hAB : pgmpre_out[0] <= dbg_dma_cc1_trigger_r;
8'hAC : pgmpre_out[0] <= dbg_dma_cc1_write_r[7:0];
8'hAD : pgmpre_out[0] <= dbg_dma_cc1_write_r[15:8];
8'hAE : pgmpre_out[0] <= dbg_dma_cc1_nonzero_write_r[7:0];
8'hAF : pgmpre_out[0] <= dbg_dma_cc1_nonzero_write_r[15:8];
8'hB0 : pgmpre_out[0] <= dma_cc1_addr_rd_r[7:0];
8'hB1 : pgmpre_out[0] <= dma_cc1_addr_rd_r[15:8];
8'hB2 : pgmpre_out[0] <= dma_cc1_addr_rd_r[23:16];
8'hB3 : pgmpre_out[0] <= dma_cc1_addr_wr_r[7:0];
8'hB4 : pgmpre_out[0] <= dma_cc1_addr_wr_r[10:8];
8'hB5 : pgmpre_out[0] <= dma_line_r;
8'hB6 : pgmpre_out[0] <= dma_byte_r;
8'hB7 : pgmpre_out[0] <= dma_comp_r;
`endif
`endif
`endif
// C0-DF EXECUTE
8'hC0 : pgmpre_out[0] <= EXE_STATE;
8'hC1 : pgmpre_out[0] <= exe_opsize_r;
8'hC2 : pgmpre_out[0] <= exe_opcode_r;
8'hC3 : pgmpre_out[0] <= exe_operand_r[7:0];
8'hC4 : pgmpre_out[0] <= exe_operand_r[15:8];
8'hC5 : pgmpre_out[0] <= exe_operand_r[23:16];
8'hC6 : pgmpre_out[0] <= exe_addr_r[7:0];
8'hC7 : pgmpre_out[0] <= exe_addr_r[15:8];
8'hC8 : pgmpre_out[0] <= exe_addr_r[23:16];
8'hC9 : pgmpre_out[0] <= exe_data_r[7:0];
8'hCA : pgmpre_out[0] <= exe_data_r[15:8];
`ifdef DEBUG_EXE
8'hCB : pgmpre_out[0] <= exe_control_r;
8'hCC : pgmpre_out[0] <= exe_nextpc_r[7:0];
8'hCD : pgmpre_out[0] <= exe_nextpc_r[15:8];
8'hCE : pgmpre_out[0] <= exe_src_r[7:0];
8'hCF : pgmpre_out[0] <= exe_src_r[15:8];
//8'hD0 : pgmpre_out[0] <= exe_dec_inst;
8'hD0 : pgmpre_out[0] <= exe_dec_grp;
8'hD1 : pgmpre_out[0] <= exe_dec_size;
8'hD2 : pgmpre_out[0] <= exe_dec_lat;
8'hD3 : pgmpre_out[0] <= exe_dec_prc;
8'hD4 : pgmpre_out[0] <= exe_dec_src;
8'hD5 : pgmpre_out[0] <= exe_dec_dst;
8'hD6 : pgmpre_out[0] <= exe_dec_ctl;
8'hD7 : pgmpre_out[0] <= exe_dec_add_bank;
8'hD8 : pgmpre_out[0] <= exe_dec_add_base;
8'hD9 : pgmpre_out[0] <= exe_dec_add_mod;
8'hDA : pgmpre_out[0] <= exe_dec_add_imm;
8'hDB : pgmpre_out[0] <= exe_dec_add_indirect;
8'hDC : pgmpre_out[0] <= exe_dec_add_long;
//8'hDD : pgmpre_out[0] <= exe_dec_add_stk;
`endif
8'hDD : pgmpre_out[0] <= exe_target_r[7:0];
8'hDE : pgmpre_out[0] <= exe_target_r[15:8];
8'hDF : pgmpre_out[0] <= exe_target_r[23:16];
//8'hC5 : pgmpre_out[0] <= exe_opindex_r;
// E0-EF ???
8'hE0 : pgmpre_out[0] <= debug_inst_addr_prev_r[ 7: 0];
8'hE1 : pgmpre_out[0] <= debug_inst_addr_prev_r[15: 8];
8'hE2 : pgmpre_out[0] <= debug_inst_addr_prev_r[23:16];
8'hF0 : pgmpre_out[0] <= config_r[0];
8'hF1 : pgmpre_out[0] <= config_r[1];
8'hF2 : pgmpre_out[0] <= config_r[2];
8'hF3 : pgmpre_out[0] <= config_r[3];
8'hF4 : pgmpre_out[0] <= config_r[4];
8'hF5 : pgmpre_out[0] <= config_r[5];
8'hF6 : pgmpre_out[0] <= config_r[6];
8'hF7 : pgmpre_out[0] <= config_r[7];
8'hF8 : pgmpre_out[0] <= stepcnt_r;
8'hF9 : pgmpre_out[0] <= sa1_clock_en;
`ifdef DEBUG_EXT
// big endian to make debugging easier
8'hFA : pgmpre_out[0] <= sa1_cycle_cnt_r[31:24];
8'hFB : pgmpre_out[0] <= sa1_cycle_cnt_r[23:16];
8'hFC : pgmpre_out[0] <= sa1_cycle_cnt_r[15: 8];
8'hFD : pgmpre_out[0] <= sa1_cycle_cnt_r[ 7: 0];
`endif
default : pgmpre_out[0] <= 8'hFF;
endcase
default : pgmpre_out[pgm_addr_r[9:8]] <= 8'hFF;
endcase
end
end
`endif
//-------------------------------------------------------------------
// MISC OUTPUTS
//-------------------------------------------------------------------
assign DBG = 0;
`ifdef DEBUG
assign PGM_DATA = pgmdata_out;
`else
assign PGM_DATA = 0;
`endif
assign DATA_ENABLE = snes_data_enable_r;
assign DATA_OUT = snes_data_out_r;
reg cpu_irq_r; initial cpu_irq_r = 0;
always @(posedge CLK) cpu_irq_r <= (SIE_r[`SIE_DMA_IRQEN] & SFR_r[`SFR_DMA_IRQFL]) | (SIE_r[`SIE_CPU_IRQEN] & SFR_r[`SFR_CPU_IRQFL]);
assign IRQ = cpu_irq_r;
assign BMAPS_SBM = BMAPS_r[`BMAPS_SBM];
assign SNV = SNV_r;
assign SIV = SIV_r;
assign SCNT_NVSW = SCNT_r[`SCNT_NVSW];
assign SCNT_IVSW = SCNT_r[`SCNT_IVSW];
assign DMA_CC1_EN = dma_cc1_en_r;
assign XXB_OUT = {xxb[3], xxb[2], xxb[1], xxb[0]};
assign XXB_EN_OUT = xxb_en;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_2_V
`define SKY130_FD_SC_LP__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_V |
module fmrv32im_max10
#(
parameter MEM_FILE = "../../src/imem.mif"
)
(
input CLK48MHZ,
output [3:0] led
);
// クロック信号
wire CLK;
assign CLK = CLK48MHZ;
// リセット信号
wire RST_N;
assign RST_N = 1'b1;
// 割込信号
wire [31:0] INTERRUPT;
assign INTERRUPT = 32'd0;
// Write Address Channel
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
// Write Data Channel
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
// Write Response Channel
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
// Read Address Channel
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
// Read Data Channel
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
// --------------------------------------------------
// AXI4 Interface(Master)
// --------------------------------------------------
// Master Write Address
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
// Master Write Data
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
// Master Write Response
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
// Master Read Address
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
// Master Read Data
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
wire [31:0] gpio_i, gpio_ot;
fmrv32im_core
#(
.MEM_FILE (MEM_FILE)
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
// ------------------------------------------------------------
// Master Write Address
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
// Master Write Data
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
// Master Write Response
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
// Master Read Address
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
// Master Read Data
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
// ------------------------------------------------------------
// Write Address Channel
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
// Write Data Channel
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
// Write Response Channel
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
// Read Address Channel
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
// Read Data Channel
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
fmrv32im_axis_dummy u_fmrv32im_axis_dummy
(
// Reset, Clock
.ARESETN ( RST_N ),
.ACLK ( CLK ),
// Master Write Address
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
// Master Write Data
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
// Master Write Response
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
// Master Read Address
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
// .M_AXI_ARLOCK(),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
// Master Read Data
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
fmrv32im_axi_gpio u_fmrv32im_axi_gpio
(
// Reset, Clock
.RST_N ( RST_N ),
.CLK ( CLK ),
// Master Write Address
.S_AXI_AWADDR ( IM_AXI_AWADDR ),
.S_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.S_AXI_AWPROT ( IM_AXI_AWPROT ),
.S_AXI_AWVALID ( IM_AXI_AWVALID ),
.S_AXI_AWREADY ( IM_AXI_AWREADY ),
// Master Write Data
.S_AXI_WDATA ( IM_AXI_WDATA ),
.S_AXI_WSTRB ( IM_AXI_WSTRB ),
.S_AXI_WVALID ( IM_AXI_WVALID ),
.S_AXI_WREADY ( IM_AXI_WREADY ),
// Master Write Response
.S_AXI_BRESP ( IM_AXI_BRESP ),
.S_AXI_BVALID ( IM_AXI_BVALID ),
.S_AXI_BREADY ( IM_AXI_BREADY ),
// Master Read Address
.S_AXI_ARADDR ( IM_AXI_ARADDR ),
.S_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.S_AXI_ARPROT ( IM_AXI_ARPROT ),
.S_AXI_ARVALID ( IM_AXI_ARVALID ),
.S_AXI_ARREADY ( IM_AXI_ARREADY ),
// Master Read Data
.S_AXI_RDATA ( IM_AXI_RDATA ),
.S_AXI_RRESP ( IM_AXI_RRESP ),
.S_AXI_RVALID ( IM_AXI_RVALID ),
.S_AXI_RREADY ( IM_AXI_RREADY ),
// GPIO
.GPIO_I ( gpio_i ),
.GPIO_OT ( gpio_ot )
);
assign led[2:0] = ~gpio_ot[2:0];
reg [31:0] count;
reg data;
always @(posedge CLK) begin
if(count >= 48000000) begin
count <= 0;
data <= ~data;
end else begin
count <= count +1;
end
end
assign led[3] = ~data;
endmodule |
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=25 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgd6m
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [24:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [24:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [24:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 25,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgd6m
//VALID FILE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:05:12 09/25/2013
// Design Name:
// Module Name: Memoria
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Memoria(WE, ADDR, DATA, mem_data );
input WE;
input [3:0] ADDR;
inout [3:0] DATA;
output [3:0] mem_data;
//Se hace una memoria como una matriz.
reg [3:0] Mem[0:15];
integer i;
//Se pone la memoria en un estado conocido
initial
begin
for(i=0; i<15; i=i+1)
begin
Mem[i] = i[3:0];
end
end
//WE# es 0 cuando se esta escribiendo en la memoria -> hay que leer de data. 4'bzzzz
//WE# es 1 cuando se esta leyendo de la memoria -> hay que escribir el dato en data
//Aqui se decide si ponerse a escuchar o mandar un dato.
assign #200 DATA = WE ? Mem[ADDR] : 4'bzzzz;
//Es caso de que se vaya a escribir en memoria
always @(posedge WE)
begin
Mem[ADDR] <= #200 DATA;
end
assign mem_data = DATA;
endmodule
|
//==================================================================================================
// Filename : musb_ifid_register.v
// Created On : 2014-09-27 20:34:54
// Last Modified : 2015-05-31 13:04:30
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Pipeline register: IF -> ID
//==================================================================================================
module musb_ifid_register(
input clk, // main clock
input rst, // main reset
input [31:0] if_instruction, // Instruction from IF
input [31:0] if_pc_add4, // PC + 1 from IF
input [31:0] if_pc, // PC from IF
input if_is_bds, // This instruction is a BDS.
input if_flush, // clean
input if_stall, // Stall IF
input id_stall, // Stall ID
output reg [31:0] id_instruction, // ID instruction
output reg [31:0] id_pc_add4, // PC + 1 to ID
output reg [31:0] id_exception_pc, // PC to ID
output reg id_is_bds, // Instruction is a BDS
output reg id_is_flushed // This instruction must be ignored
);
always @(posedge clk) begin
id_instruction <= (rst) ? 32'b0 : ((id_stall) ? id_instruction : ((if_stall | if_flush) ? 32'b0 : if_instruction));
id_pc_add4 <= (rst) ? 32'b0 : ((id_stall) ? id_pc_add4 : if_pc_add4); // check this for if_stall
id_exception_pc <= (rst) ? 32'b0 : ((id_stall) ? id_exception_pc : if_pc); // check this for if_stall
id_is_bds <= (rst) ? 1'b0 : ((id_stall) ? id_is_bds : if_is_bds);
id_is_flushed <= (rst) ? 1'b0 : ((id_stall) ? id_is_flushed : if_flush);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_2_V
`define SKY130_FD_SC_HDLL__NOR2B_2_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_2 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_2 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_2_V
|
/*
########################################################################
ELINK CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
module erx_cfg (/*AUTOARG*/
// Outputs
mi_dout, rx_enable, mmu_enable, remap_mode, remap_base,
remap_pattern, remap_sel, timer_cfg, idelay_value, load_taps,
test_mode,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, erx_test_access,
erx_test_data, gpio_datain, rx_status
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6; // 32 registers for now
parameter GROUP = 4'h0;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; // ecfg registers reset only by "hard reset"
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_en;
input mi_we; // single we, must write 32 bit words
input [14:0] mi_addr; // complete physical address (no shifting!)
input [31:0] mi_din;
output [31:0] mi_dout;
//test interface
input erx_test_access;
input [31:0] erx_test_data;
/*****************************/
/*CONFIG SIGNALS */
/*****************************/
//rx
output rx_enable; // enable signal for rx
output mmu_enable; // enables MMU on rx path (static)
input [8:0] gpio_datain; // frame and data inputs (static)
input [15:0] rx_status; // etx status signals
output [1:0] remap_mode; // remap mode (static)
output [31:0] remap_base; // base for dynamic remap (static)
output [11:0] remap_pattern; // patter for static remap (static)
output [11:0] remap_sel; // selects for static remap (static)
output [1:0] timer_cfg; // timeout config (00=off) (static)
output [44:0] idelay_value; // tap values for erx idelay
output load_taps; // loads the idelay_value into IDELAY prim
output test_mode; // testmode blocks all rx ports to fifo
/*------------------------CODE BODY---------------------------------------*/
//registers
reg [31:0] ecfg_rx_reg;
reg [31:0] ecfg_offset_reg;
reg [8:0] ecfg_gpio_reg;
reg [2:0] ecfg_rx_status_reg;
reg [63:0] ecfg_idelay_reg;
reg load_taps;
reg [31:0] mi_dout;
reg [31:0] ecfg_testdata_reg;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_rx_write;
wire ecfg_offset_write;
wire ecfg_remap_write;
wire ecfg_idelay0_write;
wire ecfg_idelay1_write;
wire ecfg_testdata_write;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_CFG);
assign ecfg_offset_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_OFFSET);
assign ecfg_idelay0_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_IDELAY0);
assign ecfg_idelay1_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_IDELAY1);
assign ecfg_testdata_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_TESTDATA);
//###########################
//# RXCFG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
ecfg_rx_reg[31:0] <= 'b0;
else if (ecfg_rx_write)
ecfg_rx_reg[31:0] <= mi_din[31:0];
assign test_mode = ecfg_rx_reg[0];
assign mmu_enable = ecfg_rx_reg[1];
assign remap_mode[1:0] = ecfg_rx_reg[3:2];
assign remap_sel[11:0] = ecfg_rx_reg[15:4];
assign remap_pattern[11:0] = ecfg_rx_reg[27:16];
assign timer_cfg[1:0] = ecfg_rx_reg[29:28];
//###########################
//# DATAIN
//###########################
always @ (posedge clk)
ecfg_gpio_reg[8:0] <= gpio_datain[8:0];
//###########################1
//# DEBUG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
ecfg_rx_status_reg[2:0] <= 'b0;
else
ecfg_rx_status_reg[2:0] <= ecfg_rx_status_reg[2:0] | rx_status[2:0];
//###########################1
//# DYNAMIC REMAP BASE
//###########################
always @ (posedge clk)
if (ecfg_offset_write)
ecfg_offset_reg[31:0] <= mi_din[31:0];
assign remap_base[31:0] = ecfg_offset_reg[31:0];
//###########################1
//# IDELAY TAP VALUES
//###########################
always @ (posedge clk or posedge reset)
if(reset)
ecfg_idelay_reg[63:0] <= 'b0;
else if (ecfg_idelay0_write)
ecfg_idelay_reg[31:0] <= mi_din[31:0];
else if(ecfg_idelay1_write)
ecfg_idelay_reg[63:32] <= mi_din[31:0];
assign idelay_value[44:0] = {ecfg_idelay_reg[46:32],ecfg_idelay_reg[29:0]};
always @ (posedge clk)
load_taps <= ecfg_idelay1_write;
//###############################
//# TESTMODE
//###############################
always @ (posedge clk)
if(ecfg_testdata_write)
ecfg_testdata_reg[31:0] <= mi_din[31:0];
else if(erx_test_access)
ecfg_testdata_reg[31:0] <= ecfg_testdata_reg[31:0] + erx_test_data[31:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ERX_CFG: mi_dout[31:0] <= {ecfg_rx_reg[31:0]};
`ERX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_gpio_reg[8:0]};
`ERX_STATUS: mi_dout[31:0] <= {16'b0, rx_status[15:3],ecfg_rx_status_reg[2:0]};
`ERX_OFFSET: mi_dout[31:0] <= {ecfg_offset_reg[31:0]};
`ERX_TESTDATA: mi_dout[31:0] <= {ecfg_testdata_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_rx
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_TB_V
`define SKY130_FD_SC_HD__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_TB_V
|
// It looks like for the models to be correctly annotated with timings from
// SDF in Icarus Verilog the timescale provided here must match the one in SDF.
// VPR writes SDFs in picoseconds hence here it is set to picoseconds as well.
`timescale 1ps/1ps
// VPR routing interconnect module
module fpga_interconnect(datain, dataout);
input datain;
output dataout;
// Behavioral model
assign dataout = datain;
// Timing paths. The values are dummy and are intended to be replaced by
// ones from a SDF file during simulation.
specify
(datain => dataout) = 0;
endspecify
endmodule
module frac_lut4_arith (\in[3] ,\in[2] ,\in[1] ,\in[0] ,cin, lut4_out, cout);
parameter [15:0] LUT = 16'd0;
parameter [0: 0] MODE = 0;
input [0:0] \in[3] ;
input [0:0] \in[2] ;
input [0:0] \in[1] ;
input [0:0] \in[0] ;
input [0:0] cin;
output [0:0] lut4_out;
output [0:0] cout;
// Mode bits of frac_lut4_arith are responsible for the LI2 mux which
// selects between the LI2 and CIN inputs.
wire [3:0] li = (MODE == 1'b1) ?
{\in[3] ,cin, \in[1] ,\in[0] } :
{\in[3] ,\in[2] ,\in[1] ,\in[0] };
// Output function
wire [7:0] s1 = li[0] ?
{LUT[14], LUT[12], LUT[10], LUT[8], LUT[6], LUT[4], LUT[2], LUT[0]} :
{LUT[15], LUT[13], LUT[11], LUT[9], LUT[7], LUT[5], LUT[3], LUT[1]};
wire [3:0] s2 = li[1] ?
{s1[6], s1[4], s1[2], s1[0]} :
{s1[7], s1[5], s1[3], s1[1]};
wire [1:0] s3 = li[2] ?
{s2[2], s2[0]} :
{s2[3], s2[1]};
assign lut4_out = li[3] ? s3[0] : s3[1];
// Carry out function
assign cout = s2[2] ? cin : s2[3];
// Timing paths. The values are dummy and are intended to be replaced by
// ones from a SDF file during simulation.
specify
(\in[0] => lut4_out) = 0;
(\in[1] => lut4_out) = 0;
(\in[2] => lut4_out) = 0;
(\in[3] => lut4_out) = 0;
(cin => lut4_out) = 0;
(\in[0] => cout) = 0;
(\in[1] => cout) = 0;
(\in[2] => cout) = 0;
(\in[3] => cout) = 0;
(cin => cout) = 0;
endspecify
endmodule
module scff (D, DI, clk, reset, Q); // QL_IOFF
parameter [0:0] MODE = 1; // The default
input [0:0] D;
input [0:0] DI;
input [0:0] clk;
input [0:0] reset;
output [0:0] Q;
scff_1 #(.MODE(MODE)) scff_1 (
.D (D),
.DI (DI),
.clk (clk),
.preset (1'b1),
.reset (reset),
.Q (Q)
);
endmodule
module scff_1 (D, DI, clk, preset, reset, Q); // QL_FF
parameter [0:0] MODE = 1; // The default
input [0:0] D;
input [0:0] DI;
input [0:0] clk;
input [0:0] preset;
input [0:0] reset;
output reg [0:0] Q;
initial Q <= 1'b0;
// Clock inverter
wire ck = (MODE == 1'b1) ? clk : !clk;
// FLip-flop behavioral model
always @(posedge ck or negedge reset or negedge preset) begin
if (!reset) Q <= 1'b0;
else if (!preset) Q <= 1'b1;
else Q <= D;
end
// Timing paths. The values are dummy and are intended to be replaced by
// ones from a SDF file during simulation.
specify
(posedge clk => (Q +: D)) = 0;
$setuphold(posedge clk, D, 0, 0);
$recrem(posedge reset, posedge clk, 0, 0);
$recrem(posedge preset, posedge clk, 0, 0);
endspecify
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_1_V
`define SKY130_FD_SC_HS__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_1_V
|
// file: Clock35MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock35MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock35MHz_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
//-----------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotLogic
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module nnip_neuron
#(
parameter WIDTH = 8
)(
// Clock & reset, arstn
// deasserted on rising edge
input wire aclk,
input wire arstn,
// Input data of the neuron
input wire ce,
input signed [ WIDTH-1:0] x0,
input signed [ WIDTH-1:0] x1,
input signed [ WIDTH-1:0] x2,
input signed [ WIDTH-1:0] x3,
// Input coefficient for each data
input signed [ WIDTH-1:0] c0,
input signed [ WIDTH-1:0] c1,
input signed [ WIDTH-1:0] c2,
input signed [ WIDTH-1:0] c3,
// Output of the neuron
output signed [2*WIDTH-1:0] y
);
reg [2*WIDTH-1:0] mac;
always @ (posedge aclk or negedge arstn) begin
if (arstn == 1'b0) begin
mac <= {2 * WIDTH{1'b0}};
end
else begin
if (ce == 1'b1)
mac <= x0 * c0 + x1 * c1 + x2 * c2 + x3 * c3;
end
end
assign y = mac;
endmodule
`resetall
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: init_config.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fixed_config (
address_in,
clock,
q);
parameter LUT_SIZE = 6;
parameter NUM_STAGES = 78;
input [31:0] address_in;
input clock;
output [31:0] q;
// (2^lut_inputs times Num_Config_stages)
reg [31:0] ram[0:(2**LUT_SIZE)*NUM_STAGES];
reg [31:0] q;
// Initializing BlockRAM from external datafile
initial
begin
//$readmemh("output.hex.mif",ram,0,(2**LUT_SIZE)*NUM_STAGES);
$readmemh("output.hex.mif",ram);
end
always@(posedge clock)
begin
q = ram[address_in];
end
endmodule
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter ve14d63 = 6000000,
parameter v2af3e8 = 4'hA,
parameter v98e11a = 4'h5
) (
input vclk,
output v7b511e,
output [3:0] v1469d9,
output va123ac,
output v5fd4fa,
output [0:0] vinit
);
localparam p2 = v2af3e8;
localparam p5 = v98e11a;
localparam p6 = ve14d63;
wire w0;
wire [0:3] w1;
wire [0:3] w3;
wire [0:3] w4;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
assign v7b511e = w0;
assign v1469d9 = w1;
assign v5fd4fa = w9;
assign va123ac = w10;
assign w11 = vclk;
assign w12 = vclk;
assign w12 = w11;
vfebcfe v14f857 (
.v9fb85f(w0)
);
v9b9118 #(
.vc5c8ea(p5)
) v7d370f (
.v1ef182(w4)
);
v9b9118 #(
.vc5c8ea(p2)
) v8f4039 (
.v1ef182(w3)
);
v952eda v06ea2a (
.v6833fd(w1),
.ve2616d(w3),
.v54ac99(w4),
.v2d3366(w8)
);
vbce541 #(
.va04f5d(p6)
) v69348d (
.v4642b6(w7),
.v6dda25(w11)
);
vbef3fc v778e1f (
.v3dc29f(w7),
.v4642b6(w8),
.v6dda25(w12)
);
vfebcfe vc1077d (
.v9fb85f(w9)
);
vd30ca9 v9efcb9 (
.v9fb85f(w10)
);
assign vinit = 1'b0;
endmodule
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module v9b9118 #(
parameter vc5c8ea = 0
) (
output [3:0] v1ef182
);
localparam p0 = vc5c8ea;
wire [0:3] w1;
assign v1ef182 = w1;
v9b9118_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 4-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 4-bits generic constant (0-15)
//---------------------------------------------------
module v9b9118_v465065 #(
parameter VALUE = 0
) (
output [3:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule
//---------------------------------------------------
//-- 4-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (4-bit channels)
//---------------------------------------------------
//---- Top entity
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule
//---------------------------------------------------
//-- Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels)
//---------------------------------------------------
//---- Top entity
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- OR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR2: Two bits input OR gate
//---------------------------------------------------
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule
//---- Top entity
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- AND2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Two bits input And gate
//---------------------------------------------------
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
//---- Top entity
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Join-all: Join all the wires into a 4-bits Bus
//---------------------------------------------------
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Split-all: Split the 4-bits bus into its wires
//---------------------------------------------------
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module vbce541 #(
parameter va04f5d = 16777216
) (
input v6dda25,
output v4642b6
);
localparam p1 = va04f5d;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire w4;
wire w5;
assign v4642b6 = w0;
assign w5 = v6dda25;
assign w4 = w0;
vef98b5 #(
.vc5c8ea(p1)
) v4016e8 (
.ve70c2d(w3)
);
vd84ae0 v45b714 (
.v4642b6(w0),
.va89056(w2),
.v06bdfb(w3)
);
v97d607 v2299cf (
.v9e1c43(w2),
.ve556f1(w4),
.v6dda25(w5)
);
endmodule
//---------------------------------------------------
//-- sysclk_divN_24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- sysclk_divN_24bits: Generate a signal from the division of the system clock by N. (24-bits precision) (N = 2,3,4,..,0x1000000))
//---------------------------------------------------
//---- Top entity
module vef98b5 #(
parameter vc5c8ea = 1
) (
output [23:0] ve70c2d
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign ve70c2d = w1;
vef98b5_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-k-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits k-1 constant (Input values: 1,2,...,h1000000). It returns the value input by the user minus 1. Outputs: 0,1,2,...,FFFFFF
//---------------------------------------------------
module vef98b5_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE-1;
endmodule
//---- Top entity
module vd84ae0 (
input [23:0] v06bdfb,
input [23:0] va89056,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:23] w4;
wire [0:23] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire [0:7] w9;
wire [0:7] w10;
wire [0:7] w11;
assign v4642b6 = w0;
assign w4 = v06bdfb;
assign w5 = va89056;
vb2762a vb6832a (
.v4642b6(w1),
.v715730(w8),
.vf191e6(w11)
);
vb2762a v302658 (
.v4642b6(w2),
.v715730(w7),
.vf191e6(w10)
);
vae245c v9196c7 (
.vcbab45(w0),
.v3ca442(w1),
.v0e28cb(w2),
.v033bf6(w3)
);
v6fef69 vb1e577 (
.v9804b7(w5),
.vd83cb2(w9),
.v243fb2(w10),
.va2a3a1(w11)
);
v6fef69 v62b64f (
.v9804b7(w4),
.vd83cb2(w6),
.v243fb2(w7),
.va2a3a1(w8)
);
vb2762a v9a65c6 (
.v4642b6(w3),
.v715730(w6),
.vf191e6(w9)
);
endmodule
//---------------------------------------------------
//-- comp2-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-24bit: Comparator of two 24-bit numbers
//---------------------------------------------------
//---- Top entity
module vb2762a (
input [7:0] v715730,
input [7:0] vf191e6,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w3 = v715730;
assign w4 = vf191e6;
v438230 v577a36 (
.v4642b6(w2),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w2)
);
v6bdcd9 v921a9f (
.vcc8c7c(w4),
.v651522(w7),
.v2cc41f(w8)
);
v6bdcd9 v8cfa4d (
.vcc8c7c(w3),
.v651522(w5),
.v2cc41f(w6)
);
v438230 vfc1765 (
.v4642b6(w1),
.v693354(w5),
.v5369cd(w7)
);
endmodule
//---------------------------------------------------
//-- comp2-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-8bit: Comparator of two 8-bit numbers
//---------------------------------------------------
//---- Top entity
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule
//---------------------------------------------------
//-- comp2-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-4bit: Comparator of two 4-bit numbers
//---------------------------------------------------
//---- Top entity
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule
//---------------------------------------------------
//-- comp2-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-1bit: Comparator of two 1-bit numbers
//---------------------------------------------------
//---- Top entity
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- XOR gate: two bits input xor gate
//---------------------------------------------------
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule
//---- Top entity
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- AND4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size
//---------------------------------------------------
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module vae245c (
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v033bf6;
assign w1 = v0e28cb;
assign w2 = v3ca442;
assign vcbab45 = w4;
vba518e v19b5b0 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w3)
);
vba518e vf3ef0f (
.v3ca442(w2),
.v0e28cb(w3),
.vcbab45(w4)
);
endmodule
//---------------------------------------------------
//-- AND3
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v6fef69 (
input [23:0] v9804b7,
output [7:0] vd83cb2,
output [7:0] v243fb2,
output [7:0] va2a3a1
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:23] w3;
assign v243fb2 = w0;
assign vd83cb2 = w1;
assign va2a3a1 = w2;
assign w3 = v9804b7;
v6fef69_v9a2a06 v9a2a06 (
.o1(w0),
.o2(w1),
.o0(w2),
.i(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-one-third: Split the 24-bits bus into three buses of the same size
//---------------------------------------------------
module v6fef69_v9a2a06 (
input [23:0] i,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v97d607 (
input v6dda25,
input ve556f1,
output [23:0] v9e1c43,
output ve37344
);
wire w0;
wire [0:23] w1;
wire [0:23] w2;
wire w3;
wire [0:23] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign v9e1c43 = w4;
assign ve37344 = w5;
assign w4 = w1;
v5495b5 v5e4c9c (
.v782748(w0),
.vb02eea(w1),
.v15c6e6(w2),
.v6dda25(w3)
);
v9c4559 v62e821 (
.v005b83(w1),
.v53d485(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 24-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module v5495b5 (
input v6dda25,
input v782748,
input [23:0] v15c6e6,
output [23:0] vb02eea
);
wire [0:23] w0;
wire [0:23] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
assign vb02eea = w0;
assign w1 = v15c6e6;
assign w8 = v6dda25;
assign w9 = v6dda25;
assign w10 = v6dda25;
assign w11 = v782748;
assign w12 = v782748;
assign w13 = v782748;
assign w9 = w8;
assign w10 = w8;
assign w10 = w9;
assign w12 = w11;
assign w13 = w11;
assign w13 = w12;
v6fef69 vad6f1d (
.v9804b7(w1),
.va2a3a1(w5),
.v243fb2(w6),
.vd83cb2(w7)
);
v33e50d vba7365 (
.v6d326e(w0),
.v77c6e9(w2),
.vf7d213(w3),
.vba04ee(w4)
);
vcf4344 v13ddeb (
.vc1f0d2(w2),
.vd85d4e(w5),
.v6dda25(w10),
.v782748(w13)
);
vcf4344 v08e1bd (
.vc1f0d2(w3),
.vd85d4e(w6),
.v6dda25(w9),
.v782748(w12)
);
vcf4344 v5c3b0f (
.vc1f0d2(w4),
.vd85d4e(w7),
.v6dda25(w8),
.v782748(w11)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x24: 24 D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v33e50d (
input [7:0] vba04ee,
input [7:0] vf7d213,
input [7:0] v77c6e9,
output [23:0] v6d326e
);
wire [0:23] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
assign v6d326e = w0;
assign w1 = vf7d213;
assign w2 = v77c6e9;
assign w3 = vba04ee;
v33e50d_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2),
.i2(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-one-third: Join the three buses into an 24-bits Bus
//---------------------------------------------------
module v33e50d_v9a2a06 (
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [23:0] o
);
assign o = {i2, i1, i0};
endmodule
//---- Top entity
module vcf4344 (
input v6dda25,
input v782748,
input [7:0] vd85d4e,
output [7:0] vc1f0d2
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w2 = vd85d4e;
assign vc1f0d2 = w3;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v5c75f6 vbdef88 (
.v50034e(w0),
.v4de61b(w1),
.v6dda25(w7),
.v782748(w9)
);
v6bdcd9 vc95779 (
.v2cc41f(w1),
.vcc8c7c(w2),
.v651522(w4)
);
vafb28f v618315 (
.v3c88fc(w0),
.va9ac17(w3),
.v515fe7(w5)
);
v5c75f6 v6188f9 (
.v4de61b(w4),
.v50034e(w5),
.v6dda25(w6),
.v782748(w8)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x08: Eight D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x04: Three D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0
//---------------------------------------------------
//---- Top entity
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-half: Join the two same halves into an 8-bits Bus
//---------------------------------------------------
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v9c4559 #(
parameter v6c5139 = 1
) (
input [23:0] v005b83,
output v4642b6,
output [23:0] v53d485
);
localparam p1 = v6c5139;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
assign v4642b6 = w0;
assign w2 = v005b83;
assign v53d485 = w3;
v44c099 #(
.vd73390(p1)
) v8c0045 (
.v4642b6(w0),
.vd90f46(w2),
.v8826c0(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-24bit: Increment a 24-bits number by one
//---------------------------------------------------
//---- Top entity
module v44c099 #(
parameter vd73390 = 0
) (
input [23:0] vd90f46,
output v4642b6,
output [23:0] v8826c0
);
localparam p1 = vd73390;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire [0:23] w4;
assign v4642b6 = w0;
assign v8826c0 = w2;
assign w3 = vd90f46;
v4c802f #(
.vc5c8ea(p1)
) ve78914 (
.v8513f7(w4)
);
v91404d v19ed8b (
.v4642b6(w0),
.vb5c06c(w2),
.v7959e8(w3),
.vb5a2f2(w4)
);
endmodule
//---------------------------------------------------
//-- AdderK-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-24bit: Adder of 24-bit operand and 24-bit constant
//---------------------------------------------------
//---- Top entity
module v4c802f #(
parameter vc5c8ea = 0
) (
output [23:0] v8513f7
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign v8513f7 = w1;
v4c802f_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits generic constant
//---------------------------------------------------
module v4c802f_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v91404d (
input [23:0] vb5a2f2,
input [23:0] v7959e8,
output v4642b6,
output [23:0] vb5c06c
);
wire w0;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
wire [0:15] w5;
wire [0:23] w6;
wire [0:15] w7;
wire [0:23] w8;
wire [0:15] w9;
wire [0:7] w10;
wire [0:23] w11;
wire [0:7] w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
assign v4642b6 = w4;
assign w6 = v7959e8;
assign w8 = vb5a2f2;
assign vb5c06c = w11;
vcb23aa v8e0bba (
.v4642b6(w0),
.v62bf25(w2),
.v39966a(w16),
.veb2f59(w17)
);
vc3c498 v917bbf (
.vb9cfc3(w0),
.veeaa8e(w1),
.v4642b6(w3),
.v45c6ee(w14),
.v20212e(w15)
);
v8cc49c v03c3e3 (
.vb334ae(w1),
.v2b8a97(w2),
.v14a530(w5)
);
vab13f0 v43653c (
.vb18564(w6),
.vf0a06e(w7),
.v5246f6(w17)
);
v306ca3 v177126 (
.v91b9c1(w7),
.vef5eee(w13),
.vd3ef3b(w15)
);
vab13f0 vf15711 (
.vb18564(w8),
.vf0a06e(w9),
.v5246f6(w16)
);
v306ca3 vf9ed57 (
.v91b9c1(w9),
.vef5eee(w12),
.vd3ef3b(w14)
);
vc3c498 vf0db78 (
.vb9cfc3(w3),
.v4642b6(w4),
.veeaa8e(w10),
.v45c6ee(w12),
.v20212e(w13)
);
va52e3b v67022b (
.vbf8961(w5),
.vf7d213(w10),
.v6d326e(w11)
);
endmodule
//---------------------------------------------------
//-- Adder-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-24bits: Adder of two operands of 24 bits
//---------------------------------------------------
//---- Top entity
module vcb23aa (
input [7:0] v39966a,
input [7:0] veb2f59,
output v4642b6,
output [7:0] v62bf25
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:7] w4;
wire w5;
wire w6;
wire [0:3] w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
assign w0 = veb2f59;
assign w1 = v39966a;
assign v62bf25 = w4;
assign v4642b6 = w5;
v6bdcd9 vd88c66 (
.vcc8c7c(w0),
.v651522(w9),
.v2cc41f(w10)
);
v6bdcd9 v26a0bb (
.vcc8c7c(w1),
.v651522(w7),
.v2cc41f(w8)
);
v25966b v9ea427 (
.v817794(w3),
.v4642b6(w6),
.v0550b6(w8),
.v24708e(w10)
);
vafb28f vc75346 (
.v515fe7(w2),
.v3c88fc(w3),
.va9ac17(w4)
);
va1ce30 v40c17f (
.v817794(w2),
.v4642b6(w5),
.vb9cfc3(w6),
.v0550b6(w7),
.v24708e(w9)
);
endmodule
//---------------------------------------------------
//-- Adder-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-8bits: Adder of two operands of 8 bits
//---------------------------------------------------
//---- Top entity
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule
//---------------------------------------------------
//-- Adder-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-4bits: Adder of two operands of 4 bits
//---------------------------------------------------
//---- Top entity
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule
//---------------------------------------------------
//-- Adder-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-1bit: Adder of two operands of 1 bit
//---------------------------------------------------
//---- Top entity
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- AdderC-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in
//---------------------------------------------------
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
//---- Top entity
module va1ce30 (
input [3:0] v0550b6,
input [3:0] v24708e,
input vb9cfc3,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
assign w11 = vb9cfc3;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w13),
.v82de4f(w17)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w14),
.vda577d(w17),
.v3f8943(w18),
.v64d863(w19)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w12),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w12),
.v82de4f(w14)
);
vad119b v3599be (
.v4642b6(w0),
.v8e8a67(w2),
.v0ef266(w11),
.v27dec4(w16),
.v82de4f(w19)
);
endmodule
//---------------------------------------------------
//-- AdderC-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-4bits: Adder of two operands of 4 bits and Carry in
//---------------------------------------------------
//---- Top entity
module vc3c498 (
input [7:0] v45c6ee,
input [7:0] v20212e,
input vb9cfc3,
output v4642b6,
output [7:0] veeaa8e
);
wire w0;
wire w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
wire [0:3] w11;
assign w1 = vb9cfc3;
assign w2 = v45c6ee;
assign w3 = v20212e;
assign veeaa8e = w4;
assign v4642b6 = w7;
v6bdcd9 v8d795a (
.vcc8c7c(w3),
.v651522(w10),
.v2cc41f(w11)
);
v6bdcd9 v23dbc5 (
.vcc8c7c(w2),
.v651522(w8),
.v2cc41f(w9)
);
vafb28f vef3a58 (
.va9ac17(w4),
.v3c88fc(w5),
.v515fe7(w6)
);
va1ce30 v0ff71a (
.v4642b6(w0),
.vb9cfc3(w1),
.v817794(w5),
.v0550b6(w9),
.v24708e(w11)
);
va1ce30 v12f94f (
.vb9cfc3(w0),
.v817794(w6),
.v4642b6(w7),
.v0550b6(w8),
.v24708e(w10)
);
endmodule
//---------------------------------------------------
//-- AdderC-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-8bits: Adder of two operands of 8 bits and Carry in
//---------------------------------------------------
//---- Top entity
module v8cc49c (
input [7:0] vb334ae,
input [7:0] v2b8a97,
output [15:0] v14a530
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign v14a530 = w0;
assign w1 = v2b8a97;
assign w2 = vb334ae;
v8cc49c_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Join-half: Join the two same halves into an 16-bits Bus
//---------------------------------------------------
module v8cc49c_v9a2a06 (
input [7:0] i1,
input [7:0] i0,
output [15:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vab13f0 (
input [23:0] vb18564,
output [15:0] vf0a06e,
output [7:0] v5246f6
);
wire [0:23] w0;
wire [0:15] w1;
wire [0:7] w2;
assign w0 = vb18564;
assign vf0a06e = w1;
assign v5246f6 = w2;
vab13f0_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-16-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-16-8: Split the 24-bits bus into two buses of 16 and 8 wires
//---------------------------------------------------
module vab13f0_v9a2a06 (
input [23:0] i,
output [15:0] o1,
output [7:0] o0
);
assign o1 = i[23:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v306ca3 (
input [15:0] v91b9c1,
output [7:0] vef5eee,
output [7:0] vd3ef3b
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign w0 = v91b9c1;
assign vef5eee = w1;
assign vd3ef3b = w2;
v306ca3_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Split-half: Split the 16-bits bus into two buses of the same size
//---------------------------------------------------
module v306ca3_v9a2a06 (
input [15:0] i,
output [7:0] o1,
output [7:0] o0
);
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module va52e3b (
input [7:0] vf7d213,
input [15:0] vbf8961,
output [23:0] v6d326e
);
wire [0:15] w0;
wire [0:23] w1;
wire [0:7] w2;
assign w0 = vbf8961;
assign v6d326e = w1;
assign w2 = vf7d213;
va52e3b_v9a2a06 v9a2a06 (
.i0(w0),
.o(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-8-16 CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-8-16: Join the two buses into an 24-bits Bus
//---------------------------------------------------
module va52e3b_v9a2a06 (
input [7:0] i1,
input [15:0] i0,
output [23:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vbef3fc #(
parameter v8bcde4 = 0
) (
input v6dda25,
input v3dc29f,
output v4642b6
);
localparam p1 = v8bcde4;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
assign w2 = v3dc29f;
assign w3 = v6dda25;
assign v4642b6 = w4;
assign w5 = w4;
v3676a0 vdebd76 (
.vcbab45(w0),
.v0e28cb(w5)
);
v22cb98 #(
.v5462c0(p1)
) v51de32 (
.v27dec4(w0),
.vd793aa(w2),
.ve4a668(w3),
.v4642b6(w4)
);
endmodule
//---------------------------------------------------
//-- Counter-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Counter-x01: 1-bit counter
//---------------------------------------------------
//---- Top entity
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule
//---------------------------------------------------
//-- 1-bit-reg
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg: 1-Bit register
//---------------------------------------------------
//---- Top entity
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule
//---------------------------------------------------
//-- MuxF-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels). Fippled version
//---------------------------------------------------
|
module memif(
input wire clk,
input wire reset,
// Avalon Slave
input wire [1:0] s_address,
input wire s_write,
input wire s_read,
input wire [31:0] s_writedata,
output reg [31:0] s_readdata,
output wire s_waitrequest,
// 36 bit Avalon Master
output wire [17:0] m_address,
output reg m_write,
output reg m_read,
output wire [35:0] m_writedata,
input wire [35:0] m_readdata,
input wire m_waitrequest
);
reg [17:0] addr;
reg [35:0] word;
assign m_address = addr;
assign m_writedata = word;
wire write_edge, read_edge;
edgedet e0(clk, reset, s_write, write_edge);
edgedet e1(clk, reset, s_read, read_edge);
reg waiting;
wire req = (write_edge|read_edge) & s_address == 2'h2;
assign s_waitrequest = req | waiting;
always @(posedge clk or negedge reset) begin
if(~reset) begin
m_write <= 0;
m_read <= 0;
waiting <= 0;
addr <= 0;
word <= 0;
end else begin
if(write_edge) begin
case(s_address)
2'h0: addr <= s_writedata[17:0];
2'h1: word[17:0] <= s_writedata[17:0];
2'h2: word[35:18] <= s_writedata[17:0];
endcase
end
if(req) begin
waiting <= 1;
if(s_write)
m_write <= 1;
else if(s_read)
m_read <= 1;
end
if(m_write & ~m_waitrequest) begin
m_write <= 0;
waiting <= 0;
end
if(m_read & ~m_waitrequest) begin
m_read <= 0;
waiting <= 0;
word <= m_readdata;
end
end
end
always @(*) begin
case(s_address)
2'h1: s_readdata <= { 14'b0, word[17:0] };
2'h2: s_readdata <= { 14'b0, word[35:18] };
default: s_readdata <= 32'b0;
endcase
end
endmodule
|
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