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// File: fifoStatusTBV.v
// Generated by MyHDL 0.10
// Date: Mon Aug 27 20:11:15 2018
`timescale 1ns/10ps
module fifoStatusTBV (
);
// myHDL -> verilog test bench for `fifoStatus` module
// Note:
// Not a complet testbench, could be better
reg wr = 0;
wire fifo_full;
reg [4:0] wptr = 0;
reg fifo_we = 0;
reg clk = 0;
reg rst_n = 0;
reg rd = 0;
wire fifo_empty;
reg [4:0] rptr = 0;
reg fifo_rd = 0;
wire fifo_threshold;
wire fifo_overflow;
wire fifo_underflow;
reg fifoStatus0_0_underflow_set = 0;
reg signed [4:0] fifoStatus0_0_pointer_result = 0;
reg fifoStatus0_0_pointer_equal = 0;
reg fifoStatus0_0_overflow_set = 0;
reg fifoStatus0_0_fifo_underflow_i = 0;
reg fifoStatus0_0_fifo_threshold_i = 0;
reg fifoStatus0_0_fifo_overflow_i = 0;
reg fifoStatus0_0_fifo_full_i = 0;
reg fifoStatus0_0_fifo_empty_i = 0;
reg fifoStatus0_0_fbit_comp = 0;
always @(rd, fifo_rd, wr, fifo_overflow, fifo_underflow, fifo_threshold, fifo_full, fifo_empty, wptr, rptr, fifo_we) begin: FIFOSTATUSTBV_PRINT_DATA
$write("%h", wr);
$write(" ");
$write("%h", rd);
$write(" ");
$write("%h", fifo_we);
$write(" ");
$write("%h", fifo_rd);
$write(" ");
$write("%h", wptr);
$write(" ");
$write("%h", rptr);
$write(" ");
$write("%h", fifo_full);
$write(" ");
$write("%h", fifo_empty);
$write(" ");
$write("%h", fifo_threshold);
$write(" ");
$write("%h", fifo_overflow);
$write(" ");
$write("%h", fifo_underflow);
$write("\n");
end
always @(rd, wr, fifoStatus0_0_fifo_full_i, rptr, wptr, fifoStatus0_0_fifo_empty_i) begin: FIFOSTATUSTBV_FIFOSTATUS0_0_LOGIC1
fifoStatus0_0_fbit_comp = (wptr[4] ^ rptr[4]);
if (($signed({1'b0, wptr[3-1:0]}) - rptr[3-1:0])) begin
fifoStatus0_0_pointer_equal = 0;
end
else begin
fifoStatus0_0_pointer_equal = 1;
end
fifoStatus0_0_pointer_result = (wptr[4-1:0] - rptr[4-1:0]);
fifoStatus0_0_overflow_set = (fifoStatus0_0_fifo_full_i & wr);
fifoStatus0_0_underflow_set = (fifoStatus0_0_fifo_empty_i & rd);
end
always @(fifoStatus0_0_fbit_comp, fifoStatus0_0_pointer_equal, fifoStatus0_0_pointer_result) begin: FIFOSTATUSTBV_FIFOSTATUS0_0_LOGIC2
fifoStatus0_0_fifo_full_i = (fifoStatus0_0_fbit_comp & fifoStatus0_0_pointer_equal);
fifoStatus0_0_fifo_empty_i = ((!fifoStatus0_0_fbit_comp) & fifoStatus0_0_pointer_equal);
if ((fifoStatus0_0_pointer_result[4] || fifoStatus0_0_pointer_result[3])) begin
fifoStatus0_0_fifo_threshold_i = 1;
end
else begin
fifoStatus0_0_fifo_threshold_i = 0;
end
end
always @(posedge clk, negedge rst_n) begin: FIFOSTATUSTBV_FIFOSTATUS0_0_OVERFLOWCONTROL
if (rst_n) begin
fifoStatus0_0_fifo_overflow_i <= 0;
end
else if (((fifoStatus0_0_overflow_set == 1) && (fifo_rd == 0))) begin
fifoStatus0_0_fifo_overflow_i <= 1;
end
else if (fifo_rd) begin
fifoStatus0_0_fifo_overflow_i <= 0;
end
else begin
fifoStatus0_0_fifo_overflow_i <= fifoStatus0_0_fifo_overflow_i;
end
end
always @(posedge clk, negedge rst_n) begin: FIFOSTATUSTBV_FIFOSTATUS0_0_UNDERFLOWCONTROL
if (rst_n) begin
fifoStatus0_0_fifo_underflow_i <= 0;
end
else if (((fifoStatus0_0_underflow_set == 1) && (fifo_we == 0))) begin
fifoStatus0_0_fifo_underflow_i <= 1;
end
else if (fifo_we) begin
fifoStatus0_0_fifo_underflow_i <= 0;
end
else begin
fifoStatus0_0_fifo_underflow_i <= fifoStatus0_0_fifo_underflow_i;
end
end
assign fifo_full = fifoStatus0_0_fifo_full_i;
assign fifo_empty = fifoStatus0_0_fifo_empty_i;
assign fifo_threshold = fifoStatus0_0_fifo_threshold_i;
assign fifo_overflow = fifoStatus0_0_fifo_overflow_i;
assign fifo_underflow = fifoStatus0_0_fifo_underflow_i;
initial begin: FIFOSTATUSTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: FIFOSTATUSTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h0: begin
wr <= 1;
rd <= 1;
fifo_we <= 0;
fifo_rd <= 0;
end
'h2: begin
wr <= 0;
rd <= 0;
fifo_we <= 1;
fifo_rd <= 1;
end
'h4: begin
wr <= 1;
rd <= 1;
fifo_we <= 1;
fifo_rd <= 1;
end
default: begin
// pass
end
endcase
if (((i >= 6) && (i <= 20))) begin
wptr <= (wptr + 1);
end
if (((i >= 7) && (i <= 20))) begin
rptr <= (rptr + 1);
end
case (i)
'h14: begin
rst_n <= 1;
end
'h15: begin
rst_n <= 0;
end
'h17: begin
$finish;
end
default: begin
// pass
end
endcase
i = i + 1;
@(posedge clk);
end
end
endmodule
|
// ============================================================================
// Copyright (c) 2014 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
//Date: Tue Dec 2 09:28:38 2014
// ============================================================================
`define ENABLE_HPS
//`define ENABLE_CLK
module HPS_CONTROL_FPGA_LED(
///////// ADC /////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
///////// ARDUINO /////////
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`ifdef ENABLE_CLK
///////// CLK /////////
output CLK_I2C_SCL,
inout CLK_I2C_SDA,
`endif /*ENABLE_CLK*/
///////// FPGA /////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
///////// GPIO /////////
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`ifdef ENABLE_HPS
///////// HPS /////////
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_GSENSOR_INT,
inout HPS_I2C0_SCLK,
inout HPS_I2C0_SDAT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
///////// KEY /////////
input [1:0] KEY,
///////// LED /////////
output [7:0] LED,
///////// SW /////////
input [3:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire hps_fpga_reset_n;
//=======================================================
// Structural coding
//=======================================================
soc_system u0 (
//Clock&Reset
.clk_clk (FPGA_CLK1_50 ), // clk.clk
.reset_reset_n (1'b1 ), // reset.reset_n
//HPS ddr3
.memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a
.memory_mem_ba ( HPS_DDR3_BA), // .mem_ba
.memory_mem_ck ( HPS_DDR3_CK_P), // .mem_ck
.memory_mem_ck_n ( HPS_DDR3_CK_N), // .mem_ck_n
.memory_mem_cke ( HPS_DDR3_CKE), // .mem_cke
.memory_mem_cs_n ( HPS_DDR3_CS_N), // .mem_cs_n
.memory_mem_ras_n ( HPS_DDR3_RAS_N), // .mem_ras_n
.memory_mem_cas_n ( HPS_DDR3_CAS_N), // .mem_cas_n
.memory_mem_we_n ( HPS_DDR3_WE_N), // .mem_we_n
.memory_mem_reset_n ( HPS_DDR3_RESET_N), // .mem_reset_n
.memory_mem_dq ( HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs ( HPS_DDR3_DQS_P), // .mem_dqs
.memory_mem_dqs_n ( HPS_DDR3_DQS_N), // .mem_dqs_n
.memory_mem_odt ( HPS_DDR3_ODT), // .mem_odt
.memory_mem_dm ( HPS_DDR3_DM), // .mem_dm
.memory_oct_rzqin ( HPS_DDR3_RZQ), // .oct_rzqin
//HPS ethernet
.hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK), // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
.hps_0_hps_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ), // .hps_io_emac1_inst_TXD0
.hps_0_hps_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ), // .hps_io_emac1_inst_TXD1
.hps_0_hps_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ), // .hps_io_emac1_inst_TXD2
.hps_0_hps_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ), // .hps_io_emac1_inst_TXD3
.hps_0_hps_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ), // .hps_io_emac1_inst_RXD0
.hps_0_hps_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ), // .hps_io_emac1_inst_MDIO
.hps_0_hps_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ), // .hps_io_emac1_inst_MDC
.hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV), // .hps_io_emac1_inst_RX_CTL
.hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN), // .hps_io_emac1_inst_TX_CTL
.hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_0_hps_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ), // .hps_io_emac1_inst_RXD1
.hps_0_hps_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ), // .hps_io_emac1_inst_RXD2
.hps_0_hps_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ), // .hps_io_emac1_inst_RXD3
//HPS SD card
.hps_0_hps_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ), // .hps_io_sdio_inst_CMD
.hps_0_hps_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ), // .hps_io_sdio_inst_D0
.hps_0_hps_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ), // .hps_io_sdio_inst_D1
.hps_0_hps_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ), // .hps_io_sdio_inst_CLK
.hps_0_hps_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ), // .hps_io_sdio_inst_D2
.hps_0_hps_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ), // .hps_io_sdio_inst_D3
//HPS USB
.hps_0_hps_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ), // .hps_io_usb1_inst_D0
.hps_0_hps_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ), // .hps_io_usb1_inst_D1
.hps_0_hps_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ), // .hps_io_usb1_inst_D2
.hps_0_hps_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ), // .hps_io_usb1_inst_D3
.hps_0_hps_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ), // .hps_io_usb1_inst_D4
.hps_0_hps_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ), // .hps_io_usb1_inst_D5
.hps_0_hps_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ), // .hps_io_usb1_inst_D6
.hps_0_hps_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ), // .hps_io_usb1_inst_D7
.hps_0_hps_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ), // .hps_io_usb1_inst_CLK
.hps_0_hps_io_hps_io_usb1_inst_STP ( HPS_USB_STP ), // .hps_io_usb1_inst_STP
.hps_0_hps_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ), // .hps_io_usb1_inst_DIR
.hps_0_hps_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ), // .hps_io_usb1_inst_NXT
//HPS SPI
.hps_0_hps_io_hps_io_spim1_inst_CLK ( HPS_SPIM_CLK ), // .hps_io_spim1_inst_CLK
.hps_0_hps_io_hps_io_spim1_inst_MOSI ( HPS_SPIM_MOSI ), // .hps_io_spim1_inst_MOSI
.hps_0_hps_io_hps_io_spim1_inst_MISO ( HPS_SPIM_MISO ), // .hps_io_spim1_inst_MISO
.hps_0_hps_io_hps_io_spim1_inst_SS0 ( HPS_SPIM_SS ), // .hps_io_spim1_inst_SS0
//HPS UART
.hps_0_hps_io_hps_io_uart0_inst_RX ( HPS_UART_RX ), // .hps_io_uart0_inst_RX
.hps_0_hps_io_hps_io_uart0_inst_TX ( HPS_UART_TX ), // .hps_io_uart0_inst_TX
//HPS I2C1
.hps_0_hps_io_hps_io_i2c0_inst_SDA ( HPS_I2C0_SDAT ), // .hps_io_i2c0_inst_SDA
.hps_0_hps_io_hps_io_i2c0_inst_SCL ( HPS_I2C0_SCLK ), // .hps_io_i2c0_inst_SCL
//HPS I2C2
.hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C1_SDAT ), // .hps_io_i2c1_inst_SDA
.hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C1_SCLK ), // .hps_io_i2c1_inst_SCL
//GPIO
.hps_0_hps_io_hps_io_gpio_inst_GPIO09 ( HPS_CONV_USB_N ), // .hps_io_gpio_inst_GPIO09
.hps_0_hps_io_hps_io_gpio_inst_GPIO35 ( HPS_ENET_INT_N ), // .hps_io_gpio_inst_GPIO35
.hps_0_hps_io_hps_io_gpio_inst_GPIO40 ( HPS_LTC_GPIO ), // .hps_io_gpio_inst_GPIO40
.hps_0_hps_io_hps_io_gpio_inst_GPIO53 ( HPS_LED ), // .hps_io_gpio_inst_GPIO53
.hps_0_hps_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY ), // .hps_io_gpio_inst_GPIO54
.hps_0_hps_io_hps_io_gpio_inst_GPIO61 ( HPS_GSENSOR_INT ), // .hps_io_gpio_inst_GPIO61
//FPGA Partion
.led_pio_external_connection_export ( LED ), // led_pio_external_connection.export
.dipsw_pio_external_connection_export ( SW ), // dipsw_pio_external_connection.export
.button_pio_external_connection_export ( KEY ), // button_pio_external_connection.export
.hps_0_h2f_reset_reset_n (hps_fpga_reset_n ) // hps_0_h2f_reset.reset_n
);
endmodule
|
module ft245_sync_if
#(
parameter DEBUG=0, // Enable it for simulation
parameter EXTRA_READ_GUARD=0, // Add an extra guard in the bus turn-around after read
parameter FAST_WRITE_OLD=0, // Jump from WRITE_OLD to WRITE
parameter USE_STATE_RESET=0) // Add an extra state for the reset state
(
/////////////////////////////////////////////////////
// Interface to the FTDI chip
/////////////////////////////////////////////////////
inout [7:0] adbus_io,
input rxf_n_i,
input txe_n_i,
output rd_n_o,
output wr_n_o,
input clk_i,
output oe_n_o,
output siwu_o,
/////////////////////////////////////////////////////
// Interface to the internal logic
/////////////////////////////////////////////////////
input rst_i,
// FPGA -> FTDI
input [7:0] tx_data_i,
input tx_empty_i,
output tx_read_o,
// FTDI -> FPGA
output [7:0] rx_data_o,
output rx_valid_o,
input rx_full_i);
`include "ft245_sync_if.v"
endmodule // ft245_sync_if
|
//-----------------------------------------------------------------------------
//-- ACC0 (Apollo CPU Core 0)
//-- FPGA, mediante lenguaje Verilog
//-----------------------------------------------------------------------------
//-- (C) August 2016. Juan Gonzaelz-Gomez (Obijuan)
//-- Released under the GPL license
//-----------------------------------------------------------------------------
`default_nettype none
module ACC0 (
input wire clk,
input wire next,
input wire prev,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
//-- Rom file
parameter ROMFILE = "rom.list";
//-- Parameters for the memory
localparam AW = 12; //-- Address bus
localparam DW = 16; //-- Data bus
//-- Initial address
localparam BOOT_ADDR = 12'h800;
wire [DW-1: 0] rom_dout;
//-- Instantiate the ROM memory (2K)
genrom #(
.ROMFILE(ROMFILE),
.AW(AW-1),
.DW(DW))
ROM (
.clk(clk),
.cs(S[AW-1]), //-- Bit A11 for the chip select
.addr(S[AW-2:0]), //-- Bits A10 - A0 for addressing the Rom (2K)
.data_out(rom_dout)
);
//-- Configure the pull-up resistors for clk and rst inputs
wire next_p; //-- Next input with pull-up activated
wire clk_in;
wire prev_p; //-- Prev input with pull-up activated
wire sw2;
wire sw1;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(next),
.D_IN_0(next_p)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(prev),
.D_IN_0(prev_p)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign sw2 = ~prev_p;
assign sw1 = ~next_p;
//-- switch button debounced
wire sw1_deb;
wire sw2_deb;
debounce_pulse deb1 (
.clk(clk),
.sw_in(sw1),
.sw_out(sw1_deb)
);
debounce_pulse deb2 (
.clk(clk),
.sw_in(sw2),
.sw_out(sw2_deb)
);
assign clk_in = sw1_deb;
//-- Register S: Accessing memory
reg [AW-1: 0] S = BOOT_ADDR;
always @(posedge clk) begin
if (sw1_deb)
S <= S + 1;
else
if (sw2_deb)
S <= S - 1;
end
//-- Instruction register
reg [14:0] G = 15'b0;
//-- Control signal for the RI register
//-- Every 15-bit instruction is sotred here before executing
reg WG = 1;
always @(posedge clk)
if (WG)
G <= rom_dout[14:0];
//-- In ACC0, the 7 more significant bits of the G reg are shown in leds
assign {d6,d5,d4,d3,d2,d1,d0} = G[14:8];
//-- The LED7 is always set to 0
assign d7 = 1'b0;
endmodule
// -- Generic ROM
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list") //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1: 0] addr, //-- Address bus
output reg [DW-1: 0] data_out); //-- Data bus
//-- Total position of the address
localparam NPOS = 2 ** AW;
//-- Memory
reg [DW-1: 0] rom [0: NPOS-1];
always @(negedge clk) begin
if (cs)
data_out <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
module debounce_pulse(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in==0)
next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debouncer_pulse
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:33 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.2 2010/02/26 08:58:33 pboya Exp $
**$Date: 2010/02/26 08:58:33 $
**$Author: pboya $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ip_top/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module iodelay_ctrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name when
// multiple IP cores used in design
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter RST_ACT_LOW = 1 // Reset input polarity
// (0 = active high, 1 = active low)
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref,
input sys_rst,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input
//***************************************************************************
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref),
.O (clk_ref_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram30x4.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram30x4 (
address,
clock,
data,
wren,
q);
input [4:0] address;
input clock;
input [3:0] data;
input wren;
output [3:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 30,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 5,
altsyncram_component.width_a = 4,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "30"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "4"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "30"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V |
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 1ns/100ps
module RAMTest;
reg clk;
wire [7:0] w_out_data;
wire [7:0] w_in_data;
reg r_enable_x;
reg r_write_x;
reg [15:0] r_addr;
reg [ 7:0] r_data;
integer i;
RAM_64Kx8 dut(
.i_addr (r_addr ),
.i_enable_x(r_enable_x),
.i_write_x (r_write_x ),
.i_data (w_in_data ),
.o_data (w_out_data));
// 20ns (50MHz)
always #10 clk = !clk;
assign w_in_data = r_data;
always @ (posedge clk) begin
if (!r_enable_x & r_write_x) begin
$display("read $%04x => $%02x", r_addr, w_out_data);
end
end
//initial $readmemh("RAM.hex", dut.ram.r_ram);
initial begin
//$dumpfile("RAM.vcd");
//$dumpvars(0, clk);
//$dumpvars(0, dut);
clk <= 1'b1;
r_enable_x <= 1'b1;
r_write_x <= 1'b1;
r_addr <= 16'h0000;
r_data <= 8'h00;
#1
r_enable_x <= 1'b0;
#20
r_addr <= 16'h0001;
for (i = 0; i < 'h10000; i = i + 1) begin
#20
r_addr <= i;
r_data <= i[7:0];
r_write_x <= 1'b0;
end
for (i = 0; i < 'h10000; i = i + 1) begin
#20
r_addr <= i;
r_write_x <= 1'b1;
end
#20
$finish;
end
endmodule // RAMTest
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_MS__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_BLACKBOX_V
|
// file: ocxo_clk_pll.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______597.520____892.144
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary__________10.000___________0.00100
`timescale 1ps/1ps
module ocxo_clk_pll_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_ocxo_clk_pll),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_ocxo_clk_pll;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (63.750),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.375),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (100.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_ocxo_clk_pll),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_ocxo_clk_pll),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_ocxo_clk_pll),
.CLKIN1 (clk_in1_ocxo_clk_pll),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Output buffering
//-----------------------------------
assign clk_out1 = clk_out1_ocxo_clk_pll;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:23:38 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Mem/Mem_funcsim.v
// Design : Mem
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Mem,dist_mem_gen_v8_0,{}" *)
(* core_generation_info = "Mem,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_ADDR_WIDTH=9,C_DEFAULT_DATA=0,C_DEPTH=512,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=1,C_HAS_DPRA=1,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=Mem.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=2,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=5,C_PARSER_TYPE=1}" *)
(* NotValidForBitStream *)
module Mem
(a,
d,
dpra,
clk,
we,
spo,
dpo);
input [8:0]a;
input [4:0]d;
input [8:0]dpra;
input clk;
input we;
output [4:0]spo;
output [4:0]dpo;
wire [8:0]a;
wire clk;
wire [4:0]d;
wire [4:0]dpo;
wire [8:0]dpra;
wire [4:0]spo;
wire we;
wire [4:0]NLW_U0_qdpo_UNCONNECTED;
wire [4:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_CLK = "1" *)
(* C_HAS_D = "1" *)
(* C_HAS_WE = "1" *)
(* C_MEM_TYPE = "2" *)
(* DONT_TOUCH *)
(* c_addr_width = "9" *)
(* c_default_data = "0" *)
(* c_depth = "512" *)
(* c_elaboration_dir = "./" *)
(* c_has_dpo = "1" *)
(* c_has_dpra = "1" *)
(* c_has_i_ce = "0" *)
(* c_has_qdpo = "0" *)
(* c_has_qdpo_ce = "0" *)
(* c_has_qdpo_clk = "0" *)
(* c_has_qdpo_rst = "0" *)
(* c_has_qdpo_srst = "0" *)
(* c_has_qspo = "0" *)
(* c_has_qspo_ce = "0" *)
(* c_has_qspo_rst = "0" *)
(* c_has_qspo_srst = "0" *)
(* c_has_spo = "1" *)
(* c_mem_init_file = "Mem.mif" *)
(* c_parser_type = "1" *)
(* c_pipeline_stages = "0" *)
(* c_qce_joined = "0" *)
(* c_qualify_we = "0" *)
(* c_read_mif = "1" *)
(* c_reg_a_d_inputs = "0" *)
(* c_reg_dpra_input = "0" *)
(* c_sync_enable = "1" *)
(* c_width = "5" *)
Mem_dist_mem_gen_v8_0__parameterized0 U0
(.a(a),
.clk(clk),
.d(d),
.dpo(dpo),
.dpra(dpra),
.i_ce(1'b1),
.qdpo(NLW_U0_qdpo_UNCONNECTED[4:0]),
.qdpo_ce(1'b1),
.qdpo_clk(1'b0),
.qdpo_rst(1'b0),
.qdpo_srst(1'b0),
.qspo(NLW_U0_qspo_UNCONNECTED[4:0]),
.qspo_ce(1'b1),
.qspo_rst(1'b0),
.qspo_srst(1'b0),
.spo(spo),
.we(we));
endmodule
(* ORIG_REF_NAME = "dist_mem_gen_v8_0" *) (* C_FAMILY = "artix7" *) (* C_ADDR_WIDTH = "9" *)
(* C_DEFAULT_DATA = "0" *) (* C_DEPTH = "512" *) (* C_HAS_CLK = "1" *)
(* C_HAS_D = "1" *) (* C_HAS_DPO = "1" *) (* C_HAS_DPRA = "1" *)
(* C_HAS_I_CE = "0" *) (* C_HAS_QDPO = "0" *) (* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *) (* C_HAS_QDPO_RST = "0" *) (* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_QSPO = "0" *) (* C_HAS_QSPO_CE = "0" *) (* C_HAS_QSPO_RST = "0" *)
(* C_HAS_QSPO_SRST = "0" *) (* C_HAS_SPO = "1" *) (* C_HAS_WE = "1" *)
(* C_MEM_INIT_FILE = "Mem.mif" *) (* C_ELABORATION_DIR = "./" *) (* C_MEM_TYPE = "2" *)
(* C_PIPELINE_STAGES = "0" *) (* C_QCE_JOINED = "0" *) (* C_QUALIFY_WE = "0" *)
(* C_READ_MIF = "1" *) (* C_REG_A_D_INPUTS = "0" *) (* C_REG_DPRA_INPUT = "0" *)
(* C_SYNC_ENABLE = "1" *) (* C_WIDTH = "5" *) (* C_PARSER_TYPE = "1" *)
module Mem_dist_mem_gen_v8_0__parameterized0
(a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo);
input [8:0]a;
input [4:0]d;
input [8:0]dpra;
input clk;
input we;
input i_ce;
input qspo_ce;
input qdpo_ce;
input qdpo_clk;
input qspo_rst;
input qdpo_rst;
input qspo_srst;
input qdpo_srst;
output [4:0]spo;
output [4:0]dpo;
output [4:0]qspo;
output [4:0]qdpo;
wire \<const0> ;
wire [8:0]a;
wire clk;
wire [4:0]d;
wire [4:0]dpo;
wire [8:0]dpra;
wire [4:0]spo;
wire we;
assign qdpo[4] = \<const0> ;
assign qdpo[3] = \<const0> ;
assign qdpo[2] = \<const0> ;
assign qdpo[1] = \<const0> ;
assign qdpo[0] = \<const0> ;
assign qspo[4] = \<const0> ;
assign qspo[3] = \<const0> ;
assign qspo[2] = \<const0> ;
assign qspo[1] = \<const0> ;
assign qspo[0] = \<const0> ;
GND GND
(.G(\<const0> ));
Mem_dist_mem_gen_v8_0_synth \synth_options.dist_mem_inst
(.a(a),
.clk(clk),
.d(d),
.dpo(dpo),
.dpra(dpra),
.spo(spo),
.we(we));
endmodule
(* ORIG_REF_NAME = "dist_mem_gen_v8_0_synth" *)
module Mem_dist_mem_gen_v8_0_synth
(spo,
dpo,
clk,
d,
a,
dpra,
we);
output [4:0]spo;
output [4:0]dpo;
input clk;
input [4:0]d;
input [8:0]a;
input [8:0]dpra;
input we;
wire [8:0]a;
wire clk;
wire [4:0]d;
wire [4:0]dpo;
wire [8:0]dpra;
wire [4:0]spo;
wire we;
Mem_dpram__parameterized0 \gen_dp_ram.dpram_inst
(.a(a),
.clk(clk),
.d(d),
.dpo(dpo),
.dpra(dpra),
.spo(spo),
.we(we));
endmodule
(* ORIG_REF_NAME = "dpram" *)
module Mem_dpram__parameterized0
(spo,
dpo,
clk,
d,
a,
dpra,
we);
output [4:0]spo;
output [4:0]dpo;
input clk;
input [4:0]d;
input [8:0]a;
input [8:0]dpra;
input we;
wire [8:0]a;
wire clk;
wire [4:0]d;
wire [4:0]dpo;
wire [8:0]dpra;
wire n_0_ram_reg_0_127_0_0;
wire n_0_ram_reg_0_127_0_0_i_1;
wire n_0_ram_reg_0_127_1_1;
wire n_0_ram_reg_0_127_2_2;
wire n_0_ram_reg_0_127_3_3;
wire n_0_ram_reg_0_127_4_4;
wire n_0_ram_reg_128_255_0_0;
wire n_0_ram_reg_128_255_0_0_i_1;
wire n_0_ram_reg_128_255_1_1;
wire n_0_ram_reg_128_255_2_2;
wire n_0_ram_reg_128_255_3_3;
wire n_0_ram_reg_128_255_4_4;
wire n_0_ram_reg_256_383_0_0;
wire n_0_ram_reg_256_383_0_0_i_1;
wire n_0_ram_reg_256_383_1_1;
wire n_0_ram_reg_256_383_2_2;
wire n_0_ram_reg_256_383_3_3;
wire n_0_ram_reg_256_383_4_4;
wire n_0_ram_reg_384_511_0_0;
wire n_0_ram_reg_384_511_0_0_i_1;
wire n_0_ram_reg_384_511_1_1;
wire n_0_ram_reg_384_511_2_2;
wire n_0_ram_reg_384_511_3_3;
wire n_0_ram_reg_384_511_4_4;
wire n_1_ram_reg_0_127_0_0;
wire n_1_ram_reg_0_127_1_1;
wire n_1_ram_reg_0_127_2_2;
wire n_1_ram_reg_0_127_3_3;
wire n_1_ram_reg_0_127_4_4;
wire n_1_ram_reg_128_255_0_0;
wire n_1_ram_reg_128_255_1_1;
wire n_1_ram_reg_128_255_2_2;
wire n_1_ram_reg_128_255_3_3;
wire n_1_ram_reg_128_255_4_4;
wire n_1_ram_reg_256_383_0_0;
wire n_1_ram_reg_256_383_1_1;
wire n_1_ram_reg_256_383_2_2;
wire n_1_ram_reg_256_383_3_3;
wire n_1_ram_reg_256_383_4_4;
wire n_1_ram_reg_384_511_0_0;
wire n_1_ram_reg_384_511_1_1;
wire n_1_ram_reg_384_511_2_2;
wire n_1_ram_reg_384_511_3_3;
wire n_1_ram_reg_384_511_4_4;
(* RTL_KEEP = "true" *) wire [4:0]qdpo_int;
(* RTL_KEEP = "true" *) wire [4:0]qspo_int;
wire [4:0]spo;
wire we;
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\dpo[0]_INST_0
(.I0(n_0_ram_reg_384_511_0_0),
.I1(n_0_ram_reg_256_383_0_0),
.I2(dpra[8]),
.I3(n_0_ram_reg_128_255_0_0),
.I4(dpra[7]),
.I5(n_0_ram_reg_0_127_0_0),
.O(dpo[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\dpo[1]_INST_0
(.I0(n_0_ram_reg_384_511_1_1),
.I1(n_0_ram_reg_256_383_1_1),
.I2(dpra[8]),
.I3(n_0_ram_reg_128_255_1_1),
.I4(dpra[7]),
.I5(n_0_ram_reg_0_127_1_1),
.O(dpo[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\dpo[2]_INST_0
(.I0(n_0_ram_reg_384_511_2_2),
.I1(n_0_ram_reg_256_383_2_2),
.I2(dpra[8]),
.I3(n_0_ram_reg_128_255_2_2),
.I4(dpra[7]),
.I5(n_0_ram_reg_0_127_2_2),
.O(dpo[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\dpo[3]_INST_0
(.I0(n_0_ram_reg_384_511_3_3),
.I1(n_0_ram_reg_256_383_3_3),
.I2(dpra[8]),
.I3(n_0_ram_reg_128_255_3_3),
.I4(dpra[7]),
.I5(n_0_ram_reg_0_127_3_3),
.O(dpo[3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\dpo[4]_INST_0
(.I0(n_0_ram_reg_384_511_4_4),
.I1(n_0_ram_reg_256_383_4_4),
.I2(dpra[8]),
.I3(n_0_ram_reg_128_255_4_4),
.I4(dpra[7]),
.I5(n_0_ram_reg_0_127_4_4),
.O(dpo[4]));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qdpo_int_reg[0]
(.C(clk),
.CE(1'b1),
.D(dpo[0]),
.Q(qdpo_int[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qdpo_int_reg[1]
(.C(clk),
.CE(1'b1),
.D(dpo[1]),
.Q(qdpo_int[1]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qdpo_int_reg[2]
(.C(clk),
.CE(1'b1),
.D(dpo[2]),
.Q(qdpo_int[2]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qdpo_int_reg[3]
(.C(clk),
.CE(1'b1),
.D(dpo[3]),
.Q(qdpo_int[3]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qdpo_int_reg[4]
(.C(clk),
.CE(1'b1),
.D(dpo[4]),
.Q(qdpo_int[4]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[0]
(.C(clk),
.CE(1'b1),
.D(spo[0]),
.Q(qspo_int[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[1]
(.C(clk),
.CE(1'b1),
.D(spo[1]),
.Q(qspo_int[1]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[2]
(.C(clk),
.CE(1'b1),
.D(spo[2]),
.Q(qspo_int[2]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[3]
(.C(clk),
.CE(1'b1),
.D(spo[3]),
.Q(qspo_int[3]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[4]
(.C(clk),
.CE(1'b1),
.D(spo[4]),
.Q(qspo_int[4]),
.R(1'b0));
RAM128X1D #(
.INIT(128'h000060000180000600001800007FFFFF))
ram_reg_0_127_0_0
(.A(a[6:0]),
.D(d[0]),
.DPO(n_0_ram_reg_0_127_0_0),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_0_127_0_0),
.WCLK(clk),
.WE(n_0_ram_reg_0_127_0_0_i_1));
LUT3 #(
.INIT(8'h02))
ram_reg_0_127_0_0_i_1
(.I0(we),
.I1(a[7]),
.I2(a[8]),
.O(n_0_ram_reg_0_127_0_0_i_1));
RAM128X1D #(
.INIT(128'h000060000180000600001800007FFFFF))
ram_reg_0_127_1_1
(.A(a[6:0]),
.D(d[1]),
.DPO(n_0_ram_reg_0_127_1_1),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_0_127_1_1),
.WCLK(clk),
.WE(n_0_ram_reg_0_127_0_0_i_1));
RAM128X1D #(
.INIT(128'h00000000000000000000000000000000))
ram_reg_0_127_2_2
(.A(a[6:0]),
.D(d[2]),
.DPO(n_0_ram_reg_0_127_2_2),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_0_127_2_2),
.WCLK(clk),
.WE(n_0_ram_reg_0_127_0_0_i_1));
RAM128X1D #(
.INIT(128'h000060000180000600001800007FFFFF))
ram_reg_0_127_3_3
(.A(a[6:0]),
.D(d[3]),
.DPO(n_0_ram_reg_0_127_3_3),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_0_127_3_3),
.WCLK(clk),
.WE(n_0_ram_reg_0_127_0_0_i_1));
RAM128X1D #(
.INIT(128'h000060000180000600001800007FFFFF))
ram_reg_0_127_4_4
(.A(a[6:0]),
.D(d[4]),
.DPO(n_0_ram_reg_0_127_4_4),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_0_127_4_4),
.WCLK(clk),
.WE(n_0_ram_reg_0_127_0_0_i_1));
RAM128X1D #(
.INIT(128'h00060000180000600001800006000018))
ram_reg_128_255_0_0
(.A(a[6:0]),
.D(d[0]),
.DPO(n_0_ram_reg_128_255_0_0),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_128_255_0_0),
.WCLK(clk),
.WE(n_0_ram_reg_128_255_0_0_i_1));
LUT3 #(
.INIT(8'h40))
ram_reg_128_255_0_0_i_1
(.I0(a[8]),
.I1(a[7]),
.I2(we),
.O(n_0_ram_reg_128_255_0_0_i_1));
RAM128X1D #(
.INIT(128'h00060000180000600001800006000018))
ram_reg_128_255_1_1
(.A(a[6:0]),
.D(d[1]),
.DPO(n_0_ram_reg_128_255_1_1),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_128_255_1_1),
.WCLK(clk),
.WE(n_0_ram_reg_128_255_0_0_i_1));
RAM128X1D #(
.INIT(128'h00000000000000000000000000000000))
ram_reg_128_255_2_2
(.A(a[6:0]),
.D(d[2]),
.DPO(n_0_ram_reg_128_255_2_2),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_128_255_2_2),
.WCLK(clk),
.WE(n_0_ram_reg_128_255_0_0_i_1));
RAM128X1D #(
.INIT(128'h00060000180000600001800006000018))
ram_reg_128_255_3_3
(.A(a[6:0]),
.D(d[3]),
.DPO(n_0_ram_reg_128_255_3_3),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_128_255_3_3),
.WCLK(clk),
.WE(n_0_ram_reg_128_255_0_0_i_1));
RAM128X1D #(
.INIT(128'h00060000180000600001800006000018))
ram_reg_128_255_4_4
(.A(a[6:0]),
.D(d[4]),
.DPO(n_0_ram_reg_128_255_4_4),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_128_255_4_4),
.WCLK(clk),
.WE(n_0_ram_reg_128_255_0_0_i_1));
RAM128X1D #(
.INIT(128'h00600001800006000018000060000180))
ram_reg_256_383_0_0
(.A(a[6:0]),
.D(d[0]),
.DPO(n_0_ram_reg_256_383_0_0),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_256_383_0_0),
.WCLK(clk),
.WE(n_0_ram_reg_256_383_0_0_i_1));
LUT3 #(
.INIT(8'h40))
ram_reg_256_383_0_0_i_1
(.I0(a[7]),
.I1(a[8]),
.I2(we),
.O(n_0_ram_reg_256_383_0_0_i_1));
RAM128X1D #(
.INIT(128'h00600001800006000018000060000180))
ram_reg_256_383_1_1
(.A(a[6:0]),
.D(d[1]),
.DPO(n_0_ram_reg_256_383_1_1),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_256_383_1_1),
.WCLK(clk),
.WE(n_0_ram_reg_256_383_0_0_i_1));
RAM128X1D #(
.INIT(128'h00000000000000000000000000000000))
ram_reg_256_383_2_2
(.A(a[6:0]),
.D(d[2]),
.DPO(n_0_ram_reg_256_383_2_2),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_256_383_2_2),
.WCLK(clk),
.WE(n_0_ram_reg_256_383_0_0_i_1));
RAM128X1D #(
.INIT(128'h00600001800006000018000060000180))
ram_reg_256_383_3_3
(.A(a[6:0]),
.D(d[3]),
.DPO(n_0_ram_reg_256_383_3_3),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_256_383_3_3),
.WCLK(clk),
.WE(n_0_ram_reg_256_383_0_0_i_1));
RAM128X1D #(
.INIT(128'h00600001800006000018000060000180))
ram_reg_256_383_4_4
(.A(a[6:0]),
.D(d[4]),
.DPO(n_0_ram_reg_256_383_4_4),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_256_383_4_4),
.WCLK(clk),
.WE(n_0_ram_reg_256_383_0_0_i_1));
RAM128X1D #(
.INIT(128'h0000000FFFFFE0000180000600001800))
ram_reg_384_511_0_0
(.A(a[6:0]),
.D(d[0]),
.DPO(n_0_ram_reg_384_511_0_0),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_384_511_0_0),
.WCLK(clk),
.WE(n_0_ram_reg_384_511_0_0_i_1));
LUT3 #(
.INIT(8'h80))
ram_reg_384_511_0_0_i_1
(.I0(we),
.I1(a[7]),
.I2(a[8]),
.O(n_0_ram_reg_384_511_0_0_i_1));
RAM128X1D #(
.INIT(128'h0000000FFFFFE0000180000600001800))
ram_reg_384_511_1_1
(.A(a[6:0]),
.D(d[1]),
.DPO(n_0_ram_reg_384_511_1_1),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_384_511_1_1),
.WCLK(clk),
.WE(n_0_ram_reg_384_511_0_0_i_1));
RAM128X1D #(
.INIT(128'h00000000000000000000000000000000))
ram_reg_384_511_2_2
(.A(a[6:0]),
.D(d[2]),
.DPO(n_0_ram_reg_384_511_2_2),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_384_511_2_2),
.WCLK(clk),
.WE(n_0_ram_reg_384_511_0_0_i_1));
RAM128X1D #(
.INIT(128'h0000000FFFFFE0000180000600001800))
ram_reg_384_511_3_3
(.A(a[6:0]),
.D(d[3]),
.DPO(n_0_ram_reg_384_511_3_3),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_384_511_3_3),
.WCLK(clk),
.WE(n_0_ram_reg_384_511_0_0_i_1));
RAM128X1D #(
.INIT(128'h0000000FFFFFE0000180000600001800))
ram_reg_384_511_4_4
(.A(a[6:0]),
.D(d[4]),
.DPO(n_0_ram_reg_384_511_4_4),
.DPRA(dpra[6:0]),
.SPO(n_1_ram_reg_384_511_4_4),
.WCLK(clk),
.WE(n_0_ram_reg_384_511_0_0_i_1));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0
(.I0(n_1_ram_reg_384_511_0_0),
.I1(n_1_ram_reg_256_383_0_0),
.I2(a[8]),
.I3(n_1_ram_reg_128_255_0_0),
.I4(a[7]),
.I5(n_1_ram_reg_0_127_0_0),
.O(spo[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0
(.I0(n_1_ram_reg_384_511_1_1),
.I1(n_1_ram_reg_256_383_1_1),
.I2(a[8]),
.I3(n_1_ram_reg_128_255_1_1),
.I4(a[7]),
.I5(n_1_ram_reg_0_127_1_1),
.O(spo[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[2]_INST_0
(.I0(n_1_ram_reg_384_511_2_2),
.I1(n_1_ram_reg_256_383_2_2),
.I2(a[8]),
.I3(n_1_ram_reg_128_255_2_2),
.I4(a[7]),
.I5(n_1_ram_reg_0_127_2_2),
.O(spo[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[3]_INST_0
(.I0(n_1_ram_reg_384_511_3_3),
.I1(n_1_ram_reg_256_383_3_3),
.I2(a[8]),
.I3(n_1_ram_reg_128_255_3_3),
.I4(a[7]),
.I5(n_1_ram_reg_0_127_3_3),
.O(spo[3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[4]_INST_0
(.I0(n_1_ram_reg_384_511_4_4),
.I1(n_1_ram_reg_256_383_4_4),
.I2(a[8]),
.I3(n_1_ram_reg_128_255_4_4),
.I4(a[7]),
.I5(n_1_ram_reg_0_127_4_4),
.O(spo[4]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_TB_V
`define SKY130_FD_SC_LS__HA_TB_V
/**
* ha: Half adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ha.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__ha dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module cf_dcfilter (
// data interface
adc_clk,
data_in,
data_out,
// control interface
coeff);
// data interface
input adc_clk;
input [13:0] data_in;
output [13:0] data_out;
// control interface
input [15:0] coeff;
// internal registers
reg [13:0] dc_offset = 'd0;
reg [13:0] data_out = 'd0;
// internal signals
wire [30:0] dc_offset_31_s;
// cancelling the dc offset
always @(posedge adc_clk) begin
dc_offset <= dc_offset_31_s[30:17];
data_out <= data_in - dc_offset;
end
cf_dcfilter_1 i_dcfilter_1 (
.clk (adc_clk),
.d (data_in),
.b (coeff),
.a (dc_offset_31_s[30:17]),
.c (dc_offset_31_s[30:17]),
.p (dc_offset_31_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: generic_cntr_reg.v
// Project: NF2.1
// Author: Jad Naous/Glen Gibb
// Description: Implements a generic counter register block that uses RAM and
// temporarily stores updates in registers before committing them to RAM.
//
// This design is efficient in that the update registers are kept small so one
// large adder can be shared amongst all registers. The routing resources
// associated with the RAM simplifies the routing of the registers.
// Demultiplexes, stores and serves register requests
//
// To use this block you should specify a number of parameters at
// instantiation:
// TAG -- the tag to match against (probably defined in udp_defines.v)
// REG_ADDR_WIDTH -- width of the address block allocated to this register
// group. It is important that this is specified correctly
// as this width is used to enable tag matching
// NUM_REGS_USED -- how many registers in this block?
// NUM_INSTANCES -- how many instances of the counters shall we emulate
//
// Other parameter which may be useful
// INPUT_WIDTH -- width of each update input
// MIN_UPDATE_INTERVAL -- how many clock cycles between successive update
// inputs
// RESET_ON_READ -- reset registers when read
//
// Last Modified: 2/22/08 by Jad Naous to allow decrements and to not ack addresses
// that are not found.
// 3/29/08 by Jad Naous to force reg file into bram
// 4/14/08 by Jad Naous to make bram write-first, fixing an issue
///////////////////////////////////////////////////////////////////////////////
module generic_cntr_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0, // Tag to match against
parameter REG_ADDR_WIDTH = 5, // Width of block addresses
parameter NUM_REGS_USED = 8, // How many registers
parameter REG_START_ADDR = 0, // Address of the first counter
parameter INPUT_WIDTH = 1, // Width of each update request
parameter MIN_UPDATE_INTERVAL = 8, // Clocks between successive inputs
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH, // How wide should each counter be?
parameter RESET_ON_READ = 0,
// Don't modify the parameters below. They are used to calculate the
// widths of the various register inputs/outputs.
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED, // address of last counter + 1
parameter UPDATES_START = REG_START_ADDR * INPUT_WIDTH, // first bit of the updates vector
parameter UPDATES_END = REG_END_ADDR * INPUT_WIDTH // bit after last bit of the updates vector
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- update interface
input [UPDATES_END - 1:UPDATES_START] updates,
input [REG_END_ADDR-1:REG_START_ADDR] decrement, // if 1 then subtract the update, else add.
input clk,
input reset
);
`LOG2_FUNC
`CEILDIV_FUNC
// ------------- Internal parameters --------------
localparam MIN_CYCLE_TIME = NUM_REGS_USED + 1;
// Calculate the number of updates we can see in a single cycle through the
// RAM.
//
// This should be:
// ceil(MIN_CYCLE_TIME / MIN_UPDATE_INTERVAL)
localparam UPDATES_PER_CYCLE = ceildiv(MIN_CYCLE_TIME, MIN_UPDATE_INTERVAL);
localparam LOG_UPDATES_PER_CYCLE = log2(UPDATES_PER_CYCLE);
// Calculate how much storage to allocate for each delta
//
// A single update requires INPUT_WIDTH bits of storage
// In the worst case we would add the updates and get a total of
// (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE
// This can be represented in:
// log2( (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE )
// = INPUT_WIDTH + log2(UPDATES_PER_CYCLE)
// we add one for sign extension.
localparam DELTA_WIDTH = INPUT_WIDTH + LOG_UPDATES_PER_CYCLE + 1;
localparam RESET = 0,
NORMAL = 1;
// ------------- Wires/reg ------------------
reg [REG_WIDTH-1:0] reg_file [REG_START_ADDR:REG_END_ADDR-1];
wire [REG_ADDR_WIDTH-1:0] addr, addr_d1;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
reg [REG_ADDR_WIDTH-1:0] reg_cnt;
wire [REG_ADDR_WIDTH-1:0] reg_cnt_nxt;
wire [REG_ADDR_WIDTH-1:0] reg_file_rd_addr;
reg [REG_ADDR_WIDTH-1:0] reg_file_rd_addr_ram;
wire [REG_ADDR_WIDTH-1:0] reg_file_wr_addr;
reg [DELTA_WIDTH-1:0] deltas[REG_START_ADDR:REG_END_ADDR-1];
wire [DELTA_WIDTH-1:0] delta;
wire [DELTA_WIDTH-1:0] update[REG_START_ADDR:REG_END_ADDR-1];
wire [REG_WIDTH-1:0] reg_file_out;
reg [REG_WIDTH-1:0] reg_file_in;
reg reg_file_wr_en;
reg [REG_ADDR_WIDTH-1:0] reg_cnt_d1;
reg reg_rd_req_good_d1, reg_wr_req_good_d1;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in_d1;
reg reg_req_in_d1;
reg reg_ack_in_d1;
reg reg_rd_wr_L_in_d1;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_in_d1;
integer i;
reg state;
// -------------- Logic --------------------
assign addr = reg_addr_in[REG_ADDR_WIDTH-1:0];
assign addr_d1 = reg_addr_in_d1[REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);
assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);
assign reg_cnt_nxt = (reg_cnt==REG_END_ADDR-1'b1) ? REG_START_ADDR : reg_cnt + 1'b1;
assign delta = deltas[reg_cnt_d1];
assign reg_file_rd_addr = reg_rd_req_good ? addr : reg_cnt;
assign reg_file_wr_addr = (state == RESET
? reg_cnt
: (reg_wr_req_good_d1 || reg_rd_req_good_d1)
? addr_d1 : reg_cnt_d1);
// choose when and what to write in the ram
always @(*) begin
reg_file_in = reg_file_out + {{(REG_WIDTH - DELTA_WIDTH){delta[DELTA_WIDTH-1]}}, delta};
reg_file_wr_en = 0;
if(state == RESET || (reg_rd_req_good_d1 && RESET_ON_READ)) begin
reg_file_wr_en = 1;
reg_file_in = 0;
end
else if(!reg_wr_req_good_d1 && !reg_rd_req_good_d1) begin
reg_file_wr_en = 1;
end
else if(reg_wr_req_good_d1) begin
reg_file_in = reg_data_in_d1;
reg_file_wr_en = 1;
end
end // always @ (*)
// Generate the individual update lines from the updates vector
//
// Note: I have the ugly bit selection because ModelSim doesn't seem to
// like parameters used in :+ selects! :-(
generate
genvar j;
for (j = REG_START_ADDR; j < REG_END_ADDR; j = j + 1) begin : update_gen
assign update[j] = {{(DELTA_WIDTH - INPUT_WIDTH){1'b0}}, updates[(j + 1) * INPUT_WIDTH - 1 : j * INPUT_WIDTH]};
end
endgenerate
/*********** RAM *************/
always @(posedge clk) begin
// write to the register file
if(reg_file_wr_en) begin
reg_file[reg_file_wr_addr] <= reg_file_in;
end
reg_file_rd_addr_ram <= reg_file_rd_addr;
end
assign reg_file_out = reg_file[reg_file_rd_addr_ram];
/****************************/
// State machine that handles register access from the CPU
always @(posedge clk) begin
if(reset) begin
reg_cnt <= REG_START_ADDR;
reg_rd_req_good_d1 <= 0;
reg_wr_req_good_d1 <= 0;
reg_req_in_d1 <= 0;
reg_ack_out <= 0;
reg_req_out <= 0;
state <= RESET;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
deltas[i] <= 0;
end
end // if (reset)
else begin
reg_cnt_d1 <= reg_cnt;
if(state == RESET) begin
reg_cnt <= reg_cnt_nxt;
if(reg_cnt == REG_END_ADDR-1'b1) begin
state <= NORMAL;
end
end
else begin
/*********************************************************************
* first stage - read bram, latch reg req signals
*/
reg_cnt <= (reg_rd_req_good || reg_wr_req_good) ? reg_cnt : reg_cnt_nxt;
reg_rd_req_good_d1 <= reg_rd_req_good;
reg_wr_req_good_d1 <= reg_wr_req_good;
reg_addr_in_d1 <= reg_addr_in;
reg_data_in_d1 <= reg_data_in;
reg_req_in_d1 <= reg_req_in;
reg_ack_in_d1 <= reg_ack_in;
reg_rd_wr_L_in_d1 <= reg_rd_wr_L_in;
reg_src_in_d1 <= reg_src_in;
// synthesis translate_off
if(reg_ack_in && (reg_rd_req_good || reg_wr_req_good)) begin
$display("%t %m ERROR: Register request already ack even though", $time);
$display("it should be destined to this module. This can happen");
$display("if two modules have aliased register addresses.");
$stop;
end
// synthesis translate_on
/********************************************************************
* second stage - output rd req or do write req or delta update
*/
reg_ack_out <= reg_rd_req_good_d1 || reg_wr_req_good_d1 || reg_ack_in_d1;
reg_data_out <= reg_rd_req_good_d1 ? reg_file_out : reg_data_in_d1;
reg_addr_out <= reg_addr_in_d1;
reg_req_out <= reg_req_in_d1;
reg_rd_wr_L_out <= reg_rd_wr_L_in_d1;
reg_src_out <= reg_src_in_d1;
/*******************************************************************
* update the deltas
*/
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
// if we just update the register corresponding to this delta then
// clear it.
if ((i==reg_cnt_d1) // this delta was committed to reg_file
&& !reg_wr_req_good_d1 // we didn't write in this cycle
&& !(reg_rd_req_good_d1 && RESET_ON_READ) // we didn't read and reset
) begin
deltas[i] <= decrement[i] ? -update[i] : update[i];
end
else begin
deltas[i] <= decrement[i] ? deltas[i] - update[i] : deltas[i] + update[i];
end
end // for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1)
end // else: !if(state == RESET)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_PP_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_TB_V
`define SKY130_FD_SC_HD__TAPVGND_TB_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_TB_V
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// Simple 1/2 rate convolutional encoder.
//
//------------------------------------------------------------------------------
`ifndef _ZL_CONV_ENCODER_V_
`define _ZL_CONV_ENCODER_V_
module zl_conv_encoder #
(
parameter I_poly = 0,
parameter Q_poly = 0,
parameter K = 0
)
(
input clk,
input rst_n,
//
input [7:0] data_in,
input data_in_req,
output data_in_ack,
//
output data_out_i,
output data_out_q,
output data_out_req,
input data_out_ack
);
integer i;
reg [2:0] in_bit_sel;
wire stall;
reg [K-1:0] shift_reg;
always @(*) begin
shift_reg[K-1] = data_in[in_bit_sel];
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
for(i=0;i<K-1;i=i+1) begin
shift_reg[i] <= 1'b0;
end
end
else if(!stall) begin
for(i=0;i<K-1;i=i+1) begin
shift_reg[i] <= shift_reg[i+1];
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
in_bit_sel <= 3'b111; // MSB first
end
else if(!stall) begin
in_bit_sel <= in_bit_sel - 1'b1;
end
end
assign data_out_req = data_in_req;
assign data_in_ack = data_in_req && (in_bit_sel == 3'b000) && data_out_ack;
assign stall = !(data_in_req && data_out_ack);
assign data_out_i = ^(shift_reg & I_poly);
assign data_out_q = ^(shift_reg & Q_poly);
endmodule // zl_conv_encoder
`endif // _ZL_CONV_ENCODER_V_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_4_V
`define SKY130_FD_SC_HS__A221OI_4_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_4_V
|
// Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2013 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module pcie_compiler_0_core (
AvlClk_i,
CraAddress_i,
CraByteEnable_i,
CraChipSelect_i,
CraRead,
CraWrite,
CraWriteData_i,
Rstn_i,
RxmIrqNum_i,
RxmIrq_i,
RxmReadDataValid_i,
RxmReadData_i,
RxmWaitRequest_i,
TxsAddress_i,
TxsBurstCount_i,
TxsByteEnable_i,
TxsChipSelect_i,
TxsRead_i,
TxsWriteData_i,
TxsWrite_i,
aer_msi_num,
app_int_sts,
app_msi_num,
app_msi_req,
app_msi_tc,
core_clk_in,
cpl_err,
cpl_pending,
crst,
hpg_ctrler,
lmi_addr,
lmi_din,
lmi_rden,
lmi_wren,
npor,
pclk_central,
pclk_ch0,
pex_msi_num,
pld_clk,
pll_fixed_clk,
pm_auxpwr,
pm_data,
pm_event,
pme_to_cr,
rc_areset,
rc_inclk_eq_125mhz,
rc_pll_locked,
rc_rx_pll_locked_one,
rx_st_mask0,
rx_st_ready0,
srst,
test_in,
tx_st_data0,
tx_st_data0_p1,
tx_st_eop0,
tx_st_eop0_p1,
tx_st_err0,
tx_st_sop0,
tx_st_sop0_p1,
tx_st_valid0,
phystatus0_ext,
rxdata0_ext,
rxdatak0_ext,
rxelecidle0_ext,
rxstatus0_ext,
rxvalid0_ext,
CraIrq_o,
CraReadData_o,
CraWaitRequest_o,
RxmAddress_o,
RxmBurstCount_o,
RxmByteEnable_o,
RxmRead_o,
RxmWriteData_o,
RxmWrite_o,
TxsReadDataValid_o,
TxsReadData_o,
TxsWaitRequest_o,
app_int_ack,
app_msi_ack,
avs_pcie_reconfig_readdata,
avs_pcie_reconfig_readdatavalid,
avs_pcie_reconfig_waitrequest,
core_clk_out,
derr_cor_ext_rcv0,
derr_cor_ext_rpl,
derr_rpl,
dl_ltssm,
dlup_exit,
eidle_infer_sel,
ev_128ns,
ev_1us,
hip_extraclkout,
hotrst_exit,
int_status,
l2_exit,
lane_act,
lmi_ack,
lmi_dout,
npd_alloc_1cred_vc0,
npd_cred_vio_vc0,
nph_alloc_1cred_vc0,
nph_cred_vio_vc0,
pme_to_sr,
r2c_err0,
rate_ext,
rc_gxb_powerdown,
rc_rx_analogreset,
rc_rx_digitalreset,
rc_tx_digitalreset,
reset_status,
rx_fifo_empty0,
rx_fifo_full0,
rx_st_bardec0,
rx_st_be0,
rx_st_be0_p1,
rx_st_data0,
rx_st_data0_p1,
rx_st_eop0,
rx_st_eop0_p1,
rx_st_err0,
rx_st_sop0,
rx_st_sop0_p1,
rx_st_valid0,
serr_out,
suc_spd_neg,
swdn_wake,
swup_hotrst,
test_out,
tl_cfg_add,
tl_cfg_ctl,
tl_cfg_ctl_wr,
tl_cfg_sts,
tl_cfg_sts_wr,
tx_cred0,
tx_deemph,
tx_fifo_empty0,
tx_fifo_full0,
tx_fifo_rdptr0,
tx_fifo_wrptr0,
tx_margin,
tx_st_ready0,
use_pcie_reconfig,
wake_oen,
powerdown0_ext,
rxpolarity0_ext,
txcompl0_ext,
txdata0_ext,
txdatak0_ext,
txdetectrx0_ext,
txelecidle0_ext);
input AvlClk_i;
input [11:0] CraAddress_i;
input [3:0] CraByteEnable_i;
input CraChipSelect_i;
input CraRead;
input CraWrite;
input [31:0] CraWriteData_i;
input Rstn_i;
input [5:0] RxmIrqNum_i;
input RxmIrq_i;
input RxmReadDataValid_i;
input [63:0] RxmReadData_i;
input RxmWaitRequest_i;
input [21:0] TxsAddress_i;
input [9:0] TxsBurstCount_i;
input [7:0] TxsByteEnable_i;
input TxsChipSelect_i;
input TxsRead_i;
input [63:0] TxsWriteData_i;
input TxsWrite_i;
input [4:0] aer_msi_num;
input app_int_sts;
input [4:0] app_msi_num;
input app_msi_req;
input [2:0] app_msi_tc;
input core_clk_in;
input [6:0] cpl_err;
input cpl_pending;
input crst;
input [4:0] hpg_ctrler;
input [11:0] lmi_addr;
input [31:0] lmi_din;
input lmi_rden;
input lmi_wren;
input npor;
input pclk_central;
input pclk_ch0;
input [4:0] pex_msi_num;
input pld_clk;
input pll_fixed_clk;
input pm_auxpwr;
input [9:0] pm_data;
input pm_event;
input pme_to_cr;
input rc_areset;
input rc_inclk_eq_125mhz;
input rc_pll_locked;
input rc_rx_pll_locked_one;
input rx_st_mask0;
input rx_st_ready0;
input srst;
input [39:0] test_in;
input [63:0] tx_st_data0;
input [63:0] tx_st_data0_p1;
input tx_st_eop0;
input tx_st_eop0_p1;
input tx_st_err0;
input tx_st_sop0;
input tx_st_sop0_p1;
input tx_st_valid0;
input phystatus0_ext;
input [7:0] rxdata0_ext;
input rxdatak0_ext;
input rxelecidle0_ext;
input [2:0] rxstatus0_ext;
input rxvalid0_ext;
output CraIrq_o;
output [31:0] CraReadData_o;
output CraWaitRequest_o;
output [31:0] RxmAddress_o;
output [9:0] RxmBurstCount_o;
output [7:0] RxmByteEnable_o;
output RxmRead_o;
output [63:0] RxmWriteData_o;
output RxmWrite_o;
output TxsReadDataValid_o;
output [63:0] TxsReadData_o;
output TxsWaitRequest_o;
output app_int_ack;
output app_msi_ack;
output [15:0] avs_pcie_reconfig_readdata;
output avs_pcie_reconfig_readdatavalid;
output avs_pcie_reconfig_waitrequest;
output core_clk_out;
output derr_cor_ext_rcv0;
output derr_cor_ext_rpl;
output derr_rpl;
output [4:0] dl_ltssm;
output dlup_exit;
output [23:0] eidle_infer_sel;
output ev_128ns;
output ev_1us;
output [1:0] hip_extraclkout;
output hotrst_exit;
output [3:0] int_status;
output l2_exit;
output [3:0] lane_act;
output lmi_ack;
output [31:0] lmi_dout;
output npd_alloc_1cred_vc0;
output npd_cred_vio_vc0;
output nph_alloc_1cred_vc0;
output nph_cred_vio_vc0;
output pme_to_sr;
output r2c_err0;
output rate_ext;
output rc_gxb_powerdown;
output rc_rx_analogreset;
output rc_rx_digitalreset;
output rc_tx_digitalreset;
output reset_status;
output rx_fifo_empty0;
output rx_fifo_full0;
output [7:0] rx_st_bardec0;
output [7:0] rx_st_be0;
output [7:0] rx_st_be0_p1;
output [63:0] rx_st_data0;
output [63:0] rx_st_data0_p1;
output rx_st_eop0;
output rx_st_eop0_p1;
output rx_st_err0;
output rx_st_sop0;
output rx_st_sop0_p1;
output rx_st_valid0;
output serr_out;
output suc_spd_neg;
output swdn_wake;
output swup_hotrst;
output [63:0] test_out;
output [3:0] tl_cfg_add;
output [31:0] tl_cfg_ctl;
output tl_cfg_ctl_wr;
output [52:0] tl_cfg_sts;
output tl_cfg_sts_wr;
output [35:0] tx_cred0;
output [7:0] tx_deemph;
output tx_fifo_empty0;
output tx_fifo_full0;
output [3:0] tx_fifo_rdptr0;
output [3:0] tx_fifo_wrptr0;
output [23:0] tx_margin;
output tx_st_ready0;
output use_pcie_reconfig;
output wake_oen;
output [1:0] powerdown0_ext;
output rxpolarity0_ext;
output txcompl0_ext;
output [7:0] txdata0_ext;
output txdatak0_ext;
output txdetectrx0_ext;
output txelecidle0_ext;
wire [7:0] signal_wire0 = 8'b0;
wire signal_wire1 = 1'b0;
wire signal_wire2 = 1'b0;
wire signal_wire3 = 1'b0;
wire signal_wire4 = 1'b0;
wire signal_wire5 = 1'b0;
wire [15:0] signal_wire6 = 16'b0;
wire [1:0] signal_wire7 = 2'b0;
wire [2:0] signal_wire8 = 3'b0;
wire [6:0] signal_wire9 = 7'b0;
wire signal_wire10 = 1'b1;
wire signal_wire11 = 1'b0;
wire signal_wire12 = 1'b0;
wire [12:0] signal_wire13 = 13'b0;
wire [11:0] signal_wire14 = 12'b0;
wire [7:0] signal_wire15 = 8'b0;
wire signal_wire16 = 1'b0;
wire [2:0] signal_wire17 = 3'b0;
wire [3:0] signal_wire18 = 4'b0;
wire [3:0] signal_wire19 = 4'b0;
wire signal_wire20 = 1'b0;
wire signal_wire21 = 1'b0;
wire signal_wire22 = 1'b0;
wire signal_wire23 = 1'b0;
wire signal_wire24 = 1'b0;
wire [2:0] signal_wire25 = 3'b0;
wire signal_wire26 = 1'b0;
wire [1:0] signal_wire27 = 2'b0;
wire [7:0] signal_wire28 = 8'b0;
wire [23:0] signal_wire29 = 24'b0;
wire [2:0] signal_wire30 = 3'b0;
wire signal_wire31 = 1'b0;
wire signal_wire32 = 1'b0;
wire [63:0] signal_wire33 = 64'b0;
wire [63:0] signal_wire34 = 64'b0;
wire signal_wire35 = 1'b0;
wire signal_wire36 = 1'b0;
wire signal_wire37 = 1'b0;
wire signal_wire38 = 1'b0;
wire signal_wire39 = 1'b0;
wire signal_wire40 = 1'b0;
wire signal_wire41 = 1'b0;
wire [7:0] signal_wire42 = 8'b0;
wire signal_wire43 = 1'b0;
wire signal_wire44 = 1'b0;
wire [2:0] signal_wire45 = 3'b0;
wire signal_wire46 = 1'b0;
wire signal_wire47 = 1'b0;
wire [7:0] signal_wire48 = 8'b0;
wire signal_wire49 = 1'b0;
wire signal_wire50 = 1'b0;
wire [2:0] signal_wire51 = 3'b0;
wire signal_wire52 = 1'b0;
wire signal_wire53 = 1'b0;
wire [7:0] signal_wire54 = 8'b0;
wire signal_wire55 = 1'b0;
wire signal_wire56 = 1'b0;
wire [2:0] signal_wire57 = 3'b0;
wire signal_wire58 = 1'b0;
wire signal_wire59 = 1'b0;
wire [7:0] signal_wire60 = 8'b0;
wire signal_wire61 = 1'b0;
wire signal_wire62 = 1'b0;
wire [2:0] signal_wire63 = 3'b0;
wire signal_wire64 = 1'b0;
wire signal_wire65 = 1'b0;
wire [7:0] signal_wire66 = 8'b0;
wire signal_wire67 = 1'b0;
wire signal_wire68 = 1'b0;
wire [2:0] signal_wire69 = 3'b0;
wire signal_wire70 = 1'b0;
wire signal_wire71 = 1'b0;
wire [7:0] signal_wire72 = 8'b0;
wire signal_wire73 = 1'b0;
wire signal_wire74 = 1'b0;
wire [2:0] signal_wire75 = 3'b0;
wire signal_wire76 = 1'b0;
wire signal_wire77 = 1'b0;
wire [7:0] signal_wire78 = 8'b0;
wire signal_wire79 = 1'b0;
wire signal_wire80 = 1'b0;
wire [2:0] signal_wire81 = 3'b0;
wire signal_wire82 = 1'b0;
altpcie_hip_pipen1b altpcie_hip_pipen1b_inst(
.AvlClk_i(AvlClk_i),
.CraAddress_i(CraAddress_i),
.CraByteEnable_i(CraByteEnable_i),
.CraChipSelect_i(CraChipSelect_i),
.CraRead(CraRead),
.CraWrite(CraWrite),
.CraWriteData_i(CraWriteData_i),
.Rstn_i(Rstn_i),
.RxmIrqNum_i(RxmIrqNum_i),
.RxmIrq_i(RxmIrq_i),
.RxmReadDataValid_i(RxmReadDataValid_i),
.RxmReadData_i(RxmReadData_i),
.RxmWaitRequest_i(RxmWaitRequest_i),
.TxsAddress_i(TxsAddress_i),
.TxsBurstCount_i(TxsBurstCount_i),
.TxsByteEnable_i(TxsByteEnable_i),
.TxsChipSelect_i(TxsChipSelect_i),
.TxsRead_i(TxsRead_i),
.TxsWriteData_i(TxsWriteData_i),
.TxsWrite_i(TxsWrite_i),
.aer_msi_num(aer_msi_num),
.app_int_sts(app_int_sts),
.app_msi_num(app_msi_num),
.app_msi_req(app_msi_req),
.app_msi_tc(app_msi_tc),
.avs_pcie_reconfig_address(signal_wire0),
.avs_pcie_reconfig_chipselect(signal_wire1),
.avs_pcie_reconfig_clk(signal_wire2),
.avs_pcie_reconfig_read(signal_wire3),
.avs_pcie_reconfig_rstn(signal_wire4),
.avs_pcie_reconfig_write(signal_wire5),
.avs_pcie_reconfig_writedata(signal_wire6),
.core_clk_in(core_clk_in),
.cpl_err(cpl_err),
.cpl_pending(cpl_pending),
.crst(crst),
.hpg_ctrler(hpg_ctrler),
.lmi_addr(lmi_addr),
.lmi_din(lmi_din),
.lmi_rden(lmi_rden),
.lmi_wren(lmi_wren),
.mode(signal_wire7),
.npor(npor),
.pclk_central(pclk_central),
.pclk_ch0(pclk_ch0),
.pex_msi_num(pex_msi_num),
.pld_clk(pld_clk),
.pll_fixed_clk(pll_fixed_clk),
.pm_auxpwr(pm_auxpwr),
.pm_data(pm_data),
.pm_event(pm_event),
.pme_to_cr(pme_to_cr),
.rc_areset(rc_areset),
.rc_inclk_eq_125mhz(rc_inclk_eq_125mhz),
.rc_pll_locked(rc_pll_locked),
.rc_rx_pll_locked_one(rc_rx_pll_locked_one),
.rx_st_mask0(rx_st_mask0),
.rx_st_ready0(rx_st_ready0),
.srst(srst),
.swdn_in(signal_wire8),
.swup_in(signal_wire9),
.test_in(test_in),
.tl_slotclk_cfg(signal_wire10),
.tlbp_dl_aspm_cr0(signal_wire11),
.tlbp_dl_comclk_reg(signal_wire12),
.tlbp_dl_ctrl_link2(signal_wire13),
.tlbp_dl_data_upfc(signal_wire14),
.tlbp_dl_hdr_upfc(signal_wire15),
.tlbp_dl_inh_dllp(signal_wire16),
.tlbp_dl_maxpload_dcr(signal_wire17),
.tlbp_dl_req_phycfg(signal_wire18),
.tlbp_dl_req_phypm(signal_wire19),
.tlbp_dl_req_upfc(signal_wire20),
.tlbp_dl_req_wake(signal_wire21),
.tlbp_dl_rx_ecrcchk(signal_wire22),
.tlbp_dl_snd_upfc(signal_wire23),
.tlbp_dl_tx_reqpm(signal_wire24),
.tlbp_dl_tx_typpm(signal_wire25),
.tlbp_dl_txcfg_extsy(signal_wire26),
.tlbp_dl_typ_upfc(signal_wire27),
.tlbp_dl_vc_ctrl(signal_wire28),
.tlbp_dl_vcid_map(signal_wire29),
.tlbp_dl_vcid_upfc(signal_wire30),
.tx_st_data0(tx_st_data0),
.tx_st_data0_p1(tx_st_data0_p1),
.tx_st_eop0(tx_st_eop0),
.tx_st_eop0_p1(tx_st_eop0_p1),
.tx_st_err0(tx_st_err0),
.tx_st_sop0(tx_st_sop0),
.tx_st_sop0_p1(tx_st_sop0_p1),
.tx_st_valid0(tx_st_valid0),
.rx_st_mask1(signal_wire31),
.rx_st_ready1(signal_wire32),
.tx_st_data1(signal_wire33),
.tx_st_data1_p1(signal_wire34),
.tx_st_eop1(signal_wire35),
.tx_st_eop1_p1(signal_wire36),
.tx_st_err1(signal_wire37),
.tx_st_sop1(signal_wire38),
.tx_st_sop1_p1(signal_wire39),
.tx_st_valid1(signal_wire40),
.phystatus0_ext(phystatus0_ext),
.rxdata0_ext(rxdata0_ext),
.rxdatak0_ext(rxdatak0_ext),
.rxelecidle0_ext(rxelecidle0_ext),
.rxstatus0_ext(rxstatus0_ext),
.rxvalid0_ext(rxvalid0_ext),
.phystatus1_ext(signal_wire41),
.rxdata1_ext(signal_wire42),
.rxdatak1_ext(signal_wire43),
.rxelecidle1_ext(signal_wire44),
.rxstatus1_ext(signal_wire45),
.rxvalid1_ext(signal_wire46),
.phystatus2_ext(signal_wire47),
.rxdata2_ext(signal_wire48),
.rxdatak2_ext(signal_wire49),
.rxelecidle2_ext(signal_wire50),
.rxstatus2_ext(signal_wire51),
.rxvalid2_ext(signal_wire52),
.phystatus3_ext(signal_wire53),
.rxdata3_ext(signal_wire54),
.rxdatak3_ext(signal_wire55),
.rxelecidle3_ext(signal_wire56),
.rxstatus3_ext(signal_wire57),
.rxvalid3_ext(signal_wire58),
.phystatus4_ext(signal_wire59),
.rxdata4_ext(signal_wire60),
.rxdatak4_ext(signal_wire61),
.rxelecidle4_ext(signal_wire62),
.rxstatus4_ext(signal_wire63),
.rxvalid4_ext(signal_wire64),
.phystatus5_ext(signal_wire65),
.rxdata5_ext(signal_wire66),
.rxdatak5_ext(signal_wire67),
.rxelecidle5_ext(signal_wire68),
.rxstatus5_ext(signal_wire69),
.rxvalid5_ext(signal_wire70),
.phystatus6_ext(signal_wire71),
.rxdata6_ext(signal_wire72),
.rxdatak6_ext(signal_wire73),
.rxelecidle6_ext(signal_wire74),
.rxstatus6_ext(signal_wire75),
.rxvalid6_ext(signal_wire76),
.phystatus7_ext(signal_wire77),
.rxdata7_ext(signal_wire78),
.rxdatak7_ext(signal_wire79),
.rxelecidle7_ext(signal_wire80),
.rxstatus7_ext(signal_wire81),
.rxvalid7_ext(signal_wire82),
.CraIrq_o(CraIrq_o),
.CraReadData_o(CraReadData_o),
.CraWaitRequest_o(CraWaitRequest_o),
.RxmAddress_o(RxmAddress_o),
.RxmBurstCount_o(RxmBurstCount_o),
.RxmByteEnable_o(RxmByteEnable_o),
.RxmRead_o(RxmRead_o),
.RxmWriteData_o(RxmWriteData_o),
.RxmWrite_o(RxmWrite_o),
.TxsReadDataValid_o(TxsReadDataValid_o),
.TxsReadData_o(TxsReadData_o),
.TxsWaitRequest_o(TxsWaitRequest_o),
.app_int_ack(app_int_ack),
.app_msi_ack(app_msi_ack),
.avs_pcie_reconfig_readdata(avs_pcie_reconfig_readdata),
.avs_pcie_reconfig_readdatavalid(avs_pcie_reconfig_readdatavalid),
.avs_pcie_reconfig_waitrequest(avs_pcie_reconfig_waitrequest),
.core_clk_out(core_clk_out),
.derr_cor_ext_rcv0(derr_cor_ext_rcv0),
.derr_cor_ext_rpl(derr_cor_ext_rpl),
.derr_rpl(derr_rpl),
.dl_ltssm(dl_ltssm),
.dlup_exit(dlup_exit),
.eidle_infer_sel(eidle_infer_sel),
.ev_128ns(ev_128ns),
.ev_1us(ev_1us),
.hip_extraclkout(hip_extraclkout),
.hotrst_exit(hotrst_exit),
.int_status(int_status),
.l2_exit(l2_exit),
.lane_act(lane_act),
.lmi_ack(lmi_ack),
.lmi_dout(lmi_dout),
.npd_alloc_1cred_vc0(npd_alloc_1cred_vc0),
.npd_cred_vio_vc0(npd_cred_vio_vc0),
.nph_alloc_1cred_vc0(nph_alloc_1cred_vc0),
.nph_cred_vio_vc0(nph_cred_vio_vc0),
.pme_to_sr(pme_to_sr),
.r2c_err0(r2c_err0),
.rate_ext(rate_ext),
.rc_gxb_powerdown(rc_gxb_powerdown),
.rc_rx_analogreset(rc_rx_analogreset),
.rc_rx_digitalreset(rc_rx_digitalreset),
.rc_tx_digitalreset(rc_tx_digitalreset),
.reset_status(reset_status),
.rx_fifo_empty0(rx_fifo_empty0),
.rx_fifo_full0(rx_fifo_full0),
.rx_st_bardec0(rx_st_bardec0),
.rx_st_be0(rx_st_be0),
.rx_st_be0_p1(rx_st_be0_p1),
.rx_st_data0(rx_st_data0),
.rx_st_data0_p1(rx_st_data0_p1),
.rx_st_eop0(rx_st_eop0),
.rx_st_eop0_p1(rx_st_eop0_p1),
.rx_st_err0(rx_st_err0),
.rx_st_sop0(rx_st_sop0),
.rx_st_sop0_p1(rx_st_sop0_p1),
.rx_st_valid0(rx_st_valid0),
.serr_out(serr_out),
.suc_spd_neg(suc_spd_neg),
.swdn_wake(swdn_wake),
.swup_hotrst(swup_hotrst),
.test_out(test_out),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_ctl_wr(tl_cfg_ctl_wr),
.tl_cfg_sts(tl_cfg_sts),
.tl_cfg_sts_wr(tl_cfg_sts_wr),
.tlbp_dl_ack_phypm(),
.tlbp_dl_ack_requpfc(),
.tlbp_dl_ack_sndupfc(),
.tlbp_dl_current_deemp(),
.tlbp_dl_currentspeed(),
.tlbp_dl_dll_req(),
.tlbp_dl_err_dll(),
.tlbp_dl_errphy(),
.tlbp_dl_link_autobdw_status(),
.tlbp_dl_link_bdwmng_status(),
.tlbp_dl_rpbuf_emp(),
.tlbp_dl_rst_enter_comp_bit(),
.tlbp_dl_rst_tx_margin_field(),
.tlbp_dl_rx_typ_pm(),
.tlbp_dl_rx_valpm(),
.tlbp_dl_tx_ackpm(),
.tlbp_dl_up(),
.tlbp_dl_vc_status(),
.tlbp_link_up(),
.tx_cred0(tx_cred0),
.tx_deemph(tx_deemph),
.tx_fifo_empty0(tx_fifo_empty0),
.tx_fifo_full0(tx_fifo_full0),
.tx_fifo_rdptr0(tx_fifo_rdptr0),
.tx_fifo_wrptr0(tx_fifo_wrptr0),
.tx_margin(tx_margin),
.tx_st_ready0(tx_st_ready0),
.use_pcie_reconfig(use_pcie_reconfig),
.wake_oen(wake_oen),
.derr_cor_ext_rcv1(),
.npd_alloc_1cred_vc1(),
.npd_cred_vio_vc1(),
.nph_alloc_1cred_vc1(),
.nph_cred_vio_vc1(),
.r2c_err1(),
.rx_fifo_empty1(),
.rx_fifo_full1(),
.rx_st_bardec1(),
.rx_st_be1(),
.rx_st_be1_p1(),
.rx_st_data1(),
.rx_st_data1_p1(),
.rx_st_eop1(),
.rx_st_eop1_p1(),
.rx_st_err1(),
.rx_st_sop1(),
.rx_st_sop1_p1(),
.rx_st_valid1(),
.tx_cred1(),
.tx_fifo_empty1(),
.tx_fifo_full1(),
.tx_fifo_rdptr1(),
.tx_fifo_wrptr1(),
.tx_st_ready1(),
.powerdown0_ext(powerdown0_ext),
.rxpolarity0_ext(rxpolarity0_ext),
.txcompl0_ext(txcompl0_ext),
.txdata0_ext(txdata0_ext),
.txdatak0_ext(txdatak0_ext),
.txdetectrx0_ext(txdetectrx0_ext),
.txelecidle0_ext(txelecidle0_ext),
.powerdown1_ext(),
.rxpolarity1_ext(),
.txcompl1_ext(),
.txdata1_ext(),
.txdatak1_ext(),
.txdetectrx1_ext(),
.txelecidle1_ext(),
.powerdown2_ext(),
.rxpolarity2_ext(),
.txcompl2_ext(),
.txdata2_ext(),
.txdatak2_ext(),
.txdetectrx2_ext(),
.txelecidle2_ext(),
.powerdown3_ext(),
.rxpolarity3_ext(),
.txcompl3_ext(),
.txdata3_ext(),
.txdatak3_ext(),
.txdetectrx3_ext(),
.txelecidle3_ext(),
.powerdown4_ext(),
.rxpolarity4_ext(),
.txcompl4_ext(),
.txdata4_ext(),
.txdatak4_ext(),
.txdetectrx4_ext(),
.txelecidle4_ext(),
.powerdown5_ext(),
.rxpolarity5_ext(),
.txcompl5_ext(),
.txdata5_ext(),
.txdatak5_ext(),
.txdetectrx5_ext(),
.txelecidle5_ext(),
.powerdown6_ext(),
.rxpolarity6_ext(),
.txcompl6_ext(),
.txdata6_ext(),
.txdatak6_ext(),
.txdetectrx6_ext(),
.txelecidle6_ext(),
.powerdown7_ext(),
.rxpolarity7_ext(),
.txcompl7_ext(),
.txdata7_ext(),
.txdatak7_ext(),
.txdetectrx7_ext(),
.txelecidle7_ext());
defparam
altpcie_hip_pipen1b_inst.CB_PCIE_MODE = 0,
altpcie_hip_pipen1b_inst.CG_AVALON_S_ADDR_WIDTH = 25,
altpcie_hip_pipen1b_inst.CG_COMMON_CLOCK_MODE = 0,
altpcie_hip_pipen1b_inst.CG_IMPL_CRA_AV_SLAVE_PORT = 1,
altpcie_hip_pipen1b_inst.INTENDED_DEVICE_FAMILY = "Stratix IV",
altpcie_hip_pipen1b_inst.CB_A2P_ADDR_MAP_NUM_ENTRIES = 2,
altpcie_hip_pipen1b_inst.CB_A2P_ADDR_MAP_PASS_THRU_BITS = 24,
altpcie_hip_pipen1b_inst.CB_A2P_ADDR_MAP_IS_FIXED = 0,
altpcie_hip_pipen1b_inst.CB_A2P_ADDR_MAP_FIXED_TABLE = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000001,
altpcie_hip_pipen1b_inst.CB_P2A_AVALON_ADDR_B0 = 32'h00000000,
altpcie_hip_pipen1b_inst.CB_P2A_AVALON_ADDR_B1 = 32'h20000000,
altpcie_hip_pipen1b_inst.CB_P2A_AVALON_ADDR_B2 = 32'h80000000,
altpcie_hip_pipen1b_inst.CB_P2A_AVALON_ADDR_B3 = 32'h00000000,
altpcie_hip_pipen1b_inst.CB_P2A_AVALON_ADDR_B4 = 32'h00000000,
altpcie_hip_pipen1b_inst.CB_P2A_AVALON_ADDR_B5 = 32'h00000000,
altpcie_hip_pipen1b_inst.TL_SELECTION = 1,
altpcie_hip_pipen1b_inst.bypass_tl = "true",
altpcie_hip_pipen1b_inst.AST_LITE = 0,
altpcie_hip_pipen1b_inst.p_pcie_hip_type = "0",
altpcie_hip_pipen1b_inst.retry_buffer_last_active_address = "2047",
altpcie_hip_pipen1b_inst.advanced_errors = "false",
altpcie_hip_pipen1b_inst.bar0_io_space = "false",
altpcie_hip_pipen1b_inst.bar0_64bit_mem_space = "false",
altpcie_hip_pipen1b_inst.bar0_prefetchable = "false",
altpcie_hip_pipen1b_inst.bar0_size_mask = 28,
altpcie_hip_pipen1b_inst.bar1_io_space = "false",
altpcie_hip_pipen1b_inst.bar1_64bit_mem_space = "false",
altpcie_hip_pipen1b_inst.bar1_prefetchable = "false",
altpcie_hip_pipen1b_inst.bar1_size_mask = 28,
altpcie_hip_pipen1b_inst.bar2_io_space = "false",
altpcie_hip_pipen1b_inst.bar2_64bit_mem_space = "false",
altpcie_hip_pipen1b_inst.bar2_prefetchable = "false",
altpcie_hip_pipen1b_inst.bar2_size_mask = 19,
altpcie_hip_pipen1b_inst.enable_ecrc_check = "false",
altpcie_hip_pipen1b_inst.enable_ecrc_gen = "false",
altpcie_hip_pipen1b_inst.enable_l1_aspm = "false",
altpcie_hip_pipen1b_inst.l01_entry_latency = 31,
altpcie_hip_pipen1b_inst.pcie_mode = "SHARED_MODE",
altpcie_hip_pipen1b_inst.expansion_base_address_register = 0,
altpcie_hip_pipen1b_inst.extend_tag_field = "false",
altpcie_hip_pipen1b_inst.bypass_cdc = "false",
altpcie_hip_pipen1b_inst.vc_arbitration = 0,
altpcie_hip_pipen1b_inst.no_soft_reset = "false",
altpcie_hip_pipen1b_inst.enable_ch0_pclk_out = "true",
altpcie_hip_pipen1b_inst.core_clk_divider = 2,
altpcie_hip_pipen1b_inst.millisecond_cycle_count = 125000,
altpcie_hip_pipen1b_inst.single_rx_detect = 1,
altpcie_hip_pipen1b_inst.enable_coreclk_out_half_rate = "false",
altpcie_hip_pipen1b_inst.enable_gen2_core = "false",
altpcie_hip_pipen1b_inst.gen2_lane_rate_mode = "false",
altpcie_hip_pipen1b_inst.lane_mask = 8'b11111110,
altpcie_hip_pipen1b_inst.max_link_width = 1,
altpcie_hip_pipen1b_inst.vendor_id = 4466,
altpcie_hip_pipen1b_inst.device_id = 57345,
altpcie_hip_pipen1b_inst.revision_id = 1,
altpcie_hip_pipen1b_inst.class_code = 16711680,
altpcie_hip_pipen1b_inst.subsystem_vendor_id = 4466,
altpcie_hip_pipen1b_inst.subsystem_device_id = 10241,
altpcie_hip_pipen1b_inst.port_link_number = 1,
altpcie_hip_pipen1b_inst.vc_enable = 7'b0000000,
altpcie_hip_pipen1b_inst.vc1_clk_enable = "false",
altpcie_hip_pipen1b_inst.low_priority_vc = 0,
altpcie_hip_pipen1b_inst.max_payload_size = 1,
altpcie_hip_pipen1b_inst.msi_function_count = 2,
altpcie_hip_pipen1b_inst.endpoint_l0_latency = 0,
altpcie_hip_pipen1b_inst.endpoint_l1_latency = 0,
altpcie_hip_pipen1b_inst.diffclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.sameclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.l1_exit_latency_sameclock = 7,
altpcie_hip_pipen1b_inst.l1_exit_latency_diffclock = 7,
altpcie_hip_pipen1b_inst.l0_exit_latency_sameclock = 7,
altpcie_hip_pipen1b_inst.l0_exit_latency_diffclock = 7,
altpcie_hip_pipen1b_inst.enable_msi_64bit_addressing = "true",
altpcie_hip_pipen1b_inst.gen2_diffclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.gen2_sameclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.enable_function_msix_support = "false",
altpcie_hip_pipen1b_inst.credit_buffer_allocation_aux = "ABSOLUTE",
altpcie_hip_pipen1b_inst.eie_before_nfts_count = 4,
altpcie_hip_pipen1b_inst.enable_completion_timeout_disable = "false",
altpcie_hip_pipen1b_inst.completion_timeout = "NONE",
altpcie_hip_pipen1b_inst.enable_adapter_half_rate_mode = "false",
altpcie_hip_pipen1b_inst.msix_pba_bir = 0,
altpcie_hip_pipen1b_inst.msix_pba_offset = 0,
altpcie_hip_pipen1b_inst.msix_table_bir = 0,
altpcie_hip_pipen1b_inst.msix_table_offset = 0,
altpcie_hip_pipen1b_inst.msix_table_size = 0,
altpcie_hip_pipen1b_inst.use_crc_forwarding = "false",
altpcie_hip_pipen1b_inst.surprise_down_error_support = "false",
altpcie_hip_pipen1b_inst.dll_active_report_support = "false",
altpcie_hip_pipen1b_inst.bar_io_window_size = "32BIT",
altpcie_hip_pipen1b_inst.bar_prefetchable = 32,
altpcie_hip_pipen1b_inst.hot_plug_support = 7'b0000000,
altpcie_hip_pipen1b_inst.no_command_completed = "true",
altpcie_hip_pipen1b_inst.slot_power_limit = 0,
altpcie_hip_pipen1b_inst.slot_power_scale = 0,
altpcie_hip_pipen1b_inst.slot_number = 0,
altpcie_hip_pipen1b_inst.enable_slot_register = "false",
altpcie_hip_pipen1b_inst.vc0_rx_flow_ctrl_posted_header = 17,
altpcie_hip_pipen1b_inst.vc0_rx_flow_ctrl_posted_data = 91,
altpcie_hip_pipen1b_inst.vc0_rx_flow_ctrl_nonposted_header = 20,
altpcie_hip_pipen1b_inst.vc0_rx_flow_ctrl_nonposted_data = 0,
altpcie_hip_pipen1b_inst.vc0_rx_flow_ctrl_compl_header = 0,
altpcie_hip_pipen1b_inst.vc0_rx_flow_ctrl_compl_data = 0,
altpcie_hip_pipen1b_inst.RX_BUF = 9,
altpcie_hip_pipen1b_inst.RH_NUM = 7,
altpcie_hip_pipen1b_inst.G_TAG_NUM0 = 32;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_lfsr5.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_lfsr5
// Description:
// The IFQ is the icache input queue. This communicates between the
// IFU and the outside world. It handles icache misses and
// invalidate requests from the crossbar.
*/
////////////////////////////////////////////////////////////////////////
module sparc_ifu_lfsr5 (/*AUTOARG*/
// Outputs
out,
// Inputs
advance, clk, se, si, so, reset
);
input advance;
input clk, se, si, so, reset;
output [1:0] out;
reg [4:0] q_next;
wire [4:0] q;
/*
always @ (posedge clk)
begin
out = $random;
end // always @ posedge
*/
// always @ (posedge clk)
// begin
// q[4:0] <= q_next[4:0];
// end
always @ (/*AUTOSENSE*/advance or q or reset)
begin
if (reset)
q_next = 5'b11111;
else if (advance)
begin
// lfsr -- stable at 000000, period of 63
q_next[1] = q[0];
q_next[2] = q[1];
q_next[3] = q[2];
q_next[4] = q[3];
q_next[0] = q[1] ^ q[4];
end
else
q_next = q;
end // always @ (...
assign out = {q[0], q[2]};
dff_s #(5) lfsr_reg(.din (q_next),
.q (q),
.clk (clk), .se(se), .si(), .so());
endmodule // sparc_ifu_lfsr5
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: reading.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module reading (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/reading.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/reading.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// CPU
module cpu(
input clk_sys,
// from power supply (?)
input off,
input pon,
input pout,
input clm, clo,
// from control panel
input [0:15] kl,
input panel_store, panel_fetch, panel_load, panel_bin,
input oprq, stop, start, work, mode, step, stop_n, cycle,
input wre, rsa, rsb, rsc,
input wic, wac, war, wir, wrs, wrz, wkb,
input zegar,
// to control panel
output p0,
output [0:15] w,
output hlt_n,
output p,
output run,
output _wait,
output irq,
output q,
output mc_0,
output awaria,
// system bus
input rpa,
output dmcl,
// -OFF
output dw,
output dr,
output ds,
output df,
output din, input rin,
output dok, input rok,
input ren,
input rpe,
output dqb,
output dpn, input rpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt, input [0:15] rdt,
output zg,
input zw,
output zz
);
assign zz = 1'b1;
// --- CPU FEATURES-----------------------------------------------------
parameter CPU_NUMBER;
parameter AWP_PRESENT = 1'b1;
parameter INOU_USER_ILLEGAL = 1'b1;
parameter STOP_ON_NOMEM = 1'b1;
parameter LOW_MEM_WRITE_DENY = 1'b0;
// --- BUS TIMINGS -----------------------------------------------------
parameter ALARM_DLY_TICKS = 8'd250; // 2.5-5us in DTR, >=5us from notes on HSO schematic, ~10us in hw(?)
parameter ALARM_TICKS = 2'd3; // 60ns
// -DDT open-collector composition
assign ddt = pa_ddt | px_ddt;
// -DAD open-collector composition
assign dad = pa_dad | pp_dad | px_dad;
// -----------------------------------------------------------------------
// --- P-X ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire k1, wp, k2, wa, wz, w$, wr, we, p1, p2, p5, p4, p3, i5, i4, i3, i2, i1, ww, wm, wx, as2, got, strob1, strob1b, strob2, strob2b, arm4, blw_pw, ekc_i, zer_sp, lipsp, pn_nb, bp_nb, bar_nb, barnb, q_nb, w_dt, dt_w, ar_ad, ic_ad, i3_ex_przer, ck_rz_w, zerrz, ok$, oken, bod, b_parz, b_p0;
wire [0:15] px_dad;
wire [0:15] px_ddt;
wire ldstate;
px #(
.AWP_PRESENT(AWP_PRESENT),
.STOP_ON_NOMEM(STOP_ON_NOMEM),
.LOW_MEM_WRITE_DENY(LOW_MEM_WRITE_DENY),
.ALARM_DLY_TICKS(ALARM_DLY_TICKS),
.ALARM_TICKS(ALARM_TICKS)
) PX(
.clk_sys(clk_sys),
.ek1(ek1),
.ewp(ewp),
.ek2(ek2),
.ewa(ewa),
.clo(clo),
.ewe(ewe),
.ewr(ewr),
.ew$(ew$),
.ewz(ewz),
.k1(k1),
.wp(wp),
.k2(k2),
.wa(wa),
.wz(wz),
.w$(w$),
.wr(wr),
.we(we),
.sp1(sp1),
.ep1(ep1),
.sp0(sp0),
.ep0(ep0),
.stp0(stp0),
.ep2(ep2),
.ep5(ep5),
.ep4(ep4),
.ep3(ep3),
.p1(p1),
.p0(p0),
.p2(p2),
.p5(p5),
.p4(p4),
.p3(p3),
.si1(si1),
.ewx(ewx),
.ewm(ewm),
.eww(eww),
.i5(i5),
.i4(i4),
.i3(i3),
.i2(i2),
.i1(i1),
.ww(ww),
.wm(wm),
.wx(wx),
.laduj(laduj),
.as2_sum_at(as2),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.mode(mode),
.step(step),
.got(got),
.ldstate(ldstate),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.przerw_z(przerw_z),
.przerw(przerw),
.lip(lip),
.sp(sp),
.lg_0(lg_0),
.pp(pp),
.lg_3(lg_3),
.arm4(arm4),
.blw_pw(blw_pw),
.ekc_i(ekc_i),
.zer_sp(zer_sp),
.lipsp(lipsp),
.sbar$(sbar$),
.q(q),
.in(in),
.ou(ou),
.k2fetch(k2fetch),
.read_fp(read_fp),
.pn_nb(pn_nb),
.bp_nb(bp_nb),
.bar_nb(bar_nb),
.barnb(barnb),
.q_nb(q_nb),
.df(df),
.w_dt(w_dt),
.dr(dr),
.dt_w(dt_w),
.ar_ad(ar_ad),
.ds(ds),
.mcl(mcl),
.gi(gi),
.ir6(ir[6]),
.fi(fi),
.arz(arz),
.k2_bin_store(k2_bin_store),
.lrz(lrz),
.ic_ad(ic_ad),
.dmcl(dmcl),
.ddt(px_ddt),
.din(din),
.dw(dw),
.i3_ex_przer(i3_ex_przer),
.ck_rz_w(ck_rz_w),
.zerrz(zerrz),
.sr_fp(sr_fp),
.zw(zw),
.srez$(srez$),
.wzi(wzi),
.is(is),
.ren(ren),
.rok(rok),
.efp(efp),
.exl(exl),
.zg(zg),
.ok$(ok$),
.oken(oken),
.stop_n(stop_n),
.zga(zga),
.rpe(rpe),
.stop(stop),
.ir9(ir[9]),
.pufa(pufa),
.ir7(ir[7]),
.ir8(ir[8]),
.hlt_n(hlt_n),
.bod(bod),
.b_parz(b_parz),
.b_p0(b_p0),
.awaria(awaria),
.dad(px_dad)
);
// -----------------------------------------------------------------------
// --- P-M ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire sp0, przerw, si1, sp1, laduj, k2_bin_store, k2fetch, w_rbc, w_rba, w_rbb, ep0, stp0, ek2, ek1, mc_3, xi$, pp, ep5, ep4, ep3, ep1, ep2, icp1, arp1, lg_3, lg_0, rc, rb, ra, lk, wls, w_r, w_ic, w_ac, w_ar, lrz, w_bar, w_rm, baa, bab, bac, aa, ab, wpb, bwb, bwa, kia, kib, w_ir, mwa, mwb, mwc;
pm PM(
.clk_sys(clk_sys),
.start(start),
.pon(pon),
.work(work),
.hlt_n(hlt_n),
.stop(stop),
.clo(clo),
.hlt(hlt),
.cycle(cycle),
.irq(irq),
._wait(_wait),
.run(run),
.ekc_1(ekc_1),
.ekc_i(ekc_i),
.ekc_2(ekc_2),
.got(got),
.ldstate(ldstate),
.ekc_fp(ekc_fp),
.clm(clm),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.sp0(sp0),
.przerw(przerw),
.si1(si1),
.sp1(sp1),
.k2(k2),
.panel_store(panel_store),
.panel_fetch(panel_fetch),
.panel_load(panel_load),
.panel_bin(panel_bin),
.rdt9(rdt[9]),
.rdt11(rdt[11]),
.k1(k1),
.laduj(laduj),
.k2_bin_store(k2_bin_store),
.k2fetch(k2fetch),
.w_rbc(w_rbc),
.w_rba(w_rba),
.w_rbb(w_rbb),
.p0(p0),
.ep0(ep0),
.stp0(stp0),
.ek2(ek2),
.ek1(ek1),
.j$(j$),
.bcoc$(bcoc$),
.zs(zs),
.p2(p2),
.ssp$(ssp$),
.sc$(sc$),
.md(md),
.xi(xi),
.p(p),
.mc_3(mc_3),
.mc_0(mc_0),
.xi$(xi$),
.p4(p4),
.b0(b0),
.na(na),
.c0(c0),
.ka2(ka2),
.ka1(ka1),
.p3(p3),
.p1(p1),
.nef(nef),
.p5(p5),
.i2(i2),
.pp(pp),
.ep5(ep5),
.ep4(ep4),
.ep3(ep3),
.ep1(ep1),
.ep2(ep2),
.icp1(icp1),
.exl(exl),
.lipsp(lipsp),
.gr(gr),
.wx(wx),
.shc(shc),
.read_fp(read_fp),
.inou(inou),
.rok(rok),
.arp1(arp1),
.lg_3(lg_3),
.lg_0(lg_0),
.rsc(rsc),
.ir6(ir[6]),
.ir7(ir[7]),
.ir8(ir[8]),
.ir9(ir[9]),
.ir10(ir[10]),
.ir11(ir[11]),
.ir12(ir[12]),
.ir13(ir[13]),
.ir14(ir[14]),
.ir15(ir[15]),
.lpb(lpb),
.rsb(rsb),
.rsa(rsa),
.lpa(lpa),
.rlp_fp(rlp_fp),
.rc(rc),
.rb(rb),
.ra(ra),
.bod(bod),
.lk(lk),
.rj(rj),
.uj(uj),
.lwlwt(lwlwt),
.sr(sr),
.lac(lac),
.lrcb(lrcb),
.rpc(rpc),
.rc$(rc$),
.ng$(ng$),
.ls(ls),
.oc(oc),
.wa(wa),
.wm(wm),
.wz(wz),
.ww(ww),
.wr(wr),
.wp(wp),
.wls(wls),
.ri(ri),
.war(war),
.wre(wre),
.i3(i3),
.s_fp(s_fp),
.sar$(sar$),
.lar$(lar$),
.in(in),
.bs(bs),
.zb$(zb$),
.w_r(w_r),
.wic(wic),
.i4(i4),
.wac(wac),
.i1(i1),
.w_ic(w_ic),
.w_ac(w_ac),
.w_ar(w_ar),
.wrz(wrz),
.wrs(wrs),
.mb(mb),
.im(im),
.lj(lj),
.lwrs(lwrs),
.jkrb(jkrb),
.lrz(lrz),
.w_bar(w_bar),
.w_rm(w_rm),
.we(we),
.ib(ib),
.cb(cb),
.i5(i5),
.rb$(rb$),
.w$(w$),
.i3_ex_przer(i3_ex_przer),
.baa(baa),
.bab(bab),
.bac(bac),
.aa(aa),
.ab(ab),
.at15(at15),
.srez$(srez$),
.rz(rz),
.wir(wir),
.blw_pw(blw_pw),
.wpb(wpb),
.bwb(bwb),
.bwa(bwa),
.kia(kia),
.kib(kib),
.w_ir(w_ir),
.ki(ki),
.dt_w(dt_w),
.f13(f13),
.wkb(wkb),
.mwa(mwa),
.mwb(mwb),
.mwc(mwc)
);
// -----------------------------------------------------------------------
// --- P-D ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire [0:15] ir;
wire c0, ls, rj, bs, ou, in, is, ri, pufa, rb$, cb, sc$, oc, ka2, gr, hlt, mcl, sin, gi, lip, mb, im, ki, fi, sp, rz, ib, lpc, rpc, shc, rc$, ng$, zb$, b0, _0_v, md, xi, nef, amb, apb, jkrb, lwrs, saryt, ap1, am1, bcoc$, sd, scb, sca, sb, sab, saa, lrcb, aryt, sbar$, nrf, ust_z, ust_v, ust_mc, ust_leg, eat0, sr, ust_y, ust_x, blr, ewa, ewp, uj, lwlwt, lj, ewe, ekc_1, ewz, ew$, lar$, ssp$, ka1, na, exl, p16, ewr, ewm, efp, sar$, eww, srez$, ewx, axy, inou, ekc_2, lac;
pd #(
.INOU_USER_ILLEGAL(INOU_USER_ILLEGAL)
) PD(
.clk_sys(clk_sys),
.w(w),
.strob1(strob1),
.strob1b(strob1b),
.w_ir(w_ir),
.ir(ir),
.c0(c0),
.si1(si1),
.ls(ls),
.rj(rj),
.bs(bs),
.ou(ou),
.in(in),
.is(is),
.ri(ri),
.pufa(pufa),
.rb$(rb$),
.cb(cb),
.sc$(sc$),
.oc(oc),
.ka2(ka2),
.gr(gr),
.hlt(hlt),
.mcl(mcl),
.sin(sin),
.gi(gi),
.lip(lip),
.mb(mb),
.im(im),
.ki(ki),
.fi(fi),
.sp(sp),
.rz(rz),
.ib(ib),
.lpc(lpc),
.rpc(rpc),
.shc(shc),
.rc$(rc$),
.ng$(ng$),
.zb$(zb$),
.b0(b0),
.q(q),
.mc_3(mc_3),
.r0(r0),
._0_v(_0_v),
.p(p),
.md(md),
.xi(xi),
.nef(nef),
.w$(w$),
.p4(p4),
.we(we),
.amb(amb),
.apb(apb),
.jkrb(jkrb),
.lwrs(lwrs),
.saryt(saryt),
.ap1(ap1),
.am1(am1),
.wz(wz),
.wls(wls),
.bcoc$(bcoc$),
.sd(sd),
.scb(scb),
.sca(sca),
.sb(sb),
.sab(sab),
.saa(saa),
.lrcb(lrcb),
.aryt(aryt),
.sbar$(sbar$),
.nrf(nrf),
.at15(at15),
.wx(wx),
.wa(wa),
.ust_z(ust_z),
.ust_v(ust_v),
.ust_mc(ust_mc),
.ust_leg(ust_leg),
.eat0(eat0),
.sr(sr),
.ust_y(ust_y),
.ust_x(ust_x),
.blr(blr),
.wpb(wpb),
.wr(wr),
.pp(pp),
.ww(ww),
.wzi(wzi),
.ewa(ewa),
.ewp(ewp),
.uj(uj),
.lwlwt(lwlwt),
.lj(lj),
.ewe(ewe),
.wp(wp),
.ekc_1(ekc_1),
.ewz(ewz),
.ew$(ew$),
.lar$(lar$),
.ssp$(ssp$),
.ka1(ka1),
.na(na),
.exl(exl),
.p16(p16),
.lk(lk),
.wm(wm),
.ewr(ewr),
.ewm(ewm),
.efp(efp),
.sar$(sar$),
.eww(eww),
.srez$(srez$),
.ewx(ewx),
.axy(axy),
.inou(inou),
.ekc_2(ekc_2),
.lac(lac)
);
// -----------------------------------------------------------------------
// --- P-R ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire [0:15] l;
wire zgpn, zer;
wire [0:8] r0;
wire [0:15] bus_ki;
pr #(
.CPU_NUMBER(CPU_NUMBER),
.AWP_PRESENT(AWP_PRESENT)
) PR(
.clk_sys(clk_sys),
.blr(blr),
.lpc(lpc),
.wa(wa),
.rpc(rpc),
.rc(rc),
.rb(rb),
.ra(ra),
.as2(as2),
.w_r(w_r),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.w(w),
.l(l),
.bar_nb(bar_nb),
.w_rbb(w_rbb),
.w_rbc(w_rbc),
.w_rba(w_rba),
.dnb(dnb),
.rpn(rpn),
.bp_nb(bp_nb),
.pn_nb(pn_nb),
.q_nb(q_nb),
.w_bar(w_bar),
.zer_sp(zer_sp),
.clm(clm),
.ustr0_fp(ustr0_fp),
.ust_leg(ust_leg),
.aryt(aryt),
.zs(zs),
.carry(carry),
.s_1(s_1),
.zgpn(zgpn),
.dpn(dpn),
.dqb(dqb),
.q(q),
.zer(zer),
.ust_z(ust_z),
.ust_mc(ust_mc),
.s0(s0),
.ust_v(ust_v),
._0_v(_0_v),
.r0(r0),
.exy(exy),
.ust_y(ust_y),
.exx(exx),
.ust_x(ust_x),
.kia(kia),
.kib(kib),
.bus_rz(bus_rz),
.zp(zp),
.rs(rs),
.bus_ki(bus_ki)
);
// -----------------------------------------------------------------------
// --- P-P ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire [0:9] rs;
wire [0:15] bus_rz;
wire przerw_z;
wire [0:15] pp_dad;
pp PP(
.clk_sys(clk_sys),
.w(w),
.clm(clm),
.w_rm(w_rm),
.strob1(strob1),
.strob1b(strob1b),
.i4(i4),
.rs(rs),
.pout(pout),
.zer(zer),
.b_parz(b_parz),
.ck_rz_w(ck_rz_w),
.b_p0(b_p0),
.zerrz(zerrz),
.i1(i1),
.przerw(przerw),
.bus_rz(bus_rz),
.rpa(rpa),
.zegar(zegar),
.xi(xi$),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.przerw_z(przerw_z),
.k1(k1),
.i2(i2),
.oprq(oprq),
.ir14(ir[14]),
.ir15(ir[15]),
.wx(wx),
.sin(sin),
.rin(rin),
.zw(zw),
.zgpn(zgpn),
.rdt(rdt),
.dok(dok),
.irq(irq),
.dad(pp_dad)
);
// -----------------------------------------------------------------------
// --- P-A ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire s0, carry, j$, exx, at15, exy, s_1, wzi, zs, arz;
wire zga;
wire [0:15] pa_ddt;
wire [0:15] pa_dad;
pa PA(
.clk_sys(clk_sys),
.ir(ir),
.bus_ki(bus_ki),
.rdt(rdt),
.w_dt(w_dt),
.mwa(mwa),
.mwb(mwb),
.mwc(mwc),
.bwa(bwa),
.bwb(bwb),
.ddt(pa_ddt),
.w(w),
.saryt(saryt),
.sab(sab),
.scb(scb),
.sb(sb),
.sd(sd),
.s0(s0),
.carry(carry),
.p16(p16),
.saa(saa),
.sca(sca),
.j$(j$),
.exx(exx),
.wx(wx),
.eat0(eat0),
.axy(axy),
.at15(at15),
.exy(exy),
.w_ac(w_ac),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.as2(as2),
.am1(am1),
.apb(apb),
.amb(amb),
.ap1(ap1),
.s_1(s_1),
.wzi(wzi),
.zs(zs),
.arm4(arm4),
.w_ar(w_ar),
.arp1(arp1),
.arz(arz),
.icp1(icp1),
.w_ic(w_ic),
.off(off),
.baa(baa),
.bab(bab),
.bac(bac),
.ab(ab),
.aa(aa),
.l(l),
.barnb(barnb),
.kl(kl),
.ic_ad(ic_ad),
.dad(pa_dad),
.ar_ad(ar_ad),
.zga(zga)
);
// -----------------------------------------------------------------------
// --- AWP ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire fi0, fi1, fi2, fi3;
wire read_fp, strob_fp, strobb_fp, sr_fp, ekc_fp, rlp_fp, ustr0_fp, s_fp;
wire f13, lpa, lpb;
wire [0:15] zp;
generate
if (~AWP_PRESENT) begin
assign {fi0, fi1, fi2, fi3} = 4'b0000;
assign {read_fp, strob_fp, sr_fp, ekc_fp, rlp_fp, ustr0_fp, s_fp} = 7'b0000000;
assign {f13, lpa, lpb} = 3'b000;
assign zp = 16'h0000;
end else begin
awp AWP(
.clk_sys(clk_sys),
.w(w),
.r02(r0[2]),
.r03(r0[3]),
.pufa(pufa),
.ir(ir[7:9]),
.nrf(nrf),
.mode(mode),
.step(step),
.efp(efp),
.got(got),
.ldstate(ldstate),
.ok$(ok$),
.oken(oken),
.zw(zw),
.zp(zp),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.rlp_fp(rlp_fp),
.lpa(lpa),
.lpb(lpb),
.s_fp(s_fp),
.ustr0_fp(ustr0_fp),
.f13(f13),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.sr_fp(sr_fp),
.read_fp(read_fp),
.ekc_fp(ekc_fp)
);
end
endgenerate
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:00:48 02/27/2014
// Design Name:
// Module Name: clk_div
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_div(
clk,
rst,
SW2,
clkdiv,
Clk_CPU
);
input wire clk,
rst;
input wire SW2;
output reg [31: 0] clkdiv = 0;
output wire Clk_CPU;
always @ (posedge clk or posedge rst) begin
if (rst) begin
clkdiv <= 0;
end
else begin
clkdiv <= clkdiv + 32'b1;
end
end
assign Clk_CPU = SW2 ? clkdiv[24] : clkdiv[1]; // SW2 to chose Cpuclk
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_TB_V
`define SKY130_FD_SC_MS__NAND4BB_TB_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ms__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Hasan Hassan
//
// Create Date: 08/24/2015 05:49:13 PM
// Design Name:
// Module Name: SHD_PE
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SHD_PE #(parameter DNA_DATA_WIDTH = 128) (
input clk,
input rst,
//Scheduler Interface
input[DNA_DATA_WIDTH - 1:0] dna_in,
input[DNA_DATA_WIDTH - 1:0] dna_ref_in,
input dna_valid_in,
output dna_rd_en,
//Collector Interface
input coll_clk,
input coll_rd_en,
output[7:0] coll_dna_err,
output coll_valid
);
//Register Input
reg[DNA_DATA_WIDTH - 1:0] dna_r, dna_ref_r;
reg dna_valid_r;
always@(posedge clk) begin
if(rst) begin
dna_valid_r <= 1'b0;
dna_r <= 0;
dna_ref_r <= 0;
end
else begin
if(~dna_valid_r || ~pe_fifo_full) begin
dna_valid_r <= dna_valid_in;
dna_r <= dna_in;
dna_ref_r <= dna_ref_in;
end
end
end
wire[7:0] dna_err;
SHD #(.LENGTH(DNA_DATA_WIDTH)) i_SHD(
.DNA_read(dna_r),
.DNA_ref(dna_ref_r),
.DNA_MinErrors(dna_err)
);
wire pe_fifo_full, pe_fifo_empty;
shd_pe_fifo i_pe_fifo (
.wr_clk(clk), // input wire wr_clk
.rd_clk(coll_clk),
.rst(rst), // input wire srst
.din(dna_err), // input wire [7 : 0] din
.wr_en(~pe_fifo_full && dna_valid_r), // input wire wr_en
.rd_en(coll_rd_en), // input wire rd_en
.dout(coll_dna_err), // output wire [7 : 0] dout
.full(pe_fifo_full), // output wire full
.empty(pe_fifo_empty) // output wire empty
);
assign dna_rd_en = ~pe_fifo_full;
assign coll_valid = ~pe_fifo_empty;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_TB_V
`define SKY130_FD_SC_HDLL__NOR2_TB_V
/**
* nor2: 2-input NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_TB_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_alu_result,
E_mem_byte_en,
E_st_data,
E_valid,
F_pcb,
F_valid,
R_ctrl_exception,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_bstatus_reg,
W_cmp_result,
W_estatus_reg,
W_ienable_reg,
W_ipending_reg,
W_mem_baddr,
W_rf_wr_data,
W_status_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write_nxt,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
d_write,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output d_write;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input [ 31: 0] E_alu_result;
input [ 3: 0] E_mem_byte_en;
input [ 31: 0] E_st_data;
input E_valid;
input [ 16: 0] F_pcb;
input F_valid;
input R_ctrl_exception;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_bstatus_reg;
input W_cmp_result;
input W_estatus_reg;
input [ 31: 0] W_ienable_reg;
input [ 31: 0] W_ipending_reg;
input [ 18: 0] W_mem_baddr;
input [ 31: 0] W_rf_wr_data;
input W_status_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 18: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write_nxt;
input [ 16: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
reg d_write;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (W_valid)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns / 1ps
module VGA_ctrl
(
input clk,
input [2:0] d_in,
output [2:0] rgb,
output Hs,
output Vs,
input VGA_en,
// For debug purposes
output[9:0] H_count,
output[9:0] V_count,
output clk_25,
output D_En
);
wire[9:0] H_cnt;
wire[9:0] V_cnt;
wire V_cnt_en;
// reg H_cnt_en = 1;
reg H_sync_next = 0;
reg H_sync_reg = 0;
reg V_sync_next = 0;
reg V_sync_reg = 0;
reg H_DEN_next = 0;
reg H_DEN_reg = 0;
reg V_DEN_next = 0;
reg V_DEN_reg = 0;
reg[9:0] H_disp = 0;
reg[9:0] V_disp = 0;
// Instantiate the module
clock_div clock_div_25 (
.CLKIN_IN(clk),
.CLKDV_OUT(clk_25),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
counter#(.CNT_MAX(800), .DATA_WIDTH(10))
H_counter
(
.clk (clk_25),
.en_in (VGA_en),
.cnt (H_cnt),
.en_out (V_cnt_en)
);
counter#(.CNT_MAX(521), .DATA_WIDTH(10))
V_counter
(
.clk (clk_25),
.en_in (V_cnt_en),
.cnt (V_cnt),
.en_out ()
);
// sync part for H and V sync signals
always @(posedge clk_25) begin
H_sync_reg <= H_sync_next;
V_sync_reg <= V_sync_next;
H_DEN_reg <= H_DEN_next;
V_DEN_reg <= V_DEN_next;
end
// Combinatoric part H sync pulse
always @* begin
if (H_cnt < 95) begin
H_sync_next <= 0;
H_DEN_next <= 0;
end else if ((H_cnt > 142) & (H_cnt < 783)) begin // random values
H_sync_next <= 1;
H_DEN_next <= 1;
end else if (H_cnt == 799) begin
H_sync_next <= 0;
H_DEN_next <= 0;
end else begin
H_sync_next <= 1;
H_DEN_next <= 0;
end
end
// Combinatoric part V sync pulse
always @* begin
if (V_cnt < 2) begin
V_sync_next <= 0;
V_DEN_next <= 0;
end else if ((V_cnt > 30) & (V_cnt < 510)) begin // random values
V_sync_next <= 1;
V_DEN_next <= 1;
end else begin
V_sync_next <= 1;
V_DEN_next <= 0;
end
end
always @* begin
if ((V_DEN_reg) & (H_DEN_reg)) begin
H_disp <= H_cnt - 144;
V_disp <= V_cnt - 31;
end else begin
H_disp <= 0;
V_disp <= 0;
end
end
// Output logic
assign rgb = ((V_DEN_reg) & (H_DEN_reg)) ? d_in : 0;
assign D_En = ((V_DEN_reg) & (H_DEN_reg));
assign Hs = H_sync_reg;
assign Vs = V_sync_reg;
assign H_count = H_disp;
assign V_count = V_disp;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_datamux(datain, sel, dataout);
parameter DATA_WIDTH = 8;
parameter SELECT_WIDTH = 1;
parameter NUMBER_OF_CHANNELS = 2;
input [NUMBER_OF_CHANNELS * DATA_WIDTH - 1 : 0] datain;
input [SELECT_WIDTH - 1 : 0] sel;
output [DATA_WIDTH - 1 : 0] dataout;
wire [DATA_WIDTH - 1 : 0] vectorized_data [0 : NUMBER_OF_CHANNELS - 1];
assign dataout = vectorized_data[sel];
genvar c;
generate
for(c = 0 ; c < NUMBER_OF_CHANNELS ; c = c + 1)
begin : channel_iterator
assign vectorized_data[c] = datain[(c + 1) * DATA_WIDTH - 1 : c * DATA_WIDTH];
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@datain NUMBER_OF_CHANNELS == 2**SELECT_WIDTH) else
$error("%t, [DATAMUX ASSERT] NUMBER_OF_CHANNELS PARAMETER is incorrect, NUMBER_OF_CHANNELS = %d, 2**SELECT_WIDTH = %d", $time, NUMBER_OF_CHANNELS, 2**SELECT_WIDTH);
`endif
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
// system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.v
// Design : system_ov7670_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
sioc,
resend,
clk);
output config_finished;
output siod;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire taken;
system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
endmodule
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_0_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod));
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_1_V
`define SKY130_FD_SC_LP__OR4B_1_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_1 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_1 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_SYMBOL_V
`define SKY130_FD_SC_HDLL__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V |
// Ken Eguro
// Alpha version - 2/11/09
// Version 1.0 - 1/4/10
// Version 1.0.1 - 5/7/10
// Version 1.1 - 8/1/11
`timescale 1ns / 1ps
`default_nettype none
module iobuf16(IO, I, O, T);
inout wire [15:0] IO;
input wire [15:0] I;
output wire [15:0] O;
input wire T;
IOBUF IOBUF_B0(.IO(IO[0]), .I(I[0]), .O(O[0]), .T(T));
IOBUF IOBUF_B1(.IO(IO[1]), .I(I[1]), .O(O[1]), .T(T));
IOBUF IOBUF_B2(.IO(IO[2]), .I(I[2]), .O(O[2]), .T(T));
IOBUF IOBUF_B3(.IO(IO[3]), .I(I[3]), .O(O[3]), .T(T));
IOBUF IOBUF_B4(.IO(IO[4]), .I(I[4]), .O(O[4]), .T(T));
IOBUF IOBUF_B5(.IO(IO[5]), .I(I[5]), .O(O[5]), .T(T));
IOBUF IOBUF_B6(.IO(IO[6]), .I(I[6]), .O(O[6]), .T(T));
IOBUF IOBUF_B7(.IO(IO[7]), .I(I[7]), .O(O[7]), .T(T));
IOBUF IOBUF_B8(.IO(IO[8]), .I(I[8]), .O(O[8]), .T(T));
IOBUF IOBUF_B9(.IO(IO[9]), .I(I[9]), .O(O[9]), .T(T));
IOBUF IOBUF_B10(.IO(IO[10]), .I(I[10]), .O(O[10]), .T(T));
IOBUF IOBUF_B11(.IO(IO[11]), .I(I[11]), .O(O[11]), .T(T));
IOBUF IOBUF_B12(.IO(IO[12]), .I(I[12]), .O(O[12]), .T(T));
IOBUF IOBUF_B13(.IO(IO[13]), .I(I[13]), .O(O[13]), .T(T));
IOBUF IOBUF_B14(.IO(IO[14]), .I(I[14]), .O(O[14]), .T(T));
IOBUF IOBUF_B15(.IO(IO[15]), .I(I[15]), .O(O[15]), .T(T));
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module soc_system_hps_only_master_b2p_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input [ 7: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket
);
reg out_channel;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = in_channel ;
// Suppress channels that are higher than the destination's max_channel.
if (in_channel > 0) begin
out_valid = 0;
// Simulation Message goes here.
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_TB_V
`define SKY130_FD_SC_HS__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hs__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_TB_V
|
module booth(x,y,p);
input [7:0] x,y;
output [15:0] p;
wire [7:0] i,j,k,l,n,o,q,r;
wire [9:0] sp,tp,fop;
wire [7:0] fp;
wire [3:0] one,two,sign;
wire [10:0] c1,c2;
wire [8:0] ip1,ip2;
wire [9:0] c3;
wire [11:0] m;
wire [3:0] cry,z;
// carry generation
// 1st
xor n9(z[0],one[0],two[0]);
and n10(cry[0],z[0],sign[0]);
//2nd
xor n13(z[1],one[1],two[1]);
and n14(cry[1],z[1],sign[1]);
//3rd
xor n15(z[2],one[2],two[2]);
and n16(cry[2],z[2],sign[2]);
//4th
xor n17(z[3],one[3],two[3]);
and n18(cry[3],z[3],sign[3]);
code e1(one[0],two[0],sign[0],y[1],y[0],1'b0);
code e2(one[1],two[1],sign[1],y[3],y[2],y[1]);
code e3(one[2],two[2],sign[2],y[5],y[4],y[3]);
code e4(one[3],two[3],sign[3],y[7],y[6],y[5]);
//first product generation
product p0(x[0],sign[0],cry[0],one[0],two[0],sign[0],p[0],i[0],n[0]);
product p1(x[1],i[0],n[0],one[0],two[0],sign[0],p[1],i[1],n[1]);
product p2(x[2],i[1],n[1],one[0],two[0],sign[0],fp[0],i[2],n[2]);
product p3(x[3],i[2],n[2],one[0],two[0],sign[0],fp[1],i[3],n[3]);
product p4(x[4],i[3],n[3],one[0],two[0],sign[0],fp[2],i[4],n[4]);
product p5(x[5],i[4],n[4],one[0],two[0],sign[0],fp[3],i[5],n[5]);
product p6(x[6],i[5],n[5],one[0],two[0],sign[0],fp[4],i[6],n[6]);
product p7(x[7],i[6],n[6],one[0],two[0],sign[0],fp[5],i[7],n[7]);
xor x1(m[0],i[7],n[7]);
and a1(m[1],two[0],i[7]);
and a2(m[2],one[0],m[0]);
or o1(fp[6],m[1],m[2]);
not n1(fp[7],fp[6]);
//second product generation
product q0(x[0],sign[1],cry[1],one[1],two[1],sign[1],sp[0],j[0],o[0]);
product q1(x[1],j[0],o[0],one[1],two[1],sign[1],sp[1],j[1],o[1]);
product q2(x[2],j[1],o[1],one[1],two[1],sign[1],sp[2],j[2],o[2]);
product q3(x[3],j[2],o[2],one[1],two[1],sign[1],sp[3],j[3],o[3]);
product q4(x[4],j[3],o[3],one[1],two[1],sign[1],sp[4],j[4],o[4]);
product q5(x[5],j[4],o[4],one[1],two[1],sign[1],sp[5],j[5],o[5]);
product q6(x[6],j[5],o[5],one[1],two[1],sign[1],sp[6],j[6],o[6]);
product q7(x[7],j[6],o[6],one[1],two[1],sign[1],sp[7],j[7],o[7]);
xor x2(m[3],j[7],o[7]);
and a3(m[4],two[1],j[7]);
and a4(m[5],one[1],m[3]);
or o2(sp[8],m[4],m[5]);
not n2(sp[9],sp[8]);
//third product
product r0(x[0],sign[2],cry[2],one[2],two[2],sign[2],tp[0],k[0],q[0]);
product r1(x[1],k[0],q[0],one[2],two[2],sign[2],tp[1],k[1],q[1]);
product r2(x[2],k[1],q[1],one[2],two[2],sign[2],tp[2],k[2],q[2]);
product r3(x[3],k[2],q[2],one[2],two[2],sign[2],tp[3],k[3],q[3]);
product r4(x[4],k[3],q[3],one[2],two[2],sign[2],tp[4],k[4],q[4]);
product r5(x[5],k[4],q[4],one[2],two[2],sign[2],tp[5],k[5],q[5]);
product r6(x[6],k[5],q[5],one[2],two[2],sign[2],tp[6],k[6],q[6]);
product r7(x[7],k[6],q[6],one[2],two[2],sign[2],tp[7],k[7],q[7]);
xor x3(m[6],k[7],q[7]);
and a5(m[7],two[2],k[7]);
and a6(m[8],one[2],m[6]);
or o3(tp[8],m[7],m[8]);
not n3(tp[9],tp[8]);
//fourth product
product s0(x[0],sign[3],cry[3],one[3],two[3],sign[3],fop[0],l[0],r[0]);
product s1(x[1],l[0],r[0],one[3],two[3],sign[3],fop[1],l[1],r[1]);
product s2(x[2],l[1],r[1],one[3],two[3],sign[3],fop[2],l[2],r[2]);
product s3(x[3],l[2],r[2],one[3],two[3],sign[3],fop[3],l[3],r[3]);
product s4(x[4],l[3],r[3],one[3],two[3],sign[3],fop[4],l[4],r[4]);
product s5(x[5],l[4],r[4],one[3],two[3],sign[3],fop[5],l[5],r[5]);
product s6(x[6],l[5],r[5],one[3],two[3],sign[3],fop[6],l[6],r[6]);
product s7(x[7],l[6],r[6],one[3],two[3],sign[3],fop[7],l[7],r[7]);
xor x4(m[9],l[7],r[7]);
and a7(m[10],two[3],l[7]);
and a8(m[11],one[3],m[9]);
or o4(fop[8],m[10],m[11]);
not n4(fop[9],fop[8]);
//1st add
HAd fa1(sp[0],fp[0],c1[0],p[2]);
FAd fa2(sp[1],fp[1],c1[0],c1[1],p[3]);
FAd fa3(sp[2],fp[2],c1[1],c1[2],ip1[0]);
FAd fa4(sp[3],fp[3],c1[2],c1[3],ip1[1]);
FAd fa5(sp[4],fp[4],c1[3],c1[4],ip1[2]);
FAd fa6(sp[5],fp[5],c1[4],c1[5],ip1[3]);
FAd fa7(sp[6],fp[6],c1[5],c1[6],ip1[4]);
FAd fa8(sp[7],fp[6],c1[6],c1[7],ip1[5]);
FAd fa9(sp[8],fp[6],c1[7],c1[8],ip1[6]);
FAd fa10(sp[9],fp[7],c1[8],c1[9],ip1[7]);
HAd fa11(c1[9],1'b1,c1[10],ip1[8]);
//2rd add
HAd sa1(tp[0],ip1[0],c2[0],p[4]);
FAd sa2(tp[1],ip1[1],c2[0],c2[1],p[5]);
FAd sa3(tp[2],ip1[2],c2[1],c2[2],ip2[0]);
FAd sa4(tp[3],ip1[3],c2[2],c2[3],ip2[1]);
FAd sa5(tp[4],ip1[4],c2[3],c2[4],ip2[2]);
FAd sa6(tp[5],ip1[5],c2[4],c2[5],ip2[3]);
FAd sa7(tp[6],ip1[6],c2[5],c2[6],ip2[4]);
FAd sa8(tp[7],ip1[7],c2[6],c2[7],ip2[5]);
FAd sa9(tp[8],ip1[8],c2[7],c2[8],ip2[6]);
FAd sa10(tp[9],c1[10],c2[8],c2[9],ip2[7]);
HAd sa11(c2[9],1'b1,c2[10],ip2[8]);
//3th add
HAd foa1(fop[0],ip2[0],c3[0],p[6]);
FAd foa2(fop[1],ip2[1],c3[0],c3[1],p[7]);
FAd foa3(fop[2],ip2[2],c3[1],c3[2],p[8]);
FAd foa4(fop[3],ip2[3],c3[2],c3[3],p[9]);
FAd foa5(fop[4],ip2[4],c3[3],c3[4],p[10]);
FAd foa6(fop[5],ip2[5],c3[4],c3[5],p[11]);
FAd foa7(fop[6],ip2[6],c3[5],c3[6],p[12]);
FAd foa8(fop[7],ip2[7],c3[6],c3[7],p[13]);
FAd foa9(fop[8],ip2[8],c3[7],c3[8],p[14]);
FAd foa10(fop[9],c2[10],c3[8],c3[9],p[15]);
endmodule
// generation of codes
module code(one,two,sign,y2,y1,y0);
input y2,y1,y0;
output one,two,sign;
wire [1:0]k;
xor x1(one,y0,y1);
xor x2(k[1],y2,y1);
not n1(k[0],one);
and a1(two,k[0],k[1]);
assign sign=y2;
endmodule
//generation of inner products
module product(x1,x0,x2,one,two,sign,p,i,ca);
input x1,x0,x2,sign,one,two;
output p,i,ca;
wire [2:0] k;
xor xo1(i,x1,sign);
and a1(k[1],i,one);
and a0(k[0],x0,two);
or o0(k[2],k[1],k[0]);
xor xo2(p,k[2],x2);
and a2(ca,k[2],x2);
endmodule
//adders design
module HAd(a,b,c,s);
input a,b;
output c,s;
xor x1(s,a,b);
and a1(c,a,b);
endmodule
module FAd(a,b,c,cy,sm);
input a,b,c;
output cy,sm;
wire x,y,z;
HAd h1(a,b,x,z);
HAd h2(z,c,y,sm);
or o1(cy,x,y);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_SYMBOL_V
/**
* udp_dlatch$PR_pp$PKG$s: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_SYMBOL_V
|
// megafunction wizard: %Altera PLL v14.0%
// GENERATION: XML
// audio_clock.v
// Generated using ACDS version 14.0 200 at 2018.06.09.21:23:33
`timescale 1 ps / 1 ps
module audio_clock (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
audio_clock_0002 audio_clock_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="14.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="8" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="12.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="3.072" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="1.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : audio_clock.vo
// RELATED_FILES: audio_clock.v, audio_clock_0002.v
|
module stopwatch
(
input wire clk,
input wire rst_n,
input wire [1:0] btn_n,
output wire [7:0] HEX0,
output wire [7:0] HEX1,
output wire [7:0] HEX2,
output wire [7:0] HEX3
);
wire start_b;
wire stop_b;
wire en100hz;
wire clr;
wire en;
wire [3:0] msecqh;
wire [3:0] msecql;
wire [3:0] secqh;
wire [3:0] secql;
wire ca10msec;
wire ca100msec;
wire ca1sec;
chattering _chattering_start_b
(
.rst_n(rst_n),
.clk(clk),
.bin_n(btn_n[0]),
.bout(start_b)
);
chattering _chattering_stop_b
(
.rst_n(rst_n),
.clk(clk),
.bin_n(btn_n[1]),
.bout(stop_b)
);
divider _divider
(
.rst_n(rst_n),
.clk(clk),
.en100hz(en100hz)
);
control _control
(
.rst_n(rst_n),
.clk(clk),
.start_b(start_b),
.stop_b(stop_b),
.en(en),
.clr(clr)
);
cnt10 _10msec
(
.rst_n(rst_n),
.clk(en100hz),
.en(en),
.clr(clr),
.q(msecql),
.ca(ca10msec)
);
cnt10 _100msec
(
.rst_n(rst_n),
.clk(en100hz),
.en(ca10msec),
.clr(clr),
.q(msecqh),
.ca(ca100msec)
);
cnt10 _1sec
(
.rst_n(rst_n),
.clk(en100hz),
.en(ca100msec),
.clr(clr),
.q(secql),
.ca(ca1sec)
);
cnt10 _10sec
(
.rst_n(rst_n),
.clk(en100hz),
.en(ca1sec),
.clr(clr),
.q(secqh)
);
seg7dec H0
(
.din(msecql),
.HEX(HEX0[7:1])
);
seg7dec H1
(
.din(msecqh),
.HEX(HEX1[7:1])
);
seg7dec H2
(
.din(secql),
.HEX(HEX2[7:1])
);
seg7dec H3
(
.din(secqh),
.HEX(HEX3[7:1])
);
assign HEX0[0] = 1'b0;
assign HEX1[0] = 1'b0;
assign HEX2[0] = 1'b1;
assign HEX3[0] = 1'b0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:32:54 03/12/2015
// Design Name:
// Module Name: CPU_MIPS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU_MIPS(
output [15 : 0] PC_out,
//output [15 : 0] IR_out,
output [7 : 0] LED_out,
output [5 : 0] LED_ctrl,
input clk,
input clk_click,
input rst,
output real_clk
//input ans_switch
//output [2 : 0] state,
//output [5 : 0] cur_ins
/*output [15 : 0] test,
output [15 : 0] test1,
output [15 : 0] test2,
output [15 : 0] test3,
output [15 : 0] test4*/
);
assign PC_out = PC;
//assign IR_out = IR;
/*assign test = ALUOut;
assign test1 = ALUReg;
assign test2 = Mux3Out;
assign test3 = Cond_Kind;
assign test4 = Jump_Kind;*/
wire [2 : 0] state;
wire [5 : 0] cur_ins;
reg [3 : 0] LED_content;
reg real_clk; // eliminate the shaking hands
reg [26 : 0] second_timer;
always @(posedge clk or negedge rst)
begin
if (rst == 0)
begin
second_timer = 0;
end
else
begin
second_timer = second_timer+1;
if (second_timer >= 10000000)
begin
second_timer = 0;
end
if (second_timer < 5000000)
begin
real_clk = 1'b1;
end
else
begin
real_clk = 1'b0;
end
end
end
// simulate-use
// always @(posedge clk or negedge rst)
// begin
// if (rst == 0)
// begin
// second_timer = 0;
// end
// else
// begin
// second_timer = second_timer+1;
// if (second_timer >= 100)
// begin
// second_timer = 0;
// end
// if (second_timer < 50)
// begin
// real_clk = 1'b1;
// end
// else
// begin
// real_clk = 1'b0;
// end
// end
// end
/*always @(posedge clk_click or negedge rst)
begin
if (rst == 0)
begin
real_clk = 0;
end
else
begin
if (real_clk != 1)
begin
real_clk = 1;
#500;
real_clk = 0;
end
end
end*/
wire [15 : 0] LED_datmem;
wire Cond;
wire Judge;
wire [15 : 0] PC;
wire [15 : 0] NPC;
wire [15 : 0] IR;
wire [15 : 0] RegA;
wire [15 : 0] RegB;
wire [15 : 0] Imm;
wire [15 : 0] ALUOut;
wire [15 : 0] LMD;
wire [15 : 0] Mux1Out;
wire [15 : 0] Mux2Out;
wire [15 : 0] Mux3Out;
wire [15 : 0] Mux4Out;
wire [15 : 0] InsMem;
wire [15 : 0] DatMem;
wire [15 : 0] ALUReg;
wire [15 : 0] AdderOut;
wire [15 : 0] RegOutA;
wire [15 : 0] RegOutB;
wire [15 : 0] ImmExt;
wire Load_NPC;
wire Load_PC;
wire Load_IR;
wire Load_RegA;
wire Load_RegB;
wire Load_Imm;
wire WT_Reg;
wire [3 : 0] Addr_Reg;
wire [2 : 0] Extend;
wire [7 : 0] Send_Reg;
wire Load_LMD;
wire Cond_Kind;
wire [1 : 0] Jump_Kind;
wire Sel_Mux1;
wire Sel_Mux2;
wire [1 : 0] Sel_Mux4;
wire [4 : 0] Cal_ALU;
wire Write;
wire Load_ALU;
Anvyl_DISP
Anvyl7Segment(LED_out, LED_ctrl, clk, rst, {PC[7 : 4], PC[3 : 0], LED_datmem});
Load_Rst_Module
PC_Unit(PC, Load_PC, Mux3Out, rst),
IR_Unit(IR, Load_IR, InsMem, rst),
NPC_Unit(NPC, Load_NPC, AdderOut, rst),
RegA_Unit(RegA, Load_RegA, RegOutA, rst),
RegB_Unit(RegB, Load_RegB, RegOutB, rst),
Imm_Unit(Imm, Load_Imm, ImmExt, rst),
ALUOut_Unit(ALUReg, Load_ALU, ALUOut, rst),
LMD_Unit(LMD, Load_LMD, DatMem, rst);
PC_Adder
Adder_Unit(AdderOut, PC);
Instruction_Memory
InsMem_Unit(InsMem, PC);
Register_Group
Reg_Gp_Unit(RegOutA, RegOutB, WT_Reg, Addr_Reg, Send_Reg, Mux4Out);
Immediate_Extend
ImmExt_Unit(ImmExt, Extend, IR);
Mux_Sel
Mux1(Mux1Out, RegA, NPC, Sel_Mux1),
Mux2(Mux2Out, RegB, Imm, Sel_Mux2),
Mux3(Mux3Out, NPC, ALUReg, Cond);
Arithmetic_Logic_Unit
ALU_Unit(ALUOut, Cal_ALU, Mux1Out, Mux2Out);
Condition_Judge
Jdg_Unit(Judge, Cond_Kind, RegA);
Condition
Cond_Unit(Cond, Jump_Kind, Judge);
Mux_Sel3
Mux4(Mux4Out, ALUReg, LMD, NPC, Sel_Mux4);
Data_Memory
DatMem_Unit(DatMem, Write, ALUReg, RegB, LED_datmem);
Control_Unit
Ctrl_Unit(Load_NPC, Load_PC, Load_IR, Load_RegA, Load_RegB, Load_Imm, WT_Reg, Addr_Reg, Extend, Send_Reg, Load_LMD, Cond_Kind, Jump_Kind,
Sel_Mux1, Sel_Mux2, Sel_Mux4, Cal_ALU, Write, Load_ALU, real_clk, IR, rst, state, cur_ins);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_3_V
`define SKY130_FD_SC_HDLL__DECAP_3_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 3 units (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_3 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_3_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_paramram_wrap.v
// Version : v1.0
// Description: manage address/data generation to paramram module.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_addrram_wrap #
(
parameter C_FAMILY = "virtex7",
parameter C_RAMINIT_ADDRRAM0_F = "NONE" ,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_ATG_BASIC_AXI4 = 0
) (
input Clk ,
input rst_l ,
//s
input [15:0] aw_agen_addr ,
input aw_agen_valid ,
input [15:0] ar_agen_addr ,
input ar_agen_valid ,
input wfifo_valid ,
input [C_S_AXI_DATA_WIDTH*9/8+1-1:0] wfifo_out ,
output [31:0] mr_ext_addr ,
output [31:0] mw_ext_addr ,
output [31:0] rd_ext_addr ,
input [9:0] mar_ptr_new_ff ,
input [9:0] maw_ptr_new_ff
);
generate if(C_M_AXI_ADDR_WIDTH > 32 ) begin : EXT_ADDR_ON
wire [31:0] addrram_rd_data_a;
wire [3:0] addrram_we_b = 4'b0 ;
wire [8:0] addrram_addr_b = {1'b1,maw_ptr_new_ff[7:0]};
wire [31:0] addrram_wr_data_b = 32'h00000000;
wire [31:0] addrram_rd_data_b;
wire addr_ram_we = aw_agen_valid && (aw_agen_addr[15:11] == 5'b00100);
reg addr_ram_we_ff;
wire [8:0] addr_ram_addr_ff;
assign addr_ram_addr_ff = (rst_l) ? ((addr_ram_we) ? aw_agen_addr[10:2] : addr_ram_addr_ff) : 9'h0 ;
wire [3:0] addrram_we_a = (wfifo_valid && addr_ram_we) ? 4'hf : 4'h0 ;
wire [8:0] addrram_addr_a = (wfifo_valid && addr_ram_we) ? addr_ram_addr_ff : (ar_agen_valid && ar_agen_addr[15:11] == 5'b00100) ? ar_agen_addr[10:2] : {1'b0,mar_ptr_new_ff[7:0]};
wire [31:0] addrram_wr_data_a;
assign rd_ext_addr = addrram_rd_data_a;
assign mr_ext_addr = addrram_rd_data_a;
assign mw_ext_addr = addrram_rd_data_b;
always @(posedge Clk) begin
addr_ram_we_ff <= (rst_l) ? ((addr_ram_we) ? 1'h1 : ((wfifo_valid) ? 1'h0 : addr_ram_we_ff)) : 1'h0 ;
end
if(C_S_AXI_DATA_WIDTH == 64) begin: EXT_ADDR_64_GEN
assign addrram_wr_data_a = (addr_ram_addr_ff[0]) ? wfifo_out[63:32]: wfifo_out[31:0];
end
if(C_S_AXI_DATA_WIDTH == 32) begin: EXT_ADDR_32_GEN
assign addrram_wr_data_a = wfifo_out[31:0];
end
axi_traffic_gen_v2_0_7_slvram_v7 #(
.C_FAMILY (C_FAMILY ),
.C_DATAWIDTH (32 ),
.C_SIZE (512 ),
.C_ADDR_WIDTH(9 ),
.C_INITRAM_F (C_RAMINIT_ADDRRAM0_F )
) addrram (
.clk_a (Clk ),
.we_a (addrram_we_a ),
.addr_a (addrram_addr_a ),
.wr_data_a(addrram_wr_data_a),
.rd_data_a(addrram_rd_data_a),
.clk_b (Clk ),
.we_b (addrram_we_b ),
.addr_b (addrram_addr_b ),
.wr_data_b(addrram_wr_data_b),
.rd_data_b(addrram_rd_data_b)
);
end
endgenerate
endmodule
|
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
// semantics of "1" are write occurs, then read
// the other semantics cannot be simulated on a hardened, non-simultaneous
// 1r1w SRAM without changing timing.
// fixme: change to write_then_read_same_addr_p
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( w_v_i | r_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_1r1w_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p (els_p )
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
,.disable_collision_warning_p(disable_collision_warning_p)
) synth
(.clk_i(clk_lo)
,.reset_i
,.w_v_i
,.w_mask_i
,.w_addr_i
,.w_data_i
,.r_v_i
,.r_addr_i
,.r_data_o
);
//synopsys translate_off
/*
always_ff @(negedge clk_lo)
begin
if (reset_i!==1'b1 & (r_v_i | w_v_i))
$display("@@ w=%b w_addr=%x w_data=%x w_mask=%x r=%b r_addr=%x (%m)",w_v_i,w_addr_i,w_data_i,w_mask_i,r_v_i,r_addr_i);
end
*/
always_ff @(posedge clk_lo)
if (w_v_i===1)
begin
assert ((reset_i === 'X) || (reset_i === 1'b1) || (w_addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, w_v_i = %b, clk_lo = %b)\n", w_addr_i, els_p, reset_i, w_v_i, clk_lo);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p)))
else
begin
$error("%m: Attempt to read and write same address reset_i %b, %x <= %x (mask %x)",reset_i, w_addr_i,w_data_i,w_mask_i);
//$finish();
end
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p, harden_p);
if (disable_collision_warning_p)
$display("## %m %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n");
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_mask_write_bit)
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Down-Sizer
// Down-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data, Write Response and Read Data Down-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Down-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi4lite_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_9_axi4lite_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [3-1:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [64-1:0] s_axi_wdata,
input wire [64/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [3-1:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [64-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [32-1:0] m_axi_wdata,
output wire [32/8-1:0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [32-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
reg s_axi_arready_i ;
reg s_axi_rvalid_i ;
reg m_axi_arvalid_i ;
reg m_axi_rready_i ;
reg split_ar ;
reg split_r ;
reg ar_start ;
reg aw_start ;
reg ar_done ;
reg [31:0] rdata_low ;
reg [1:0] rresp_low ;
reg s_axi_awready_i ;
reg s_axi_bvalid_i ;
reg m_axi_awvalid_i ;
reg m_axi_wvalid_i ;
reg m_axi_bready_i ;
reg split_aw ;
reg split_w ;
reg high_aw ;
reg aw_done ;
reg w_done ;
reg [1:0] bresp_low ;
wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr ;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr ;
generate
if (C_AXI_SUPPORTS_READ != 0) begin : gen_read
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_arready_i <= 1'b0 ;
s_axi_rvalid_i <= 1'b0 ;
m_axi_arvalid_i <= 1'b0 ;
m_axi_rready_i <= 1'b0 ;
split_ar <= 1'b0 ;
split_r <= 1'b0 ;
ar_start <= 1'b0 ;
ar_done <= 1'b0 ;
rdata_low <= 32'b0 ;
rresp_low <= 2'b0 ;
end else begin
m_axi_rready_i <= 1'b0; // end single-cycle pulse
if (s_axi_rvalid_i) begin
if (s_axi_rready) begin
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
split_ar <= 1'b0;
split_r <= 1'b0;
ar_start <= 1'b0;
end
end else if (s_axi_arready_i) begin
s_axi_arready_i <= 1'b0; // end single-cycle pulse
s_axi_rvalid_i <= 1'b1;
end else if (ar_done) begin
if (m_axi_rvalid) begin
ar_done <= 1'b0;
if (split_ar & ~split_r) begin
split_r <= 1'b1;
rdata_low <= m_axi_rdata;
rresp_low <= m_axi_rresp;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
m_axi_arvalid_i <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1; // begin single-cycle pulse
end
end
end else if (m_axi_arvalid_i) begin
if (m_axi_arready) begin
m_axi_arvalid_i <= 1'b0;
ar_done <= 1'b1;
end
end else if (s_axi_arvalid & ((C_AXI_SUPPORTS_WRITE==0) | (~aw_start))) begin
m_axi_arvalid_i <= 1'b1;
split_ar <= ~s_axi_araddr[2];
ar_start <= 1'b1;
end
end
end
assign s_axi_arready = s_axi_arready_i ;
assign s_axi_rvalid = s_axi_rvalid_i ;
assign m_axi_arvalid = m_axi_arvalid_i ;
assign m_axi_rready = m_axi_rready_i ;
assign m_axi_araddr = m_axaddr;
assign s_axi_rresp = split_r ? ({m_axi_rresp[1], &m_axi_rresp} | {rresp_low[1], &rresp_low}) : m_axi_rresp;
assign s_axi_rdata = split_r ? {m_axi_rdata,rdata_low} : {m_axi_rdata,m_axi_rdata};
assign m_axi_arprot = s_axi_arprot;
end else begin : gen_noread
assign s_axi_arready = 1'b0 ;
assign s_axi_rvalid = 1'b0 ;
assign m_axi_arvalid = 1'b0 ;
assign m_axi_rready = 1'b0 ;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign s_axi_rresp = 2'b0 ;
assign s_axi_rdata = 64'b0 ;
assign m_axi_arprot = 3'b0 ;
always @ * begin
ar_start = 1'b0;
split_r = 1'b0;
end
end
if (C_AXI_SUPPORTS_WRITE != 0) begin : gen_write
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_awready_i <= 1'b0 ;
s_axi_bvalid_i <= 1'b0 ;
m_axi_awvalid_i <= 1'b0 ;
m_axi_wvalid_i <= 1'b0 ;
m_axi_bready_i <= 1'b0 ;
split_aw <= 1'b0 ;
split_w <= 1'b0 ;
high_aw <= 1'b0 ;
aw_start <= 1'b0 ;
aw_done <= 1'b0 ;
w_done <= 1'b0 ;
bresp_low <= 2'b0 ;
end else begin
m_axi_bready_i <= 1'b0; // end single-cycle pulse
if (s_axi_bvalid_i) begin
if (s_axi_bready) begin
s_axi_bvalid_i <= 1'b0;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
split_aw <= 1'b0;
split_w <= 1'b0;
high_aw <= 1'b0;
aw_start <= 1'b0 ;
end
end else if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0; // end single-cycle pulse
s_axi_bvalid_i <= 1'b1;
end else if (aw_done & w_done) begin
if (m_axi_bvalid) begin
aw_done <= 1'b0;
w_done <= 1'b0;
if (split_aw & ~split_w) begin
split_w <= 1'b1;
bresp_low <= m_axi_bresp;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
m_axi_awvalid_i <= 1'b1;
m_axi_wvalid_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1; // begin single-cycle pulse
end
end
end else begin
if (m_axi_awvalid_i | m_axi_wvalid_i) begin
if (m_axi_awvalid_i & m_axi_awready) begin
m_axi_awvalid_i <= 1'b0;
aw_done <= 1'b1;
end
if (m_axi_wvalid_i & m_axi_wready) begin
m_axi_wvalid_i <= 1'b0;
w_done <= 1'b1;
end
end else if (s_axi_awvalid & s_axi_wvalid & ~aw_done & ~w_done & ((C_AXI_SUPPORTS_READ==0) | (~ar_start & ~s_axi_arvalid))) begin
m_axi_awvalid_i <= 1'b1;
m_axi_wvalid_i <= 1'b1;
aw_start <= 1'b1 ;
split_aw <= ~s_axi_awaddr[2] & (|s_axi_wstrb[7:4]) & (|s_axi_wstrb[3:0]);
high_aw <= ~s_axi_awaddr[2] & (|s_axi_wstrb[7:4]) & ~(|s_axi_wstrb[3:0]);
end
end
end
end
assign s_axi_awready = s_axi_awready_i ;
assign s_axi_wready = s_axi_awready_i ;
assign s_axi_bvalid = s_axi_bvalid_i ;
assign m_axi_awvalid = m_axi_awvalid_i ;
assign m_axi_wvalid = m_axi_wvalid_i ;
assign m_axi_bready = m_axi_bready_i ;
assign m_axi_awaddr = m_axaddr;
assign s_axi_bresp = split_w ? ({m_axi_bresp[1], &m_axi_bresp} | {bresp_low[1], &bresp_low}) : m_axi_bresp;
assign m_axi_wdata = (split_w | s_axi_awaddr[2] | (|s_axi_wstrb[7:4]) & ~(|s_axi_wstrb[3:0])) ? s_axi_wdata[63:32] : s_axi_wdata[31:0];
assign m_axi_wstrb = (split_w | s_axi_awaddr[2] | (|s_axi_wstrb[7:4]) & ~(|s_axi_wstrb[3:0])) ? s_axi_wstrb[7:4] : s_axi_wstrb[3:0];
assign m_axi_awprot = s_axi_awprot;
end else begin : gen_nowrite
assign s_axi_awready = 1'b0 ;
assign s_axi_wready = 1'b0 ;
assign s_axi_bvalid = 1'b0 ;
assign m_axi_awvalid = 1'b0 ;
assign m_axi_wvalid = 1'b0 ;
assign m_axi_bready = 1'b0 ;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign s_axi_bresp = 2'b0 ;
assign m_axi_wdata = 32'b0 ;
assign m_axi_wstrb = 4'b0 ;
assign m_axi_awprot = 3'b0 ;
always @ * begin
aw_start = 1'b0;
split_w = 1'b0;
end
end
if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_ro_addr
assign m_axaddr = split_r ? ({s_axi_araddr[C_AXI_ADDR_WIDTH-1:2], 2'b00} | 3'b100) : s_axi_araddr;
end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_wo_addr
assign m_axaddr = (split_w | high_aw) ? ({s_axi_awaddr[C_AXI_ADDR_WIDTH-1:2], 2'b00} | 3'b100) : s_axi_awaddr;
end else begin : gen_rw_addr
assign s_axaddr = ar_start ? s_axi_araddr : s_axi_awaddr;
assign m_axaddr = (split_w | split_r | high_aw) ? ({s_axaddr[C_AXI_ADDR_WIDTH-1:2], 2'b00} | 3'b100) : s_axaddr;
end
endgenerate
endmodule
|
/*
* Command Buffer
*
* Serial input to parallel output
*
* Check correctness of the received command
*
* Enable/Disable CRC-5 and CRC-16 Encoder/Decoder
*
* Enable to processing the command if the received command is valid
*
* This design of baseband processor is improved by TSMC 0.18 um CMOS standard process
* it does not support EEPROM, so we chose ROM to be the baseband processor's memory
* because we use ROM to be the memory, we are not able to verify the Write command
*/
`timescale 1us / 1ns
module cmd_buf
(
output reg [7:0]cmd,
output [51:0]param,
output package_complete,
output en_crc5,
output en_crc16,
input clk_cmd,
input rst_for_new_package,
input bits_in,
input sync
);
// --- mandatory command of EPC Gen2 protocol ---
parameter QueryRep = 8'b0000_1100;
parameter ACK = 8'b0000_1101;
parameter Query = 8'b0011_1000;
parameter QueryAdjust = 8'b0011_1001;
parameter Select = 8'b0011_1010;
parameter NAK = 8'b1100_0000;
parameter Req_RN = 8'b1100_0001;
parameter Read = 8'b1100_0010;
//parameter Write = 8'b1100_0011;
parameter Kill = 8'b1100_0100;
parameter Lock = 8'b1100_0101;
reg cmd_complete;
reg [52:0]param_tmp;
assign param = param_tmp[51:0];
assign en_crc5 = (cmd_complete & cmd != Query)? 1'b0 : 1'b1;
assign en_crc16 = (cmd_complete & cmd != Select & cmd != Req_RN & cmd != Read & cmd != Kill & cmd != Lock)? 1'b0 : 1'b1;
assign package_complete = (cmd == QueryRep & param_tmp[2])? 1'b1 :
(cmd == ACK & param_tmp[16])? 1'b1 :
(cmd == Query & param_tmp[18])? 1'b1 :
(cmd == QueryAdjust & param_tmp[5])? 1'b1 :
(cmd == Select & param_tmp[52])? 1'b1 :
(cmd == NAK)? 1'b1 :
(cmd == Req_RN & param_tmp[32])? 1'b1 :
(cmd == Read & param_tmp[50])? 1'b1 :
(cmd == Kill & param_tmp[51])? 1'b1 :
(cmd == Lock & param_tmp[52])? 1'b1 : 1'b0;
always@(*) begin
if(cmd == QueryRep | cmd == ACK | cmd == Query |
cmd == QueryAdjust | cmd == Select | cmd == NAK |
cmd == Req_RN | cmd == Read | cmd == Kill | cmd == Lock) cmd_complete = 1'b1;
else cmd_complete = 1'b0;
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) cmd <= 8'b0000_0011;
else begin
if(sync & ~cmd_complete) cmd <= {cmd[6:0], bits_in};
end
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) param_tmp <= 53'b1;
else begin
if(cmd_complete & ~package_complete) param_tmp <= {param_tmp[51:0], bits_in};
end
end
endmodule
|
//`timescale 1 ms /1 us
`include "mux81b.v"
module chap4p32b_tb (S);
// module declaration
output [0:3] S;
reg [0:3] S;
//S[0]=A, S[1]=B, S[2]=C, S[3]=D
wire [0:7] I;
wire Y;
integer fp;
// program body
assign I[0]=~S[3];
assign I[1]=~S[3];
assign I[2]=S[3];
assign I[3]=S[3];
assign I[4]=1'b0;
assign I[5]=S[3];
assign I[6]=1'b0;
assign I[7]=~S[3];
mux81b I1 (I,S[0:2],Y);
initial
begin
fp=$fopen("./chap4p32b_tb.out");
$fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);
#2000
$fclose(fp);
$finish;
end
initial
begin
S=4'b0000;
#100
S=4'b0001;
#100
S=4'b0010;
#100
S=4'b0011;
#100
S=4'b0100;
#100
S=4'b0101;
#100
S=4'b0110;
#100
S=4'b0111;
#100
S=4'b1000;
#100
S=4'b1001;
#100
S=4'b1010;
#100
S=4'b1011;
#100
S=4'b1100;
#100
S=4'b1101;
#100
S=4'b1110;
#100
S=4'b1111;
end
initial #4000 $finish;
endmodule
|
module debounce_pulse(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in==0)
next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debouncer_pulse
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_1_V
`define SKY130_FD_SC_LS__TAPVGNDNOVPB_1_V
/**
* tapvgndnovpb: Substrate only tap cell.
*
* Verilog wrapper for tapvgndnovpb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgndnovpb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgndnovpb_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapvgndnovpb base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgndnovpb_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapvgndnovpb base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGNDNOVPB_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_2_V
`define SKY130_FD_SC_HD__O22A_2_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:47:02 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.v
// Design : system_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_processing_system7_0_0
(SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_WP;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
PULLUP pullup_MIO_0
(.O(MIO[0]));
PULLUP pullup_MIO_9
(.O(MIO[9]));
PULLUP pullup_MIO_10
(.O(MIO[10]));
PULLUP pullup_MIO_11
(.O(MIO[11]));
PULLUP pullup_MIO_12
(.O(MIO[12]));
PULLUP pullup_MIO_13
(.O(MIO[13]));
PULLUP pullup_MIO_14
(.O(MIO[14]));
PULLUP pullup_MIO_15
(.O(MIO[15]));
PULLUP pullup_MIO_46
(.O(MIO[46]));
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *)
(* C_GP1_EN_MODIFIABLE_TXN = "0" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
system_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(SDIO0_WP),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *) (* C_GP1_EN_MODIFIABLE_TXN = "0" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module system_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog Module to implement a 64-bit ripple adder
*/
module ripple_adder_64
(
input [63:0] A,
input [63:0] B,
output [63:0] SUM,
output CARRY
);
// Create wires to connect each full_adder module to another to create a ripple
wire CARRY0, CARRY1, CARRY2, CARRY3, CARRY4, CARRY5, CARRY6, CARRY7, CARRY8, CARRY9, CARRY10;
wire CARRY11, CARRY12, CARRY13, CARRY14, CARRY15, CARRY16, CARRY17, CARRY18, CARRY19, CARRY20;
wire CARRY21, CARRY22, CARRY23, CARRY24, CARRY25, CARRY26, CARRY27, CARRY28, CARRY29, CARRY30;
wire CARRY31, CARRY32, CARRY33, CARRY34, CARRY35, CARRY36, CARRY37, CARRY38, CARRY39, CARRY40;
wire CARRY41, CARRY42, CARRY43, CARRY44, CARRY45, CARRY46, CARRY47, CARRY48, CARRY49, CARRY50;
wire CARRY51, CARRY52, CARRY53, CARRY54, CARRY55, CARRY56, CARRY57, CARRY58, CARRY59, CARRY60;
wire CARRY61, CARRY62, CARRY63;
// The first carry is zero
assign CARRY0 = 1'b0;
// Sixty-Four separate full adders are combined together to perform as one 64-bit adder
full_adder op1 (A[0], B[0], CARRY0, SUM[0], CARRY1);
full_adder op2 (A[1], B[1], CARRY1, SUM[1], CARRY2);
full_adder op3 (A[2], B[2], CARRY2, SUM[2], CARRY3);
full_adder op4 (A[3], B[3], CARRY3, SUM[3], CARRY4);
full_adder op5 (A[4], B[4], CARRY4, SUM[4], CARRY5);
full_adder op6 (A[5], B[5], CARRY5, SUM[5], CARRY6);
full_adder op7 (A[6], B[6], CARRY6, SUM[6], CARRY7);
full_adder op8 (A[7], B[7], CARRY7, SUM[7], CARRY8);
full_adder op9 (A[8], B[8], CARRY8, SUM[8], CARRY9);
full_adder op10 (A[9], B[9], CARRY9, SUM[9], CARRY10);
full_adder op11 (A[10], B[10], CARRY10, SUM[10], CARRY11);
full_adder op12 (A[11], B[11], CARRY11, SUM[11], CARRY12);
full_adder op13 (A[12], B[12], CARRY12, SUM[12], CARRY13);
full_adder op14 (A[13], B[13], CARRY13, SUM[13], CARRY14);
full_adder op15 (A[14], B[14], CARRY14, SUM[14], CARRY15);
full_adder op16 (A[15], B[15], CARRY15, SUM[15], CARRY16);
full_adder op17 (A[16], B[16], CARRY16, SUM[16], CARRY17);
full_adder op18 (A[17], B[17], CARRY17, SUM[17], CARRY18);
full_adder op19 (A[18], B[18], CARRY18, SUM[18], CARRY19);
full_adder op20 (A[19], B[19], CARRY19, SUM[19], CARRY20);
full_adder op21 (A[20], B[20], CARRY20, SUM[20], CARRY21);
full_adder op22 (A[21], B[21], CARRY21, SUM[21], CARRY22);
full_adder op23 (A[22], B[22], CARRY22, SUM[22], CARRY23);
full_adder op24 (A[23], B[23], CARRY23, SUM[23], CARRY24);
full_adder op25 (A[24], B[24], CARRY24, SUM[24], CARRY25);
full_adder op26 (A[25], B[25], CARRY25, SUM[25], CARRY26);
full_adder op27 (A[26], B[26], CARRY26, SUM[26], CARRY27);
full_adder op28 (A[27], B[27], CARRY27, SUM[27], CARRY28);
full_adder op29 (A[28], B[28], CARRY28, SUM[28], CARRY29);
full_adder op30 (A[29], B[29], CARRY29, SUM[29], CARRY30);
full_adder op31 (A[30], B[30], CARRY30, SUM[30], CARRY31);
full_adder op32 (A[31], B[31], CARRY31, SUM[31], CARRY32);
full_adder op33 (A[32], B[32], CARRY32, SUM[32], CARRY33);
full_adder op34 (A[33], B[33], CARRY33, SUM[33], CARRY34);
full_adder op35 (A[34], B[34], CARRY34, SUM[34], CARRY35);
full_adder op36 (A[35], B[35], CARRY35, SUM[35], CARRY36);
full_adder op37 (A[36], B[36], CARRY36, SUM[36], CARRY37);
full_adder op38 (A[37], B[37], CARRY37, SUM[37], CARRY38);
full_adder op39 (A[38], B[38], CARRY38, SUM[38], CARRY39);
full_adder op40 (A[39], B[39], CARRY39, SUM[39], CARRY40);
full_adder op41 (A[40], B[40], CARRY40, SUM[40], CARRY41);
full_adder op42 (A[41], B[41], CARRY41, SUM[41], CARRY42);
full_adder op43 (A[42], B[42], CARRY42, SUM[42], CARRY43);
full_adder op44 (A[43], B[43], CARRY43, SUM[43], CARRY44);
full_adder op45 (A[44], B[44], CARRY44, SUM[44], CARRY45);
full_adder op46 (A[45], B[45], CARRY45, SUM[45], CARRY46);
full_adder op47 (A[46], B[46], CARRY46, SUM[46], CARRY47);
full_adder op48 (A[47], B[47], CARRY47, SUM[47], CARRY48);
full_adder op49 (A[48], B[48], CARRY48, SUM[48], CARRY49);
full_adder op50 (A[49], B[49], CARRY49, SUM[49], CARRY50);
full_adder op51 (A[50], B[50], CARRY50, SUM[50], CARRY51);
full_adder op52 (A[51], B[51], CARRY51, SUM[51], CARRY52);
full_adder op53 (A[52], B[52], CARRY52, SUM[52], CARRY53);
full_adder op54 (A[53], B[53], CARRY53, SUM[53], CARRY54);
full_adder op55 (A[54], B[54], CARRY54, SUM[54], CARRY55);
full_adder op56 (A[55], B[55], CARRY55, SUM[55], CARRY56);
full_adder op57 (A[56], B[56], CARRY56, SUM[56], CARRY57);
full_adder op58 (A[57], B[57], CARRY57, SUM[57], CARRY58);
full_adder op59 (A[58], B[58], CARRY58, SUM[58], CARRY59);
full_adder op60 (A[59], B[59], CARRY59, SUM[59], CARRY60);
full_adder op61 (A[60], B[60], CARRY60, SUM[60], CARRY61);
full_adder op62 (A[61], B[61], CARRY61, SUM[61], CARRY62);
full_adder op63 (A[62], B[62], CARRY62, SUM[62], CARRY63);
full_adder op64 (A[63], B[63], CARRY63, SUM[63], CARRY);
endmodule
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog Module for the full adder module that will be used in the 64-bit ripple adder
*/
module full_adder
(
input A,
input B,
input CARRY_IN,
output SUM,
output CARRY_OUT
);
// Declaring wires for gate connections
wire tmpSum;
wire tmp1;
wire tmp1n;
wire tmp2;
wire tmp2n;
wire tmp3;
wire tmp4;
wire tmp5;
wire tmp6;
// Using two XOR gates with 2 inputs per gate to compute the SUM bit output
xor A1 (tmpSum, A, B);
xor A2 (SUM, CARRY_IN, tmpSum);
// Using various AND, NOT and OR gates with 2 inputs per gate to compute the CARRY_OUT bit
not B1N (tmp1n, B);
and B1 (tmp1, A, tmp1n);
not B2N (tmp2n, A);
and B2 (tmp2, tmp2n, B);
and B3 (tmp3, A, B);
and B4 (tmp4, tmp1, CARRY_IN);
and B5 (tmp5, tmp2, CARRY_IN);
or B6 (tmp6, tmp4, tmp5);
or B7 (CARRY_OUT, tmp6, tmp3);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Source Synchronous Input Deserializer without delay element
// /___/ /\ Filename : ISERDES_NODELAY.v
// \ \ / \ Timestamp : Fri Oct 21 10:31:45 PDT 2005
// \___\/\___\
//
// Revision:
// 10/21/05 - Initial version.
// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real)
// 06/16/06 - Added new port CLKB
// 10/13/06 - Fixed CR 426606
// 07/07/07 - Added wire declaration for internal signals
// 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations
// 12/03/07 - CR 454107 Added DRC warnings for INTERFACE_TYPE, DATA_RATE and DATA_WIDTH combinations
// 01/12/11 - CR 589496 changed some internal parameters to localparams
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDES_NODELAY (Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2,
BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2);
parameter BITSLIP_ENABLE = "FALSE";
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter INIT_Q3 = 1'b0;
parameter INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter integer NUM_CE = 2;
parameter SERDES_MODE = "MASTER";
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKB;
input CLKDIV;
input D;
input OCLK;
input RST;
input SHIFTIN1;
input SHIFTIN2;
localparam SRVAL_Q1 = 1'b0;
localparam SRVAL_Q2 = 1'b0;
localparam SRVAL_Q3 = 1'b0;
localparam SRVAL_Q4 = 1'b0;
tri0 GSR = glbl.GSR;
reg [1:0] sel;
reg [3:0] data_width_int;
reg bts_q1, bts_q2, bts_q3;
reg c23, c45, c67;
reg ce1r, ce2r;
reg dataq1rnk2, dataq2rnk2, dataq3rnk2;
reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1;
reg dataq4rnk2, dataq5rnk2, dataq6rnk2;
reg ice, memmux, q2pmux;
reg mux, mux1, muxc;
reg notifier;
reg clkdiv_int, clkdivmux;
reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0;
reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2;
reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3;
reg q4rnk1, q5rnk1, q6rnk1, q6prnk1;
reg num_ce_int;
reg qr1, qr2, qhc1, qhc2, qlc1, qlc2;
reg shiftn2_in, shiftn1_in;
reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1;
reg serdes_mode_int, data_rate_int, bitslip_enable_int;
wire o_delay;
reg rev_in = 0;
wire shiftout1_out, shiftout2_out;
wire [1:0] sel1;
wire [2:0] bsmux;
wire [3:0] selrnk3;
wire bitslip_in;
wire ce1_in;
wire ce2_in;
wire clk_in;
wire clkb_in;
wire clkdiv_in;
wire d_in;
wire dlyce_in;
wire dlyinc_in;
wire dlyrst_in;
wire gsr_in;
wire oclk_in;
wire sr_in;
wire shiftin1_in;
wire shiftin2_in;
buf b_q1 (Q1, q1_out);
buf b_q2 (Q2, q2_out);
buf b_q3 (Q3, q3_out);
buf b_q4 (Q4, q4_out);
buf b_q5 (Q5, q5_out);
buf b_q6 (Q6, q6_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_bitslip (bitslip_in, BITSLIP);
buf b_ce1 (ce1_in, CE1);
buf b_ce2 (ce2_in, CE2);
buf b_clk (clk_in, CLK);
buf b_clkb (clkb_in, CLKB);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d (d_in, D);
buf b_gsr (gsr_in, GSR);
buf b_oclk (oclk_in, OCLK);
buf b_sr (sr_in, RST);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
// WARNING !!!: This model may not work properly if the
// following parameters are changed.
// xilinx_internal_parameter on
// Parameter declarations for delays
localparam ffinp = 300;
localparam mxinp1 = 60;
localparam mxinp2 = 120;
// Delay parameters
localparam ffice = 300;
localparam mxice = 60;
// Delay parameter assignment
localparam ffbsc = 300;
localparam mxbsc = 60;
localparam mxinp1_my = 0;
// xilinx_internal_parameter off
// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------
task CR454107_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n");
$display("NETWORKING DDR 4, 6, 8, 10\n");
$display("MEMORY SDR None\n");
$display("MEMORY DDR 4\n");
end
endtask // CR454107_msg
initial begin
// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------
case (INTERFACE_TYPE)
"NETWORKING" :
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4, 6, 8, 10 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
"MEMORY" :
case(DATA_RATE)
"DDR" :
case(DATA_WIDTH)
4 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
default : CR454107_msg;
endcase // DATA_RATE
default : ;
endcase // INTERFACE_TYPE
// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------
if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin
$display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration.");
#1 $finish;
end
else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin
$display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground.");
#1 $finish;
end
//------------------------------------------------------------------------------------
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
#1 $finish;
end
endcase // case(SERDES_MODE)
case (DATA_RATE)
"SDR" : data_rate_int <= 1'b1;
"DDR" : data_rate_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
#1 $finish;
end
endcase // case(DATA_RATE)
case (BITSLIP_ENABLE)
"FALSE" : bitslip_enable_int <= 1'b0;
"TRUE" : bitslip_enable_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE);
#1 $finish;
end
endcase // case(BITSLIP_ENABLE)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
#1 $finish;
end
endcase // case(DATA_WIDTH)
case (NUM_CE)
1 : num_ce_int <= 1'b0;
2 : num_ce_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
#1 $finish;
end
endcase // case(NUM_CE)
end // initial begin
assign sel1 = {serdes_mode_int, data_rate_int};
assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00};
assign bsmux = {bitslip_enable_int, data_rate_int, muxc};
// GSR
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
assign bts_q3 = 1'b0;
assign bts_q2 = 1'b0;
assign bts_q1 = 1'b0;
assign clkdiv_int = 1'b0;
assign ce1r = 1'b0;
assign ce2r = 1'b0;
assign q1rnk1 = INIT_Q1;
assign q2nrnk1 = INIT_Q2;
assign q1prnk1 = INIT_Q3;
assign q2prnk1 = INIT_Q4;
assign q3rnk1 = 1'b0;
assign q4rnk1 = 1'b0;
assign q5rnk1 = 1'b0;
assign q6rnk1 = 1'b0;
assign q6prnk1 = 1'b0;
assign q6rnk2 = 1'b0;
assign q5rnk2 = 1'b0;
assign q4rnk2 = 1'b0;
assign q3rnk2 = 1'b0;
assign q2rnk2 = 1'b0;
assign q1rnk2 = 1'b0;
assign q6rnk3 = 1'b0;
assign q5rnk3 = 1'b0;
assign q4rnk3 = 1'b0;
assign q3rnk3 = 1'b0;
assign q2rnk3 = 1'b0;
assign q1rnk3 = 1'b0;
end
else if (gsr_in == 1'b0) begin
deassign bts_q3;
deassign bts_q2;
deassign bts_q1;
deassign clkdiv_int;
deassign ce1r;
deassign ce2r;
deassign q1rnk1;
deassign q2nrnk1;
deassign q1prnk1;
deassign q2prnk1;
deassign q3rnk1;
deassign q4rnk1;
deassign q5rnk1;
deassign q6rnk1;
deassign q6prnk1;
deassign q6rnk2;
deassign q5rnk2;
deassign q4rnk2;
deassign q3rnk2;
deassign q2rnk2;
deassign q1rnk2;
deassign q6rnk3;
deassign q5rnk3;
deassign q4rnk3;
deassign q3rnk3;
deassign q2rnk3;
deassign q1rnk3;
end // if (gsr_in == 1'b0)
end // always @ (gsr_in)
// to workaround the glitches generated by mux of assign delay above
// always @(delay_count)
// delay_count_int <= #0 delay_count;
assign o_delay = d_in;
// 1st rank of registers
// Asynchronous Operation
always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
// 1st flop in rank 1 that is full featured
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1))
q1rnk1 <= # ffinp SRVAL_Q1;
else if (rev_in == 1'b1)
q1rnk1 <= # ffinp !SRVAL_Q1;
else if (ice == 1'b1)
q1rnk1 <= # ffinp o_delay;
end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
always @(posedge clk_in or posedge sr_in) begin
// rest of flops which are not full featured and don't have clock options
if (sr_in == 1'b1) begin
q5rnk1 <= # ffinp 1'b0;
q6rnk1 <= # ffinp 1'b0;
q6prnk1 <= # ffinp 1'b0;
end
else begin
q5rnk1 <= # ffinp dataq5rnk1;
q6rnk1 <= # ffinp dataq6rnk1;
q6prnk1 <= # ffinp q6rnk1;
end
end // always @ (posedge clk_in or sr_in)
// 2nd flop in rank 1
// Asynchronous Operation
always @(posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1))
q2nrnk1 <= # ffinp SRVAL_Q2;
else if (rev_in == 1'b1)
q2nrnk1 <= # ffinp !SRVAL_Q2;
else if (ice == 1'b1)
q2nrnk1 <= # ffinp o_delay;
end // always @ (posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 4th flop in rank 1 operating on the posedge for networking
// Asynchronous Operation
always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1))
q2prnk1 <= # ffinp SRVAL_Q4;
else if (rev_in == 1'b1)
q2prnk1 <= # ffinp !SRVAL_Q4;
else if (ice == 1'b1)
q2prnk1 <= # ffinp q2nrnk1;
end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 3rd flop in 2nd rank which is full featured and has
// a choice of being clocked by oclk or clk
// Asynchronous Operation
always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1))
q1prnk1 <= # ffinp SRVAL_Q3;
else if (rev_in == 1'b1)
q1prnk1 <= # ffinp !SRVAL_Q3;
else if (ice == 1'b1)
q1prnk1 <= # ffinp q1rnk1;
end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 5th and 6th flops in rank 1 which are not full featured but can be clocked
// by either clk or oclk
always @(posedge memmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q3rnk1 <= # ffinp 1'b0;
q4rnk1 <= # ffinp 1'b0;
end
else begin
q3rnk1 <= # ffinp dataq3rnk1;
q4rnk1 <= # ffinp dataq4rnk1;
end
end // always @ (posedge memmux or posedge sr_in)
//////////////////////////////////////////
// Mux elements for the 1st rank
////////////////////////////////////////
// Optional inverter for q2p (4th flop in rank1)
always @ (memmux) begin
case (INTERFACE_TYPE)
"MEMORY" : q2pmux <= # mxinp1 !memmux;
"NETWORKING" : q2pmux <= # mxinp1 memmux;
default: q2pmux <= # mxinp1 !memmux;
endcase
end // always @ (memmux)
// 4 clock muxs in first rank
always @(clk_in or oclk_in) begin
case (INTERFACE_TYPE)
"MEMORY" : memmux <= # mxinp1 oclk_in;
"NETWORKING" : memmux <= # mxinp1 clk_in;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE);
$finish;
end
endcase // case(INTERFACE_TYPE)
end // always @(clk_in or oclk_in)
// data input mux for q3, q4, q5 and q6
always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin
case (sel1)
2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in;
2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in;
default : dataq3rnk1 <= # mxinp1 q1prnk1;
endcase // case(sel1)
end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2)
always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin
case (sel1)
2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1;
2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1;
2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in;
2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1;
default : dataq4rnk1 <= # mxinp1 q2prnk1;
endcase // case(sel1)
end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1)
always @(data_rate_int or q3rnk1 or q4rnk1) begin
case (data_rate_int)
1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1;
1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1;
default : dataq5rnk1 <= # mxinp1 q4rnk1;
endcase // case(DATA_RATE)
end
always @(data_rate_int or q4rnk1 or q5rnk1) begin
case (data_rate_int)
1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1;
1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1;
default : dataq6rnk1 <= # mxinp1 q5rnk1;
endcase // case(DATA_RATE)
end
// 2nd rank of registers
// clkdivmux to pass clkdiv_int or CLKDIV to rank 2
always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin
case (bitslip_enable_int)
1'b0 : clkdivmux <= # mxinp1 clkdiv_in;
1'b1 : clkdivmux <= # mxinp1 clkdiv_int;
default : clkdivmux <= # mxinp1 clkdiv_in;
endcase // case(BITSLIP_ENABLE)
end // always @(clkdiv_int or clkdiv_in)
// Asynchronous Operation
always @(posedge clkdivmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk2 <= # ffinp 1'b0;
q2rnk2 <= # ffinp 1'b0;
q3rnk2 <= # ffinp 1'b0;
q4rnk2 <= # ffinp 1'b0;
q5rnk2 <= # ffinp 1'b0;
q6rnk2 <= # ffinp 1'b0;
end
else begin
q1rnk2 <= # ffinp dataq1rnk2;
q2rnk2 <= # ffinp dataq2rnk2;
q3rnk2 <= # ffinp dataq3rnk2;
q4rnk2 <= # ffinp dataq4rnk2;
q5rnk2 <= # ffinp dataq5rnk2;
q6rnk2 <= # ffinp dataq6rnk2;
end
end // always @ (posedge clkdivmux or sr_in)
// Data mux for 2nd rank of flops
// Delay for mux set to 120
always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin
casex (bsmux)
3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1;
3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1;
default : dataq1rnk2 <= # mxinp2 q2prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1)
always @(bsmux or q1prnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1;
3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1;
default : dataq2rnk2 <= # mxinp2 q1prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1prnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1;
3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1;
default : dataq3rnk2 <= # mxinp2 q4rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1;
3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1;
default : dataq4rnk2 <= # mxinp2 q3rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1;
3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1;
default : dataq5rnk2 <= # mxinp2 q6rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin
casex (bsmux)
3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1;
3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1;
default : dataq6rnk2 <= # mxinp2 q5rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1)
// 3rd rank of registers
// Asynchronous Operation
always @(posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk3 <= # ffinp 1'b0;
q2rnk3 <= # ffinp 1'b0;
q3rnk3 <= # ffinp 1'b0;
q4rnk3 <= # ffinp 1'b0;
q5rnk3 <= # ffinp 1'b0;
q6rnk3 <= # ffinp 1'b0;
end
else begin
q1rnk3 <= # ffinp q1rnk2;
q2rnk3 <= # ffinp q2rnk2;
q3rnk3 <= # ffinp q3rnk2;
q4rnk3 <= # ffinp q4rnk2;
q5rnk3 <= # ffinp q5rnk2;
q6rnk3 <= # ffinp q6rnk2;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Outputs
assign shiftout2_out = q5rnk1;
assign shiftout1_out = q6rnk1;
always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin
casex (selrnk3)
4'b0X00 : q1_out <= # mxinp1_my q1prnk1;
4'b0X01 : q1_out <= # mxinp1_my q1rnk1;
4'b0X10 : q1_out <= # mxinp1_my q1rnk1;
4'b10XX : q1_out <= # mxinp1_my q1rnk2;
4'b11XX : q1_out <= # mxinp1_my q1rnk3;
default : q1_out <= # mxinp1_my q1rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3)
always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin
casex (selrnk3)
4'b0X00 : q2_out <= # mxinp1_my q2prnk1;
4'b0X01 : q2_out <= # mxinp1_my q2prnk1;
4'b0X10 : q2_out <= # mxinp1_my q2nrnk1;
4'b10XX : q2_out <= # mxinp1_my q2rnk2;
4'b11XX : q2_out <= # mxinp1_my q2rnk3;
default : q2_out <= # mxinp1_my q2rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3)
always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin
case (bitslip_enable_int)
1'b0 : q3_out <= # mxinp1_my q3rnk2;
1'b1 : q3_out <= # mxinp1_my q3rnk3;
endcase // case(BITSLIP_ENABLE)
end // always @ (q3rnk2 or q3rnk3)
always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin
casex (bitslip_enable_int)
1'b0 : q4_out <= # mxinp1_my q4rnk2;
1'b1 : q4_out <= # mxinp1_my q4rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q4rnk2 or q4rnk3)
always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin
casex (bitslip_enable_int)
1'b0 : q5_out <= # mxinp1_my q5rnk2;
1'b1 : q5_out <= # mxinp1_my q5rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q5rnk2 or q5rnk3)
always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin
casex (bitslip_enable_int)
1'b0 : q6_out <= # mxinp1_my q6rnk2;
1'b1 : q6_out <= # mxinp1_my q6rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q6rnk2 or q6rnk3)
// Set value of counter in bitslip controller
always @(data_rate_int or data_width_int) begin
casex ({data_rate_int, data_width_int})
5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default : begin
$display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time);
$finish;
end
endcase
end // always @ (data_rate_int or data_width_int)
///////////////////////////////////////////
// Bit slip controler
///////////////////////////////////////////
// Divide by 2 - 8 counter
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b0) begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (posedge qr2 or negedge clk_in)
// Synchronous Operation
always @ (negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b1) begin
clkdiv_int <= # ffbsc clkdiv_int;
bts_q1 <= # ffbsc bts_q1;
bts_q2 <= # ffbsc bts_q2;
bts_q3 <= # ffbsc bts_q3;
end
else begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (negedge clk_in)
// 4:1 selector mux and divider selections
always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin
case (sel)
2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2));
2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3));
2'b11 : mux <= # mxbsc !bts_q3;
default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
endcase
end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3)
// Bitslip control logic
// Low speed control flop
// Asynchronous Operation
always @ (posedge qr1 or posedge clkdiv_in) begin
if (qr1 == 1'b1) begin
qlc1 <= # ffbsc 1'b0;
qlc2 <= # ffbsc 1'b0;
end
else if (bitslip_in == 1'b0) begin
qlc1 <= # ffbsc qlc1;
qlc2 <= # ffbsc 1'b0;
end
else begin
qlc1 <= # ffbsc !qlc1;
qlc2 <= # ffbsc (bitslip_in & mux1);
end
end // always @ (posedge qr1 or posedge clkdiv_in)
// Mux to select between sdr "1" and ddr "0"
always @ (data_rate_int or qlc1) begin
case (data_rate_int)
1'b0 : mux1 <= # mxbsc qlc1;
1'b1 : mux1 <= # mxbsc 1'b1;
endcase
end
// High speed control flop
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
qhc1 <= # ffbsc 1'b0;
qhc2 <= # ffbsc 1'b0;
end
else begin
qhc1 <= # ffbsc (qlc2 & !qhc2);
qhc2 <= # ffbsc qlc2;
end
end // always @ (posedge qr2 or negedge clk_in)
// Mux that drives control line of mux in front
// of 2nd rank of flops
always @ (data_rate_int or mux1) begin
case (data_rate_int)
1'b0 : muxc <= # mxbsc mux1;
1'b1 : muxc <= # mxbsc 1'b0;
endcase
end
// Asynchronous set flops
// Low speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qr1 <= # ffbsc 1'b1;
else
qr1 <= # ffbsc 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or negedge clk_in) begin
if (sr_in == 1'b1)
qr2 <= # ffbsc 1'b1;
else
qr2 <= # ffbsc qr1;
end // always @ (posedge sr_in or negedge clk_in)
/////////////////////////////////////////////
// ICE
///////////////////////////////////////////
// Asynchronous Operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
ce1r <= # ffice 1'b0;
ce2r <= # ffice 1'b0;
end
else begin
ce1r <= # ffice ce1_in;
ce2r <= # ffice ce2_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Output mux ice
always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin
case ({num_ce_int, clkdiv_in})
2'b00 : ice <= # mxice ce1_in;
2'b01 : ice <= # mxice ce1_in;
// 426606
2'b10 : ice <= # mxice ce2r;
2'b11 : ice <= # mxice ce1r;
default : ice <= # mxice ce1_in;
endcase
end
//*** Timing Checks Start here
specify
(CLKDIV => Q1) = (100:100:100, 100:100:100);
(CLKDIV => Q2) = (100:100:100, 100:100:100);
(CLKDIV => Q3) = (100:100:100, 100:100:100);
(CLKDIV => Q4) = (100:100:100, 100:100:100);
(CLKDIV => Q5) = (100:100:100, 100:100:100);
(CLKDIV => Q6) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // ISERDES_NODELAY
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_4_V
`define SKY130_FD_SC_HD__DFXTP_4_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V |
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => negb b2
| false => true
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match b1 with
| true => andb b2 b3
| false => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
ble_nat (n + 1) m.
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o.
intros H J.
rewrite -> H.
rewrite -> J.
reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
intros H.
rewrite -> plus_1_l.
rewrite <- H.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n. destruct n.
simpl. reflexivity.
simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite -> H.
rewrite -> H.
reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite -> H.
rewrite -> H.
destruct b.
reflexivity.
reflexivity. Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
destruct b.
(* First Case *)
intros c.
simpl.
intros H.
rewrite H.
reflexivity.
(* Second Case *)
intros c.
simpl.
intros H.
rewrite H.
reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| B : bin (* Zero *)
| M : bin -> bin (* One more than twice a number *)
| T : bin -> bin. (* Twice a number *)
Fixpoint inc (n : bin) : bin :=
match n with
| B => M B
| T n => M n
| M n => T (inc n)
end.
Example text_zero:
inc B = M B.
Proof. reflexivity. Qed.
Example test_even_zero:
inc (T B) = M B.
Proof. reflexivity. Qed.
Example test_one:
inc (M B) = T (M B).
Proof. reflexivity. Qed.
Example test_seven:
inc (M (M (M B))) = T (T (T (M B))).
Proof. reflexivity. Qed.
Fixpoint bin_to_nat (n : bin) : nat :=
match n with
| B => O
| T n => 2 * (bin_to_nat n)
| M n => 2 * (bin_to_nat n) + 1
end.
Example test_bin_to_nat_even_zero:
bin_to_nat (T B) = 0.
Proof. reflexivity. Qed.
Example test_bin_to_nat_six:
bin_to_nat (T (M (M B))) = 6.
Proof. reflexivity. Qed.
Example test_bin_to_nat_ten:
bin_to_nat (T (M (T (M B)))) = 10.
Proof. reflexivity. Qed.
(* To ramp up to showing distributivity of inc and conversion, let's prove some basic maths first! *)
Lemma plus_0_r:
forall (n : nat),
n + 0 = n.
Proof.
intros n.
induction n as [|n'].
(* Base case *)
reflexivity.
(* Ind. case *)
simpl.
rewrite IHn'.
reflexivity.
Qed.
Lemma plus_S_assoc:
forall (m n : nat),
m + (S n) = S (m + n).
Proof.
intros m n.
induction m as [|m'].
(* Base case *)
reflexivity.
(* Ind. case *)
simpl.
rewrite IHm'.
reflexivity.
Qed.
Lemma plus_comm:
forall (m n : nat),
m + n = n + m.
Proof.
intros m n.
induction n as [|n'].
(* Base Case *)
simpl.
rewrite plus_0_r.
reflexivity.
(* Ind. case *)
simpl.
rewrite <- IHn'.
rewrite plus_S_assoc.
reflexivity.
Qed.
(* Phew, now for what's important *)
Lemma inc_bin_to_nat_distributive:
forall (b : bin),
bin_to_nat (inc b) = S (bin_to_nat b).
Proof.
intros b.
induction b as [|b'|b'].
(* Base case *)
reflexivity.
(* IC1 *)
simpl.
rewrite IHb'.
rewrite plus_0_r.
rewrite plus_0_r.
rewrite plus_S_assoc.
rewrite plus_S_assoc.
rewrite plus_0_r.
reflexivity.
(* IC2 *)
simpl.
rewrite plus_0_r.
rewrite plus_S_assoc.
rewrite plus_0_r.
reflexivity.
Qed.
(* Woop! *)
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(** A classic! Ackermann *)
(*
Fixpoint ackermann (m n : nat) {struct n} : nat :=
match m with
| O => S n
| S m =>
match n with
| 0 => ackermann m 1
| S n => ackermann m (ackermann (S m) n)
end
end.
*)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHa2.
SSCase "n <> 0". simpl. rewrite IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
Case "AMinus".
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Case "AMult".
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
(* FILL IN HERE *) admit.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
(* FILL IN HERE *)
*)
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Liebniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
(*
Inductive bevalR:
(* FILL IN HERE *)
*)
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** *** Adding nondeterminism *)
(* /TERSE *)
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(** After you've defined [s_compile], uncomment the following to test
that it works. *)
(*
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
calculator implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;
Y ::= 1;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;
X ::= 1;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
(* FILL IN HERE *)
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK; c) / st || s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2014-02-22 09:43:41 -0500 (Sat, 22 Feb 2014) $ *)
|
module Transmit(
input Transmit_CLK, //100MHz
input [7:0] Line_Num, //Line Num,256 Lines totally,0~255
input [1:0] Focus_Num, //Focus_num ,3 totally
input Pr_Gate, //prepare for everythings
input RX_Gate, // Start Transmit
output reg Sample_Gate, //
output reg [15:0] P,
output reg [15:0] N,
output reg HV_SW_CLR,
output reg HV_SW_LE,
output reg HV_SW_CLK,
output reg HV_SW_DOUT,
output reg [3:0] AX,
output reg [2:0] AY,
output reg MT_CS,
output reg MT_Strobe,
output reg MT_Data
);
wire [7:0] Delay_CH1,Delay_CH2, Delay_CH3, Delay_CH4, Delay_CH5, Delay_CH6, Delay_CH7, Delay_CH8;
wire [7:0] Delay_CH9,Delay_CH10,Delay_CH11,Delay_CH12,Delay_CH13,Delay_CH14,Delay_CH15,Delay_CH16;
reg [5:0] EMIT_WIDTH;
always @(*) begin
case(Focus_Num[1:0])
2'b00: //20mm
EMIT_WIDTH <= 6'd14; //4MHz
2'b01: //40mm
EMIT_WIDTH <= 6'd14; //3.5MHz
2'b10: //80mm
EMIT_WIDTH <= 6'd16; //3MHz
2'b11: //80mm
EMIT_WIDTH <= 6'd16; //3MHz
endcase
end
//replace rom for saving M9K ram
wire [7:0] Test_q;
Test_Line Test_Line_inst (
.address (1'b0 ),
.clock (Pr_Gate),
.q (Test_q )
);
reg [127:0] Delay_ALL;
always @(posedge Pr_Gate) begin
/*
case(Test_q[2:0] )
//R=60mm
//20mm
3'b00: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h8000070D1215181A1A1A1815120D0700;
else // even
Delay_ALL <= 128'h00070D1215181A1A1A1815120D070080;
end
// 40mm
3'b001: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h800004080B0D0F1011100F0D0B080400;
else // even
Delay_ALL <= 128'h0004080B0D0F1011100F0D0B08040080;
end
//60mm
3'b010: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h80000406090B0C0D0D0D0C0B09060400;
else // even
Delay_ALL <= 128'h000406090B0C0D0D0D0C0B0906040080;
end
//80mm
3'b011: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h8000030608090B0B0C0B0B0908060300;
else // even
Delay_ALL <= 128'h00030608090B0B0C0B0B090806030080;
end
//100mm
3'b100: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h8000030507090A0A0B0A0A0907050300;
else // even
Delay_ALL <= 128'h00030507090A0A0B0A0A090705030080;
end
//120mm
3'b101: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h800003050708090A0A0A090807050300;
else // even
Delay_ALL <= 128'h0003050708090A0A0A09080705030080;
end
endcase
*/
case(Focus_Num[1:0] )
//20mm
2'b00: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h8000070D1215181A1A1A1815120D0700;
else // even
Delay_ALL <= 128'h00070D1215181A1A1A1815120D070080;
end
// 40mm
2'b01: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h800004080B0D0F1011100F0D0B080400;
else // even
Delay_ALL <= 128'h0004080B0D0F1011100F0D0B08040080;
end
//80mm outside
2'b10: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h800004080B0D0F1011100F0D0B080400;
else // even
Delay_ALL <= 128'h0004080B0D0F1011100F0D0B08040080;
/*
// 80mm
if(Line_Num[0]) // odd
Delay_ALL <= 128'h8000030608090B0B0C0B0B0908060300;
else // even
Delay_ALL <= 128'h00030608090B0B0C0B0B090806030080;
*/
end
//80mm inside
2'b11: begin
if(Line_Num[0]) // odd
Delay_ALL <= 128'h800004080B0D0F1011100F0D0B080400;
else // even
Delay_ALL <= 128'h0004080B0D0F1011100F0D0B08040080;
/*
// 80mm
if(Line_Num[0]) // odd
Delay_ALL <= 128'h8000030608090B0B0C0B0B0908060300;
else // even
Delay_ALL <= 128'h00030608090B0B0C0B0B090806030080;
*/
end
endcase
end
assign Delay_CH1=(Pr_Gate)?Delay_ALL[127:120]:Delay_CH1;
assign Delay_CH2=(Pr_Gate)?Delay_ALL[119:112]:Delay_CH2;
assign Delay_CH3=(Pr_Gate)?Delay_ALL[111:104]:Delay_CH3;
assign Delay_CH4=(Pr_Gate)?Delay_ALL[103:96]:Delay_CH4;
assign Delay_CH5=(Pr_Gate)?Delay_ALL[95:88]:Delay_CH5;
assign Delay_CH6=(Pr_Gate)?Delay_ALL[87:80]:Delay_CH6;
assign Delay_CH7=(Pr_Gate)?Delay_ALL[79:72]:Delay_CH7;
assign Delay_CH8=(Pr_Gate)?Delay_ALL[71:64]:Delay_CH8;
assign Delay_CH9=(Pr_Gate)?Delay_ALL[63:56]:Delay_CH9;
assign Delay_CH10=(Pr_Gate)?Delay_ALL[55:48]:Delay_CH10;
assign Delay_CH11=(Pr_Gate)?Delay_ALL[47:40]:Delay_CH11;
assign Delay_CH12=(Pr_Gate)?Delay_ALL[39:32]:Delay_CH12;
assign Delay_CH13=(Pr_Gate)?Delay_ALL[31:24]:Delay_CH13;
assign Delay_CH14=(Pr_Gate)?Delay_ALL[23:16]:Delay_CH14;
assign Delay_CH15=(Pr_Gate)?Delay_ALL[15:8]:Delay_CH15;
assign Delay_CH16=(Pr_Gate)?Delay_ALL[7:0]:Delay_CH16;
reg [7:0] Delay_Counter;
reg Sec_HW_Gate ;
always @(posedge Transmit_CLK or negedge RX_Gate)
begin
if(~RX_Gate) begin
Delay_Counter <= 8'd0;
Sample_Gate <= 1'b0;
Sec_HW_Gate <= 1'b0;
end
else
begin
if(Delay_Counter < Delay_CH8 ) //longest path
begin
Delay_Counter <= Delay_Counter + 1'b1;
Sample_Gate <= 1'b0;
Sec_HW_Gate <= 1'b0;
end
else if(Delay_Counter < (Delay_CH8 + 8'd5) ) begin //about 50ns width
Delay_Counter <= Delay_Counter + 1'b1;
Sample_Gate <= 1'b1;
Sec_HW_Gate <= 1'b0;
end
else if(Delay_Counter < (Delay_CH8 + {EMIT_WIDTH[5:0],2'b0} +EMIT_WIDTH[5:0] ) ) begin //wait finish emit
Delay_Counter <= Delay_Counter + 1'b1;
Sample_Gate <= 1'b0;
Sec_HW_Gate <= 1'b0;
end
else if(Delay_Counter < (Delay_CH8 + {EMIT_WIDTH[5:0],2'b0}+EMIT_WIDTH[5:0]+8'd5) ) begin //switch to inner
Delay_Counter <= Delay_Counter + 1'b1;
Sample_Gate <= 1'b0;
Sec_HW_Gate <= 1'b1;
end
else begin
Sample_Gate <= 1'b0;
Sec_HW_Gate<= 1'b0;
end
end
end
wire [15:0] TXP;
wire [15:0] TXN;
EmitOneCH EmitOneCH1
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate (RX_Gate), //Transmit Enable
.EmitDelay (Delay_CH1), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width (EMIT_WIDTH), //Emit pulse width
.TXP (TXP[0]),
.TXN (TXN[0])
);
EmitOneCH EmitOneCH2
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate (RX_Gate), //Transmit Enable
.EmitDelay (Delay_CH2), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width (EMIT_WIDTH), //Emit pulse width
.TXP (TXP[1]),
.TXN (TXN[1])
);
EmitOneCH EmitOneCH3
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH3), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[2]),
.TXN(TXN[2])
);
EmitOneCH EmitOneCH4
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH4), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[3]),
.TXN(TXN[3])
);
EmitOneCH EmitOneCH5
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH5), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[4]),
.TXN(TXN[4])
);
EmitOneCH EmitOneCH6
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH6), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[5]),
.TXN(TXN[5])
);
EmitOneCH EmitOneCH7
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH7), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[6]),
.TXN(TXN[6])
);
EmitOneCH EmitOneCH8
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH8), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[7]),
.TXN(TXN[7])
);
EmitOneCH EmitOneCH9
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH9), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[8]),
.TXN(TXN[8])
);
EmitOneCH EmitOneCH10
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH10), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[9]),
.TXN(TXN[9])
);
EmitOneCH EmitOneCH11
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH11), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[10]),
.TXN(TXN[10])
);
EmitOneCH EmitOneCH12
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH12), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[11]),
.TXN(TXN[11])
);
EmitOneCH EmitOneCH13
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH13), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[12]),
.TXN(TXN[12])
);
EmitOneCH EmitOneCH14
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH14), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[13]),
.TXN(TXN[13])
);
EmitOneCH EmitOneCH15
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH15), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[14]),
.TXN(TXN[14])
);
EmitOneCH EmitOneCH16
(
.Transmit_CLK(Transmit_CLK), //100MHz
.RX_Gate(RX_Gate), //Transmit Enable
.EmitDelay(Delay_CH16), //7th bit for Transmit Enable, 6:0 for Delay
.Emit_Width(EMIT_WIDTH), //Emit pulse width
.TXP(TXP[15]),
.TXN(TXN[15])
);
/////////////////////////////
//// Seq_adjust
always @( posedge Transmit_CLK) begin //start from 8 line
case (Line_Num[4:1]+4'd8) //??//
4'd0:
begin
P[15:0] <= TXP[15:0];
N[15:0] <= TXN[15:0];
end
4'd1:
begin
P[15:0] <= {TXP[14:0],TXP[15]};
N[15:0] <= {TXN[14:0],TXN[15]};
end
4'd02:
begin
P[15:0] <= {TXP[13:0],TXP[15:14]};
N[15:0] <= {TXN[13:0],TXN[15:14]};
end
4'd03:
begin
P[15:0] <= {TXP[12:0],TXP[15:13]};
N[15:0] <= {TXN[12:0],TXN[15:13]};
end
4'd04:
begin
P[15:0] <= {TXP[11:0],TXP[15:12]};
N[15:0] <= {TXN[11:0],TXN[15:12]};
end
4'd05:
begin
P[15:0] <= {TXP[10:0],TXP[15:11]};
N[15:0] <= {TXN[10:0],TXN[15:11]};
end
4'd06:
begin
P[15:0] <= {TXP[9:0],TXP[15:10]};
N[15:0] <= {TXN[9:0],TXN[15:10]};
end
4'd07:
begin
P[15:0] <= {TXP[8:0],TXP[15:9]};
N[15:0] <= {TXN[8:0],TXN[15:9]};
end
4'd08:
begin
P[15:0] <= {TXP[7:0],TXP[15:8]};
N[15:0] <= {TXN[7:0],TXN[15:8]};
end
4'd09:
begin
P[15:0] <= {TXP[6:0],TXP[15:7]};
N[15:0] <= {TXN[6:0],TXN[15:7]};
end
4'd10:
begin
P[15:0] <= {TXP[5:0],TXP[15:6]};
N[15:0] <= {TXN[5:0],TXN[15:6]};
end
4'd11:
begin
P[15:0] <= {TXP[4:0],TXP[15:5]};
N[15:0] <= {TXN[4:0],TXN[15:5]};
end
4'd12:
begin
P[15:0] <= {TXP[3:0],TXP[15:4]};
N[15:0] <= {TXN[3:0],TXN[15:4]};
end
4'd13:
begin
P[15:0] <= {TXP[2:0],TXP[15:3]};
N[15:0] <= {TXN[2:0],TXN[15:3]};
end
4'd14:
begin
P[15:0] <= {TXP[1:0],TXP[15:2]};
N[15:0] <= {TXN[1:0],TXN[15:2]};
end
4'd15:
begin
P[15:0] <= {TXP[0],TXP[15:1]};
N[15:0] <= {TXN[0],TXN[15:1]};
end
endcase
end
wire [127:0] HW_SW_value;
reg [7:0] HW_Addr;
always @(*)
begin
if(Focus_Num == 2'b00) //20mm
HW_Addr <={1'b0,Line_Num[7:1]};
else if(Focus_Num == 2'b01) //40mm
HW_Addr <={1'b0,Line_Num[7:1]};
else if(Focus_Num == 2'b11) //80mm //inner 16ch
HW_Addr <={1'b0,Line_Num[7:1]};
else if(Focus_Num == 2'b10) //80mm //outside 16ch
if(Sec_HW_Gate)
HW_Addr <={1'b1,Line_Num[7:1]}; // outside 16ch
else
HW_Addr <={1'b0,Line_Num[7:1]}; //transmit inner 16CH
end
HW_SW HW_SW_inst (
.address (HW_Addr ),
.clock (Transmit_CLK ),
.q (HW_SW_value )
);
/////////////////////////////////////////
///shift the value to HW switch
reg [7:0] Shift_Counter;
reg [1:0] State_Counter;
reg [127:0] Shift_HW_SW;
wire Pr_Gate_Trigger;
reg Pr_Gate_Reg1,Pr_Gate_Reg2,Pr_Gate_Reg3,Pr_Gate_Reg4;
always @(posedge Transmit_CLK)
begin
Pr_Gate_Reg4 <= Pr_Gate_Reg3;
Pr_Gate_Reg3 <= Pr_Gate_Reg2;
Pr_Gate_Reg2 <= Pr_Gate_Reg1;
Pr_Gate_Reg1 <= Pr_Gate;
end
assign Pr_Gate_Trigger = Pr_Gate_Reg1 & (~Pr_Gate_Reg4);
always @(posedge Transmit_CLK or posedge Pr_Gate_Trigger)
begin
if(Pr_Gate_Trigger)
begin
HV_SW_CLR <= 1'b0;
HV_SW_LE <= 1'b1;
HV_SW_CLK <= 1'b0;
HV_SW_DOUT <= 1'b0;
Shift_Counter <= 8'd0;
State_Counter <= 8'd0;
Shift_HW_SW <= HW_SW_value;
HV_SW_LE <= 1'b1;
end
else
begin
if(Sec_HW_Gate)
begin
HV_SW_CLR <= 1'b0;
HV_SW_LE <= 1'b1;
HV_SW_CLK <= 1'b0;
HV_SW_DOUT <= 1'b0;
Shift_Counter <= 8'd0;
State_Counter <= 8'd0;
Shift_HW_SW <= HW_SW_value;
HV_SW_LE <= 1'b1;
end
else begin
if(Shift_Counter <8'd128)
begin
HV_SW_LE <= 1'b1;
if(State_Counter ==2'b00) begin //set data
HV_SW_DOUT <= Shift_HW_SW[0];
HV_SW_CLK <= 1'b0;
State_Counter <= State_Counter + 1'b1;
end
else if(State_Counter ==2'b01) begin //shift the value
Shift_HW_SW <= Shift_HW_SW >>1;
HV_SW_CLK <= 1'b0;
State_Counter <= State_Counter + 1'b1;
end
else if(State_Counter ==2'b10) begin // data period == 25M
HV_SW_CLK <= 1'b1;
State_Counter <= State_Counter + 1'b1;
end
else if(State_Counter ==2'b11) begin // set next shift counter
HV_SW_CLK <= 1'b1;
State_Counter <= State_Counter + 1'b1;
Shift_Counter <= Shift_Counter + 1'b1;
end
HV_SW_CLR <= 1'b0;
end
else if(Shift_Counter <8'd130) begin
HV_SW_LE <= 1'b0;
HV_SW_CLK <= 1'b0;
HV_SW_CLR <= 1'b0;
Shift_Counter <= Shift_Counter + 1'b1;
end
else begin
HV_SW_LE <= 1'b1;
HV_SW_CLK <= 1'b0;
HV_SW_CLR <= 1'b0;
end
end
end
end
reg [7:0] R_SEQ_Addr;
always @(*) begin
if(Focus_Num == 2'b00) //20mm
R_SEQ_Addr <={1'b0,Line_Num[7:1]};
else if(Focus_Num == 2'b01) //40mm
R_SEQ_Addr <={1'b0,Line_Num[7:1]};
else if(Focus_Num == 2'b11) //80mm //inner 16ch
R_SEQ_Addr <={1'b0,Line_Num[7:1]};
else if(Focus_Num == 2'b10) //80mm //outside 16ch
R_SEQ_Addr <={1'b1,Line_Num[7:1]}; // Receive outside 16CH
end
wire [127:0] SEQ_value; //SEQ & FOLD
R_SEQ R_SEQ_inst (
.address (R_SEQ_Addr ),
.clock (Transmit_CLK ),
.q (SEQ_value )
);
reg [7:0] SEL_Counter;
reg [2:0] ST_Counter; //10MHz
reg [127:0] Shift_SEQ;
reg [3:0] AX_Decode;
always @(*) //correspond mt8816
begin
case(SEL_Counter[6:3])
4'b0000:
AX_Decode <= 4'b0000;
4'b0001:
AX_Decode <= 4'b0001;
4'b0010:
AX_Decode <= 4'b0010;
4'b0011:
AX_Decode <= 4'b0011;
4'b0100:
AX_Decode <= 4'b0100;
4'b0101:
AX_Decode <= 4'b0101;
4'b0110:
AX_Decode <= 4'b1000;
4'b0111:
AX_Decode <= 4'b1001;
4'b1000:
AX_Decode <= 4'b1010;
4'b1001:
AX_Decode <= 4'b1011;
4'b1010:
AX_Decode <= 4'b1100;
4'b1011:
AX_Decode <= 4'b1101;
4'b1100:
AX_Decode <= 4'b0110;
4'b1101:
AX_Decode <= 4'b0111;
4'b1110:
AX_Decode <= 4'b1110;
4'b1111:
AX_Decode <= 4'b1111;
endcase
end
always @(posedge Transmit_CLK or negedge Pr_Gate)
begin
if(~Pr_Gate)
begin
MT_CS <= 1'b0;
MT_Strobe <= 1'b0;
MT_Data <= 1'b0;
SEL_Counter <= 8'd0;
ST_Counter <= 4'd0;
Shift_SEQ <= SEQ_value;
end
else
begin
if(SEL_Counter <8'd128)
begin
MT_CS <= 1'b1;
if(ST_Counter <=3'd1)
begin //set Address,attention: Address and Data can't set at the same time
MT_Strobe <= 1'b0;
AX[3:0] <= AX_Decode[3:0];
AY[2:0] <= SEL_Counter[2:0];
ST_Counter <= ST_Counter + 1'b1;
end
else if(ST_Counter <=3'd2)
begin //set up strobe
MT_Strobe <= 1'b1;
ST_Counter <= ST_Counter + 1'b1;
end
else if(ST_Counter <=3'd3)
begin //shift the value
MT_Data <= Shift_SEQ[127];
MT_Strobe <= 1'b1;
ST_Counter <= ST_Counter + 1'b1;
end
else if(ST_Counter <=3'd4)
begin //shift data
MT_Strobe <= 1'b1;
ST_Counter <= ST_Counter + 1'b1;
Shift_SEQ <= Shift_SEQ <<1;
end
else if(ST_Counter <=3'd5)
begin //wait
MT_Strobe <= 1'b1;
ST_Counter <= ST_Counter + 1'b1;
end
else if(ST_Counter <=3'd6)
begin // set next shift counter
MT_Strobe <= 1'b0;
ST_Counter <= ST_Counter + 1'b1;
SEL_Counter <= SEL_Counter + 1'b1;
end
else if(ST_Counter <=3'd7)
begin //End
MT_Strobe <= 1'b0;
MT_Data <= 1'b0;
ST_Counter <= ST_Counter + 1'b1;
end
end
else
begin
MT_Strobe <= 1'b0;
MT_CS <= 1'b0;
MT_Data <= 1'b0;
end
end
end
endmodule
|
`include "bsg_defines.v"
`include "config_defs.v"
module config_node_bind
#(parameter // node specific parameters
id_p = -1, // unique ID of this node
data_bits_p = -1) // number of bits of configurable register associated with this node
(input clk, // this reflects the destiniation domain clock
input [data_bits_p - 1 : 0] data_o);
logic [data_bits_p - 1 : 0] data_o_r, data_o_n;
logic [data_bits_p - 1 : 0] data_o_ref;
integer probe_file;
integer rt, ch;
integer test_idx = 0;
integer node_id = -1;
integer test_sets = -1;
integer node_id_found = 0;
integer restart_pos; // start position of valid probe reference
integer errors = 0;
initial
begin: initial_open_file
if ($test$plusargs("config-node-bind")) begin
probe_file = $fopen("config_probe.in", "r"); // open config_probe.in file to read
end else begin
probe_file = 0;
end
if (!probe_file) begin
disable initial_open_file;
end
data_o_ref = '0; // just to get rid of Lint warning about never assigning to this variable
ch = $fgetc(probe_file);
while(ch != -1) begin // end of file
if (ch == "#") begin // comments
rt = $ungetc(ch, probe_file);
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(probe_file);
end
end else if (ch == "c") begin // a line giving config_node id
rt = $ungetc(ch, probe_file);
rt = $fscanf(probe_file, "config id: %d\n", node_id);
if (node_id == id_p) begin // found relevant reference data
node_id_found = 1;
rt = $fscanf(probe_file, "test sets: %d\n", test_sets); // a line giving number of test sets for a config_node with that id
restart_pos = $ftell(probe_file); // bookmark the probe_file position
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // a line giving a reference configuration string in binary
break; // to be continued from here
end else begin // invalid patterns
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(probe_file);
end
end
end else begin
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(probe_file);
end
end
ch = $fgetc(probe_file);
end
end
assign data_o_n = data_o;
always @ (posedge clk) begin
data_o_r <= data_o_n;
end
// Since the design is synchronized to posedge of clk, using negedge clk
// here is to allow all flip-flops become stable in the register connected
// to data_o. This might guarantee simulation correct even at gate level,
// when all flip-flops don't necessarily change at the same time.
always @ (negedge clk)
begin: always_check_change
if (probe_file && (node_id_found == 1)) begin
if(test_idx == 0) begin
if (data_o === data_o_ref) begin
$display("\n @time %0d: \t output data_o_%0d\t reset to %b", $time, id_p, data_o);
test_idx += 1;
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // read next reference value
end
end else begin
if (data_o !== data_o_r) begin
$display("\n @time %0d: \t output data_o_%0d\t changed to %b", $time, id_p, data_o);
if (data_o !== data_o_ref) begin
$display("\n @time %0d: \t ERROR output data_o_%0d = %b <-> expected = %b", $time, id_p, data_o, data_o_ref);
errors += 1;
end
test_idx += 1;
if (test_idx == test_sets) begin
if ($test$plusargs("cyclic-test")) begin
rt = $fseek(probe_file, restart_pos, 0); // circulate
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // read next reference value
test_idx = 0;
end
end else begin
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // read next reference value
end
end
end
end else begin // probe_file doesn't exist
disable always_check_change;
end
end
final
begin: final_statistics
if (probe_file) begin
if (node_id_found == 1) begin
if (errors != 0) begin
$display("### FAILED: Config node %5d has received at least %0d wrong packet(s)!\n", id_p, errors);
end else begin
$display("### PASSED: Config node %5d is probably working properly.\n", id_p);
end
if (!$test$plusargs("cyclic-test")) begin
if(test_idx == 0) begin
$display("### FAILED: Config node %5d has not reset properly!\n", id_p);
end else if (test_idx < test_sets) begin
$display("### FAILED: Config node %5d has missed at least %0d packet(s)!\n", id_p, test_sets - test_idx);
end else if (test_idx > test_sets) begin
$display("### FAILED: Config node %5d has received at least %0d more packet(s)!\n", id_p, test_idx - test_sets);
end
end
end else begin // config_node having id_p is instantiated but not listed in the probe_file
$display("### WARNING: Config node %5d is detected in design but not listed in the probe file.\n", id_p);
end
$fclose(probe_file);
end else begin
disable final_statistics;
end
end
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/jp.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Joypad controller block.
***************************************************************************************************/
module jp(
input clk, // 100MHz system clock signal
input rst, // reset signal
input i_wr, // i_write enable signal
input [15:0] i_addr, // 16-bit memory i_address
input i_din, // data input bus
output reg [7:0] o_dout, // data output bus
input [7:0] i_jp1_state, //state of the joy pad 1
input [7:0] i_jp2_state //state of the joy pad 2
);
//Local Parameters
localparam [15:0] JOYPAD1_MMR_ADDR = 16'h4016;
localparam [15:0] JOYPAD2_MMR_ADDR = 16'h4017;
//Registers/Wires
reg [15:0] r_prev_addr;
wire w_new_addr;
reg r_wrote_1_flag;
reg [8:0] r_jp1_state;
reg [8:0] r_jp2_state;
//Submodules
//Asynchronous Logic
assign w_new_addr = (r_prev_addr != i_addr);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_dout <= 0;
r_prev_addr <= 0;
r_wrote_1_flag <= 0;
r_jp1_state <= 0;
r_jp2_state <= 0;
end
else begin
//Only process a command when i_address changes from not this i_address to this i_address
if (i_addr[15:1] == JOYPAD1_MMR_ADDR[15:1]) begin
//User has accessed the joypad register(s), depeni_ding on the last
//bit send the appropriate joystick information (1 or 2)
o_dout <= { 7'h00, ((i_addr[0]) ? r_jp2_state[0] : r_jp1_state[0]) };
if (w_new_addr) begin
if (i_wr && !i_addr[0]) begin
if (!r_wrote_1_flag) begin
if (i_din == 1'b1) begin
r_wrote_1_flag <= 1;
end
end
else begin
if (i_din == 1'b0) begin
r_wrote_1_flag <= 0;
r_jp1_state <= {i_jp1_state, 1'b0};
r_jp2_state <= {i_jp2_state, 1'b0};
end
end
end
//Shift appropriate JP read state on every read, after 8 reads, all subsequent reads should be 1
else if (!i_wr && !i_addr[0]) begin
r_jp1_state <= {1'b1, r_jp1_state[8:1]};
end
else if (!i_wr && i_addr[0]) begin
r_jp2_state <= {1'b1, r_jp2_state[8:1]};
end
end
end
r_prev_addr <= i_addr;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
////////////////////////////////////////////////////////////////////////////////
//
// Module Common Reset CBCC
// Generated by Xilinx Aurora 64B66B
`timescale 1 ps / 1 ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings="yes" *)
//***********************************Entity Declaration*******************************
module aurora_64b66b_25p4G_common_reset_cbcc
(
input enchansync,
input chan_bond_reset,
input reset,
input rd_clk,
input init_clk,
input cb_bit_err,
input user_clk,
output reg cbcc_fifo_reset_wr_clk,
output cbcc_fifo_reset_to_fifo_wr_clk,
output reg cbcc_data_srst = 1'b0,
output reg cbcc_fifo_reset_rd_clk,
output cbcc_fifo_reset_to_fifo_rd_clk,
output cbcc_only_reset_rd_clk,
(* shift_extract = "{no}" *) output reg cbcc_reset_cbstg2_rd_clk
);
//---- cbcc_only_reset_rd_clk ---{
aurora_64b66b_25p4G_rst_sync u_rst_sync_cbcc_only_reset_rd_clk
(
.prmry_in ( reset ),
.scndry_aclk ( rd_clk ),
.scndry_out ( cbcc_only_reset_rd_clk )
);
//---- cbcc_only_reset_rd_clk ---}
//-------------- Wire declaration----------------------------
wire fifo_reset_wr_sync3;
wire fifo_reset_comb;
(* shift_extract = "{no}" *) wire fifo_reset_comb_user_clk;
(* shift_extract = "{no}" *) wire fifo_reset_comb_read_clk;
//-------------- Register declaration----------------------------
reg fifo_reset_rd = 1'b1;
(* shift_extract = "{no}" *) reg reset_cbcc_comb = 1'b1;
(* shift_extract = "{no}" *) reg cbc_wr_if_reset = 1'b1;
wire chan_bond_reset_r2;
reg [3:0] cb_bit_err_ext_cnt; //used for pulse extension to avoid drc violations on fifo
//*********************************Main Body of Code***************************
//----- reset_cbcc_comb ----{
// Double synchronize CHAN_BOND_RESET to account for domain crossing.
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (5) // Number of sync stages needed
) u_cdc_chan_bond_reset
(
.prmry_aclk (1'b0),
.prmry_rst_n (1'b1 ),
.prmry_in (chan_bond_reset),
.prmry_vect_in ('d0 ),
.scndry_aclk (user_clk ),
.scndry_rst_n (1'b1 ),
.prmry_ack ( ),
.scndry_out (chan_bond_reset_r2),
.scndry_vect_out ( )
);
always @(posedge user_clk)
begin
if(reset)
cb_bit_err_ext_cnt <= `DLY 4'd0;
else if(cb_bit_err)
cb_bit_err_ext_cnt <= `DLY 4'b1111;
else if(cb_bit_err_ext_cnt == 4'd0)
cb_bit_err_ext_cnt <= `DLY 4'd0;
else
cb_bit_err_ext_cnt <= `DLY cb_bit_err_ext_cnt - 1'b1;
end
always @(posedge user_clk)
begin
if(reset)
reset_cbcc_comb <= `DLY 1'b1;
else if(chan_bond_reset_r2)
reset_cbcc_comb <= `DLY 1'b1;
else if(cb_bit_err_ext_cnt != 4'd0)
reset_cbcc_comb <= `DLY 1'b1;
else
reset_cbcc_comb <= `DLY 1'b0;
end
//----- reset_cbcc_comb ----}
//---- cbcc_reset_cbstg2_rd_clk ---{
wire rst_cbcc_comb_rd_clk;
aurora_64b66b_25p4G_rst_sync u_rst_sync_rst_cbcc_rd_clk
(
.prmry_in ( reset_cbcc_comb ),
.scndry_aclk ( rd_clk ),
.scndry_out ( rst_cbcc_comb_rd_clk )
);
(* shift_extract = "{no}" *) reg rd_stg1 = 1'b1;
always @(posedge rd_clk)
begin
if(rst_cbcc_comb_rd_clk)
begin
rd_stg1 <= `DLY 1'b1;
cbcc_reset_cbstg2_rd_clk <= `DLY 1'b1;
end
else
begin
rd_stg1 <= `DLY rst_cbcc_comb_rd_clk;
cbcc_reset_cbstg2_rd_clk <= `DLY rd_stg1;
end
end
//---- cbcc_reset_cbstg2_rd_clk ---}
//----- fifo_reset_comb ----{
always @(posedge rd_clk)
begin
if(cbcc_reset_cbstg2_rd_clk)
fifo_reset_rd <= `DLY 1'b1;
else if(enchansync)
fifo_reset_rd <= `DLY 1'b0;
end
aurora_64b66b_25p4G_rst_sync u_rst_sync_r_sync3
(
.prmry_in ( fifo_reset_rd ),
.scndry_aclk ( user_clk ),
.scndry_out ( fifo_reset_wr_sync3 )
);
assign fifo_reset_comb = fifo_reset_wr_sync3 | reset_cbcc_comb;
//----- fifo_reset_comb ----}
//---- fifo_reset_comb_user_clk fifo_reset_comb_read_clk ---{
//below signal will go to fifo_reset_i generation , wr domain as well as rd domain logic
//--- emulating 9 stages for fifo_reset_comb_user_clk from fifo_reset_comb to account for data path delays
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (11)
)u_rst_sync_fifo_reset_user_clk
(
.prmry_in (fifo_reset_comb),
.scndry_aclk (user_clk ),
.scndry_out (fifo_reset_comb_user_clk)
);
aurora_64b66b_25p4G_rst_sync u_rst_sync_cbcc_fifo_reset_rd_clk
(
.prmry_in (fifo_reset_comb_user_clk),
.scndry_aclk (rd_clk),
.scndry_out (fifo_reset_comb_read_clk)
);
//---- fifo_reset_comb_user_clk fifo_reset_comb_read_clk ---}
//---- cbcc_fifo_reset_to_fifo_wr_clk ----{
wire fifo_reset_comb_user_clk_int;
reg fifo_reset_comb_user_clk_int_22q =1'b1;
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (21)
) u_rst_sync_fifo_reset_comb_user_clk_in
(
.prmry_in (fifo_reset_comb_user_clk),
.scndry_aclk (user_clk),
.scndry_out (fifo_reset_comb_user_clk_int)
);
always @(posedge user_clk)
begin
fifo_reset_comb_user_clk_int_22q <= `DLY fifo_reset_comb_user_clk_int;
end
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (9)
) u_rst_sync_reset_to_fifo_wr_clk
(
.prmry_in (fifo_reset_comb_user_clk_int_22q),
.scndry_aclk (user_clk),
.scndry_out (cbcc_fifo_reset_to_fifo_wr_clk)
);
reg dbg_srst_assert = 1'b0;
always @(posedge user_clk)
begin
dbg_srst_assert <= `DLY (fifo_reset_comb_user_clk_int_22q && !(fifo_reset_comb_user_clk_int));
end
localparam dbg_srst_high_period = 4'd11;
reg [3:0] dbg_extend_srst = 4'd11;
always @(posedge user_clk)
begin
if(dbg_srst_assert)
dbg_extend_srst <= `DLY 4'd0;
else if(dbg_extend_srst < dbg_srst_high_period)
dbg_extend_srst <= `DLY dbg_extend_srst + 1'b1;
end
always @(posedge user_clk)
begin
cbcc_data_srst <= `DLY dbg_srst_assert || (dbg_extend_srst < dbg_srst_high_period);
end
//---- cbcc_fifo_reset_to_fifo_wr_clk ----}
//---- cbcc_fifo_reset_to_fifo_rd_clk ----{
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (31)
) u_rst_sync_reset_to_fifo_rd_clk
(
.prmry_in (fifo_reset_comb_read_clk),
.scndry_aclk (rd_clk),
.scndry_out (cbcc_fifo_reset_to_fifo_rd_clk)
);
//---- cbcc_fifo_reset_to_fifo_rd_clk ----}
//---- cbcc_fifo_reset_wr_clk ---{
wire cbcc_fifo_reset_wr_clk_pre;
(* shift_extract = "{no}" *) reg cbcc_fifo_reset_to_fifo_wr_clk_dlyd = 1'b1;
always @(posedge user_clk)
begin
cbcc_fifo_reset_to_fifo_wr_clk_dlyd <= `DLY cbcc_fifo_reset_to_fifo_wr_clk;
end
always @(posedge user_clk)
begin
if(fifo_reset_comb_user_clk)
cbc_wr_if_reset <= 1'b1;
else if(!cbcc_fifo_reset_to_fifo_wr_clk & cbcc_fifo_reset_to_fifo_wr_clk_dlyd)
cbc_wr_if_reset <= 1'b0;
end
aurora_64b66b_25p4G_rst_sync u_rst_sync_reset_wr_clk
(
.prmry_in (cbc_wr_if_reset),
.scndry_aclk (user_clk),
.scndry_out (cbcc_fifo_reset_wr_clk_pre)
);
always @(posedge user_clk)
cbcc_fifo_reset_wr_clk <= `DLY cbcc_fifo_reset_wr_clk_pre;
//---- cbcc_fifo_reset_wr_clk ---}
//---- cbcc_fifo_reset_rd_clk ---{
wire cbcc_fifo_reset_rd_clk_pre;
(* shift_extract = "{no}" *) reg cbc_rd_if_reset = 1'b1;
(* shift_extract = "{no}" *) reg cbcc_fifo_reset_to_fifo_rd_clk_dlyd = 1'b1;
always @(posedge rd_clk)
begin
cbcc_fifo_reset_to_fifo_rd_clk_dlyd <= `DLY cbcc_fifo_reset_to_fifo_rd_clk;
end
always @(posedge rd_clk)
begin
if(fifo_reset_comb_read_clk)
cbc_rd_if_reset <= 1'b1;
else if(!cbcc_fifo_reset_to_fifo_rd_clk & cbcc_fifo_reset_to_fifo_rd_clk_dlyd)
cbc_rd_if_reset <= 1'b0;
end
aurora_64b66b_25p4G_rst_sync u_rst_sync_reset_rd_clk
(
.prmry_in (cbc_rd_if_reset),
.scndry_aclk (rd_clk),
.scndry_out (cbcc_fifo_reset_rd_clk_pre)
);
always @(posedge rd_clk)
cbcc_fifo_reset_rd_clk <= `DLY cbcc_fifo_reset_rd_clk_pre;
//---- cbcc_fifo_reset_rd_clk ---}
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_1_V
`define SKY130_FD_SC_HDLL__SDFBBP_1_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_1_V
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2006-2008 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
module rs232out
(// Control
input wire clock,
// Serial line
output wire serial_out,
input wire [7:0] transmit_data,
input wire we,
output wire busy);
parameter bps = 0;
parameter frequency = 0;
`ifndef __ICARUS__
parameter period = (frequency + bps/2) / bps;
`else
// One of the very few simulation artifacts we have to deal with at the source level.
parameter period = 0;
`endif
parameter TTYCLK_SIGN = 16; // 2^TTYCLK_SIGN > period * 2
parameter COUNT_SIGN = 4;
reg [TTYCLK_SIGN:0] ttyclk = 0; // [-4096; 4095]
wire [31:0] ttyclk_bit = period - 2;
reg [8:0] shift_out = 0;
reg [COUNT_SIGN:0] count = 0; // [-16; 15]
assign serial_out = shift_out[0];
assign busy = ~count[COUNT_SIGN] | ~ttyclk[TTYCLK_SIGN];
always @(posedge clock)
if (~ttyclk[TTYCLK_SIGN]) begin
ttyclk <= ttyclk - 1'd1;
end else if (~count[COUNT_SIGN]) begin
ttyclk <= ttyclk_bit[TTYCLK_SIGN:0];
count <= count - 1'd1;
shift_out <= {1'b1, shift_out[8:1]};
end else if (we) begin
ttyclk <= ttyclk_bit[TTYCLK_SIGN:0];
count <= 9; // 1 start bit + 8 data + 1 stop - 1 due to SIGN trick
shift_out <= {transmit_data, 1'b0};
end
endmodule
|
module elink(/*AUTOARG*/
// Outputs
rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, e_chipid, elink_en, rxwr_access,
rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
txwr_wait, txrd_wait, txrr_wait, mailbox_not_empty, mailbox_full,
timeout,
// Inputs
reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk,
rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait,
txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access,
txrr_packet
);
parameter AW = 32; //native address width
parameter DW = 32; //native data width
parameter PW = 104; //packet width
parameter ID = 12'h810; //epiphany ID for elink (ie addr[31:20])
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
/****************************/
/*CLOCK AND RESET */
/****************************/
input reset; // hardware reset
input sys_clk; // a single system clock for master/slave FIFOs
input tx_lclk; // fast tx clock for IO
input tx_lclk90; // fast 90deg shifted lclk
input tx_lclk_div4; // slow tx clock for core logic
input rx_lclk; // rx input clock tweaked by pll for IO
input rx_lclk_div4; // slow clock for rx logic
output rx_lclk_pll; // rx_lclk pass through input for pll
/********************************/
/*ELINK RECEIVER */
/********************************/
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
/********************************/
/*ELINK TRANSMITTER */
/********************************/
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback input
input txi_rd_wait_p,txi_rd_wait_n; // tx read pushback input
/*************************************/
/*EPIPHANY MISC INTERFACE (I/O PINS) */
/*************************************/
output [11:0] e_chipid; // chip id strap pins for epiphany
output elink_en; // master enable (reset) for elink/epiphany
/*****************************/
/*MAILBOX INTERRUPTS */
/*****************************/
output mailbox_not_empty;
output mailbox_full;
/*****************************/
/*READBACK TIMEOUT (TBD) */
/*****************************/
output timeout;
/*****************************/
/*SYSTEM SIDE INTERFACE */
/*****************************/
//Master Write (from RX)
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//Master Read Request (from RX)
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//Slave Read Response (from RX)
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//Slave Write (to TX)
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Slave Read Request (to TX)
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Master Read Response (to TX)
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
/*#############################################*/
/* END OF BLOCK INTERFACE */
/*#############################################*/
/*AUTOINPUT*/
//wire
wire erx_cfg_access; // To erx of erx.v
wire [PW-1:0] erx_cfg_packet; // To erx of erx.v
wire etx_cfg_wait; // To etx of etx.v
wire [31:0] mi_rd_data;
wire [31:0] mi_dout_ecfg;
wire [31:0] mi_dout_embox;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] clk_config; // From ecfg_elink of ecfg_elink.v
wire erx_cfg_wait; // From erx of erx.v
wire erx_reset; // From ereset of ereset.v
wire etx_cfg_access; // From etx of etx.v
wire [PW-1:0] etx_cfg_packet; // From etx of etx.v
wire etx_reset; // From ereset of ereset.v
wire sys_reset; // From ereset of ereset.v
wire txwr_gated_access; // From ecfg_elink of ecfg_elink.v
wire etx90_reset;
wire erx_ioreset;
// End of automatics
/***********************************************************/
/*CLOCK AND RESET CONFIG */
/***********************************************************/
defparam ecfg_elink.ID=ID;
ecfg_elink ecfg_elink (.clk (sys_clk),
/*AUTOINST*/
// Outputs
.txwr_gated_access (txwr_gated_access),
.elink_en (elink_en),
.clk_config (clk_config[15:0]),
.e_chipid (e_chipid[11:0]),
// Inputs
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.reset (reset));
/***********************************************************/
/*RESET CIRCUITRY */
/***********************************************************/
//Synchronize with each clock domain
ereset ereset (
/*AUTOINST*/
// Outputs
.etx_reset (etx_reset),
.erx_reset (erx_reset),
.sys_reset (sys_reset),
.etx90_reset (etx90_reset),
.erx_ioreset(erx_ioreset),
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.tx_lclk90(tx_lclk90),
.rx_lclk(rx_lclk),
.tx_lclk_div4 (tx_lclk_div4),
.rx_lclk_div4 (rx_lclk_div4));
/***********************************************************/
/*RECEIVER */
/***********************************************************/
/*erx AUTO_TEMPLATE (
.mi_dout (mi_rx_dout[]),
.reset (erx_reset),
);
*/
defparam erx.ID = ID;
defparam erx.IOSTD_ELINK = IOSTD_ELINK;
defparam erx.ETYPE = ETYPE;
erx erx(
/*AUTOINST*/
// Outputs
.rx_lclk_pll (rx_lclk_pll),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.erx_cfg_wait (erx_cfg_wait),
.timeout (timeout),
.mailbox_full (mailbox_full),
.mailbox_not_empty (mailbox_not_empty),
// Inputs
.erx_reset (erx_reset),
.erx_ioreset (erx_ioreset),
.sys_reset (sys_reset),
.sys_clk (sys_clk),
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
.erx_cfg_access (erx_cfg_access),
.erx_cfg_packet (erx_cfg_packet[PW-1:0]));
/***********************************************************/
/*TRANSMITTER */
/***********************************************************/
/*etx AUTO_TEMPLATE (.mi_dout (mi_tx_dout[]),
.emwr_\(.*\) (esaxi_emwr_\1[]),
.emrq_\(.*\) (esaxi_emrq_\1[]),
.emrr_\(.*\) (emaxi_emrr_\1[]),
.reset (etx_reset),
);
*/
defparam etx.ID = ID;
defparam etx.IOSTD_ELINK = IOSTD_ELINK;
defparam etx.ETYPE = ETYPE;
etx etx(.txwr_access (txwr_gated_access),
/*AUTOINST*/
// Outputs
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.txrd_wait (txrd_wait),
.txwr_wait (txwr_wait),
.txrr_wait (txrr_wait),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
// Inputs
.etx90_reset (etx90_reset),
.etx_reset (etx_reset),
.sys_reset (sys_reset),
.sys_clk (sys_clk),
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait));
/***********************************************************/
/*TX-->RX REGISTER INTERFACE CONNECTION */
/***********************************************************/
defparam ecfg_cdc.DW=104;
defparam ecfg_cdc.DEPTH=32;
fifo_cdc ecfg_cdc (// Outputs
.wait_out (etx_cfg_wait),
.access_out (erx_cfg_access),
.packet_out (erx_cfg_packet[PW-1:0]),
// Inputs
.clk_in (tx_lclk_div4),
.reset_in (etx_reset),
.access_in (etx_cfg_access),
.packet_in (etx_cfg_packet[PW-1:0]),
.clk_out (rx_lclk_div4),
.reset_out (erx_reset),
.wait_in (erx_cfg_wait)
);
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../erx/hdl" "../../etx/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_TX_ENGINE.v
// Version : 1.11
//-- Description: Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_TX_ENGINE #(
// RX/TX interface data width
parameter C_DATA_WIDTH = 64,
parameter TCQ = 1,
// TSTRB width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8
)(
input clk,
input rst_n,
// AXIS
input s_axis_tx_tready,
output reg [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output reg [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output reg s_axis_tx_tlast,
output reg s_axis_tx_tvalid,
output tx_src_dsc,
input req_compl,
input req_compl_wd,
output reg compl_done,
input [2:0] req_tc,
input req_td,
input req_ep,
input [1:0] req_attr,
input [9:0] req_len,
input [15:0] req_rid,
input [7:0] req_tag,
input [7:0] req_be,
input [12:0] req_addr,
output [10:0] rd_addr,
output reg [3:0] rd_be,
input [31:0] rd_data,
input [15:0] completer_id
);
localparam PIO_CPLD_FMT_TYPE = 7'b10_01010;
localparam PIO_CPL_FMT_TYPE = 7'b00_01010;
localparam PIO_TX_RST_STATE = 1'b0;
localparam PIO_TX_CPLD_QW1 = 1'b1;
// Local registers
reg [11:0] byte_count;
reg [6:0] lower_addr;
reg req_compl_q;
reg req_compl_wd_q;
// Local wires
wire compl_wd;
// Unused discontinue
assign tx_src_dsc = 1'b0;
// Present address and byte enable to memory module
assign rd_addr = req_addr[12:2];
always @(posedge clk) begin
if (!rst_n)
begin
rd_be <= #TCQ 0;
end else begin
rd_be <= #TCQ req_be[3:0];
end
end
// Calculate byte count based on byte enable
always @ (rd_be) begin
casex (rd_be[3:0])
4'b1xx1 : byte_count = 12'h004;
4'b01x1 : byte_count = 12'h003;
4'b1x10 : byte_count = 12'h003;
4'b0011 : byte_count = 12'h002;
4'b0110 : byte_count = 12'h002;
4'b1100 : byte_count = 12'h002;
4'b0001 : byte_count = 12'h001;
4'b0010 : byte_count = 12'h001;
4'b0100 : byte_count = 12'h001;
4'b1000 : byte_count = 12'h001;
4'b0000 : byte_count = 12'h001;
endcase
end
always @ ( posedge clk ) begin
if (!rst_n )
begin
req_compl_q <= #TCQ 1'b0;
req_compl_wd_q <= #TCQ 1'b1;
end // if !rst_n
else
begin
req_compl_q <= #TCQ req_compl;
req_compl_wd_q <= #TCQ req_compl_wd;
end // if rst_n
end
// generate
// if (C_DATA_WIDTH == 128) begin : init_128
//
// reg req_compl_q2;
// reg req_compl_wd_q2;
//
// always @ ( posedge clk ) begin
// if (!rst_n )
// begin
// req_compl_q2 <= #TCQ 1'b0;
// req_compl_wd_q2 <= #TCQ 1'b0;
// end // if (!rst_n )
// else
// begin
// req_compl_q2 <= #TCQ req_compl_q;
// req_compl_wd_q2 <= #TCQ req_compl_wd_q;
// end // if (rst_n )
// end
// end
// endgenerate
// Calculate lower address based on byte enable
// generate
// if (C_DATA_WIDTH == 64) begin : cd_64
// assign compl_wd = req_compl_wd_q;
// end
// else if (C_DATA_WIDTH == 128) begin : cd_128
// assign compl_wd = req_compl_wd_q2;
// end
// endgenerate
always @ (rd_be or req_addr or compl_wd) begin
casex ({compl_wd, rd_be[3:0]})
5'b1_0000 : lower_addr = {req_addr[6:2], 2'b00};
5'b1_xxx1 : lower_addr = {req_addr[6:2], 2'b00};
5'b1_xx10 : lower_addr = {req_addr[6:2], 2'b01};
5'b1_x100 : lower_addr = {req_addr[6:2], 2'b10};
5'b1_1000 : lower_addr = {req_addr[6:2], 2'b11};
5'b0_xxxx : lower_addr = 8'h0;
endcase // casex ({compl_wd, rd_be[3:0]})
end
// Generate Completion with 1 DW Payload
generate
if (C_DATA_WIDTH == 64) begin : gen_cpl_64
reg state;
assign compl_wd = req_compl_wd_q;
always @ ( posedge clk ) begin
if (!rst_n )
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
compl_done <= #TCQ 1'b0;
state <= #TCQ PIO_TX_RST_STATE;
end // if (!rst_n )
else
begin
case ( state )
PIO_TX_RST_STATE : begin
if (req_compl_q)
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
completer_id, // 16
{3'b0}, // 3
{1'b0}, // 1
byte_count, // 12
{1'b0}, // 1
(req_compl_wd_q ?
PIO_CPLD_FMT_TYPE :
PIO_CPL_FMT_TYPE), // 7
{1'b0}, // 1
req_tc, // 3
{4'b0}, // 4
req_td, // 1
req_ep, // 1
req_attr, // 2
{2'b0}, // 2
req_len // 10
};
s_axis_tx_tkeep <= #TCQ 8'hFF;
// Wait in this state if the PCIe core does not accept
// the first beat of the packet
if (s_axis_tx_tready)
state <= #TCQ PIO_TX_CPLD_QW1;
else
state <= #TCQ PIO_TX_RST_STATE;
end // if (req_compl_q)
else
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ 64'b0;
s_axis_tx_tkeep <= #TCQ 8'hFF;
compl_done <= #TCQ 1'b0;
state <= #TCQ PIO_TX_RST_STATE;
end // if !(req_compl_q)
end // PIO_TX_RST_STATE
PIO_TX_CPLD_QW1 : begin
if (s_axis_tx_tready)
begin
s_axis_tx_tlast <= #TCQ 1'b1;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
rd_data, // 32
req_rid, // 16
req_tag, // 8
{1'b0}, // 1
lower_addr // 7
};
// Here we select if the packet has data or
// not. The strobe signal will mask data
// when it is not needed. No reason to change
// the data bus.
if (req_compl_wd_q)
s_axis_tx_tkeep <= #TCQ 8'hFF;
else
s_axis_tx_tkeep <= #TCQ 8'h0F;
compl_done <= #TCQ 1'b1;
state <= #TCQ PIO_TX_RST_STATE;
end // if (s_axis_tx_tready)
else
state <= #TCQ PIO_TX_CPLD_QW1;
end // PIO_TX_CPLD_QW1
default : begin
// case default stmt
state <= #TCQ PIO_TX_RST_STATE;
end
endcase
end // if rst_n
end
end
else if (C_DATA_WIDTH == 128) begin : gen_cpl_128
reg hold_state;
reg req_compl_q2;
reg req_compl_wd_q2;
assign compl_wd = req_compl_wd_q2;
always @ ( posedge clk ) begin
if (!rst_n )
begin
req_compl_q2 <= #TCQ 1'b0;
req_compl_wd_q2 <= #TCQ 1'b0;
end // if (!rst_n )
else
begin
req_compl_q2 <= #TCQ req_compl_q;
req_compl_wd_q2 <= #TCQ req_compl_wd_q;
end // if (rst_n )
end
always @ ( posedge clk ) begin
if (!rst_n )
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
compl_done <= #TCQ 1'b0;
hold_state <= #TCQ 1'b0;
end // if !rst_n
else
begin
if (req_compl_q2 | hold_state)
begin
if (s_axis_tx_tready)
begin
s_axis_tx_tlast <= #TCQ 1'b1;
s_axis_tx_tvalid <= #TCQ 1'b1;
s_axis_tx_tdata <= #TCQ { // Bits
rd_data, // 32
req_rid, // 16
req_tag, // 8
{1'b0}, // 1
lower_addr, // 7
completer_id, // 16
{3'b0}, // 3
{1'b0}, // 1
byte_count, // 12
{1'b0}, // 1
(req_compl_wd_q2 ?
PIO_CPLD_FMT_TYPE :
PIO_CPL_FMT_TYPE), // 7
{1'b0}, // 1
req_tc, // 3
{4'b0}, // 4
req_td, // 1
req_ep, // 1
req_attr, // 2
{2'b0}, // 2
req_len // 10
};
// Here we select if the packet has data or
// not. The strobe signal will mask data
// when it is not needed. No reason to change
// the data bus.
if (req_compl_wd_q2)
s_axis_tx_tkeep <= #TCQ 16'hFFFF;
else
s_axis_tx_tkeep <= #TCQ 16'h0FFF;
compl_done <= #TCQ 1'b1;
hold_state <= #TCQ 1'b0;
end // if (s_axis_tx_tready)
else
hold_state <= #TCQ 1'b1;
end // if (req_compl_q2 | hold_state)
else
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
compl_done <= #TCQ 1'b0;
end // if !(req_compl_q2 | hold_state)
end // if rst_n
end
end
endgenerate
endmodule // PIO_TX_ENGINE
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* message_disable = "14320" *) module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8,
REGISTER_OUTPUT = 0
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
localparam BUFFER_REGISTER_OUTPUT = (REGISTER_OUTPUT) ? "CLOCK0" : "UNREGISTERED";
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = BUFFER_REGISTER_OUTPUT,
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// CLK I 1 clock
// RST_N I 1 reset
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTop_HW_Side(CLK,
RST_N);
input CLK;
input RST_N;
// register rg_banner_printed
reg rg_banner_printed;
wire rg_banner_printed$D_IN, rg_banner_printed$EN;
// register rg_console_in_poll
reg [11 : 0] rg_console_in_poll;
wire [11 : 0] rg_console_in_poll$D_IN;
wire rg_console_in_poll$EN;
// ports of submodule mem_model
wire [352 : 0] mem_model$mem_server_request_put;
wire [255 : 0] mem_model$mem_server_response_get;
wire mem_model$EN_mem_server_request_put,
mem_model$EN_mem_server_response_get,
mem_model$RDY_mem_server_request_put,
mem_model$RDY_mem_server_response_get;
// ports of submodule soc_top
wire [352 : 0] soc_top$to_raw_mem_request_get;
wire [255 : 0] soc_top$to_raw_mem_response_put;
wire [63 : 0] soc_top$mv_tohost_value,
soc_top$set_verbosity_logdelay,
soc_top$set_watch_tohost_tohost_addr;
wire [7 : 0] soc_top$get_to_console_get,
soc_top$mv_status,
soc_top$put_from_console_put;
wire [3 : 0] soc_top$set_verbosity_verbosity;
wire soc_top$EN_get_to_console_get,
soc_top$EN_ma_ddr4_ready,
soc_top$EN_put_from_console_put,
soc_top$EN_set_verbosity,
soc_top$EN_set_watch_tohost,
soc_top$EN_to_raw_mem_request_get,
soc_top$EN_to_raw_mem_response_put,
soc_top$RDY_get_to_console_get,
soc_top$RDY_put_from_console_put,
soc_top$RDY_to_raw_mem_request_get,
soc_top$RDY_to_raw_mem_response_put,
soc_top$set_watch_tohost_watch_tohost;
// rule scheduling signals
wire CAN_FIRE_RL_memCnx_ClientServerRequest,
CAN_FIRE_RL_memCnx_ClientServerResponse,
CAN_FIRE_RL_rl_relay_console_in,
CAN_FIRE_RL_rl_relay_console_out,
CAN_FIRE_RL_rl_step0,
CAN_FIRE_RL_rl_terminate,
CAN_FIRE_RL_rl_terminate_tohost,
WILL_FIRE_RL_memCnx_ClientServerRequest,
WILL_FIRE_RL_memCnx_ClientServerResponse,
WILL_FIRE_RL_rl_relay_console_in,
WILL_FIRE_RL_rl_relay_console_out,
WILL_FIRE_RL_rl_step0,
WILL_FIRE_RL_rl_terminate,
WILL_FIRE_RL_rl_terminate_tohost;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h771;
reg [31 : 0] v__h821;
reg [31 : 0] v__h937;
reg [31 : 0] v__h1084;
reg TASK_testplusargs___d12;
reg TASK_testplusargs___d11;
reg TASK_testplusargs___d15;
reg [63 : 0] tohost_addr__h637;
reg [31 : 0] v__h702;
reg [7 : 0] v__h1278;
reg [31 : 0] v__h696;
reg [31 : 0] v__h815;
reg [31 : 0] v__h1078;
reg [31 : 0] v__h765;
reg [31 : 0] v__h931;
// synopsys translate_on
// remaining internal signals
wire [63 : 0] test_num__h980;
// submodule mem_model
mkMem_Model mem_model(.CLK(CLK),
.RST_N(RST_N),
.mem_server_request_put(mem_model$mem_server_request_put),
.EN_mem_server_request_put(mem_model$EN_mem_server_request_put),
.EN_mem_server_response_get(mem_model$EN_mem_server_response_get),
.RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put),
.mem_server_response_get(mem_model$mem_server_response_get),
.RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get));
// submodule soc_top
mkSoC_Top soc_top(.CLK(CLK),
.RST_N(RST_N),
.put_from_console_put(soc_top$put_from_console_put),
.set_verbosity_logdelay(soc_top$set_verbosity_logdelay),
.set_verbosity_verbosity(soc_top$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost),
.to_raw_mem_response_put(soc_top$to_raw_mem_response_put),
.EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get),
.EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put),
.EN_get_to_console_get(soc_top$EN_get_to_console_get),
.EN_put_from_console_put(soc_top$EN_put_from_console_put),
.EN_set_verbosity(soc_top$EN_set_verbosity),
.EN_set_watch_tohost(soc_top$EN_set_watch_tohost),
.EN_ma_ddr4_ready(soc_top$EN_ma_ddr4_ready),
.to_raw_mem_request_get(soc_top$to_raw_mem_request_get),
.RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get),
.RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put),
.get_to_console_get(soc_top$get_to_console_get),
.RDY_get_to_console_get(soc_top$RDY_get_to_console_get),
.RDY_put_from_console_put(soc_top$RDY_put_from_console_put),
.status(),
.RDY_set_verbosity(),
.RDY_set_watch_tohost(),
.mv_tohost_value(soc_top$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(soc_top$mv_status));
// rule RL_rl_terminate
assign CAN_FIRE_RL_rl_terminate = soc_top$mv_status != 8'd0 ;
assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ;
// rule RL_rl_terminate_tohost
assign CAN_FIRE_RL_rl_terminate_tohost = soc_top$mv_tohost_value != 64'd0 ;
assign WILL_FIRE_RL_rl_terminate_tohost = CAN_FIRE_RL_rl_terminate_tohost ;
// rule RL_rl_step0
assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ;
assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ;
// rule RL_rl_relay_console_out
assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
// rule RL_rl_relay_console_in
assign CAN_FIRE_RL_rl_relay_console_in =
rg_console_in_poll != 12'd0 || soc_top$RDY_put_from_console_put ;
assign WILL_FIRE_RL_rl_relay_console_in = CAN_FIRE_RL_rl_relay_console_in ;
// rule RL_memCnx_ClientServerRequest
assign CAN_FIRE_RL_memCnx_ClientServerRequest =
soc_top$RDY_to_raw_mem_request_get &&
mem_model$RDY_mem_server_request_put ;
assign WILL_FIRE_RL_memCnx_ClientServerRequest =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
// rule RL_memCnx_ClientServerResponse
assign CAN_FIRE_RL_memCnx_ClientServerResponse =
soc_top$RDY_to_raw_mem_response_put &&
mem_model$RDY_mem_server_response_get ;
assign WILL_FIRE_RL_memCnx_ClientServerResponse =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// register rg_banner_printed
assign rg_banner_printed$D_IN = 1'd1 ;
assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ;
// register rg_console_in_poll
assign rg_console_in_poll$D_IN = rg_console_in_poll + 12'd1 ;
assign rg_console_in_poll$EN = CAN_FIRE_RL_rl_relay_console_in ;
// submodule mem_model
assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ;
assign mem_model$EN_mem_server_request_put =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign mem_model$EN_mem_server_response_get =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// submodule soc_top
assign soc_top$put_from_console_put = v__h1278 ;
assign soc_top$set_verbosity_logdelay = 64'd0 ;
assign soc_top$set_verbosity_verbosity =
TASK_testplusargs___d11 ?
4'd2 :
(TASK_testplusargs___d12 ? 4'd1 : 4'd0) ;
assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h637 ;
assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ;
assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ;
assign soc_top$EN_to_raw_mem_request_get =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign soc_top$EN_to_raw_mem_response_put =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ;
assign soc_top$EN_put_from_console_put =
WILL_FIRE_RL_rl_relay_console_in &&
rg_console_in_poll == 12'd0 &&
v__h1278 != 8'd0 ;
assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ;
assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ;
assign soc_top$EN_ma_ddr4_ready = CAN_FIRE_RL_rl_step0 ;
// remaining internal signals
assign test_num__h980 = { 1'd0, soc_top$mv_tohost_value[63:1] } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_banner_printed$EN)
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN;
if (rg_console_in_poll$EN)
rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY rg_console_in_poll$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_banner_printed = 1'h0;
rg_console_in_poll = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h771 = $stime;
#0;
end
v__h765 = v__h771 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)",
v__h765,
soc_top$mv_status,
soc_top$mv_status);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h821 = $stime;
#0;
end
v__h815 = v__h821 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$imported_c_end_timing({ 32'd0, v__h815 });
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
$display("****************************************************************");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
begin
v__h937 = $stime;
#0;
end
v__h931 = v__h937 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
$display("%0d: %m:.rl_terminate_tohost: tohost_value is 0x%0h (= 0d%0d)",
v__h931,
soc_top$mv_tohost_value,
soc_top$mv_tohost_value);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost &&
soc_top$mv_tohost_value[63:1] == 63'd0)
$display(" PASS");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost &&
soc_top$mv_tohost_value[63:1] != 63'd0)
$display(" FAIL <test_%0d>", test_num__h980);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
begin
v__h1084 = $stime;
#0;
end
v__h1078 = v__h1084 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
$imported_c_end_timing({ 32'd0, v__h1078 });
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Bluespec RISC-V WindSoC simulation v1.2");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Copyright (c) 2017-2020 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d12 = $test$plusargs("v1");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d11 = $test$plusargs("v2");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d15 = $test$plusargs("tohost");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
tohost_addr__h637 = $imported_c_get_symbol_val("tohost");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h",
TASK_testplusargs___d15,
tohost_addr__h637);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
v__h702 = $stime;
#0;
end
v__h696 = v__h702 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0) $imported_c_start_timing({ 32'd0, v__h696 });
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get)
$write("%c", soc_top$get_to_console_get);
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0)
begin
v__h1278 = $imported_c_trygetchar(8'hAA);
#0;
end
end
// synopsys translate_on
endmodule // mkTop_HW_Side
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_top
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_top.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_top.v,v $
// Revision 1.1 2006/07/10 07:30:08 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_top
//
// No user `defines in this module
module avfb_top
//
// Generated module i_avfb_top
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
// __I_IN_OPEN wire BC_RA_02_fail ; // __W_BAD_BRANCH
wire tc_BC_RA_02_fail;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_cgu
cgu i_avfb_cgu (
);
// End of Generated Instance Port Map for i_avfb_cgu
// Generated Instance Port Map for i_avfb_logic
avfb_logic i_avfb_logic (
);
// End of Generated Instance Port Map for i_avfb_logic
// Generated Instance Port Map for i_avfb_pad_mux
avfb_pad_mux i_avfb_pad_mux (
// __I_RECONN .BC_RA_02_fail_i(),
.BC_RA_02_fail_i(tc_BC_RA_02_fail)
);
// End of Generated Instance Port Map for i_avfb_pad_mux
// Generated Instance Port Map for i_avfb_tc
avfb_tc i_avfb_tc (
.BC_RA_02_fail_o(tc_BC_RA_02_fail)
);
// End of Generated Instance Port Map for i_avfb_tc
endmodule
//
// End of Generated Module rtl of avfb_top
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S6S_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYMETAL6S6S_PP_BLACKBOX_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S6S_PP_BLACKBOX_V
|
/*
* Titor - System - Bank selection manager
* Copyright (C) 2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_BANK_MANAGER
`else
`define INC_BANK_MANAGER
`timescale 1 ns / 100 ps
module BankManager(
dout,
din,
address,
size,
read_write,
enable,
bank,
bank_enable,
reset,
clk
);
`include "definition/Definition.v"
localparam ELEM_VALID = 0;
localparam ELEM_SLOT = 1;
localparam ELEM_LINK = 2;
output reg [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output reg [WORD-1:0] bank;
output reg bank_enable;
input reset;
input clk;
reg valid [NUM_BANK-1:0];
reg [WORD-1:0] slot [NUM_BANK-1:0];
reg [WORD-1:0] link [NUM_BANK-1:0];
reg sel_section [NUM_BANK-1:0];
reg [WORD-1:0] stage;
// under the standard configuration (8 banks and 7 pipeline stages + PC-only stage)
// this initialization is inefficient since one bubble per round can be cut out and only one bank is used
// to get the most efficient bootup set the next-to-last link to point back to 0 and/or enable
// more banks working in multiprocessing mode with trusted code
genvar i;
generate
for(i=0; i<NUM_BANK; i=i+1) begin : GENBANK
always @(posedge clk) begin
if(reset) begin
// for bank 0:
// turn on bank by default to enable bootstrapping
// for other banks:
// leave the other banks off at reset so they don't interfere with bank 0
// until explicitly told to active with bank 0 at the root of that activation chain
valid[i] <= (i==0) ? ENABLE : DISABLE; // enable only 0 by default
slot[i] <= i; // for bank i
link[i] <= (i+1)%NUM_BANK; // point to next slot
end
else begin
if( sel_section[i] && ((address/(WORDBYTE*NUM_BANK))==ELEM_VALID) ) begin
valid[i] <= din;
end
else begin
valid[i] <= valid[i];
end
if( sel_section[i] && ((address/(WORDBYTE*NUM_BANK))==ELEM_SLOT) ) begin
slot[i] <= din;
end
else begin
slot[i] <= slot[i];
end
if( sel_section[i] && ((address/(WORDBYTE*NUM_BANK))==ELEM_LINK) ) begin
link[i] <= din;
end
else begin
link[i] <= link[i];
end
end
end
always @(*) begin
sel_section[i] <= (((address/WORDBYTE)%NUM_BANK)==i) && (read_write==WRITE) && (enable==ENABLE);
end
end
endgenerate
always @(posedge clk) begin
if(reset) begin
stage <= 0;
end
else begin
stage <= link[stage];
end
end
always @(*) begin
bank <= slot[stage];
bank_enable <= valid[stage];
end
endmodule
`endif
|
// Enqueues pixel information and when the Z read
// returns, does a compare and then sends the pixel on to the write FIFO.
module Read_FIFO
#(parameter FIFO_DEPTH=32, FIFO_DEPTH_LOG2=5)
(
// Clock and reset.
input wire clock,
input wire reset_n,
// Module controls.
input wire z_active, // Whether to expect a Z read and to do a comparison.
// Memory interface for reading Z pixels.
input wire [63:0] read_readdata,
input wire read_readdatavalid,
// FIFO controls.
input wire enqueue,
input wire [28:0] color_address,
input wire [63:0] color,
input wire [28:0] z_address,
input wire [63:0] z,
input wire [1:0] pixel_active, // Bit 0 is the left-most pixel.
output wire [FIFO_DEPTH_LOG2-1:0] size,
// Write FIFO controls.
output reg write_enqueue,
output reg [28:0] write_color_address,
output reg [63:0] write_color,
output reg [28:0] write_z_address,
output reg [63:0] write_z,
output reg [1:0] write_pixel_active // Bit 0 is the left-most pixel.
);
/* verilator lint_off WIDTH */
// Latched Z from memory.
reg [63:0] memory_z;
reg [63:0] memory_z_delayed;
// Pack the FIFO data.
wire [187:0] fifo_write_data = {
pixel_active,
z,
z_address,
color,
color_address
};
// Unpack the FIFO data.
wire [187:0] fifo_read_data;
wire [28:0] fifo_color_address = fifo_read_data[28:0];
wire [63:0] fifo_color = fifo_read_data[92:29];
wire [28:0] fifo_z_address = fifo_read_data[121:93];
wire [63:0] fifo_z = fifo_read_data[185:122];
wire [1:0] fifo_pixel_active = fifo_read_data[187:186];
// Unpack pixels.
wire [31:0] fifo_z_0 = fifo_z[31:0];
wire [31:0] fifo_z_1 = fifo_z[63:32];
wire [31:0] memory_z_0 = memory_z_delayed[31:0];
wire [31:0] memory_z_1 = memory_z_delayed[63:32];
// Z computation. Hard-code "less than or equal to" (ZF_LEQUAL).
wire z_pass_0 = fifo_z_0 <= memory_z_0;
wire z_pass_1 = fifo_z_1 <= memory_z_1;
wire [1:0] new_pixel_active = fifo_pixel_active & { z_pass_1, z_pass_0 };
// FIFO implementation.
wire fifo_empty;
/* verilator lint_off UNUSED */
wire fifo_full;
/* verilator lint_on UNUSED */
reg fifo_read;
reg got_fifo_data;
/* verilator lint_off PINMISSING */
scfifo #(.add_ram_output_register("OFF"),
.intended_device_family("CYCLONEV"),
.lpm_numwords(FIFO_DEPTH),
.lpm_showahead("OFF"),
.lpm_type("scfifo"),
.lpm_width(188),
.lpm_widthu(FIFO_DEPTH_LOG2),
.overflow_checking("ON"),
.underflow_checking("ON"),
.use_eab("ON")) fifo(
.aclr(!reset_n),
.clock(clock),
.data(fifo_write_data),
.empty(fifo_empty),
.full(fifo_full),
.usedw(size),
.q(fifo_read_data),
.rdreq(fifo_read),
.wrreq(enqueue));
/* verilator lint_on PINMISSING */
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
fifo_read <= 1'b0;
got_fifo_data <= 1'b0;
write_enqueue <= 1'b0;
memory_z <= 1'b0;
memory_z_delayed <= 1'b0;
end else begin
// If memory has data, or if we don't care about memory (Z is
// off), initiate a queue read.
fifo_read <= !z_active || read_readdatavalid;
// Doesn't hurt to always grab the memory data. At worst we won't
// use it.
memory_z <= read_readdata;
// One clock after the queue read, we know whether the read was
// valid (queue not empty).
got_fifo_data <= fifo_read && !fifo_empty;
// Delay the memory read too.
memory_z_delayed <= memory_z;
// One clock after that, we have access to the queue data (if
// available) and the delayed memory read. Enqueue if Z is
// off, or if either new Z pixel is not behind existing pixel.
write_enqueue <= got_fifo_data && (!z_active || |new_pixel_active);
write_color_address <= fifo_color_address;
write_color <= fifo_color;
write_z_address <= fifo_z_address;
write_z <= fifo_z;
write_pixel_active <= z_active ? new_pixel_active : fifo_pixel_active;
end
end
/* verilator lint_on WIDTH */
endmodule
|
/**********************************************************
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: phy_4lanes.v,v 1.12.10.3 2011/05/30 10:45:54 pboya Exp $
// $Author: pboya $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is the parameterizable 4-byte lane phy primitive top
// This module may be ganged to create an N-lane phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
///////////////////////////////////////////////////////////
**********************************************************/
`timescale 1ps/1ps
`define PC_DATA_OFFSET_RANGE 22:17
module phy_4lanes #(
parameter GENERATE_IDELAYCTRL = "TRUE",
parameter GENERATE_DDR_CK = "B", // choose lane "A", "B", "C" or "D" or for no clock : " " (blank)
parameter NUM_DDR_CK = 1,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter BITLANES = 48'hffff_ffff_ffff,
parameter BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
parameter DIFFERENTIAL_DQS = "TRUE",
parameter RCLK_SELECT_LANE = "B",
parameter MC_DIVIDE = 4,
parameter real TCK = 0.00,
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PO_FINE_DELAY = 0,
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_CLKOUT_DIV = 2,
parameter A_PI_BURST_MODE = "TRUE",
parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter A_PI_FINE_DELAY = 60,
parameter A_PI_SYNC_IN_DIV_RST = "TRUE",
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter C_PI_FINE_DELAY = 0,
parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter D_PI_FINE_DELAY = 0,
parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
//phaser_out parameters
parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? MC_DIVIDE : 2,
parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_COARSE_DELAY = 0,
parameter A_PO_OCLK_DELAY = 0,
parameter A_PO_OCLKDELAY_INV = "FALSE",
parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter A_PO_SYNC_IN_DIV_RST = "TRUE",
//parameter A_PO_SYNC_IN_DIV_RST = "FALSE",
parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? MC_DIVIDE : 2,
parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? MC_DIVIDE : 2,
parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? MC_DIVIDE : 2,
parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter A_IDELAYE2_IDELAY_VALUE = 00,
parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter IODELAY_GRP = "IODELAY_MIG",
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_CLK_RATIO = MC_DIVIDE,
parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "TRUE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
// io fifo parameters
parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
parameter A_OS_DATA_RATE = "DDR",
parameter A_OS_DATA_WIDTH = 4,
parameter B_OS_DATA_RATE = A_OS_DATA_RATE,
parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter C_OS_DATA_RATE = A_OS_DATA_RATE,
parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter D_OS_DATA_RATE = A_OS_DATA_RATE,
parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8",
parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
// this is used locally, not for external pushdown
// NOTE: the 0+ is needed in each to coerce to integer for addition.
// otherwise 4x 1'b values are added producing a 1'b value.
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
// assume odt per rank + any declared cke's
parameter AUXOUT_WIDTH = 4,
parameter LP_DDR_CK_WIDTH = 2
)
(
//`include "phy.vh"
input rst,
input phy_clk,
input phy_ctl_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input phy_ctl_mstr_empty,
input [31:0] phy_ctl_wd,
input [`PC_DATA_OFFSET_RANGE] data_offset,
input phy_ctl_wr,
input if_empty_def,
input input_sink,
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk, // to memory
output rclk,
output if_a_empty,
output if_empty,
output mux_i0,
output mux_i1,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus
output phy_ctl_empty,
output phy_ctl_a_full,
output phy_ctl_full,
output [HIGHEST_LANE*12-1:0]mem_dq_out,
output [HIGHEST_LANE*12-1:0]mem_dq_ts,
input [HIGHEST_LANE*10-1:0]mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
output [AUXOUT_WIDTH-1:0]aux_out,
output reg rst_out = 0,
output reg mcGo,
output phy_ctl_ready,
input phy_read_calib,
input phy_write_calib,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input [2:0] calib_sel,
input calib_zero_ctrl,
input calib_in_common,
output [1:0] phy_encalib,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output reg pi_dqs_out_of_range,
output reg pi_phase_locked,
output pi_phase_locked_all
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];
localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];
localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];
localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE";
localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam IO_A_START = 41;
localparam IO_A_END = 40;
localparam IO_B_START = 43;
localparam IO_B_END = 42;
localparam IO_C_START = 45;
localparam IO_C_END = 44;
localparam IO_D_START = 47;
localparam IO_D_END = 46;
localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;
localparam IO_A_X_END = (IO_A_X_START-1);
localparam IO_B_X_START = (IO_A_X_START + 2);
localparam IO_B_X_END = (IO_B_X_START -1);
localparam IO_C_X_START = (IO_B_X_START + 2);
localparam IO_C_X_END = (IO_C_X_START -1);
localparam IO_D_X_START = (IO_C_X_START + 2);
localparam IO_D_X_END = (IO_D_X_START -1);
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI+ 8;
localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
wire A_pi_dqs_found;
wire A_pi_dqs_out_of_range;
wire A_pi_phase_locked;
wire A_pi_iserdes_rst;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_po_fine_enable;
reg A_po_coarse_enable;
reg A_po_fine_inc;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_rclk;
reg A_idelay_ce;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
wire B_pi_phase_locked;
wire B_pi_iserdes_rst;
wire B_pi_dqs_found;
wire B_pi_dqs_out_of_range;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
reg B_po_fine_enable;
reg B_po_coarse_enable;
reg B_po_fine_inc;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
wire B_rclk;
reg B_idelay_ce;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc;
reg D_po_fine_inc;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_coarse_enable;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_dqs_found;
wire D_pi_dqs_found;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire C_pi_phase_locked;
wire C_pi_iserdes_rst;
wire D_pi_phase_locked;
wire D_pi_iserdes_rst;
wire C_pi_dqs_out_of_range;
wire D_pi_dqs_out_of_range;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_rclk;
wire D_rclk;
reg C_idelay_ce;
reg D_idelay_ce;
wire pi_iserdes_rst;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
wire A_if_full;
wire B_if_full;
wire C_if_full;
wire D_if_full;
wire A_of_empty;
wire B_of_empty;
wire C_of_empty;
wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
wire [NUM_DDR_CK*LP_DDR_CK_WIDTH-1:0] A_ddr_clk; // for generation
wire [NUM_DDR_CK*LP_DDR_CK_WIDTH-1:0] B_ddr_clk; //
wire [NUM_DDR_CK*LP_DDR_CK_WIDTH-11:0] C_ddr_clk; //
wire [NUM_DDR_CK*LP_DDR_CK_WIDTH-11:0] D_ddr_clk; //
wire [31:0] _phy_ctl_wd;
assign pi_dqs_found_any =
( PRESENT_DATA_A & A_pi_dqs_found) |
( PRESENT_DATA_B & B_pi_dqs_found) |
( PRESENT_DATA_C & C_pi_dqs_found) |
( PRESENT_DATA_D & D_pi_dqs_found) ;
assign pi_dqs_found_all =
(! PRESENT_DATA_A | A_pi_dqs_found) &
(! PRESENT_DATA_B | B_pi_dqs_found) &
(! PRESENT_DATA_C | C_pi_dqs_found) &
(! PRESENT_DATA_D | D_pi_dqs_found) ;
assign pi_phase_locked_all =
(! PRESENT_DATA_A | A_pi_phase_locked) &
(! PRESENT_DATA_B | B_pi_phase_locked) &
(! PRESENT_DATA_C | C_pi_phase_locked) &
(! PRESENT_DATA_D | D_pi_phase_locked);
wire dangling_outputs; // this reduces all constant 0 values to 1 signal
// which can be tied to an unused input. The purpose
// is to fake the tools into ignoring dangling outputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign dangling_outputs = ( &phy_dout) ;
assign mux_i0 = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);
assign mux_i1 = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;
assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full ;
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
reg rst_out_trig = 1'b0;
reg [31:0] rclk_delay;
reg rst_edge1 = 1'b0;
reg rst_edge2 = 1'b0;
reg rst_edge3 = 1'b0;
reg rst_edge_detect = 1'b0;
wire rclk_;
reg rst_out_start = 1'b0 ;
reg rst_primitives;
// synthesis attribute MAX_FANOUT of rst_primitives is 10;
`ifdef USE_PHY_CONTROL_TEST
wire [15:0] test_output;
wire [15:0] test_input;
wire [2:0] test_select=0;
wire scan_enable = 0;
`endif
generate
if (RCLK_SELECT_LANE == "A") begin
assign rclk_ = A_rclk;
assign pi_iserdes_rst = A_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "B") begin
assign rclk_ = B_rclk;
assign pi_iserdes_rst = B_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "C") begin
assign rclk_ = C_rclk;
assign pi_iserdes_rst = C_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "D") begin
assign rclk_ = D_rclk;
assign pi_iserdes_rst = D_pi_iserdes_rst;
end
else begin
assign rclk_ = B_rclk; // default
end
if ( GENERATE_DDR_CK == "A")
assign ddr_clk = A_ddr_clk;
if ( GENERATE_DDR_CK == "B")
assign ddr_clk = B_ddr_clk;
if ( GENERATE_DDR_CK == "C")
assign ddr_clk = C_ddr_clk;
if ( GENERATE_DDR_CK == "D")
assign ddr_clk = D_ddr_clk;
// cover case where no clock is desired
if ( GENERATE_DDR_CK != "A" && GENERATE_DDR_CK != "B" && GENERATE_DDR_CK != "C" && GENERATE_DDR_CK != "D") assign ddr_clk = 0;
endgenerate
always @(posedge mem_refclk_div4 or posedge rst) begin
if ( rst == 1) begin
rst_out <= #1 0;
rst_out_start <= #1 0;
rst_out_trig <= #1 0;
rst_edge1 <= #1 1;
rst_edge2 <= #1 0;
rst_edge3 <= #1 0;
rst_edge_detect <= #1 0;
rst_primitives <= #1 1;
mcGo <= #1 0;
end
else begin
rst_edge1 <= #1 rst;
rst_edge2 <= #1 rst_edge1;
rst_edge3 <= #1 rst_edge2;
rst_edge_detect <= #1 rst_edge3 == 1 && rst_edge2 == 0 || rst_edge_detect ;
rst_primitives <= rst_out_start && ! rst_out_trig;
if ( rst_out == 1)
rst_out_start <= #1 0;
else
rst_out_start <= #1 rst_out_start || (rclk_delay[11] === 0 && ! rst_out_trig && rst_edge_detect);
rclk_delay <= #1 (rclk_delay << 1) | (rst_out_start);
mcGo <= #1 rst_out == 1 && ! rst_out_start;
rst_out_trig <= #1 rst_out_trig || rst_out_start ;
if ( rclk_delay[11] === 1)
rst_out <= #1 1;
end
end
generate
if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
end
else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
end
if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
end
else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
end
if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
end
else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
end
if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
end
else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (HIGHEST_LANE > 1)
assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};
if (HIGHEST_LANE == 1)
assign _phy_ctl_wd_ = phy_ctl_wd;
//module BUFR (O, CE, CLR, I);
//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));
BUFIO rclk_buf(.I(rclk_), .O(rclk) );
if ( BYTE_LANES[0] ) begin : byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
byte_lane#(
.ABCD ("A"),
.PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[11:0]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (A_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.DIFFERENTIAL_DQS (DIFFERENTIAL_DQS),
.GENERATE_DDR_CK (GENERATE_DDR_CK),
.NUM_DDR_CK (NUM_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.TCK (TCK),
.MC_DIVIDE (MC_DIVIDE),
.PI_BURST_MODE (A_PI_BURST_MODE),
.PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),
.PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),
.PO_FINE_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),
// .OSERDES_DATA_RATE (A_OS_DATA_RATE),
// .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
byte_lane_A(
.mem_dq_out (mem_dq_out[11:0]),
.mem_dq_ts (mem_dq_ts[11:0]),
.mem_dq_in (mem_dq_in[9:0]),
.mem_dqs_out (mem_dqs_out[0]),
.mem_dqs_ts (mem_dqs_ts[0]),
.mem_dqs_in (mem_dqs_in[0]),
.rst (rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (A_ddr_clk),
.rclk (A_rclk),
.pi_dqs_found (A_pi_dqs_found),
.dqs_out_of_range (A_pi_dqs_out_of_range),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (if_a_full),
.if_full (A_if_full),
.of_a_empty (of_a_empty),
.of_empty (A_of_empty),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (A_idelay_ce),
.idelay_ld (idelay_ld),
.pi_rst_dqs_find (pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.pi_iserdes_rst (A_pi_iserdes_rst),
.pi_phase_locked (A_pi_phase_locked)
);
end
else begin : no_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_if_empty = 1'b0;
assign A_if_a_empty = 1'b0;
assign A_pi_phase_locked = 1;
assign A_pi_dqs_found = 1;
assign A_rclk = 0;
assign A_pi_counter_read_val = 0;
assign A_po_counter_read_val = 0;
assign A_pi_fine_overflow = 0;
assign A_po_coarse_overflow = 0;
assign A_po_fine_overflow = 0;
end
if ( BYTE_LANES[1] ) begin : byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
byte_lane#(
.ABCD ("B"),
.PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[23:12]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (B_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.DIFFERENTIAL_DQS (DIFFERENTIAL_DQS),
.GENERATE_DDR_CK (GENERATE_DDR_CK),
.NUM_DDR_CK (NUM_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.TCK (TCK),
.MC_DIVIDE (MC_DIVIDE),
.PI_BURST_MODE (B_PI_BURST_MODE),
.PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),
.PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),
.PO_FINE_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (B_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
byte_lane_B(
.mem_dq_out (mem_dq_out[23:12]),
.mem_dq_ts (mem_dq_ts[23:12]),
.mem_dq_in (mem_dq_in[19:10]),
.mem_dqs_out (mem_dqs_out[1]),
.mem_dqs_ts (mem_dqs_ts[1]),
.mem_dqs_in (mem_dqs_in[1]),
.rst (rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (B_ddr_clk),
.rclk (B_rclk),
.pi_dqs_found (B_pi_dqs_found),
.dqs_out_of_range (B_pi_dqs_out_of_range),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (B_if_full),
.of_a_empty (/*of_a_empty*/),
.of_empty (B_of_empty),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (B_idelay_ce),
.idelay_ld (idelay_ld),
.pi_rst_dqs_find (pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.pi_iserdes_rst (B_pi_iserdes_rst),
.pi_phase_locked (B_pi_phase_locked)
);
end
else begin : no_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_if_empty = 1'b0;
assign B_if_a_empty = 1'b0;
assign B_pi_phase_locked = 1;
assign B_pi_dqs_found = 1;
assign B_rclk = 0;
assign B_pi_counter_read_val = 0;
assign B_po_counter_read_val = 0;
assign B_pi_fine_overflow = 0;
assign B_po_coarse_overflow = 0;
assign B_po_fine_overflow = 0;
end
if ( BYTE_LANES[2] ) begin : byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
byte_lane#(
.ABCD ("C"),
.PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[35:24]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (C_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.DIFFERENTIAL_DQS (DIFFERENTIAL_DQS),
.GENERATE_DDR_CK (GENERATE_DDR_CK),
.NUM_DDR_CK (NUM_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.TCK (TCK),
.MC_DIVIDE (MC_DIVIDE),
.PI_BURST_MODE (C_PI_BURST_MODE),
.PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),
.PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),
.PO_FINE_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (C_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
byte_lane_C(
.mem_dq_out (mem_dq_out[35:24]),
.mem_dq_ts (mem_dq_ts[35:24]),
.mem_dq_in (mem_dq_in[29:20]),
.mem_dqs_out (mem_dqs_out[2]),
.mem_dqs_ts (mem_dqs_ts[2]),
.mem_dqs_in (mem_dqs_in[2]),
.rst (rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (C_ddr_clk),
.rclk (C_rclk),
.pi_dqs_found (C_pi_dqs_found),
.dqs_out_of_range (C_pi_dqs_out_of_range),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (C_if_full),
.of_a_empty (/*of_a_empty*/),
.of_empty (C_of_empty),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (C_idelay_ce),
.idelay_ld (idelay_ld),
.pi_rst_dqs_find (pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.pi_iserdes_rst (C_pi_iserdes_rst),
.pi_phase_locked (C_pi_phase_locked)
);
end
else begin : no_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_if_empty = 1'b0;
assign C_if_a_empty = 1'b0;
assign C_pi_phase_locked = 1;
assign C_pi_dqs_found = 1;
assign C_rclk = 0;
assign C_pi_counter_read_val = 0;
assign C_po_counter_read_val = 0;
assign C_pi_fine_overflow = 0;
assign C_po_coarse_overflow = 0;
assign C_po_fine_overflow = 0;
end
if ( BYTE_LANES[3] ) begin : byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
byte_lane#(
.ABCD ("D"),
.PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[47:36]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (D_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.DIFFERENTIAL_DQS (DIFFERENTIAL_DQS),
.GENERATE_DDR_CK (GENERATE_DDR_CK),
.NUM_DDR_CK (NUM_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.TCK (TCK),
.MC_DIVIDE (MC_DIVIDE),
.PI_BURST_MODE (D_PI_BURST_MODE),
.PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),
.PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),
.PO_FINE_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (D_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
byte_lane_D(
.mem_dq_out (mem_dq_out[47:36]),
.mem_dq_ts (mem_dq_ts[47:36]),
.mem_dq_in (mem_dq_in[39:30]),
.mem_dqs_out (mem_dqs_out[3]),
.mem_dqs_ts (mem_dqs_ts[3]),
.mem_dqs_in (mem_dqs_in[3]),
.rst (rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (D_ddr_clk),
.rclk (D_rclk),
.pi_dqs_found (D_pi_dqs_found),
.dqs_out_of_range (D_pi_dqs_out_of_range),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (D_if_full),
.of_a_empty (/*of_a_empty*/),
.of_empty (D_of_empty),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_inc (idelay_inc),
.idelay_ce (D_idelay_ce),
.idelay_ld (idelay_ld),
// calibration signals
.pi_rst_dqs_find (pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.pi_iserdes_rst (D_pi_iserdes_rst),
.pi_phase_locked (D_pi_phase_locked)
);
end
else begin : no_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_if_empty = 1'b0;
assign D_if_a_empty = 1'b0;
assign D_rclk = 0;
assign D_pi_dqs_found = 1;
assign D_pi_phase_locked = 1;
assign D_pi_counter_read_val = 0;
assign D_po_counter_read_val = 0;
assign D_pi_fine_overflow = 0;
assign D_po_coarse_overflow = 0;
assign D_po_fine_overflow = 0;
end
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
`ifdef FUJI_PHY_BLH
B_PHY_CONTROL #(
`else
PHY_CONTROL #(
`endif
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
.INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
.INRANKA (in_rank[1:0]),
.INRANKB (in_rank[3:2]),
.INRANKC (in_rank[5:4]),
.INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (_phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock),
.RESET (rst_primitives),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
`ifdef USE_PHY_CONTROL_TEST
, .TESTINPUT (16'b0),
.TESTOUTPUT (test_output),
.TESTSELECT (test_select),
.SCANENABLEN (scan_enable)
`endif
);
// register outputs to give extra slack in timing
always @(posedge phy_clk or posedge rst) begin
if (rst) begin
pi_counter_read_val <= #1 0;
pi_dqs_found <= #1 0;
pi_dqs_out_of_range <= #1 0;
pi_fine_overflow <= #1 0;
pi_phase_locked <= #1 0;
po_coarse_overflow <= #1 0;
po_counter_read_val <= #1 0;
po_fine_overflow <= #1 0;
end
else begin
case (calib_sel[1:0])
2'h0: begin
// TEMP: condition on whether this byte lane is
// control/addr or data. If control/address, then
// hardcode these outputs, and allow SYN/PAR to
// trim out the PHASER_IN in this byte lane
if (! PRESENT_DATA_A) begin
po_coarse_overflow <= #1 1'b0;
po_fine_overflow <= #1 1'b0;
po_counter_read_val <= #1 9'b0;
pi_fine_overflow <= #1 1'b0;
pi_counter_read_val<= #1 6'b0;
pi_phase_locked <= #1 1'b0;
pi_dqs_found <= #1 1'b0;
pi_dqs_out_of_range <= #1 1'b0;
end
else begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val<= #1 A_pi_counter_read_val;
pi_phase_locked <= #1 A_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 A_pi_dqs_found;
pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;
end
end
2'h1: begin
if (! PRESENT_DATA_B) begin
po_coarse_overflow <= #1 1'b0;
po_fine_overflow <= #1 1'b0;
po_counter_read_val <= #1 9'b0;
pi_fine_overflow <= #1 1'b0;
pi_counter_read_val<= #1 6'b0;
pi_phase_locked <= #1 1'b0;
pi_dqs_found <= #1 1'b0;
pi_dqs_out_of_range <= #1 1'b0;
end
else begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
pi_phase_locked <= #1 B_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 B_pi_dqs_found;
pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;
end
end
2'h2: begin
if (! PRESENT_DATA_C) begin
po_coarse_overflow <= #1 1'b0;
po_fine_overflow <= #1 1'b0;
po_counter_read_val <= #1 9'b0;
pi_fine_overflow <= #1 1'b0;
pi_counter_read_val<= #1 6'b0;
pi_phase_locked <= #1 1'b0;
pi_dqs_found <= #1 1'b0;
pi_dqs_out_of_range <= #1 1'b0;
end
else begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
pi_phase_locked <= #1 C_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 C_pi_dqs_found;
pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;
end
end
2'h3: begin
if (! PRESENT_DATA_D) begin
po_coarse_overflow <= #1 1'b0;
po_fine_overflow <= #1 1'b0;
po_counter_read_val <= #1 9'b0;
pi_fine_overflow <= #1 1'b0;
pi_counter_read_val<= #1 6'b0;
pi_phase_locked <= #1 1'b0;
pi_dqs_found <= #1 1'b0;
pi_dqs_out_of_range <= #1 1'b0;
end
else begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
pi_phase_locked <= #1 D_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 D_pi_dqs_found;
pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;
end
end
default: begin
po_coarse_overflow <= po_coarse_overflow;
end
endcase
end
end
always @(*) begin
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
if ( calib_sel[2]) begin
// if this is asserted, all calib signals are deasserted
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_idelay_ce = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val= 0;
B_idelay_ce = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val= 0;
C_idelay_ce = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val= 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_idelay_ce = 0;
end else
if (calib_in_common) begin
// if this is asserted, each signal is broadcast to all phasers
// in common
if ( ! calib_zero_ctrl || DATA_CTL_N[0]) begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
end
if ( ! calib_zero_ctrl || DATA_CTL_N[1]) begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
end
if ( ! calib_zero_ctrl || DATA_CTL_N[2]) begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
end
if ( ! calib_zero_ctrl || DATA_CTL_N[3]) begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_read_en = po_counter_read_en;
D_po_counter_load_val = po_counter_load_val;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
end
end
else begin
// otherwise, only a single phaser is selected
case (calib_sel[1:0])
0: begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_idelay_ce = idelay_ce;
end
1: begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_idelay_ce = idelay_ce;
end
2: begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_idelay_ce = idelay_ce;
end
3: begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_load_val = po_counter_load_val;
D_po_counter_read_en = po_counter_read_en;
D_idelay_ce = idelay_ce;
end
endcase
end
end
//obligatory phaser-ref
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST (rst)
);
// optional idelay_ctrl
generate
if ( GENERATE_IDELAYCTRL == "TRUE")
IDELAYCTRL idelayctrl (
.RDY (/*idelayctrl_rdy*/),
.REFCLK (idelayctrl_refclk),
.RST (rst)
);
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////
//// ////
//// xilinx_internal_jtag.v ////
//// ////
//// ////
//// ////
//// Author(s): ////
//// Nathan Yawn ([email protected]) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// //
// This file is a wrapper for the various Xilinx internal BSCAN //
// TAP devices. It is designed to take the place of a separate TAP //
// controller in Xilinx systems, to allow a user to access a CPU //
// debug module (such as that of the OR1200) through the FPGA's //
// dedicated JTAG / configuration port. //
// //
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xilinx_internal_jtag.v,v $
// Revision 1.4 2009-12-28 01:15:28 Nathan
// Removed incorrect duplicate assignment of capture_dr_o in SPARTAN2 TAP, per bug report from Raul Fajardo.
//
// Revision 1.3 2009/06/16 02:54:23 Nathan
// Changed some signal names for better consistency between different hardware modules.
//
// Revision 1.2 2009/05/17 20:54:16 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/18 20:07:32 Nathan
// Changed the directory structure to match existing projects.
//
// Revision 1.4 2008/07/11 08:26:10 Nathan
// Ran through dos2unix
//
// Revision 1.3 2008/07/11 08:25:52 Nathan
// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4.
//
// Revision 1.2 2008/06/09 19:34:14 Nathan
// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools.
//
// Revision 1.1 2008/05/22 19:54:07 Nathan
// Initial version
//
`include "xilinx_internal_jtag_options.v"
// Note that the SPARTAN BSCAN controllers have more than one channel.
// This implementation always uses channel 1, this is not configurable.
// If you want to use another channel, then it is probably because you
// want to attach multiple devices to the BSCAN device, which means
// you'll be making changes to this file anyway.
// Virtex BSCAN devices are instantiated separately for each channel.
// To select something other than the default (1), change the parameter
// "virtex_jtag_chain".
module xilinx_internal_jtag (
tck_o,
debug_tdo_i,
tdi_o,
test_logic_reset_o,
run_test_idle_o,
shift_dr_o,
capture_dr_o,
pause_dr_o,
update_dr_o,
debug_select_o
);
// May be 1, 2, 3, or 4
// Only used for Virtex 4/5 devices
parameter virtex_jtag_chain = 1;
input debug_tdo_i;
output tck_o;
output tdi_o;
output test_logic_reset_o;
output run_test_idle_o;
output shift_dr_o;
output capture_dr_o;
output pause_dr_o;
output update_dr_o;
output debug_select_o;
wire debug_tdo_i;
wire tck_o;
wire drck;
wire tdi_o;
wire test_logic_reset_o;
wire run_test_idle_o;
wire shift_dr_o;
wire pause_dr_o;
wire update_dr_o;
wire debug_select_o;
`ifdef SPARTAN2
// Note that this version is missing three outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected
// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no
// capture_dr output.
reg capture_dr_o;
wire update_bscan;
reg update_out;
BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0 ) // Data input for USER2 function
);
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
// On that negative edge, set capture_dr, and it will get registered on the rising
// edge.
always @ (negedge tck_o)
begin
if(debug_select_o && !shift_dr_o)
capture_dr_o <= 1'b1;
else
capture_dr_o <= 1'b0;
end
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
assign update_dr_o = update_out;
`else
`ifdef SPARTAN3
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
wire capture_dr_o;
wire update_bscan;
reg update_out;
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2(1'b0) // Data input for USER2 function
);
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
assign update_dr_o = update_out;
`else
`ifdef SPARTAN3A
// Note that this version is missing two outputs.
// At least it has a real TCK.
wire capture_dr_o;
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK1(), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TCK(tck_o), // TCK output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.TMS(), // TMS output from TAP controller
.UPDATE(update_dr_o), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0) // Data input for USER2 function
);
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
`else
`ifdef SPARTAN6
wire capture_dr_o;
BSCAN_SPARTAN6 #(
.JTAG_CHAIN(1) // Chain number.
)
BSCAN_SPARTAN6_inst (.
.CAPTURE(capture_dr_o), // 1-bit Scan Data Register Capture instruction.
.DRCK(drck), // 1-bit Scan Clock instruction. DRCK is a gated version of TCTCK,
.RESET(test_logic_reset_o), // 1-bit Scan register reset instruction.
.RUNTEST(), // 1-bit Asserted when TAP controller is in Run Test Idle state. Mak
.SEL(debug_select_o), // 1-bit Scan mode Select instruction.
.SHIFT(shift_dr_o), // 1-bit Scan Chain Shift instruction.
.TCK(tck_o), // 1-bit Scan Clock. Fabric connection to TAP Clock pin.
.TDI(tdi_o), // 1-bit Scan Chain Output. Mirror of TDI input pin to FPGA.
.TMS(), // 1-bit Test Mode Select. Fabric connection to TAP.
.UPDATE(update_dr_o), // 1-bit Scan Register Update instruction.
.TDO(debug_tdo_i) // 1-bit Scan Chain Input.
);
// End of BSCAN_SPARTAN6_inst instantiation
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
`else
`ifdef VIRTEX
// Note that this version is missing three outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
reg capture_dr_o;
wire update_bscan;
reg update_out;
BSCAN_VIRTEX BSCAN_VIRTEX_inst (
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0) // Data input for USER2 function
);
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low)
// On that negative edge, set capture_dr, and it will get registered on the rising
// edge, then de-asserted on the same edge that SHIFT goes high.
always @ (negedge tck_o)
begin
if(debug_select_o && !shift_dr_o)
capture_dr_o <= 1'b1;
else
capture_dr_o <= 1'b0;
end
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
assign update_dr_o = update_out;
`else
`ifdef VIRTEX2
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
wire capture_dr_o;
wire update_bscan;
reg update_out;
BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK1(drck), // Data register output for USER1 functions
.DRCK2(), // Data register output for USER2 functions
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL1(debug_select_o), // USER1 active output
.SEL2(), // USER2 active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO1(debug_tdo_i), // Data input for USER1 function
.TDO2( 1'b0 ) // Data input for USER2 function
);
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
assign update_dr_o = update_out;
`else
`ifdef VIRTEX4
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK is only active when USERn is selected.
wire capture_dr_o;
wire update_bscan;
reg update_out;
BSCAN_VIRTEX4 #(
.JTAG_CHAIN(virtex_jtag_chain)
) BSCAN_VIRTEX4_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK(drck), // Data register output for USER function
.RESET(test_logic_reset_o), // Reset output from TAP controller
.SEL(debug_select_o), // USER active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO( debug_tdo_i ) // Data input for USER function
);
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
assign update_dr_o = update_out;
`else
`ifdef VIRTEX5
// Note that this version is missing two outputs.
// It also does not have a real TCK...DRCK is only active when USERn is selected.
wire capture_dr_o;
wire update_bscan;
reg update_out;
BSCAN_VIRTEX5 #(
.JTAG_CHAIN(virtex_jtag_chain)
) BSCAN_VIRTEX5_inst (
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
.DRCK(drck), // Data register output for USER function
.RESET(test_logic_reset), // Reset output from TAP controller
.SEL(debug_select_o), // USER active output
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
.TDI(tdi_o), // TDI output from TAP controller
.UPDATE(update_bscan), // UPDATE output from TAP controller
.TDO(debug_tdo_i) // Data input for USER function
);
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
assign tck_o = (drck & debug_select_o & !update_bscan);
// This will hold the update_dr output so it can be registered on the rising edge
// of the clock created above.
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
if(update_bscan) update_out <= 1'b1;
else if(capture_dr_o) update_out <= 1'b0;
else if(!debug_select_o) update_out <= 1'b0;
end
assign update_dr_o = update_out;
`endif
`endif
`endif
`endif
`endif
`endif
`endif
endmodule |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_s4_amphy_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr3_s4_amphy_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
c6,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output c6;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire6;
wire sub_wire9;
wire [0:0] sub_wire12 = 1'h0;
wire [4:4] sub_wire8 = sub_wire0[4:4];
wire [0:0] sub_wire7 = sub_wire0[0:0];
wire [3:3] sub_wire5 = sub_wire0[3:3];
wire [6:6] sub_wire4 = sub_wire0[6:6];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c2 = sub_wire3;
wire c6 = sub_wire4;
wire c3 = sub_wire5;
wire locked = sub_wire6;
wire c0 = sub_wire7;
wire c4 = sub_wire8;
wire phasedone = sub_wire9;
wire sub_wire10 = inclk0;
wire [1:0] sub_wire11 = {sub_wire12, sub_wire10};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire11),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.scanclk (scanclk),
.phaseupdown (phaseupdown),
.clk (sub_wire0),
.locked (sub_wire6),
.phasedone (sub_wire9),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 3,
altpll_component.clk0_phase_shift = "556",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 3,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 3,
altpll_component.clk2_phase_shift = "556",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 3,
altpll_component.clk3_phase_shift = "-833",
altpll_component.clk4_divide_by = 1,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 3,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 2,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 3,
altpll_component.clk5_phase_shift = "0",
altpll_component.clk6_divide_by = 2,
altpll_component.clk6_duty_cycle = 50,
altpll_component.clk6_multiply_by = 3,
altpll_component.clk6_phase_shift = "4444",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_USED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 83,
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE6 STRING "150.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "83.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "60.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "240.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK6_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK6_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK6_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK6_PHASE_SHIFT STRING "4444"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "83"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: c6 0 0 0 0 OUTPUT_CLK_EXT VCC "c6"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: c6 0 0 0 0 @clk 0 0 1 6
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_amphy_phy_alt_mem_phy_pll_bb.v TRUE
|
`default_nettype none
module reservation_alu2_entry(
//System
input wire iCLOCK,
input wire inRESET,
//Entry Remove
input wire iREMOVE_VALID,
//Regist
input wire iREGISTER_VALID,
output wire oINFO_REGIST_LOCK,
input wire iREGISTER_DESTINATION_SYSREG,
input wire iREGISTER_WRITEBACK,
input wire [4:0] iREGISTER_CMD,
input wire [3:0] iREGISTER_AFE,
input wire iREGISTER_SYS_REG,
input wire iREGISTER_LOGIC,
input wire iREGISTER_SHIFT,
input wire iREGISTER_ADDER,
input wire iREGISTER_FLAGS_OPT_VALID,
input wire [3:0] iREGISTER_FLAGS_REGNAME,
input wire iREGISTER_SOURCE0_VALID,
input wire [31:0] iREGISTER_SOURCE0,
input wire iREGISTER_SOURCE1_VALID,
input wire [31:0] iREGISTER_SOURCE1,
input wire [31:0] iREGISTER_PCR,
input wire [4:0] iREGISTER_LOGIC_DEST,
input wire [5:0] iREGISTER_DESTINATION_REGNAME,
input wire [5:0] iREGISTER_COMMIT_TAG,
//Common Data Bus CDB(CH0, ADDER)
input wire iALU1_VALID,
input wire [5:0] iALU1_DESTINATION_REGNAME,
input wire iALU1_WRITEBACK,
input wire [31:0] iALU1_DATA,
//Common Data Bus CDB(CH1, MULDIV)
input wire iALU2_VALID,
input wire [5:0] iALU2_DESTINATION_REGNAME,
input wire iALU2_WRITEBACK,
input wire [31:0] iALU2_DATA,
//Common Data Bus CDB(CH1, LDST)
input wire iALU3_VALID,
input wire [5:0] iALU3_DESTINATION_REGNAME,
input wire [31:0] iALU3_DATA,
//Request Execution
input wire iEXOUT_VALID,
//Info
output wire oINFO_ENTRY_VALID,
output wire oINFO_MATCHING,
output wire oINFO_DESTINATION_SYSREG,
output wire oINFO_WRITEBACK,
output wire [4:0] oINFO_CMD,
output wire [3:0] oINFO_AFE,
output wire oINFO_SYS_REG,
output wire oINFO_LOGIC,
output wire oINFO_SHIFT,
output wire oINFO_ADDER,
output wire oINFO_FLAGS_OPT_VALID,
output wire [3:0] oINFO_FLAGS_REGNAME,
output wire oINFO_SOURCE0_VALID,
output wire [31:0] oINFO_SOURCE0,
output wire oINFO_SOURCE1_VALID,
output wire [31:0] oINFO_SOURCE1,
output wire [31:0] oINFO_PCR,
output wire [4:0] oINFO_LOGIC_DEST,
output wire [5:0] oINFO_DESTINATION_REGNAME,
output wire [5:0] oINFO_COMMIT_TAG
);
reg b0_state;
reg b0_reg_lock;
reg b0_destination_sysreg;
reg b0_writeback;
reg [4:0] b0_cmd;
reg [3:0] b0_afe;
reg b0_sys_reg;
reg b0_logic;
reg b0_shift;
reg b0_adder;
reg b0_flag_opt_valid;
reg [3:0] b0_flags_regname;
reg b0_source0_valid;
reg [31:0] b0_source0;
reg b0_source1_valid;
reg [31:0] b0_source1;
reg [31:0] b0_pcr;
reg [4:0] b0_logic_dest;
reg [5:0] b0_destination_regname;
reg [5:0] b0_commit_tag;
always@(negedge inRESET or posedge iCLOCK)begin
if(!inRESET)begin
b0_state <= 1'h0;
b0_reg_lock <= 1'b0;
b0_destination_sysreg <= 1'b0;
b0_writeback <= 1'b0;
b0_cmd <= {5{1'b0}};
b0_afe <= {4{1'b0}};
b0_sys_reg <= 1'b0;
b0_logic <= 1'b0;
b0_shift <= 1'b0;
b0_adder <= 1'b0;
b0_flag_opt_valid <= 1'b0;
b0_flags_regname <= 4'h0;
b0_source0_valid <= 1'b0;
b0_source0 <= {32{1'b0}};
b0_source1_valid <= 1'b0;
b0_source1 <= {32{1'b0}};
b0_pcr <= 32'h0;
b0_destination_regname <= {6{1'b0}};
b0_commit_tag <= {6{1'b0}};
b0_logic_dest <= 5'h0;
end
else if(iREMOVE_VALID || iEXOUT_VALID)begin
b0_state <= 1'h0;
b0_reg_lock <= 1'b1;
b0_destination_sysreg <= 1'b0;
b0_writeback <= 1'b0;
b0_cmd <= {5{1'b0}};
b0_afe <= {4{1'b0}};
b0_sys_reg <= 1'b0;
b0_logic <= 1'b0;
b0_shift <= 1'b0;
b0_adder <= 1'b0;
b0_flag_opt_valid <= 1'b0;
b0_flags_regname <= 4'h0;
b0_source0_valid <= 1'b0;
b0_source0 <= {32{1'b0}};
b0_source1_valid <= 1'b0;
b0_source1 <= {32{1'b0}};
b0_pcr <= 32'h0;
b0_destination_regname <= {6{1'b0}};
b0_commit_tag <= {6{1'b0}};
b0_logic_dest <= 5'h0;
end
else begin
case(b0_state)
1'h0 : //Entry Regist Wait
begin
if(iREGISTER_VALID)begin
b0_state <= 1'h1;
b0_reg_lock <= 1'b1;
b0_destination_sysreg <= iREGISTER_DESTINATION_SYSREG;
b0_writeback <= iREGISTER_WRITEBACK;
b0_cmd <= iREGISTER_CMD;
b0_afe <= iREGISTER_AFE;
b0_sys_reg <= iREGISTER_SYS_REG;
b0_logic <= iREGISTER_LOGIC;
b0_shift <= iREGISTER_SHIFT;
b0_adder <= iREGISTER_ADDER;
//Source 0
if(iREGISTER_SOURCE0_VALID)begin
b0_source0_valid <= 1'b1;
b0_source0 <= iREGISTER_SOURCE0;
end
else if(iALU1_VALID & iALU1_WRITEBACK && iREGISTER_SOURCE0[5:0] == iALU1_DESTINATION_REGNAME)begin
b0_source0_valid <= 1'b1;
b0_source0 <= iALU1_DATA;
end
else if(iALU2_VALID & iALU2_WRITEBACK && iREGISTER_SOURCE0[5:0] == iALU2_DESTINATION_REGNAME)begin
b0_source0_valid <= 1'b1;
b0_source0 <= iALU2_DATA;
end
else if(iALU3_VALID && iREGISTER_SOURCE0[5:0] == iALU3_DESTINATION_REGNAME)begin
b0_source0_valid <= 1'b1;
b0_source0 <= iALU3_DATA;
end
else begin
b0_source0_valid <= 1'b0;
b0_source0 <= {{26{1'b0}}, iREGISTER_SOURCE0[5:0]};
end
//Source1
if(iREGISTER_SOURCE1_VALID)begin
b0_source1_valid <= 1'b1;
b0_source1 <= iREGISTER_SOURCE1;
end
else if(iALU1_VALID & iALU1_WRITEBACK && iREGISTER_SOURCE1[5:0] == iALU1_DESTINATION_REGNAME)begin
b0_source1_valid <= 1'b1;
b0_source1 <= iALU1_DATA;
end
else if(iALU2_VALID & iALU2_WRITEBACK && iREGISTER_SOURCE1[5:0] == iALU2_DESTINATION_REGNAME)begin
b0_source1_valid <= 1'b1;
b0_source1 <= iALU2_DATA;
end
else if(iALU3_VALID && iREGISTER_SOURCE1[5:0] == iALU3_DESTINATION_REGNAME)begin
b0_source1_valid <= 1'b1;
b0_source1 <= iALU3_DATA;
end
else begin
b0_source1_valid <= 1'b0;
b0_source1 <= {{26{1'b0}}, iREGISTER_SOURCE1[5:0]};
end
b0_flag_opt_valid <= iREGISTER_FLAGS_OPT_VALID;
b0_flags_regname <= iREGISTER_FLAGS_REGNAME;
b0_destination_regname <= iREGISTER_DESTINATION_REGNAME;
b0_commit_tag <= iREGISTER_COMMIT_TAG;
b0_pcr <= iREGISTER_PCR;
b0_logic_dest <= iREGISTER_LOGIC_DEST;
end
else begin
b0_reg_lock <= 1'b0;
end
end
default :
begin
//Source0 Matching Check
if(!b0_source0_valid & iALU1_VALID & iALU1_WRITEBACK && b0_source0[5:0] == iALU1_DESTINATION_REGNAME)begin
b0_source0_valid <= 1'b1;
b0_source0 <= iALU1_DATA;
end
else if(!b0_source0_valid & iALU2_VALID & iALU2_WRITEBACK && b0_source0[5:0] == iALU2_DESTINATION_REGNAME)begin
b0_source0_valid <= 1'b1;
b0_source0 <= iALU2_DATA;
end
else if(!b0_source0_valid & iALU3_VALID && b0_source0[5:0] == iALU3_DESTINATION_REGNAME)begin
b0_source0_valid <= 1'b1;
b0_source0 <= iALU3_DATA;
end
//Source1 Matching Check
if(!b0_source1_valid & iALU1_VALID & iALU1_WRITEBACK && b0_source1[5:0] == iALU1_DESTINATION_REGNAME)begin
b0_source1_valid <= 1'b1;
b0_source1 <= iALU1_DATA;
end
else if(!b0_source1_valid & iALU2_VALID & iALU2_WRITEBACK && b0_source1[5:0] == iALU2_DESTINATION_REGNAME)begin
b0_source1_valid <= 1'b1;
b0_source1 <= iALU2_DATA;
end
else if(!b0_source1_valid & iALU3_VALID && b0_source1[5:0] == iALU3_DESTINATION_REGNAME)begin
b0_source1_valid <= 1'b1;
b0_source1 <= iALU3_DATA;
end
end
endcase
end
end //always
//Output
assign oINFO_ENTRY_VALID = b0_state;
assign oINFO_REGIST_LOCK = b0_reg_lock;
assign oINFO_MATCHING = b0_source0_valid & b0_source1_valid;
assign oINFO_DESTINATION_SYSREG = b0_destination_sysreg;
assign oINFO_WRITEBACK = b0_writeback;
assign oINFO_CMD = b0_cmd;
assign oINFO_AFE = b0_afe;
assign oINFO_SYS_REG = b0_sys_reg;
assign oINFO_LOGIC = b0_logic;
assign oINFO_SHIFT = b0_shift;
assign oINFO_ADDER = b0_adder;
assign oINFO_FLAGS_OPT_VALID = b0_flag_opt_valid;
assign oINFO_FLAGS_REGNAME = b0_flags_regname;
assign oINFO_SOURCE0_VALID = b0_source0_valid;
assign oINFO_SOURCE0 = b0_source0;
assign oINFO_SOURCE1_VALID = b0_source1_valid;
assign oINFO_SOURCE1 = b0_source1;
assign oINFO_LOGIC_DEST = b0_logic_dest;
assign oINFO_DESTINATION_REGNAME = b0_destination_regname;
assign oINFO_COMMIT_TAG = b0_commit_tag;
assign oINFO_PCR = b0_pcr;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_FUNCTIONAL_V |
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Default depth for this memory model is 2048, do these when
//changing the depth.
//1)Set ARRAY_DEPTH generic/parameter from 2048 to new depth.
//2)Change mem_array depth from 2047 to (new depth - 1).
//3)VHDL only, don't forget the generic in component declaration
module ddr3_int_mem_model_ram_module (
// inputs:
data,
rdaddress,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
parameter ARRAY_DEPTH = 2048;
output [127: 0] q;
input [127: 0] data;
input [ 24: 0] rdaddress;
input [ 24: 0] wraddress;
input wrclock;
input wren;
wire [127: 0] aq;
reg [153: 0] mem_array [2047: 0];
wire [127: 0] q;
assign aq = mem_array[0][127:0];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [ 128 - 1: 0] out;
integer i;
reg found_valid_data;
reg data_written;
initial
begin
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
mem_array[i][0] <= 1'b0;
data_written <= 1'b0;
end
always @(rdaddress)
begin
found_valid_data <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (rdaddress == mem_array[i][154 - 1:154 - 25] && mem_array[i][0])
begin
out = mem_array[i][154 - 25 - 1:154 - 25 - 128];
found_valid_data = 1'b1;
end
end
if (!found_valid_data)
out = 128'dX;
end
always @(posedge wrclock)
if (wren)
begin
data_written <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (wraddress == mem_array[i][154 - 1:154 - 25] && !data_written)
begin
mem_array[i][154 - 25 - 1:154 - 25 - 128] <= data;
mem_array[i][0] <= 1'b1;
data_written = 1'b1;
end
else if (!mem_array[i][0] && !data_written)
begin
mem_array[i] <= {wraddress,data,1'b1};
data_written = 1'b1;
end
end
if (!data_written)
begin
$write($time);
$write(" --- Data could not be written, increase array depth or use full memory model --- ");
$stop;
end
end
assign q = out;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_int_mem_model (
// inputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_rst_n,
mem_we_n,
// outputs:
global_reset_n,
mem_dq,
mem_dqs,
mem_dqs_n
)
;
output global_reset_n;
inout [ 63: 0] mem_dq;
inout [ 7: 0] mem_dqs;
inout [ 7: 0] mem_dqs_n;
input [ 12: 0] mem_addr;
input [ 2: 0] mem_ba;
input mem_cas_n;
input mem_cke;
input mem_clk;
input mem_clk_n;
input mem_cs_n;
input [ 7: 0] mem_dm;
input mem_odt;
input mem_ras_n;
input mem_rst_n;
input mem_we_n;
wire [ 23: 0] CODE;
wire [ 12: 0] a;
reg [ 3: 0] additive_latency;
wire [ 8: 0] addr_col;
wire [ 2: 0] ba;
reg [ 2: 0] burstlength;
reg burstmode;
wire cas_n;
wire cke;
wire clk;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 2: 0] current_row;
wire [ 7: 0] dm;
reg [ 15: 0] dm_captured;
reg [127: 0] dq_captured;
wire [ 63: 0] dq_temp;
wire dq_valid;
wire [ 7: 0] dqs_n_temp;
wire [ 7: 0] dqs_temp;
wire dqs_valid;
reg dqs_valid_temp;
reg [ 63: 0] first_half_dq;
wire global_reset_n;
wire [127: 0] mem_bytes;
wire [ 63: 0] mem_dq;
wire [ 7: 0] mem_dqs;
wire [ 7: 0] mem_dqs_n;
reg [ 12: 0] open_rows [ 7: 0];
wire ras_n;
reg [ 24: 0] rd_addr_pipe_0;
reg [ 24: 0] rd_addr_pipe_1;
reg [ 24: 0] rd_addr_pipe_10;
reg [ 24: 0] rd_addr_pipe_11;
reg [ 24: 0] rd_addr_pipe_12;
reg [ 24: 0] rd_addr_pipe_13;
reg [ 24: 0] rd_addr_pipe_14;
reg [ 24: 0] rd_addr_pipe_15;
reg [ 24: 0] rd_addr_pipe_16;
reg [ 24: 0] rd_addr_pipe_17;
reg [ 24: 0] rd_addr_pipe_18;
reg [ 24: 0] rd_addr_pipe_19;
reg [ 24: 0] rd_addr_pipe_2;
reg [ 24: 0] rd_addr_pipe_20;
reg [ 24: 0] rd_addr_pipe_21;
reg [ 24: 0] rd_addr_pipe_3;
reg [ 24: 0] rd_addr_pipe_4;
reg [ 24: 0] rd_addr_pipe_5;
reg [ 24: 0] rd_addr_pipe_6;
reg [ 24: 0] rd_addr_pipe_7;
reg [ 24: 0] rd_addr_pipe_8;
reg [ 24: 0] rd_addr_pipe_9;
reg [ 24: 0] rd_burst_counter;
reg [ 25: 0] rd_valid_pipe;
wire [ 24: 0] read_addr_delayed;
reg read_cmd;
reg read_cmd_echo;
wire [127: 0] read_data;
wire [ 63: 0] read_dq;
reg [ 4: 0] read_latency;
wire read_valid;
reg read_valid_r;
reg read_valid_r2;
reg read_valid_r3;
reg read_valid_r4;
reg reset_n;
wire [ 24: 0] rmw_address;
reg [127: 0] rmw_temp;
reg [ 63: 0] second_half_dq;
reg [ 3: 0] tcl;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 24: 0] wr_addr_delayed;
reg [ 24: 0] wr_addr_delayed_r;
reg [ 24: 0] wr_addr_pipe_0;
reg [ 24: 0] wr_addr_pipe_1;
reg [ 24: 0] wr_addr_pipe_10;
reg [ 24: 0] wr_addr_pipe_11;
reg [ 24: 0] wr_addr_pipe_12;
reg [ 24: 0] wr_addr_pipe_13;
reg [ 24: 0] wr_addr_pipe_14;
reg [ 24: 0] wr_addr_pipe_15;
reg [ 24: 0] wr_addr_pipe_16;
reg [ 24: 0] wr_addr_pipe_17;
reg [ 24: 0] wr_addr_pipe_18;
reg [ 24: 0] wr_addr_pipe_2;
reg [ 24: 0] wr_addr_pipe_3;
reg [ 24: 0] wr_addr_pipe_4;
reg [ 24: 0] wr_addr_pipe_5;
reg [ 24: 0] wr_addr_pipe_6;
reg [ 24: 0] wr_addr_pipe_7;
reg [ 24: 0] wr_addr_pipe_8;
reg [ 24: 0] wr_addr_pipe_9;
reg [ 24: 0] wr_burst_counter;
reg [ 25: 0] wr_valid_pipe;
wire write_burst_length;
reg [ 25: 0] write_burst_length_pipe;
reg write_cmd;
reg write_cmd_echo;
reg [ 4: 0] write_latency;
wire write_to_ram;
reg write_to_ram_r;
wire write_valid;
reg write_valid_r;
reg write_valid_r2;
reg write_valid_r3;
reg [ 3: 0] wtcl;
initial
begin
$write("\n");
$write("**********************************************************************\n");
$write("This testbench includes a generated Altera memory model:\n");
$write("'ddr3_int_mem_model.v', to simulate accesses to the DDR3 SDRAM memory.\n");
$write(" \n");
$write("**********************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
ddr3_int_mem_model_ram_module ddr3_int_mem_model_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress (rmw_address),
.wraddress (wr_addr_delayed_r),
.wrclock (clk),
.wren (write_to_ram_r)
);
assign clk = mem_clk;
assign dm = mem_dm;
assign cke = mem_cke;
assign cs_n = mem_cs_n;
assign ras_n = mem_ras_n;
assign cas_n = mem_cas_n;
assign we_n = mem_we_n;
assign ba = mem_ba;
assign a = mem_addr;
//generate a fake reset inside the memory model
assign global_reset_n = reset_n;
initial
begin
reset_n <= 0;
#100 reset_n <= 1;
end
assign cmd_code = (&cs_n) ? 3'b111 : {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[9 : 1];
assign current_row = {ba};
// Decode commands into their actions
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
write_cmd_echo <= 0;
read_cmd_echo <= 0;
end
else // No Activity if the clock is
if (cke)
begin
// Checks whether to echo read cmd
if (read_cmd_echo && !read_cmd)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b0;
end
else // This is a read command
if (cmd_code == 3'b101)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b1;
end
else
read_cmd <= 1'b0;
// Checks whether to echo write cmd
if (write_cmd_echo && !write_cmd)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b0;
end
else // This is a write command
if (cmd_code == 3'b100)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b1;
write_burst_length_pipe[0] <= a[12];
end
else
write_cmd <= 1'b0;
// This is an activate - store the chip/row/bank address in the same order as the DDR controller
if (cmd_code == 3'b011)
open_rows[current_row] <= a;
end
end
// Pipes are flushed here
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_1 <= 0;
wr_addr_pipe_2 <= 0;
wr_addr_pipe_3 <= 0;
wr_addr_pipe_4 <= 0;
wr_addr_pipe_5 <= 0;
wr_addr_pipe_6 <= 0;
wr_addr_pipe_7 <= 0;
wr_addr_pipe_8 <= 0;
wr_addr_pipe_9 <= 0;
wr_addr_pipe_10 <= 0;
wr_addr_pipe_11 <= 0;
wr_addr_pipe_12 <= 0;
wr_addr_pipe_13 <= 0;
wr_addr_pipe_14 <= 0;
wr_addr_pipe_15 <= 0;
wr_addr_pipe_16 <= 0;
wr_addr_pipe_17 <= 0;
wr_addr_pipe_18 <= 0;
rd_addr_pipe_1 <= 0;
rd_addr_pipe_2 <= 0;
rd_addr_pipe_3 <= 0;
rd_addr_pipe_4 <= 0;
rd_addr_pipe_5 <= 0;
rd_addr_pipe_6 <= 0;
rd_addr_pipe_7 <= 0;
rd_addr_pipe_8 <= 0;
rd_addr_pipe_9 <= 0;
rd_addr_pipe_10 <= 0;
rd_addr_pipe_11 <= 0;
rd_addr_pipe_12 <= 0;
rd_addr_pipe_13 <= 0;
rd_addr_pipe_14 <= 0;
rd_addr_pipe_15 <= 0;
rd_addr_pipe_16 <= 0;
rd_addr_pipe_17 <= 0;
rd_addr_pipe_18 <= 0;
rd_addr_pipe_19 <= 0;
rd_addr_pipe_20 <= 0;
rd_addr_pipe_21 <= 0;
end
else // No Activity if the clock is
if (cke)
begin
rd_addr_pipe_21 <= rd_addr_pipe_20;
rd_addr_pipe_20 <= rd_addr_pipe_19;
rd_addr_pipe_19 <= rd_addr_pipe_18;
rd_addr_pipe_18 <= rd_addr_pipe_17;
rd_addr_pipe_17 <= rd_addr_pipe_16;
rd_addr_pipe_16 <= rd_addr_pipe_15;
rd_addr_pipe_15 <= rd_addr_pipe_14;
rd_addr_pipe_14 <= rd_addr_pipe_13;
rd_addr_pipe_13 <= rd_addr_pipe_12;
rd_addr_pipe_12 <= rd_addr_pipe_11;
rd_addr_pipe_11 <= rd_addr_pipe_10;
rd_addr_pipe_10 <= rd_addr_pipe_9;
rd_addr_pipe_9 <= rd_addr_pipe_8;
rd_addr_pipe_8 <= rd_addr_pipe_7;
rd_addr_pipe_7 <= rd_addr_pipe_6;
rd_addr_pipe_6 <= rd_addr_pipe_5;
rd_addr_pipe_5 <= rd_addr_pipe_4;
rd_addr_pipe_4 <= rd_addr_pipe_3;
rd_addr_pipe_3 <= rd_addr_pipe_2;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_valid_pipe[25 : 1] <= rd_valid_pipe[24 : 0];
rd_valid_pipe[0] <= cmd_code == 3'b101;
wr_addr_pipe_18 <= wr_addr_pipe_17;
wr_addr_pipe_17 <= wr_addr_pipe_16;
wr_addr_pipe_16 <= wr_addr_pipe_15;
wr_addr_pipe_15 <= wr_addr_pipe_14;
wr_addr_pipe_14 <= wr_addr_pipe_13;
wr_addr_pipe_13 <= wr_addr_pipe_12;
wr_addr_pipe_12 <= wr_addr_pipe_11;
wr_addr_pipe_11 <= wr_addr_pipe_10;
wr_addr_pipe_10 <= wr_addr_pipe_9;
wr_addr_pipe_9 <= wr_addr_pipe_8;
wr_addr_pipe_8 <= wr_addr_pipe_7;
wr_addr_pipe_7 <= wr_addr_pipe_6;
wr_addr_pipe_6 <= wr_addr_pipe_5;
wr_addr_pipe_5 <= wr_addr_pipe_4;
wr_addr_pipe_4 <= wr_addr_pipe_3;
wr_addr_pipe_3 <= wr_addr_pipe_2;
wr_addr_pipe_2 <= wr_addr_pipe_1;
wr_addr_pipe_1 <= wr_addr_pipe_0;
wr_valid_pipe[25 : 1] <= wr_valid_pipe[24 : 0];
wr_valid_pipe[0] <= cmd_code == 3'b100;
wr_addr_delayed_r <= wr_addr_delayed;
write_burst_length_pipe[25 : 1] <= write_burst_length_pipe[24 : 0];
end
end
// Decode CAS Latency from bits a[6:4]
always @(posedge clk)
begin
// No Activity if the clock is disabled
if (cke)
//Load mode register - set CAS latency, burst mode and length
if (cmd_code == 3'b000 && ba == 2'b00)
begin
burstmode <= a[3];
burstlength <= a[2 : 0] << 1;
//CAS Latency = 5
if (a[6 : 4] == 3'b001)
tcl <= 4'b0100;
else //CAS Latency = 6
if (a[6 : 4] == 3'b010)
tcl <= 4'b0101;
else //CAS Latency = 7
if (a[6 : 4] == 3'b011)
tcl <= 4'b0110;
else //CAS Latency = 8
if (a[6 : 4] == 3'b100)
tcl <= 4'b0111;
else //CAS Latency = 9
if (a[6 : 4] == 3'b101)
tcl <= 4'b1000;
else
tcl <= 4'b1001;
end
else //Get additive latency
if (cmd_code == 3'b000 && ba == 2'b01)
additive_latency <= {2'b00,a[4 : 3]};
else //Get write latency
if (cmd_code == 3'b000 && ba == 2'b10)
//CWL = 5
if (a[5 : 3] == 3'b000)
wtcl <= 4'b0101;
else //CWL = 6
if (a[5 : 3] == 3'b001)
wtcl <= 4'b0110;
else //CWL = 7
if (a[5 : 3] == 3'b010)
wtcl <= 4'b0111;
else //CWL = 8
if (a[5 : 3] == 3'b011)
wtcl <= 4'b1000;
end
//Calculate actual write and read latency
always @(additive_latency or tcl or wtcl)
begin
//no additive latency
if (additive_latency == 4'd0)
begin
read_latency = tcl;
write_latency = wtcl;
end
else //CL - 1
if (additive_latency == 4'd1)
begin
read_latency = tcl + (tcl + 1) - 1;
write_latency = wtcl + (tcl + 1) - 1;
end
else
begin
read_latency = tcl + (tcl + 1) - 2;
write_latency = wtcl + (tcl + 1) - 2;
end
end
// Burst support - make the wr_addr & rd_addr keep counting
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_0 <= 0;
rd_addr_pipe_0 <= 0;
end
else
begin
// Reset write address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
begin
wr_addr_pipe_0 <= 0;
wr_burst_counter <= 0;
end
else if (cmd_code == 3'b100)
begin
wr_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
wr_burst_counter[24 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
wr_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (write_cmd || write_to_ram || write_cmd_echo)
begin
wr_addr_pipe_0 <= wr_burst_counter;
wr_burst_counter[1 : 0] <= wr_burst_counter[1 : 0] + 1;
end
else
wr_addr_pipe_0 <= 0;
// Reset read address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
rd_addr_pipe_0 <= 0;
else if (cmd_code == 3'b101)
begin
rd_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
rd_burst_counter[24 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
rd_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (read_cmd || dq_valid || read_valid || read_cmd_echo)
begin
rd_addr_pipe_0 <= rd_burst_counter;
rd_burst_counter[1 : 0] <= rd_burst_counter[1 : 0] + 1;
end
else
rd_addr_pipe_0 <= 0;
end
end
// read data transition from single to double clock rate
always @(posedge clk)
begin
first_half_dq <= read_data[127 : 64];
second_half_dq <= read_data[63 : 0];
end
assign read_dq = clk ? second_half_dq : first_half_dq;
assign dq_temp = dq_valid ? read_dq : {64{1'bz}};
assign dqs_temp = dqs_valid ? {8{clk}} : {8{1'bz}};
assign dqs_n_temp = dqs_valid ? {8{~clk}} : {8{1'bz}};
assign mem_dqs = dqs_temp;
assign mem_dq = dq_temp;
assign mem_dqs_n = dqs_n_temp;
//Pipelining registers for burst counting
always @(posedge clk)
begin
write_valid_r <= write_valid;
read_valid_r <= read_valid;
write_valid_r2 <= write_valid_r;
write_valid_r3 <= write_valid_r2;
write_to_ram_r <= write_to_ram;
read_valid_r2 <= read_valid_r;
read_valid_r3 <= read_valid_r2;
read_valid_r4 <= read_valid_r3;
end
assign write_to_ram = write_burst_length ? write_valid || write_valid_r || write_valid_r2 || write_valid_r3 : write_valid || write_valid_r;
assign dq_valid = read_valid_r || read_valid_r2 || read_valid_r3 || read_valid_r4;
assign dqs_valid = dq_valid || dqs_valid_temp;
//
always @(negedge clk)
begin
dqs_valid_temp <= read_valid;
end
//capture first half of write data with rising edge of DQS, for simulation use only 1 DQS pin
always @(posedge mem_dqs[0])
begin
#0.1 dq_captured[63 : 0] <= mem_dq[63 : 0];
#0.1 dm_captured[7 : 0] <= mem_dm[7 : 0];
end
//capture second half of write data with falling edge of DQS, for simulation use only 1 DQS pin
always @(negedge mem_dqs[0])
begin
#0.1 dq_captured[127 : 64] <= mem_dq[63 : 0];
#0.1 dm_captured[15 : 8] <= mem_dm[7 : 0];
end
//Support for incomplete writes, do a read-modify-write with mem_bytes and the write data
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[7 : 0] <= dm_captured[0] ? mem_bytes[7 : 0] : dq_captured[7 : 0];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[15 : 8] <= dm_captured[1] ? mem_bytes[15 : 8] : dq_captured[15 : 8];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[23 : 16] <= dm_captured[2] ? mem_bytes[23 : 16] : dq_captured[23 : 16];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[31 : 24] <= dm_captured[3] ? mem_bytes[31 : 24] : dq_captured[31 : 24];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[39 : 32] <= dm_captured[4] ? mem_bytes[39 : 32] : dq_captured[39 : 32];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[47 : 40] <= dm_captured[5] ? mem_bytes[47 : 40] : dq_captured[47 : 40];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[55 : 48] <= dm_captured[6] ? mem_bytes[55 : 48] : dq_captured[55 : 48];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[63 : 56] <= dm_captured[7] ? mem_bytes[63 : 56] : dq_captured[63 : 56];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[71 : 64] <= dm_captured[8] ? mem_bytes[71 : 64] : dq_captured[71 : 64];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[79 : 72] <= dm_captured[9] ? mem_bytes[79 : 72] : dq_captured[79 : 72];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[87 : 80] <= dm_captured[10] ? mem_bytes[87 : 80] : dq_captured[87 : 80];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[95 : 88] <= dm_captured[11] ? mem_bytes[95 : 88] : dq_captured[95 : 88];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[103 : 96] <= dm_captured[12] ? mem_bytes[103 : 96] : dq_captured[103 : 96];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[111 : 104] <= dm_captured[13] ? mem_bytes[111 : 104] : dq_captured[111 : 104];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[119 : 112] <= dm_captured[14] ? mem_bytes[119 : 112] : dq_captured[119 : 112];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[127 : 120] <= dm_captured[15] ? mem_bytes[127 : 120] : dq_captured[127 : 120];
end
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives valid
assign write_valid = (write_latency == 0)? wr_valid_pipe[0] :
(write_latency == 1)? wr_valid_pipe[1] :
(write_latency == 2)? wr_valid_pipe[2] :
(write_latency == 3)? wr_valid_pipe[3] :
(write_latency == 4)? wr_valid_pipe[4] :
(write_latency == 5)? wr_valid_pipe[5] :
(write_latency == 6)? wr_valid_pipe[6] :
(write_latency == 7)? wr_valid_pipe[7] :
(write_latency == 8)? wr_valid_pipe[8] :
(write_latency == 9)? wr_valid_pipe[9] :
(write_latency == 10)? wr_valid_pipe[10] :
(write_latency == 11)? wr_valid_pipe[11] :
(write_latency == 12)? wr_valid_pipe[12] :
(write_latency == 13)? wr_valid_pipe[13] :
(write_latency == 14)? wr_valid_pipe[14] :
(write_latency == 15)? wr_valid_pipe[15] :
(write_latency == 16)? wr_valid_pipe[16] :
(write_latency == 17)? wr_valid_pipe[17] :
wr_valid_pipe[18];
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives addr
assign wr_addr_delayed = (write_latency == 0)? wr_addr_pipe_0 :
(write_latency == 1)? wr_addr_pipe_1 :
(write_latency == 2)? wr_addr_pipe_2 :
(write_latency == 3)? wr_addr_pipe_3 :
(write_latency == 4)? wr_addr_pipe_4 :
(write_latency == 5)? wr_addr_pipe_5 :
(write_latency == 6)? wr_addr_pipe_6 :
(write_latency == 7)? wr_addr_pipe_7 :
(write_latency == 8)? wr_addr_pipe_8 :
(write_latency == 9)? wr_addr_pipe_9 :
(write_latency == 10)? wr_addr_pipe_10 :
(write_latency == 11)? wr_addr_pipe_11 :
(write_latency == 12)? wr_addr_pipe_12 :
(write_latency == 13)? wr_addr_pipe_13 :
(write_latency == 14)? wr_addr_pipe_14 :
(write_latency == 15)? wr_addr_pipe_15 :
(write_latency == 16)? wr_addr_pipe_16 :
(write_latency == 17)? wr_addr_pipe_17 :
wr_addr_pipe_18;
//DDR3 has on the fly mode
assign write_burst_length = (write_latency == 0)? write_burst_length_pipe[0] :
(write_latency == 1)? write_burst_length_pipe[1] :
(write_latency == 2)? write_burst_length_pipe[2] :
(write_latency == 3)? write_burst_length_pipe[3] :
(write_latency == 4)? write_burst_length_pipe[4] :
(write_latency == 5)? write_burst_length_pipe[5] :
(write_latency == 6)? write_burst_length_pipe[6] :
(write_latency == 7)? write_burst_length_pipe[7] :
(write_latency == 8)? write_burst_length_pipe[8] :
(write_latency == 9)? write_burst_length_pipe[9] :
(write_latency == 10)? write_burst_length_pipe[10] :
(write_latency == 11)? write_burst_length_pipe[11] :
(write_latency == 12)? write_burst_length_pipe[12] :
(write_latency == 13)? write_burst_length_pipe[13] :
(write_latency == 14)? write_burst_length_pipe[14] :
(write_latency == 15)? write_burst_length_pipe[15] :
(write_latency == 16)? write_burst_length_pipe[16] :
(write_latency == 17)? write_burst_length_pipe[17] :
write_burst_length_pipe[18];
assign mem_bytes = (rmw_address == wr_addr_delayed_r && write_to_ram_r) ? rmw_temp : read_data;
assign rmw_address = (write_to_ram) ? wr_addr_delayed : read_addr_delayed;
//use read_latency to select which pipeline stage drives addr
assign read_addr_delayed = (read_latency == 0)? rd_addr_pipe_0 :
(read_latency == 1)? rd_addr_pipe_1 :
(read_latency == 2)? rd_addr_pipe_2 :
(read_latency == 3)? rd_addr_pipe_3 :
(read_latency == 4)? rd_addr_pipe_4 :
(read_latency == 5)? rd_addr_pipe_5 :
(read_latency == 6)? rd_addr_pipe_6 :
(read_latency == 7)? rd_addr_pipe_7 :
(read_latency == 8)? rd_addr_pipe_8 :
(read_latency == 9)? rd_addr_pipe_9 :
(read_latency == 10)? rd_addr_pipe_10 :
(read_latency == 11)? rd_addr_pipe_11 :
(read_latency == 12)? rd_addr_pipe_12 :
(read_latency == 13)? rd_addr_pipe_13 :
(read_latency == 14)? rd_addr_pipe_14 :
(read_latency == 15)? rd_addr_pipe_15 :
(read_latency == 16)? rd_addr_pipe_16 :
(read_latency == 17)? rd_addr_pipe_17 :
(read_latency == 18)? rd_addr_pipe_18 :
(read_latency == 19)? rd_addr_pipe_19 :
(read_latency == 20)? rd_addr_pipe_20 :
rd_addr_pipe_21;
//use read_latency to select which pipeline stage drives valid
assign read_valid = (read_latency == 0)? rd_valid_pipe[0] :
(read_latency == 1)? rd_valid_pipe[1] :
(read_latency == 2)? rd_valid_pipe[2] :
(read_latency == 3)? rd_valid_pipe[3] :
(read_latency == 4)? rd_valid_pipe[4] :
(read_latency == 5)? rd_valid_pipe[5] :
(read_latency == 6)? rd_valid_pipe[6] :
(read_latency == 7)? rd_valid_pipe[7] :
(read_latency == 8)? rd_valid_pipe[8] :
(read_latency == 9)? rd_valid_pipe[9] :
(read_latency == 10)? rd_valid_pipe[10] :
(read_latency == 11)? rd_valid_pipe[11] :
(read_latency == 12)? rd_valid_pipe[12] :
(read_latency == 13)? rd_valid_pipe[13] :
(read_latency == 14)? rd_valid_pipe[14] :
(read_latency == 15)? rd_valid_pipe[15] :
(read_latency == 16)? rd_valid_pipe[16] :
(read_latency == 17)? rd_valid_pipe[17] :
(read_latency == 18)? rd_valid_pipe[18] :
(read_latency == 19)? rd_valid_pipe[19] :
(read_latency == 20)? rd_valid_pipe[20] :
rd_valid_pipe[21];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_ctrl_in (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 1: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] data_out;
wire [ 1: 0] out_port;
wire [ 1: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[1 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
module data_path(
clk,
reset,
MIO_ready,
IorD,
IRWrite,
RegDst,
RegWrite,
MemtoReg,
ALUSrcA,
ALUSrcB,
PCSource,
PCWrite,
PCWriteCond,
Beq,
ALU_operation,
PC_Current,
data2CPU,
Inst_R,
data_out,
M_addr,
zero,
overflow
);
input clk, reset;
input MIO_ready, IorD, IRWrite, RegWrite, ALUSrcA, PCWrite, PCWriteCond, Beq;
input [1:0] RegDst, MemtoReg, ALUSrcB, PCSource;
input [2:0] ALU_operation;
input [31:0] data2CPU;
output [31:0] Inst_R, M_addr, data_out, PC_Current;
output zero, overflow;
reg [31:0] Inst_R, ALU_Out, MDR, PC_Current;
wire reset, rst, zero, overflow, IRWrite, MIO_ready, RegWrite, Beq, modificative;
wire IorD, ALUSrcA, PCWrite, PCWriteCond;
wire [1:0] RegDst, MemtoReg, ALUSrcB, PCSource;
// wire [31:0] reg_outA, reg_outB, r6out;
//ALU
wire [31:0] Alu_A, Alu_B, res;
wire [31:0] w_reg_data, rdata_A, rdata_B, data_out, data2CPU, M_addr;
wire [2:0] ALU_operation;
wire [15:0] imm;
wire [4:0] reg_Rs_addr_A, reg_Rt_addr_B, reg_rd_addr, reg_Wt_addr;
initial begin
PC_Current <= 0;
Inst_R <= 0;
ALU_Out <= 0;
MDR <= 0;
end
assign rst = reset;
// locked inst form memory
always @(posedge clk or posedge rst)begin
if (rst) begin
Inst_R<=0;
end else begin
if (IRWrite && MIO_ready)
Inst_R<=data2CPU;
else
Inst_R<=Inst_R;
if (MIO_ready) MDR<=data2CPU;
ALU_Out<=res;
end
end
alu x_ALU(
.A(Alu_A),
.B(Alu_B),
.ALU_operation(ALU_operation),
.res(res),
.zero(zero),
.overflow(overflow)
);
Regs reg_files(
.clk(clk),
.rst(rst),
.reg_R_addr_A(reg_Rs_addr_A),
.reg_R_addr_B(reg_Rt_addr_B),
.reg_W_addr(reg_Wt_addr),
.wdata(w_reg_data),
.reg_we(RegWrite),
.rdata_A(rdata_A),
.rdata_B(rdata_B)
);
// reg path
assign reg_Rs_addr_A=Inst_R[25:21]; //REG Source 1 rs
assign reg_Rt_addr_B=Inst_R[20:16]; //REG Source 2 or Destination rt
assign reg_rd_addr=Inst_R[15:11]; //REG Destination rd
assign imm=Inst_R[15:0]; //Immediate
// reg write data
mux4to1_32 mux_w_reg_data(
.a(ALU_Out), //ALU OP
.b(MDR), //LW
.c({imm,16'h0000}), //lui
.d(PC_Current), // jal jalr
.sel(MemtoReg),
.o(w_reg_data)
);
// reg write port addr
mux4to1_5 mux_w_reg_addr(
.a(reg_Rt_addr_B), // dst rt
.b(reg_rd_addr), // dst rd
.c(5'b11111), // $ra
.d(5'b00000), // useless
.sel(RegDst),
.o(reg_Wt_addr)
);
//ALU path
mux2to1_32 mux_Alu_A(
.a(rdata_A),
.b(PC_Current),
.sel(ALUSrcA),
.o(Alu_A)
);
mux4to1_32 mux_Alu_B(
.a(rdata_B),
.b(32'h00000004), // pc_next
.c({{16{imm[15]}},imm}), //sign-extended imm
.d({{14{imm[15]}},imm,2'b00}), // offset beq, bne
.sel(ALUSrcB),
.o(Alu_B)
);
//pc Generator
assign modificative=PCWrite||(PCWriteCond&&(~(zero||Beq)|(zero&&Beq)));
//(PCWriteCond&&zero)
always @(posedge clk or posedge reset)begin
if (reset==1) // reset
PC_Current<=32'h00000000;
else if (modificative==1)begin
case(PCSource)
2'b00: if (MIO_ready) PC_Current <= res; // PC+4
2'b01: PC_Current <= ALU_Out; // branch
2'b10: PC_Current <= {PC_Current[31:28],Inst_R[25:0],2'b00}; // jump
2'b11: PC_Current <= ALU_Out; // jr
endcase
end
end
//memory path
assign data_out=rdata_B;
mux2to1_32 mux_M_addr (
.a(ALU_Out),
.b(PC_Current),
.sel(IorD),
.o(M_addr)
);
endmodule
module ctrl(
clk,
reset,
Inst_in,
zero,
overflow,
MIO_ready,
MemRead,
MemWrite,
ALU_operation,
state_out,
CPU_MIO,
IorD,
IRWrite,
RegDst,
RegWrite,
MemtoReg,
ALUSrcA,
ALUSrcB,
PCSource,
PCWrite,
PCWriteCond,
Beq
);
input clk,reset;
input zero,overflow,MIO_ready;
input [31:0] Inst_in;
output [2:0] ALU_operation;
output CPU_MIO,MemRead,MemWrite,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq;
output [4:0] state_out;
output [1:0] RegDst,MemtoReg,ALUSrcB,PCSource;
wire [4:0] state_out;
wire reset,MIO_ready;
reg CPU_MIO,MemRead,MemWrite,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq;
reg [1:0] RegDst,MemtoReg,ALUSrcB,PCSource;
reg [2:0] ALU_operation;
reg [4:0] state;
parameter
IF = 5'b00000,
ID = 5'b00001,
EX_R = 5'b00010,
EX_Mem =5'b00011,
EX_I = 5'b00100,
Lui_WB = 5'b00101,
EX_beq = 5'b00110,
EX_bne = 5'b00111,
EX_jr = 5'b01000,
EX_JAL = 5'b01001,
EX_jalr = 5'b10000,
Exe_J = 5'b01010,
MEM_RD = 5'b01011,
MEM_WD = 5'b01100,
WB_R = 5'b01101,
WB_I = 5'b01110,
WB_LW = 5'b01111,
Error = 5'b11111;
parameter
AND = 3'b000,
OR = 3'b001,
ADD = 3'b010,
SUB = 3'b110,
NOR = 3'b100,
SLT = 3'b111,
XOR = 3'b011,
SRL = 3'b101;
`define CPU_ctrl_signals {PCWrite,PCWriteCond,IorD,MemRead,MemWrite,IRWrite,MemtoReg,PCSource,ALUSrcB,ALUSrcA,RegWrite,RegDst, CPU_MIO}
assign state_out=state;
initial begin
`CPU_ctrl_signals<=17'h12821; //12821
ALU_operation<=ADD;
state <= IF;
end
always @(posedge clk or posedge reset)
if (reset==1) begin
`CPU_ctrl_signals<=17'h12821; //12821
ALU_operation<=ADD;
state <= IF;
end else
case (state)
IF: begin
if(MIO_ready)begin
`CPU_ctrl_signals<=17'h00060;
ALU_operation<=ADD;
state <= ID;
end
else begin
state <=IF; `CPU_ctrl_signals<=17'h12821;
end
end
ID: begin
case (Inst_in[31:26])
6'b000000: begin
`CPU_ctrl_signals<=17'h00010;
state <= EX_R;
case (Inst_in[5:0])
6'b100000: ALU_operation<=ADD;
6'b100010: ALU_operation<=SUB;
6'b100100: ALU_operation<=AND;
6'b100101: ALU_operation<=OR;
6'b100111: ALU_operation<=NOR;
6'b101010: ALU_operation<=SLT;
6'b000010: ALU_operation<=SRL; //shfit 1bit right
6'b100110: ALU_operation<=XOR;
6'b001000: begin
`CPU_ctrl_signals<=17'h10010;
ALU_operation<=ADD;
state <= EX_jr;
end
6'b001001:begin
`CPU_ctrl_signals<=17'h00208; //rd << current_pc==ori_pc+4
ALU_operation<=ADD;
state <=EX_jalr;
end
default: ALU_operation <= ADD;
endcase
end
6'b100011: begin //Lw
`CPU_ctrl_signals<=17'h00050;
ALU_operation<=ADD;
state <= EX_Mem;
end
6'b101011:begin //Sw
`CPU_ctrl_signals<=17'h00050;
ALU_operation<=ADD;
state <= EX_Mem;
end
6'b000010:begin //Jump
`CPU_ctrl_signals<=17'h10160;
state <= Exe_J;
end
6'b000011:begin //Jal
`CPU_ctrl_signals<=17'h1076c;
state <= EX_JAL;
end
6'b000100:begin //Beq
`CPU_ctrl_signals<=17'h08090;
Beq<=1;
ALU_operation<= SUB;
state <= EX_beq;
end
6'b000101:begin //Bne
`CPU_ctrl_signals<=17'h08090;
Beq<=0;
ALU_operation<= SUB;
state <= EX_bne;
end
6'b001000:begin //Addi
`CPU_ctrl_signals<=17'h00050;
ALU_operation <= ADD;
state <= EX_I;
end
6'b001100:begin //Andi
`CPU_ctrl_signals<=17'h00050;
ALU_operation <= AND;
state <= EX_I;
end
6'b001101:begin //Ori
`CPU_ctrl_signals<=17'h00050;
ALU_operation <= OR;
state <= EX_I;
end
6'b001110:begin //Xori
`CPU_ctrl_signals<=17'h00050;
ALU_operation <= XOR;
state <= EX_I;
end
6'b001010:begin //Slti
`CPU_ctrl_signals<=17'h00050;
ALU_operation <= SLT;
state <= EX_I;
end
6'b001111:begin //Lui
`CPU_ctrl_signals<=17'h00468;
state <= Lui_WB;
end
default: begin
`CPU_ctrl_signals<=17'h12821;
state <= Error;
end
endcase
end //end ID
EX_jalr:begin
`CPU_ctrl_signals<=17'h10018;
ALU_operation<=ADD; state <= EX_jr;
end
EX_Mem: begin
if (Inst_in[31:26]==6'b100011) begin
`CPU_ctrl_signals<=17'h06051;
state <= MEM_RD;
end else if (Inst_in[31:26]==6'b101011) begin
`CPU_ctrl_signals<=17'h05051;
state <= MEM_WD;
end
end
MEM_RD: begin
if (MIO_ready) begin
`CPU_ctrl_signals<=17'h00208; state <= WB_LW;
end else begin
state <=MEM_RD;
`CPU_ctrl_signals<=17'h06050;
end
end
MEM_WD:begin
if(MIO_ready)begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD;
state <= IF;
end else begin
state <=MEM_WD;
`CPU_ctrl_signals<=17'h05050;
end
end
WB_LW:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <=IF; end
EX_R:begin
`CPU_ctrl_signals<=17'h0001a; state <= WB_R; end
EX_I:begin
`CPU_ctrl_signals<=17'h00058; state <= WB_I; end
WB_R:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
WB_I:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
Exe_J:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
EX_bne:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
EX_beq:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
EX_jr:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
EX_JAL:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
Lui_WB:begin
`CPU_ctrl_signals<=17'h12821;
ALU_operation<=ADD; state <= IF; end
Error: state <= Error;
default: begin
`CPU_ctrl_signals<=17'h12821;
Beq<=0;ALU_operation<=ADD;
state <= Error;
end
endcase
endmodule
module Muliti_cycle_Cpu(
clk,
reset,
MIO_ready,
pc_out, //TEST
Inst, //TEST
mem_w,
Addr_out,
data_out,
data_in,
CPU_MIO,
state
);
input clk,reset,MIO_ready;
output [31:0] pc_out;
output [31:0] Inst;
output mem_w, CPU_MIO;
output [31:0] Addr_out;
output [31:0] data_out;
output [4:0] state;
input [31:0] data_in;
wire [31:0] Inst,Addr_out,PC_Current,pc_out,data_in,data_out;
wire [4:0] state;
wire [2:0] ALU_operation;
wire [1:0] RegDst,MemtoReg,ALUSrcB,PCSource;
wire CPU_MIO,MemRead,MemWrite,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq;
wire reset,MIO_ready, mem_w,zero,overflow;
// assign rst=reset;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
ctrl x_ctrl(
.clk(clk),
.reset(reset),
.Inst_in(Inst),
.zero(zero),
.overflow(overflow),
.MIO_ready(MIO_ready),
.MemRead(MemRead),
.MemWrite(MemWrite),
.ALU_operation(ALU_operation),
.state_out(state),
.CPU_MIO(CPU_MIO),
.IorD(IorD),
.IRWrite(IRWrite),
.RegDst(RegDst),
.RegWrite(RegWrite),
.MemtoReg(MemtoReg),
.ALUSrcA(ALUSrcA),
.ALUSrcB(ALUSrcB),
.PCSource(PCSource),
.PCWrite(PCWrite),
.PCWriteCond(PCWriteCond),
.Beq(Beq)
);
data_path x_datapath(
.clk(clk),
.reset(reset),
.MIO_ready(MIO_ready),
.IorD(IorD),
.IRWrite(IRWrite),
.RegDst(RegDst),
.RegWrite(RegWrite),
.MemtoReg(MemtoReg),
.ALUSrcA(ALUSrcA),
.ALUSrcB(ALUSrcB),
.PCSource(PCSource),
.PCWrite(PCWrite),
.PCWriteCond(PCWriteCond),
.Beq(Beq),
.ALU_operation(ALU_operation),
.PC_Current(PC_Current),
.data2CPU(data_in),
.Inst_R(Inst),
.data_out(data_out),
.M_addr(Addr_out),
.zero(zero),
.overflow(overflow)
);
assign mem_w=MemWrite&&(~MemRead);
assign pc_out=PC_Current;
endmodule
module Top_Muliti_IOBUS(
clk_50mhz,
BTN,
SW,
LED,
SEGMENT,
AN_SEL
);
input clk_50mhz;
input [3:0] BTN;
input [7:0] SW;
output [7:0] LED,SEGMENT;
output [3:0] AN_SEL;
wire Clk_CPU, rst,clk_m, mem_w,data_ram_we,GPIOf0000000_we,GPIOe0000000_we,counter_we;
wire counter_OUT0,counter_OUT1,counter_OUT2;
wire [1:0] Counter_set;
wire [4:0] state;
wire [3:0] digit_anode,blinke;
wire [3:0] button_out;
wire [7:0] SW_OK,SW,led_out,LED,SEGMENT; //led_out is current LED light
wire [9:0] rom_addr,ram_addr;
wire [21:0] GPIOf0;
wire [31:0] pc,Inst,addr_bus,Cpu_data2bus,ram_data_out,disp_num;
wire [31:0] clkdiv,Cpu_data4bus,counter_out,ram_data_in,Peripheral_in;
wire MIO_ready;
wire CPU_MIO;
assign MIO_ready=~button_out[1];
assign rst=button_out[3];
assign SW2=SW_OK[2];
assign LED={led_out[7]|Clk_CPU,led_out[6:0]};
assign clk_m=~clk_50mhz;
assign rom_addr=pc[11:2];
assign AN_SEL=digit_anode;
assign clk_io=~Clk_CPU;
seven_seg_dev seven_seg(
.disp_num(disp_num),
.clk(clk_50mhz),
.clr(rst),
.SW(SW_OK[1:0]),
// .Scanning(clkdiv[19:18]),
.SEGMENT(SEGMENT),
.AN(digit_anode)
);
BTN_Anti_jitter BTN_OK (button_out, SW_OK, clk_50mhz, BTN,SW );
clk_div div_clk(clk_50mhz,rst, SW2, clkdiv, Clk_CPU ); // Clock divider
Muliti_cycle_Cpu muliti_cycle_cpu(
.clk(Clk_CPU),
.reset(rst),
.MIO_ready(MIO_ready), //MIO_ready
.pc_out(pc), //Test
.Inst(Inst), //Test
.mem_w(mem_w),
.Addr_out(addr_bus),
.data_out(Cpu_data2bus),
.data_in(Cpu_data4bus),
.CPU_MIO(CPU_MIO),
.state(state) //Test
);
Mem_B RAM_I_D(
.clka(clk_m),
.wea(data_ram_we),
.addra(ram_addr),
.dina(ram_data_in),
.douta(ram_data_out)
);
MIO_BUS MIO_interface(
.clk(clk_50mhz),
.rst(rst),
.BTN(botton_out),
.SW(SW_OK),
.mem_w(mem_w),
.Cpu_data2bus(Cpu_data2bus),
.addr_bus(addr_bus),
.ram_data_out(ram_data_out),
.led_out(led_out),
.counter_out(counter_out),
.counter0_out(counter_OUT0),
.counter1_out(counter_OUT1),
.counter2_out(counter_OUT2),
.Cpu_data4bus(Cpu_data4bus),
.ram_data_in(ram_data_in),
.ram_addr(ram_addr),//Memory Address signals
.data_ram_we(data_ram_we),
.GPIOf0000000_we(GPIOf0000000_we),
.GPIOe0000000_we(GPIOe0000000_we),
.counter_we(counter_we),
.Peripheral_in(Peripheral_in)
);
led_Dev_IO Device_led(
clk_io,
rst,
GPIOf0000000_we,
Peripheral_in,
Counter_set,
led_out,
GPIOf0
);
seven_seg_Dev_IO Device_7seg(
.clk(clk_io),
.rst(rst),
.GPIOe0000000_we(GPIOe0000000_we),
.Test(SW_OK[7:5]),
.disp_cpudata(Peripheral_in), //CPU data output
.Test_data0({2'b00,pc[31:2]}), //pc[31:2]
.Test_data1(counter_out), //counter
.Test_data2(Inst), //Inst
.Test_data3(addr_bus), //addr_bus
.Test_data4(Cpu_data2bus), //Cpu_data2bus;
.Test_data5(Cpu_data4bus), //Cpu_data4bus;
.Test_data6(pc),
.disp_num(disp_num)
);
Counter_x Counter_xx(.clk(clk_io),
.rst(rst),
.clk0(clkdiv[9]),
.clk1(clkdiv[10]),
.clk2(clkdiv[10]),
.counter_we(counter_we),
.counter_val(Peripheral_in),
.counter_ch(Counter_set),
.counter0_OUT(counter_OUT0),
.counter1_OUT(counter_OUT1),
.counter2_OUT(counter_OUT2),
.counter_out(counter_out)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ifu_top
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ifu_top.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ifu_top.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ifu_top
//
// No user `defines in this module
module ifu_top
//
// Generated Module ifu_top_i1
//
(
nreset // Async. Reset (CGU,PAD)
);
// Generated Module Inputs:
input nreset;
// Generated Wires:
wire nreset;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ifu_top
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_PP_SYMBOL_V
`define SKY130_FD_SC_LP__OR3_PP_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A211OI_PP_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a211oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_PP_SYMBOL_V
|
`timescale 1 ns / 1 ps
//
// KIA registers
//
`define KQSTAT 0
`define KQDATA 1
// KIA status flag bits
`define KQSF_EMPTY 8'h01
`define KQSF_FULL 8'h02
module TEST_UNIT_KIA;
// To test the KIA, we need a Wishbone bus.
reg CLK_O;
reg RES_O;
// The KIA will communicate with the microprocessor through
// a typical memory bus interface.
reg [0:0] ADR_O;
reg WE_O;
reg CYC_O;
reg STB_O;
wire ACK_I;
wire [7:0] DAT_I;
// The KIA must also talk to a keyboard.
reg C_O;
reg D_O;
// This register is used to identify a specific test in progress.
// This eases correspondence between waveform traces and their
// corresponding (successful) tests.
reg [15:0] STORY_O;
// The KIA under test.
KIA_M kia(
.CLK_I(CLK_O),
.RES_I(RES_O),
.ADR_I(ADR_O),
.WE_I(WE_O),
.CYC_I(CYC_O),
.STB_I(STB_O),
.ACK_O(ACK_I),
.DAT_O(DAT_I),
.D_I(D_O),
.C_I(C_O)
);
always begin
#50 CLK_O <= ~CLK_O;
end;
initial begin
RES_O <= 0;
CLK_O <= 0;
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 0;
STB_O <= 0;
D_O <= 1;
C_O <= 1;
wait(CLK_O);
wait(~CLK_O);
// AS A systems programmer
// I WANT the KIA to report an empty queue after reset
// SO THAT I can start the operating system with a clean slate.
STORY_O <= 0;
RES_O <= 1;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h01) begin
$display("Expected queue to be empty."); $stop;
end
// AS A systems programmer
// I WANT the KIA to report a non-empty queue after receiving a keycode
// SO THAT I can pull the key code from the queue.
STORY_O <= 16'h0010;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h00) begin
$display("Expected queue to be neither full nor empty."); $stop;
end
// AS A systems programmer
// I WANT the keyboard queue to faithfully record the received scan code
// SO THAT I can respond intelligently to user input.
STORY_O <= 16'h0020;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h1B) begin
$display("Head of the queue doesn't have the right data byte."); $stop;
end
// AS A systems programmer
// I WANT the queue to capture multiple data bytes while I'm busy
// SO THAT I don't have to have such stringent real-time requirements.
STORY_O <= 16'h0030;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'hE0) begin
$display("Expected 8'hE0 for first byte."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h1B) begin
$display("Expected 8'h1B for second byte."); $stop;
end
// AS A verilog engineer
// I WANT the KIA to drop excess characters when the queue is full
// SO THAT software engineers don't have to worry about key-code order issues.
STORY_O <= 16'h0040;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE0) begin
$display("Pattern mismatch on byte 0."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE1) begin
$display("Pattern mismatch on byte 1."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE2) begin
$display("Pattern mismatch on byte 2."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE3) begin
$display("Pattern mismatch on byte 3."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE4) begin
$display("Pattern mismatch on byte 4."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE5) begin
$display("Pattern mismatch on byte 5."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE6) begin
$display("Pattern mismatch on byte 6."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE7) begin
$display("Pattern mismatch on byte 7."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE8) begin
$display("Pattern mismatch on byte 8."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE9) begin
$display("Pattern mismatch on byte 9."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEA) begin
$display("Pattern mismatch on byte A."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEB) begin
$display("Pattern mismatch on byte B."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEC) begin
$display("Pattern mismatch on byte C."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hED) begin
$display("Pattern mismatch on byte D."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEE) begin
$display("Pattern mismatch on byte E."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hCF) begin
$display("Pattern mismatch on byte F."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hCF) begin
$display("Should not be able to read beyond the bottom of the queue."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
// AS A software engineer
// I WANT the KIA to indicate the queue is empty after reading the last available byte
// SO THAT my keyboard handling loops have an exit criterion.
STORY_O <= 16'h0050;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
WE_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `KQSF_FULL) begin
$display("Before popping first byte, queue must be full."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 1."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 2."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 3."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 4."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 5."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 6."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 7."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 8."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 9."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte A."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte B."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte C."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte D."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte E."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `KQSF_EMPTY) begin
$display("After reading 15 bytes, the queue should be empty."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `KQSF_EMPTY) begin
$display("Popping an empty queue should have no effect."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
// AS A verilog engineer
// I WANT the end of all tests to be delineated on the waveform
// SO THAT I don't have to hunt around for the end of the test sequence.
STORY_O <= -1;
wait(CLK_O); wait(~CLK_O);
$stop;
end;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts resamples the chroma components of a video in *
* stream, whos colour space is YCrCb. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_chroma_resampler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15; // Incoming frame's data width
parameter ODW = 23; // Outcoming frame's data width
parameter IEW = 0; // Incoming frame's empty width
parameter OEW = 1; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
reg [ 7: 0] saved_CrCb;
reg cur_is_Cr_or_Cb;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
saved_CrCb <= 8'h00;
else if (stream_in_ready & stream_in_startofpacket)
saved_CrCb <= 8'h00;
else if (transfer_data & valid)
saved_CrCb <= data[15: 8];
end
always @(posedge clk)
begin
if (reset)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready & stream_in_startofpacket)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready)
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb ^ 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = (cur_is_Cr_or_Cb) ? data[15: 8] : saved_CrCb;
assign converted_data[15: 8] = (cur_is_Cr_or_Cb) ? saved_CrCb : data[15: 8];
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard ([email protected])
// 2013 Aaron Dahlen
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
//** INSTANTIATION ********************************************
//
// To instantiate this module copy this section to your main code...
//
// uart #(
// .baud_rate(baud_rate), // default is 9600
// .sys_clk_freq(sys_clk_freq) // default is 100000000
// )
// instance_name(
// .clk(clk), // The master clock for this module
// .rst(rst), // Synchronous reset
// .rx(rx), // Incoming serial line
// .tx(tx), // Outgoing serial line
// .transmit(transmit), // Signal to transmit
// .tx_byte(tx_byte), // Byte to transmit
// .received(received), // Indicated that a byte has been received
// .rx_byte(rx_byte), // Byte received
// .is_receiving(is_receiving), // Low when receive line is idle
// .is_transmitting(is_transmitting),// Low when transmit line is idle
// .recv_error(recv_error) // Indicates error in receiving packet.
// //.recv_state(recv_state), // for test bench
// //.tx_state(tx_state) // for test bench
// );
//
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Assert to begin transmission
input [7:0] tx_byte, // Byte to transmit
output received, // Indicates that a byte has been received
output [7:0] rx_byte, // Byte received
output wire is_receiving, // Low when receive line is idle.
output wire is_transmitting,// Low when transmit line is idle.
output wire recv_error, // Indicates error in receiving packet.
output reg [3:0] rx_samples,
output reg [3:0] rx_sample_countdown
);
// The clock_divider is calculated using baud_rate and sys_clk_freq.
// To modify baud rate you can modify the defaults shown below or instantiate
// the module using the template shown in the INSTANTIATION section above.
// For aditional information about instantiation please see:
// http://www.sunburst-design.com/papers/CummingsHDLCON2002_Parameters_rev1_2.pdf
parameter baud_rate = 9600;
parameter sys_clk_freq = 100000000;
localparam one_baud_cnt = sys_clk_freq / (baud_rate);
//** SYMBOLIC STATE DECLARATIONS ******************************
localparam [2:0]
RX_IDLE = 3'd0,
RX_CHECK_START = 3'd1,
RX_SAMPLE_BITS = 3'd2,
RX_READ_BITS = 3'd3,
RX_CHECK_STOP = 3'd4,
RX_DELAY_RESTART = 3'd5,
RX_ERROR = 3'd6,
RX_RECEIVED = 3'd7;
localparam [1:0]
TX_IDLE = 2'd0,
TX_SENDING = 2'd1,
TX_DELAY_RESTART = 2'd2,
TX_RECOVER = 2'd3;
//** SIGNAL DECLARATIONS **************************************
reg [log2(one_baud_cnt * 16)-1:0] rx_clk;
reg [log2(one_baud_cnt)-1:0] tx_clk;
reg [2:0] recv_state = RX_IDLE;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
//** ASSIGN STATEMENTS ****************************************
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
//** TASKS / FUNCTIONS ****************************************
function integer log2(input integer M);
integer i;
begin
log2 = 1;
for (i = 0; 2**i <= M; i = i + 1)
log2 = i + 1;
end endfunction
//** Body *****************************************************
always @(posedge clk) begin
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
// Countdown timers for the receiving and transmitting
// state machines are decremented.
if(rx_clk) begin
rx_clk = rx_clk - 1'd1;
end
if(tx_clk) begin
tx_clk = tx_clk - 1'd1;
end
//** Receive state machine ************************************
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait 1/2 of the bit period
rx_clk = one_baud_cnt / 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_clk) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period plus 3/8 of the next
rx_clk = (one_baud_cnt / 2) + (one_baud_cnt * 3) / 8;
rx_bits_remaining = 8;
recv_state = RX_SAMPLE_BITS;
rx_samples = 0;
rx_sample_countdown = 5;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_SAMPLE_BITS: begin
// sample the rx line multiple times
if (!rx_clk) begin
if (rx) begin
rx_samples = rx_samples + 1'd1;
end
rx_clk = one_baud_cnt / 8;
rx_sample_countdown = rx_sample_countdown -1'd1;
recv_state = rx_sample_countdown ? RX_SAMPLE_BITS : RX_READ_BITS;
end
end
RX_READ_BITS: begin
if (!rx_clk) begin
// Should be finished sampling the pulse here.
// Update and prep for next
if (rx_samples > 3) begin
rx_data = {1'd1, rx_data[7:1]};
end else begin
rx_data = {1'd0, rx_data[7:1]};
end
rx_clk = (one_baud_cnt * 3) / 8;
rx_samples = 0;
rx_sample_countdown = 5;
rx_bits_remaining = rx_bits_remaining - 1'd1;
if(rx_bits_remaining)begin
recv_state = RX_SAMPLE_BITS;
end else begin
recv_state = RX_CHECK_STOP;
rx_clk = one_baud_cnt / 2;
end
end
end
RX_CHECK_STOP: begin
if (!rx_clk) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_clk = 8 * sys_clk_freq / (baud_rate);
recv_state = RX_DELAY_RESTART;
end
// why is this state needed? Why not go to idle and wait for next?
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_clk ? RX_DELAY_RESTART : RX_IDLE;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
//** Transmit state machine ***********************************
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
// tx_clk_divider = clock_divide;
tx_clk = one_baud_cnt;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_clk) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1'd1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_clk = one_baud_cnt;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_clk = 16 * one_baud_cnt;// tx_countdown = 16;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_clk ? TX_DELAY_RESTART : TX_RECOVER;// TX_IDLE;
end
TX_RECOVER: begin
// Wait unitil the transmit line is deactivated. This prevents repeated characters
tx_state = transmit ? TX_RECOVER : TX_IDLE;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:28:25 03/19/2013
// Design Name:
// Module Name: NERP_demo_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Game(
input wire clk, //master clock = 100MHz
input wire clr, //right-most pushbutton for reset
input wire [4:0] sw, // Controls the input move number, AI difficulty
input wire btnInput, // Middle Button
input wire btnReset, // Top Button
//output wire [6:0] seg, //7-segment display LEDs
//output wire [3:0] an, //7-segment display anode enable
//output wire dp, //7-segment display decimal point
output wire [2:0] red, //red vga output - 3 bits
output wire [2:0] green,//green vga output - 3 bits
output wire [1:0] blue, //blue vga output - 2 bits
output wire hsync, //horizontal sync out
output wire vsync, //vertical sync out
output wire [7:0] seg,
output wire [3:0] an
);
// VGA display clock interconnect
wire pix_en;
wire logic_en;//logic clock interconnect
wire logic_en_delay;//logic clock interconnect
wire display_en;
reg rst_vga;
reg rst_ff;
always @(posedge clk or posedge clr) begin
if (clr) begin
{rst_vga,rst_ff} <= 2'b11;
end
else begin
{rst_vga,rst_ff} <= {rst_ff,1'b0};
end
end
// generate 7-segment clock & display clock
clockdiv U1(
.clk(clk),
.rst(rst_vga),
.logic_en(logic_en),
.logic_en_1(logic_en_delay),
.pix_en(pix_en),
.display_en(display_en)
);
/* DEBOUCNING INPUT */
wire btnMove_sync;
wire rst;
wire AI_switch;
wire switch1, switch2, switch3, switch4;
Synchronizer rst_sync(
.clk(clk),
.async_in(btnReset),
.reset(1'b0),
.synch_out(rst)
);
Synchronizer input_move_sync(
.clk(clk),
.async_in(btnInput),
.reset(rst),
.synch_out(btnMove_sync)
);
Synchronizer AI_sw_sync(
.clk(clk),
.async_in(sw[0]),
.reset(rst),
.synch_out(AI_switch)
);
// syncrhonize user's move input
Synchronizer input1_sw_sync(
.clk(clk),
.async_in(sw[1]),
.reset(rst),
.synch_out(switch1)
);
Synchronizer input2_sw_sync(
.clk(clk),
.async_in(sw[2]),
.reset(rst),
.synch_out(switch2)
);
Synchronizer input3_sw_sync(
.clk(clk),
.async_in(sw[3]),
.reset(rst),
.synch_out(switch3)
);
Synchronizer input4_sw_sync(
.clk(clk),
.async_in(sw[4]),
.reset(rst),
.synch_out(switch4)
);
wire move; // Player indicates they want to make a move - debounced btnInput rising edge
Debouncer deb_S(
.clk(clk),
.clk2(logic_en),
.real_btn_input(btnMove_sync),
.debounced_btn_input(move)
);
reg [3:0] nextMove;
always @(*)
begin nextMove = {switch4, switch3, switch2, switch1};
end
wire [8:0] X_state;
wire [8:0] O_state;
wire [2:0] GameStatus;
wire [8:0] AIMove;
wire [8:0] AIMove_hard;
//
//
// wire player;
SimpleAI sa(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove)
);
LookupTableAI hard_ai(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove_hard)
);
wire [7:0] numWins;
GameState state(
.rst(rst),
.move(move),
.clk(logic_en_delay),
.nextMove(nextMove),
.AISwitch(AI_switch),
.AIMove(AIMove),
.AIMove_Hard(AIMove_hard),
// .player(player),
.X_state(X_state),
.O_state(O_state),
.GameStatus(GameStatus),
.numWins(numWins)
);
// VGA controller
vga640x480 U3(
.pix_en(pix_en),
.clk(clk),
.rst(rst_vga),
.o_vec(O_state),
.x_vec(X_state),
.game_status(GameStatus),
.hsync(hsync),
.vsync(vsync),
.red(red),
.green(green),
.blue(blue)
);
Display d(
.Value(numWins),
.clk(display_en),
.seg(seg),
.an(an)
);
// Display Module
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V |
`timescale 1 ns / 1 ps
module myip_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule
|
(*
Copyright 2014 Cornell University
Copyright 2015 Cornell University
Copyright 2016 Cornell University
Copyright 2017 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Websites: http://nuprl.org/html/verification/
http://nuprl.org/html/Nuprl2Coq
https://github.com/vrahli/NuprlInCoq
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export terms2.
Require Export terms_tacs.
Require Export lmap.
(** printing # $\times$ #×# *)
(** printing $ $\times$ #×# *)
(** printing <=> $\Leftrightarrow$ #⇔# *)
(** printing & $\times$ #×# *)
(* ---- substitution: td[x\ts] *) (*(\x.x+1)(x+2)*)
(*(\y.y+z)[z->y]*)
(** The goal of this section is to formalize the notion of simultaneous
substitution([lsubst]) and alpha equality [alpha_eq].
We needed many properties about substitution and alpha equality
to formalize all of Nuprl. Proofs of all these properties run into
several thousands of lines and took us several weeks to finish.
These proofs are independent
of the operators of the language and will work unchanged
even if we formalize some different language, e.g. first order logic
by merely changing the definition of [Opid]. Thus, we believe
that we have accidentally created a fairly general-purpose
library for nominal reasoning about virtually any language. *)
(** ** Substitution*)
(** The Substitution operation
is a key concept in functional languages.
Among other things, it is required to define the
computation system and the semantics of dependent types.
The goal of this subsection is to formalize [lsubst], a function
that simultaneously substitutes some variables for some terms.
We define a Substitution as a list of pairs:
[[
Definition Substitution : Set := list (NVar # NTerm).
]]
*)
(* begin hide *)
Definition Substitution {p} : tuniv := lmap NVar (@NTerm p).
Definition WfSubstitution {p} : tuniv := lmap NVar (@WTerm p).
Definition CSubstitution {p} : tuniv := lmap NVar (@CTerm p).
(* end hide *)
(** % \noindent %
The function [var_ren] below provides a way to
define the specialized substitutions that are
variable renamings (substituting one variable for another).
The %\coqslibref{combine}{Coq.Lists.List}{\coqdocdefinition{combine}}% function
from the standard library takes two lists and zips them up.
*)
Definition var_ren {p} (lvo lvn : list NVar) : @Substitution p :=
combine lvo (map vterm lvn).
(* begin hide *)
Lemma var_ren_nil_l {p} :
forall vs, @var_ren p [] vs = [].
Proof. sp. Qed.
Lemma var_ren_nil_r {p} :
forall vs, @var_ren p vs [] = [].
Proof.
induction vs; simpl; sp.
Qed.
Lemma var_ren_cons {p} :
forall v1 v2 vs1 vs2,
@var_ren p (v1 :: vs1) (v2 :: vs2)
= (v1, vterm v2) :: (var_ren vs1 vs2).
Proof. sp. Qed.
Lemma fold_var_ren {p} :
forall lvo lvn, combine lvo (map vterm lvn) = @var_ren p lvo lvn.
Proof. sp. Qed.
(* end hide *)
(** % \noindent \\* %
The domain and range of a substitution are defined as follows:
[[
Definition dom_sub (sub : Substitution) : list NVar := map (fun x => fst x) sub.
]]
*)
(* begin hide *)
Definition Sub {p} := @Substitution p.
Definition CSub {p} := @CSubstitution p.
Definition dom_sub {p} : @Substitution p -> (list NVar):= @dom_lmap NVar NTerm.
Definition dom_csub {p} (sub : @CSubstitution p) := map (fun x => fst x) sub.
Definition wf_dom_sub {p} (sub : @WfSubstitution p) := map (fun x => fst x) sub.
(* end hide *)
Definition range {p} (sub : @Substitution p) : list NTerm := map (fun x => snd x) sub.
(** % \noindent \\*%
We need to define some helper functions before defining the
substitution function that simultaneously substitutes the
in the first component([NVar]s) of the pairs with the second ones([NTerm]s).
*)
(* begin hide *)
Definition crange {p} (sub : @CSubstitution p) : list CTerm := map (fun x => snd x) sub.
(*
Lemma deq_in_sub {p} :
dec_consts p
-> forall v t (sub : @Substitution p),
LIn (v,t) sub + !LIn (v,t) sub.
Proof.
introv dc; introv.
apply in_deq; sp.
apply deq_prod; sp; try (apply deq_nvar); try (apply deq_nterm).
Qed.
*)
Definition sub_range_sat {p} (sub: @Substitution p) (P: NTerm -> Type) :=
forall v t, LIn (v,t) sub -> P t.
(*
Definition sub_range_satb {p} (dc : dec_consts p) (sub: @Substitution p) (P: NTerm -> Type) :=
forall t, assert (memberb (deq_nterm dc) t (range sub)) -> P t.
*)
Lemma in_range {p} :
forall t sub, LIn t (@range p sub) -> {v : NVar $ LIn (v,t) sub}.
Proof.
induction sub; allsimpl; sp; allsimpl; subst.
exists a0; sp.
exists v; sp.
Qed.
(*
Lemma in_range_t {p} :
dec_consts p
-> forall (t : @NTerm p) sub, LIn t (range sub) -> {v : NVar & LIn (v,t) sub}.
Proof.
introv dc i.
rw <- (@assert_memberb (@NTerm p) (deq_nterm dc)) in i.
induction sub; allsimpl; sp; allsimpl.
unfold assert in i; sp.
destruct (deq_nterm dc a t); subst; sp.
exists a0; sp.
exists v; sp.
Qed.
Lemma in_range_t_iff {p} :
dec_consts p
-> forall (t : @NTerm p) sub, LIn t (range sub) <=> {v : NVar & LIn (v,t) sub}.
Proof.
introv dc; introv; split; intro k.
apply in_range_t; auto.
exrepnd.
unfold range.
rw in_map_iff.
exists (v,t); auto.
Qed.
*)
(*
Lemma sub_range_sat_implies_b {p} :
forall dc : dec_consts p,
forall sub P,
@sub_range_sat p sub P -> sub_range_satb dc sub P.
Proof.
unfold sub_range_sat, sub_range_satb; introv s a.
rw (@assert_memberb (@NTerm p) (deq_nterm dc)) in a.
allapply (@in_range_t p dc); sp.
discover; sp.
Qed.
*)
Lemma sub_range_sat_implies {p} :
forall (P Q : @NTerm p -> Type),
(forall t, P t -> Q t)
-> forall sub,
sub_range_sat sub P
-> sub_range_sat sub Q.
Proof.
introv Himp Hsat Hin. apply Hsat in Hin.
apply Himp in Hin. sp.
Qed.
Definition prog_sub {p} (sub : @Substitution p) := sub_range_sat sub isprogram.
Definition wf_sub {p} (sub : @Substitution p) := sub_range_sat sub nt_wf.
Lemma wf_sub_nil {o} : @wf_sub o [].
Proof.
unfold wf_sub, sub_range_sat; simpl; sp.
Qed.
Hint Resolve wf_sub_nil : slow.
Lemma wf_sub_cons {o} :
forall v (t : @NTerm o) sub,
wf_term t -> wf_sub sub -> wf_sub ((v,t) :: sub).
Proof.
introv wt ws.
allunfold @wf_sub.
allunfold @sub_range_sat; simpl; introv k; repndors; ginv.
- rw @nt_wf_eq; auto.
- eapply ws; eauto.
Qed.
Hint Resolve wf_sub_cons : slow.
(* will not specialize this lemma.. those are always trivial*)
Lemma sub_app_sat {p} :
forall P sub1 sub2,
@sub_range_sat p sub1 P
-> sub_range_sat sub2 P
-> sub_range_sat (sub1 ++ sub2) P.
Proof.
introv sat1 sat2 Hin.
apply in_app_iff in Hin.
dorn Hin; [ apply sat1 in Hin | apply sat2 in Hin]; trivial.
Qed.
Lemma sub_app_sat_if {p} :
forall P sub1 sub2,
@sub_range_sat p (sub1 ++ sub2) P
-> sub_range_sat sub1 P # sub_range_sat sub2 P.
Proof.
introv Hsat.
split;
introv Hin;
assert (LIn (v, t) (sub1 ++ sub2))
as Hx
by (apply in_app_iff;((left;sp;fail) || (right;sp;fail)));
apply Hsat in Hx;sp.
Qed.
(* end hide *)
Fixpoint sub_find {p} (sub : @Substitution p) (var : NVar) : option NTerm :=
match sub with
| nil => None
| (v, t) :: xs => if beq_var v var then Some t else sub_find xs var
end.
(* begin hide *)
Lemma beq_deq : forall T v1 v2 (ct cf:T) ,
(if (beq_var v1 v2) then ct else cf) = (if (deq_nvar v1 v2) then ct else cf).
intros. cases_if as Hb; auto; cases_if as Hd ; auto; subst.
apply not_eq_beq_var_false in Hd. rewrite Hd in Hb; sp.
rewrite <- beq_var_refl in Hb. sp.
Qed.
Definition lmap_apply {A : Set} (eqdec: Deq A) (sub: lmap A A) (a:A): A :=
match lmap_find eqdec sub a with
| inl (existT _ a' _) => a'
| inr _ => a
end.
Definition lmap_lapply {A : Set} (eqdec: Deq A) (sub: lmap A A) (la:list A): list A :=
map (fun a:A => lmap_apply eqdec sub a) la.
Definition lvmap_lapply (sub: lmap NVar NVar) (la:list NVar): list NVar :=
map (fun a:NVar => lmap_apply deq_nvar sub a) la.
Lemma sub_lmap_find {p} :
forall sub v,
@sub_find p sub v =
proj_as_option (lmap_find deq_nvar sub v).
Proof.
induction sub as [| a]; intros ; auto; simpl.
destruct a. rewrite beq_deq.
cases_if; subst; auto.
rewrite IHsub. destruct ((lmap_find deq_nvar sub v)); simpl;
try(destruct s; simpl); auto.
Qed.
Lemma sub_lmap_find_first {p} :
forall sub v,
@sub_find p sub v =
proj_as_option (lmap_find_first deq_nvar sub v).
Proof.
induction sub as [| a]; intros ; auto; simpl.
destruct a. rewrite beq_deq.
cases_if; subst; auto.
rewrite IHsub. destruct ((lmap_find_first deq_nvar sub v)); simpl;
exrepnd; auto.
Qed.
(*
Lemma match_sub_lmap_find: forall sub v cs cn,
match (sub_find sub v)
| Some t => cs t
| None => cn
end
=
match (sub_find sub v)
| Some t => cs t
| None => cn
end
*)
Definition csub2sub {p} (sub : @CSubstitution p) : Substitution :=
map (fun x => (fst x, get_cterm (snd x))) sub.
Lemma csub2sub_app {p} :
forall sub1 sub2,
@csub2sub p sub1 ++ csub2sub sub2 = csub2sub (sub1 ++ sub2).
Proof.
unfold csub2sub; sp.
rewrite <- map_app; sp.
Qed.
Lemma csub2sub_snoc {p} :
forall sub v t,
@csub2sub p (snoc sub (v, t)) = snoc (csub2sub sub) (v, get_cterm t).
Proof.
unfold csub2sub; sp.
rewrite map_snoc; sp.
Qed.
Lemma in_csub2sub {p} :
forall sub : @CSubstitution p,
forall v : NVar,
forall u : NTerm,
LIn (v, u) (csub2sub sub)
-> isprogram u.
Proof.
induction sub; simpl; sp; destruct a; allsimpl.
inj.
allrw @isprogram_eq; sp.
apply_in_hyp pp; sp.
Qed.
(* end hide *)
Definition over_vars {p} (vs : list NVar) (sub : @CSubstitution p) :=
subvars vs (dom_csub sub).
(* begin hide *)
Lemma over_vars_proof_irrelevance {p} :
forall vs s,
forall x y : @over_vars p vs s,
x = y.
Proof.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : over_vars ?vs ?s , H2 : over_vars ?vs ?s |- _ ] =>
pose proof (over_vars_proof_irrelevance vs s H2 H1) as h; subst
end : pi.
(* end hide *)
(**
A term [t] is covered by a substitution [sub] if the free variables
of [t] are all in the domain of [sub].
*)
Definition cover_vars {p} (t : @NTerm p) (sub : @CSubstitution p) :=
over_vars (free_vars t) sub.
(* begin hide *)
Lemma cover_vars_proof_irrelevance {p} :
forall t s,
forall x y : @cover_vars p t s,
x = y.
Proof.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : cover_vars ?t ?s , H2 : cover_vars ?t ?s |- _ ] =>
pose proof (cover_vars_proof_irrelevance t s H2 H1) as h; subst
end : pi.
(* end hide *)
(**
We sometimes need the slightly more general definition that
expresses that a term [t] is covered by a substitution [sub] up to a
set of variables [vs], meaning that the free variables of [t] have
to either be in [vs] or in the domain of [sub]. Such a concept is
needed to deal with type families such as function or W types.
*)
Definition cover_vars_upto {p} (t : @NTerm p) (sub : @CSub p) (vs : list NVar) :=
subvars (free_vars t) (vs ++ dom_csub sub).
(* begin hide *)
Lemma cover_vars_upto_proof_irrelevance {p} :
forall t s vs,
forall x y : @cover_vars_upto p t s vs,
x = y.
Proof.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : cover_vars_upto ?t ?s ?vs , H2 : cover_vars_upto ?t ?s ?vs |- _ ] =>
pose proof (cover_vars_upto_proof_irrelevance t s vs H2 H1) as h; subst
end : pi.
Lemma covered_free_from_atom {p} :
forall a b c vs,
@covered p (mk_free_from_atom a b c) vs
<=> covered a vs
# covered b vs
# covered c vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_free_from_atoms {p} :
forall a b vs,
@covered p (mk_free_from_atoms a b) vs
<=> covered a vs
# covered b vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_equality {p} :
forall a b T vs,
@covered p (mk_equality a b T) vs
<=> covered a vs
# covered b vs
# covered T vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_tequality {p} :
forall a b vs,
@covered p (mk_tequality a b) vs
<=> covered a vs
# covered b vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_axiom {p} :
forall vs, @covered p mk_axiom vs.
Proof.
unfold covered; sp; simpl.
Qed.
Hint Immediate covered_axiom.
Lemma covered_uni {p} :
forall vs i, @covered p (mk_uni i) vs.
Proof.
unfold covered; sp; simpl.
Qed.
Hint Immediate covered_uni.
Lemma covered_isect {p} :
forall a v b vs,
@covered p (mk_isect a v b) vs
<=> covered a vs # covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_eisect {p} :
forall a v b vs,
@covered p (mk_eisect a v b) vs
<=> covered a vs # covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_disect {p} :
forall a v b vs,
@covered p (mk_disect a v b) vs
<=> covered a vs # covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_set {p} :
forall a v b vs,
@covered p (mk_set a v b) vs
<=> covered a vs # covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_tunion {p} :
forall a v b vs,
@covered p (mk_tunion a v b) vs
<=> covered a vs # covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_quotient {p} :
forall a v1 v2 b vs,
@covered p (mk_quotient a v1 v2 b) vs
<=> covered a vs # covered b (v1 :: v2 :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_var {p} :
forall v vs, @covered p (mk_var v) vs <=> LIn v vs.
Proof.
unfold covered; sp; simpl.
rw subvars_prop; simpl; split; sp; subst; sp.
Qed.
Lemma covered_subvars {p} :
forall t vs1 vs2,
subvars vs1 vs2
-> @covered p t vs1
-> covered t vs2.
Proof.
intros.
allunfold @covered.
apply subvars_trans with (vs2 := vs1); sp.
Qed.
Lemma covered_snoc_app_weak {p} :
forall t vs1 vs2 v,
@covered p t (vs1 ++ vs2)
-> covered t (snoc vs1 v ++ vs2).
Proof.
sp; allunfold @covered; allrw subvars_prop; sp.
apply_in_hyp pp.
allrw in_app_iff; allrw in_snoc; sp.
Qed.
(* filters out the mappings whose domain lies in vars *)
Fixpoint lmap_filter {A B: Set}
(eqdec: Deq A) (sub: lmap A B) (vars : list A) : lmap A B :=
match sub with
| nil => nil
| (v, t) :: xs =>
if in_deq A eqdec v vars
then lmap_filter eqdec xs vars
else (v, t) :: lmap_filter eqdec xs vars
end.
(* end hide *)
(* removes from sub the variables from vars *)
Fixpoint sub_filter {p} (sub : @Substitution p) (vars : list NVar) : Substitution :=
match sub with
| nil => nil
| (v, t) :: xs =>
if memvar v vars
then sub_filter xs vars
else (v, t) :: sub_filter xs vars
end.
(* begin hide *)
(* Same as sub_filter but on a CSub *)
Fixpoint csub_filter {p} (sub : @CSub p) (vars : list NVar) : CSub :=
match sub with
| nil => nil
| (v, t) :: xs =>
if memvar v vars
then csub_filter xs vars
else (v, t) :: csub_filter xs vars
end.
Lemma sub_filter_csub2sub {p} :
forall sub vs,
@sub_filter p (csub2sub sub) vs
= csub2sub (csub_filter sub vs).
Proof.
induction sub; simpl; sp.
destruct a; allsimpl.
destruct (memvar a0 vs); sp; simpl.
rewrite IHsub; sp.
Qed.
Lemma sub_filter_subset {p} :
forall sub vars,
subset (@sub_filter p sub vars) sub.
Proof.
induction sub; simpl; sp.
destruct (memvar a0 vars).
apply subset_cons1; auto.
apply subset_cons2; auto.
Qed.
Lemma sub_filter_nil_r {p} :
forall sub, @sub_filter p sub [] = sub.
Proof.
induction sub; simpl; sp.
rewrite IHsub; auto.
Qed.
Lemma in_sub_filter {p} :
forall v t sub vars,
LIn (v, t) (@sub_filter p sub vars)
<=>
(
LIn (v, t) sub
#
! LIn v vars
).
Proof.
induction sub; simpl; sp.
split; sp.
boolvar; simpl; allrw; split; sp; cpx.
Qed.
Lemma sub_filter_sat {p} :
forall P sub lv,
@sub_range_sat p sub P
-> sub_range_sat (sub_filter sub lv) P.
Proof. introv Hall hsub. apply in_sub_filter in hsub. repnd.
apply Hall in hsub0; auto.
Qed.
Lemma sub_filter_app {p} :
forall sub1 sub2 vars,
@sub_filter p (sub1 ++ sub2) vars
= sub_filter sub1 vars ++ sub_filter sub2 vars.
Proof.
induction sub1; simpl; sp.
rewrite IHsub1; auto.
destruct (memvar a0 vars); sp.
Qed.
Lemma sub_filter_snoc {p} :
forall sub v t vars,
@sub_filter p (snoc sub (v, t)) vars
= if memvar v vars
then sub_filter sub vars
else snoc (sub_filter sub vars) (v, t).
Proof.
induction sub; simpl; sp; allsimpl.
rewrite IHsub.
destruct (eq_var_dec a0 v); subst.
destruct (memvar v vars); sp.
destruct (memvar v vars); sp.
destruct (memvar a0 vars); sp.
Qed.
Lemma dom_sub_sub_filter {p} :
forall l sub,
remove_nvars l (@dom_sub p sub) = dom_sub (sub_filter sub l).
Proof.
induction sub; simpl; sp; allsimpl.
apply remove_nvars_nil_r.
rewrite remove_nvars_cons_r.
destruct (memvar a0 l); auto.
rewrite IHsub.
simpl; auto.
Qed.
Lemma dom_csub_csub_filter {p} :
forall l sub,
dom_csub (@csub_filter p sub l) = remove_nvars l (dom_csub sub).
Proof.
induction sub; simpl; sp; allsimpl.
rewrite remove_nvars_nil_r; sp.
rewrite remove_nvars_cons_r.
destruct (memvar a0 l); auto; simpl.
rewrite IHsub; auto.
Qed.
Lemma sub_filter_app_r {p} :
forall sub vs1 vs2,
@sub_filter p sub (vs1 ++ vs2)
= sub_filter (sub_filter sub vs1) vs2.
Proof.
induction sub; simpl; sp.
rewrite memvar_app.
destruct (memvar a0 vs1); simpl.
apply IHsub.
destruct (memvar a0 vs2); simpl.
apply IHsub.
rewrite IHsub; auto.
Qed.
Lemma crange_snoc {p} :
forall sub x,
@crange p (snoc sub x) = snoc (crange sub) (snd x).
Proof.
unfold crange; simpl; sp.
rewrite map_snoc; sp.
Qed.
Lemma crange_length {p} :
forall sub,
length (@crange p sub) = length sub.
Proof.
unfold crange; sp.
rewrite map_length; sp.
Qed.
Lemma dom_csub_length {p} :
forall sub,
length (@dom_csub p sub) = length sub.
Proof.
unfold dom_csub; sp.
rewrite map_length; sp.
Qed.
Lemma cover_vars_covered {p} :
forall t sub,
@cover_vars p t sub <=> covered t (dom_csub sub).
Proof.
sp.
Qed.
(** clear_irr removes the duplicates of proofs of propositions that
* have proof irrelevance. *)
Ltac clear_irr :=
repeat match goal with
| [ H1 : covered ?a ?b, H2 : covered ?a ?b |- _ ] =>
assert (H2 = H1) by apply covered_proof_irrelevance; subst
| [ H1 : cover_vars ?a ?b, H2 : cover_vars ?a ?b |- _ ] =>
assert (H2 = H1) by apply cover_vars_proof_irrelevance; subst
| [ H1 : cover_vars_upto ?a ?b ?c, H2 : cover_vars_upto ?a ?b ?c |- _ ] =>
assert (H2 = H1) by apply cover_vars_upto_proof_irrelevance; subst
| [ H1 : wf_term ?a, H2 : wf_term ?a |- _ ] =>
assert (H2 = H1) by apply wf_term_proof_irrelevance; subst
| [ H1 : isprog ?a, H2 : isprog ?a |- _ ] =>
assert (H2 = H1) by apply isprog_proof_irrelevance; subst
end.
Lemma dom_sub_snoc {p} :
forall s v t,
@dom_sub p (snoc s (v, t)) = snoc (dom_sub s) v.
Proof.
induction s; simpl; sp; simpl; allrw; sp.
Qed.
Lemma dom_csub_snoc {p} :
forall sub x,
@dom_csub p (snoc sub x) = snoc (dom_csub sub) (fst x).
Proof.
induction sub; simpl; sp.
rewrite IHsub; sp.
Qed.
Lemma cover_vars_upto_csub_filter_snoc_weak {p} :
forall t x sub vs,
@cover_vars_upto p t (csub_filter sub vs) vs
-> cover_vars_upto t (csub_filter (snoc sub x) vs) vs.
Proof.
introv cv.
allunfold @cover_vars_upto.
prove_subvars cv.
allrw in_app_iff; sp.
allrw @dom_csub_csub_filter.
allrw in_remove_nvars; sp.
allrw @dom_csub_snoc; allsimpl.
allrw in_snoc; sp.
Qed.
Lemma cover_vars_upto_snoc_weak {p} :
forall t x sub vs,
@cover_vars_upto p t sub vs
-> cover_vars_upto t (snoc sub x) vs.
Proof.
introv cv.
allunfold @cover_vars_upto.
prove_subvars cv.
allrw in_app_iff; sp.
allrw @dom_csub_snoc; allsimpl.
allrw in_snoc; sp.
Qed.
Lemma dom_csub_app {p} :
forall sub1 sub2,
@dom_csub p (sub1 ++ sub2) = dom_csub sub1 ++ dom_csub sub2.
Proof.
unfold dom_csub; sp.
rewrite map_app; sp.
Qed.
Lemma dom_csub_eq {p} :
forall sub,
@dom_sub p (csub2sub sub) = dom_csub sub.
Proof.
induction sub; simpl; sp.
rewrite IHsub; sp.
Qed.
Lemma over_vars_eq {p} :
forall vs : list NVar,
forall sub : @CSub p,
over_vars vs sub <=> subvars vs (dom_csub sub).
Proof.
unfold over_vars; sp.
Qed.
Lemma cover_vars_eq {p} :
forall t : NTerm,
forall sub : @CSub p,
cover_vars t sub <=> subvars (free_vars t) (dom_csub sub).
Proof.
unfold cover_vars; sp.
Qed.
Lemma cover_vars_cterm {p} :
forall t s, @cover_vars p (get_cterm t) s.
Proof.
introv; destruct_cterms; simpl.
rw @cover_vars_eq.
allrw @isprog_eq; allunfold @isprogram; repnd; allrw; sp.
Qed.
Hint Immediate cover_vars_cterm.
Lemma cover_vars_app_weak {p} :
forall t sub1 sub2,
@cover_vars p t sub1
-> cover_vars t (sub1 ++ sub2).
Proof.
intros.
allrw @cover_vars_eq.
allrw subvars_eq.
rw @dom_csub_app.
apply subset_app_r; auto.
Qed.
Lemma cover_vars_snoc_weak {p} :
forall t x sub,
@cover_vars p t sub
-> cover_vars t (snoc sub x).
Proof.
intros.
allrw @cover_vars_eq.
allrw subvars_eq.
rw @dom_csub_snoc.
apply subset_snoc_r; auto.
Qed.
Lemma cover_vars_snoc_weak_r {p} :
forall t sub v u,
(forall x, LIn x (free_vars t) -> x = v)
-> @cover_vars p t (snoc sub (v,u)).
Proof.
intros.
rw @cover_vars_eq.
rw subvars_eq.
rw @dom_csub_snoc; simpl.
apply subset_snoc_l; auto.
Qed.
Lemma cover_vars_axiom {p} :
forall sub,
@cover_vars p mk_axiom sub.
Proof.
intro; rw @cover_vars_eq; rw subvars_eq; simpl.
unfold subset; allsimpl; sp.
Qed.
Hint Immediate cover_vars_axiom.
Lemma cover_vars_axiom_iff {p} :
forall sub,
@cover_vars p mk_axiom sub <=> True.
Proof.
sp; split; sp.
Qed.
Lemma cover_vars_base {p} :
forall sub,
@cover_vars p mk_base sub.
Proof.
intro; rw @cover_vars_eq; rw subvars_eq; simpl; sp.
Qed.
Hint Immediate cover_vars_base.
Lemma cover_vars_base_iff {p} :
forall sub,
@cover_vars p mk_base sub <=> True.
Proof.
sp.
Qed.
Lemma over_vars_app_l {p} :
forall vs1 vs2 sub,
@over_vars p (vs1 ++ vs2) sub <=> over_vars vs1 sub # over_vars vs2 sub.
Proof.
sp; rw subvars_app_l; sp.
Qed.
Lemma cover_vars_free_from_atom {p} :
forall a b c sub,
@cover_vars p (mk_free_from_atom a b c) sub
<=> cover_vars a sub
# cover_vars b sub
# cover_vars c sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_free_from_atoms {p} :
forall a b sub,
@cover_vars p (mk_free_from_atoms a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_equality {p} :
forall a b T sub,
@cover_vars p (mk_equality a b T) sub
<=> cover_vars a sub
# cover_vars b sub
# cover_vars T sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_tequality {p} :
forall a b sub,
@cover_vars p (mk_tequality a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_approx {p} :
forall a b sub,
@cover_vars p (mk_approx a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_cequiv {p} :
forall a b sub,
@cover_vars p (mk_cequiv a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_apply {p} :
forall a b sub,
@cover_vars p (mk_apply a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_sup {p} :
forall a b sub,
@cover_vars p (mk_sup a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_member {p} :
forall a T sub,
@cover_vars p (mk_member a T) sub
<=> cover_vars a sub
# cover_vars T sub.
Proof.
sp; unfold mk_member.
rw @cover_vars_equality; split; sp.
Qed.
Lemma cover_vars_type {p} :
forall a sub,
@cover_vars p (mk_type a) sub
<=> cover_vars a sub.
Proof.
sp; unfold mk_type.
rw @cover_vars_tequality; split; sp.
Qed.
Lemma cover_vars_function {p} :
forall a v b sub,
@cover_vars p (mk_function a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_product {p} :
forall a v b sub,
@cover_vars p (mk_product a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_w {p} :
forall a v b sub,
@cover_vars p (mk_w a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_m {p} :
forall a v b sub,
@cover_vars p (mk_m a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_pw {p} :
forall P ap A bp ba B cp ca cb C q sub,
@cover_vars p (mk_pw P ap A bp ba B cp ca cb C q) sub
<=> cover_vars P sub
# cover_vars_upto A (csub_filter sub [ap]) [ap]
# cover_vars_upto B (csub_filter sub [bp,ba]) [bp,ba]
# cover_vars_upto C (csub_filter sub [cp,ca,cb]) [cp,ca,cb]
# cover_vars q sub.
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
assert (ap :: remove_nvars [ap] (dom_csub sub)
= [ap] ++ remove_nvars [ap] (dom_csub sub)) as eq by auto.
rw eq; clear eq.
assert (bp :: ba :: remove_nvars [bp,ba] (dom_csub sub)
= [bp,ba] ++ remove_nvars [bp,ba] (dom_csub sub)) as eq by auto.
rw eq; clear eq.
assert (cp :: ca :: cb :: remove_nvars [cp,ca,cb] (dom_csub sub)
= [cp,ca,cb] ++ remove_nvars [cp,ca,cb] (dom_csub sub)) as eq by auto.
rw eq; clear eq.
allrw subvars_app_remove_nvars_r.
assert (forall vs1 vs2,
subvars vs1 (vs2 ++ dom_csub sub)
<=> subvars vs1 (dom_csub sub ++ vs2))
as eq by (intros; apply subvars_swap_r; sp).
allrw eq; sp.
Qed.
Lemma cover_vars_pm {p} :
forall P ap A bp ba B cp ca cb C q sub,
@cover_vars p (mk_pm P ap A bp ba B cp ca cb C q) sub
<=> cover_vars P sub
# cover_vars_upto A (csub_filter sub [ap]) [ap]
# cover_vars_upto B (csub_filter sub [bp,ba]) [bp,ba]
# cover_vars_upto C (csub_filter sub [cp,ca,cb]) [cp,ca,cb]
# cover_vars q sub.
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
assert (ap :: remove_nvars [ap] (dom_csub sub)
= [ap] ++ remove_nvars [ap] (dom_csub sub)) as eq by auto.
rw eq; clear eq.
assert (bp :: ba :: remove_nvars [bp,ba] (dom_csub sub)
= [bp,ba] ++ remove_nvars [bp,ba] (dom_csub sub)) as eq by auto.
rw eq; clear eq.
assert (cp :: ca :: cb :: remove_nvars [cp,ca,cb] (dom_csub sub)
= [cp,ca,cb] ++ remove_nvars [cp,ca,cb] (dom_csub sub)) as eq by auto.
rw eq; clear eq.
allrw subvars_app_remove_nvars_r.
assert (forall vs1 vs2,
subvars vs1 (vs2 ++ dom_csub sub)
<=> subvars vs1 (dom_csub sub ++ vs2))
as eq by (intros; apply subvars_swap_r; sp).
allrw eq; sp.
Qed.
Lemma cover_vars_upto_axiom {p} :
forall vs sub, @cover_vars_upto p mk_axiom sub vs.
Proof.
intros; unfold cover_vars_upto; simpl; sp.
Qed.
Hint Immediate cover_vars_upto_axiom.
Lemma cover_vars_image {p} :
forall a b sub,
@cover_vars p (mk_image a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_isect {p} :
forall a v b sub,
@cover_vars p (mk_isect a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_eisect {p} :
forall a v b sub,
@cover_vars p (mk_eisect a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_disect {p} :
forall a v b sub,
@cover_vars p (mk_disect a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_set {p} :
forall a v b sub,
@cover_vars p (mk_set a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_tunion {p} :
forall a v b sub,
@cover_vars p (mk_tunion a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_quotient {p} :
forall a v1 v2 b sub,
@cover_vars p (mk_quotient a v1 v2 b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v1,v2]) [v1,v2].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v1 :: v2 :: remove_nvars [v1,v2] (dom_csub sub)
= [v1,v2] ++ remove_nvars [v1,v2] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_lam {p} :
forall v b sub,
@cover_vars p (mk_lam v b) sub
<=> cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw app_nil_r.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_id {p} :
forall sub, @cover_vars p mk_id sub.
Proof.
unfold mk_id; sp.
rw @cover_vars_lam; simpl.
unfold cover_vars_upto.
simpl.
rw subvars_eq.
unfold subset; simpl; sp.
Qed.
Hint Immediate cover_vars_id.
Lemma cover_vars_squash {p} :
forall a sub, @cover_vars p (mk_squash a) sub <=> cover_vars a sub.
Proof.
introv.
rw @cover_vars_image; split; sp.
apply cover_vars_lam; sp.
Qed.
Lemma cover_vars_subtype {p} :
forall a b sub,
@cover_vars p (mk_subtype a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; unfold mk_subtype, mk_vsubtype.
rw @cover_vars_member.
rw @cover_vars_function.
unfold cover_vars_upto.
rw subvars_eq; simpl.
rw subset_nil_l_iff.
split; sp.
rw @cover_vars_eq; allrw subvars_prop; sp.
apply_in_hyp pp; allsimpl; sp; subst.
allapply @newvar_prop; sp.
allrewrite @dom_csub_csub_filter.
allrw in_remove_nvars; sp.
rw @dom_csub_csub_filter.
allrw @cover_vars_eq.
apply subvars_cons_r.
allrw subvars_prop; sp.
apply_in_hyp pp.
rw in_remove_nvars; simpl; sp; subst.
allapply @newvar_prop; sp.
Qed.
Lemma cover_vars_cbv {p} :
forall a v b sub,
@cover_vars p (mk_cbv a v b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v]) [v].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v :: remove_nvars [v] (dom_csub sub)
= [v] ++ remove_nvars [v] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_halts {p} :
forall a sub,
@cover_vars p (mk_halts a) sub
<=> cover_vars a sub.
Proof.
sp; unfold mk_halts; split; sp; allrw @cover_vars_eq; allsimpl;
allrw remove_nvars_nil_l; allrw app_nil_r;
allrw subvars_app_l; sp.
Qed.
Lemma cover_vars_uni {p} :
forall i sub, @cover_vars p (mk_uni i) sub.
Proof.
sp; rw @cover_vars_eq; simpl.
autorewrite with core; sp.
Qed.
Hint Immediate cover_vars_uni.
Definition CSubOver {p} (vs : list NVar) : tuniv :=
{ s : @CSubstitution p | over_vars vs s }.
Definition csubo2csub {p} (vs : list NVar) (sub : CSubOver vs) : @CSubstitution p :=
let (s,x) := sub in s.
Definition dom_csubo {p} (vs : list NVar) (sub : @CSubOver p vs) :=
dom_csub (csubo2csub vs sub).
Definition csubo2sub {p} (vs : list NVar) (sub : @CSubOver p vs) : Substitution :=
csub2sub (csubo2csub vs sub).
Lemma in_dom_sub {p} :
forall v t sub,
LIn (v, t) sub
-> LIn v (@dom_sub p sub).
Proof.
unfold dom_sub; sp.
rw in_map_iff.
exists (v, t); sp.
Qed.
Lemma dom_sub_app {p} :
forall sub1 sub2,
@dom_sub p (sub1 ++ sub2) = dom_sub sub1 ++ dom_sub sub2.
Proof.
unfold dom_sub, dom_lmap; intros; rw map_app; auto.
Qed.
Lemma dom_sub_map_axiom {p} :
forall vars,
@dom_sub p (map (fun v => (v, mk_axiom)) vars) = vars.
Proof.
induction vars; simpl; sp.
rw IHvars; sp.
Qed.
Lemma in_dom_sub_exists {p} :
forall v sub,
LIn v (@dom_sub p sub)
-> {t : NTerm $ sub_find sub v = Some t}.
Proof.
induction sub; simpl; sp; allsimpl; subst; boolvar.
exists a; sp.
exists a; sp.
exists t; sp.
Qed.
Lemma in_dom_csub_exists {p} :
forall v sub,
LIn v (@dom_csub p sub)
-> {t : NTerm $ sub_find (csub2sub sub) v = Some t # isprogram t}.
Proof.
induction sub; simpl; sp; destruct a; allsimpl; subst; boolvar; sp.
exists x; sp; rw @isprogram_eq; sp.
exists x; sp; rw @isprogram_eq; sp.
exists t; auto.
Qed.
Definition insub {p} sub var : bool :=
match @sub_find p sub var with
| Some _ => true
| None => false
end.
Lemma sub_find_some {p} :
forall sub : @Substitution p,
forall v : NVar,
forall u : NTerm,
sub_find sub v = Some u
-> LIn (v, u) sub.
Proof.
induction sub; simpl; sp.
inversion H.
remember (beq_var a0 v).
destruct b.
inversion H; subst.
apply beq_var_eq in Heqb; subst.
left; auto.
apply IHsub in H; right; auto.
Qed.
Lemma sub_find_some_eq {p} :
forall sub : @Substitution p,
forall v : NVar,
forall u t : NTerm,
sub_find sub v = Some t
-> sub_find sub v = Some u
-> t = u.
Proof.
induction sub; simpl; sp.
inversion H.
remember (beq_var a0 v).
destruct b.
inversion H; subst.
inversion H0; subst.
auto.
apply IHsub with (t := t) in H0; auto.
Qed.
Lemma sub_find_app {p} :
forall v sub1 sub2,
@sub_find p (sub1 ++ sub2) v
= match sub_find sub1 v with
| Some t => Some t
| None => sub_find sub2 v
end.
Proof.
induction sub1; simpl; sp.
destruct (beq_var a0 v); auto.
Qed.
Lemma sub_find_snoc {p} :
forall v sub x t,
@sub_find p (snoc sub (x, t)) v
= match sub_find sub v with
| Some t => Some t
| None => if beq_var x v then Some t else None
end.
Proof.
induction sub; simpl; sp; allsimpl.
destruct (beq_var a0 v); auto.
Qed.
Lemma sub_find_some_app {p} :
forall v t sub1 sub2,
@sub_find p sub1 v = Some t
-> sub_find (sub1 ++ sub2) v = Some t.
Proof.
intros.
rw @sub_find_app.
rw H; auto.
Qed.
Lemma sub_find_none {p} :
forall sub : @Substitution p,
forall v : NVar,
forall u : @NTerm p,
sub_find sub v = None
-> forall u, ! LIn (v, u) sub.
Proof.
induction sub; simpl; sp; inj.
rw <- beq_var_refl in H; sp.
remember (beq_var a0 v).
destruct b; sp.
apply IHsub with (u0 := u0) in H; auto.
Qed.
Lemma sub_find_none2 {p} :
forall sub v,
@sub_find p sub v = None
-> ! LIn v (dom_sub sub).
Proof.
induction sub; simpl; sp; subst; allsimpl.
rw <- beq_var_refl in H; inversion H.
remember (beq_var a0 v).
destruct b.
inversion H.
apply IHsub in H; auto.
Qed.
Lemma sub_find_none_iff {p} :
forall sub v,
@sub_find p sub v = None
<=> ! LIn v (dom_sub sub).
Proof.
induction sub; simpl; sp; subst; split; sp; allsimpl; subst.
rw <- beq_var_refl in H; inversion H.
remember (beq_var a0 v); destruct b.
inversion H.
rw IHsub in H; auto.
remember (beq_var a0 v); destruct b.
provefalse; apply H.
apply beq_var_eq in Heqb; left; auto.
symmetry in Heqb.
apply beq_var_false_not_eq in Heqb.
rw IHsub; intro.
apply H; right; auto.
Qed.
(* computes the set of free variables occurring in the co-domain of sub *)
Fixpoint sub_free_vars {p} (sub : @Substitution p) : list NVar :=
match sub with
| nil => nil
| (v, t) :: xs => free_vars t ++ sub_free_vars xs
end.
Lemma in_sub_free_vars {p} :
forall sub v,
LIn v (@sub_free_vars p sub)
-> {x : NVar $ {t : NTerm $
LIn (x,t) sub # LIn v (free_vars t) }}.
Proof.
induction sub; simpl; sp; allsimpl.
allrw in_app_iff; sp.
exists a0 a; sp.
discover; sp.
exists x t; sp.
Qed.
Lemma in_sub_free_vars_iff {p} :
forall sub v,
LIn v (@sub_free_vars p sub)
<=> {x : NVar $ {t : NTerm $
LIn (x,t) sub # LIn v (free_vars t)}}.
Proof.
induction sub; simpl; sp.
split; sp.
rw in_app_iff.
rw IHsub; split; sp; inj; sp.
exists a0 a; sp.
exists x t; sp.
right; exists x t; sp.
Qed.
Lemma subset_free_vars_mem {p} :
forall v t sub,
LIn (v, t) sub
-> subset (@free_vars p t) (sub_free_vars sub).
Proof.
induction sub; simpl; sp; inj.
apply subset_app_r; apply subset_refl.
apply subset_app_l; auto.
Qed.
Lemma subset_sub_free_vars {p} :
forall sub1 sub2,
subset sub1 sub2
-> subset (@sub_free_vars p sub1) (sub_free_vars sub2).
Proof.
induction sub1; simpl; sp.
destruct sub2.
allapply subset_cons_nil; sp.
destruct p.
simpl.
allrw cons_subset; allsimpl; sp; inj.
rw app_subset; sp.
apply subset_app_r; apply subset_refl.
apply_in_hyp p; allsimpl; sp.
rw app_subset; sp.
apply subset_app_l.
apply subset_free_vars_mem with (v := a0); auto.
apply_in_hyp p; allsimpl; sp.
Qed.
Lemma sub_free_vars_isprogram {p} :
forall sub,
(forall v t, LIn (v, t) sub -> @isprogram p t)
-> null (sub_free_vars sub).
Proof.
induction sub; simpl; intros k; sp.
rw null_app; sp.
generalize (k a0 a); intro i.
dest_imp i hyp.
unfold isprogram, closed in i; sp.
allrw; sp.
apply IHsub; sp.
apply k with (v := v); sp.
Qed.
Definition sub_mk_rename (var : NVar) (fvars : list NVar) : NVar :=
if memvar var fvars
then fresh_var fvars
else var.
(** chose new variables if for bvars if they are in fvars.
if new variables have to be chose, make sure that
the new choices are disjoint from lva.
need not choose a new var if it is in lva but not in fvars.
This is to avoid renamings as much as possible
*)
Fixpoint sub_mk_renames2 {p} (bvars : list NVar) (fvars : list NVar)
(lva: list NVar): (list NVar) * @Substitution p :=
match bvars with
| nil => (nil, nil)
| v :: vs =>
let (vars, sub) := sub_mk_renames2 vs fvars lva in
if memvar v fvars
then let u := fresh_var (vars ++ fvars ++ lva) in
(u :: vars, (v, vterm u) :: sub)
else (v :: vars, sub)
end.
(* generates renamings for all the variables in bvars that also occur in fvars *)
Fixpoint sub_mk_renames {p} (bvars : list NVar) (fvars : list NVar) :
(list NVar) * @Substitution p :=
match bvars with
| nil => (nil, nil)
| v :: vs =>
let (vars, sub) := sub_mk_renames vs fvars in
if memvar v fvars
then let u := fresh_var (vars ++ fvars) in
(u :: vars, (v, vterm u) :: sub)
else (v :: vars, sub)
end.
Lemma sub_mk_renames_eta {p} :
forall vs frees,
@sub_mk_renames p vs frees
= (fst (@sub_mk_renames p vs frees), snd (sub_mk_renames vs frees)).
Proof.
induction vs; simpl; sp.
rw IHvs; simpl.
destruct (memvar a frees).
simpl; auto.
simpl; auto.
Qed.
Lemma sub_mk_renames2_eta {p} :
forall vs frees lva,
sub_mk_renames2 vs frees lva
= (fst (@sub_mk_renames2 p vs frees lva), snd (@sub_mk_renames2 p vs frees lva)).
Proof.
induction vs; simpl; sp.
rw IHvs; simpl.
destruct (memvar a frees).
simpl; auto.
simpl; auto.
Qed.
Lemma sub_mk_renames_snd_vterm {p} :
forall bvars fvars v t,
LIn (v,t) (snd (sub_mk_renames bvars fvars))
-> {x : NVar $ t = @vterm p x}.
Proof.
induction bvars; simpl; introv k; sp.
rw @sub_mk_renames_eta in k; allsimpl.
destruct (memvar a fvars); allsimpl; sp; inj.
exists (fresh_var (fst (@sub_mk_renames p bvars fvars) ++ fvars)); auto.
discover; sp.
discover; sp.
Qed.
Lemma sub_mk_renames2_snd_vterm {p} :
forall bvars fvars v t lva,
LIn (v,t) (snd (sub_mk_renames2 bvars fvars lva))
-> {x : NVar $ t = @vterm p x}.
Proof.
induction bvars; simpl; introv k; sp.
rw @sub_mk_renames2_eta in k; allsimpl.
destruct (memvar a fvars); allsimpl; sp; inj.
eexists; eauto.
discover; sp.
discover; sp.
Qed.
Lemma sub_mk_renames2_nil {p} :
forall vs lva,
@sub_mk_renames2 p vs [] lva = (vs, []).
Proof.
induction vs; simpl; sp.
rw IHvs. sp.
Qed.
Lemma sub_mk_renames_nil {p} :
forall vs,
@sub_mk_renames p vs [] = (vs, []).
Proof.
induction vs; simpl; sp.
rw @sub_mk_renames_eta.
rw IHvs; simpl; auto.
Qed.
Lemma sub_mk_renames_length {p} :
forall vs frees,
length (fst (@sub_mk_renames p vs frees)) = length vs.
Proof.
induction vs; simpl; sp.
rw @sub_mk_renames_eta; simpl.
destruct (memvar a frees); simpl; rw IHvs; auto.
Qed.
Lemma sub_mk_renames2_length {p} :
forall vs frees lva,
length (fst (@sub_mk_renames2 p vs frees lva)) = length vs.
Proof.
induction vs; simpl; sp.
rw @sub_mk_renames2_eta; simpl.
destruct (memvar a frees); simpl; rw IHvs; auto.
Qed.
Lemma in_snd_sub_mk_renames {p} :
forall v t bvars fvars,
LIn (v, t) (snd (sub_mk_renames bvars fvars))
->
(
LIn v bvars
#
LIn v fvars
#
{x : NVar $ (t = @vterm p x # ! LIn x fvars)}
).
Proof.
induction bvars; simpl; introv k; sp.
- rw @sub_mk_renames_eta in k; allsimpl.
remember (memvar a fvars); destruct b; allsimpl; sp; inj; sp;
apply_in_hyp pp; sp.
- rw @sub_mk_renames_eta in k; allsimpl.
remember (memvar a fvars); destruct b; allsimpl; sp; inj; sp.
symmetry in Heqb.
rw fold_assert in Heqb.
rw assert_memvar in Heqb; auto.
apply_in_hyp pp; sp.
apply_in_hyp pp; sp.
- rw @sub_mk_renames_eta in k; allsimpl.
remember (memvar a fvars); destruct b; allsimpl; sp; inj; sp.
symmetry in Heqb.
rw fold_assert in Heqb.
rw assert_memvar in Heqb; auto.
exists (fresh_var (fst (@sub_mk_renames p bvars fvars) ++ fvars)); sp.
assert (! (LIn (fresh_var (fst (@sub_mk_renames p bvars fvars) ++ fvars))
(fst (@sub_mk_renames p bvars fvars) ++ fvars))) as nin
by apply fresh_var_not_in.
apply nin.
rw in_app_iff; sp.
apply_in_hyp pp; sp.
apply_in_hyp pp; sp.
Qed.
Lemma sub_mk_renames_not_in {p} :
forall l v vs,
! LIn v l
-> @sub_mk_renames p l vs = (l, [])
-> @sub_mk_renames p l (v :: vs) = (l, []).
Proof.
induction l; simpl; sp.
allrw not_over_or; repd.
remember (memvar a vs); destruct b; symmetry in Heqb.
rw fold_assert in Heqb.
rw assert_memvar in Heqb; allsimpl; sp; subst.
rw @sub_mk_renames_eta in H0; cpx.
rw @sub_mk_renames_eta in H0; cpx.
invs2.
assert (@sub_mk_renames p l vs = (l, [])) as seq by (rw @sub_mk_renames_eta; allrw; sp).
allrw; allsimpl; sp.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb.
remember (memvar a (v :: vs)); destruct b; symmetry in Heqb0; sp.
rw fold_assert in Heqb0.
rw assert_memvar in Heqb0; allsimpl; sp.
Qed.
Lemma sub_mk_renames2_not_in {p} :
forall l v vs lva,
! LIn v l
-> @sub_mk_renames2 p l vs lva= (l, [])
-> @sub_mk_renames2 p l (v :: vs) lva = (l, []).
Proof.
induction l; simpl; sp.
allrw not_over_or; repd.
remember (memvar a vs); destruct b; symmetry in Heqb.
rw fold_assert in Heqb.
rw assert_memvar in Heqb; allsimpl; sp; subst.
rw @sub_mk_renames2_eta in H0; cpx.
rw @sub_mk_renames2_eta in H0; cpx.
invs2.
assert (@sub_mk_renames2 p l vs lva= (l, [])) as seq by (rw @sub_mk_renames2_eta; allrw; sp).
allrw; allsimpl; sp.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb.
remember (memvar a (v :: vs)); destruct b; symmetry in Heqb0; sp.
rw fold_assert in Heqb0.
rw assert_memvar in Heqb0; allsimpl; sp.
Qed.
Lemma sub_mk_renames_trivial_vars {p} :
forall vars l,
@sub_mk_renames p
l
(sub_free_vars
(sub_filter (map (fun v => (v, @vterm p v)) vars) l))
= (l, []).
Proof.
induction vars; simpl; sp.
rw @sub_mk_renames_nil; simpl; sp.
remember (memvar a l); destruct b; symmetry in Heqb; auto; simpl.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb.
apply sub_mk_renames_not_in; auto.
Qed.
Lemma sub_mk_renames2_trivial_vars {p} :
forall vars l lva,
@sub_mk_renames2 p
l
(sub_free_vars
(sub_filter (map (fun v => (v, @vterm p v)) vars) l)) lva
= (l, []).
Proof.
induction vars; simpl; sp.
rw @sub_mk_renames2_nil; simpl; sp.
remember (memvar a l); destruct b; symmetry in Heqb; auto; simpl.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb.
apply sub_mk_renames2_not_in; auto.
Qed.
Lemma sub_find_sub_filter {p} :
forall sub vars n,
LIn n vars -> sub_find (@sub_filter p sub vars) n = None.
Proof.
induction sub; simpl; sp.
remember (memvar a0 vars); destruct b; simpl; symmetry in Heqb.
apply_in_hyp pp; sp.
remember (beq_var a0 n); destruct b.
apply beq_var_eq in Heqb0; subst.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb; sp.
apply_in_hyp pp; sp.
Qed.
(*
Fixpoint update_bvar_subst (bvs: list NVar) (sub: Substitution) : Substitution :=
match bvs with
| [] => sub
| v::tv =>
let sub' := sub_filter sub [v] in
let frees := sub_free_vars sub' in
let u := sub_mk_rename v frees in
(v, vterm u):: (update_bvar_subst tv sub)
end.
*)
(*
Fixpoint bvar_renamings_subst' (bvs: list NVar) (sub: Substitution)
: Substitution * (list NVar) :=
match bvs with
| [] => (sub,[])
| v::tv =>
let sub' := sub_filter sub [v] in
let frees := sub_free_vars sub' in
let u := sub_mk_rename v frees in
let r := bvar_renamings_subst' tv sub in
((v, vterm u) :: (fst r), u :: (snd r))
end.
*)
(** bvar_renamings_subst returns three things:
* 1) a list of variables computed from vs such that the ones that
* also occur in the free variables of sub get renamed
* 2) a renamings for the bound variables in vs that also occur in sub
* 3) a subset of sub that does not clash with vs
*)
Definition bvar_renamings_subst {p} (vs: list NVar) (bd : @NTerm p) (sub: @Substitution p)
: (list NVar) * @Substitution p * @Substitution p :=
let sub1 := sub_filter sub vs in
let (vs',sub2) := sub_mk_renames2 vs (sub_free_vars sub1) (dom_sub sub1++(all_vars bd)) in
(vs', sub2, sub1).
Definition disjoint_bv_sub {p} (nt : @NTerm p) (sub: @Substitution p) :=
sub_range_sat sub (fun t => disjoint (free_vars t) (bound_vars nt)).
Theorem prog_sub_disjoint_bv_sub {p} :
forall nt sub, @prog_sub p sub -> disjoint_bv_sub nt sub.
Proof. intros nt. apply sub_range_sat_implies.
introv Hpr. invertsn Hpr.
rw Hpr. introv Hin. inverts Hin.
Qed.
Definition disjoint_bvbt_sub {p} (bt : @BTerm p) (sub: @Substitution p) :=
sub_range_sat sub (fun t => disjoint (free_vars t) (bound_vars_bterm bt)).
(* Eval simpl in (lsubst (mk_lam nvarx (vterm nvary)) [(nvarz,vterm nvarx)]).
This was a bug in lsubst. it will return \lambda y.y because
the new variables were not disjoint from the fvars of the body
*)
(*
Lemma disjoint_bvbt_sub_ot : forall op lbt bt sub,
LIn bt lbt
-> disjoint_bv_sub (oterm op lbt) sub
-> disjoint_bvbt_sub bt sub.
AdCmitted.
Fixpoint lsubstd (t : NTerm) (sub : Substitution) (p: disjoint_bv_sub t sub): NTerm :=
(*if nullb sub then t else*)
match t with
| vterm var =>
match sub_find sub var with
| Some t => t
| None => t
end
| oterm op bts => let btsp := pairInProofs bts in
let f:= (fun ppp => match ppp with
| existT bt pp => lsubst_btermc bt sub _
(disjoint_bvbt_sub_ot _ _ _ _ pp p)
end) in
oterm op (map f bts)
end
with lsubst_btermc (bt : BTerm) (sub : Substitution) (p:disjoint_bvbt_sub bt sub): BTerm :=
match bt with
| bterm lv nt =>
bterm lv (lsubstc nt (sub_filter sub lv) _)
end.
*)
(* end hide *)
(** % \noindent \\* %
The following function is an auxilliary one that performs a
[Substitution] on an [NTerm] assuming that its bound
variables of are already disjoint from the free variables
of the range of the [Substitution].
*)
(*if nullb sub then t else*)
Fixpoint lsubst_aux {p} (nt : @NTerm p) (sub : Substitution) : NTerm :=
match nt with
| vterm var =>
match sub_find sub var with
| Some t => t
| None => nt
end
| sterm f => sterm f
| oterm op bts => oterm op (map (fun t => lsubst_bterm_aux t sub) bts)
end
with lsubst_bterm_aux {p} (bt : BTerm) (sub : Substitution) : BTerm :=
match bt with
| bterm lv nt => bterm lv (lsubst_aux nt (sub_filter sub lv))
end.
(** % \noindent \\* %
To define the actual substitution function, we just have to pre-process [t]
such that its bound variables have been renamed to avoid
the free variables of the range of [sub].
Here is a function that does that.
*)
Fixpoint change_bvars_alpha {p} (lv : list NVar) (t : @NTerm p) :=
match t with
| vterm v => vterm v
| sterm f => sterm f
| oterm o lbt => oterm o (map (change_bvars_alphabt lv) lbt)
end
with change_bvars_alphabt {p} lv bt:=
match bt with
| bterm blv bnt =>
let bnt' := change_bvars_alpha lv bnt in
let lvn := fresh_distinct_vars (length blv) (lv++(all_vars bnt')) in
bterm lvn (lsubst_aux bnt' (var_ren blv lvn))
end.
(** % \noindent \\* %
When we define alpha equality in the next section, we prove that
[change_bvars_alpha] returns a term which is alpha equal to the input.
Finally, here is the function that safely perfoms
a [Substitution] on an [NTerm].
*)
Definition lsubst {p} (t : @NTerm p) (sub : Substitution) : NTerm :=
let sfr := flat_map free_vars (range sub) in
if dec_disjointv (bound_vars t) sfr
then lsubst_aux t sub
else lsubst_aux (change_bvars_alpha sfr t) sub.
(** %\noindent% The following definition will be useful while
defining the computation system.
*)
Definition apply_bterm {p} (bt : @BTerm p) (lnt: list NTerm) : NTerm :=
lsubst (get_nt bt) (combine (get_vars bt) lnt).
(** %\noindent \\*% The formalization of Nuprl requires many lemmas about [lsubst].
Because [lsubst] often renames bound variables, we
need alpha equality to state many useful properties of substitution.
We will first define alpha equality and then list some useful properties
that we proved about [lsubst].
*)
(* begin hide *)
Lemma lsubst_lsubst_aux {p} :
forall t sub, disjoint (bound_vars t) (flat_map free_vars (@range p sub))
-> lsubst t sub = lsubst_aux t sub.
Proof.
introv Hdis. unfold lsubst. cases_if;sp.
Qed.
Lemma bvar_renamings_subst_trivial_vars {p} :
forall l nt vars,
bvar_renamings_subst l nt (map (fun v => (v, vterm v)) vars)
= (l, [], sub_filter (map (fun v => (v, @vterm p v)) vars) l).
Proof.
intros.
unfold bvar_renamings_subst.
rw @sub_mk_renames2_trivial_vars.
auto.
Qed.
Lemma bvar_renamings_subst_eta' {p} :
forall vs sub nt,
{vs' : list NVar & {ren : Substitution & {sub' : @Substitution p &
bvar_renamings_subst vs nt sub = (vs', ren, sub') }}}.
Proof.
intros.
unfold bvar_renamings_subst.
rw @sub_mk_renames2_eta; simpl.
eexists; eauto.
Qed.
Lemma bvar_renamings_subst_eta {p} :
forall vs sub nt,
@bvar_renamings_subst p vs nt sub
= (fst (fst (bvar_renamings_subst vs nt sub)),
snd (fst (bvar_renamings_subst vs nt sub)),
snd (bvar_renamings_subst vs nt sub)).
Proof.
intros.
unfold bvar_renamings_subst.
rw @sub_mk_renames2_eta; simpl.
auto.
Qed.
Lemma bvar_renamings_subst_length {p} :
forall l sub nt,
length (fst (fst (@bvar_renamings_subst p l nt sub))) = length l.
Proof.
intros; unfold bvar_renamings_subst.
rw @sub_mk_renames2_eta; simpl.
rw @sub_mk_renames2_length; auto.
Qed.
Lemma bvar_renamings_subst_nil {p} :
forall l nt, @bvar_renamings_subst p l nt [] = (l, [], []).
Proof.
intros; unfold bvar_renamings_subst; simpl.
rw @sub_mk_renames2_eta; simpl.
rw @sub_mk_renames2_nil; auto.
Qed.
Lemma bvar_renamings_subst_isprogram {p} :
forall vars sub nt,
(forall v t, LIn (v, t) sub -> @isprogram p t)
-> bvar_renamings_subst vars nt sub = (vars, [], sub_filter sub vars).
Proof.
intros.
unfold bvar_renamings_subst.
rw @sub_mk_renames2_eta; simpl.
allapply @sub_free_vars_isprogram.
assert (null (sub_free_vars (sub_filter sub vars)))
by (assert (subset (sub_free_vars (sub_filter sub vars)) (sub_free_vars sub))
by (apply subset_sub_free_vars; apply sub_filter_subset);
apply null_subset with (l2 := sub_free_vars sub); sp).
allrw null_iff_nil.
allrw. simpl_vlist.
rw @sub_mk_renames2_nil; simpl; auto.
Qed.
Fixpoint lsubst_vs {p} (vars : list NVar) (t : @NTerm p) (sub : Substitution) : NTerm :=
(*if nullb sub then t else*)
match t with
| vterm var =>
match sub_find sub var with
| Some t => t
| None => t
end
| sterm f => sterm f
| oterm op bts => oterm op (map (fun t => lsubst_vs_bterm vars t sub) bts)
end
with lsubst_vs_bterm {p} (vars : list NVar) (bt : BTerm) (sub : Substitution) : BTerm :=
match bt with
| bterm lv nt =>
let (x,s) := bvar_renamings_subst lv nt sub in
let (vs,ren) := x in
bterm vs (lsubst_vs (vars ++ vs) nt (ren ++ s))
end.
(*
Lemma isprogram_lsubst_vars_implies :
forall t sub vars,
isprogram (lsubst_vs vars t sub)
-> forall v,
LIn v (free_vars t)
-> ! LIn v vars
-> exists u, sub_find sub v = Some u # isprogram u.
Proof.
nterm_ind t Case; simpl; intros.
- Case "vterm".
sp; subst.
remember (sub_find sub v); destruct o; symmetry in Heqo.
exists n; sp.
rw isprogram_vterm in H; sp.
- Case "oterm".
rw in_flat_map in H1; sp.
destruct x.
simpl in H3.
rw in_remove_nvars in H3; sp.
apply H with (nt := n) (lv := l) (vars := vars ++ l); auto.
unfold isprogram, closed in H0; sp; allsimpl.
rw flat_map_empty in H0.
inversion H5; subst.
rw map_map in H9.
unfold compose in H9.
generalize (H0 (lsubst_vs_bterm vars (bterm l n) sub)).
generalize (H8 (lsubst_vs_bterm vars (bterm l n) sub)).
simpl.
rw bvar_renamings_subst_eta.
rw in_map_iff.
sp.
assert (exists x,
lsubst_vs_bterm vars x sub =
bterm (fst (fst (bvar_renamings_subst l sub)))
(lsubst_vs (vars ++ fst (fst (bvar_renamings_subst l sub))) n
(snd (fst (bvar_renamings_subst l sub)) ++
snd (bvar_renamings_subst l sub))) #
LIn x lbt) by
(exists (bterm l n); simpl; rw bvar_renamings_subst_eta; simpl; auto).
applydup H6 in H10.
applydup H7 in H10.
allsimpl.
unfold isprogram, closed.
Abort.
*)
Definition csubst {p} (t : @NTerm p) (sub : CSubstitution) :=
lsubst t (csub2sub sub).
Lemma fold_csubst {p} :
forall t sub, lsubst t (@csub2sub p sub) = csubst t sub.
Proof.
sp.
Qed.
Lemma csubst_mk_axiom {p} :
forall sub, @csubst p mk_axiom sub = mk_axiom.
Proof.
sp.
Qed.
Lemma csubst_mk_uni {p} :
forall i sub, @csubst p (mk_uni i) sub = mk_uni i.
Proof.
sp.
Qed.
Lemma csubst_mk_base {p} :
forall sub, @csubst p mk_base sub = mk_base.
Proof.
sp.
Qed.
Lemma lsubst_aux_nil {p} :
forall t, @lsubst_aux p t [] = t.
Proof.
nterm_ind t Case; simpl; auto.
assert (map (fun t : BTerm => lsubst_bterm_aux t []) lbt = lbt);
try (rw H0; auto).
induction lbt; simpl; auto.
rw IHlbt; auto.
destruct a; simpl.
f_equal; sp.
f_equal; sp.
eapply H; eauto.
left; auto.
intros. eapply H; eauto.
right;sp.
eauto.
Qed.
Lemma lsubst_nil {p} :
forall t, @lsubst p t [] = t.
Proof.
intros. unfold lsubst. simpl. cases_if.
- apply lsubst_aux_nil.
- disjoint_reasoning.
Qed.
Hint Rewrite @lsubst_nil.
Lemma csubst_nil {p} :
forall t, @csubst p t [] = t.
Proof.
unfold csubst; simpl; sp.
rw @lsubst_nil; sp.
Qed.
Hint Rewrite @csubst_nil.
Lemma lsubst_aux_trivial {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> @isprogram p u # ! LIn v (free_vars t))
-> lsubst_aux t sub = t.
Proof.
unfold lsubst.
nterm_ind t as [|f ind|op lbt ind] Case; simpl; introv imp; auto.
- Case "vterm".
allunfold @isprogram; allunfold @closed; sp.
remember (sub_find sub n); destruct o; symmetry in Heqo; auto.
apply sub_find_some in Heqo.
apply_in_hyp pp; sp.
allrw not_over_or; sp.
- Case "oterm".
assert (map (fun t : BTerm => lsubst_bterm_aux t sub) lbt = lbt) as eq;
try (rw eq; auto).
induction lbt; simpl; auto.
rw IHlbt; sp.
+ destruct a; simpl.
f_equal. f_equal.
rewrite ind with (lv := l); sp.
allrw @in_sub_filter; sp.
apply_in_hyp pp; sp.
allrw @in_sub_filter; sp.
apply_in_hyp pp; sp; allsimpl.
allrw in_app_iff.
allrw not_over_or; sp.
allrw in_remove_nvars; sp.
+ rewrite ind with (lv := lv); sp.
+ apply_in_hyp pp; sp.
+ apply_in_hyp pp; sp; allsimpl.
allrw in_app_iff.
allrw not_over_or; sp.
Qed.
Lemma prog_sub_flatmap_range {p} : forall sub, @prog_sub p sub
-> flat_map free_vars (range sub) =[].
Proof.
unfold prog_sub, isprogram,closed . introv Hps. apply flat_map_empty. cpx.
introv Hin. rw in_map_iff in Hin. exrepnd. subst.
simpl.
apply Hps in Hin1. cpx.
Qed.
Theorem dom_range_is_split_snd {p} :
forall sub, @range p sub = snd (split sub).
Proof.
induction sub; auto. allsimpl.
destruct (split sub) as [lv lnt].
destruct (a) as [v nt].
allsimpl. f_equal. auto.
Qed.
Theorem dom_range_combine {p} :
forall lv lnt,
length lv = length lnt
-> @range p (combine lv lnt) = lnt.
Proof.
intros. rw @dom_range_is_split_snd.
rewrite combine_split; auto.
Qed.
Lemma sub_eta {p} : forall sub,
sub = combine (@dom_sub p sub) (range sub).
Proof.
induction sub as [| (v,t) Hind]; auto;simpl;congruence.
Qed.
Lemma sub_eta_length {p} : forall sub,
length (@dom_sub p sub) = length (range sub).
Proof.
induction sub as [| (v,t) Hind]; auto;simpl;congruence.
Qed.
Lemma in_sub_eta {p} : forall sub v t,
LIn (v,t) sub -> (LIn v (@dom_sub p sub)) # (LIn t (range sub)).
Proof.
introns HH.
pose proof (sub_eta sub) as XX.
rw XX in HH.
apply in_combine in HH.
trivial.
Qed.
Lemma disjoint_sub_as_flat_map {p} :
forall (f: NTerm -> (list NVar)) sub lvd,
(forall (v : NVar) (u : @NTerm p),
LIn (v, u) sub -> disjoint (f u) lvd)
<=> disjoint (flat_map f (range sub)) lvd.
Proof.
introv. sp_iff Case.
Case "->".
- introv Hin. apply disjoint_flat_map_l.
intros nt Hinr. pose proof (sub_eta_length sub) as XXX.
apply combine_in_right with (l1:=dom_sub sub) in Hinr;[| omega];[].
exrepnd. rewrite <- sub_eta in Hinr0.
apply Hin in Hinr0. sp.
- introv Hdis. introv Hin. apply in_sub_eta in Hin. repnd.
rw disjoint_flat_map_l in Hdis.
apply Hdis in Hin. sp.
Qed.
Ltac false_disjoint :=
match goal with
| [ H: !( disjoint _ _) |- _] => provefalse; apply H; clear H; disjoint_reasoningv
end.
Lemma flat_map_free_var_vterm {p} :
forall lv, flat_map free_vars (map (@vterm p) lv)=lv.
Proof.
induction lv;sp;simpl;f_equal;sp.
Qed.
Lemma flat_map_bound_var_vterm {p} :
forall lv, flat_map bound_vars (map (@vterm p) lv)=[].
Proof.
induction lv;sp;simpl;f_equal;sp.
Qed.
Lemma range_var_ren {p} : forall lvi lvo,
length lvi=length lvo
-> range (var_ren lvi lvo) = map (@vterm p) lvo.
Proof.
induction lvi as [|? ? Hind]; introv Hlen; allsimpl; destruct lvo; inverts Hlen;sp;[];simpl.
f_equal. apply Hind; sp.
Qed.
Lemma flat_map_free_var_vars_range {p} : forall lvi lvo,
length lvi=length lvo
-> flat_map free_vars (range (@var_ren p lvi lvo)) = lvo.
Proof.
intros. rw @range_var_ren;sp. apply flat_map_free_var_vterm.
Qed.
Lemma flat_map_bound_var_vars_range {p} : forall lvi lvo,
length lvi=length lvo
-> flat_map bound_vars (range (@var_ren p lvi lvo)) = [].
Proof. intros. rw @range_var_ren;sp. apply flat_map_bound_var_vterm.
Qed.
Theorem dom_sub_is_split_snd {p} :
forall sub, @dom_sub p sub = fst (split sub).
Proof.
induction sub; auto. allsimpl.
destruct (split sub) as [lv lnt].
destruct (a) as [v nt].
allsimpl. f_equal. auto.
Qed.
Theorem dom_sub_combine {p} :
forall lv lnt,
length lv = length lnt
-> @dom_sub p (combine lv lnt) = lv.
Proof.
intros.
rw @dom_sub_is_split_snd.
revert lnt H; induction lv; sp; simpl; destruct lnt; allsimpl; sp; try omega.
rw split_eta; simpl; allrw; sp; omega.
Qed.
Theorem dom_sub_combine_le {p} :
forall lv lnt,
length lv <= length lnt
-> @dom_sub p (combine lv lnt) = lv.
Proof.
intros.
rw @dom_sub_is_split_snd.
revert lnt H; induction lv; sp; simpl; destruct lnt; allsimpl; sp; try omega.
rw split_eta; simpl; allrw; sp; omega.
Qed.
Ltac simpl_sub :=
(match goal with
| [ H : context[dom_sub (combine _ _)] |- _] => rewrite dom_sub_combine in H;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ |- context[dom_sub (combine _ _)] ] => rewrite dom_sub_combine;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ H : context[range (combine _ _)] |- _] => rewrite dom_range_combine in H;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ |- context[range (combine _ _)] ] => rewrite dom_range_combine;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ H : context[range (var_ren _ _)] |- _] => unfold var_ren in H
| [ |- context[range (var_ren _ _)] ] => unfold var_ren
| [ H : context[dom_sub (var_ren _ _)] |- _] => unfold var_ren in H
| [ |- context[dom_sub (var_ren _ _)] ] => unfold var_ren
| [ H : context[flat_map free_vars (map vterm _)] |- _] => rewrite flat_map_free_var_vterm in H
| [ |- context[flat_map free_vars (map vterm _)] ] => rewrite flat_map_free_var_vterm
| [ H : context[flat_map bound_vars (map vterm _)] |- _] => rewrite flat_map_bound_var_vterm in H
| [ |- context[flat_map bound_vars (map vterm _)] ] => rewrite flat_map_bound_var_vterm
| [ H : isprogram _ |- _ ] => allrewrite (fst (H))
end).
Tactic Notation "spcl" := spc;simpl_list.
Tactic Notation "spcls" := repeat(simpl_list);sp;repeat(simpl_sub).
Lemma prog_sub_csub2sub {p} :
forall sub, prog_sub (@csub2sub p sub).
Proof.
introv hn; allapply @in_csub2sub; sp.
Qed.
Hint Immediate prog_sub_csub2sub.
Lemma wf_sub_csub2sub {p} :
forall sub, wf_sub (@csub2sub p sub).
Proof.
introv hn; allapply @in_csub2sub; sp.
destruct hn; auto.
Qed.
Hint Immediate wf_sub_csub2sub.
Lemma prog_sub_implies_wf_sub {p} :
forall sub, @prog_sub p sub -> wf_sub sub.
Proof.
introv psub.
introv k.
apply psub in k.
destruct k; auto.
Qed.
Lemma prog_sub_implies_wf {p} :
forall sub, @prog_sub p sub -> wf_sub sub.
Proof.
exact prog_sub_implies_wf_sub.
Qed.
Lemma prog_sub_cons {p} :
forall sub v t,
@prog_sub p ((v,t) :: sub) <=> (isprogram t # prog_sub sub).
Proof.
introv.
unfold prog_sub, sub_range_sat; simpl; split; intro k; sp; cpx; discover; sp.
apply k with (v0 := v); sp.
apply k with (v0 := v0); sp.
Qed.
Lemma in_range_iff {p} :
forall (t : @NTerm p) (sub : Substitution),
LIn t (range sub) <=> {v : NVar $ LIn (v, t) sub}.
Proof.
induction sub; simpl; split; intro k; sp; allsimpl; subst; discover; sp; cpx.
exists a0; sp.
exists v; sp.
right; allrw; exists v; sp.
Qed.
Lemma prog_sub_eq {p} :
forall sub,
(forall t, LIn t (@range p sub) -> isprogram t)
<=> prog_sub sub.
Proof.
induction sub; simpl; split; intro k; introv; sp; subst; allsimpl; sp; cpx.
apply k; right; rw @in_range_iff; exists v; sp.
allrw @prog_sub_cons; sp.
allrw @prog_sub_cons; sp; discover; sp.
Qed.
Lemma prog_sub_exists_csub {p} :
forall sub, @prog_sub p sub -> {s : CSub & csub2sub s = sub}.
Proof.
induction sub; simpl.
- exists ([] : @CSub p); sp.
- intro ps.
destruct a.
rw @prog_sub_cons in ps; repnd.
apply IHsub in ps; exrepnd.
exists ((n,mk_cterm n0 ps0) :: s).
simpl; rw ps1; sp.
Qed.
Definition hide_csub2sub {p} sub := @csub2sub p sub.
Ltac change_to_lsubst_aux4 :=
unfold lsubst;
allunfold disjoint_bv_sub;
(repeat match goal with
| [ |- context [csub2sub ?sub] ] =>
let name := fresh "ps_csub2sub" in
pose proof (prog_sub_csub2sub sub) as name;
fold (hide_csub2sub sub)
end);
allunfold hide_csub2sub;
allunfold prog_sub;
allunfold sub_range_sat;
(repeat match goal with
| [ H:(forall _ _, LIn (_, _) _ -> isprogram _) |- _ ] =>
progress(rw (prog_sub_flatmap_range _ H))
| [ H:( forall _ _, LIn (_, _) _
-> disjoint (free_vars _) (bound_vars _)) |- _ ] =>
apply disjoint_sub_as_flat_map in H;apply disjoint_sym in H
end);
repeat(cases_if;clears_last; [|sp;disjoint_reasoningv;spcls;try(false_disjoint)]).
Lemma lsubst_trivial {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> @isprogram p u # ! LIn v (free_vars t))
-> lsubst t sub = t.
Proof.
introv Hpr. assert (prog_sub sub). introv Hin. apply Hpr in Hin;sp.
change_to_lsubst_aux4.
apply lsubst_aux_trivial;sp.
Qed.
Lemma lsubst_cterm {p} :
forall t s,
lsubst (get_cterm t) (@csub2sub p s) = get_cterm t.
Proof.
introv.
apply lsubst_trivial; introv i.
rw @free_vars_cterm; simpl; sp.
apply in_csub2sub in i; sp.
Qed.
(* This is not true because lsubst might renames some bound variables of t
that occur in the free variables of sub.
Lemma lsubst_trivial1 :
forall t sub,
(forall v u, LIn (v, u) sub -> ! LIn v (free_vars t))
-> lsubst t sub = t.
Proof.
nterm_ind t Case; simpl; intros.
- Case "vterm".
allunfold isprogram; allunfold closed; sp.
remember (sub_find sub n); destruct o; symmetry in Heqo; auto.
apply sub_find_some in Heqo.
apply H in Heqo; sp.
provefalse; apply Heqo; left; auto.
- Case "oterm".
assert (map (fun t : BTerm => lsubst_bterm t sub) lbt = lbt);
try (rw H1; auto).
induction lbt; simpl; auto.
rw IHlbt; sp.
+ destruct a; simpl.
assert (bterm (snd (bvar_renamings_subst l sub))
(lsubst n (fst (bvar_renamings_subst l sub)))
= bterm l n).
+ rw H with (lv := lv); sp; simpl.
right; auto.
+ apply H0 in H1; sp.
simpl in H1; rw in_app_iff in H1.
apply H1; right; auto.
Qed.
*)
Lemma lsubst_aux_trivial2 {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> @isprogram p u)
-> isprogram t
-> lsubst_aux t sub = t.
Proof.
introv k isp; apply lsubst_aux_trivial; introv ins.
apply_in_hyp pp.
inversion isp as [c w].
dands; try (complete sp).
intro ivt.
rw c in ivt; sp.
Qed.
Lemma lsubst_trivial2 {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> @isprogram p u)
-> isprogram t
-> lsubst t sub = t.
Proof.
intros. change_to_lsubst_aux4.
apply lsubst_aux_trivial2;sp.
Qed.
Lemma csubst_get_cterm {p} :
forall t sub,
@csubst p (get_cterm t) sub = get_cterm t.
Proof.
unfold csubst; sp.
rw @lsubst_trivial2; sp.
allapply @in_csub2sub; sp.
Qed.
Theorem disjoint_lbt_bt2 {p} : forall vs lbt lv nt,
disjoint vs (flat_map (@bound_vars_bterm p) lbt)
-> LIn (bterm lv nt) lbt
-> disjoint vs lv # disjoint vs (bound_vars nt).
Proof. introv Hink1 Hin. apply disjoint_sym in Hink1;rw disjoint_flat_map_l in Hink1.
apply Hink1 in Hin. simpl in Hin. rw disjoint_app_l in Hin. repnd.
split; apply disjoint_sym; trivial.
Qed.
Ltac disjoint_flat := allunfold disjoint_bv_sub; allunfold sub_range_sat; allsimpl;
repeat match goal with
|[ H: (LIn (_,?t) ?sub), H2 : (disjoint (flat_map ?f (range ?sub)) ?l) |- disjoint (?f ?t) ?l ] =>
exact ((tiff_snd (disjoint_sub_as_flat_map _ _ _) H2 _ _ H))
|[ H: (LIn (_,?t) ?sub), H2 : (disjoint ?l (flat_map ?f (range ?sub))) |- disjoint (?f ?t) ?l ] =>
exact ((tiff_snd (disjoint_sub_as_flat_map _ _ _)
(disjoint_sym_impl _ _ _ H2) _ _ H))
|[ H: (LIn (bterm ?lv _) ?lbt), H2 : (disjoint (flat_map free_vars (range ?sub))
(flat_map bound_vars_bterm ?lbt)) |- _ ] =>
pose proof (disjoint_lbt_bt2 _ _ _ _ H2 H); apply hide_hyp in H2
|[ H: (LIn (bterm ?lv _) ?lbt), H2 : (disjoint (flat_map bound_vars_bterm ?lbt)
(flat_map free_vars (range ?sub))) |- _ ] =>
pose proof (disjoint_lbt_bt2 _ _ _ _ (disjoint_sym_impl _ _ _ H2) H);
apply hide_hyp in H
| [ H:( forall _ _, LIn (_, _) _
-> disjoint (free_vars _) _) |- _ ] =>
apply disjoint_sub_as_flat_map in H
| [ |- ( forall _ _, LIn (_, _) _
-> disjoint (free_vars _) _) ] =>
apply disjoint_sub_as_flat_map
end ; allrw <- hide_hyp.
Theorem disjoint_sub_filter_r_flatmap {p} :
forall {T:Type} lvi lnt lvis lnts lv
(ld: list T) (f:NTerm-> list T),
@sub_filter p (combine lvi lnt) lv = combine lvis lnts
-> length lvi =length lnt
-> length lvis =length lnts
-> disjoint (flat_map f lnt) ld
-> disjoint (flat_map f lnts) ld.
Proof.
introv Hsf Hlen Hle1n Hdis. introv Hin Hc.
apply lin_flat_map in Hin. exrepnd.
apply combine_in_right with (l1:=lvis) in Hin1; auto; [| omega];[].
rename Hin1 into Hinc. exrepnd. rw <- Hsf in Hinc0.
apply in_sub_filter in Hinc0. repnd. apply in_combine in Hinc1. repnd.
assert({x : NTerm $ LIn x lnt # LIn t (f x)}) as XX by(eexists; eauto).
allrw <- lin_flat_map.
apply Hdis in XX. sp.
Qed.
Theorem disjoint_sub_filter_r_flatmap2 {p} : forall {T:Type} sub lv
(ld: list T) (f:NTerm-> list T),
disjoint (flat_map f (@range p sub)) ld
-> disjoint (flat_map f (range (sub_filter sub lv))) ld.
Proof.
introv. pose proof (sub_eta (sub_filter sub lv)) as YY.
pose proof (sub_eta sub) as XX.
rewrite XX in YY at 1.
pose proof (sub_eta_length sub).
pose proof (sub_eta_length (sub_filter sub lv)).
eapply disjoint_sub_filter_r_flatmap; eauto.
Qed.
Ltac disjoint_flat_sf :=
repeat match goal with
| [|- disjoint (flat_map _ (range (sub_filter _ _))) _] =>
apply disjoint_sub_filter_r_flatmap2
| [|- disjoint _ (flat_map _ (range (sub_filter _ _)))] =>
apply disjoint_sym; apply disjoint_sub_filter_r_flatmap2
end.
Lemma simple_lsubst_aux_app {p} :
forall t sub1 sub2,
(forall v u, LIn (v, u) sub1 -> isprogram u)
-> (forall v u, LIn (v, u) sub2 -> @isprogram p u)
-> lsubst_aux (lsubst_aux t sub1) sub2 = lsubst_aux t (sub1 ++ sub2).
Proof.
nterm_ind t Case; simpl; intros; auto.
- Case "vterm".
remember (sub_find sub1 n); destruct o; symmetry in Heqo; simpl; sp.
+ rewrite sub_find_some_app with (t := n0); sp.
apply sub_find_some in Heqo.
apply_in_hyp pp.
rw @lsubst_aux_trivial2; sp.
+ rw @sub_find_app.
rw Heqo; auto.
- Case "oterm". f_equal.
induction lbt; simpl; auto.
rw IHlbt; sp;
try (rewrite H with (lv := lv); sp; simpl; sp).
f_equal.
destruct a; simpl.
rewrite H with (lv := l); sp.
rw @sub_filter_app; auto.
allrw @in_sub_filter; sp.
apply_in_hyp pp; sp.
allrw @in_sub_filter; sp.
apply_in_hyp pp; sp.
Defined.
Lemma simple_lsubst_app {p} :
forall t sub1 sub2,
(forall v u, LIn (v, u) sub1 -> isprogram u)
-> (forall v u, LIn (v, u) sub2 -> @isprogram p u)
-> lsubst (lsubst t sub1) sub2 = lsubst t (sub1 ++ sub2).
Proof.
intros. assert(prog_sub (sub1++sub2)) by (apply sub_app_sat;sp).
change_to_lsubst_aux4.
apply simple_lsubst_aux_app; sp.
Qed.
Lemma csubst_app {p} :
forall t sub1 sub2,
csubst (@csubst p t sub1) sub2 = csubst t (sub1 ++ sub2).
Proof.
unfold csubst; sp.
rw @simple_lsubst_app; sp; try (allapply @in_csub2sub; sp).
rw @csub2sub_app; sp.
Defined.
(* This is not true because lsubst might renames some bound variables of t
that occur in the free variables of sub.
Lemma lsubst_isprogram :
forall t sub,
isprogram t
-> lsubst t sub = t.
Proof.
nterm_ind t Case; simpl; intros.
- Case "vterm".
rw isprogram_vterm in H; sp.
- Case "oterm".
Qed.
*)
Definition subst_aux {p} (t : @NTerm p) (v : NVar) (u : NTerm) : NTerm :=
lsubst_aux t [(v,u)].
Definition subst {p} (t : @NTerm p) (v : NVar) (u : NTerm) : NTerm :=
lsubst t [(v,u)].
Lemma axiom_sub_as_csubst {p} :
forall t x,
@subst p t x mk_axiom = csubst t [(x,mkc_axiom)].
Proof.
sp.
Qed.
(* in a separate commit, we might want to make everything compatible with
Notation apply_bterm (bt :BTerm) (lnt: list NTerm) : NTerm :=
match bt with
| bterm lv nt => lsubst nt (combine lv lnt)
end.
*)
Lemma apply_bterm_nobnd {p} :
forall t,
apply_bterm (@nobnd p t) [] = t.
Proof.
unfold apply_bterm, get_nt, nobnd; simpl; sp.
rw @lsubst_nil; auto.
Qed.
Lemma num_bvars_bterm {p} :
forall bt sub,
num_bvars (@lsubst_bterm_aux p bt sub) = num_bvars bt.
Proof.
destruct bt; unfold num_bvars; simpl; sp.
Qed.
Lemma map_num_bvars_bterms {p} :
forall bts sub,
map num_bvars (map (fun t : @BTerm p => lsubst_bterm_aux t sub) bts) =
map num_bvars bts.
Proof.
induction bts; simpl; sp.
rw @num_bvars_bterm; rw IHbts; auto.
Qed.
Lemma remove_nvars_comb {p} :
forall sub l vars,
remove_nvars (l ++ dom_sub (@sub_filter p sub l)) vars
= remove_nvars (l ++ dom_sub sub) vars.
Proof.
induction sub; simpl; sp.
remember (memvar a0 l); destruct b; symmetry in Heqb; simpl.
rw fold_assert in Heqb.
rw assert_memvar in Heqb.
rw IHsub.
rw <- remove_nvars_dup; auto.
repeat (rw remove_nvars_move).
repeat (rw remove_nvars_cons).
rw IHsub; auto.
Qed.
Lemma isprogram_lsubst_aux1 {p} :
forall t : NTerm,
forall sub : @Substitution p,
nt_wf t
-> (forall v u, LIn (v, u) sub -> isprogram u)
-> nt_wf (lsubst_aux t sub)
# free_vars (lsubst_aux t sub) = remove_nvars (dom_sub sub) (free_vars t).
Proof.
nterm_ind t as [|f ind|o lbt ind] Case; simpl; introv wf k; auto.
- Case "vterm".
remember (sub_find sub n); destruct o; symmetry in Heqo; simpl.
+ apply sub_find_some in Heqo.
apply_in_hyp pp.
unfold isprogram, closed in pp; sp.
allrw.
symmetry; rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp; subst.
apply in_dom_sub in Heqo; sp.
+ sp.
apply sub_find_none2 in Heqo.
symmetry.
rw <- remove_nvars_unchanged.
unfold disjoint; simpl; sp; subst; auto.
- Case "sterm".
allrw remove_nvars_nil_r; dands; auto.
- Case "oterm".
inversion wf; subst; sp.
+ constructor.
introv i.
allrw in_map_iff; exrepnd; subst.
destruct a; simpl.
constructor.
apply ind with (sub := sub_filter sub l) in i1; sp.
apply_in_hyp pp.
inversion pp; subst; auto.
apply k with (v := v).
assert (subset (sub_filter sub l) sub) as s by apply sub_filter_subset.
unfold subset in s.
apply_in_hyp pp; sp.
allrw <-.
apply map_num_bvars_bterms.
+ auto.
rw flat_map_map; unfold compose.
rw remove_nvars_flat_map; unfold compose.
apply eq_flat_maps; introv i.
destruct x; simpl.
apply_in_hyp pp.
inversion pp as [vs t w]; subst.
apply ind with (sub := sub_filter sub l) in i; sp.
allrw.
rw remove_nvars_app_l.
rw remove_nvars_comm.
rw remove_nvars_app_l.
rw @remove_nvars_comb; auto.
apply k with (v := v).
assert (subset (sub_filter sub l) sub) as s by apply sub_filter_subset.
unfold subset in s.
discover; sp.
Qed.
Lemma isprogram_lsubst1 {p} :
forall t : NTerm,
forall sub : @Substitution p,
nt_wf t
-> (forall v u, LIn (v, u) sub -> isprogram u)
-> nt_wf (lsubst t sub)
# free_vars (lsubst t sub) = remove_nvars (dom_sub sub) (free_vars t).
Proof.
intros. change_to_lsubst_aux4.
apply isprogram_lsubst_aux1;sp.
Qed.
Lemma isprogram_lsubst_nt_wf {p} :
forall t : WTerm,
forall sub : @CSubstitution p,
nt_wf (csubst (get_wterm t) sub).
Proof.
sp; destruct t; allsimpl.
apply isprogram_lsubst1; sp.
rw @nt_wf_eq; sp.
allapply @in_csub2sub; sp.
Qed.
Lemma isprogram_lsubst_wf_term {p} :
forall t : @WTerm p,
forall sub : CSubstitution,
wf_term (csubst (get_wterm t) sub).
Proof.
sp; rw @wf_term_eq.
apply isprogram_lsubst_nt_wf.
Qed.
Definition wf_term_csubst {p} :
forall t : NTerm,
forall sub : @CSubstitution p,
wf_term t
-> wf_term (csubst t sub).
Proof.
sp; allrw @wf_term_eq.
apply isprogram_lsubst1; sp.
allapply @in_csub2sub; sp.
Qed.
Definition lsubstw {p} (t : @WTerm p) (sub : CSubstitution) : WTerm :=
exist wf_term (csubst (get_wterm t) sub) (isprogram_lsubst_wf_term t sub).
Lemma lsubstw_nil {p} :
forall t, @lsubstw p t [] = t.
Proof.
intro; destruct t; unfold lsubstw; simpl.
Abort.
Lemma isprogram_lsubst_aux2 {p} :
forall t : @NTerm p,
forall sub : Substitution,
(forall v u, LIn (v, u) sub -> isprogram u)
-> free_vars (lsubst_aux t sub) = remove_nvars (dom_sub sub) (free_vars t).
Proof.
nterm_ind t as [|f ind| o lbt ind ] Case; simpl; introv k.
- Case "vterm".
remember (sub_find sub n); destruct o; symmetry in Heqo; simpl.
+ apply sub_find_some in Heqo.
discover.
allunfold @isprogram; allunfold @closed; sp.
allrw.
symmetry.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp; subst.
apply in_dom_sub in Heqo; sp.
+ apply sub_find_none2 in Heqo.
symmetry.
rw <- remove_nvars_unchanged.
unfold disjoint; simpl; sp; subst; auto.
- Case "sterm".
rw remove_nvars_nil_r; auto.
- Case "oterm".
auto.
rw flat_map_map; unfold compose.
rw remove_nvars_flat_map; unfold compose.
apply eq_flat_maps; introv i.
destruct x; simpl.
apply ind with (sub := sub_filter sub l) in i; sp.
allrw.
rw remove_nvars_app_l.
rw remove_nvars_comm.
rw remove_nvars_app_l.
rw @remove_nvars_comb; auto.
apply k with (v := v).
assert (subset (sub_filter sub l) sub) as s by apply sub_filter_subset.
unfold subset in s.
discover; sp.
Qed.
Lemma isprogram_lsubst2 {p} :
forall t : @NTerm p,
forall sub : Substitution,
(forall v u, LIn (v, u) sub -> isprogram u)
-> free_vars (lsubst t sub) = remove_nvars (dom_sub sub) (free_vars t).
Proof.
intros. change_to_lsubst_aux4.
apply isprogram_lsubst_aux2;sp.
Qed.
Lemma free_vars_csubst {p} :
forall t : @NTerm p,
forall sub : CSubstitution,
free_vars (csubst t sub)
= remove_nvars (dom_sub (csub2sub sub)) (free_vars t).
Proof.
sp; apply isprogram_lsubst2; sp.
allapply @in_csub2sub; sp.
Qed.
Lemma isprogram_lsubst {p} :
forall t : @NTerm p,
forall sub : Substitution,
nt_wf t
-> (forall v u, LIn (v, u) sub -> isprogram u)
-> (forall v, LIn v (free_vars t) -> LIn v (dom_sub sub))
-> isprogram (lsubst t sub).
Proof.
introv w k1 k2.
unfold isprogram.
apply @isprogram_lsubst1 with (sub := sub) in w; sp.
unfold closed.
allrw.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
Qed.
(*
Lemma isprogram_lcsubst0 :
forall vs : list NVar,
forall t : CVTerm vs,
forall sub : CSubOver vs,
isprogram (lsubst (get_cvterm vs t) (csubo2sub vs sub)).
Proof.
sp.
destruct t, sub; allunfold dom_csubo; allunfold csubo2sub; allsimpl.
allrw isprog_vars_eq; sp.
apply isprogram_lsubst; allsimpl; sp.
apply in_csub2sub in H1; sp.
allrw subvars_prop.
apply H in H1.
allrw over_vars_eq.
allrw subvars_prop.
apply o in H1.
allapply in_dom_csub_exists; sp.
allapply sub_find_some.
exists t; sp.
Qed.
Lemma isprog_lcsubst0 :
forall vs : list NVar,
forall t : CVTerm vs,
forall sub : CSubOver vs,
isprog (lsubst (get_cvterm vs t) (csubo2sub vs sub)).
Proof.
sp; rw isprog_eq; apply isprogram_lcsubst0.
Qed.
Definition lsubstc0 (vs : list NVar)
(t : CVTerm vs)
(sub : CSubOver vs) : CTerm :=
exist isprog
(lsubst (get_cvterm vs t) (csubo2sub vs sub))
(isprog_lcsubst0 vs t sub).
*)
Lemma isprogram_csubst {p} :
forall t : @NTerm p,
forall sub : CSubstitution,
nt_wf t
-> cover_vars t sub
-> isprogram (csubst t sub).
Proof.
sp.
apply isprogram_lsubst; sp.
allapply @in_csub2sub; sp.
allrw @cover_vars_eq.
allrw subvars_prop.
apply_in_hyp pp.
allapply @in_dom_csub_exists; sp.
allapply @sub_find_some.
allapply @in_dom_sub; sp.
Qed.
Lemma isprog_csubst {p} :
forall t : @NTerm p,
forall sub : CSubstitution,
wf_term t
-> cover_vars t sub
-> isprog (csubst t sub).
Proof.
sp; allsimpl; rw @isprog_eq; apply isprogram_csubst; sp.
rw @nt_wf_eq; sp.
Defined.
Lemma isprog_csubst_pi {p} :
forall t sub w1 w2 c1 c2,
@isprog_csubst p t sub w1 c1 = isprog_csubst t sub w2 c2.
Proof.
sp.
eauto with pi.
Qed.
Definition lsubstc {p}
(t : @NTerm p)
(w : wf_term t)
(sub : CSubstitution)
(p : cover_vars t sub) : CTerm :=
exist isprog
(csubst t sub)
(isprog_csubst t sub w p).
Lemma lsubstc_replace {p} :
forall t w1 w2 s p1 p2,
@lsubstc p t w1 s p1 = lsubstc t w2 s p2.
Proof.
introv.
destruct_cterms.
apply cterm_eq; simpl; auto.
Qed.
Lemma lsubstc_cterm {p} :
forall t w s c,
@lsubstc p (get_cterm t) w s c = t.
Proof.
introv.
apply cterm_eq; simpl.
unfold csubst.
apply lsubst_trivial; introv i.
rw @free_vars_cterm; simpl; sp.
apply in_csub2sub in i; sp.
Qed.
Lemma lsubstc_eq {p} :
forall t1 t2 w1 w2 s1 s2 p1 p2,
t1 = t2
-> s1 = s2
-> @lsubstc p t1 w1 s1 p1 = lsubstc t2 w2 s2 p2.
Proof.
sp.
revert p1 p2 w1 w2.
rewrite H, H0; sp.
apply lsubstc_replace.
Qed.
Lemma lsubstc_ex {pp} :
forall t w s p,
{w' : @wf_term pp t & {p' : cover_vars t s &
lsubstc t w s p = lsubstc t w' s p'}}.
Proof.
sp; exists w p; auto.
Qed.
Lemma free_vars_csubst_sub {p} :
forall t sub vs,
subvars (free_vars (@csubst p t sub)) vs
-> subvars (free_vars t) (dom_csub sub ++ vs).
Proof.
sp; allrewrite @free_vars_csubst.
allrw subvars_remove_nvars.
allrewrite @dom_csub_eq.
rw subvars_comm_r; sp.
Qed.
Lemma free_vars_csubst_sub_iff {p} :
forall t sub vs,
subvars (free_vars (@csubst p t sub)) vs
<=> subvars (free_vars t) (dom_csub sub ++ vs).
Proof.
sp; split; sp; try (apply free_vars_csubst_sub; auto).
rw @free_vars_csubst.
rw subvars_remove_nvars.
rw @dom_csub_eq.
rw subvars_comm_r; sp.
Qed.
Lemma cover_vars_csubst {p} :
forall t sub1 sub2,
@cover_vars p t (sub1 ++ sub2)
<=>
cover_vars (csubst t sub1) sub2.
Proof.
intros.
repeat (rw @cover_vars_eq).
rw @dom_csub_app.
rw @free_vars_csubst_sub_iff; sp.
Qed.
Lemma cover_vars_csubst2 {p} :
forall t sub1 sub2,
cover_vars (@csubst p t sub1) sub2
<=>
cover_vars_upto t sub2 (dom_csub sub1).
Proof.
intros.
rw <- @cover_vars_csubst.
repeat (rw @cover_vars_eq).
unfold cover_vars_upto.
rw @dom_csub_app; sp.
Qed.
Lemma cover_vars_csubst3 {p} :
forall t sub1 sub2,
cover_vars (@csubst p t sub1) sub2
<=>
cover_vars_upto t (csub_filter sub2 (dom_csub sub1)) (dom_csub sub1).
Proof.
intros.
rw @cover_vars_csubst2.
unfold cover_vars_upto.
rewrite dom_csub_csub_filter.
rw subvars_app_remove_nvars_r; sp.
Qed.
Lemma subst_preserves_program {p} :
forall t v u,
@nt_wf p t
-> (forall x, LIn x (free_vars t) -> x = v)
-> isprogram u
-> isprogram (subst t v u).
Proof.
introv w k isp.
apply isprogram_lsubst with (sub := [(v,u)]) in w; allsimpl; sp; inj; sp.
apply_in_hyp pp; subst; sp.
Qed.
Lemma subst_preserves_isprog {p} :
forall t : @NTerm p,
forall v : NVar,
forall u : NTerm,
isprog_vars [v] t
-> isprog u
-> isprog (subst t v u).
Proof.
introv ispt ispu.
allrw <- @isprogram_eq.
allunfold @isprog_vars; repnd.
allrw <- @nt_wf_eq.
apply subst_preserves_program; tcsp.
introv i.
allrw assert_sub_vars.
apply ispt0 in i; allsimpl; sp.
Qed.
Hint Resolve subst_preserves_isprog : isprog.
Definition substc {p} (u : @CTerm p) (v : NVar) (t : CVTerm [v]) : CTerm :=
let (a,x) := t in
let (b,y) := u in
exist isprog (subst a v b) (subst_preserves_isprog a v b x y).
Tactic Notation "allrwxxx" constr(T) :=
repeat match goal with
| [ H : _ |- _ ] =>
progress (trw_h T H || trw T || rewrite T in H || rewrite T)
end.
Tactic Notation "allrwxxx" ident(T) :=
let t := type of T in
repeat match goal with
| [ H1 : t, H : _ |- _ ] =>
progress (trw_h T H || trw T || rewrite T in H || rewrite T)
end.
Lemma substc_cvterm_var {p} :
forall t v u,
substc t v (@cvterm_var p v u) = u.
Proof.
introv; destruct_cterms.
apply cterm_eq; simpl.
apply lsubst_trivial; simpl; introv h; repndors; tcsp; ginv.
allrw <- @isprogram_eq; dands; auto.
intro h.
inversion i as [c w].
unfold closed in c; rw c in h; allsimpl; sp.
Qed.
(** the lsubst version of this is best done after
we have the lemma that alpha_equality preserves wf
lsubst_wf_iff is proved in alphaeq.v*)
Lemma lsubst_aux_preserves_wf {p} :
forall t : @NTerm p,
forall sub : Substitution,
nt_wf t
-> (forall v u, LIn (v, u) sub -> nt_wf u)
-> nt_wf (lsubst_aux t sub).
Proof.
nterm_ind1 t as [?|f ind| o lbt Hind]Case; simpl; introv HX hwf; auto.
- Case "vterm".
remember (sub_find sub n); destruct o; symmetry in Heqo; sp.
apply sub_find_some in Heqo.
apply_in_hyp pp; sp.
- Case "oterm".
invertsna HX Hwf; subst.
allrw in_map_iff; sp; subst.
constructor.
Focus 2. rw @map_num_bvars_bterms;sp;fail.
intros bt Hin.
apply in_map_iff in Hin; exrepnd; destruct a as [lv nt].
allsimpl. subst.
constructor.
eapply Hind; eauto;[|].
+ apply Hwf in Hin1.
invertsn Hin1;sp.
+ introv Hin. apply in_sub_filter in Hin. sp.
discover; sp.
Qed.
Lemma in_var_ren {p} : forall lvi lvo u t,
LIn (u, t) (var_ren lvi lvo)
-> (LIn u lvi) # {v:NVar & (t = @vterm p v) # (LIn v lvo)}.
Proof.
introv Hl.
apply in_combine in Hl.
repnd. apply in_map_iff in Hl.
exrepnd.
split; cpx.
eexists; eauto.
Defined.
(**This is a trivial consequence of the fact that
its output is alpha equal to input. But lemma that comes
way too late in alpha_eq.v. Hence, a direct proof here*)
Lemma change_bvars_alpha_preserves_wf {p} :
forall (nt : @NTerm p) lv,
nt_wf nt
-> nt_wf (change_bvars_alpha lv nt).
Proof.
nterm_ind1 nt as [v|f ind| o lbt Hind] Case; introv HX; auto;[].
invertsna HX Hwf; subst.
simpl; constructor.
- introv i.
rw in_map_iff in i; exrepnd; subst.
destruct a; simpl.
remember (fresh_vars (length l) (lv ++ all_vars (change_bvars_alpha lv n))) as s.
destruct s; allsimpl; repnd.
constructor.
apply lsubst_aux_preserves_wf; auto.
+ eapply Hind; eauto.
apply Hwf in i1; inversion i1; subst; auto.
+ introv k.
apply in_var_ren in k; exrepnd; subst; auto.
- rw <- Hwf0.
rw map_map.
apply eq_maps; introv k.
unfold compose, num_bvars.
destruct x; simpl.
pose proof (fresh_distinct_vars_spec
(length l)
(lv ++ all_vars (change_bvars_alpha lv n))) as h;
simpl in h; sp.
Qed.
Definition wf_lsubst_to_lsubst {p} (sub : @WfSubstitution p) : Substitution :=
map (fun x => (fst x, get_wterm (snd x))) sub.
(** TODO: non aux version *)
Lemma lsubst_aux_preserves_wf_term {p} :
forall t : NTerm,
forall sub : @Substitution p,
wf_term t
-> (forall v u, LIn (v, u) sub -> wf_term u)
-> wf_term (lsubst_aux t sub).
Proof.
sp.
rw <- @nt_wf_eq.
apply lsubst_aux_preserves_wf; sp.
rw @nt_wf_eq; auto.
apply_in_hyp pp.
rw @nt_wf_eq; auto.
Qed.
(* Abhishek, is that easy to prove? *)
Lemma lsubst_preserves_wf_term {p} :
forall t : NTerm,
forall sub : @Substitution p,
wf_term t
-> (forall v u, LIn (v, u) sub -> wf_term u)
-> wf_term (lsubst t sub).
Proof.
sp.
unfold lsubst.
destruct (dec_disjointv (bound_vars t) (flat_map free_vars (range sub)));
try (apply lsubst_aux_preserves_wf_term; sp).
Abort.
(*
(** TODO: non aux version *)
Lemma lsubst_aux_preserves_wf_term' {p} :
forall t : NTerm,
forall sub : @Substitution p,
wf_term t
-> assert (ball (map (fun x => wft (snd x)) sub))
-> wf_term (lsubst_aux t sub).
Proof.
intros.
apply lsubst_aux_preserves_wf_term; sp.
rw <- fold_assert in H0.
rw ball_map_true in H0.
apply_in_hyp pp.
allfold (wf_term u); auto.
Qed.
*)
(*
Definition wf_lsubst (t : WTerm) (sub : WfSubstitution) : WTerm :=
let (a,w) := t in
let s := wf_lsubst_to_lsubst sub in
exist
wf_term
(lsubst a s)
(lsubst_preserves_wf_term'
a
s
w
(eq_refl (ball (map (fun x => snd x) sub)))).
*)
(** TODO: non aux version *)
Lemma subst_aux_preserves_wf {p} :
forall t : NTerm,
forall v : NVar,
forall u : @NTerm p,
nt_wf t
-> nt_wf u
-> nt_wf (subst_aux t v u).
Proof.
introv wt wu.
apply lsubst_aux_preserves_wf with (sub := [(v,u)]) in wt; allsimpl; sp; inj.
Qed.
(** TODO: non aux version *)
Lemma subst_aux_preserves_wf_term {p} :
forall t : @NTerm p,
forall v : NVar,
forall u : NTerm,
wf_term t
-> wf_term u
-> wf_term (subst_aux t v u).
Proof.
intros t v u.
repeat (rw <- @nt_wf_eq); sp.
apply subst_aux_preserves_wf; auto.
Qed.
(** TODO: non aux version *)
Definition substwf {p} (t : @WTerm p) (v : NVar) (u : WTerm) : WTerm :=
let (a,x) := t in
let (b,y) := u in
exist wf_term (subst_aux a v b) (subst_aux_preserves_wf_term a v b x y).
(*
Lemma isprogram_bt_iff :
forall vs t,
(forall sub,
(forall v u, LIn (v, u) sub -> isprogram u)
-> (forall v, LIn v vs -> exists u, LIn (v, u) sub)
-> isprogram (lsubst t sub))
<=> isprogram_bt (bterm vs t).
Proof.
unfold isprogram_bt, closed_bt, isprogram, closed; simpl; sp.
rw <- null_nil.
rw <- null_nil in H1.
rw null_remove_nvars; sp.
aXdmit.
aXdmit.
Qed.
*)
Lemma isprogram_bt_implies2 {p} :
forall (bt: @BTerm p),
isprogram_bt bt
-> forall lnt : list NTerm,
(forall nt : NTerm, LIn nt lnt -> isprogram nt)
-> num_bvars bt <= length lnt
-> isprogram (apply_bterm bt lnt).
Proof.
intros ? Hprog ? Hprognt Hlen. inverts Hprog as Hclos Hwf.
inverts Hwf. unfold num_bvars in Hlen. simpl in Hlen.
unfold apply_bterm. simpl. apply isprogram_lsubst; auto.
- intros ? ? Htemp. apply in_combine in Htemp; sp.
- intros ? Hin.
inverts Hclos as Hrem.
apply null_iff_nil in Hrem.
unfold remove_nvars in Hrem. rw null_diff in Hrem.
assert (LIn v lnv) as Hinv by (apply Hrem; auto).
apply in_nth in Hinv; try (apply deq_nvar).
destruct Hinv as [n Hp].
rw @dom_sub_combine_le; sp.
Qed.
Lemma isprogram_bt_implies {p} :
forall (bt:@BTerm p),
isprogram_bt bt
-> forall lnt : list NTerm,
(forall nt : NTerm, LIn nt lnt -> isprogram nt)
-> num_bvars bt = length lnt
-> isprogram (apply_bterm bt lnt).
Proof.
intros ? Hprog ? Hprognt Hlen. apply isprogram_bt_implies2; auto. omega.
Qed.
(*
Lemma isprogram_lsubst_implies :
forall t sub,
isprogram (lsubst t sub)
-> forall v u,
alpha_eq [] t u
-> LIn v (free_vars u)
-> exists u, sub_find sub v = Some u # isprogram u.
Proof.
nterm_ind t Case; simpl; intros.
- Case "vterm".
unfold lsubst in H; simpl in H.
sp; subst.
remember (sub_find sub v); destruct o; symmetry in Heqo.
exists n; sp.
rw isprogram_vterm in H; sp.
- Case "oterm".
rw isprogram_ot_iff in H0; sp.
rw in_flat_map in H1; sp.
destruct x.
simpl in H3.
rw in_remove_nvars in H3; sp.
generalize (H2 (lsubst_bterm (bterm l n) sub)); sp.
dimp H5.
rw in_map_iff. exists (bterm l n); sp.
apply isprogram_bt_implies with (lnt := map (fun v => mk_axiom) (fst (fst (bvar_renamings_subst l sub)))) in hyp; sp.
unfold apply_bterm in hyp.
simpl in hyp.
rw bvar_renamings_subst_eta in hyp.
apply isprogram_bt_implies with (lnt := map (fun v => mk_axiom) (fst (fst (bvar_renamings_subst l sub)))) in hyp; sp.
unfold apply_bterm in hyp; simpl in hyp.
apply H with (lv := ) in hyp.
rw in_map_iff in H6; sp; subst.
apply isprogram_axiom.
rw num_bvars_on_bterm.
rw map_length; auto.
apply H with (nt := n) (lv := l); auto.
Abort.
*)
Lemma subset_free_vars_sub_aux_app {p} :
forall t sub1 sub2,
(forall v t, LIn (v, t) (sub1 ++ sub2) -> @isprogram p t)
-> disjoint (free_vars t) (dom_sub sub2)
-> lsubst_aux t (sub1 ++ sub2) = lsubst_aux t sub1.
Proof.
nterm_ind t Case; simpl; introv k d; auto.
- Case "vterm".
allrw disjoint_singleton_l; sp.
remember (sub_find sub1 n); destruct o; symmetry in Heqo.
apply @sub_find_some_app with (sub2 := sub2) in Heqo.
rw Heqo; auto.
rw @sub_find_none_iff in Heqo.
assert (! LIn n (dom_sub (sub1 ++ sub2))) as nin
by (rw @dom_sub_app; rw in_app_iff; intro; sp).
rw <- @sub_find_none_iff in nin.
rw nin; auto.
- Case "oterm".
f_equal.
apply eq_maps; sp.
destruct x; simpl.
repeat (rw bvar_renamings_subst_isprogram; auto); simpl;
try (sp; apply X with (v := v); rw in_app_iff; sp).
rw @sub_filter_app.
rewrite H with (lv := l); sp.
apply k with (v := v).
allrw in_app_iff.
allrw @in_sub_filter; sp.
allrw disjoint_flat_map_l.
apply_in_hyp pp.
allsimpl.
rw disjoint_remove_nvars_l in pp.
rw <- @dom_sub_sub_filter; auto.
Qed.
Lemma subset_free_vars_sub_app {p} :
forall t sub1 sub2,
(forall v t, LIn (v, t) (sub1 ++ sub2) -> @isprogram p t)
-> disjoint (free_vars t) (dom_sub sub2)
-> lsubst t (sub1 ++ sub2) = lsubst t sub1.
Proof.
introv Hpr. applydup (sub_app_sat_if (@isprogram p)) in Hpr. repnd.
allfold (prog_sub sub1). intros.
change_to_lsubst_aux4.
apply subset_free_vars_sub_aux_app;sp.
Qed.
Lemma sub_find_member {p} :
forall sub1 sub2 x t,
! LIn x (@dom_sub p sub1)
-> sub_find (sub1 ++ (x, t) :: sub2) x = Some t.
Proof.
induction sub1; simpl; sp.
rw <- beq_var_refl; auto; allsimpl.
remember (beq_var a0 x); destruct b.
apply beq_var_eq in Heqb; subst.
provefalse; apply H; left; auto.
symmetry in Heqb.
apply beq_var_false_not_eq in Heqb.
apply IHsub1; sp.
Qed.
Lemma sub_filter_map_trivial_vars {p} :
forall vars l,
sub_filter (map (fun v : NVar => (v, vterm v)) vars) l
= map (fun v : NVar => (v, @vterm p v)) (remove_nvars l vars).
Proof.
induction vars; simpl; sp.
rw remove_nvars_nil_r; simpl; auto.
rw IHvars.
rw remove_nvars_cons_r.
destruct (memvar a l); auto.
Qed.
Lemma sub_find_sub_filter_some {p} :
forall l v t sub,
(sub_find (@sub_filter p sub l) v = Some t)
<=> (sub_find sub v = Some t # ! LIn v l).
Proof.
induction sub; simpl; sp; split; sp; allsimpl.
remember (beq_var a0 v); destruct b.
apply beq_var_eq in Heqb; subst.
remember (memvar v l); destruct b; allsimpl.
rw IHsub in H; sp.
symmetry in Heqb.
rw fold_assert in Heqb.
rw assert_memvar in Heqb; sp.
rw <- beq_var_refl in H; allsimpl; sp.
symmetry in Heqb.
applydup beq_var_false_not_eq in Heqb.
remember (memvar a0 l); destruct b; allsimpl.
rw IHsub in H; sp.
rw Heqb in H.
rw IHsub in H; sp.
remember (memvar a0 l); destruct b; allsimpl.
rw IHsub in H; sp.
symmetry in Heqb.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb.
remember (beq_var a0 v); destruct b.
apply beq_var_eq in Heqb0; subst; sp.
rw IHsub in H; sp.
remember (memvar a0 l); destruct b; allsimpl.
symmetry in Heqb; rw fold_assert in Heqb; rw assert_memvar in Heqb.
rw IHsub; sp.
remember (beq_var a0 v); destruct b; sp.
apply beq_var_eq in Heqb0; subst; sp.
remember (beq_var a0 v); destruct b; sp.
rw IHsub; sp.
Qed.
Lemma sub_find_sub_filter_none {p} :
forall l v sub,
(sub_find (@sub_filter p sub l) v = None)
<=> (sub_find sub v = None [+] LIn v l).
Proof.
induction sub; simpl; sp; split; sp; allsimpl;
remember (memvar a0 l); destruct b; allsimpl;
duplicate Heqb as eq;
symmetry in Heqb;
try (rw fold_assert in Heqb; rw assert_memvar in Heqb);
try (rw not_of_assert in Heqb; rw assert_memvar in Heqb);
remember (beq_var a0 v); destruct b;
duplicate Heqb0 as eq2;
try (apply beq_var_eq in Heqb0; subst);
try (symmetry in Heqb0; apply beq_var_false_not_eq in Heqb0); sp;
try (complete (apply IHsub; auto)).
Qed.
Lemma sub_filter_swap {p} :
forall l1 l2 sub,
sub_filter (@sub_filter p sub l1) l2
= sub_filter (sub_filter sub l2) l1.
Proof.
induction sub; simpl; sp.
remember (memvar a0 l1); destruct b; remember (memvar a0 l2); destruct b; simpl; sp.
rw <- Heqb; sp.
rw <- Heqb0; sp.
rw <- Heqb; sp.
rw <- Heqb0; sp.
rw IHsub; sp.
Qed.
Lemma sub_filter_app_as_remove_nvars {p} :
forall sub l1 l2,
@sub_filter p sub (l1 ++ l2)
= sub_filter sub (l1 ++ remove_nvars l1 l2).
Proof.
induction sub; simpl; sp; allsimpl.
remember (memvar a0 (l1 ++ l2)); symmetry in Heqb; destruct b.
rw fold_assert in Heqb; rw assert_memvar in Heqb.
rw in_app_iff in Heqb; sp.
remember (memvar a0 (l1 ++ remove_nvars l1 l2)); symmetry in Heqb; destruct b.
rw fold_assert in Heqb; rw assert_memvar in Heqb; rw in_app_iff in Heqb; sp.
rw not_of_assert in Heqb; rw assert_memvar in Heqb; rw in_app_iff in Heqb.
apply not_over_or in Heqb; sp.
remember (memvar a0 (l1 ++ remove_nvars l1 l2)); symmetry in Heqb; destruct b.
rw fold_assert in Heqb; rw assert_memvar in Heqb; rw in_app_iff in Heqb; sp.
rw not_of_assert in Heqb; rw assert_memvar in Heqb; rw in_app_iff in Heqb.
apply not_over_or in Heqb; repnd.
allrw in_remove_nvars.
provefalse; apply Heqb; sp.
rw not_of_assert in Heqb; rw assert_memvar in Heqb; rw in_app_iff in Heqb.
apply not_over_or in Heqb; repnd.
remember (memvar a0 (l1 ++ remove_nvars l1 l2)); symmetry in Heqb1; destruct b.
rw fold_assert in Heqb1; rw assert_memvar in Heqb1; rw in_app_iff in Heqb1; sp.
allrw in_remove_nvars; sp.
rw <- IHsub; sp.
Qed.
Lemma sub_find_sub_filter_eta {p} :
forall lv v sub,
!LIn v lv
-> sub_find (@sub_filter p sub lv) v
= sub_find sub v.
Proof.
intros.
cases (sub_find (sub_filter sub lv) v) as Hl.
- apply sub_find_sub_filter_some in Hl; repnd; auto.
- apply sub_find_sub_filter_none in Hl. dorn Hl; sp.
Qed.
Lemma lsubst_aux_sub_filter_aux {o} :
forall (t : @NTerm o) sub l,
(forall v, LIn v (free_vars t) -> LIn v l -> !LIn v (dom_sub sub))
-> lsubst_aux t (sub_filter sub l) = lsubst_aux t sub.
Proof.
nterm_ind1 t as [v|f ind|op bs ind] Case; simpl; introv disj; auto.
- Case "vterm".
allrw disjoint_singleton_l.
destruct (in_deq NVar deq_nvar v l) as [i|i].
+ pose proof (disj v) as h; repeat (autodimp h hyp).
rw @sub_find_sub_filter; auto.
apply sub_find_none_iff in h; rw h; auto.
+ rw @sub_find_sub_filter_eta; auto.
- Case "oterm".
f_equal.
apply eq_maps; intros b i.
destruct b as [vs t]; simpl.
f_equal.
rw @sub_filter_swap.
eapply ind; eauto.
introv a b c.
allrw <- @dom_sub_sub_filter.
allrw in_remove_nvars; repnd.
pose proof (disj v) as h.
autodimp h hyp; tcsp.
rw lin_flat_map.
eexists; dands; eauto; simpl.
rw in_remove_nvars; sp.
Qed.
Lemma lsubst_aux_sub_filter {o} :
forall (t : @NTerm o) sub l,
disjoint (free_vars t) l
-> lsubst_aux t (sub_filter sub l) = lsubst_aux t sub.
Proof.
introv disj.
apply lsubst_aux_sub_filter_aux.
introv a b c.
apply disj in a; sp.
Qed.
(*
(** TODO : use the stronger lemma lsubst_aux_sub_filter2 for a smaller and
more maintainable proof*)
Lemma lsubst_aux_sub_filter {p} :
forall t sub l,
(forall v u, LIn (v, u) sub -> @isprogram p u)
-> disjoint (free_vars t) l
-> lsubst_aux t (sub_filter sub l) = lsubst_aux t sub.
Proof.
nterm_ind t Case; simpl; intros.
- Case "vterm".
remember (sub_find (sub_filter sub l) n); symmetry in Heqo; destruct o.
rw @sub_find_sub_filter_some in Heqo; sp.
allrw; sp.
rw @sub_find_sub_filter_none in Heqo; sp.
allrw; sp.
allrw disjoint_singleton_l; sp.
- Case "oterm".
f_equal.
apply eq_maps; sp.
destruct x; simpl.
allrw disjoint_flat_map_l.
apply_in_hyp pp; allsimpl.
allrw disjoint_remove_nvars_l.
repeat (rw bvar_renamings_subst_isprogram; sp).
repeat (rw app_nil_l).
rw @sub_filter_swap.
rw <- @sub_filter_app_r.
rw @sub_filter_app_as_remove_nvars.
rw @sub_filter_app_r.
rewrite H with (lv := l0); sp.
allrw @in_sub_filter; sp.
discover; sp.
Qed.
*)
Lemma lsubst_sub_filter {p} :
forall t sub l,
(forall v u, LIn (v, u) sub -> @isprogram p u)
-> disjoint (free_vars t) l
-> lsubst t (sub_filter sub l) = lsubst t sub.
Proof.
introv Hpr. duplicate Hpr. eapply sub_filter_sat with (lv:=l) in Hpr; eauto.
change_to_lsubst_aux4.
apply lsubst_aux_sub_filter;sp.
Qed.
Lemma csubst_csub_filter {p} :
forall t sub l,
disjoint (free_vars t) l
-> csubst t (@csub_filter p sub l) = csubst t sub.
Proof.
unfold csubst; sp.
rw <- @sub_filter_csub2sub.
apply lsubst_sub_filter; sp.
allapply @in_csub2sub; sp.
Qed.
(* XXXXXXXXXXXXXXXXXXX switch XXXXXXXXXXXXXXXXXXX *)
Lemma lsubst_aux_trivial_vars {p} :
forall t vars,
lsubst_aux t (map (fun v => (v, @vterm p v)) vars) = t.
Proof.
nterm_ind t Case; simpl; intros; auto.
- Case "vterm".
remember (sub_find (map (fun v : NVar => (v, vterm v)) vars) n); destruct o; auto.
symmetry in Heqo.
applydup @sub_find_some in Heqo; rw in_map_iff in Heqo0; sp; inj.
- Case "oterm".
f_equal.
induction lbt; simpl; sp.
rw IHlbt; sp; try (rewrite H with (lv := lv); sp; simpl; sp).
destruct a; simpl.
f_equal. f_equal.
rw @sub_filter_map_trivial_vars.
rewrite H with (lv := l); sp.
Qed.
Lemma apply_bterm_append_program_id {p} :
forall bt lnt lnta ,
(isprogram (apply_bterm bt lnt)) ->
(forall nt, LIn nt lnt -> isprogram nt) ->
(forall nt, LIn nt lnta -> @isprogram p nt) ->
(apply_bterm bt lnt = apply_bterm bt (lnt++lnta)).
Proof.
intros ? ? ? Hisp Hnt Hnta. destruct bt as [lv nt].
unfold apply_bterm. simpl.
assert(length lv <= length lnt \/ length lnt < length lv ) as Hdi by omega.
destruct Hdi. rw <- combine_app_eq; auto.
rw combine_app_app; auto; try omega.
rw <- @simple_lsubst_app.
unfold apply_bterm in Hisp.
apply lsubst_trivial2 with
(sub:= (combine (skipn (length lnt) lv) (firstn (length lv - length lnt) lnta)))
in Hisp; auto.
- intros ? ? Hin. apply in_combine in Hin; exrepnd.
apply in_firstn in Hin; try omega; auto.
- intros ? ? Hin. apply in_combine in Hin. sp.
- intros ? ? Hin. apply in_combine in Hin. exrepnd.
apply in_firstn in Hin; try omega; auto.
Qed.
Lemma lsubst_aux_nt_wf {p} :
forall t sub,
nt_wf (@lsubst_aux p t sub)
-> nt_wf t.
Proof.
nterm_ind t as [|f ind|o lbt ind] Case; simpl; introv w; auto.
Case "oterm".
inversion w as [|f|op lnt k e]; subst; auto.
constructor.
- introv i; destruct l.
generalize (k (lsubst_bterm_aux (bterm l n) sub)); intro j.
dest_imp j hyp.
rw in_map_iff.
exists (bterm l n); sp.
simpl in j.
inversion j; subst.
apply ind with (sub := (sub_filter sub l)) in i; auto.
- rw <- e; rw map_map; unfold compose.
rewrite eq_maps with (g := fun x : BTerm => num_bvars (lsubst_bterm_aux x sub)); sp.
destruct x.
unfold num_bvars. simpl;refl.
Qed.
(*
Lemma isprog_lcsubst_pi2 :
forall t sub1 sub2 w1 w2 c1 c2,
isprog_lcsubst (csubst t sub1) sub2 w1 c1
= isprog_lcsubst t (sub1 ++ sub2) w2 c2.
Proof.
Qed.
*)
(*
Lemma isprog_lcsubst_pi2 :
forall t1 t2 : NTerm,
forall sub,
forall w1 : wf_term t1,
forall w2 : wf_term t2,
forall c1 : cover_vars t1 sub,
forall c2 : cover_vars t2 sub,
forall e : t1 = t2,
match e with eq_refl => isprog_lcsubst t1 sub w1 c1 end
= isprog_lcsubst t2 sub w2 c2.
Proof.
sp.
apply isprog_proof_irrelevance.
Qed.
*)
Lemma lsubst_aux_snoc_dup {p} :
forall t sub v u,
(forall v t, LIn (v, t) sub -> isprogram t)
-> @isprogram p u
-> LIn v (dom_sub sub)
-> lsubst_aux t (snoc sub (v, u)) = lsubst_aux t sub.
Proof.
nterm_ind t Case; simpl; intros; auto.
- Case "vterm".
rw @sub_find_snoc.
remember (sub_find sub n); destruct o; symmetry in Heqo; sp.
applydup @sub_find_none2 in Heqo.
remember (beq_var v n); destruct b; sp.
apply beq_var_true in Heqb; subst; sp.
- Case "oterm".
f_equal.
apply eq_maps; sp.
destruct x; simpl.
repeat (rw bvar_renamings_subst_isprogram; auto); simpl;
try (complete (sp; allrw in_snoc; sp; allapply pair_inj; sp; subst; sp; apply_in_hyp p; sp)).
rw @sub_filter_snoc.
remember (memvar v l); symmetry in Heqb; destruct b; sp.
rewrite H with (lv := l); sp.
allrw @in_sub_filter; sp.
apply_in_hyp pp; sp.
rw <- @dom_sub_sub_filter.
rw in_remove_nvars; sp.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb; sp.
Qed.
Lemma lsubst_snoc_dup {p} :
forall t sub v u,
(forall v t, LIn (v, t) sub -> isprogram t)
-> @isprogram p u
-> LIn v (dom_sub sub)
-> lsubst t (snoc sub (v, u)) = lsubst t sub.
Proof.
introv k isp i. assert(prog_sub (snoc sub (v,u))). introv Hin.
apply in_snoc in Hin. dorn Hin; auto.
- apply k in Hin. sp.
- inverts Hin. subst. trivial.
- change_to_lsubst_aux4.
apply lsubst_aux_snoc_dup ;sp.
Qed.
Lemma csubst_snoc_dup {p} :
forall t sub v u,
LIn v (@dom_csub p sub)
-> csubst t (snoc sub (v,u)) = csubst t sub.
Proof.
intros.
unfold csubst; simpl.
rw @csub2sub_snoc.
apply lsubst_snoc_dup; sp.
allapply @in_csub2sub; sp.
destruct u; allsimpl.
rw @dom_csub_eq; sp.
Qed.
Lemma lsubst_aux_swap {p} :
forall t sub v u,
(forall v t, LIn (v, t) sub -> @isprogram p t)
-> isprogram u
-> ! LIn v (dom_sub sub)
-> lsubst_aux t ((v, u) :: sub) = lsubst_aux t (snoc sub (v, u)).
Proof.
nterm_ind t Case; simpl; intros; auto.
- Case "vterm".
rw @sub_find_snoc.
remember (sub_find sub n); destruct o; symmetry in Heqo; sp.
remember (beq_var v n); destruct b; sp.
apply beq_var_true in Heqb; subst; sp.
apply sub_find_some in Heqo.
apply in_dom_sub in Heqo; sp.
- Case "oterm".
f_equal.
apply eq_maps; sp.
destruct x; simpl.
repeat (rw bvar_renamings_subst_isprogram; auto); simpl;
try (complete (sp; allrw in_snoc; sp; allapply pair_inj; sp; subst; sp; apply_in_hyp p; sp)).
rw @sub_filter_snoc.
remember (memvar v l); symmetry in Heqb; destruct b; sp; simpl.
rewrite H with (lv := l); sp.
allrw @in_sub_filter; sp.
apply_in_hyp pp; sp.
allrw <- @dom_sub_sub_filter.
allrw in_remove_nvars; sp.
Qed.
Lemma lsubst_swap {p} :
forall t sub v u,
(forall v t, LIn (v, t) sub -> @isprogram p t)
-> isprogram u
-> ! LIn v (dom_sub sub)
-> lsubst t ((v, u) :: sub) = lsubst t (snoc sub (v, u)).
Proof.
introv k isp ni. assert(prog_sub (snoc sub (v,u))).
- introv Hin.
apply in_snoc in Hin. dorn Hin; auto.
+ apply k in Hin. sp.
+ inverts Hin. subst. trivial.
- assert(prog_sub (cons (v,u) sub)). introv Hin.
dorn Hin; auto.
+ inverts Hin. subst. trivial.
+ apply k in Hin. sp.
+ change_to_lsubst_aux4.
apply lsubst_aux_swap ;sp.
Qed.
Lemma csubst_swap {p} :
forall t sub v u,
! LIn v (@dom_csub p sub)
-> csubst t ((v, u) :: sub) = csubst t (snoc sub (v, u)).
Proof.
intros.
unfold csubst; simpl.
rw @csub2sub_snoc.
apply lsubst_swap; sp.
allapply @in_csub2sub; sp.
destruct u; allsimpl.
allrw @dom_csub_eq; sp.
Qed.
Lemma cover_vars_var {p} :
forall v sub,
LIn v (@dom_csub p sub)
-> cover_vars (mk_var v) sub.
Proof.
sp.
rw @cover_vars_eq; simpl.
rw subvars_eq.
unfold subset; simpl; sp; subst; auto.
Qed.
Lemma lsubst_aux_shift {p} :
forall t sub1 sub2 sub3,
(forall v t, LIn (v, t) (sub1 ++ sub2 ++ sub3) -> @isprogram p t)
-> disjoint (dom_sub sub1) (dom_sub sub2)
-> lsubst_aux t (sub1 ++ sub2 ++ sub3) = lsubst_aux t (sub2 ++ sub1 ++ sub3).
Proof.
nterm_ind t as [|f ind|o lbt ind] Case; simpl; introv k d; auto.
- Case "vterm".
repeat (rw @sub_find_app).
remember (sub_find sub1 n); destruct o; symmetry in Heqo; auto.
apply sub_find_some in Heqo.
unfold disjoint in d.
apply in_dom_sub in Heqo.
apply d in Heqo.
rw <- @sub_find_none_iff in Heqo; rw Heqo; sp.
- Case "oterm".
f_equal.
apply eq_maps; introv i.
destruct x; simpl.
repeat (rw bvar_renamings_subst_isprogram; auto); simpl.
repeat (rw @sub_filter_app).
rewrite ind with (lv := l); sp.
allrw in_app_iff; sp; allrw @in_sub_filter; sp;
apply k with (v := v); rw in_app_iff; sp;
rw in_app_iff; sp.
repeat (rw <- @dom_sub_sub_filter).
unfold disjoint; introv i1 i2.
allrw in_remove_nvars; exrepnd.
unfold disjoint in d; apply_in_hyp pp; sp.
Qed.
Lemma lsubst_shift {p} :
forall t sub1 sub2 sub3,
(forall v t, LIn (v, t) (sub1 ++ sub2 ++ sub3) -> @isprogram p t)
-> disjoint (dom_sub sub1) (dom_sub sub2)
-> lsubst t (sub1 ++ sub2 ++ sub3) = lsubst t (sub2 ++ sub1 ++ sub3).
Proof.
introv Hpr. assert (prog_sub (sub2 ++ sub1 ++ sub3)).
apply sub_app_sat_if in Hpr. repnd.
apply sub_app_sat_if in Hpr. repnd.
apply sub_app_sat;sp.
apply sub_app_sat;sp.
intros.
change_to_lsubst_aux4.
apply lsubst_aux_shift;sp.
Qed.
Lemma csubst_shift {p} :
forall t sub1 sub2 sub3,
disjoint (dom_csub sub1) (@dom_csub p sub2)
-> csubst t (sub1 ++ sub2 ++ sub3) = csubst t (sub2 ++ sub1 ++ sub3).
Proof.
unfold csubst; sp.
repeat (rw <- @csub2sub_app).
apply lsubst_shift; sp; allrw in_app_iff; sp;
try (allapply @in_csub2sub; sp).
repeat (rw @dom_csub_eq); sp.
Qed.
Lemma cover_vars_shift {p} :
forall t sub1 sub2 sub3,
@cover_vars p t (sub1 ++ sub2 ++ sub3)
-> cover_vars t (sub2 ++ sub1 ++ sub3).
Proof.
sp; allrw @cover_vars_eq; sp; allrw subvars_eq.
unfold subset; unfold subset in H; sp.
apply_in_hyp pp.
allrw @dom_csub_app; allrw in_app_iff; sp.
Qed.
Lemma lsubstc_shift {pp} :
forall t sub1 sub2 sub3 w p,
forall d : disjoint (dom_csub sub1) (@dom_csub pp sub2),
lsubstc t w (sub1 ++ sub2 ++ sub3) p
= lsubstc t w (sub2 ++ sub1 ++ sub3) (cover_vars_shift t sub1 sub2 sub3 p).
Proof.
sp; unfold lsubstc.
apply cterm_eq; simpl.
apply csubst_shift; auto.
Qed.
Lemma lsubstc_shift_ex {pp} :
forall t sub1 sub2 sub3 w p,
forall d : disjoint (@dom_csub pp sub1) (dom_csub sub2),
{p' : cover_vars t (sub2 ++ sub1 ++ sub3)
& lsubstc t w (sub1 ++ sub2 ++ sub3) p
= lsubstc t w (sub2 ++ sub1 ++ sub3) p'}.
Proof.
sp.
exists (cover_vars_shift t sub1 sub2 sub3 p).
apply lsubstc_shift; sp.
Qed.
Fixpoint lsubst_sub {p} (sub1 sub2 : @Substitution p) : Substitution :=
match sub1 with
| nil => nil
| (v,t) :: sub => (v,lsubst t sub2) :: lsubst_sub sub sub2
end.
Lemma lsubst_sub_cons {p} :
forall v t sub1 sub2,
@lsubst_sub p ((v, t) :: sub1) sub2
= (v, lsubst t sub2) :: lsubst_sub sub1 sub2.
Proof.
sp.
Qed.
Lemma lsubst_sub_nil {p} :
forall sub, @lsubst_sub p [] sub = [].
Proof.
sp.
Qed.
Hint Rewrite @lsubst_sub_nil.
Lemma sub_find_lsubst_sub_if_some {p} :
forall v t sub1 sub2,
@sub_find p sub1 v = Some t
-> sub_find (lsubst_sub sub1 sub2) v = Some (lsubst t sub2).
Proof.
induction sub1; simpl; sp; allsimpl.
remember (beq_var a0 v); destruct b.
inversion H; subst; sp.
apply IHsub1 with (sub2 := sub2) in H; sp.
Qed.
Lemma sub_find_lsubst_sub_if_none {p} :
forall v sub1 sub2,
@sub_find p sub1 v = None
-> sub_find (lsubst_sub sub1 sub2) v = None.
Proof.
induction sub1; simpl; sp; allsimpl.
remember (beq_var a0 v); destruct b; sp.
Qed.
Lemma in_lsubst_sub_implies {p} :
forall v t sub1 sub2,
LIn (v, t) (@lsubst_sub p sub1 sub2)
-> {u : NTerm $ (LIn (v, u) sub1 # t = lsubst u sub2)}.
Proof.
induction sub1; simpl; sp; allsimpl; sp; inj.
exists a; sp.
apply_in_hyp pp; sp; subst.
exists u; sp.
Qed.
Lemma sub_filter_lsubst_sub {p} :
forall sub1 sub2 l,
sub_filter (@lsubst_sub p sub1 sub2) l
= lsubst_sub (sub_filter sub1 l) sub2.
Proof.
induction sub1; simpl; sp; allsimpl.
destruct (memvar a0 l); sp; simpl.
rw IHsub1; sp.
Qed.
Theorem disjoint_bv_sub_ot {p} :
forall o lbt lv nt sub, disjoint_bv_sub (@oterm p o lbt) sub
-> LIn (bterm lv nt) lbt
-> disjoint_bv_sub nt (sub_filter sub lv).
Proof. unfold disjoint_bv_sub. introv Hdis Hin. introv Hins.
apply in_sub_filter in Hins. repnd. apply Hdis in Hins0. simpl in Hins0.
eapply disjoint_lbt_bt2 in Hins0. Focus 2. eauto. repnd; auto.
Qed.
(*
Lemma lsubst_aux_sub_filter2 {p} :
forall t sub l,
@disjoint_bv_sub p t sub
-> disjoint (free_vars t) l
-> lsubst_aux t (sub_filter sub l) = lsubst_aux t sub.
Proof.
nterm_ind1 t as [v| o lbt Hind] Case; simpl; introv Hbv Hd.
- Case "vterm".
remember (sub_find (sub_filter sub l) v); symmetry in Heqo; destruct o.
rw @sub_find_sub_filter_some in Heqo; sp.
allrw; sp.
rw @sub_find_sub_filter_none in Heqo; sp.
allrw; sp.
allrw disjoint_singleton_l; sp.
- Case "oterm".
f_equal.
apply eq_maps. intros bt Hin.
destruct bt as [lv nt]; simpl.
pose proof (sub_eta_length (sub_filter sub l)) as X99X.
f_equal. rw @sub_filter_swap.
rw <- @sub_filter_app_r.
rw @sub_filter_app_as_remove_nvars.
rw @sub_filter_app_r.
rewrite Hind with (lv := lv); sp; [
eapply disjoint_bv_sub_ot in Hbv;eauto |].
eapply disjoint_flat_map_l in Hd;eauto.
allsimpl. apply disjoint_remove_nvars_l in Hd.
sp.
Qed.
*)
Lemma lsubst_aux_sub_filter3 {p} :
forall t sub vs,
disjoint (remove_nvars vs (@dom_csub p sub)) (free_vars t)
-> lsubst_aux t (sub_filter (csub2sub sub) vs) = t.
Proof.
introv disj.
apply lsubst_aux_trivial; introv i.
apply in_sub_filter in i; repnd.
dands; try (complete (apply in_csub2sub in i0; sp)).
introv j.
generalize (disj v); intro imp.
dest_imp imp hyp.
rw in_remove_nvars; sp.
rw <- @dom_csub_eq.
apply in_dom_sub in i0; sp.
Qed.
Lemma lsubst_sub_filter2 {p}:
forall t sub l,
@disjoint_bv_sub p t sub
-> disjoint (free_vars t) l
-> lsubst t (sub_filter sub l) = lsubst t sub.
Proof.
intros. change_to_lsubst_aux4.
apply lsubst_aux_sub_filter;try(sp;fail);
try(rw @disjoint_sub_as_flat_map;disjoint_reasoning).
apply @disjoint_sym. rw <- @disjoint_sub_as_flat_map.
apply sub_filter_sat.
rw @disjoint_sub_as_flat_map. disjoint_reasoning.
Qed.
Ltac disjoint_flat2 := allunfold disjoint_bv_sub; allunfold sub_range_sat; allsimpl;
match goal with
|[ H: (LIn (_,?t) ?sub), H2 : (disjoint (flat_map ?f (range ?sub)) ?l) |- disjoint (?f ?t) ?l ] =>
exact ((snd (disjoint_sub_as_flat_map _ _ _) H2 _ _ H))
|[ H: (LIn (_,?t) ?sub), H2 : (disjoint ?l (flat_map ?f (range ?sub))) |- disjoint (?f ?t) ?l ] =>
exact ((snd (disjoint_sub_as_flat_map _ _ _)
(disjoint_sym_impl _ _ _ H2) _ _ H))
| [ H:( forall _ _, LIn (_, _) _
-> disjoint (free_vars _) _) |- _ ] =>
apply disjoint_sub_as_flat_map in H
| [ |- ( forall _ _, LIn (_, _) _
-> disjoint (free_vars _) _) ] =>
apply disjoint_sub_as_flat_map
end.
Lemma lsubst_sub_sub_filter_disjoint2 {p} :
forall sub1 sub2 l,
disjoint (flat_map bound_vars (range sub1))
(flat_map free_vars (@range p sub2))
-> disjoint l (flat_map free_vars (range sub1))
-> lsubst_sub (sub_filter sub1 l) (sub_filter sub2 l)
= lsubst_sub (sub_filter sub1 l) sub2.
Proof.
induction sub1 as [|(v,t) sub Hind]; introv H1dis H2dis; allsimpl;sp.
rw memvar_dmemvar.
cases_ifn Hm; allsimpl; rw Hind; disjoint_reasoningv;[].
f_equal; f_equal;[].
rw @lsubst_sub_filter2;sp; disjoint_reasoningv;[].
disjoint_flat. disjoint_reasoningv.
Qed.
Lemma lsubst_sub_sub_filter_disjoint {p} :
forall sub1 sub2 l,
(forall v u, LIn (v, u) sub2 -> @isprogram p u)
-> (forall v u, LIn (v, u) sub1 -> disjoint (free_vars u) l)
-> lsubst_sub (sub_filter sub1 l) (sub_filter sub2 l)
= lsubst_sub (sub_filter sub1 l) sub2.
Proof.
intros. apply lsubst_sub_sub_filter_disjoint2;sp;
disjoint_flat;
change_to_lsubst_aux4;
disjoint_reasoningv.
Qed.
Lemma sub_mk_renames_disjoint {p} :
forall l1 l2,
disjoint l1 l2
-> @sub_mk_renames p l1 l2 = (l1, []).
Proof.
induction l1; simpl; sp.
allrw disjoint_cons_l; sp.
apply_in_hyp pp.
allrw.
remember (memvar a l2); symmetry in Heqb; destruct b; sp.
allrw fold_assert.
rw assert_memvar in Heqb; sp.
Qed.
Lemma sub_mk_renames2_disjoint {p} :
forall l1 l2 lva,
disjoint l1 l2
-> @sub_mk_renames2 p l1 l2 lva = (l1, []).
Proof.
induction l1; simpl; try (complete sp); introv d.
allrw disjoint_cons_l; exrepnd.
apply IHl1 with (lva:=lva) in d0.
allrw; boolvar; sp.
Qed.
(** This is similar to bvar_renamings_subst_isprogram (same conclusion)
* but it has a diffrent hypothesis. *)
(** not needed anymore *)
Lemma bvar_renamings_subst_disjoint_bound_vars {p} :
forall l sub nt,
(forall v u, LIn (v, u) sub -> disjoint (@free_vars p u) l)
-> bvar_renamings_subst l nt sub
= (l, [], sub_filter sub l).
Proof.
unfold bvar_renamings_subst; introv k.
rw @sub_mk_renames2_eta; simpl.
remember (sub_free_vars (sub_filter sub l)).
assert (disjoint l0 l)
as d
by (subst; unfold disjoint; sp;
allrw @in_sub_free_vars_iff; sp;
allrw @in_sub_filter; sp;
apply_in_hyp q;
unfold disjoint in q;
discover; sp).
rw @sub_mk_renames2_disjoint; sp.
apply disjoint_sym; sp.
Qed.
Ltac dsub_find sn :=
match goal with
| [ |- context[sub_find ?s ?v] ] =>
let sns := fresh sn "s" in
remember (sub_find s v) as sn;
destruct sn as [sns |]
| [ H: context[sub_find ?s ?v] |- _ ] =>
let sns := fresh sn "s" in
remember (sub_find s v) as sn;
destruct sn as [sns |]
end.
Lemma lsubst_aux_app {p} :
forall t sub1 sub2,
disjoint (flat_map bound_vars (range sub1)) (flat_map free_vars (@range p sub2))
-> disjoint_bv_sub t sub1
-> disjoint_bv_sub t sub2
-> lsubst_aux (lsubst_aux t sub1) sub2 = lsubst_aux t (lsubst_sub sub1 sub2 ++ sub2).
Proof.
nterm_ind1 t as [v|f ind|o lbt Hind] Case; simpl; introns Hss; auto.
- Case "vterm".
rw @sub_find_app.
dsub_find s1v; symmetry in Heqs1v.
+ applydup @sub_find_some in Heqs1v.
apply @sub_find_lsubst_sub_if_some with (sub2 := sub2) in Heqs1v.
rw Heqs1v; sp. revert Heqs1v. change_to_lsubst_aux4; sp.
disjoint_flat.
+ apply @sub_find_lsubst_sub_if_none with (sub2 := sub2) in Heqs1v.
rw Heqs1v ; simpl; sp.
- Case "oterm".
f_equal. rw map_map.
apply eq_maps. intros bt Hin.
destruct bt as [lv nt]. unfold compose. simpl.
f_equal.
rw @sub_filter_app.
rw @sub_filter_lsubst_sub.
assert (lsubst_sub (sub_filter sub1 lv) (sub_filter sub2 lv)
= lsubst_sub (sub_filter sub1 lv) sub2) as eq.
+ apply lsubst_sub_sub_filter_disjoint2; sp.
disjoint_flat. disjoint_reasoning.
+ rw <- eq. sp. rewrite Hind with (lv := lv); sp;
disjoint_flat;
disjoint_flat_sf; disjoint_reasoningv.
Qed.
Lemma simple_lsubst_aux_lsubst_aux {p} :
forall t sub1 sub2,
(forall v u, LIn (v, u) sub1 -> disjoint (free_vars u) (bound_vars t))
-> (forall v u, LIn (v, u) sub2 -> @isprogram p u)
-> lsubst_aux (lsubst_aux t sub1) sub2
= lsubst_aux t ((lsubst_sub sub1 sub2) ++ sub2).
Proof.
introv H1 H2. apply lsubst_aux_app; disjoint_flat; disjoint_reasoningv;
change_to_lsubst_aux4; disjoint_reasoningv.
Qed.
Lemma disjoint_bv_sub_lsubst_sub {p} :
forall t sub1 sub2,
disjoint_bv_sub t sub1
-> @prog_sub p sub2
-> disjoint_bv_sub t (lsubst_sub sub1 sub2).
Proof.
introv H1b H2b.
unfold sub_range_sat. introv Hin. apply in_lsubst_sub_implies in Hin.
exrepnd.
subst. introv Hin.
rw @isprogram_lsubst2 in Hin;[|sp;fail]. apply in_remove_nvars in Hin. repnd.
apply H1b in Hin1. apply Hin1 in Hin0. sp.
Qed.
Lemma simple_lsubst_lsubst {p} :
forall t sub1 sub2,
(forall v u, LIn (v, u) sub1 -> disjoint (free_vars u) (bound_vars t))
-> (forall v u, LIn (v, u) sub2 -> @isprogram p u)
-> lsubst (lsubst t sub1) sub2
= lsubst t ((lsubst_sub sub1 sub2) ++ sub2).
Proof.
introv Hd Hp.
assert (disjoint_bv_sub t (lsubst_sub sub1 sub2 ++ sub2)).
apply sub_app_sat;sp.
- apply disjoint_bv_sub_lsubst_sub;sp.
- apply prog_sub_disjoint_bv_sub;sp.
- change_to_lsubst_aux4. apply simple_lsubst_aux_lsubst_aux; [|sp].
apply disjoint_sub_as_flat_map;sp. disjoint_reasoning.
Qed.
Lemma lsubstc_eq_if_csubst {p} :
forall t1 t2 w1 w2 s1 s2 p1 p2,
csubst t1 s1 = @csubst p t2 s2
-> lsubstc t1 w1 s1 p1 = lsubstc t2 w2 s2 p2.
Proof.
unfold lsubstc; sp.
apply cterm_eq; simpl; auto.
Qed.
Lemma csubst_eq_if_lsubst {p} :
forall t1 t2 s1 s2,
lsubst t1 (csub2sub s1) = lsubst t2 (@csub2sub p s2)
-> csubst t1 s1 = csubst t2 s2.
Proof.
unfold csubst; sp.
Qed.
(*
Lemma simple_csubst_lsubst :
forall t sub1 sub2,
(forall v u, LIn (v, u) sub1 -> disjoint (free_vars u) (bound_vars t))
-> csubst (lsubst t sub1) sub2
= csubst t ((lsubst_sub sub1 sub2) ++ sub2).
Proof.
*)
(* keeps the variables from vars *)
Fixpoint sub_keep {p} (sub : @Substitution p) (vars : list NVar) : Substitution :=
match sub with
| nil => nil
| (v, t) :: xs =>
if memvar v vars
then (v, t) :: sub_keep xs vars
else sub_keep xs vars
end.
Lemma sub_find_sub_keep_some {p} :
forall sub vs v t,
sub_find (@sub_keep p sub vs) v = Some t
<=> sub_find sub v = Some t
# LIn v vs.
Proof.
induction sub; simpl; sp.
split; sp.
boolvar; simpl; allrw; boolvar; sp; split; sp.
Qed.
Lemma sub_find_sub_keep_none {p} :
forall sub vs v,
sub_find (@sub_keep p sub vs) v = None
<=> sub_find sub v = None
[+] ! LIn v vs.
Proof.
induction sub; simpl; sp.
boolvar; simpl; allrw; boolvar; sp; split; sp.
Qed.
Lemma sub_filter_sub_keep {p} :
forall sub vs1 vs2,
sub_filter (@sub_keep p sub vs1) vs2
= sub_keep (sub_filter sub vs2) vs1.
Proof.
induction sub; simpl; sp.
remember (memvar a0 vs1); remember (memvar a0 vs2).
symmetry in Heqb; symmetry in Heqb0.
destruct b; destruct b0; allsimpl;
try (rw Heqb); try (rw Heqb0); sp.
rw IHsub; sp.
Qed.
Theorem in_sub_keep {p} :
forall (sub : @Substitution p) (v : NVar) (t : NTerm) (vars : list NVar),
LIn (v, t) (sub_keep sub vars) <=> LIn (v, t) sub # LIn v vars.
Proof.
induction sub. simpl; split; sp.
simpl. destruct a as [v t]. introv.
cases_if as Hmv;
(applydup assert_memvar in Hmv || applydup assert_memvar_false in Hmv) ; simpl;
split; introv Hor.
- invertsn Hor. invertsn Hor; split; auto. apply IHsub in Hor; repnd; auto.
- inverts Hor as Hor Hin. invertsn Hor. invertsn Hor. left; reflexivity. right. apply IHsub; auto.
- apply IHsub in Hor. repnd. split; trivial. right; trivial.
- inverts Hor as Hor Hin. invertsn Hor. invertsn Hor. destruct Hmv0; trivial. apply IHsub; split; trivial.
Qed.
(* Theorem memvar2 (v:NVar) (vs:list NVar) : {LIn v vs} + {! LIn v vs} := *)
Theorem sub_keep_nest {p} :
forall sub vs1 vs2,
(forall v, LIn v vs2 -> LIn v vs1 [+] ! LIn v (@dom_sub p sub))
-> sub_keep (sub_keep sub vs1) vs2 =sub_keep sub vs2.
Proof.
induction sub as [| (hv,ht) sub]; introv Hin; [reflexivity | allsimpl].
simpl. cases_if as Hmv1; cases_if as Hmv2; simpl; try rw Hmv1; try rw Hmv2; sp;
(applydup assert_memvar in Hmv1 || applydup assert_memvar_false in Hmv1);
(applydup assert_memvar in Hmv2 || applydup assert_memvar_false in Hmv2); sp;
[f_equal | trivial | trivial | trivial] ;
try(apply IHsub; introv Hinv; applydup Hin in Hinv; invertsn Hinv0;
[left ;trivial | right; apply not_over_or in Hinv0; repnd; trivial]).
apply Hin in Hmv3. invertsn Hmv3. apply Hmv0 in Hmv3; sp.
apply not_over_or in Hmv3. repnd. destruct Hmv4. reflexivity.
Qed.
Lemma simple_lsubst_aux_trim {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> disjoint (@free_vars p u) (bound_vars t))
-> lsubst_aux t sub = lsubst_aux t (sub_keep sub (free_vars t)).
Proof.
nterm_ind t Case; introv Hdis; auto.
Case "vterm". simpl.
cases (sub_find sub n) as Heqs.
assert (sub_find (sub_keep sub [n]) n = Some n0) as Heqk.
apply sub_find_sub_keep_some; split; simpl; auto.
rw Heqk; reflexivity.
assert (sub_find (sub_keep sub [n]) n = None) as Heqk.
apply sub_find_sub_keep_none. left; trivial.
rw Heqk; reflexivity.
Case "oterm". simpl. f_equal.
apply eq_maps. intros bt Hin.
destruct bt as [lv nt].
simpl.
repeat (rw bvar_renamings_subst_disjoint_bound_vars).
repeat (rw app_nil_l); simpl.
f_equal.
rw @sub_filter_sub_keep.
symmetry.
rewrite H with (lv := lv); eauto. Focus 2.
introv Hink. rw @in_sub_keep in Hink. repnd. apply in_sub_filter in Hink0. repnd.
apply Hdis in Hink1. simpl in Hink1. apply disjoint_sym in Hink1;rw disjoint_flat_map_l in Hink1.
apply Hink1 in Hin. simpl in Hin. rw disjoint_app_l in Hin. repnd; apply disjoint_sym. trivial.
assert( (sub_keep (sub_keep (sub_filter sub lv)
(flat_map free_vars_bterm lbt)) (free_vars nt)) =
sub_keep (sub_filter sub lv) (free_vars nt)) as Hskeq.
+ apply sub_keep_nest. introv Hinf. destruct (in_nvar_list_dec v lv).
* right. rw <- @dom_sub_sub_filter. intro HC. apply in_remove_nvars in HC. sp.
* left. apply lin_flat_map. eexists; split; eauto. simpl. apply in_remove_nvars; split; trivial.
+ rw Hskeq.
symmetry. eapply H; eauto.
introv Hinf. apply in_sub_filter in Hinf. repnd. apply Hdis in Hinf0.
simpl in Hinf0. apply disjoint_sym in Hinf0. rw disjoint_flat_map_l in Hinf0.
apply Hinf0 in Hin. simpl in Hin. rw disjoint_app_l in Hin. repnd; apply disjoint_sym. trivial.
Qed.
Lemma sub_keep_sat {p} : forall P sub lv,
@sub_range_sat p sub P
-> sub_range_sat (sub_keep sub lv) P.
Proof. introv Hall hsub. apply in_sub_keep in hsub. repnd.
apply Hall in hsub0; auto.
Qed.
Lemma simple_lsubst_trim {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> disjoint (@free_vars p u) (bound_vars t))
-> lsubst t sub = lsubst t (sub_keep sub (free_vars t)).
Proof.
introv Hd. duplicate Hd as Hdd.
apply sub_keep_sat with (lv:=(free_vars t))in Hd.
change_to_lsubst_aux4.
apply simple_lsubst_aux_trim;try(sp;fail);
try(apply disjoint_sub_as_flat_map;disjoint_reasoning).
Qed.
Definition disjoint_bv2_sub {p} (nt1 nt2 : @NTerm p) (sub: @Substitution p) :=
forall (v : NVar) (t : NTerm),
LIn (v, t) sub
-> disjoint (free_vars t) (bound_vars nt1 ++ bound_vars nt2).
Theorem wf_sub_filter {p} :
forall lv sub, @wf_sub p sub -> wf_sub (sub_filter sub lv).
Proof.
unfold wf_sub; introv s.
introv Hin.
allrw @in_sub_filter; exrepnd.
apply s in Hin0; sp.
Qed.
Theorem wf_sub_keep {p} : forall lv sub, @wf_sub p sub -> wf_sub (sub_keep sub lv).
Proof.
unfold wf_sub; introv s.
introv Hin.
allrw @in_sub_keep; exrepnd.
apply s in Hin0; sp.
Qed.
(** TODO : use the stronger lemma free_vars_lsubst_aux2 for a shorter
and more maintainable proof *)
Theorem free_vars_lsubst_aux {p} :
forall nt sub,
@disjoint_bv_sub p nt sub
-> forall v,
LIn v (free_vars (lsubst_aux nt sub))
-> LIn v (free_vars nt)
[+] {v' : NVar
$ {t : NTerm
$ LIn (v',t) sub # LIn v' (free_vars nt) # LIn v (free_vars t)}}.
Proof. nterm_ind1 nt as [vn| f ind | o lbt Hind] Case; introv Hdis Hin; auto.
Case "vterm". induction sub as [| (vs,ts) sub].
- rw @lsubst_aux_nil in Hin. left;auto.
- destruct (eq_var_dec vn vs) as [? | Hneq];
subst;simpl in Hin;
((rw <- beq_var_refl in Hin;auto)
|| (rw not_eq_beq_var_false in Hin;auto)).
+ right. exists vs ts. sp; auto.
+ cases (sub_find sub vn) as Hf.
* applydup @sub_find_some in Hf.
right; exists vn n; split; auto. right;auto. simpl. split; auto.
* left; auto.
- Case "oterm".
simpl in Hin. rw lin_flat_map in Hin.
destruct Hin as [bt' Hin]. repnd. apply in_map_iff in Hin0.
destruct Hin0 as [bt Hin0]. repnd. subst. destruct bt as [lv nt].
simpl in Hin.
simpl in Hin. rw in_remove_nvars in Hin. repnd.
apply Hind with (lv:=lv) in Hin0; auto.
destruct Hin0 as [Hl | Hr].
+ left. simpl. apply lin_flat_map. eexists; split; eauto. simpl.
apply in_remove_nvars. split; auto.
+ right. parallel vs Hr. parallel ts Hr. repnd. sp;auto.
* rw @in_sub_filter in Hr0. repnd; auto.
* simpl. apply lin_flat_map. eexists; split; eauto. simpl.
apply in_remove_nvars. split; auto. rw @in_sub_filter in Hr0.
repnd; auto.
+ eapply disjoint_bv_sub_ot in Hdis; eauto.
Qed.
Theorem free_vars_lsubst {p} :
forall nt sub,
@disjoint_bv_sub p nt sub
-> forall v,
LIn v (free_vars (lsubst nt sub))
-> LIn v (free_vars nt)
[+] {v' : NVar
$ {t : NTerm
$ LIn (v',t) sub # LIn v' (free_vars nt) # LIn v (free_vars t)}}.
Proof.
introns XX. change_to_lsubst_aux4.
apply free_vars_lsubst_aux;try(sp;fail).
try(rw @disjoint_sub_as_flat_map;disjoint_reasoning).
revert XX0. change_to_lsubst_aux4.
sp.
Qed.
Theorem free_vars_lsubst_closed {p} : forall nt sub, @wf_sub p sub
-> disjoint_bv_sub nt sub
-> prog_sub sub
-> subvars (free_vars (lsubst nt sub)) (free_vars nt).
Proof.
introv Hwf Hdis Hcl. apply subvars_prop. intros v Hin.
apply @free_vars_lsubst with (v:=v )in Hdis; auto.
dorn Hdis; auto. exrepnd. apply Hcl in Hdis0.
inverts Hdis0 as Hpr ?. rw Hpr in Hdis1. inverts Hdis1.
Qed.
Lemma simple_lsubst_trim2 {p} :
forall t sub lv,
@disjoint_bv_sub p t sub
-> subvars (free_vars t) lv
-> lsubst t sub = lsubst t (sub_keep sub lv).
Proof.
introv Hdis Hsub.
rw @simple_lsubst_trim; auto.
symmetry. rw @simple_lsubst_trim; auto.
rw @sub_keep_nest; try reflexivity.
intros; left. rw subvars_prop in Hsub. auto.
introv Hin. rw @in_sub_keep in Hin. repnd.
apply Hdis in Hin0; auto.
Qed.
Lemma csubst_trivial {p} :
forall t sub,
disjoint (@dom_csub p sub) (free_vars t)
-> csubst t sub = t.
Proof.
sp.
unfold csubst.
apply lsubst_trivial; sp.
allapply @in_csub2sub; sp.
unfold disjoint in H.
apply_in_hyp pp; sp.
rewrite <- dom_csub_eq.
allapply @in_dom_sub; sp.
Qed.
Lemma sub_find_none_if {p} :
forall sub v,
! LIn v (@dom_sub p sub)
-> sub_find sub v = None.
Proof.
intros.
apply sub_find_none_iff; auto.
Qed.
Lemma lsubst_sub_trivial_closed1 {p} :
forall sub1 sub2,
(forall v u, LIn (v, u) sub1 -> isprogram u)
-> (forall v u, LIn (v, u) sub2 -> @isprogram p u)
-> lsubst_sub sub1 sub2 = sub1.
Proof.
induction sub1; simpl; try (complete sp); introv k1 k2.
destruct a as [a0 a]; allsimpl.
rewrite lsubst_trivial; introv.
rewrite IHsub1; sp.
apply k1 with (v := v); sp.
introv i; dands.
apply k2 with (v := v); sp.
generalize (k1 a0 a); intros k.
dest_imp k hyp.
unfold isprogram, closed in k; destruct k as [c w].
rw c; sp.
Qed.
Lemma cover_vars_cvterm1 {p} :
forall v t u,
cover_vars (@get_cvterm p [v] t) [(v, u)].
Proof.
destruct t; sp; simpl.
rw @isprog_vars_eq in i; sp.
Qed.
Lemma substc_eq_lsubstc {p} :
forall u v t,
@substc p u v t
= lsubstc (get_cvterm [v] t)
(wf_cvterm [v] t)
[(v, u)]
(cover_vars_cvterm1 v t u).
Proof.
introv; destruct_cterms; apply cterm_eq; simpl; auto.
Qed.
Lemma lsubst_sub_singleton {p} :
forall x t sub,
@lsubst_sub p [(x, t)] sub = [(x, lsubst t sub)].
Proof.
sp.
Qed.
Lemma csub2sub_cons {p} :
forall x a s,
@csub2sub p ((x,a) :: s) = (x, get_cterm a) :: csub2sub s.
Proof.
sp.
Qed.
Lemma csub_filter_snoc1 {p} :
forall sub v t,
@csub_filter p (snoc sub (v, t)) [v]
= csub_filter sub [v].
Proof.
sp.
induction sub; sp; simpl.
remember (memvar v [v]); destruct b; sp.
symmetry in Heqb.
rw not_of_assert in Heqb.
rw assert_memvar in Heqb; allsimpl.
rw not_over_or in Heqb; sp.
destruct (memvar a0 [v]); sp.
rewrite IHsub; sp.
Qed.
Lemma csub_filter_app_r {p} :
forall sub vs1 vs2,
@csub_filter p sub (vs1 ++ vs2)
= csub_filter (csub_filter sub vs1) vs2.
Proof.
induction sub; simpl; sp.
rewrite memvar_app.
destruct (memvar a0 vs1); simpl.
apply IHsub.
destruct (memvar a0 vs2); simpl.
apply IHsub.
rewrite IHsub; auto.
Qed.
Lemma csub_filter_swap {p} :
forall l1 l2 sub,
csub_filter (@csub_filter p sub l1) l2
= csub_filter (csub_filter sub l2) l1.
Proof.
induction sub; simpl; sp.
remember (memvar a0 l1); destruct b; remember (memvar a0 l2); destruct b; simpl; sp.
rw <- Heqb; sp.
rw <- Heqb0; sp.
rw <- Heqb; sp.
rw <- Heqb0; sp.
rw IHsub; sp.
Qed.
Lemma cover_vars_upto_eq_dom_csub {p} :
forall t s1 s2 vs,
cover_vars_upto t (csub_filter s1 vs) vs
-> dom_csub s1 = @dom_csub p s2
-> cover_vars_upto t (csub_filter s2 vs) vs.
Proof.
unfold cover_vars_upto; sp.
allrw subvars_prop; sp.
apply_in_hyp pp.
allrw in_app_iff; sp.
allrw @dom_csub_csub_filter.
allrw in_remove_nvars; sp.
right; sp.
rewrite <- H0; sp.
Qed.
Lemma sub_find_varsub {p} :
forall lvo lvn vo vnt,
sub_find (var_ren lvo lvn) vo = Some vnt
-> {vn : NVar $ vnt = @vterm p vn # LIn (vo,vn) (combine lvo lvn)}.
Proof.
induction lvo as [| hvo tlvo Hind]; introv Hsome;
[inverts Hsome | ]. applydup @sub_find_some in Hsome.
apply in_combine in Hsome0. repnd. apply in_map_iff in Hsome0.
exrepnd.
destruct lvn.
inverts Hsome0. allsimpl.
dorn Hsome1; subst. eexists; split; eauto. left. f_equal.
rewrite <- beq_var_refl in Hsome. inverts Hsome. reflexivity.
cases_if in Hsome as hbeq. invertsn Hsome.
eexists; split; eauto. left. f_equal. apply beq_var_eq; auto.
pose proof (Hind _ _ _ Hsome) as Hinds. clear Hind.
exrepnd. exists vn. split; auto.
Qed.
Definition isvarc {p} (nt: @NTerm p) := {v : NVar $ nt = vterm v}.
Definition allvars_sub {p} (sub: @Substitution p) :=
sub_range_sat sub isvarc.
Lemma sub_find_sat {p} : forall P sub vo vnt,
@sub_range_sat p sub P
-> sub_find sub vo = Some vnt
-> P vnt.
Proof. introv Hall hsub. apply sub_find_some in hsub.
applydup Hall in hsub. exrepnd. subst. auto.
Qed.
Lemma sub_find_allvars {p} : forall sub vo vnt,
allvars_sub sub
-> sub_find sub vo = Some vnt
-> {vn : NVar $ vnt = @vterm p vn}.
Proof. exact (sub_find_sat isvarc).
Qed.
Lemma sub_filter_allvars {p} : forall sub lv,
@allvars_sub p sub
-> allvars_sub (sub_filter sub lv).
Proof. exact (sub_filter_sat isvarc).
Qed.
Definition get_sub_dom_vars {p} sub (pall: @allvars_sub p sub) : list NVar.
refine (gmap sub (fun (t : NVar * NTerm) (p : LIn t sub) =>
projT1 (pall (fst t) (snd t) _))).
destruct t. simpl. auto.
Defined.
Lemma sub_mk_renames_allvars {p} :
forall lv1 lv2 lv sub,
(lv, sub) = (@sub_mk_renames p lv1 lv2)
-> allvars_sub sub.
Proof. induction lv1 as [|v lv1 Hind]; introv Heq.
allsimpl. invertsn Heq. introv Hin. inverts Hin.
allsimpl. remember (sub_mk_renames lv1 lv2) as recv.
destruct recv. apply Hind in Heqrecv.
cases_if in Heq; inverts Heq; trivial.
introv Hin. allsimpl. dorn Hin. inverts Hin. eexists; eauto.
apply Heqrecv in Hin; trivial.
Qed.
Lemma sub_mk_renames2_allvars {p} : forall lv1 lv2 lv sub lva,
(lv, sub) = (@sub_mk_renames2 p lv1 lv2 lva)
-> allvars_sub sub.
Proof. induction lv1 as [|v lv1 Hind]; introv Heq.
allsimpl. invertsn Heq. introv Hin. inverts Hin.
allsimpl. remember (sub_mk_renames2 lv1 lv2 lva) as recv.
destruct recv. apply Hind in Heqrecv.
cases_if in Heq; inverts Heq; trivial.
introv Hin. allsimpl. dorn Hin. inverts Hin. eexists; eauto.
apply Heqrecv in Hin; trivial.
Qed.
Lemma bvar_renamings_subst_vars {p} : forall lv nt sub sub1 sub2 lv',
@allvars_sub p sub
-> ((lv', sub1), sub2)=(bvar_renamings_subst lv nt sub)
-> (allvars_sub sub1) # (allvars_sub sub2).
Proof. introv Hall Heq. allunfold @bvar_renamings_subst.
remember (sub_mk_renames2 lv (sub_free_vars (sub_filter sub lv))
(dom_sub (sub_filter sub lv) ++ all_vars nt)) as smr.
destruct smr.
invertsn Heq. split; [ |apply sub_filter_allvars; trivial; fail].
apply sub_mk_renames2_allvars in Heqsmr; auto.
Qed.
Lemma lsubst_aux_allvars_preserves_size {p} : forall nt sub,
@allvars_sub p sub
-> size (lsubst_aux nt sub) = size nt.
Proof. nterm_ind1 nt as [v|f ind|o lbt Hind] Case; introv Hall; auto.
Case "vterm". simpl.
cases (sub_find sub v ) as Hsf; try reflexivity.
apply sub_find_allvars in Hsf; trivial. exrepnd. subst; auto.
Case "oterm". simpl. f_equal. f_equal.
rewrite map_map. apply eq_maps. intros bt Hin.
destruct bt as [lv nt]. unfold compose. simpl.
repnd. eapply Hind; eauto. apply sub_filter_sat;sp.
Qed.
Theorem allvars_combine {p} : forall lvo lvn,
allvars_sub (@var_ren p lvo lvn).
Proof. introv Hin. apply in_combine in Hin. repnd.
apply in_map_iff in Hin. exrepnd. exists a; auto.
Qed.
Lemma lsubst_aux_allvars_preserves_size2 {p} : forall nt lvo lvn,
size (lsubst_aux nt (@var_ren p lvo lvn)) = size nt.
Proof.
intros. apply lsubst_aux_allvars_preserves_size.
apply allvars_combine.
Qed.
Theorem not_isvarc_ot {p} : forall op lbt,
(isvarc (@oterm p op lbt)) <=> False.
Proof.
split; try (sp; fail ). introv Hc. exrepnud Hc. inverts Hc0.
Qed.
Theorem isvarc_lsubst_iff {p} : forall sub nt,
@allvars_sub p sub
-> (isvarc (lsubst nt sub) <=> isvarc nt).
Proof.
destruct nt; introv Hal.
- simpl. unfold lsubst. simpl. cases (sub_find sub n) as Hc.
apply sub_find_allvars in Hc; auto. exrepnd. subst.
split ;eexists; eauto. apply t_iff_refl.
- unfold lsubst; simpl; sp.
- unfold lsubst.
cases_if;simpl; allrw @not_isvarc_ot; apply t_iff_refl.
Qed.
Theorem isvarc_lsubst_vterm {p} : forall sub v,
@allvars_sub p sub
-> (isvarc (lsubst (vterm v) sub)).
Proof. intros.
apply isvarc_lsubst_iff; auto.
eexists; eauto.
Qed.
Theorem isvarc_lsubst_implies2 {p} : forall v nt sub,
@allvars_sub p sub
-> vterm v = (lsubst nt sub)
-> isvarc nt.
Proof. intros.
assert (isvarc (lsubst nt sub)) as Hisv by (eexists; eauto).
eapply isvarc_lsubst_iff; eauto.
Qed.
Theorem isvarc_lsubst_ot {p} : forall v lbt sub o,
@allvars_sub p sub
-> oterm o lbt = lsubst (vterm v) sub
-> False.
Proof. introv Hall Heq.
assert (isvarc (@vterm p v)) as Hc by (eexists; eauto).
apply (isvarc_lsubst_iff sub) in Hc; trivial.
rw <- Heq in Hc. rw @not_isvarc_ot in Hc; sp.
Qed.
Lemma covered_app_weak_l {p} :
forall t vs1 vs2,
@covered p t vs1
-> covered t (vs1 ++ vs2).
Proof.
unfold covered; intros.
allrw subvars_prop; sp.
apply_in_hyp pp.
allrw in_app_iff; sp.
Qed.
Lemma covered_app_weak_r {p} :
forall t vs1 vs2,
@covered p t vs2
-> covered t (vs1 ++ vs2).
Proof.
unfold covered; intros.
allrw subvars_prop; sp.
apply_in_hyp pp.
allrw in_app_iff; sp.
Qed.
Lemma sub_find_some_implies_memvar_true {p} :
forall sub v t,
@sub_find p sub v = Some t
-> memvar v (dom_sub sub) = true.
Proof.
sp.
apply sub_find_some in H.
rewrite fold_assert.
rw assert_memvar.
apply in_dom_sub in H; auto.
Qed.
Lemma sub_find_none_implies_memvar_false {p} :
forall sub v,
@sub_find p sub v = None
-> memvar v (dom_sub sub) = false.
Proof.
sp.
apply sub_find_none2 in H.
rw not_of_assert.
rw assert_memvar; auto.
Qed.
Fixpoint sub_keep_first {p} (sub : @Substitution p) (vars : list NVar) : Substitution :=
match sub with
| nil => nil
| (v, t) :: xs =>
if memvar v vars
then (v, t) :: sub_keep_first xs (remove_nvar vars v)
else sub_keep_first xs vars
end.
Lemma sub_keep_first_nil_r {p} :
forall sub,
@sub_keep_first p sub [] = [].
Proof.
induction sub; simpl; sp.
Qed.
Lemma sub_keep_first_singleton_r_some {p} :
forall sub v t,
@sub_find p sub v = Some t
-> sub_keep_first sub [v] = [(v,t)].
Proof.
induction sub; simpl; sp.
rewrite remove_nvar_cons.
rewrite memvar_singleton.
rewrite remove_nvar_nil.
destruct (eq_var_dec a0 v); subst.
allrw <- beq_var_refl.
inversion H; subst.
rewrite sub_keep_first_nil_r; auto.
rw not_eq_beq_var_false; auto.
rw not_eq_beq_var_false in H; auto.
Qed.
Lemma sub_keep_first_singleton_r_none {p} :
forall sub v,
@sub_find p sub v = None
-> sub_keep_first sub [v] = [].
Proof.
induction sub; simpl; sp.
rewrite remove_nvar_cons.
rewrite memvar_singleton.
rewrite remove_nvar_nil.
destruct (eq_var_dec a0 v); subst.
allrw <- beq_var_refl; sp.
rw not_eq_beq_var_false; auto.
rw not_eq_beq_var_false in H; auto.
Qed.
Lemma sub_filter_sub_keep_first_weak_in {p} :
forall sub vs1 vs2 v,
LIn v vs1
-> sub_filter (@sub_keep_first p sub vs2) vs1
= sub_filter (sub_keep_first sub (remove_nvar vs2 v)) vs1.
Proof.
induction sub; simpl; sp.
remember (memvar a0 (remove_nvar vs2 v)); symmetry in Heqb; destruct b;
remember (memvar a0 vs2); symmetry in Heqb0; destruct b; simpl;
remember (memvar a0 vs1); symmetry in Heqb1; destruct b; simpl; sp;
allrw fold_assert;
allrw not_of_assert;
allrw assert_memvar;
allrw in_remove_nvar; sp.
- rewrite remove_nvar_comm; auto.
- rewrite remove_nvar_comm.
symmetry.
rewrite <- IHsub; sp.
- destruct (eq_var_dec a0 v); subst; sp.
provefalse; apply Heqb; sp.
- destruct (eq_var_dec a0 v); subst; sp.
provefalse; apply Heqb; sp.
Qed.
Lemma sub_keep_first_sub_filter {p} :
forall sub vs1 vs2,
sub_keep_first (@sub_filter p sub vs1) vs2
= sub_filter (sub_keep_first sub vs2) vs1.
Proof.
induction sub; simpl; sp.
remember (memvar a0 vs1); symmetry in Heqb; destruct b;
remember (memvar a0 vs2); symmetry in Heqb0; destruct b; sp; simpl; allrw; sp.
rw <- @sub_filter_sub_keep_first_weak_in; sp.
allrw fold_assert; allrw assert_memvar; sp.
Qed.
Lemma in_sub_keep_first {p} :
forall sub v vs t,
LIn (v,t) (@sub_keep_first p sub vs)
<=> (sub_find sub v = Some t # LIn v vs).
Proof.
induction sub; simpl; sp.
split; sp.
destruct (eq_var_dec a0 v); subst;
allrw <- beq_var_refl;
allrw not_eq_beq_var_false; auto;
try (remember (memvar v vs); symmetry in Heqb; destruct b);
try (remember (memvar a0 vs); symmetry in Heqb; destruct b);
allsimpl; rw IHsub; allrw in_remove_nvars; allsimpl; allrw not_over_or;
split; sp; cpx.
rw fold_assert in Heqb; rw assert_memvar in Heqb; auto.
rw not_of_assert in Heqb; rw assert_memvar in Heqb; sp.
rw not_of_assert in Heqb; rw assert_memvar in Heqb; sp.
right; sp.
right; sp.
Qed.
Lemma eqvars_free_vars_disjoint_aux {pp} :
forall t : NTerm,
forall sub : @Substitution pp,
(forall v u, LIn (v, u) sub -> disjoint (free_vars u) (bound_vars t))
-> eqvars (free_vars (lsubst_aux t sub))
(remove_nvars (dom_sub sub) (free_vars t)
++ sub_free_vars (sub_keep_first sub (free_vars t))).
Proof.
nterm_ind t Case; simpl; intros; auto.
- Case "vterm".
remember (sub_find sub n); destruct o; symmetry in Heqo; simpl;
rewrite remove_nvars_cons_r.
+ applydup @sub_find_some_implies_memvar_true in Heqo.
rewrite Heqo0.
rewrite remove_nvars_nil_r; simpl.
applydup @sub_keep_first_singleton_r_some in Heqo.
rewrite Heqo1; simpl.
rewrite app_nil_r; auto.
+ applydup @sub_find_none_implies_memvar_false in Heqo.
rewrite Heqo0.
rewrite remove_nvars_nil_r.
applydup @sub_keep_first_singleton_r_none in Heqo.
rewrite Heqo1; simpl; sp.
- Case "sterm".
allrw remove_nvars_nil_r; allsimpl.
allrw @sub_keep_first_nil_r; simpl; auto.
- Case "oterm".
rewrite remove_nvars_flat_map.
rewrite flat_map_map; unfold compose.
rw eqvars_prop; sp.
sp_iff SCase; intro.
+ SCase "->".
allrw in_app_iff.
allrw lin_flat_map; exrepd.
destruct x0; allsimpl.
allrw in_remove_nvars; sp.
generalize (H n l1 l (sub_filter sub l1)); sp.
dest_imp H1 hyp.
sp.
apply in_sub_filter in X; sp.
apply H0 in X0.
rw disjoint_flat_map_r in X0.
apply X0 in l; allsimpl.
rw disjoint_app_r in l; sp.
rw eqvars_prop in H1.
rw H1 in l2.
allrw in_app_iff; sp.
rw <- @dom_sub_sub_filter in l2.
allrw in_remove_nvars; sp.
left.
exists (bterm l1 n); simpl; sp.
allrw in_remove_nvars; sp.
allrw @in_sub_free_vars_iff; sp.
rewrite @sub_keep_first_sub_filter in p0.
allrw @in_sub_filter; sp.
allrw @in_sub_keep_first; sp.
right.
exists x0 t; sp.
allrw @in_sub_keep_first; sp.
rw lin_flat_map.
exists (bterm l1 n); simpl; sp.
rw in_remove_nvars; sp.
+ SCase "<-".
allrw in_app_iff; sp; allrw lin_flat_map; exrepd;
allrw in_remove_nvars; repd; allsimpl.
destruct x0; allsimpl.
allrw in_remove_nvars; sp.
exists (bterm l1 n0); simpl; sp.
rw in_remove_nvars; sp.
generalize (H n0 l1 l (sub_filter sub l1)); sp.
dest_imp H1 hyp; sp.
allrw @in_sub_filter; sp.
apply H0 in X0.
allrw disjoint_flat_map_r.
apply X0 in l; allsimpl.
allrw disjoint_app_r; sp.
rw eqvars_prop in H1.
rw H1.
rw in_app_iff.
rw in_remove_nvars.
rewrite <- dom_sub_sub_filter.
rw in_remove_nvars.
left; sp.
allrw @in_sub_free_vars_iff; exrepd.
allrw @in_sub_keep_first; sp.
allrw lin_flat_map; sp.
exists x1; sp.
destruct x1; allsimpl.
allrw in_remove_nvars; sp.
generalize (H n l p0 (sub_filter sub l)); sp.
dest_imp H1 hyp; sp.
allrw @in_sub_filter; sp.
apply H0 in X0.
allrw disjoint_flat_map_r.
apply X0 in p0; allsimpl.
allrw disjoint_app_r; sp.
allrw eqvars_prop.
rw H1.
rw in_app_iff.
rw @in_sub_free_vars_iff; right.
exists x0 t; sp.
rw @in_sub_keep_first; sp.
rw @sub_find_sub_filter_some; sp.
applydup @sub_find_some in l1.
apply H0 in l2.
allrw disjoint_flat_map_r.
apply l2 in p0; allsimpl.
allrw disjoint_app_r; sp.
unfold disjoint in p2.
apply p2 in l0; sp.
Qed.
Theorem lmap_lapply_eq_implies: forall lv1 lvi1 lvo1 lv2 lvi2 lvo2,
lvmap_lapply (combine lvi1 lvo1) lv1
= lvmap_lapply (combine lvi2 lvo2) lv2
-> disjoint (lvo1++ lvo2) (lv1 ++ lv2)
-> length lvi1=length lvo1
-> length lvi2=length lvo2
-> remove_nvars lvi1 lv1 = remove_nvars lvi2 lv2.
Proof.
unfold lvmap_lapply. induction lv1 as [| v1 lv1 Hind]; introv Heq Hdis; auto.
- simpl in Heq. symmetry in Heq. apply map_eq_nil in Heq. subst.
repeat( rewrite remove_nvars_nil_r). refl.
- destruct lv2 as [| v2 lv2]; [ inverts Heq; fail | allsimpl].
repeat(rewrite remove_nvars_cons_r).
repeat (rewrite memvar_dmemvar).
apply disjoint_cons_r in Hdis.
rw disjoint_app_r in Hdis.
rw disjoint_cons_r in Hdis.
inverts Heq as Heq1 Heq2. unfold lmap_apply in Heq1.
intros Hl1 Hl2.
destruct (lmap_find deq_nvar (combine lvi1 lvo1) v1)
as [s1 | Hin1];
[ destruct s1 as [b1 Hin1]; apply in_combine in Hin1
| rewrite combine_split in Hin1; auto; simpl];
destruct (lmap_find deq_nvar (combine lvi2 lvo2) v2)
as [s2 | Hin2]; repnd;
try( destruct s2 as [? Hin2];
apply in_combine in Hin2);
try (rewrite combine_split in Hin2; auto);
repnd; allsimpl; subst.
+ (repeat cases_if; try contradiction). eapply Hind; eauto.
apply disjoint_app_r. split; trivial.
+ subst. provefalse. apply Hdis0. apply in_app_iff. sp.
+ subst. provefalse. apply Hdis. apply in_app_iff; sp.
+ subst. (repeat cases_if; try contradiction). f_equal.
eapply Hind; eauto.
apply disjoint_app_r. split; trivial.
Qed.
(**lsubst_wf_iff proved in alpgaeq.v*)
Theorem lsubst_aux_wf_iff {p} :
forall sub,
sub_range_sat sub (@nt_wf p)
-> forall nt, (nt_wf nt <=> nt_wf (lsubst_aux nt sub)).
Proof.
introv sr. sp_iff Case; introv hyp.
- apply lsubst_aux_preserves_wf; auto.
- apply lsubst_aux_nt_wf in hyp; auto.
Qed.
Theorem lsubst_aux_allvars_wf_iff {p}:
forall sub,
@allvars_sub p sub
-> forall nt, (nt_wf nt <=> nt_wf (lsubst_aux nt sub)).
Proof.
introv sr. apply lsubst_aux_wf_iff.
introv Hlin. apply sr in Hlin.
exrepnud Hlin; subst; auto.
Qed.
Lemma sub_app_sat_iff {p} : forall P sub1 sub2,
(@sub_range_sat p sub1 P
# sub_range_sat sub2 P)
<=> sub_range_sat (sub1 ++ sub2) P.
Proof. sp_iff Case.
- introv sat Hin. repnd. apply in_app_iff in Hin.
dorn Hin; [ apply sat0 in Hin | apply sat in Hin]; trivial.
- introv sat. allunfold @sub_range_sat. split; intros; eapply sat;
apply in_app_iff; eauto.
Qed.
Lemma isvarc_fst_unique {p} : forall (t: @NTerm p) (p1 p2: isvarc t),
projT1 p1=projT1 p2.
Proof. intros.
destruct p1. destruct p2.
simpl. rewrite e in e0.
inverts e0. refl.
Qed.
Definition get_sub_dom_varsd {p} sub (pall : @allvars_sub p sub) : list NVar :=
gmapd sub (fun t => match t with (a, b) => fun (p : LIn (a,b) sub) => projT1 (pall a b p) end).
Lemma get_sub_dom_vars_eq_d {p} :
forall sub (pall : @allvars_sub p sub),
get_sub_dom_vars sub pall = get_sub_dom_varsd sub pall.
Proof.
intros.
unfold get_sub_dom_vars, get_sub_dom_varsd.
rw <- gmap_eq_d; simpl.
apply eq_gmaps.
intros.
destruct a; simpl; sp.
Qed.
Lemma get_sub_dom_vars_cons {p} :
forall a b sub (pall : @allvars_sub p ((a,b)::sub)),
get_sub_dom_vars ((a,b) :: sub) pall
= projT1 (pall a b (inl eq_refl))
:: get_sub_dom_vars sub (fun v t i => pall v t (inr i)).
Proof.
introv.
repeat (rw @get_sub_dom_vars_eq_d).
unfold get_sub_dom_varsd; simpl.
apply cons_eq.
apply eq_gmapds; intros.
dprods; simpl; sp.
Qed.
Theorem get_sub_dom_vars_spec {p} :
forall sub (Hall: allvars_sub sub),
sub = combine (fst (split sub)) (map (@vterm p) (get_sub_dom_vars sub Hall)).
Proof.
introv.
induction sub; introv; try (complete auto).
dprods.
rw split_cons; rw simpl_fst.
rw @get_sub_dom_vars_cons.
rw map_cons; rw combine_cons.
destruct (Hall n n0 (inl eq_refl)); simpl; subst.
apply cons_eq.
generalize (IHsub (fun v t i => Hall v t (inr i))); sp.
Qed.
(*
Theorem get_sub_dom_vars_spec :
forall sub (Hall: allvars_sub sub),
sub = combine (fst (split sub)) (map vterm (get_sub_dom_vars sub Hall)).
Proof.
induction sub as [| (v,t) sub Hind]; auto. intros ?. simpl.
destruct (split sub) as [lv lnt]. simpl. f_equal.
- f_equal.
(** wierd! if I dont specify implicit args,
it guesses wrong ones and causes failure *)
remember (Hall v t
(@inl
(@eq (prod NVar NTerm) (@pair NVar NTerm v t)
(@pair NVar NTerm v t))
(@LIn (prod NVar NTerm) (@pair NVar NTerm v t) sub)
(@eq_refl (prod NVar NTerm) (@pair NVar NTerm v t))))
as Hisvar.
destruct Hisvar. subst. simpl. reflexivity.
- allsimpl. fold ([(v, t)] ++ sub) in Hall.
pose proof (tiff_snd (sub_app_sat_iff _ _ _) Hall). repnd.
assert (allvars_sub sub) as Hsub by auto.
pose proof (Hind Hsub ) as Hw.
allsimpl.
symmetry in Hw.
(** need to rewrite just the LHS. *)
apply ( @ transport _ _ _
(fun sub1 : Substitution =>
sub1 =
combine lv
(map vterm
(gmap sub
(fun (a0 : NVar # NTerm) (Hin : LIn a0 sub) =>
projT1
(Hall (fst a0) (snd a0)
((let (n, n0) as p
return
((v, t) = p[+]LIn p sub ->
(v, t) = (fst p, snd p)[+]LIn (fst p, snd p) sub) :=
a0 in
fun p : (v, t) = (n, n0)[+]LIn (n, n0) sub => p) (inr Hin)))))))
Hw ).
unfold get_sub_dom_vars. repeat (f_equal).
repeat (apply functional_extensionality_dep; intros).
apply isvarc_fst_unique.
Qed.
*)
Theorem get_sub_dom_vars_eta {p} : forall sub
(Hall: allvars_sub sub),
{lvi,lvo: list NVar $ (sub = @var_ren p lvi lvo) # length lvi =length lvo}.
Proof.
intros. exists (fst (split sub)).
exists (get_sub_dom_vars sub Hall).
split. apply get_sub_dom_vars_spec.
rewrite split_length_l.
unfold get_sub_dom_vars.
rewrite gmap_length; auto.
Defined.
Theorem get_sub_dom_vars_ren {p} : forall lvi lvo
(Hall: allvars_sub (@var_ren p lvi lvo)),
length lvi=length lvo
-> get_sub_dom_vars (var_ren lvi lvo) Hall = lvo.
Proof.
introv H.
pose proof (get_sub_dom_vars_spec (var_ren lvi lvo) Hall) as HH.
unfold var_ren in HH.
rewrite combine_split in HH;
[ | rewrite map_length; trivial].
allsimpl. apply combine_eq in HH;
try (rewrite map_length; auto).
repnd. apply (@map_eq_lift_vterm p); auto.
unfold get_sub_dom_vars. rewrite gmap_length.
rewrite combine_length.
rewrite map_length.
rewrite H. rewrite Min.min_idempotent; refl.
Qed.
Lemma allvars_sub_filter {p} :
forall lvi lvo lv, allvars_sub (sub_filter (@var_ren p lvi lvo) lv).
Proof.
intros. apply sub_filter_allvars.
apply allvars_combine.
Defined.
Lemma allvars_sub_filter_cons {p} : forall lvi lvo lv vi vo,
allvars_sub ((vi,vterm vo) :: (sub_filter (@var_ren p lvi lvo) lv)).
Proof.
introv Hin. dorn Hin. inverts Hin; eexists; eauto.
apply allvars_sub_filter in Hin; auto.
Defined.
Theorem no_repeats_sub_filter {p} :
forall lvi lvo lvi0 lvo0 lv,
var_ren lvi0 lvo0 = sub_filter (@var_ren p lvi lvo) lv
-> length lvi0 = length lvo0
-> no_repeats lvo
-> no_repeats lvo0.
Proof.
induction lvi as [|vi lvi Hind]; introv Heq Heql Hnr.
unfold var_ren in Heq. simpl in Heq.
destruct lvi0; destruct lvo0; try (inverts Heql);
try (inverts Heq).
- constructor.
- destruct lvo.
+ unfold var_ren in Heq.
simpl in Heq.
destruct lvi0;
destruct lvo0; try (inverts Heql);
try (inverts Heq). constructor.
+ simpl in Heq. rewrite memvar_dmemvar in Heq.
inverts Hnr as Hnin Hnr.
destruct (dmemvar vi lv).
eapply Hind; eauto.
destruct lvi0;
destruct lvo0; try (invertsn Heql);
try (invertsn Heq). constructor; auto.
Focus 2. eapply Hind; eauto.
intro Hc.
apply (@lin_lift_vterm p) in Hc.
apply combine_in_right with (l1:=lvi0) in Hc.
exrepnd.
rewrite Heq in Hc0.
apply in_sub_filter in Hc0.
repnd. apply in_combine in Hc1. repnd. sp.
apply lin_lift_vterm in Hc1. sp.
rewrite map_length. omega.
Qed.
Fixpoint diff_vars {p} (l : list NVar) (ts : list (@NTerm p)) : list NTerm :=
match ts with
| [] => []
| t :: ts =>
if intersect_vars (free_vars t) l
then diff_vars l ts
else t :: diff_vars l ts
end.
(*
This is similar to map_removevars but does not need the equality
decider and uses diff_vars instead of diff.
*)
Lemma map_removevars_l {p} :
forall lvi lvr,
map (@vterm p) (remove_nvars lvi lvr)
= diff_vars lvi (map vterm lvr).
Proof.
induction lvr; simpl.
rw remove_nvars_nil_r; simpl; auto.
rw remove_nvars_cons_r; boolvar; simpl; tcsp.
- rw disjoint_cons_l in d; repnd; tcsp.
- rw intersect_single_l in i; tcsp.
- rw IHlvr; sp.
Qed.
Theorem freevars_lsubst_aux_allvars {pp} :
forall (t : NTerm) sub
(p : allvars_sub sub),
no_repeats (get_sub_dom_vars sub p)
-> disjoint (get_sub_dom_vars sub p) (all_vars t)
-> map vterm (free_vars (lsubst_aux t sub))
= map (fun t=> lsubst_aux t sub) (map (@vterm pp) (free_vars t)).
Proof.
nterm_ind1 t as [v|f ind|o lbt Hind] Case; introv Hnr Hdis; auto.
- Case "vterm".
simpl.
unfold lmap_apply.
cases (sub_find sub v) as Hsf; auto.
exrepnd. apply sub_find_some in Hsf.
pose proof (p _ _ Hsf) as X; exrepnud X.
subst. refl.
- Case "oterm".
induction lbt as [|bt lbt IHlbt]; auto.
allsimpl. repeat(rewrite map_app).
rewrite IHlbt;
[ | intros; eapply Hind; eauto; fail
| (allrw disjoint_app_r); repnd;auto; fail].
clear IHlbt.
f_equal.
destruct bt as [lv nt].
simpl. unfold bvar_renamings_subst. simpl.
remember ((sub_filter sub lv)) as sfio.
remember (@sub_mk_renames2 pp lv (sub_free_vars sfio) (dom_sub sfio ++ all_vars nt) ) as H99.
destruct H99 as [lvr subr].
pose proof (get_sub_dom_vars_eta sub p).
exrepnd. subst.
duplicate Hdis.
unfold all_vars in Hdis. simpl in Hdis.
repeat(rw disjoint_app_r in Hdis).
rewrite sub_mk_renames2_disjoint in HeqH99.
Focus 2.
repnd. rewrite get_sub_dom_vars_ren in Hdis3; auto.
apply disjoint_sym in Hdis3.
introv Hc1 Hc2. apply Hdis3 in Hc1.
apply in_sub_free_vars in Hc2. exrepnd.
apply in_sub_filter in Hc0; repnd.
apply in_combine in Hc3. repnd.
apply in_map_iff in Hc3. exrepnd. subst.
allsimpl. dorn Hc2; sp.
subst; sp.
inverts HeqH99. allsimpl.
pose proof (@allvars_sub_filter pp lvi lvo lv) as Halv.
rewrite map_removevars_l.
erewrite Hind with (p:=Halv); eauto.
clear Hind.
unfold lvmap_lapply.
remember (free_vars nt) as fnt.
pose proof (@transport _ _ _ (fun vs => subvars fnt vs)
Heqfnt (subvars_refl fnt)) as Hsub.
allsimpl.
clear Heqfnt. repnd.
induction fnt as [| vnt fnt Hfntind];
[ complete (rw remove_nvars_nil_r; refl) | simpl ].
apply subvars_cons_l in Hsub; repnd.
rewrite Hfntind; auto. clear Hfntind.
dest_intersect_vars.
+ f_equal. rewrite remove_nvars_cons_r.
rewrite memvar_dmemvar.
cases_if_sum Hmemdin;auto.
rewrite sub_lmap_find in i.
provefalse.
apply disjoint_sym in Hdis3.
destruct (lmap_find deq_nvar (sub_filter (var_ren lvi lvo) lv)
vnt) as [ex | ?]; exrepnd; allsimpl;
[ | rw intersect_single_l in i; sp].
subst. apply in_sub_filter in ex0; repnd.
rewrite get_sub_dom_vars_ren in Hdis3; auto.
clear Hdis Hdis1 Hdis2 Hdis4 Hdis0 Halv.
apply in_combine in ex1. repnd.
apply in_map_iff in ex1. exrepnd.
subst; allsimpl.
rw intersect_single_l in i.
apply Hdis3 in i; sp.
+ rewrite remove_nvars_cons_r.
rewrite memvar_dmemvar.
cases_if_sum Hmemdin; auto.
* provefalse.
rewrite sub_lmap_find in d.
destruct (lmap_find deq_nvar
(sub_filter (var_ren lvi lvo) lv) vnt)
as [ex | ?]; exrepnd; allsimpl.
subst. apply in_sub_filter in ex0; repnd.
apply in_combine in ex1. repnd. sp.
rw disjoint_singleton_l in d; sp.
* simpl. f_equal.
rewrite sub_find_sub_filter_eta; auto.
+ clear Hfntind. rewrite get_sub_dom_vars_ren; auto.
rewrite get_sub_dom_vars_ren in Hdis4; auto.
rewrite remove_nvars_cons_r in Hdis4.
revert Hdis4. cases_if; auto.
rw disjoint_cons_r; sp.
+ remember ((sub_filter (var_ren lvi lvo) lv)) as Hsb.
pose proof (get_sub_dom_vars_eta Hsb Halv) as ex. exrepnd.
revert Halv. rewrite ex0.
intro. rewrite ex0 in HeqHsb.
rewrite get_sub_dom_vars_ren; auto.
rewrite get_sub_dom_vars_ren in Hnr; auto.
apply no_repeats_sub_filter in HeqHsb; trivial.
+ remember ((sub_filter (var_ren lvi lvo) lv)) as Hsb.
pose proof (get_sub_dom_vars_eta Hsb Halv) as ex. exrepnd.
revert Halv. rewrite ex0.
intro. rewrite ex0 in HeqHsb.
rewrite get_sub_dom_vars_ren; auto.
rewrite get_sub_dom_vars_ren in Hdis2; auto.
rewrite get_sub_dom_vars_ren in Hdis4; auto.
rewrite get_sub_dom_vars_ren in Hdis3; auto.
clear Hdis Hdis1 Hdis0 .
assert (disjoint lvo (all_vars nt)) as Hvo.
* apply disjoint_app_r. split; auto.
introv Hin Hc. applydup Hdis4 in Hin.
apply Hin0. apply in_remove_nvars. split; auto.
* introv Hin Hc. apply (@lin_lift_vterm pp) in Hin.
apply combine_in_right with (l1:=lvi0) in Hin.
exrepnd. unfold var_ren in HeqHsb.
rewrite HeqHsb in Hin0.
apply in_sub_filter in Hin0. repnd.
apply in_combine in Hin1. repnd.
apply lin_lift_vterm in Hin1.
apply Hvo in Hin1. sp.
rewrite map_length. omega.
Qed.
Theorem no_repeats_subvars : forall lvi lvo,
no_repeats lvi
-> subvars lvo lvi
-> no_repeats lvo.
Proof.
induction lvi; introv Hnr Hsub; auto; destruct lvo; cpx.
- rw subvars_cons_l in Hsub. repnd. cpx.
- constructor.
Abort. (**not true*)
(* Print Assumptions freevars_lsubst_allvars. *)
Lemma lmap_apply_var {p} : forall lvi lvo v,
(fun t=> lsubst t (var_ren lvi lvo)) (vterm v)
= @vterm p (lmap_apply deq_nvar (combine lvi lvo) v).
Proof.
intros. simpl. unfold lsubst. simpl. rewrite sub_lmap_find.
unfold lmap_apply.
unfold var_ren. rewrite <- lmap_find_injection; [| introv H; inverts H;sp].
cases(lmap_find deq_nvar (combine lvi lvo) v); exrepnd; simpl; auto.
Qed.
Lemma lmap_lapply_var_map {p} : forall lvi lvo lv,
map (fun t=> lsubst_aux t (var_ren lvi lvo)) (map vterm lv)
= map (@vterm p) (lmap_lapply deq_nvar (combine lvi lvo) lv).
Proof.
induction lv as [|v lv Hind];auto.
simpl. rewrite Hind. f_equal.
rewrite <- lmap_apply_var; refl.
Qed.
Theorem freevars_lsubst_allvars2 {p} :
forall (t : NTerm) (lvi lvo: list NVar),
length lvi= length lvo
-> no_repeats lvo
-> disjoint lvo (all_vars t)
-> free_vars (lsubst t (@var_ren p lvi lvo) )
= lvmap_lapply (combine lvi lvo) (free_vars t).
Proof.
introv Hleq Hnr Hdis.
unfold lsubst. cases_ifn Hd.
Focus 2. allunfold @var_ren. spcls. spcls.
provefalse. apply Hd. disjoint_reasoningv.
pose proof (freevars_lsubst_aux_allvars
t (var_ren lvi lvo) (allvars_combine lvi lvo)) as HH.
rewrite get_sub_dom_vars_ren in HH; auto.
allsimpl. pose proof (HH Hnr Hdis) as HH1.
clear HH.
rewrite lmap_lapply_var_map in HH1.
apply (@map_eq_lift_vterm p); trivial.
Qed.
Lemma lsubst_aux_trivial3 {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> disjoint (@free_vars p u) (bound_vars t)
# ! LIn v (free_vars t))
-> lsubst_aux t sub = t.
Proof.
nterm_ind t Case; simpl; intros; auto.
- Case "vterm".
allunfold @isprogram; allunfold @closed; sp.
remember (sub_find sub n); destruct o; symmetry in Heqo; auto.
apply sub_find_some in Heqo.
apply_in_hyp pp; sp.
apply not_over_or in pp; sp.
- Case "oterm". f_equal.
induction lbt; simpl; auto.
rw IHlbt; sp.
+ destruct a; simpl. f_equal.
* f_equal. f_equal. eapply H; try(left); eauto.
introv Hin. apply in_sub_filter in Hin. repnd.
rename H0 into Hdis. apply Hdis in Hin0. repnd.
rw disjoint_app_r in Hin1.
rw disjoint_app_r in Hin1.
repnd. split; auto.
intro Hc. apply Hin0.
apply in_app_iff.
left. apply in_remove_nvars; sp.
+ rewrite H with (lv := lv); sp.
+ apply_in_hyp pp; sp. allsimpl.
rw disjoint_app_r in pp0. sp.
+ apply_in_hyp pp; sp; allsimpl.
allrw in_app_iff.
allrw not_over_or; sp.
Qed.
Lemma lsubst_trivial3 {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> disjoint (@free_vars p u) (bound_vars t)
# ! LIn v (free_vars t))
-> lsubst t sub = t.
Proof.
introv HH. assert (disjoint_bv_sub t sub).
introv Hin. apply HH in Hin. sp.
change_to_lsubst_aux4.
apply lsubst_aux_trivial3; try(sp;fail);
try(apply disjoint_sub_as_flat_map;disjoint_reasoning).
Qed.
Lemma lsubst_trivial4 {p} :
forall t sub, disjoint (@dom_sub p sub) (free_vars t)
-> (forall v u, LIn (v, u) sub -> disjoint (free_vars u) (bound_vars t))
-> lsubst t sub = t.
Proof.
introv Hdis Hfr.
apply lsubst_trivial3.
introv Hin.
applydup_clear Hfr in Hin.
sp. apply disjoint_sym in Hdis.
apply Hdis in X.
apply in_dom_sub in Hin. sp.
Qed.
Lemma lsubst_aux_trivial4 {p} :
forall t sub, disjoint (@dom_sub p sub) (free_vars t)
-> (forall v u, LIn (v, u) sub -> disjoint (free_vars u) (bound_vars t))
-> lsubst_aux t sub = t.
Proof.
introv Hdis Hfr.
apply lsubst_aux_trivial3.
introv Hin.
applydup_clear Hfr in Hin.
sp. apply disjoint_sym in Hdis.
apply Hdis in X.
apply in_dom_sub in Hin. sp.
Qed.
Lemma sub_filter_disjoint1 {p} :
forall sub lf,
disjoint (@dom_sub p sub) lf
-> sub_filter sub lf
= sub.
Proof.
induction sub as [|(v,t) sub Hind]; introv K; auto.
simpl. allsimpl. apply disjoint_cons_l in K.
rewrite memvar_dmemvar.
cases_if; [clear H | ];sp.
f_equal. auto.
Qed.
Lemma sub_filter_disjoint {p} :
forall lvi lvo lvf,
length lvi = length lvo
-> disjoint lvi lvf
-> sub_filter (var_ren lvi lvo) lvf
= @var_ren p lvi lvo.
Proof.
intros. apply sub_filter_disjoint1.
unfold var_ren. rewrite dom_sub_combine. auto.
rewrite map_length; auto; try omega.
Qed.
Lemma in_combine_vars_vterm {p} : forall lvi lvo u v ,
LIn (u,v) (combine lvi lvo) -> LIn (u, vterm v) (@var_ren p lvi lvo).
Proof.
introv X. assert (injective_fun (fun x:NVar => x)) as Hi by (introv;auto).
pose proof (tiff_fst (lin_combine_injective (fun x : NVar => x) vterm
Hi (@vterm_inj p) _ _ _ _) X) as XX. rewrite map_id in XX.
auto.
Qed.
Theorem disjoint_sub_filter_vars_l {p} : forall lvi lvo lvis lvos lv ld,
sub_filter (var_ren lvi lvo) lv = @var_ren p lvis lvos
-> length lvi =length lvo
-> length lvis =length lvos
-> disjoint lvi ld
-> disjoint lvis ld.
Proof.
introv Hsf Hlen Hle1n Hdis. introv Hin.
apply combine_in_left with (l2:=lvos) in Hin; auto.
exrepnd. apply (@in_combine_vars_vterm p) in Hin0. rewrite <- Hsf in Hin0.
apply in_sub_filter in Hin0. repnd. apply in_combine in Hin1. repnd.
apply Hdis in Hin2. sp.
Qed.
Theorem disjoint_sub_filter_vars_r {p} : forall lvi lvo lvis lvos lv ld,
sub_filter (var_ren lvi lvo) lv = @var_ren p lvis lvos
-> length lvi =length lvo
-> length lvis =length lvos
-> disjoint lvo ld
-> disjoint lvos ld.
Proof.
introv Hsf Hlen Hle1n Hdis. introv Hin.
apply combine_in_right with (l1:=lvis) in Hin; auto.
exrepnd. apply (@in_combine_vars_vterm p) in Hin0. rewrite <- Hsf in Hin0.
apply in_sub_filter in Hin0. repnd. apply in_combine in Hin1. repnd.
apply in_map_iff in Hin1. exrepnd. inverts Hin3.
apply Hdis in Hin1. sp.
omega.
Qed.
Theorem disjoint_sub_filter_l {p} : forall lvi lnt lvis lnts ld lv,
@sub_filter p (combine lvi lnt) lv = combine lvis lnts
-> length lvi =length lnt
-> length lvis =length lnts
-> disjoint lvi ld
-> disjoint lvis ld.
Proof.
introv Hsf Hlen Hle1n Hdis. introv Hin Hc.
apply combine_in_left with (l2:=lnts) in Hin ; auto.
exrepnd.
rw <- Hsf in Hin0.
apply in_sub_filter in Hin0. repnd. apply in_combine in Hin1. repnd.
apply Hdis in Hin2. sp.
Qed.
Theorem disjoint_sub_filter_vars {p} : forall lvi lvo lvis lvos lv ld,
sub_filter (var_ren lvi lvo) lv = @var_ren p lvis lvos
-> length lvi =length lvo
-> length lvis =length lvos
-> disjoint (lvi++lvo) ld
-> disjoint (lvis++lvos) ld.
Proof.
introv Hsf Hlen Hle1n Hdis. apply disjoint_app_l in Hdis. repnd.
duplicate Hsf.
apply @disjoint_sub_filter_vars_l with (ld:=ld) in Hsf; auto.
apply @disjoint_sub_filter_vars_r with (ld:=ld) in Hsf0; auto.
apply disjoint_app_l; auto.
Qed.
Lemma sub_find_first {p} : forall sub v t,
@sub_find p sub v= Some t
-> {n: nat & (n < length sub) # nth n sub (v,t) =(v,t) #
not_in_prefix (dom_sub sub) v n}.
Proof.
introns K. rewrite (sub_lmap_find_first) in K.
destruct (lmap_find_first deq_nvar sub v) as [s1s|n1n];
exrepnd; allsimpl; allfold (@dom_sub p); inverts K.
exists n; sp.
Qed.
Lemma sub_find_some2_first {p} :
forall lv lnt1 lnt2 v t1 t2,
length lv = length lnt1
-> length lv = length lnt2
-> @sub_find p (combine lv lnt1) v = Some t1
-> @sub_find p (combine lv lnt2) v = Some t2
-> {n:nat & n< length lv #
nth n lv v= v # not_in_prefix lv v n
# nth n lnt1 t1= t1 # nth n lnt2 t2= t2}.
Proof.
introv H1len H2len H1s H2s.
apply sub_find_first in H1s.
apply sub_find_first in H2s.
exrepnd.
rewrite_once combine_length.
rewrite_once combine_length.
rewrite_once @dom_sub_combine; cpx.
rewrite_once @dom_sub_combine; cpx.
rewrite_once combine_nth; cpx.
rewrite_once combine_nth; cpx.
rewrite_once min_eq; cpx.
rewrite_once min_eq; cpx.
assert (is_first_index lv v n) as H1isf by
(unfolds_base;split;(try split);cpx; try(congruence)).
assert (is_first_index lv v n0) as H2isf by
(unfolds_base;split;(try split);cpx; try(congruence)).
assert (n=n0) by (eapply is_first_index_unique; eauto).
subst. rename n0 into n. GC.
repeat (dpair_eq).
exists n; dands; cpx; try congruence;
try (rewrite H1s2l; auto);
try (rewrite H1s2l; auto).
Qed.
Lemma sub_find_some_none_contra {p} : forall lv lnt1 lnt2 v t1,
length lv = length lnt1
-> length lv = length lnt2
-> @sub_find p (combine lv lnt1) v = Some t1
-> @sub_find p (combine lv lnt2) v = None
-> False.
Proof.
introv H1l H2n Hsfs Hsfn.
apply sub_find_some in Hsfs. apply in_combine in Hsfs. repnd.
apply sub_find_none2 in Hsfn. rewrite_once @dom_sub_combine; sp.
Qed.
Lemma disjoint_free_vars_lsubst {p} :
forall (nt : NTerm) (sub : @Substitution p) lvdr,
disjoint (flat_map free_vars (range sub)) (bound_vars nt)
-> disjoint (free_vars nt ++ (flat_map free_vars (range sub))) lvdr
-> disjoint (free_vars (lsubst nt sub)) lvdr.
Proof.
introv H1dis H2dis.
introv Hin Hc.
apply free_vars_lsubst in Hin;
[|unfold disjoint_bv_sub;rw @disjoint_sub_as_flat_map;sp];[].
apply disjoint_app_l in H2dis; repnd.
dorn Hin.
- apply H2dis0 in Hin. sp.
- exrepnd. rw <- @disjoint_sub_as_flat_map in H2dis.
apply H2dis in Hin0.
apply Hin0 in Hin1. sp.
Qed.
Lemma disjoint_free_vars_lsubst_aux {p} :
forall (nt : NTerm) (sub : @Substitution p) lvdr,
disjoint (flat_map free_vars (range sub)) (bound_vars nt)
-> disjoint (free_vars nt ++ (flat_map free_vars (range sub))) lvdr
-> disjoint (free_vars (lsubst_aux nt sub)) lvdr.
Proof.
introv H1dis H2dis.
introv Hin Hc.
apply free_vars_lsubst_aux in Hin;
[|unfold disjoint_bv_sub;rw @disjoint_sub_as_flat_map;sp];[].
apply disjoint_app_l in H2dis; repnd.
dorn Hin.
- apply H2dis0 in Hin. sp.
- exrepnd. rw <- @disjoint_sub_as_flat_map in H2dis.
apply H2dis in Hin0.
apply Hin0 in Hin1. sp.
Qed.
Lemma boundvars_lsubst_aux {p}:
forall nt sub v,
disjoint_bv_sub nt sub
-> LIn v (bound_vars (lsubst_aux nt sub))
-> LIn v (bound_vars nt)[+]
{v' : NVar &
{t : @NTerm p & sub_find sub v' =Some t # LIn v' (free_vars nt) # LIn v (bound_vars t)}}.
Proof.
nterm_ind1s nt as [v|f ind| o lbt Hind] Case; introv Hdis Hin; auto; auto.
- Case "vterm". allsimpl. right.
allsimpl. dsub_find sn; cpx;[].
exists v sns. split; auto.
- Case "oterm". simpl.
simpl in Hin. rw lin_flat_map in Hin.
destruct Hin as [bt' Hin]. repnd. apply in_map_iff in Hin0.
destruct Hin0 as [bt Hin0]. repnd. subst. destruct bt as [lv nt].
simpl in Hin.
simpl in Hin. apply in_app_iff in Hin. dorn Hin.
+ left. apply lin_flat_map. eexists; split; eauto. simpl. apply in_app_iff.
left; sp.
+ apply Hind with (lv:=lv) (nt:=nt) in Hin; cpx;
[|eauto 3 with slow|eapply disjoint_bv_sub_ot; eauto].
dorn Hin.
* left. simpl. apply lin_flat_map. eexists; split; eauto. simpl.
apply in_app_iff. right. auto.
* exrepnd. right. rw @sub_find_sub_filter_some in Hin0.
repnd. eexists; eauto. eexists; dands; eauto.
apply lin_flat_map. eexists; split; eauto;[].
simpl. apply in_remove_nvars. split; auto.
Qed.
Lemma boundvars_lsubst {p} :
forall nt sub v,
disjoint_bv_sub nt sub
-> LIn v (bound_vars (lsubst nt sub))
-> LIn v (bound_vars nt)[+]
{v' : NVar &
{t : @NTerm p & sub_find sub v' =Some t # LIn v' (free_vars nt) # LIn v (bound_vars t)}}.
Proof.
introv Hd. change_to_lsubst_aux4. intros.
apply boundvars_lsubst_aux;try(sp;fail);
try(rw @disjoint_sub_as_flat_map;disjoint_reasoning).
Qed.
Lemma boundvars_lsubst_aux_vars {p} :
forall nt lvi lvo,
length lvi = length lvo
-> disjoint lvo (bound_vars nt)
-> bound_vars (lsubst_aux nt (@var_ren p lvi lvo))
= bound_vars nt.
Proof.
nterm_ind1s nt as [v|f ind|o lbt Hind] Case; introv Hl Hdis; auto.
- Case "vterm". simpl. rewrite sub_lmap_find.
destruct (lmap_find deq_nvar (var_ren lvi lvo) v) as [s1s| n1n];auto; exrepnd.
allsimpl. apply in_var_ren in s1s0. exrepnd. subst. auto.
- Case "oterm". simpl. rewrite flat_map_map.
apply eq_flat_maps. intros bt Hin. destruct bt as [lv nt].
unfold compose. simpl.
eapply (@disjoint_lbt_bt2 p) in Hdis; eauto. repnd.
+ simpl. f_equal. pose proof (@allvars_sub_filter p lvi lvo lv) as X1X.
apply get_sub_dom_vars_eta in X1X. exrepnd.
rewrite X1X0. eapply Hind; eauto 3 with slow.
eapply disjoint_sub_filter_vars_r with (ld:= (bound_vars nt)) in X1X0
; eauto.
Qed.
Lemma boundvars_lsubst_vars {p} :
forall nt lvi lvo,
length lvi = length lvo
-> disjoint lvo (bound_vars nt)
-> bound_vars (lsubst nt (@var_ren p lvi lvo))
= bound_vars nt.
Proof.
intros. change_to_lsubst_aux4.
apply boundvars_lsubst_aux_vars;try(sp;fail);
try(rw disjoint_sub_as_flat_map;disjoint_reasoningv).
Qed.
Lemma boundvars_lsubst_vars2 {p} :
forall nt sub,
@allvars_sub p sub
-> disjoint_bv_sub nt sub
-> bound_vars (lsubst nt sub)
= bound_vars nt.
Proof.
introv Ha Hd. change_to_lsubst_aux4.
pose proof (get_sub_dom_vars_eta _ Ha) as XX.
exrepnd. GC. revert Hd. intro Hd. allrw XX0.
spcls.
apply boundvars_lsubst_aux_vars;try(sp;fail).
disjoint_reasoning.
Qed.
Lemma disjoint_bound_vars_lsubst {p} :
forall (nt : NTerm) (sub : @Substitution p) lvdr,
disjoint (flat_map free_vars (range sub)) (bound_vars nt)
-> disjoint (bound_vars nt ++ (flat_map bound_vars (range sub))) lvdr
-> disjoint (bound_vars (lsubst nt sub)) lvdr.
Proof.
introv H1dis H2dis.
introv Hin Hc.
apply boundvars_lsubst in Hin;
[|unfold disjoint_bv_sub;rw @disjoint_sub_as_flat_map;sp];[].
apply disjoint_app_l in H2dis; repnd.
dorn Hin.
- apply H2dis0 in Hin. sp.
- exrepnd. rw <- @disjoint_sub_as_flat_map in H2dis.
apply sub_find_some in Hin0.
apply H2dis in Hin0.
apply Hin0 in Hin1. sp.
Qed.
Lemma disjoint_bound_vars_lsubst_aux {p} :
forall (nt : NTerm) (sub : @Substitution p) lvdr,
disjoint (flat_map free_vars (range sub)) (bound_vars nt)
-> disjoint (bound_vars nt ++ (flat_map bound_vars (range sub))) lvdr
-> disjoint (bound_vars (lsubst_aux nt sub)) lvdr.
Proof.
introv H1dis H2dis.
introv Hin Hc.
apply boundvars_lsubst_aux in Hin;
[|unfold disjoint_bv_sub;rw @disjoint_sub_as_flat_map;sp];[].
apply disjoint_app_l in H2dis; repnd.
dorn Hin.
- apply H2dis0 in Hin. sp.
- exrepnd. rw <- @disjoint_sub_as_flat_map in H2dis.
apply sub_find_some in Hin0.
apply H2dis in Hin0.
apply Hin0 in Hin1. sp.
Qed.
(** 1 or less renaming subgoals. see lsubst_nest_swap2 for an example*)
Ltac almost_complete1 t :=
((t;fail) || (t;[])).
Ltac dis_almost_complete1 t :=
try(almost_complete1 t);try (apply disjoint_sym; almost_complete1 t).
Hint Resolve prog_sub_implies_wf : slow.
Hint Resolve disjoint_sub_filter_r_flatmap2 : slow.
Hint Resolve disjoint_sym : slow.
Lemma disjoint_dom_sub_filt {p} : forall sub lv,
disjoint (dom_sub (@sub_filter p sub lv)) lv.
Proof. introv Hin Hinc.
unfold dom_sub, dom_lmap in Hin.
apply in_map_iff in Hin.
exrepnd.
allsimpl. subst.
apply in_sub_filter in Hin1.
repnd. sp.
Qed.
Lemma disjoint_dom_sub_filt2 {p} : forall sub lv1 lvn,
disjoint (@dom_sub p sub) lvn
-> disjoint (dom_sub (sub_filter sub lv1)) lvn.
Proof.
introv Hdis Hin Hinc.
unfold dom_sub, dom_lmap in Hin.
apply in_map_iff in Hin.
exrepnd.
allsimpl. subst.
apply in_sub_filter in Hin1.
repnd. apply in_dom_sub in Hin0.
disjoint_lin_contra.
Qed.
(** update it in substitution.v *)
Ltac disjoint_sub_filter :=
let tac1:=(eapply disjoint_sub_filter_l;eauto) in
let tac2:=(eapply disjoint_sub_filter_r_flatmap;eauto) in
dis_almost_complete1 tac1;dis_almost_complete1 tac2;disjoint_reasoningv;
(
let maintac := apply disjoint_sub_filter_r_flatmap2; disjoint_reasoningv in
match goal with
|[ |- (disjoint (flat_map _ (range (sub_filter _ _ ))) _ )]
=> maintac
|[ |- ( disjoint _ (flat_map _ (range (sub_filter _ _ ))))]
=> apply disjoint_sym; maintac
| [ |- disjoint (dom_sub (sub_filter ?sub ?lv)) ?lv ]
=> apply disjoint_dom_sub_filt; fail
| [ |- disjoint ?lv (dom_sub (sub_filter ?sub ?lv)) ]
=> apply disjoint_sym; apply disjoint_dom_sub_filt; fail
| [ H : (disjoint (dom_sub (sub_filter ?sub ?lv)) ?lv) |- _]
=> clear H
| [ H : ?lv (disjoint (dom_sub (sub_filter ?sub ?lv))) |- _]
=> clear H
| [ |- disjoint (dom_sub (sub_filter ?sub _)) _ ]
=> apply disjoint_dom_sub_filt2; disjoint_reasoningv
| [ |- disjoint _ (dom_sub (sub_filter ?sub _))]
=> apply disjoint_sym; apply disjoint_dom_sub_filt2; disjoint_reasoningv
end
).
Ltac disjoint_lsubst :=
let maintacf := apply disjoint_free_vars_lsubst_aux;
disjoint_reasoningv;try(disjoint_sub_filter) in
let maintacb := apply disjoint_bound_vars_lsubst_aux;
disjoint_reasoningv;try(disjoint_sub_filter) in
match goal with
|[ |- disjoint (free_vars (lsubst_aux _ _ )) _ ]
=> maintacf
|[ |- disjoint _ (free_vars (lsubst_aux _ _ ))]
=> apply disjoint_sym ; maintacf
|[ |- disjoint (bound_vars (lsubst_aux _ _ )) _ ]
=> maintacb
|[ |- disjoint _ (bound_vars (lsubst_aux _ _ ))]
=> apply disjoint_sym ; maintacb
end.
Lemma lsubst_aux_nest_swap2 {p} : forall t sub1 sub2,
let lvi1 := @dom_sub p sub1 in
let lvi2 := dom_sub sub2 in
let lnt1 := range sub1 in
let lnt2 := range sub2 in
disjoint lvi1 (flat_map free_vars lnt2) (**o/w capture will occur in RHS*)
-> disjoint lvi2 (flat_map free_vars lnt1) (**o/w capture will occur in LHS*)
-> disjoint lvi1 lvi2 (**o/w order will matter*)
-> disjoint (flat_map bound_vars lnt1) (flat_map free_vars lnt2) (**o/w renaming will occur in LHS*)
-> disjoint (flat_map bound_vars lnt2) (flat_map free_vars lnt1) (**o/w renaming will occur in RHS*)
-> disjoint (bound_vars t) ((flat_map free_vars lnt1) ++ (flat_map free_vars lnt2)) (**o/w renaming will occur*)
-> lsubst_aux(lsubst_aux t sub1) sub2 = lsubst_aux(lsubst_aux t sub2) sub1.
Proof.
nterm_ind1s t as [v|f ind|o lbt Hind] Case; auto;
introv H1dis H2dis H3dis H4dis H5dis Hdist; simpl;
pose proof (sub_eta sub1) as Xsub1eta;
pose proof (sub_eta sub2) as Xsub2eta;
pose proof (sub_eta_length sub1) as Xlen1;
pose proof (sub_eta_length sub2) as Xlen2;
remember (dom_sub sub1) as lvi1;
remember (dom_sub sub2) as lvi2;
remember (range sub1) as lnt1;
remember (range sub2) as lnt2.
Case "vterm".
- simpl. destructr (sub_find sub1 v) as [s1|n1].
+ symmetry in HeqHdeq. applydup @sub_find_some in HeqHdeq.
simpl. rw Xsub1eta in HeqHdeq0.
apply in_combine in HeqHdeq0. repnd.
assert (disjoint lvi1 lvi2) as XX by disjoint_reasoningv.
apply XX in HeqHdeq1.
destructr (sub_find (combine lvi2 lnt2) v) as [s2|n2];
[ symmetry in HeqHdeq2; applydup @sub_find_some in HeqHdeq2;
apply in_combine in HeqHdeq3; repnd; sp | ];[].
simpl. rw Xsub2eta. rewrite <- HeqHdeq2. simpl. rw HeqHdeq.
rewrite lsubst_aux_trivial4; auto.
* rewrite dom_sub_combine; sp. disjoint_reasoningv.
GC. allsimpl. clear Hdist Hdist0.
apply disjoint_sym in H2dis. rw disjoint_flat_map_l in H2dis.
apply H2dis in HeqHdeq0. allsimpl. disjoint_reasoningv.
* rw @disjoint_sub_as_flat_map.
try(rewrite dom_range_combine;try( congruence)).
revert HeqHdeq0. clear HeqHdeq.
revert s1. apply disjoint_flat_map_r.
disjoint_reasoningv.
+ symmetry in HeqHdeq. rw Xsub2eta.
destructr (sub_find (combine lvi2 lnt2) v) as [s2|n2];simpl;
[|rewrite HeqHdeq;rewrite <- HeqHdeq0; sp];[].
simpl. rewrite <- HeqHdeq0.
applysym @sub_find_some in HeqHdeq0.
apply in_combine in HeqHdeq0. repnd.
rewrite lsubst_aux_trivial4; auto.
* rw <- Heqlvi1. revert HeqHdeq0. apply disjoint_flat_map_r.
disjoint_reasoningv.
* rw @disjoint_sub_as_flat_map.
rw <- Heqlnt1.
revert HeqHdeq0. clear HeqHdeq.
apply disjoint_flat_map_r.
disjoint_reasoningv.
- Case "oterm".
simpl. f_equal. repeat(rewrite map_map).
apply eq_maps. intros bt Hin.
destruct bt as [lv nt].
unfold compose.
simpl.
allsimpl. apply disjoint_sym in Hdist.
eapply disjoint_lbt_bt2 in Hdist; eauto. repnd.
apply disjoint_app_l in Hdist0. repnd.
repeat (rewrite (bvar_renamings_subst_disjoint_bound_vars); [|
apply disjoint_sub_as_flat_map;try (rewrite <-Heqlnt1);try (rewrite <-Heqlnt2); sp;
disjoint_reasoning]).
simpl.
repeat (rewrite (bvar_renamings_subst_disjoint_bound_vars); [|
apply disjoint_sub_as_flat_map;try (rewrite <-Heqlnt1);try (rewrite <-Heqlnt2); sp;
disjoint_reasoningv]).
simpl. f_equal. disjoint_reasoningv.
erewrite Hind; eauto;[| | | | | |]; eauto 3 with slow;
pose proof (sub_eta (sub_filter sub1 lv)) as Xsf1eta;
pose proof (sub_eta (sub_filter sub2 lv)) as Xssf2eta;
pose proof (sub_eta_length (sub_filter sub1 lv)) as X1len;
pose proof (sub_eta_length (sub_filter sub2 lv)) as X2len;
remember (dom_sub (sub_filter sub1 lv)) as lsvi1;
remember (dom_sub (sub_filter sub2 lv)) as lsvi2;
remember (range (sub_filter sub1 lv)) as lsnt1;
remember (range (sub_filter sub2 lv)) as lsnt2;
rewrite_once Xsub1eta;
rewrite_once Xsub1eta;
rewrite_once Xsub1eta;
rewrite_once Xsub1eta;
rewrite_once Xsub2eta;
rewrite_once Xsub2eta;
rewrite_once Xsub2eta;
rewrite_once Xsub2eta;[| | | | |]; disjoint_reasoningv; disjoint_sub_filter.
Qed.
Lemma lsubst_nest_swap2 {p} : forall t sub1 sub2,
let lvi1 := @dom_sub p sub1 in
let lvi2 := dom_sub sub2 in
let lnt1 := range sub1 in
let lnt2 := range sub2 in
disjoint lvi1 (flat_map free_vars lnt2) (**o/w capture will occur in RHS*)
-> disjoint lvi2 (flat_map free_vars lnt1) (**o/w capture will occur in LHS*)
-> disjoint lvi1 lvi2 (**o/w order will matter*)
-> disjoint (flat_map bound_vars lnt1) (flat_map free_vars lnt2) (**o/w renaming will occur in LHS*)
-> disjoint (flat_map bound_vars lnt2) (flat_map free_vars lnt1) (**o/w renaming will occur in RHS*)
-> disjoint (bound_vars t) ((flat_map free_vars lnt1) ++ (flat_map free_vars lnt2)) (**o/w renaming will occur*)
-> lsubst(lsubst t sub1) sub2 = lsubst(lsubst t sub2) sub1.
Proof.
intros. change_to_lsubst_aux4.
apply lsubst_aux_nest_swap2;try(sp;fail);
try(apply disjoint_sub_as_flat_map;disjoint_reasoning).
- rw <- @lsubst_lsubst_aux;disjoint_reasoningv.
apply disjoint_bound_vars_lsubst; disjoint_reasoningv.
- rw <- @lsubst_lsubst_aux;disjoint_reasoningv.
apply disjoint_bound_vars_lsubst; disjoint_reasoningv.
Qed.
Lemma lsubst_nest_swap {p} : forall t lvi1 lvo1 lvi2 lvo2,
length lvi1=length lvo1
-> length lvi2=length lvo2
-> disjoint lvi1 lvi2 # disjoint lvi1 lvo2 # disjoint lvi2 lvo1
-> disjoint (bound_vars t) (lvo1 ++ lvo2)
-> let sub1:= @var_ren p lvi1 lvo1 in
let sub2:= var_ren lvi2 lvo2 in
lsubst(lsubst t sub1) sub2 = lsubst(lsubst t sub2) sub1.
Proof.
simpl.
intros.
unfold var_ren.
apply lsubst_nest_swap2; spcls; disjoint_reasoningv.
Qed.
Lemma lsubst_aux_nest_swap {p} : forall t lvi1 lvo1 lvi2 lvo2,
length lvi1=length lvo1
-> length lvi2=length lvo2
-> disjoint lvi1 lvi2 # disjoint lvi1 lvo2 # disjoint lvi2 lvo1
-> disjoint (bound_vars t) (lvo1 ++ lvo2)
-> let sub1:= @var_ren p lvi1 lvo1 in
let sub2:= var_ren lvi2 lvo2 in
lsubst_aux(lsubst_aux t sub1) sub2 = lsubst_aux(lsubst_aux t sub2) sub1.
Proof.
simpl. intros. unfold var_ren. apply lsubst_aux_nest_swap2;spcls; disjoint_reasoningv.
Qed.
Lemma disjoint_bv_vars {p} : forall t lvi lvo,
disjoint lvo (bound_vars t)
-> disjoint_bv_sub t (@var_ren p lvi lvo).
Proof.
introv Hdis XX. apply in_var_ren in XX; exrepnd; subst.
simpl. apply disjoint_cons_l. split;[sp|].
apply Hdis; auto.
Qed.
Lemma wf_sub_vars {p} : forall lvi lvo, wf_sub (@var_ren p lvi lvo).
Proof.
introv Hin. apply in_var_ren in Hin; exrepnd; subst.
constructor.
Qed.
Definition filt_var_ren {p} lvi lvo lv := sub_filter (@var_ren p lvi lvo) lv.
Lemma nth_var_ren_implies {p} : forall lvi lvo v b vd bd n,
nth n (var_ren lvi lvo) (vd, bd) = (v, b)
-> length lvi = length lvo
-> n < length lvi
-> (nth n lvi v= v)
# {vsr : NVar & (b = @vterm p vsr)
# (nth n lvo vsr= vsr)}.
Proof.
introv X1X X2X X3X. unfold var_ren in X1X.
rewrite combine_nth in X1X;[| rewrite map_length]; auto.
inversion X1X . pose proof (nth_in _ n ((map (@vterm p) lvo)) ) as XX.
rewrite map_length in XX. rewrite <- X2X in XX. lapply (XX bd); auto.
intro Hin. apply in_map_iff in Hin. exrepnd.
split; auto.
apply nth_indep; auto.
exists a; auto. sp.
assert (nth n (map vterm lvo) bd =nth n (map vterm lvo) (vterm a)) as XXX by
(apply nth_indep; repeat(rewrite map_length); auto;congruence ).
rewrite XXX in Hin0. rewrite map_nth in Hin0. inversion Hin0. rewrite H2. auto.
Qed.
Definition filt_combine {p} lvi lnt lv := @sub_filter p (combine lvi lnt) lv.
(* instead of var_Ren, we will need swapping *)
Lemma lsubst_aux_nest_same_str {p} :
forall t lvi lvio lnt lf,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint (lvio++(flat_map (@free_vars p) lnt)) (bound_vars t ++ lf)
-> disjoint lvio (free_vars t)
-> lsubst_aux (lsubst_aux t (filt_var_ren lvi lvio lf)) (filt_combine lvio lnt lf)
= lsubst_aux t (filt_combine lvi lnt lf).
Proof.
nterm_ind1s t as [v|f ind|o lbt Hind] Case; auto;
introv Hl1 Hl2 Hnr Hdisb Hdisf.
Focus 2.
Case "oterm". (**this part is easier!!*)
allsimpl. f_equal. rewrite map_map. eapply eq_maps; eauto.
intros bt Hinb. destruct bt as [lv nt].
unfold compose.
allsimpl. apply disjoint_app_r in Hdisb. repnd.
rename Hdisb into Hdisl.
rename Hdisb0 into Hdisb.
eapply disjoint_lbt_bt2 in Hdisb; eauto. repnd.
apply disjoint_app_l in Hdisb0. repnd.
simpl. f_equal.
unfold filt_var_ren. unfold filt_combine.
repeat(rewrite <- sub_filter_app_r).
eapply Hind; eauto 3 with slow;[disjoint_reasoningv|].
rw disjoint_flat_map_r in Hdisf. apply Hdisf in Hinb.
simpl in Hinb. rw <- disjoint_remove_nvars_l in Hinb.
apply remove_nvars_unchanged in Hdisb1.
rewrite Hdisb1 in Hinb. trivial.
Case "vterm".
simpl. destructr (sub_find (@filt_var_ren p lvi lvio lf) v) as [s1st|n1n].
- apply symmetry in HeqHdeq. rename HeqHdeq into s1s.
apply sub_find_sub_filter_some in s1s. repnd.
apply sub_find_first in s1s0. exrepnd.
unfold var_ren in s1s1.
rewrite dom_sub_combine in s1s1;
[| rewrite map_length; congruence] .
unfold var_ren in s1s0.
rewrite length_combine_eq
in s1s0;[| rewrite map_length]; auto.
apply nth_var_ren_implies in s1s2;auto. exrepnd. rename vsr into vio.
simpl. rewrite s1s2. simpl.
destructr (sub_find (filt_combine lvio lnt lf) vio) as [s2st|n2n].
+ apply symmetry in HeqHdeq. rename HeqHdeq into s2s.
apply sub_find_sub_filter_some in s2s. repnd.
apply sub_find_first in s2s0. exrepnd.
unfold var_ren in s2s0. rewrite length_combine_eq
in s2s0;spc.
rw combine_nth in s2s2;spc. inverts s2s2 as s2s3 s2s4.
simpl. rewrite <- Hl1 in s1s0.
(** clear s2s1. it cannot rule out case when n>n0*)
pose proof (no_repeats_index_unique2
_ _ _ _ _ _ Hnr s1s0 s2s0 s1s4 s2s3) as X99.
destruct X99. GC. clear s1s2. clear s1st.
destructr (sub_find (filt_combine lvi lnt lf) v) as [s3st|n3n].
* apply symmetry in HeqHdeq. rename HeqHdeq into s3s.
apply sub_find_sub_filter_some in s3s. repnd.
apply sub_find_first in s3s0. exrepnd.
unfold var_ren in s3s0. rewrite length_combine_eq
in s3s0;spc.
rw combine_nth in s3s2;spc. inverts s3s2 as s3s3 s3s4.
simpl. rewrite Hl1 in s1s0.
allfold (@dom_sub p).
allunfold (@var_ren p). spcls.
assert (n0<n \/ n0=n \/ n<n0) as Htri by omega.
(dorn Htri);[|(dorn Htri)];
try (apply s1s1 in Htri); cpx;
try (apply s3s1 in Htri); cpx.
destruct Htri. GC. apply nth_select3 in s3s4;[| congruence].
apply nth_select3 in s2s4; congruence.
* rename HeqHdeq into n3n. symmetry in n3n.
apply sub_find_sub_filter_none in n3n. dorn n3n; [ |sp(**see s1s*)].
apply sub_find_none2 in n3n.
clear s1s1. apply nth_in2 in s1s3;[| congruence]. allunfold (@var_ren).
simpl. spcls. sp.
+ rename HeqHdeq into n2n. symmetry in n2n.
apply sub_find_sub_filter_none in n2n. dorn n2n.
* apply sub_find_none2 in n2n.
apply nth_in2 in s1s4;[| congruence]. allunfold (@var_ren).
simpl. spcls. sp.
* apply nth_in2 in s1s4;[| congruence].
assert (disjoint lvio lf) as X99 by disjoint_reasoningv.
apply X99 in s1s4; sp.
- apply disjoint_singleton_r in Hdisf. allfold @dom_sub.
assert ((dom_sub (combine lvi lnt)) = lvi) as Xrw by (spcls;sp).
rename HeqHdeq into n1n. symmetry in n1n.
apply sub_find_sub_filter_none in n1n.
assert(sub_find (combine lvi lnt) v = None[+]LIn v lf) as X99.
+ dorn n1n;[left|right]; auto.
apply sub_find_none2 in n1n.
unfold var_ren in n1n. rewrite dom_sub_combine in n1n
;[| rewrite map_length; congruence].
rewrite <- Xrw in n1n. apply sub_find_none_iff in n1n. rewrite n1n.
refl.
+ apply sub_find_sub_filter_none in X99.
unfold filt_combine. rewrite X99.
assert ((dom_sub (combine lvio lnt)) = lvio) as X2rw by (spcls;sp).
rewrite <- X2rw in Hdisf. apply sub_find_none_iff in Hdisf.
simpl.
assert(sub_find (combine lvio lnt) v = None[+]LIn v lf)
as X98 by (left;sp).
apply sub_find_sub_filter_none in X98.
rewrite X98. refl.
Qed.
Lemma lsubst_nest_same_str {p} :
forall t lvi lvio lnt lf,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint (lvio++(flat_map (@free_vars p) lnt)) (bound_vars t ++ lf)
-> disjoint lvio (free_vars t)
-> lsubst (lsubst t (filt_var_ren lvi lvio lf)) (filt_combine lvio lnt lf)
= lsubst t (filt_combine lvi lnt lf).
Proof.
intros. change_to_lsubst_aux4;
try(apply lsubst_aux_nest_same_str;try(sp;fail));
apply disjoint_sym;
rw <- @disjoint_sub_as_flat_map;
try(apply sub_filter_sat).
- rw @disjoint_sub_as_flat_map; spcls; disjoint_reasoningv.
- rw @disjoint_sub_as_flat_map; spcls; disjoint_reasoningv.
- rw <- @lsubst_lsubst_aux; disjoint_reasoningv.
rw @boundvars_lsubst_vars2; spcls; disjoint_reasoningv.
+ rw @disjoint_sub_as_flat_map. spcls. sp.
+ apply allvars_sub_filter.
+ apply sub_filter_sat. rw @disjoint_sub_as_flat_map.
spcls. disjoint_reasoningv.
- rw @disjoint_sub_as_flat_map; spcls; disjoint_reasoningv.
Qed.
Lemma lsubst_nest_vars_same_str {p} :
forall t lvi lvio lvo lf,
length lvio=length lvi
-> length lvio=length lvo
-> no_repeats lvio
-> disjoint (lvio++lvo) (bound_vars t ++ lf)
-> disjoint lvio (free_vars t)
-> lsubst (lsubst t (filt_var_ren lvi lvio lf)) (filt_var_ren lvio lvo lf)
= lsubst t (@filt_var_ren p lvi lvo lf).
Proof.
intros. apply lsubst_nest_same_str;spc; spcls;sp.
Qed.
Lemma lsubst_nest_same {p} :
forall t lvi lvio lnt,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint (lvio++(flat_map (@free_vars p) lnt)) (bound_vars t)
-> disjoint lvio (free_vars t)
-> lsubst (lsubst t (var_ren lvi lvio)) (combine lvio lnt)
= lsubst t (combine lvi lnt).
Proof.
intros.
pose proof (sub_filter_nil_r (@var_ren p lvi lvio)) as K.
rewrite <- K. clear K.
pose proof (sub_filter_nil_r (combine lvio lnt)) as K.
rewrite <- K. clear K.
pose proof (sub_filter_nil_r (combine lvi lnt)) as K.
rewrite <- K. clear K.
apply lsubst_nest_same_str; simpl; auto.
rewrite app_nil_r. auto.
Qed.
Lemma lsubst_aux_nest_same {p} :
forall t lvi lvio lnt,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint (lvio++(flat_map (@free_vars p) lnt)) (bound_vars t)
-> disjoint lvio (free_vars t)
-> lsubst_aux (lsubst_aux t (var_ren lvi lvio)) (combine lvio lnt)
= lsubst_aux t (combine lvi lnt).
Proof.
intros.
pose proof (sub_filter_nil_r (@var_ren p lvi lvio)) as K.
rewrite <- K. clear K.
pose proof (sub_filter_nil_r (combine lvio lnt)) as K.
rewrite <- K. clear K.
pose proof (sub_filter_nil_r (combine lvi lnt)) as K.
rewrite <- K. clear K.
apply lsubst_aux_nest_same_str; simpl; auto.
rewrite app_nil_r. auto.
Qed.
Lemma lsubst_nest_vars_same {p} :
forall t lvi lvio lvo,
length lvio=length lvi
-> length lvio=length lvo
-> no_repeats lvio
-> disjoint (lvio++lvo) (bound_vars t)
-> disjoint lvio (free_vars t)
-> lsubst (lsubst t (var_ren lvi lvio)) (var_ren lvio lvo)
= lsubst t (@var_ren p lvi lvo).
Proof.
intros. apply lsubst_nest_same;spc;spcls;sp.
Qed.
Lemma lsubst_aux_nest_vars_same {p} :
forall t lvi lvio lvo,
length lvio=length lvi
-> length lvio=length lvo
-> no_repeats lvio
-> disjoint (lvio++lvo) (bound_vars t)
-> disjoint lvio (free_vars t)
-> lsubst_aux (lsubst_aux t (var_ren lvi lvio)) (var_ren lvio lvo)
= lsubst_aux t (@var_ren p lvi lvo).
Proof.
intros. apply lsubst_aux_nest_same;spc;spcls;sp.
Qed.
Theorem free_vars_lsubst_aux2 {p} :
forall nt sub,
@disjoint_bv_sub p nt sub
-> forall v,
LIn v (free_vars (lsubst_aux nt sub))
-> (LIn v (free_vars nt) # ! LIn v (dom_sub sub))
[+] {v' : NVar
& {t : NTerm
& LIn (v',t) sub # LIn v' (free_vars nt) # LIn v (free_vars t)}}.
Proof. nterm_ind1 nt as [vn|f ind|o lbt Hind] Case; introv Hdis Hin; auto.
Case "vterm". induction sub as [| (vs,ts) sub].
- rw @lsubst_aux_nil in Hin. left; split; auto. sp.
- destruct (eq_var_dec vn vs) as [? | Hneq];
subst;simpl in Hin;
((rw <- beq_var_refl in Hin;auto)
|| (rw not_eq_beq_var_false in Hin;auto)).
+ right. exists vs ts. sp; auto.
+ cases (sub_find sub vn) as Hf.
* applydup @sub_find_some in Hf.
right; exists vn n; split; auto. right;auto. simpl. split; auto.
* left;split;auto. allsimpl;subst. introv Hc. dorn Hc; subst; sp.
subst. apply sub_find_none2 in Hf. sp.
- Case "sterm".
allsimpl; tcsp.
- Case "oterm".
simpl in Hin. rw lin_flat_map in Hin.
destruct Hin as [bt' Hin]. repnd. apply in_map_iff in Hin0.
destruct Hin0 as [bt Hin0]. repnd. subst. destruct bt as [lv nt].
simpl in Hin.
simpl in Hin. rw in_remove_nvars in Hin. repnd.
apply Hind with (lv:=lv) in Hin0; auto.
destruct Hin0 as [Hl | Hr].
+ left. simpl. repnd. split.
* apply lin_flat_map. eexists; split; eauto. simpl.
apply in_remove_nvars. split; auto.
* introv Hc. apply Hl.
rewrite <- dom_sub_sub_filter.
apply in_remove_nvars. sp.
+ right. parallel vs Hr. parallel ts Hr. repnd. sp;auto.
* rw @in_sub_filter in Hr0. repnd; auto.
* simpl. apply lin_flat_map. eexists; split; eauto. simpl.
apply in_remove_nvars. split; auto. rw @in_sub_filter in Hr0.
repnd; auto.
+ eapply disjoint_bv_sub_ot in Hdis; eauto.
Qed.
Theorem free_vars_lsubst2 {p} :
forall nt sub,
@disjoint_bv_sub p nt sub
-> forall v,
LIn v (free_vars (lsubst nt sub))
-> (LIn v (free_vars nt) # ! LIn v (dom_sub sub))
[+] {v' : NVar
& {t : NTerm
& LIn (v',t) sub # LIn v' (free_vars nt) # LIn v (free_vars t)}}.
Proof.
introns Hd. change_to_lsubst_aux4.
apply free_vars_lsubst_aux2;try(sp;fail);
try(apply disjoint_sub_as_flat_map;disjoint_reasoning).
- rw @disjoint_sub_as_flat_map. disjoint_reasoningv.
- rw <- @lsubst_lsubst_aux;sp; disjoint_reasoning.
Qed.
Lemma subst_mk_false {p} :
forall v t,
! LIn nvarx (free_vars t)
-> (subst mk_false v t = @mk_false p).
Proof.
unfold subst. unfold lsubst. introv Hin.
change_to_lsubst_aux4; simpl; disjoint_reasoningv;sp.
allsimpl. rw memvar_dmemvar. clear d.
cases_ifn Hmem;
rw in_single_iff in Hmem;simpl;sp.
rw beq_deq. cases_if; sp.
Qed.
Lemma covered_cequiv {p} :
forall a b vs,
covered (@mk_cequiv p a b) vs
<=> covered a vs
# covered b vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_approx {p} :
forall a b vs,
covered (@mk_approx p a b) vs
<=> covered a vs
# covered b vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_fix {p} :
forall f s, covered (@mk_fix p f) s <=> covered f s.
Proof.
unfold mk_fix, covered; intros; simpl.
rw remove_nvars_nil_l; rw app_nil_r; sp.
Qed.
Lemma covered_id {p} :
forall s, @covered p mk_id s.
Proof.
unfold mk_id, covered; simpl; sp.
Qed.
Hint Immediate covered_id.
Lemma covered_bot {p} :
forall s, @covered p mk_bot s.
Proof.
unfold mk_bot, mk_bottom.
intro; rw @covered_fix; sp.
Qed.
Hint Immediate covered_bot.
Lemma covered_mk_false {p} :
forall s, @covered p mk_false s.
Proof.
intro; rw @covered_approx; sp.
Qed.
Hint Immediate covered_mk_false.
Lemma covered_top {p} :
forall s, @covered p mk_top s.
Proof.
intro; rw @covered_isect; sp.
Qed.
Hint Immediate covered_top.
Lemma covered_lam {p} :
forall v b vs,
covered (@mk_lam p v b) vs
<=> covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma lsubst_lsubst_aux2 {p} : forall t lvi lvo,
disjoint (bound_vars t) (lvo)
-> length lvi = length lvo
-> lsubst t (var_ren lvi lvo) = lsubst_aux t (@var_ren p lvi lvo).
Proof.
introv Hdis Hlen. unfold lsubst. rw @flat_map_free_var_vars_range;sp.
cases_if; sp.
Qed.
Lemma sub_mk_renames2_length2 {p} : forall lva1 lva2 lv lsr ssr,
(lsr, ssr) = @sub_mk_renames2 p lv lva1 lva2
-> length lsr = length lv.
Proof.
introv HH. pose proof (@sub_mk_renames2_length p lv lva1 lva2) as XX.
rw <- HH in XX. sp.
Qed.
Lemma cover_vars_dom_csub_eq {p} :
forall t s1 s2,
cover_vars t s1
-> dom_csub s1 = @dom_csub p s2
-> cover_vars t s2.
Proof.
introv cv eq.
allrw @cover_vars_eq.
rw <- eq; sp.
Qed.
(*
Lemma cover_vars_esquash :
forall T sub,
cover_vars (mk_esquash T) sub <=> cover_vars T sub.
Proof.
sp; repeat (rw cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
*)
Lemma cover_vars_apply2 {p} :
forall a b c sub,
cover_vars (@mk_apply2 p a b c) sub
<=> cover_vars a sub
# cover_vars b sub
# cover_vars c sub.
Proof.
sp; repeat (rw cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
repeat (rw app_nil_r).
repeat (rw subvars_app_l); sp; split; sp.
Qed.
Definition subst_axiom {p} (lv : list NVar) : @Substitution p :=
map (fun v => (v,mk_axiom)) lv.
Definition csubst_axiom {p} (lv : list NVar) : @CSub p :=
map (fun v => (v,mkc_axiom)) lv.
Hint Resolve isprogram_axiom.
Lemma prog_subst_axiom {p} : forall lv,
prog_sub (@subst_axiom p lv).
Proof.
introv Hin.
rw in_map_iff in Hin.
exrepnd. inverts Hin0.
eauto.
Qed.
Hint Resolve prog_subst_axiom.
Lemma close_with_axiom {p} : forall t,
nt_wf t
-> let sub := @subst_axiom p (free_vars t) in
(prog_sub sub) # (isprogram (lsubst t sub)).
Proof.
introv Hnt. pose proof (@prog_subst_axiom p (free_vars t)) as Hpr.
simpl. split; auto;[].
apply isprogram_lsubst;try(sp;fail).
introv Hin. apply in_map_iff. exists (v, @mk_axiom p). split; auto.
unfold subst_axiom. apply in_map_iff. eexists;eauto.
Qed.
Ltac dlmap_find sn :=
match goal with
| [ |- context[lmap_find deq_nvar ?s ?v]] =>
let sns := fresh sn "s" in
remember (lmap_find deq_nvar s v) as sn;
destruct sn as [sns |]
| [ H:context[lmap_find deq_nvar ?s ?v] |- _ ] =>
let sns := fresh sn "s" in
remember (lmap_find deq_nvar s v) as sn;
destruct sn as [sns |]
end.
Ltac dsub_find2 sn :=
match goal with
| [ |- context[sub_find ?s ?v]] =>
let sns := fresh sn "s" in
remember (sub_find s v) as sn;
let H := get_last_hyp tt in
let H' := fresh H "l" in
(destruct sn as [sns |];
symmetry in H;
try (pose proof (sub_find_some _ _ _ H) as H');
try (pose proof (sub_find_none2 _ _ H) as H'))
| [ H: context[sub_find ?s ?v] |- _ ] =>
let sns := fresh sn "s" in
remember (sub_find s v) as sn;
destruct sn as [sns |]
end.
Lemma prog_lsubst_aux_app {p} : forall nt sub sub2,
disjoint (free_vars (lsubst_aux nt sub)) (@dom_sub p sub2)
-> disjoint_bv_sub nt sub
-> prog_sub sub2
-> lsubst_aux nt sub = lsubst_aux nt (sub++sub2).
Proof.
nterm_ind1 nt as [v|f ind|o lbt Hind] Case. introv; auto.
- Case "vterm".
simpl. dsub_find2 sv.
symmetry in Heqsv.
+ rw @sub_find_app. rw <- Heqsv;sp.
+ simpl. introv Hdis Hdbv Hprog. disjoint_reasoningv.
dsub_find sa;sp. applysym @sub_find_some in
Heqsa. apply in_dom_sub in Heqsa;sp.
rw @dom_sub_app in Heqsa.
rw in_app_iff in Heqsa.
cpx.
- Case "sterm".
simpl; sp.
- Case "oterm".
introv Hpr Hbv Hps. simpl. f_equal. apply eq_maps.
intros bt Hin. destruct bt as [blv bnt].
simpl. f_equal. rw @sub_filter_app.
Hint Resolve sub_filter_sat.
eapply Hind; allunfold @prog_sub; allunfold @disjoint_bv_sub; eauto.
+ allsimpl.
apply lin_lift with (f:=fun t : BTerm => lsubst_bterm_aux t sub) in Hin.
eapply disjoint_flat_map_l in Hpr; eauto;[].
allsimpl. apply disjoint_remove_nvars_l in Hpr.
rw @dom_sub_sub_filter in Hpr. sp.
+ apply sub_filter_sat. sp.
eapply sub_range_sat_implies; eauto.
introv Hdis. allsimpl.
eapply disjoint_flat_map_r in Hdis; eauto.
allsimpl. disjoint_reasoningv.
Qed.
Lemma range_app {p} : forall s1 s2, @range p (s1++s2) =
(range s1) ++ (range s2).
Proof.
introv. unfold range. rw map_app.
sp.
Qed.
Lemma sub_keep_first_sat {p} : forall P sub lv,
@sub_range_sat p sub P
-> sub_range_sat (sub_keep_first sub lv) P.
Proof. introv Hall hsub. apply in_sub_keep_first in hsub. repnd.
apply sub_find_some in hsub0. apply Hall in hsub0; auto.
Qed.
Theorem sub_keep_first_nest {p} :
forall sub vs1 vs2,
(forall v, LIn v vs2 -> LIn v vs1 [+] ! LIn v (@dom_sub p sub))
-> sub_keep_first (sub_keep_first sub vs1) vs2 =sub_keep_first sub vs2.
Proof.
induction sub as [| (hv,ht) sub Hind]; introv Hin; [reflexivity | allsimpl].
simpl. allrw memvar_dmemvar.
cases_ifd h1v; simpl; repeat (rw memvar_dmemvar); cases_ifd h2v;
repeat (rw memvar_dmemvar); try(cases_ifd h3v);cpx.
- f_equal. rw Hind;try(spc;fail). introv H2in.
allrw in_remove_nvars. repnd. apply Hin in H2in0.
dorn H2in0;[left;split|right];cpx.
- rw Hind;try(spc;fail). introv H2in.
allrw in_remove_nvars. repnd. applydup Hin in H2in.
dorn H2in0;[left;split|right];cpx;[].
simpl. introv Hc; dorn Hc; subst; sp.
- provefalse. apply Hin in h2vt. dorn h2vt;sp.
- rw Hind;try(spc;fail). introv H2in.
allrw in_remove_nvars. repnd. applydup Hin in H2in.
dorn H2in0;[left|right];cpx.
Qed.
(** w/o the hypothesis, this does not hold for lsubst
might occur only in RHS. if it happens in both,
the new variables might be different as
RHS has to avoid more variables.
w/o hypothesis, we can prove alpha equality *)
Lemma lsubst_aux_trim {p} :
forall t sub,
(forall v u, LIn (v, u) sub -> disjoint (@free_vars p u) (bound_vars t))
-> lsubst_aux t sub = lsubst_aux t (sub_keep_first sub (free_vars t)).
Proof.
nterm_ind1 t as [v|f ind|o lbt Hind] Case; introv Hdis; auto.
- Case "vterm". simpl.
dsub_find2 ds.
+ apply sub_keep_first_singleton_r_some in Heqds.
rw Heqds. simpl. rw beq_deq. cases_if; sp.
+ apply sub_keep_first_singleton_r_none in Heqds.
rw Heqds; sp.
- Case "oterm". simpl. f_equal.
apply eq_maps. intros bt Hin.
destruct bt as [lv nt].
simpl.
f_equal.
rw <- @sub_keep_first_sub_filter.
symmetry.
rewrite Hind with (lv := lv); eauto;
[ |
apply sub_keep_first_sat;
apply sub_filter_sat;
disjoint_flat; sp;fail].
assert( (sub_keep_first (sub_keep_first (sub_filter sub lv)
(flat_map free_vars_bterm lbt)) (free_vars nt)) =
sub_keep_first (sub_filter sub lv) (free_vars nt)) as Hskeq.
+ apply sub_keep_first_nest. introv Hinf. destruct (in_nvar_list_dec v lv).
* right. rw <- @dom_sub_sub_filter. intro HC. apply in_remove_nvars in HC. sp.
* left. apply lin_flat_map. eexists; split; eauto.
simpl. apply in_remove_nvars; split; trivial.
+ rw Hskeq.
symmetry. eapply Hind; eauto.
apply sub_filter_sat. disjoint_flat. disjoint_reasoning.
Qed.
Lemma in_sub_keep_first_app {p} :
forall lv1 lv2 sub v u,
LIn (v,u) (@sub_keep_first p sub (lv1++lv2))
-> LIn (v,u) (sub_keep_first sub lv1) [+]
LIn (v,u) (sub_keep_first sub lv2).
Proof. introv Hin.
apply in_sub_keep_first in Hin.
repnd.
apply in_app_iff in Hin. dorn Hin;[left|right];
apply in_sub_keep_first;sp.
Qed.
Ltac lsubst_lsubst_aux_eq H :=
match goal with
| [ |- context[lsubst ?t ?sub]] =>
assert (lsubst t sub = lsubst_aux t sub) as H;
[change_to_lsubst_aux4; sp ;fail | rw H]
end.
Ltac lsubst_lsubst_aux_eq_hyp H Hyp :=
let T := type of Hyp in
match T with
| context[lsubst ?t ?sub] =>
assert (lsubst t sub = lsubst_aux t sub) as H;
[change_to_lsubst_aux4; sp | rewrite H in Hyp ]
end.
Lemma disjoint_sym_eauto: forall (T : [univ]) (l1 l2 : list T),
disjoint l1 l2 -> disjoint l2 l1.
Proof.
introv. apply disjoint_sym; auto.
Qed.
Fixpoint sub_range_rel {p} (R : bin_rel NTerm) (subl subr : @Sub p) : [univ] :=
match (subl, subr) with
| ([],[]) => True
| ((vl,tl) :: sl , (vr,tr) :: sr) => (vl=vr # R tl tr # sub_range_rel R sl sr)
| ( _ , _) => False
end.
Lemma sub_range_rel_app {p} : forall R subl1 subl2 subr1 subr2,
(@sub_range_rel p R subl1 subl2 # sub_range_rel R subr1 subr2)
-> sub_range_rel R (subl1 ++ subr1) (subl2 ++ subr2).
Proof.
induction subl1 as [|(v1,t1) subl1 Hind]; introv Hsr;
destruct subl2 as [|(v2,t2) subl2]; inverts Hsr; allsimpl;sp.
Qed.
Lemma sub_range_refl {p} : forall R,
refl_rel R -> refl_rel (@sub_range_rel p R).
Proof.
introv Hr. unfold refl_rel in Hr. unfold refl_rel.
induction x as [|(v1,t1) subl1 Hind]; allsimpl;sp.
Qed.
Lemma sub_range_sat_nil {p} : forall P, @sub_range_sat p [] P.
Proof.
unfold sub_range_sat. introv HH.
inverts HH.
Qed.
Hint Resolve disjoint_sym_eauto disjoint_flat_map_r : slow.
Lemma cover_vars_upto_lam {p} :
forall vs v b sub,
@cover_vars_upto p (mk_lam v b) sub vs
<=> cover_vars_upto b (csub_filter sub [v]) (v :: vs).
Proof.
introv.
unfold cover_vars_upto; simpl.
rw app_nil_r.
rw subvars_remove_nvars.
rw @dom_csub_csub_filter.
allrw subvars_prop; simpl; split; sp.
apply_in_hyp pp; allrw in_app_iff; allrw in_single_iff; sp.
rw in_remove_nvars; rw in_single_iff.
generalize (deq_nvar v x); intro o; sp.
right; right; sp.
apply_in_hyp pp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
Qed.
Lemma cover_vars_upto_isect {p} :
forall vs a v b sub,
@cover_vars_upto p (mk_isect a v b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b (csub_filter sub [v]) (v :: vs).
Proof.
sp; repeat (rw cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
allrw subvars_prop; simpl; split; sp; apply_in_hyp pp;
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
generalize (deq_nvar v x); intro o; sp.
right; right; sp.
Qed.
Lemma cover_vars_upto_eisect {p} :
forall vs a v b sub,
@cover_vars_upto p (mk_eisect a v b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b (csub_filter sub [v]) (v :: vs).
Proof.
sp; repeat (rw cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
allrw subvars_prop; simpl; split; sp; apply_in_hyp pp;
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
generalize (deq_nvar v x); intro o; sp.
right; right; sp.
Qed.
Lemma cover_vars_upto_disect {p} :
forall vs a v b sub,
@cover_vars_upto p (mk_disect a v b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b (csub_filter sub [v]) (v :: vs).
Proof.
sp; repeat (rw cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
allrw subvars_prop; simpl; split; sp; apply_in_hyp pp;
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
generalize (deq_nvar v x); intro o; sp.
right; right; sp.
Qed.
Lemma cover_vars_upto_set {p} :
forall vs a v b sub,
@cover_vars_upto p (mk_set a v b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b (csub_filter sub [v]) (v :: vs).
Proof.
sp; repeat (rw cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
allrw subvars_prop; simpl; split; sp; apply_in_hyp pp;
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
generalize (deq_nvar v x); intro o; sp.
right; right; sp.
Qed.
Lemma cover_vars_upto_tunion {p} :
forall vs a v b sub,
@cover_vars_upto p (mk_tunion a v b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b (csub_filter sub [v]) (v :: vs).
Proof.
sp; repeat (rw cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
allrw subvars_prop; simpl; split; sp; apply_in_hyp pp;
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
generalize (deq_nvar v x); intro o; sp.
right; right; sp.
Qed.
Lemma cover_vars_upto_quotient {p} :
forall vs a v1 v2 b sub,
@cover_vars_upto p (mk_quotient a v1 v2 b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b (csub_filter sub [v1,v2]) (v1 :: v2 :: vs).
Proof.
sp; repeat (rw cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
allrw subvars_prop; simpl; split; sp; apply_in_hyp pp;
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp;
generalize (deq_nvar v1 x); generalize (deq_nvar v2 x); intro o; sp;
right; right; right; allsimpl; sp.
Qed.
Lemma cover_vars_upto_base {p} :
forall vs sub,
@cover_vars_upto p mk_base sub vs.
Proof.
unfold cover_vars_upto; sp.
Qed.
Hint Immediate cover_vars_upto_base.
Lemma cover_vars_upto_base_iff {p} :
forall vs sub,
@cover_vars_upto p mk_base sub vs <=> True.
Proof.
intros; split; sp.
Qed.
Lemma cover_vars_upto_free_from_atom {p} :
forall vs a b c sub,
@cover_vars_upto p (mk_free_from_atom a b c) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b sub vs
# cover_vars_upto c sub vs.
Proof.
intros; unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
Qed.
Lemma cover_vars_upto_free_from_atoms {p} :
forall vs a b sub,
@cover_vars_upto p (mk_free_from_atoms a b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b sub vs.
Proof.
intros; unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
Qed.
Lemma cover_vars_upto_equality {p} :
forall vs a b T sub,
@cover_vars_upto p (mk_equality a b T) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b sub vs
# cover_vars_upto T sub vs.
Proof.
intros; unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
Qed.
Lemma cover_vars_upto_tequality {p} :
forall vs a b sub,
@cover_vars_upto p (mk_tequality a b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b sub vs.
Proof.
intros; unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
Qed.
Lemma cover_vars_upto_apply {p} :
forall vs a b sub,
@cover_vars_upto p (mk_apply a b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b sub vs.
Proof.
intros; unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
Qed.
Lemma cover_vars_upto_var {p} :
forall vs v sub,
@cover_vars_upto p (mk_var v) sub vs
<=> LIn v (vs ++ dom_csub sub).
Proof.
intros; unfold cover_vars_upto; simpl.
rw subvars_singleton_l; sp.
Qed.
Lemma cover_vars_upto_csub_filter_disjoint {p} :
forall t s vs1 vs2,
eqvars vs1 vs2
-> disjoint (free_vars t) vs1
-> (cover_vars_upto t (@csub_filter p s vs1) vs2
<=> cover_vars t s).
Proof.
introv eqv disj.
unfold cover_vars_upto.
rw @cover_vars_eq.
allrw subvars_prop; split; sp; allrw in_app_iff;
allrw @dom_csub_csub_filter; allrw in_remove_nvars.
applydup X in X0; allrw in_app_iff; sp.
apply disj in X0.
allrw eqvars_prop.
apply eqv in l; sp.
allrw in_remove_nvars; sp.
applydup X in X0.
apply disj in X0; sp.
Qed.
Lemma le_sub_range_rel {p} : forall R1 R2, le_bin_rel R1 R2
-> le_bin_rel (@sub_range_rel p R1) (sub_range_rel R2).
Proof.
introv Hl. unfold le_bin_rel; induction a as [| (va,ta) suba Hind];
intros subb Hs1; destruct subb as [| (vb,tb) subb]; simpl; invertsn Hs1;
auto;[]; repnud Hl; dands; auto.
Qed.
Lemma le_binrel_sub_un {p} : forall R Rul Rur,
le_bin_rel R (indep_bin_rel Rul Rur)
-> le_bin_rel (@sub_range_rel p R)
(indep_bin_rel (fun s => sub_range_sat s Rul) (fun s => sub_range_sat s Rur)).
Proof.
introv Hle.
unfold le_bin_rel, indep_bin_rel; induction a as [| (va,ta) suba Hind];
intros subb Hs1; destruct subb as [| (vb,tb) subb]; dands; dands;
introv Hin; try(invertsn Hin); repnud Hle; allsimpl;
unfold indep_bin_rel in Hle;cpx; subst;
try(apply Hle in r); repnd; auto;
apply Hind in Hs1;
repnd;allunfold @sub_range_sat; eauto.
Qed.
Lemma isprogram_lsubst3 {p} :
forall t : NTerm,
forall sub : @Substitution p,
isprogram t
-> prog_sub sub
-> isprogram (lsubst t sub).
Proof.
introv Hpr Hps.
apply isprogram_lsubst; eauto with slow;[].
repnud Hpr.
rw Hpr0.
introv Hin; inverts Hin.
Qed.
Lemma sub_filter_pair_dom {p} : forall lvf R lvi lnta lntb,
length lvi = length lnta
-> length lvi = length lntb
-> bin_rel_nterm R lnta lntb
-> {lvi' : list NVar $ { lnta', lntb' : list (@NTerm p) $ sub_filter (combine lvi lnta) lvf = combine lvi' lnta'
# sub_filter (combine lvi lntb) lvf = combine lvi' lntb'
# length lvi' = length lnta'
# length lvi' = length lntb'
# bin_rel_nterm R lnta' lntb'
(** pairwise relationships are preserved *)
} }.
Proof.
induction lvi as [| v lvi Hind]; introns Hl.
- repeat (eapply existT with (x:=nil)). dands; spc. apply binrel_list_nil.
- simpl. destruct lnta as [|ha lnta];invertsn Hl;
destruct lntb as [| hb lntb];invertsn Hl0; allsimpl.
rw memvar_dmemvar. rw memvar_dmemvar.
apply binrel_list_cons in Hl1. repnd. duplicate Hl0.
cases_ifd Ha; eapply Hind with (lnta := lnta) in Hl0 ; eauto;[].
exrepnd. exists (v::lvi') (ha :: lnta') (hb :: lntb').
allsimpl. dands; spc; try (f_equal;spc).
apply binrel_list_cons; sp.
Qed.
Lemma lsubst_bterm_trivial {p} : forall bt sub,
isprogram_bt bt
-> @prog_sub p sub
-> lsubst_bterm_aux bt sub = bt.
Proof.
introv Hpr Hps.
destruct bt as [lv nt].
simpl. f_equal.
rw @lsubst_aux_trivial. sp.
introv Hin.
apply in_sub_filter in Hin.
repnd.
apply Hps in Hin0.
split; auto;[].
repnud Hpr.
invertsn Hpr0.
rw nil_remove_nvars_iff in Hpr0.
spc.
Qed.
Ltac disjoint_flat3 := allunfold disjoint_bv_sub; allunfold sub_range_sat; allsimpl;
match goal with
|[ H: (LIn (_,?t) ?sub), H2 : (disjoint (flat_map ?f (range ?sub)) ?l) |- disjoint (?f ?t) ?l ] =>
exact ((snd (disjoint_sub_as_flat_map _ _ _) H2 _ _ H))
|[ H: (LIn (_,?t) ?sub), H2 : (disjoint ?l (flat_map ?f (range ?sub))) |- disjoint (?f ?t) ?l ] =>
exact ((snd (disjoint_sub_as_flat_map _ _ _)
(disjoint_sym_impl _ _ _ H2) _ _ H))
|[ H: (LIn _ ?tl), H2 : (disjoint _ (flat_map _ ?tl)) |- _ ] =>
apply ((tiff_fst (disjoint_flat_map_r _ _ _ _ _)) H2) in H; hide_hyp H
|[ H: (LIn _ ?tl), H2 : (disjoint (flat_map _ ?tl) _) |- _ ] =>
apply ((tiff_fst (disjoint_flat_map_l _ _ _ _ _)) H2) in H; hide_hyp H
| [ H:( forall _ _, LIn (_, _) _
-> disjoint (free_vars _) _) |- _ ] =>
apply disjoint_sub_as_flat_map in H
| [ |- ( forall _ _, LIn (_, _) _
-> disjoint (free_vars _) _) ] =>
apply disjoint_sub_as_flat_map
end.
Ltac fold_lsubst_ot :=
match goal with
[ |- context [ (oterm ?o (map (fun _ : BTerm => lsubst_bterm_aux _ ?sub) ?lbt))]]
=> let Hf := fresh "xxx" in
let ts := eval simpl in (lsubst_aux (oterm o lbt) sub) in
assert (ts = lsubst_aux (oterm o lbt) sub) as Hf by refl;
rewrite Hf; clear Hf
end.
Ltac prove_sub_range_sat :=
let Hin := fresh "Hin" in
introv Hin; simpl in Hin;
repeat(dorn Hin;auto); try(inverts Hin); subst;auto.
Ltac lsubst_aux_ot_eq Hyp := let T := type of Hyp in
let Hf := fresh Hyp "lseq" in
match T with
context [ lsubst_aux (oterm ?o ?lbt) ?sub] =>
let ts := eval simpl in (lsubst_aux (oterm o lbt) sub) in
assert (ts = lsubst_aux (oterm o lbt) sub) as Hf by refl
end.
Lemma lsubst_app_swap {p} : forall t sub1 sub2,
prog_sub sub1
-> @prog_sub p sub2
-> disjoint (dom_sub sub1) (dom_sub sub2)
-> lsubst t (sub1++sub2) = lsubst t (sub2++sub1).
Proof.
introv H1p H2p Hdis.
pose proof (sub_app_sat _ _ _ H1p H2p).
pose proof (sub_app_sat _ _ _ H2p H1p).
change_to_lsubst_aux4;[].
pose proof (lsubst_aux_shift t sub1 sub2 []).
simpl_vlist.
eauto.
Qed.
Lemma lsubst_lsubst_aux_prog_sub {p} : forall t sub,
@prog_sub p sub
-> lsubst t sub = lsubst_aux t sub.
Proof.
introv Hpr. change_to_lsubst_aux4. sp.
Qed.
Ltac fold_lsubst_subh Hyp := let T := type of Hyp in
match T with
| [(?v1 ,lsubst ?t1 ?sub)] => fold (lsubst_sub [v1,t1] sub)
end.
Ltac fold_lsubst_sub :=
match goal with
| [ |- context [ [(?v1 ,lsubst ?t1 ?sub), (?v2 ,lsubst ?t2 ?sub)] ] ] => fold (lsubst_sub [(v1,t1),(v2,t2)] sub)
| [ |- context [ [(?v1 ,lsubst ?t1 ?sub)] ] ] => fold (lsubst_sub [(v1,t1)] sub)
end.
Lemma lsubst_bterm_aux_trim {p} : forall lvf o lbt,
disjoint (free_vars (@oterm p o lbt)) lvf
-> forall sub bt,
LIn bt lbt
-> lsubst_bterm_aux bt sub = lsubst_bterm_aux bt (sub_filter sub lvf).
Proof.
introv Hdis Hin.
destruct bt as [lv nt].
simpl. f_equal.
rw @sub_filter_swap.
rw <- @sub_filter_app_r.
rw @sub_filter_app_as_remove_nvars.
rw @sub_filter_app_r.
rewrite <- lsubst_aux_sub_filter with (l:= (remove_nvars lv lvf));sp.
simpl in Hdis. eapply disjoint_flat_map_l in Hdis;eauto.
allsimpl. apply disjoint_remove_nvars_l in Hdis;sp.
Qed.
Lemma lsubst_bterm_aux_trivial {p} : forall bt,
@lsubst_bterm_aux p bt [] = bt.
Proof.
introv. destruct bt.
simpl. f_equal.
apply lsubst_aux_nil.
Qed.
Lemma closed_sub {p} :
forall sub,
(forall v t, LIn (v, t) sub -> @isprogram p t)
-> flat_map free_vars (range sub) = [].
Proof.
induction sub; allsimpl; sp.
generalize (X a0 a); sp.
rw IHsub; allsimpl; sp.
allunfold @isprogram; allunfold @closed; sp; allrw; sp.
generalize (X v t); sp.
Qed.
Lemma disjoint_sub_if_program {p} :
forall sub,
(forall (v : NVar) (t : @NTerm p),
LIn (v, t) sub -> isprogram t)
-> forall t, disjoint (@bound_vars p t) (flat_map free_vars (range sub)).
Proof.
intros.
generalize (closed_sub sub); sp.
rw H; sp.
Qed.
Lemma lsubst_lsubst_aux_prog {p} :
forall t sub,
(forall v t, LIn (v, t) sub -> @isprogram p t)
-> lsubst t sub = lsubst_aux t sub.
Proof.
intros.
apply lsubst_lsubst_aux.
apply disjoint_sub_if_program; sp.
Qed.
Lemma cover_vars_cvterm2 {p} :
forall v1 v2 t u1 u2,
cover_vars (@get_cvterm p [v1,v2] t) [(v1, u1), (v2, u2)].
Proof.
destruct t; sp; simpl.
rw (@isprog_vars_eq p) in i; sp.
Qed.
Lemma cover_vars_cvterm3 {p} :
forall v1 v2 v3 t u1 u2 u3,
cover_vars (@get_cvterm p [v1,v2,v3] t) [(v1, u1), (v2, u2), (v3, u3)].
Proof.
destruct t; sp; simpl.
rw @isprog_vars_eq in i; sp.
Qed.
Definition lsubstc2 {p}
(v1 : NVar) (u1 : @CTerm p)
(v2 : NVar) (u2 : CTerm)
(t : CVTerm [v1;v2]) :=
lsubstc (get_cvterm [v1;v2] t)
(wf_cvterm [v1;v2] t)
[(v1,u1),(v2,u2)]
(cover_vars_cvterm2 v1 v2 t u1 u2).
Definition lsubstc3 {p}
(v1 : NVar) (u1 : @CTerm p)
(v2 : NVar) (u2 : CTerm)
(v3 : NVar) (u3 : CTerm)
(t : CVTerm [v1;v2;v3]) :=
lsubstc (get_cvterm [v1;v2;v3] t)
(wf_cvterm [v1;v2;v3] t)
[(v1,u1),(v2,u2),(v3,u3)]
(cover_vars_cvterm3 v1 v2 v3 t u1 u2 u3).
Lemma substc_cnewvar {p} :
forall a t,
substc a (@cnewvar p t) (mk_cv [cnewvar t] t) = t.
Proof.
introv; destruct_cterms.
apply cterm_eq; simpl.
unfold cnewvar; simpl.
apply lsubst_trivial; simpl; sp; cpx.
rw @isprogram_eq; sp.
allapply @newvar_prop; sp.
Qed.
Lemma cover_vars_weak {p} :
forall u s1 s2 v t,
@cover_vars p u (s1 ++ s2)
-> cover_vars u (snoc s1 (v, t) ++ s2).
Proof.
introv cv.
allrw @cover_vars_eq.
allrw @dom_csub_app.
allrw @dom_csub_snoc; allsimpl.
allrw subvars_prop; introv nih.
generalize (cv x); intro nia.
dest_imp nia hyp.
allrw in_app_iff; allrw in_snoc; sp.
Qed.
Lemma cover_vars_add {p} :
forall u s1 s2 v t,
!LIn v (@free_vars p u)
-> cover_vars u (snoc s1 (v, t) ++ s2)
-> cover_vars u (s1 ++ s2).
Proof.
introv nivh cv.
allrw @cover_vars_eq.
allrw @dom_csub_app.
allrw @dom_csub_snoc; allsimpl.
allrw subvars_prop; introv nih.
generalize (cv x); intro nia.
dest_imp nia hyp.
allrw in_app_iff; allrw in_snoc; sp; subst; sp.
Qed.
Lemma csubst_swap_app {p} :
forall t sub1 sub2,
disjoint (dom_csub sub1) (@dom_csub p sub2)
-> csubst t (sub1 ++ sub2) = csubst t (sub2 ++ sub1).
Proof.
introv disj.
generalize (csubst_shift t sub1 sub2 []); allrw app_nil_r; sp.
Qed.
Lemma fold_subst {p} :
forall t v u, @lsubst p t [(v,u)] = subst t v u.
Proof. auto. Qed.
Lemma simple_lsubst_cons {p} :
forall t v u sub,
isprogram u
-> (forall v u, LIn (v, u) sub -> @isprogram p u)
-> lsubst (subst t v u) sub = lsubst t ((v, u) :: sub).
Proof.
intros.
unfold subst.
rw @simple_lsubst_app; simpl; sp; cpx.
Qed.
Definition map_sub_range {p} (f : NTerm -> @NTerm p) (sub : @Substitution p) :=
map (fun p => (fst p, f (snd p))) sub.
Lemma dom_sub_map_range {p} : forall f sub,
dom_sub (@map_sub_range p f sub) = dom_sub sub.
Proof.
induction sub; auto.
simpl. f_equal. auto.
Qed.
Lemma sub_range_sat_cons {p} : forall h t P,
@sub_range_sat p (h::t) P <=> (P (snd h) # sub_range_sat t P).
Proof.
intros. rw cons_as_app. rw <- @sub_app_sat_iff.
split; introv HH; repnd; dands; allunfold @sub_range_sat; allsimpl; eauto;[].
introv Hin; in_reasoning. cpx. cpx.
Qed.
Ltac simpl_sub5 :=
(match goal with
| [ H : (prog_sub _) |- _ ] => (allrewrite (prog_sub_flatmap_range _ H))
| [ H : isprogram _ |- _ ] => allrewrite (fst (H))
| [ H : (forall _ _, LIn (_, _) _ -> isprogram _) |- _ ] => (allrewrite (prog_sub_flatmap_range _ H))
| [ H : context[dom_sub (combine _ _)] |- _] => rewrite dom_sub_combine in H;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ |- context[dom_sub (combine _ _)] ] => rewrite dom_sub_combine;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ H : context[range (combine _ _)] |- _] => rewrite dom_range_combine in H;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ |- context[range (combine _ _)] ] => rewrite dom_range_combine;[|try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ H : context[range (var_ren _ _)] |- _] => unfold var_ren in H
| [ |- context[range (var_ren _ _)] ] => unfold var_ren
| [ H : context[dom_sub (var_ren _ _)] |- _] => unfold var_ren in H
| [ |- context[dom_sub (var_ren _ _)] ] => unfold var_ren
| [ H : context[flat_map free_vars (map vterm _)] |- _] => rewrite flat_map_free_var_vterm in H
| [ |- context[flat_map free_vars (map vterm _)] ] => rewrite flat_map_free_var_vterm
| [ H : context[flat_map bound_vars (map vterm _)] |- _] => rewrite flat_map_bound_var_vterm in H
| [ |- context[flat_map bound_vars (map vterm _)] ] => rewrite flat_map_bound_var_vterm
end).
Lemma lsubst_nest_progs_swap {p} :
forall (t : NTerm) (sub1 sub2 : @Substitution p),
prog_sub sub1 ->
prog_sub sub2 ->
disjoint (dom_sub sub1) (dom_sub sub2) ->
(lsubst (lsubst t sub1) sub2) = (lsubst (lsubst t sub2) sub1).
Proof.
introv H1p H2p Hdis.
change_to_lsubst_aux4.
apply lsubst_aux_nest_swap2; spcls; repeat(simpl_sub5); auto;
rewrite (prog_sub_flatmap_range _ H1p); spcls; auto.
Qed.
Lemma lsubst_nest_progs_swap_single {p} :
forall (t st: @NTerm p) (sub : Substitution) (v: NVar),
prog_sub sub ->
isprogram st ->
disjoint (dom_sub sub) [v] ->
(lsubst (lsubst t sub) [(v,st)]) = (lsubst (lsubst t [(v,st)]) sub).
Proof.
intros. apply lsubst_nest_progs_swap; auto.
prove_sub_range_sat.
Qed.
Ltac fold_applybt := let XX := fresh "XX" in
match goal with
[ |- context [lsubst ?e [(?v1, ?t1)]]] =>
assert (apply_bterm (bterm [v1] e) [t1] = lsubst e [(v1, t1)]) as XX by auto;
rewrite <- XX; clear XX
end.
Lemma simple_lsubst_cons2 {p} :
forall t v u sub,
@prog_sub p ((v, u) :: sub)
-> lsubst (subst t v u) sub = lsubst t ((v, u) :: sub).
Proof.
introv Hps.
rw cons_as_app in Hps.
apply sub_app_sat_if in Hps.
repnd. unfold subst.
rw @simple_lsubst_app; simpl; auto.
Qed.
Lemma simple_lsubst_cons3 {p} :
forall t v u sub,
@prog_sub p ((v, u) :: sub)
-> (!LIn v (dom_sub sub))
-> subst (lsubst t sub) v u = lsubst t ((v, u) :: sub).
Proof.
introv Hps Hd.
rw cons_as_app in Hps.
apply sub_app_sat_if in Hps.
repnd.
rw @lsubst_swap; auto;
[ |repnud Hps0; eapply Hps0; left; eauto].
rw snoc_as_append.
rw <- @simple_lsubst_app; simpl; auto.
Qed.
Lemma cover_vars_disjoint {p} :
forall u sub vs,
@cover_vars p u sub
-> disjoint (dom_csub sub) vs
-> disjoint (free_vars u) vs.
Proof.
introv cv disj.
rw @cover_vars_eq in cv.
unfold disjoint in disj.
unfold disjoint.
introv i.
rw subvars_prop in cv.
apply cv in i.
apply disj in i; sp.
Qed.
Lemma csub_filter_trivial {p} :
forall s vs,
disjoint vs (@dom_csub p s)
-> csub_filter s vs = s.
Proof.
induction s; introv disj; sp; allsimpl.
allrw disjoint_cons_r; repnd.
discover; allrw.
boolvar; sp.
Qed.
Lemma eqvars_sub_keep_first {p} :
forall sub la lb,
eqvars la lb
-> (@sub_keep_first p sub la) = (sub_keep_first sub lb).
Proof.
induction sub as [| (v,t) sub Hind]; introv Heq;auto.
simpl. duplicate Heq. rw eqvars_prop in Heq.
rw memvar_dmemvar.
rw memvar_dmemvar.
dtiffs2.
cases_if; cases_if; try (provefalse; eauto;fail); erewrite Hind; eauto 2 with eqvars.
Qed.
Lemma simple_lsubst_snoc {p} :
forall t v u sub,
@isprogram p u
-> (forall v u, LIn (v, u) sub -> isprogram u)
-> subst (lsubst t sub) v u = lsubst t (snoc sub (v,u)).
Proof.
intros.
unfold subst.
rw @simple_lsubst_app; simpl; sp; cpx.
rw snoc_as_append; sp.
Qed.
Lemma simple_csubst_subst {p} :
forall t x B s,
disjoint (@free_vars p t) (bound_vars B)
-> cover_vars t s
-> wf_term t
-> csubst (subst B x t) s
= subst (csubst B (csub_filter s [x])) x (csubst t s).
Proof.
introv disj cov wt.
unfold csubst, subst; simpl.
repeat (rw @simple_lsubst_lsubst; simpl);
try (complete (intros; allapply @in_csub2sub; sp;
allunfold @isprogram; repnd; allrw; sp));
try (complete (intros; sp; cpx; sp; apply @isprogram_csubst; sp; rw @nt_wf_eq; sp)).
rw @lsubst_sub_trivial_closed1; simpl;
try (complete (intros; allapply @in_csub2sub; sp;
allunfold @isprogram; repnd; allrw; sp));
try (complete (intros; sp; cpx; sp; apply @isprogram_csubst; sp; rw @nt_wf_eq; sp)).
rw <- snoc_as_append.
rw <- @lsubst_swap; simpl;
try (complete (intros; allapply @in_csub2sub; sp;
allunfold @isprogram; repnd; allrw; sp));
try (complete (intros; sp; cpx; sp; apply @isprogram_csubst; sp; rw @nt_wf_eq; sp));
try (complete (intro; allrw @dom_csub_eq; allrw @dom_csub_csub_filter;
allrw in_remove_nvars; allsimpl; sp)).
rw @fold_csubst.
repeat (rw <- @simple_lsubst_cons; simpl);
try (complete (intros; allapply @in_csub2sub; sp;
allunfold @isprogram; repnd; allrw; sp));
try (complete (intros; sp; cpx; sp; apply @isprogram_csubst; sp; rw @nt_wf_eq; sp)).
rw <- @sub_filter_csub2sub.
rw @lsubst_sub_filter; sp;
try (complete (intros; allapply @in_csub2sub; sp;
allunfold @isprogram; repnd; allrw; sp));
try (complete (intros; sp; cpx; sp; apply @isprogram_csubst; sp; rw @nt_wf_eq; sp)).
rw disjoint_singleton_r; intro i.
unfold subst in i; rw @isprogram_lsubst2 in i; allsimpl.
rw in_remove_nvars in i; allsimpl; sp.
intros; sp; cpx; apply isprogram_csubst; sp; rw @nt_wf_eq; sp.
Qed.
Lemma cover_vars_iff_closed_lsubstc {p} :
forall t s,
@cover_vars p t s <=> closed (csubst t s).
Proof.
introv.
unfold closed.
rw @cover_vars_eq.
unfold csubst.
rw @isprogram_lsubst2; sp; allapply @in_csub2sub; sp.
rw <- null_iff_nil.
rw null_remove_nvars_subvars.
rw @dom_csub_eq; sp.
Qed.
Lemma lsubst_aux_app_sub_filter {p} :
forall s1 s2 t,
prog_sub s1
-> @prog_sub p s2
-> lsubst t (s1 ++ s2)
= lsubst t (s1 ++ sub_filter s2 (dom_sub s1)).
Proof.
induction s1; simpl; introv ps1 ps2.
rw @sub_filter_nil_r; sp.
destruct a as [v u]; allsimpl.
allrw @prog_sub_cons; repnd.
repeat (rw <- @simple_lsubst_cons);
try (complete sp);
try (complete (introv i; allrw in_app_iff; sp; allrw <- @prog_sub_eq;
allrw @in_sub_filter; repnd; allsimpl; allrw not_over_or; repnd;
try (complete (apply ps1; rw @in_range_iff; exists v0; sp));
try (complete (apply ps2; rw @in_range_iff; exists v0; sp)))).
rw IHs1; sp.
generalize (lsubst_sub_filter (subst t v u) (s1 ++ sub_filter s2 (dom_sub s1)) [v]);
intro eq1.
dest_imp eq1 hyp.
introv i; allrw in_app_iff; sp; allrw <- @prog_sub_eq;
allrw @in_sub_filter; repnd; allsimpl; allrw not_over_or; repnd;
try (complete (apply ps1; rw @in_range_iff; exists v0; sp));
try (complete (apply ps2; rw @in_range_iff; exists v0; sp)).
dest_imp eq1 hyp.
unfold subst; rw @isprogram_lsubst2; simpl.
rw disjoint_remove_nvars_l; rw remove_nvars_eq; sp.
introv k; sp; cpx.
generalize (lsubst_sub_filter (subst t v u) (s1 ++ sub_filter s2 (v :: dom_sub s1)) [v]);
intro eq2.
dest_imp eq2 hyp.
introv i; allrw in_app_iff; sp; allrw <- @prog_sub_eq;
allrw @in_sub_filter; repnd; allsimpl; allrw not_over_or; repnd;
try (complete (apply ps1; rw @in_range_iff; exists v0; sp));
try (complete (apply ps2; rw @in_range_iff; exists v0; sp)).
dest_imp eq2 hyp.
unfold subst; rw @isprogram_lsubst2; simpl.
rw disjoint_remove_nvars_l; rw remove_nvars_eq; sp.
introv k; sp; cpx.
rw <- eq1; rw <- eq2.
allrw @sub_filter_app; simpl.
allrw <- @sub_filter_app_r.
assert (sub_filter s2 (dom_sub s1 ++ [v]) = sub_filter s2 ((v :: dom_sub s1) ++ [v]))
as eq; try (complete (rw eq; sp)).
symmetry.
rewrite sub_filter_app_as_remove_nvars; simpl.
rw remove_nvars_cons_r; boolvar; try (complete (allrw not_over_or; sp)).
rw remove_nvars_nil_r; rw app_nil_r.
rw cons_as_app.
allrw @sub_filter_app_r.
rewrite sub_filter_swap; sp.
Qed.
Lemma prog_sub_sub_filter {p} :
forall s vs, @prog_sub p s -> prog_sub (sub_filter s vs).
Proof.
introv ps.
allunfold @prog_sub.
allunfold @sub_range_sat.
introv i.
apply in_sub_filter in i; repnd; discover; sp.
Qed.
Lemma prog_sub_snoc {p} :
forall s v t,
@prog_sub p (snoc s (v,t)) <=> (prog_sub s # isprogram t).
Proof.
introv.
unfold prog_sub, sub_range_sat; split; intro k.
dands.
introv i.
generalize (k v0 t0); intro j; allrw in_snoc; sp.
generalize (k v t); intro j; allrw in_snoc; sp.
repnd.
introv i; allrw in_snoc; sp; cpx; discover; sp.
Qed.
Lemma covered_apply {p} :
forall a b vs,
@covered p (mk_apply a b) vs
<=> covered a vs
# covered b vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_apply2 {p} :
forall a b c vs,
@covered p (mk_apply2 a b c) vs
<=> covered a vs
# covered b vs
# covered c vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
repeat (rewrite app_nil_r).
repeat (rw subvars_app_l); sp; split; sp.
Qed.
Lemma cover_vars_change_sub2 {p} :
forall t sub1 sub2,
subvars (@dom_csub p sub1) (dom_csub sub2)
-> cover_vars t sub1
-> cover_vars t sub2.
Proof.
introv eq cv.
allrw @cover_vars_eq.
apply subvars_trans with (vs2 := dom_csub sub1); sp.
Qed.
Lemma cover_vars_upto_w {p} :
forall A v B sub vs,
@cover_vars_upto p (mk_w A v B) sub vs
<=> cover_vars_upto A sub vs
# cover_vars_upto B (csub_filter sub [v]) (v :: vs).
Proof.
introv; repeat (rw cover_vars_eq); unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; simpl.
allrw @dom_csub_csub_filter.
split; sp; allrw subvars_prop; sp; discover; sp;
allsimpl; allrw in_app_iff; allrw in_remove_nvars;
allrw in_single_iff; sp.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma csubst_as_lsubst_aux {p} :
forall t sub, @csubst p t sub = lsubst_aux t (csub2sub sub).
Proof.
sp.
unfold csubst, lsubst.
change_to_lsubst_aux4; sp.
Qed.
Lemma lsubst_aux_lam_csub2sub {p} :
forall v b s,
lsubst_aux (mk_lam v b) (@csub2sub p s)
= mk_lam v (lsubst_aux b (csub2sub (csub_filter s [v]))).
Proof.
sp; simpl.
rw @fold_lam.
rw @sub_filter_csub2sub; sp.
Qed.
Lemma csub_filter_nil {p} :
forall s, @csub_filter p s [] = s.
Proof.
induction s; simpl; sp.
rw IHs; sp.
Qed.
Lemma lsubst_aux_isect_csub2sub {p} :
forall a v b s,
lsubst_aux (mk_isect a v b) (@csub2sub p s)
= mk_isect (lsubst_aux a (csub2sub s)) v (lsubst_aux b (csub2sub (csub_filter s [v]))).
Proof.
sp; simpl.
rw @fold_nobnd.
rw @fold_isect.
allrw @sub_filter_csub2sub.
allrw @csub_filter_nil; sp.
Qed.
Lemma lsubst_aux_free_from_atom_csub2sub {p} :
forall a b c s,
lsubst_aux (mk_free_from_atom a b c) (@csub2sub p s)
= mk_free_from_atom
(lsubst_aux a (csub2sub s))
(lsubst_aux b (csub2sub s))
(lsubst_aux c (csub2sub s)).
Proof.
sp; simpl.
allrw @fold_nobnd.
rw @fold_free_from_atom.
allrw @sub_filter_csub2sub.
allrw @csub_filter_nil; sp.
Qed.
Lemma lsubst_aux_free_from_atoms_csub2sub {p} :
forall a b s,
lsubst_aux (mk_free_from_atoms a b) (@csub2sub p s)
= mk_free_from_atoms
(lsubst_aux a (csub2sub s))
(lsubst_aux b (csub2sub s)).
Proof.
sp; simpl.
allrw @fold_nobnd.
rw @fold_free_from_atoms.
allrw @sub_filter_csub2sub.
allrw @csub_filter_nil; sp.
Qed.
Lemma lsubst_aux_equality_csub2sub {p} :
forall a b T s,
lsubst_aux (mk_equality a b T) (@csub2sub p s)
= mk_equality
(lsubst_aux a (csub2sub s))
(lsubst_aux b (csub2sub s))
(lsubst_aux T (csub2sub s)).
Proof.
sp; simpl.
allrw @fold_nobnd.
rw @fold_equality.
allrw @sub_filter_csub2sub.
allrw @csub_filter_nil; sp.
Qed.
Lemma lsubst_aux_tequality_csub2sub {p} :
forall a b s,
lsubst_aux (mk_tequality a b) (@csub2sub p s)
= mk_tequality
(lsubst_aux a (csub2sub s))
(lsubst_aux b (csub2sub s)).
Proof.
sp; simpl.
allrw @fold_nobnd.
rw @fold_tequality.
allrw @sub_filter_csub2sub.
allrw @csub_filter_nil; sp.
Qed.
Lemma lsubst_aux_apply_csub2sub {p} :
forall a b s,
lsubst_aux (mk_apply a b) (@csub2sub p s)
= mk_apply
(lsubst_aux a (csub2sub s))
(lsubst_aux b (csub2sub s)).
Proof.
sp; simpl.
allrw @fold_nobnd.
rw @fold_apply.
allrw @sub_filter_csub2sub.
allrw @csub_filter_nil; sp.
Qed.
Lemma lsubst_aux_base_csub2sub {p} :
forall s,
lsubst_aux mk_base (csub2sub s) = @mk_base p.
Proof.
sp.
Qed.
Lemma lsubst_aux_var_csub2sub_out {p} :
forall v s,
!LIn v (dom_csub s)
-> lsubst_aux (mk_var v) (csub2sub s) = @mk_var p v.
Proof.
introv ni; simpl.
rw <- @dom_csub_eq in ni.
apply sub_find_none_iff in ni.
rw ni; sp.
Qed.
Lemma cover_vars_fun {p} :
forall a b sub,
cover_vars (@mk_fun p a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
introv.
rw @cover_vars_function.
generalize (cover_vars_upto_csub_filter_disjoint b sub [newvar b] [newvar b]).
intro e.
repeat (dest_imp e hyp).
rw disjoint_singleton_r.
apply newvar_prop.
rw e; sp.
Qed.
Lemma cover_vars_ufun {p} :
forall a b sub,
cover_vars (@mk_ufun p a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
introv.
rw @cover_vars_isect.
generalize (cover_vars_upto_csub_filter_disjoint b sub [newvar b] [newvar b]).
intro e.
repeat (dest_imp e hyp).
rw disjoint_singleton_r.
apply newvar_prop.
rw e; sp.
Qed.
Lemma cover_vars_eufun {p} :
forall a b sub,
cover_vars (@mk_eufun p a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
introv.
rw @cover_vars_eisect.
generalize (cover_vars_upto_csub_filter_disjoint b sub [newvar b] [newvar b]).
intro e.
repeat (dest_imp e hyp).
rw disjoint_singleton_r.
apply newvar_prop.
rw e; sp.
Qed.
Lemma cover_vars_prod {p} :
forall a b sub,
cover_vars (@mk_prod p a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
introv.
rw @cover_vars_product.
generalize (cover_vars_upto_csub_filter_disjoint b sub [newvar b] [newvar b]).
intro e.
repeat (dest_imp e hyp).
rw disjoint_singleton_r.
apply newvar_prop.
rw e; sp.
Qed.
Lemma cover_vars_void {p} :
forall sub, @cover_vars p mk_void sub.
Proof.
introv.
rw @cover_vars_eq; simpl; sp.
Qed.
Hint Immediate cover_vars_void.
Lemma cover_vars_not {p} :
forall a sub, cover_vars (@mk_not p a) sub <=> cover_vars a sub.
Proof.
introv.
rw @cover_vars_fun; split; sp.
Qed.
Lemma covered_function {p} :
forall a v b vs,
covered (@mk_function p a v b) vs
<=> covered a vs # covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_product {p} :
forall a v b vs,
covered (@mk_product p a v b) vs
<=> covered a vs # covered b (v :: vs).
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_fun {p} :
forall a b vs,
covered (@mk_fun p a b) vs
<=> covered a vs # covered b vs.
Proof.
introv; rw @covered_function; split; intro k; repnd; dands; auto.
allunfold @covered.
apply subvars_cons_r_weak_if_not_in in k; auto.
apply newvar_prop.
allunfold @covered.
apply subvars_cons_r; auto.
Qed.
Lemma covered_ufun {p} :
forall a b vs,
covered (@mk_ufun p a b) vs
<=> covered a vs # covered b vs.
Proof.
introv; rw @covered_isect; split; intro k; repnd; dands; auto.
allunfold @covered.
apply subvars_cons_r_weak_if_not_in in k; auto.
apply newvar_prop.
allunfold @covered.
apply subvars_cons_r; auto.
Qed.
Lemma covered_eufun {p} :
forall a b vs,
covered (@mk_eufun p a b) vs
<=> covered a vs # covered b vs.
Proof.
introv; rw @covered_eisect; split; intro k; repnd; dands; auto.
allunfold @covered.
apply subvars_cons_r_weak_if_not_in in k; auto.
apply newvar_prop.
allunfold @covered.
apply subvars_cons_r; auto.
Qed.
Lemma covered_prod {p} :
forall a b vs,
covered (@mk_prod p a b) vs
<=> covered a vs # covered b vs.
Proof.
introv; rw @covered_product; split; intro k; repnd; dands; auto.
allunfold @covered.
apply subvars_cons_r_weak_if_not_in in k; auto.
apply newvar_prop.
allunfold @covered.
apply subvars_cons_r; auto.
Qed.
Lemma covered_iff {p} :
forall a b vs,
covered (@mk_iff p a b) vs
<=> covered a vs # covered b vs.
Proof.
introv.
rw @covered_prod.
allrw @covered_fun; split; sp.
Qed.
Lemma isprog_vars_lsubst {p} :
forall t : NTerm,
forall vs : list NVar,
forall sub : @Substitution p,
nt_wf t
-> (forall v u, LIn (v, u) sub -> isprogram u)
-> (forall v, LIn v (free_vars t) -> LIn v (vs ++ dom_sub sub))
-> isprog_vars vs (lsubst t sub).
Proof.
introv w k1 k2.
rw @isprog_vars_eq.
apply @isprogram_lsubst1 with (sub := sub) in w; sp.
allrw.
rw subvars_remove_nvars.
rw subvars_prop; auto.
Qed.
Lemma isprog_vars_csubst {p} :
forall t : NTerm,
forall vs : list NVar,
forall sub : @CSub p,
nt_wf t
-> (forall v, LIn v (free_vars t) -> LIn v (vs ++ dom_csub sub))
-> isprog_vars vs (csubst t sub).
Proof.
introv w k.
unfold csubst.
apply isprog_vars_lsubst; sp;
allapply @in_csub2sub; sp.
rw @dom_csub_eq; sp.
Qed.
Lemma cover_vars_pertype {p} :
forall a sub,
cover_vars (@mk_pertype p a) sub
<=> cover_vars a sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_ipertype {p} :
forall a sub,
cover_vars (@mk_ipertype p a) sub
<=> cover_vars a sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_spertype {p} :
forall a sub,
cover_vars (@mk_spertype p a) sub
<=> cover_vars a sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_tuni {p} :
forall a sub,
cover_vars (@mk_tuni p a) sub
<=> cover_vars a sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma sub_find_some_app2 {p} :
forall v t sub1 sub2,
!LIn v (dom_sub sub1)
-> @sub_find p sub2 v = Some t
-> sub_find (sub1 ++ sub2) v = Some t.
Proof.
introv niv sf.
rw @sub_find_app.
rw <- @sub_find_none_iff in niv.
rw niv; sp.
Qed.
Lemma subset_free_vars_sub_aux_app2 {p} :
forall t sub1 sub2,
(forall v t, LIn (v, t) (sub1 ++ sub2) -> @isprogram p t)
-> disjoint (free_vars t) (dom_sub sub1)
-> lsubst_aux t (sub1 ++ sub2) = lsubst_aux t sub2.
Proof.
nterm_ind t Case; simpl; introv k d; auto.
- Case "vterm".
allrw disjoint_singleton_l; sp.
remember (sub_find sub2 n); destruct o; symmetry in Heqo.
apply @sub_find_some_app2 with (sub1 := sub1) in Heqo; auto.
rw Heqo; auto.
rw @sub_find_none_iff in Heqo.
assert (!LIn n (dom_sub (sub1 ++ sub2))) as nin
by (rw @dom_sub_app; rw in_app_iff; intro; sp).
rw <- @sub_find_none_iff in nin.
rw nin; auto.
- Case "oterm".
f_equal.
apply eq_maps; sp.
destruct x; simpl.
repeat (rw bvar_renamings_subst_isprogram; auto); simpl;
try (sp; apply X with (v := v); rw in_app_iff; sp).
rw @sub_filter_app.
rewrite H with (lv := l); sp.
apply k with (v := v).
allrw in_app_iff.
allrw @in_sub_filter; sp.
allrw disjoint_flat_map_l.
apply_in_hyp pp.
allsimpl.
rw disjoint_remove_nvars_l in pp.
rw <- @dom_sub_sub_filter; auto.
Qed.
Lemma subset_free_vars_sub_app2 {p} :
forall t sub1 sub2,
(forall v t, LIn (v, t) (sub1 ++ sub2) -> @isprogram p t)
-> disjoint (free_vars t) (dom_sub sub1)
-> lsubst t (sub1 ++ sub2) = lsubst t sub2.
Proof.
introv Hpr.
applydup (sub_app_sat_if (@isprogram p)) in Hpr.
repnd.
change_to_lsubst_aux4.
apply subset_free_vars_sub_aux_app2; sp.
Qed.
Lemma subset_free_vars_csub_app2 {p} :
forall t sub1 sub2,
disjoint (free_vars t) (@dom_csub p sub1)
-> csubst t (sub1 ++ sub2) = csubst t sub2.
Proof.
unfold csubst; sp.
rw <- @csub2sub_app.
apply subset_free_vars_sub_app2; sp.
allrw in_app_iff; sp; allapply @in_csub2sub; sp.
rw @dom_csub_eq; auto.
Qed.
Lemma subset_free_vars_csub_cons {p} :
forall t sub v u,
!LIn v (@free_vars p t)
-> csubst t ((v,u) :: sub) = csubst t sub.
Proof.
intros.
rw cons_as_app.
rw @subset_free_vars_csub_app2; simpl; auto.
unfold disjoint; simpl; sp; subst; sp.
Qed.
Lemma cover_vars_app_disjoint2 {p} :
forall t sub1 sub2,
@cover_vars p t (sub1 ++ sub2)
-> disjoint (free_vars t) (dom_csub sub1)
-> cover_vars t sub2.
Proof.
introv cv disj.
allrw @cover_vars_eq.
rw @dom_csub_app in cv.
provesv.
allrw in_app_iff; sp.
unfold disjoint in disj.
discover; sp.
Qed.
Lemma cover_vars_cons_disjoint {p} :
forall t sub v u,
@cover_vars p t ((v,u) :: sub)
-> !LIn v (free_vars t)
-> cover_vars t sub.
Proof.
introv cv ni.
rw cons_as_app in cv.
apply cover_vars_app_disjoint2 in cv; sp.
simpl; unfold disjoint; simpl; sp; subst; sp.
Qed.
Lemma cover_vars_upto_csub_filter_app {p} :
forall t s vs1 vs2 vs,
eqvars vs1 vs2
-> disjoint (free_vars t) vs1
-> (cover_vars_upto t (@csub_filter p s vs1) (vs2 ++ vs)
<=> cover_vars_upto t s vs).
Proof.
introv eqv disj.
unfold cover_vars_upto.
allrw subvars_prop; split; intro k; introv i; allrw in_app_iff;
allrw @dom_csub_csub_filter; allrw in_remove_nvars.
applydup disj in i.
apply k in i.
allrw in_app_iff; allrw in_remove_nvars; repdors; try (complete sp).
rw eqvars_prop in eqv.
apply eqv in i2; sp.
applydup disj in i.
apply k in i.
allrw in_app_iff; repdors; try (complete sp).
Qed.
Lemma covered_cons_weak_iff {p} :
forall t v (ni : !LIn v (@free_vars p t)) vs,
covered t (v :: vs) <=> covered t vs.
Proof.
introv.
unfold covered; split; intro k; provesv; allsimpl; repdors; subst; sp.
Qed.
Lemma cover_vars_upto_pertype {p} :
forall a sub vs,
cover_vars_upto (@mk_pertype p a) sub vs
<=> cover_vars_upto a sub vs.
Proof.
sp; unfold cover_vars_upto; split; intro k;
allrw subvars_prop; introv i; apply k;
allsimpl; allrw remove_nvars_nil_l; allrw app_nil_r; sp.
Qed.
Lemma covered_pertype {p} :
forall a vs,
covered (@mk_pertype p a) vs
<=> covered a vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_upto_ipertype {p} :
forall a sub vs,
cover_vars_upto (@mk_ipertype p a) sub vs
<=> cover_vars_upto a sub vs.
Proof.
sp; unfold cover_vars_upto; split; intro k;
allrw subvars_prop; introv i; apply k;
allsimpl; allrw remove_nvars_nil_l; allrw app_nil_r; sp.
Qed.
Lemma covered_ipertype {p} :
forall a vs,
covered (@mk_ipertype p a) vs
<=> covered a vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_upto_spertype {p} :
forall a sub vs,
cover_vars_upto (@mk_spertype p a) sub vs
<=> cover_vars_upto a sub vs.
Proof.
sp; unfold cover_vars_upto; split; intro k;
allrw subvars_prop; introv i; apply k;
allsimpl; allrw remove_nvars_nil_l; allrw app_nil_r; sp.
Qed.
Lemma covered_spertype {p} :
forall a vs,
covered (@mk_spertype p a) vs
<=> covered a vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_upto_tuni {p} :
forall a sub vs,
cover_vars_upto (@mk_tuni p a) sub vs
<=> cover_vars_upto a sub vs.
Proof.
sp; unfold cover_vars_upto; split; intro k;
allrw subvars_prop; introv i; apply k;
allsimpl; allrw remove_nvars_nil_l; allrw app_nil_r; sp.
Qed.
Lemma covered_tuni {p} :
forall a vs,
covered (@mk_tuni p a) vs
<=> covered a vs.
Proof.
unfold covered; sp; simpl.
repeat (rw remove_nvars_nil_l).
rewrite app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma covered_base {p} :
forall vs, @covered p mk_base vs.
Proof.
unfold covered; sp; simpl.
Qed.
Hint Immediate covered_base.
Lemma covered_base_iff {p} :
forall vs, @covered p mk_base vs <=> True.
Proof.
sp.
Qed.
Lemma covered_iff_cover_vars {p} :
forall vs t s, @dom_csub p s = vs -> (covered t vs <=> cover_vars t s).
Proof.
introv e.
rw @cover_vars_eq.
unfold covered; subst; sp.
Qed.
Lemma cover_vars_spread {p} :
forall a v1 v2 b sub,
cover_vars (@mk_spread p a v1 v2 b) sub
<=> cover_vars a sub
# cover_vars_upto b (csub_filter sub [v1,v2]) [v1,v2].
Proof.
sp; repeat (rw @cover_vars_eq); unfold cover_vars_upto; simpl.
rw @remove_nvars_nil_l; rw app_nil_r.
rw subvars_app_l.
rw subvars_remove_nvars; simpl.
rw @dom_csub_csub_filter.
assert (v1 :: v2 :: remove_nvars [v1,v2] (dom_csub sub)
= [v1,v2] ++ remove_nvars [v1,v2] (dom_csub sub)) as eq by auto.
rw eq.
rw subvars_app_remove_nvars_r.
rw subvars_swap_r; sp.
Qed.
Lemma cover_vars_pair {p} :
forall a b sub,
@cover_vars p (mk_pair a b) sub
<=> cover_vars a sub
# cover_vars b sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_ispair {p} :
forall a b T sub,
@cover_vars p (mk_ispair a b T) sub
<=> cover_vars a sub
# cover_vars b sub
# cover_vars T sub.
Proof.
sp; repeat (rw @cover_vars_eq); simpl.
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
repeat (rw subvars_app_l); sp.
Qed.
Lemma cover_vars_upto_ispair {p} :
forall vs a b T sub,
@cover_vars_upto p (mk_ispair a b T) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b sub vs
# cover_vars_upto T sub vs.
Proof.
intros; unfold cover_vars_upto; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
Qed.
Lemma subst_ispair {p} :
forall t a b x u,
@isprogram p u
-> subst (mk_ispair t a b) x u
= mk_ispair (subst t x u) (subst a x u) (subst b x u).
Proof.
introv ipu.
destruct ipu as [cl wf].
unfold subst.
change_to_lsubst_aux4; simpl; allrw app_nil_r; allrw; sp.
Qed.
Lemma cover_vars_eta_pair {p} :
forall t s, cover_vars (@mk_eta_pair p t) s <=> cover_vars t s.
Proof.
introv.
rw @cover_vars_pair.
allrw @cover_vars_spread.
allrw @cover_vars_upto_var.
allrw in_app_iff; simpl; split; sp.
Qed.
Lemma cover_vars_upto_approx {p} :
forall a b sub vs,
cover_vars_upto (@mk_approx p a b) sub vs
<=> cover_vars_upto a sub vs
# cover_vars_upto b sub vs.
Proof.
unfold cover_vars_upto; introv; simpl.
rw app_nil_r.
allrw remove_nvars_nil_l.
rw subvars_app_l; sp.
Qed.
Lemma cover_vars_upto_fix {p} :
forall a sub vs,
cover_vars_upto (@mk_fix p a) sub vs
<=> cover_vars_upto a sub vs.
Proof.
unfold cover_vars_upto; introv; simpl.
rw app_nil_r.
rw remove_nvars_nil_l; sp.
Qed.
Lemma cover_vars_upto_id {p} :
forall sub vs, @cover_vars_upto p mk_id sub vs.
Proof.
unfold cover_vars_upto; introv; simpl; sp.
Qed.
Hint Immediate cover_vars_upto_id.
Lemma cover_vars_upto_bot {p} :
forall sub vs, @cover_vars_upto p mk_bot sub vs.
Proof.
unfold mk_bot, mk_bottom.
introv.
apply cover_vars_upto_fix; sp.
Qed.
Hint Immediate cover_vars_upto_bot.
Lemma cover_vars_upto_false {p} :
forall sub vs, @cover_vars_upto p mk_false sub vs.
Proof.
introv.
unfold mk_false.
rw @cover_vars_upto_approx; sp.
Qed.
Hint Immediate cover_vars_upto_false.
Lemma cover_vars_upto_top {p} :
forall sub vs, @cover_vars_upto p mk_top sub vs.
Proof.
introv.
unfold mk_top.
rw @cover_vars_upto_isect; sp.
Qed.
Hint Immediate cover_vars_upto_top.
Lemma cover_vars_top {p} :
forall sub, @cover_vars p mk_top sub.
Proof.
introv.
generalize (cover_vars_upto_csub_filter_disjoint mk_top sub [] []);
intro k; repeat (autodimp k hyp).
rw <- k; sp.
Qed.
Hint Immediate cover_vars_top.
Lemma lsubst_mk_bot {pp} :
forall sub, {v : NVar & lsubst mk_bot sub = @mk_vbot pp v}.
Proof.
introv.
unfold lsubst.
destruct (dec_disjointv (bound_vars mk_bot) (flat_map free_vars (range sub))).
- simpl in d.
rw disjoint_singleton_l in d.
exists nvarx.
simpl.
rw @sub_filter_nil_r.
rw @sub_find_sub_filter; simpl; sp.
- simpl in n; rw disjoint_singleton_l in n.
generalize (ex_fresh_var (flat_map free_vars (range sub))); intro k; exrepnd.
simpl; unfold all_vars; simpl.
rw @sub_filter_nil_r.
rw @sub_find_sub_filter; simpl; tcsp.
remember (fresh_var (flat_map free_vars (range sub) ++ [nvarx])) as fv.
exists fv; sp.
Qed.
Lemma sub_free_vars_is_flat_map_free_vars_range {o} :
forall sub : @Sub o,
sub_free_vars sub = flat_map free_vars (range sub).
Proof.
induction sub; simpl; auto.
destruct a; simpl; rw IHsub; auto.
Qed.
(*
Lemma lsubst_mk_exception {o} :
forall (a e : @NTerm o) sub,
lsubst (mk_exception a e) sub = mk_exception (lsubst a sub) (lsubst e sub).
Proof.
introv.
unfold lsubst, mk_exception; simpl.
allrw app_nil_r.
allrw @sub_filter_nil_r.
unfold var_ren; simpl.
allrw @lsubst_aux_nil.
unfold nobnd.
allrw <- @sub_free_vars_is_flat_map_free_vars_range.
boolvar; allrw disjoint_app_l; tcsp; try (complete (provefalse; sp)).
Qed.
Lemma subst_mk_exception {p} :
forall e v t,
subst (@mk_exception p e) v t = mk_exception (subst e v t).
Proof.
introv.
unfold subst.
apply lsubst_mk_exception.
Qed.
*)
Lemma isprogram_bt_implies_isprogram_lsubst {p} :
forall vs t sub,
@dom_sub p sub = vs
-> (forall v t, LIn (v,t) sub -> isprogram t)
-> isprogram_bt (bterm vs t)
-> isprogram (lsubst t sub).
Proof.
introv domeq ispsub ispbt; subst.
apply isprogram_lsubst; auto.
inversion ispbt as [cl wf].
inversion wf; subst; auto.
introv i.
inversion ispbt as [cl wf].
inversion cl as [e].
rw <- null_iff_nil in e.
rw null_remove_nvars in e.
discover; auto.
Qed.
(* The line below should be at the end of the file. Do NOT
write anything below that is not supposed to be included in the Tech Report*)
(* end hide*)
|
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 3.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : srio_gen2_0_tx_startup_fsm.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Description : This module performs TX reset and initialization.
//
//
//
// Module srio_gen2_0_tx_startup_fsm
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//*****************************************************************************
`timescale 1ns / 1ps
`define DLY #1
module srio_gen2_0_TX_STARTUP_FSM #
(
parameter STABLE_CLOCK_PERIOD = 8, // Period of the stable clock driving this state-machine, unit is [ns]
parameter RETRY_COUNTER_BITWIDTH = 8,
parameter EXAMPLE_SIMULATION = 0,
parameter TX_QPLL_USED = "FALSE", // the TX and RX Reset FSMs must
parameter RX_QPLL_USED = "FALSE", // share these two generic values
parameter PHASE_ALIGNMENT_MANUAL = "TRUE" // Decision if a manual phase-alignment is necessary or the automatic
// is enough. For single-lane applications the automatic alignment is
// sufficient
)
(
input wire STABLE_CLOCK, //Stable Clock, either a stable clock from the PCB
input wire TXUSERCLK, //TXUSERCLK as used in the design
input wire SOFT_RESET, //User Reset, can be pulled any time
input wire QPLLREFCLKLOST, //QPLL Reference-clock for the GT is lost
input wire CPLLREFCLKLOST, //CPLL Reference-clock for the GT is lost
input wire QPLLLOCK, //Lock Detect from the QPLL of the GT
input wire CPLLLOCK , //Lock Detect from the CPLL of the GT
input wire TXRESETDONE,
input wire MMCM_LOCK,
output GTTXRESET,
output reg MMCM_RESET = 1'b1,
output reg QPLL_RESET = 1'b0, //Reset QPLL
output reg CPLL_RESET = 1'b0, //Reset CPLL
output TX_FSM_RESET_DONE, //Reset-sequence has sucessfully been finished.
output reg TXUSERRDY = 1'b0 ,
output RUN_PHALIGNMENT,
output reg RESET_PHALIGNMENT = 1'b0,
input wire PHALIGNMENT_DONE,
output [RETRY_COUNTER_BITWIDTH-1:0] RETRY_COUNTER // Number of
// Retries it took to get the transceiver up and running
);
//Interdependencies:
// * Timing depends on the frequency of the stable clock. Hence counters-sizes
// are calculated at design-time based on the Generics
//
// * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
// => signal which PLL has been reset
// *
localparam [3:0]
INIT = 4'b0000,
ASSERT_ALL_RESETS = 4'b0001,
WAIT_FOR_PLL_LOCK = 4'b0010,
RELEASE_PLL_RESET = 4'b0011,
WAIT_FOR_TXOUTCLK = 4'b0100,
RELEASE_MMCM_RESET = 4'b0101,
WAIT_FOR_TXUSRCLK = 4'b0110,
WAIT_RESET_DONE = 4'b0111,
DO_PHASE_ALIGNMENT = 4'b1000,
RESET_FSM_DONE = 4'b1001;
reg [3:0] tx_state = INIT;
localparam integer MMCM_LOCK_CNT_MAX = 1024;
localparam integer STARTUP_DELAY = 500;//AR43482: Transceiver needs to wait for 500 ns after configuration
localparam integer WAIT_CYCLES = STARTUP_DELAY / STABLE_CLOCK_PERIOD; // Number of Clock-Cycles to wait after configuration
localparam integer WAIT_MAX = WAIT_CYCLES + 10; // 500 ns plus some additional margin
localparam integer WAIT_TIMEOUT_2ms = 2000000 / STABLE_CLOCK_PERIOD;// 2 ms time-out
localparam integer WAIT_TLOCK_MAX = 100000 / STABLE_CLOCK_PERIOD;//100 us time-out
localparam integer WAIT_TIMEOUT_500us = 500000 / STABLE_CLOCK_PERIOD;//100 us time-out
localparam integer WAIT_1us_CYCLES = 1000 / STABLE_CLOCK_PERIOD;//1 us time-out
localparam integer WAIT_1us = WAIT_1us_CYCLES+10; //1us plus additional margin
localparam integer WAIT_TIME_MAX = EXAMPLE_SIMULATION? 100 : 10000 / STABLE_CLOCK_PERIOD;
reg [7:0] init_wait_count = 0;
reg init_wait_done = 1'b0;
reg pll_reset_asserted = 1'b0;
reg tx_fsm_reset_done_int = 1'b0;
wire tx_fsm_reset_done_int_s2;
reg tx_fsm_reset_done_int_s3 = 1'b0;
localparam integer MAX_RETRIES = 2**RETRY_COUNTER_BITWIDTH-1;
reg [7:0] retry_counter_int = 0;
reg [18:0] time_out_counter = 0;
reg reset_time_out = 1'b0;
reg time_out_2ms = 1'b0; //--\Flags that the various time-out points
reg time_tlock_max = 1'b0; //--|have been reached.
reg time_out_500us = 1'b0; //--/
reg [9:0] mmcm_lock_count = 0;
reg mmcm_lock_int = 1'b0;
wire mmcm_lock_i;
reg mmcm_lock_reclocked = 1'b0;
reg run_phase_alignment_int = 1'b0;
wire run_phase_alignment_int_s2;
reg run_phase_alignment_int_s3 = 1'b0;
localparam integer MAX_WAIT_BYPASS = 86784;
reg [16:0] wait_bypass_count = 0;
reg time_out_wait_bypass = 1'b0;
wire time_out_wait_bypass_s2;
reg time_out_wait_bypass_s3 = 1'b0;
wire txresetdone_s2;
reg txresetdone_s3 = 1'b0;
reg gttxreset_i = 1'b0;
reg txpmaresetdone_i = 1'b0;
wire txpmaresetdone_sync;
wire refclk_lost;
wire cplllock_sync;
wire qplllock_sync;
reg [15:0] wait_time_cnt;
wire wait_time_done;
//Alias section, signals used within this module mapped to output ports:
assign RETRY_COUNTER = retry_counter_int;
assign RUN_PHALIGNMENT = run_phase_alignment_int;
assign TX_FSM_RESET_DONE = tx_fsm_reset_done_int;
assign GTTXRESET = gttxreset_i;
always @(posedge STABLE_CLOCK or posedge SOFT_RESET)
begin
// The counter starts running when configuration has finished and
// the clock is stable. When its maximum count-value has been reached,
// the 500 ns from Answer Record 43482 have been passed.
if(SOFT_RESET)
begin
init_wait_count <= `DLY 8'h0;
init_wait_done <= `DLY 1'b0;
end
else if (init_wait_count == WAIT_MAX)
init_wait_done <= `DLY 1'b1;
else
init_wait_count <= `DLY init_wait_count + 1;
end
always @(posedge STABLE_CLOCK)
begin
// One common large counter for generating three time-out signals.
// Intermediate time-outs are derived from calculated values, based
// on the period of the provided clock.
if (reset_time_out == 1'b1)
begin
time_out_counter <= `DLY 0;
time_out_2ms <= `DLY 1'b0;
time_tlock_max <= `DLY 1'b0;
time_out_500us <= `DLY 1'b0;
end
else
begin
if (time_out_counter == WAIT_TIMEOUT_2ms)
time_out_2ms <= `DLY 1'b1;
else
time_out_counter <= `DLY time_out_counter + 1;
if (time_out_counter == WAIT_TLOCK_MAX)
time_tlock_max <= `DLY 1'b1;
if (time_out_counter == WAIT_TIMEOUT_500us)
time_out_500us <= `DLY 1'b1;
end
end
always @(posedge STABLE_CLOCK)
begin
if (mmcm_lock_i == 1'b0)
begin
mmcm_lock_count <= `DLY 0;
mmcm_lock_reclocked <= `DLY 1'b0;
end
else
begin
if (mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1)
mmcm_lock_count <= `DLY mmcm_lock_count + 1;
else
mmcm_lock_reclocked <= `DLY 1'b1;
end
end
//Clock Domain Crossing
srio_gen2_0_sync_block sync_run_phase_alignment_int
(
.clk (TXUSERCLK),
.data_in (run_phase_alignment_int),
.data_out (run_phase_alignment_int_s2)
);
srio_gen2_0_sync_block sync_tx_fsm_reset_done_int
(
.clk (TXUSERCLK),
.data_in (tx_fsm_reset_done_int),
.data_out (tx_fsm_reset_done_int_s2)
);
always @(posedge TXUSERCLK)
begin
run_phase_alignment_int_s3 <= `DLY run_phase_alignment_int_s2;
tx_fsm_reset_done_int_s3 <= `DLY tx_fsm_reset_done_int_s2;
end
srio_gen2_0_sync_block sync_time_out_wait_bypass
(
.clk (STABLE_CLOCK),
.data_in (time_out_wait_bypass),
.data_out (time_out_wait_bypass_s2)
);
srio_gen2_0_sync_block sync_TXRESETDONE
(
.clk (STABLE_CLOCK),
.data_in (TXRESETDONE),
.data_out (txresetdone_s2)
);
srio_gen2_0_sync_block sync_mmcm_lock_reclocked
(
.clk (STABLE_CLOCK),
.data_in (MMCM_LOCK),
.data_out (mmcm_lock_i)
);
srio_gen2_0_sync_block sync_cplllock
(
.clk (STABLE_CLOCK),
.data_in (CPLLLOCK),
.data_out (cplllock_sync)
);
srio_gen2_0_sync_block sync_qplllock
(
.clk (STABLE_CLOCK),
.data_in (QPLLLOCK),
.data_out (qplllock_sync)
);
always @(posedge STABLE_CLOCK)
begin
time_out_wait_bypass_s3 <= `DLY time_out_wait_bypass_s2;
txresetdone_s3 <= `DLY txresetdone_s2;
end
always @(posedge TXUSERCLK)
begin
if (run_phase_alignment_int_s3 == 1'b0)
begin
wait_bypass_count <= `DLY 0;
time_out_wait_bypass <= `DLY 1'b0;
end
else if (run_phase_alignment_int_s3 == 1'b1 && tx_fsm_reset_done_int_s3 == 1'b0)
begin
if (wait_bypass_count == MAX_WAIT_BYPASS - 1)
time_out_wait_bypass <= `DLY 1'b1;
else
wait_bypass_count <= `DLY wait_bypass_count + 1;
end
end
assign refclk_lost = ( TX_QPLL_USED == "TRUE" && QPLLREFCLKLOST == 1'b1) ? 1'b1 :
( TX_QPLL_USED == "FALSE" && CPLLREFCLKLOST == 1'b1) ? 1'b1 : 1'b0;
always @(posedge STABLE_CLOCK )
begin
if((tx_state == ASSERT_ALL_RESETS) |
(tx_state == RELEASE_PLL_RESET) |
(tx_state == RELEASE_MMCM_RESET))
begin
wait_time_cnt <= `DLY WAIT_TIME_MAX;
end else if (wait_time_cnt != 16'h0)
begin
wait_time_cnt <= wait_time_cnt - 16'h1;
end
end
assign wait_time_done = (wait_time_cnt == 16'h0);
//FSM for resetting the GTX/GTH/GTP in the 7-series.
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//
// Following steps are performed:
// 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
// answer-record 43482
// 2) Assert all resets on the GT and on an MMCM potentially connected.
// After that wait until a reference-clock has been detected.
// 3) Release the reset to the GT and wait until the GT-PLL has locked.
// 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
// Also signal to the RX-side which PLL has been reset.
// 5) Wait for the RESET_DONE-signal from the GTX.
// 6) Signal to start the phase-alignment procedure and wait for it to
// finish.
// 7) Reset-sequence has successfully run through. Signal this to the
// rest of the design by asserting TX_FSM_RESET_DONE.
always @(posedge STABLE_CLOCK)
begin
if (SOFT_RESET == 1'b1)
//if (SOFT_RESET == 1'b1 || (tx_state != INIT && tx_state != ASSERT_ALL_RESETS && refclk_lost == 1'b1))
begin
tx_state <= `DLY INIT;
TXUSERRDY <= `DLY 1'b0;
gttxreset_i <= `DLY 1'b0;
MMCM_RESET <= `DLY 1'b0;
tx_fsm_reset_done_int <= `DLY 1'b0;
QPLL_RESET <= `DLY 1'b0;
CPLL_RESET <= `DLY 1'b0;
pll_reset_asserted <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
retry_counter_int <= `DLY 0;
run_phase_alignment_int <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
end
else
begin
case (tx_state)
INIT :
begin
//Initial state after configuration. This state will be left after
//approx. 500 ns and not be re-entered.
if (init_wait_done == 1'b1)
tx_state <= `DLY ASSERT_ALL_RESETS;
reset_time_out <= `DLY 1'b1;
end
ASSERT_ALL_RESETS :
begin
//This is the state into which the FSM will always jump back if any
//time-outs will occur.
//The number of retries is reported on the output RETRY_COUNTER. In
//case the transceiver never comes up for some reason, this machine
//will still continue its best and rerun until the FPGA is turned off
//or the transceivers come up correctly.
if (TX_QPLL_USED == "TRUE")
begin
if (pll_reset_asserted == 1'b0)
begin
QPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
QPLL_RESET <= `DLY 1'b0;
end
else
begin
if (pll_reset_asserted == 1'b0)
begin
CPLL_RESET <= `DLY 1'b1;
pll_reset_asserted <= `DLY 1'b1;
end
else
CPLL_RESET <= `DLY 1'b0;
end
TXUSERRDY <= `DLY 1'b0;
gttxreset_i <= `DLY 1'b1;
MMCM_RESET <= `DLY 1'b1;
reset_time_out <= `DLY 1'b1;
run_phase_alignment_int <= `DLY 1'b0;
RESET_PHALIGNMENT <= `DLY 1'b1;
if ((TX_QPLL_USED == "TRUE" && qplllock_sync == 1'b0 && pll_reset_asserted ) ||
(TX_QPLL_USED == "FALSE" && cplllock_sync == 1'b0 && pll_reset_asserted ))
tx_state <= `DLY WAIT_FOR_PLL_LOCK;
end
WAIT_FOR_PLL_LOCK :
begin
if(wait_time_done)
tx_state <= `DLY RELEASE_PLL_RESET;
end
RELEASE_PLL_RESET :
begin
//PLL-Reset of the GTX gets released and the time-out counter
//starts running.
pll_reset_asserted <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
if ((TX_QPLL_USED == "TRUE" && qplllock_sync == 1'b1) ||
(TX_QPLL_USED == "FALSE" && cplllock_sync == 1'b1))
begin
tx_state <= `DLY WAIT_FOR_TXOUTCLK;
reset_time_out <= `DLY 1'b1;
end
if (time_out_2ms == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
WAIT_FOR_TXOUTCLK :
begin
gttxreset_i <= `DLY 1'b0;
if(wait_time_done)
tx_state <= `DLY RELEASE_MMCM_RESET;
end
RELEASE_MMCM_RESET :
begin
//Release of the MMCM-reset. Waiting for the MMCM to lock.
MMCM_RESET <= `DLY 1'b0;
reset_time_out <= `DLY 1'b0;
if (mmcm_lock_reclocked == 1'b1)
begin
tx_state <= `DLY WAIT_FOR_TXUSRCLK;
reset_time_out <= `DLY 1'b1;
end
if (time_tlock_max == 1'b1 && mmcm_lock_reclocked == 1'b0 && reset_time_out == 1'b0)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
WAIT_FOR_TXUSRCLK :
begin
if(wait_time_done)
tx_state <= `DLY WAIT_RESET_DONE;
end
WAIT_RESET_DONE :
begin
TXUSERRDY <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (txresetdone_s3 == 1'b1)
begin
tx_state <= `DLY DO_PHASE_ALIGNMENT;
reset_time_out <= `DLY 1'b1;
end
if (time_out_500us == 1'b1 && reset_time_out == 1'b0)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
DO_PHASE_ALIGNMENT :
begin
//The direct handling of the signals for the Phase Alignment is done outside
//this state-machine.
RESET_PHALIGNMENT <= `DLY 1'b0;
run_phase_alignment_int <= `DLY 1'b1;
reset_time_out <= `DLY 1'b0;
if (PHALIGNMENT_DONE == 1'b1)
tx_state <= `DLY RESET_FSM_DONE;
if (time_out_wait_bypass_s3 == 1'b1)
begin
if (retry_counter_int == MAX_RETRIES)
// If too many retries are performed compared to what is specified in
// the generic, the counter simply wraps around.
retry_counter_int <= `DLY 0;
else
retry_counter_int <= `DLY retry_counter_int + 1;
tx_state <= `DLY ASSERT_ALL_RESETS;
end
end
RESET_FSM_DONE :
begin
reset_time_out <= `DLY 1'b1;
tx_fsm_reset_done_int <= `DLY 1'b1;
end
default:
tx_state <= `DLY INIT;
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_V |
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_axi.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:04 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v4_0_ddr2_7Series, bd_mig_7series_0_0, 2016.2" , CORE_GENERATION_INFO = "ddr2_7Series,mig_7series_v4_0,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=1, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR2, AXI_ENABLE=1, CLK_PERIOD=4000, PHY_RATIO=2, CLKIN_PERIOD=10000, VCCAUX_IO=1.8V, MEMORY_TYPE=COMP, MEMORY_PART=mt47h64m16hr-25e, DQ_WIDTH=16, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=50, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=1, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=NO_BUFFER}" *)
module mig_7series_v4_0_memc_ui_top_axi #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP0 = "IODELAY_MIG0",
parameter IODELAY_GRP1 = "IODELAY_MIG1",
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'b1111,
parameter [3:0] BYTE_LANES_B1 = 4'b1111,
parameter [3:0] BYTE_LANES_B2 = 4'b1111,
parameter [3:0] BYTE_LANES_B3 = 4'b1111,
parameter [3:0] BYTE_LANES_B4 = 4'b1111,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter SKIP_CALIB = "FALSE",
parameter TAPSPERKCLK = 56,
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_ADDR_WIDTH = 30,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// Instatiates register slices before upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN0[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Same as C_S_AXI_REG_EN0, but this register is after
// the upsizer
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
parameter FPGA_VOLT_TYPE = "N"
)
(
// Clock and reset ports
input clk,
input clk_div2,
input rst_div2,
input [1:0] clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input mmcm_ps_clk,
input poc_sample_pd,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_o,
output [2*nCK_PER_CLK-1:0] app_ecc_single_err,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// Ports to be used with SKIP_CALIB defined
output calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
// temperature monitor ports
input [11:0] device_temp,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
input aresetn,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
// AXI CTRL port
input s_axi_ctrl_awvalid,
output s_axi_ctrl_awready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
// Slave Interface Write Data Ports
input s_axi_ctrl_wvalid,
output s_axi_ctrl_wready,
input [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
// Slave Interface Write Response Ports
output s_axi_ctrl_bvalid,
input s_axi_ctrl_bready,
output [1:0] s_axi_ctrl_bresp,
// Slave Interface Read Address Ports
input s_axi_ctrl_arvalid,
output s_axi_ctrl_arready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
// Slave Interface Read Data Ports
output s_axi_ctrl_rvalid,
input s_axi_ctrl_rready,
output [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
output [1:0] s_axi_ctrl_rresp,
// Interrupt output
output interrupt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
input iddr_rst,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output [1023:0] dbg_poc
);
localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;
localparam INTERFACE = "AXI4";
// Port Interface.
// # = UI - User Interface,
// = AXI4 - AXI4 Interface.
localparam C_FAMILY = "virtex7";
localparam C_MC_DATA_WIDTH_LCL = 2*nCK_PER_CLK*DATA_WIDTH ;
// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire app_correct_en;
wire app_correct_en_i;
wire [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
wire [DQ_WIDTH/8-1:0] fi_xor_we;
wire [DQ_WIDTH-1:0] fi_xor_wrdata;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_rd_data_to_axi;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire [ADDR_WIDTH-1:0] app_addr;
wire [2:0] app_cmd;
wire app_en;
wire app_hi_pri;
wire app_sz;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_wdf_data_axi_o;
wire app_wdf_end;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire [C_MC_DATA_WIDTH_LCL/8-1:0] app_wdf_mask_axi_o;
wire app_wdf_wren;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
reg reset /* synthesis syn_maxfan = 10 */;
reg init_calib_complete_r;
//***************************************************************************
// Added a single register stage for the calib_done to fix timing
//***************************************************************************
always @(posedge clk)
init_calib_complete_r <= init_calib_complete;
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
mig_7series_v4_0_mem_intfc #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB (SKIP_CALIB),
.FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)
)
mem_intfc0
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
// skip calibration i/f
.calib_tap_req (calib_tap_req),
.calib_tap_load (calib_tap_load),
.calib_tap_addr (calib_tap_addr),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
.device_temp (device_temp),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.iddr_rst (iddr_rst),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.dbg_poc (dbg_poc[1023:0])
);
genvar o;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(o=0;o<8;o=o+1) begin
assign app_wdf_data[o*72+:72] = {app_wdf_data_axi_o[o*64+:8],app_wdf_data_axi_o[o*64+:64]} ;
assign app_wdf_mask[o*9+:9] = {app_wdf_mask_axi_o[o*8],app_wdf_mask_axi_o[o*8+:8]} ;
end
end else begin
end
end else begin
assign app_wdf_data = app_wdf_data_axi_o ;
assign app_wdf_mask = app_wdf_mask_axi_o ;
end
endgenerate
genvar e;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(e=0;e<8;e=e+1) begin
assign app_rd_data_to_axi[e*64+:64] = app_rd_data[e*72+:64];
end
end
end else begin
assign app_rd_data_to_axi = app_rd_data;
end
endgenerate
mig_7series_v4_0_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
// ECC ports
.app_raw_not_ecc (app_raw_not_ecc),
.app_ecc_multiple_err (app_ecc_multiple_err_o),
.app_ecc_single_err (app_ecc_single_err),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
mig_7series_v4_0_axi_mc #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_MC_DATA_WIDTH (C_MC_DATA_WIDTH_LCL),
.C_MC_ADDR_WIDTH (ADDR_WIDTH),
.C_MC_BURST_MODE (BURST_MODE),
.C_MC_nCK_PER_CLK (nCK_PER_CLK),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_ECC (ECC)
)
u_axi_mc
(
.aclk (clk),
.aresetn (aresetn),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// MC Master Interface
//CMD PORT
.mc_app_en (app_en),
.mc_app_cmd (app_cmd),
.mc_app_sz (app_sz),
.mc_app_addr (app_addr),
.mc_app_hi_pri (app_hi_pri),
.mc_app_rdy (app_rdy),
.mc_init_complete (init_calib_complete_r),
//DATA PORT
.mc_app_wdf_wren (app_wdf_wren),
.mc_app_wdf_mask (app_wdf_mask_axi_o),
.mc_app_wdf_data (app_wdf_data_axi_o),
.mc_app_wdf_end (app_wdf_end),
.mc_app_wdf_rdy (app_wdf_rdy),
.mc_app_rd_valid (app_rd_data_valid),
.mc_app_rd_data (app_rd_data_to_axi),
.mc_app_rd_end (app_rd_data_end),
.mc_app_ecc_multiple_err (app_ecc_multiple_err_o)
);
generate
if (ECC == "ON") begin : gen_axi_ctrl_top
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata_r;
mig_7series_v4_0_axi_ctrl_top #
(
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH) ,
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH) ,
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH) ,
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR) ,
.C_ECC_TEST (ECC_TEST) ,
.C_DQ_WIDTH (DQ_WIDTH) ,
.C_ECC_WIDTH (ECC_WIDTH) ,
.C_MEM_ADDR_ORDER (MEM_ADDR_ORDER) ,
.C_BANK_WIDTH (BANK_WIDTH) ,
.C_ROW_WIDTH (ROW_WIDTH) ,
.C_COL_WIDTH (COL_WIDTH) ,
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE) ,
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH) ,
.C_NCK_PER_CLK (nCK_PER_CLK) ,
.C_MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH)
)
axi_ctrl_top_0
(
.aclk (clk) ,
.aresetn (aresetn) ,
.s_axi_awvalid (s_axi_ctrl_awvalid) ,
.s_axi_awready (s_axi_ctrl_awready) ,
.s_axi_awaddr (s_axi_ctrl_awaddr) ,
.s_axi_wvalid (s_axi_ctrl_wvalid) ,
.s_axi_wready (s_axi_ctrl_wready) ,
.s_axi_wdata (s_axi_ctrl_wdata) ,
.s_axi_bvalid (s_axi_ctrl_bvalid) ,
.s_axi_bready (s_axi_ctrl_bready) ,
.s_axi_bresp (s_axi_ctrl_bresp) ,
.s_axi_arvalid (s_axi_ctrl_arvalid) ,
.s_axi_arready (s_axi_ctrl_arready) ,
.s_axi_araddr (s_axi_ctrl_araddr) ,
.s_axi_rvalid (s_axi_ctrl_rvalid) ,
.s_axi_rready (s_axi_ctrl_rready) ,
.s_axi_rdata (s_axi_ctrl_rdata) ,
.s_axi_rresp (s_axi_ctrl_rresp) ,
.interrupt (interrupt) ,
.init_complete (init_calib_complete_r) ,
.ecc_single (ecc_single) ,
.ecc_multiple (ecc_multiple) ,
.ecc_err_addr (ecc_err_addr) ,
.app_correct_en (app_correct_en) ,
.dfi_rddata (dbg_rddata_r) ,
.fi_xor_we (fi_xor_we) ,
.fi_xor_wrdata (fi_xor_wrdata)
);
// dbg_rddata delayed one cycle to match ecc_*
always @(posedge clk) begin
dbg_rddata_r <= dbg_rddata;
end
//if(ECC_TEST == "ON") begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b1}};
// assign app_correct_en_i = 'b0 ;
//end else begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
// assign app_correct_en_i = app_correct_en ;
//end
assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
assign app_correct_en_i = app_correct_en ;
end
else begin : gen_no_axi_ctrl_top
assign s_axi_ctrl_awready = 1'b0;
assign s_axi_ctrl_wready = 1'b0;
assign s_axi_ctrl_bvalid = 1'b0;
assign s_axi_ctrl_bresp = 2'b0;
assign s_axi_ctrl_arready = 1'b0;
assign s_axi_ctrl_rvalid = 1'b0;
assign s_axi_ctrl_rdata = {C_S_AXI_CTRL_DATA_WIDTH{1'b0}};
assign s_axi_ctrl_rresp = 2'b0;
assign interrupt = 1'b0;
assign app_correct_en = 1'b1;
assign app_raw_not_ecc = 4'b0;
assign fi_xor_we = {DQ_WIDTH/8{1'b0}};
assign fi_xor_wrdata = {DQ_WIDTH{1'b0}};
end
endgenerate
endmodule
|
module add_5stage (
input ck,
input [63:0] i_a, i_b,
input [6:0] i_htId,
input i_vld,
output [63:0] o_res,
output [6:0] o_htId,
output o_vld
);
// Wires & Registers
wire [63:0] c_t1_res;
wire [6:0] c_t1_htId;
wire c_t1_vld;
reg [63:0] r_t2_res, r_t3_res, r_t4_res, r_t5_res, r_t6_res;
reg [6:0] r_t2_htId, r_t3_htId, r_t4_htId, r_t5_htId, r_t6_htId;
reg r_t2_vld, r_t3_vld, r_t4_vld, r_t5_vld, r_t6_vld;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
r_t2_res <= c_t1_res;
r_t2_htId <= c_t1_htId;
r_t2_vld <= c_t1_vld;
r_t3_res <= r_t2_res;
r_t3_htId <= r_t2_htId;
r_t3_vld <= r_t2_vld;
r_t4_res <= r_t3_res;
r_t4_htId <= r_t3_htId;
r_t4_vld <= r_t3_vld;
r_t5_res <= r_t4_res;
r_t5_htId <= r_t4_htId;
r_t5_vld <= r_t4_vld;
r_t6_res <= r_t5_res;
r_t6_htId <= r_t5_htId;
r_t6_vld <= r_t5_vld;
end
// Inputs
assign c_t1_res = i_a + i_b;
assign c_t1_htId = i_htId;
assign c_t1_vld = i_vld;
// Outputs
assign o_res = r_t6_res;
assign o_htId = r_t6_htId;
assign o_vld = r_t6_vld;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: div.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: Provide an Integer divide capability to the Zip CPU. Provides
// for both signed and unsigned divide.
//
// Steps:
// i_reset The DIVide unit starts in idle. It can also be placed into an
// idle by asserting the reset input.
//
// i_wr When i_reset is asserted, a divide begins. On the next clock:
//
// o_busy is set high so everyone else knows we are at work and they can
// wait for us to complete.
//
// pre_sign is set to true if we need to do a signed divide. In this
// case, we take a clock cycle to turn the divide into an unsigned
// divide.
//
// o_quotient, a place to store our result, is initialized to all zeros.
//
// r_dividend is set to the numerator
//
// r_divisor is set to 2^31 * the denominator (shift left by 31, or add
// 31 zeros to the right of the number.
//
// pre_sign When true (clock cycle after i_wr), a clock cycle is used
// to take the absolute value of the various arguments (r_dividend
// and r_divisor), and to calculate what sign the output result
// should be.
//
//
// At this point, the divide is has started. The divide works by walking
// through every shift of the
//
// DIVIDEND over the
// DIVISOR
//
// If the DIVISOR is bigger than the dividend, the divisor is shifted
// right, and nothing is done to the output quotient.
//
// DIVIDEND
// DIVISOR
//
// This repeats, until DIVISOR is less than or equal to the divident, as in
//
// DIVIDEND
// DIVISOR
//
// At this point, if the DIVISOR is less than the dividend, the
// divisor is subtracted from the dividend, and the DIVISOR is again
// shifted to the right. Further, a '1' bit gets set in the output
// quotient.
//
// Once we've done this for 32 clocks, we've accumulated our answer into
// the output quotient, and we can proceed to the next step. If the
// result will be signed, the next step negates the quotient, otherwise
// it returns the result.
//
// On the clock when we are done, o_busy is set to false, and o_valid set
// to true. (It is a violation of the ZipCPU internal protocol for both
// busy and valid to ever be true on the same clock. It is also a
// violation for busy to be false with valid true thereafter.)
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2018, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
// `include "cpudefs.v"
//
module zipdiv(i_clk, i_reset, i_wr, i_signed, i_numerator, i_denominator,
o_busy, o_valid, o_err, o_quotient, o_flags);
parameter BW=32, LGBW = 5;
input wire i_clk, i_reset;
// Input parameters
input wire i_wr, i_signed;
input wire [(BW-1):0] i_numerator, i_denominator;
// Output parameters
output reg o_busy, o_valid, o_err;
output reg [(BW-1):0] o_quotient;
output wire [3:0] o_flags;
// r_busy is an internal busy register. It will clear one clock
// before we are valid, so it can't be o_busy ...
//
reg r_busy;
reg [(2*BW-2):0] r_divisor;
reg [(BW-1):0] r_dividend;
wire [(BW):0] diff; // , xdiff[(BW-1):0];
assign diff = r_dividend - r_divisor[(BW-1):0];
reg r_sign, pre_sign, r_z, r_c, last_bit;
reg [(LGBW-1):0] r_bit;
reg zero_divisor;
// The Divide logic begins with r_busy. We use r_busy to determine
// whether or not the divide is in progress, vs being complete.
// Here, we clear r_busy on any reset and set it on i_wr (the request
// do to a divide). The divide ends when we are on the last bit,
// or equivalently when we discover we are dividing by zero.
initial r_busy = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_busy <= 1'b0;
else if (i_wr)
r_busy <= 1'b1;
else if ((last_bit)||(zero_divisor))
r_busy <= 1'b0;
// o_busy is very similar to r_busy, save for some key differences.
// Primary among them is that o_busy needs to (possibly) be true
// for an extra clock after r_busy clears. This would be that extra
// clock where we negate the result (assuming a signed divide, and that
// the result is supposed to be negative.) Otherwise, the two are
// identical.
initial o_busy = 1'b0;
always @(posedge i_clk)
if (i_reset)
o_busy <= 1'b0;
else if (i_wr)
o_busy <= 1'b1;
else if (((last_bit)&&(!r_sign))||(zero_divisor))
o_busy <= 1'b0;
else if (!r_busy)
o_busy <= 1'b0;
// If we are asked to divide by zero, we need to halt. The sooner
// we halt and report the error, the better. Hence, here we look
// for a zero divisor while being busy. The always above us will then
// look at this and halt a divide in the middle if we are trying to
// divide by zero.
//
// Note that this works off of the 2BW-1 length vector. If we can
// simplify that, it should simplify our logic as well.
initial zero_divisor = 1'b0;
always @(posedge i_clk)
// zero_divisor <= (r_divisor == 0)&&(r_busy);
if (i_reset)
zero_divisor <= 1'b0;
else if (i_wr)
zero_divisor <= (i_denominator == 0);
else if (!r_busy)
zero_divisor <= 1'b0;
// o_valid is part of the ZipCPU protocol. It will be set to true
// anytime our answer is valid and may be used by the calling module.
// Indeed, the ZipCPU will halt (and ignore us) once the i_wr has been
// set until o_valid gets set.
//
// Here, we clear o_valid on a reset, and any time we are on the last
// bit while busy (provided the sign is zero, or we are dividing by
// zero). Since o_valid is self-clearing, we don't need to clear
// it on an i_wr signal.
initial o_valid = 1'b0;
always @(posedge i_clk)
if (i_reset)
o_valid <= 1'b0;
else if (r_busy)
begin
if ((last_bit)||(zero_divisor))
o_valid <= (zero_divisor)||(!r_sign);
end else if (r_sign)
begin
o_valid <= (!zero_divisor); // 1'b1;
end else
o_valid <= 1'b0;
// Division by zero error reporting. Anytime we detect a zero divisor,
// we set our output error, and then hold it until we are valid and
// everything clears.
initial o_err = 1'b0;
always @(posedge i_clk)
if (i_reset)
o_err <= 1'b0;
else if (o_valid)
o_err <= 1'b0;
else if (((r_busy)||(r_sign))&&(zero_divisor))
o_err <= 1'b1;
else
o_err <= 1'b0;
// r_bit
//
// Keep track of which "bit" of our divide we are on. This number
// ranges from 31 down to zero. On any write, we set ourselves to
// 5'h1f. Otherwise, while we are busy (but not within the pre-sign
// adjustment stage), we subtract one from our value on every clock.
initial r_bit = 0;
always @(posedge i_clk)
if (i_reset)
r_bit <= 0;
else if ((r_busy)&&(!pre_sign))
r_bit <= r_bit + 1'b1;
else
r_bit <= 0;
// last_bit
//
// This logic replaces a lot of logic that was inside our giant state
// machine with ... something simpler. In particular, we'll use this
// logic to determine we are processing our last bit. The only trick
// is, this bit needs to be set whenever (r_busy) and (r_bit == 0),
// hence we need to set on (r_busy) and (r_bit == 1) so as to be set
// when (r_bit == 0).
initial last_bit = 1'b0;
always @(posedge i_clk)
if (i_reset)
last_bit <= 1'b0;
else if (r_busy)
last_bit <= (r_bit == {(LGBW){1'b1}}-1'b1);
else
last_bit <= 1'b0;
// pre_sign
//
// This is part of the state machine. pre_sign indicates that we need
// a extra clock to take the absolute value of our inputs. It need only
// be true for the one clock, and then it must clear itself.
initial pre_sign = 1'b0;
always @(posedge i_clk)
if (i_reset)
pre_sign <= 1'b0;
else if (i_wr)
pre_sign <= (i_signed)&&((i_numerator[BW-1])||(i_denominator[BW-1]));
else
pre_sign <= 1'b0;
// As a result of our operation, we need to set the flags. The most
// difficult of these is the "Z" flag indicating that the result is
// zero. Here, we'll use the same logic that sets the low-order
// bit to clear our zero flag, and leave the zero flag set in all
// other cases. Well ... not quite. If we need to flip the sign of
// our value, then we can't quite clear the zero flag ... yet.
initial r_z = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_z <= 1'b0;
else if((r_busy)&&(r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW]))
// If we are busy, the upper bits of our divisor are
// zero (i.e., we got the shift right), and the top
// (carry) bit of the difference is zero (no overflow),
// then we could subtract our divisor from our dividend
// and hence we add a '1' to the quotient, while setting
// the zero flag to false.
r_z <= 1'b0;
else if (i_wr)
r_z <= 1'b1;
// r_dividend
// This is initially the numerator. On a signed divide, it then becomes
// the absolute value of the numerator. We'll subtract from this value
// the divisor shifted as appropriate for every output bit we are
// looking for--just as with traditional long division.
initial r_dividend = 0;
always @(posedge i_clk)
if (i_reset)
r_dividend <= 0;
else if (pre_sign)
begin
// If we are doing a signed divide, then take the
// absolute value of the dividend
if (r_dividend[BW-1])
r_dividend <= -r_dividend;
// The begin/end block is important so we don't lose
// the fact that on an else we don't do anything.
end else if((r_busy)&&(r_divisor[(2*BW-2):(BW)]==0)&&(!diff[BW]))
// This is the condition whereby we set a '1' in our
// output quotient, and we subtract the (current)
// divisor from our dividend. (The difference is
// already kept in the diff vector above.)
r_dividend <= diff[(BW-1):0];
else if (!r_busy)
// Once we are done, and r_busy is no longer high, we'll
// always accept new values into our dividend. This
// guarantees that, when i_wr is set, the new value
// is already set as desired.
r_dividend <= i_numerator;
initial r_divisor = 0;
always @(posedge i_clk)
if (i_reset)
r_divisor <= 0;
else if (pre_sign)
begin
if (r_divisor[(2*BW-2)])
r_divisor[(2*BW-2):(BW-1)]
<= -r_divisor[(2*BW-2):(BW-1)];
end else if (r_busy)
r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
else
r_divisor <= { i_denominator, {(BW-1){1'b0}} };
// r_sign
// is a flag for our state machine control(s). r_sign will be set to
// true any time we are doing a signed divide and the result must be
// negative. In that case, we take a final logic stage at the end of
// the divide to negate the output. This flag is what tells us we need
// to do that. r_busy will be true during the divide, then when r_busy
// goes low, r_sign will be checked, then the idle/reset stage will have
// been reached. For this reason, we cannot set r_sign unless we are
// up to something.
initial r_sign = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_sign <= 1'b0;
else if (pre_sign)
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));
else if (r_busy)
r_sign <= (r_sign)&&(!zero_divisor);
else
r_sign <= 1'b0;
initial o_quotient = 0;
always @(posedge i_clk)
if (i_reset)
o_quotient <= 0;
else if (r_busy)
begin
o_quotient <= { o_quotient[(BW-2):0], 1'b0 };
if ((r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW]))
o_quotient[0] <= 1'b1;
end else if (r_sign)
o_quotient <= -o_quotient;
else
o_quotient <= 0;
// Set Carry on an exact divide
// Perhaps nothing uses this, but ... well, I suppose we could remove
// this logic eventually, just ... not yet.
initial r_c = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_c <= 1'b0;
else
r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
// The last flag: Negative. This flag is set assuming that the result
// of the divide was negative (i.e., the high order bit is set). This
// will also be true of an unsigned divide--if the high order bit is
// ever set upon completion. Indeed, you might argue that there's no
// logic involved.
wire w_n;
assign w_n = o_quotient[(BW-1)];
assign o_flags = { 1'b0, w_n, r_c, r_z };
`ifdef FORMAL
reg f_past_valid;
initial f_past_valid = 0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
`ifdef DIV
`define ASSUME assume
`else
`define ASSUME assert
`endif
initial `ASSUME(i_reset);
always @(*)
if (!f_past_valid)
`ASSUME(i_reset);
always @(posedge i_clk)
if ((!f_past_valid)||($past(i_reset)))
begin
assert(!o_busy);
assert(!o_valid);
assert(!o_err);
//
assert(!r_busy);
assert(!zero_divisor);
assert(r_bit==0);
assert(!last_bit);
assert(!pre_sign);
assert(!r_z);
assert(r_dividend==0);
assert(o_quotient==0);
assert(!r_c);
assert(r_divisor==0);
`ASSUME(!i_wr);
end
always @(*)
if (o_busy)
`ASSUME(!i_wr);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(o_busy))&&(!o_busy))
begin
assert(o_valid);
end
// A formal methods section
//
// This section isn't yet complete. For now, it is just
// a description of things I think should be in here ... not
// yet a description of what it would take to prove
// this divide (yet).
always @(*)
if (o_err)
assert(o_valid);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_wr)))
assert(!pre_sign);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr))&&($past(i_signed))
&&(|$past({i_numerator[BW-1],i_denominator[BW-1]})))
assert(pre_sign);
// always @(posedge i_clk)
// if ((f_past_valid)&&(!$past(pre_sign)))
// assert(!r_sign);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr)))
assert(o_busy);
always @(posedge i_clk)
if ((f_past_valid)&&($past(o_valid)))
assert(!o_valid);
always @(*)
if ((o_valid)&&(!o_err))
assert(r_z == ((o_quotient == 0)? 1'b1:1'b0));
always @(*)
if ((o_valid)&&(!o_err))
assert(w_n == o_quotient[BW-1]);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(r_busy))&&(!$past(i_wr)))
assert(!o_busy);
always @(posedge i_clk)
assert((!o_busy)||(!o_valid));
always @(posedge i_clk)
if(o_busy) `ASSUME(!i_wr);
always @(*)
if(r_busy) assert(o_busy);
reg [BW:0] f_bits_set;
always @(posedge i_clk)
if (i_reset)
f_bits_set <= 0;
else if (i_wr)
f_bits_set <= 0;
else if ((r_busy)&&(!pre_sign))
f_bits_set <= { f_bits_set[BW-1:0], 1'b1 };
always @(*)
if ((o_valid)&&(!o_err))
assert((!f_bits_set[BW])&&(&f_bits_set[BW-1:0]));
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(r_busy))
&&($past(r_divisor[2*BW-2:BW])==0))
begin
if ($past(r_divisor) == 0)
assert(o_err);
else if ($past(pre_sign))
begin
if ($past(r_dividend[BW-1]))
assert(r_dividend == -$past(r_dividend));
if ($past(r_divisor[(2*BW-2)]))
begin
assert(r_divisor[(2*BW-2):(BW-1)]
== -$past(r_divisor[(2*BW-2):(BW-1)]));
assert(r_divisor[BW-2:0] == 0);
end
end else begin
if (o_quotient[0])
assert(r_dividend == $past(diff));
else
assert(r_dividend == $past(r_dividend));
// r_divisor should shift down on every step
assert(r_divisor[2*BW-2]==0);
assert(r_divisor[2*BW-3:0]==$past(r_divisor[2*BW-2:1]));
end
if ($past(r_dividend) >= $past(r_divisor[BW-1:0]))
assert(o_quotient[0]);
else
assert(!o_quotient[0]);
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_TB_V
`define SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_TB_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_mux_2to1_n.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_hdll__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_TB_V
|
`timescale 1ns / 1ps
`include "cache_defines.vh"
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:33:56 03/01/2015
// Design Name:
// Module Name: cache
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cache(
data_out, data_out_miss, tag_out_miss, hit_miss_out,
vector_in, clk, enable
);
// parameters for the module
parameter TAG_WIDTH = 16; // width of the tag
parameter DATA_WIDTH = 32; // width of the data
parameter ENTRIES_WIDTH = 128; // # of entries
parameter OPCODE_WIDTH = 2; // width of opcode
parameter LINE_WIDTH = TAG_WIDTH+DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
parameter ENTRIES_BIT_WIDTH = `LOG2(ENTRIES_WIDTH); // length of the input vector
// outputs of the module
output reg [DATA_WIDTH-1:0]data_out;// final output of the block
output reg [DATA_WIDTH-1:0]data_out_miss;// final output of the block
output reg [TAG_WIDTH-1:0]tag_out_miss; // tag bits miss in the write task
output reg hit_miss_out; // outputs the hit/miss of the block
// inputs of the module
input [LINE_WIDTH-1:0]vector_in; // input vector
input clk; // input clk
input enable; // input enable
// the final cache block vector array
reg [DATA_WIDTH-1:0]cache_block[ENTRIES_WIDTH-1:0];
// cache tag entries
reg [TAG_WIDTH-1:0]tag_entries[ENTRIES_WIDTH-1:0];
// cache valid bit entries
reg [ENTRIES_WIDTH-1:0]tag_valid_invalid_bit;
// local module variables
reg [OPCODE_WIDTH-1:0]control_in; // control bits for the module obtained from the input vector
reg [TAG_WIDTH-1:0]tag_in; // tag bits for the module obtained from the input vector
reg [DATA_WIDTH-1:0]data_in; // data bits for the module obtained from the input vector
reg [DATA_WIDTH-1:0]temp_data_out; // data bits for the module obtained from the input vector
reg hit_entry; // internal hit/miss entry used between tasks
reg [ENTRIES_BIT_WIDTH:0]mru_entry; // tag bits for replacement policy
// count variable
reg [ENTRIES_BIT_WIDTH:0]for_cnt_entries; // general variable for the FOR loop
// initialize the variables
initial
begin
// initializing the outputs
data_out = {DATA_WIDTH-1{1'b0}};
temp_data_out = {DATA_WIDTH-1{1'b0}};
data_out_miss = {DATA_WIDTH-1{1'b0}};
tag_out_miss = {TAG_WIDTH-1{1'b0}};
// hit_miss_out = 1'b0;
control_in = {OPCODE_WIDTH-1{1'b0}};
tag_in = {TAG_WIDTH-1{1'b0}};
data_in = {DATA_WIDTH{1'b0}};
for_cnt_entries = {ENTRIES_BIT_WIDTH{1'b0}};
mru_entry = {ENTRIES_WIDTH-1{1'b0}};
// initializing the various required regs
for(for_cnt_entries = {ENTRIES_WIDTH-1{1'b0}}; for_cnt_entries < ENTRIES_WIDTH; for_cnt_entries = for_cnt_entries + 1)
begin
// tag_entries[for_cnt_entries]={TAG_WIDTH-1{1'b0}};
cache_block[for_cnt_entries]={DATA_WIDTH-1{1'b0}};
tag_valid_invalid_bit[for_cnt_entries]=1'b0;
end
$display("TAG:%d, DATA:%d, ENTRIES:%d, LINE: %d",TAG_WIDTH,DATA_WIDTH,ENTRIES_WIDTH,LINE_WIDTH);
end
// task for reading the cache entries
task cache_read_task;
output [DATA_WIDTH-1:0]data_task_out;
output hit_miss;
output [ENTRIES_BIT_WIDTH:0]hit_cache_entry;
input [TAG_WIDTH-1:0]tag_check;
// loop variable
reg [ENTRIES_BIT_WIDTH:0]entries_count;
begin: label_cache_read
entries_count = {ENTRIES_WIDTH-1{1'b0}};
data_task_out = {DATA_WIDTH-1{1'b0}};
hit_miss = `MISS;
hit_cache_entry = {ENTRIES_BIT_WIDTH{1'b0}};
// loop for going through the cache tag entries
repeat(ENTRIES_WIDTH)
begin
$display("entries_count:%d, tag_entries:%d, tag_check:%d",entries_count,tag_entries[entries_count],tag_check);
// check tag entry first
if(tag_entries[entries_count] == tag_check)
begin
// tag match, check the line validity/invalidity
$display("READ TASK, tag_valid_invalid_bit:%d",tag_valid_invalid_bit[entries_count]);
if(tag_valid_invalid_bit[entries_count] == `TAG_ENTRY_VALID)
begin
// line valid, give out the data, the cache entry, generate a hit and disable the loop
data_task_out = cache_block[entries_count];
mru_entry = entries_count;
hit_cache_entry = entries_count;
hit_miss = `HIT;
$display("DISABLED READ REPEAT, valid hit_cache_entry:%d",hit_cache_entry);
disable label_cache_read;
end else
begin
// line invalid, generate a hit and disable the loop
// data_task_out = cache_block[entries_count];
mru_entry = entries_count;
hit_cache_entry = entries_count;
hit_miss = `HIT;
$display("DISABLED READ REPEAT, invalid hit_cache_entry:%d",hit_cache_entry);
disable label_cache_read;
end
end // tag not present
entries_count = entries_count + 1;
end
end
endtask
// task for searching available cache entry
task cache_search_task;
output [DATA_WIDTH-1:0]data_task_out;
output hit_miss;
output [ENTRIES_BIT_WIDTH:0]hit_cache_entry;
input [TAG_WIDTH-1:0]tag_check;
// loop variable
reg [ENTRIES_BIT_WIDTH:0]entries_count;
begin: label_cache_read
entries_count = {ENTRIES_WIDTH-1{1'b0}};
data_task_out = {DATA_WIDTH-1{1'b0}};
hit_miss = 1'b0;
hit_cache_entry = {ENTRIES_BIT_WIDTH{1'b0}};
// loop for going through the cache tag entries
repeat(ENTRIES_WIDTH)
begin
$display("entries_count:%d, tag_entries:%d, tag_check:%d",entries_count,tag_entries[entries_count],tag_check);
// check the line validity/invalidity
if(tag_valid_invalid_bit[entries_count] == tag_check)
begin
// line invalid, give out the data, the cache entry, generate a hit and disable the loop
// data_task_out = cache_block[entries_count];
mru_entry = entries_count;
hit_cache_entry = entries_count;
hit_miss = `HIT;
$display("DISABLED READ REPEAT, hit_cache_entry:%d",hit_cache_entry);
disable label_cache_read;
end else
begin
// line invalid, generate a hit and disable the loop
// data_task_out = cache_block[entries_count];
if(entries_count > ENTRIES_WIDTH)
begin
hit_cache_entry = entries_count;
hit_miss = `MISS;
// $display("DISABLED READ REPEAT, hit_cache_entry:%d",hit_cache_entry);
// disable label_cache_read;
end
end
entries_count = entries_count + 1;
end
end
endtask
// task for writing a cache entry
task cache_write_task;
output [DATA_WIDTH-1:0]data_task_out;
output [DATA_WIDTH-1:0]data_miss_out;
output [TAG_WIDTH-1:0]tag_miss_out;
output hit_miss;
output [ENTRIES_BIT_WIDTH:0]hit_cache_entry;
input [TAG_WIDTH-1:0]tag_check;
input [ENTRIES_WIDTH-1:0]tag_replacement_entry;
input [DATA_WIDTH-1:0]data_task_in;
begin
data_miss_out = {DATA_WIDTH-1{1'b0}};
tag_miss_out = {TAG_WIDTH-1{1'b0}};
hit_miss = 1'b0;
hit_cache_entry = {ENTRIES_BIT_WIDTH{1'b0}};
// check the cache for the validity of the tag to be written
cache_read_task(data_task_out,hit_miss,hit_cache_entry,tag_check);
if(hit_miss == `HIT)
begin
// HIT: cache entry available, data overwritten in the cache entry
$display("Cache Read HIT, hit_miss:%d, hit_cache_entry:%d, tag_check:%d, data_task_in:%d",hit_miss, hit_cache_entry, tag_check, data_task_in);
// tag_valid_invalid_bit[hit_cache_entry] = `TAG_ENTRY_VALID;
cache_block[hit_cache_entry] = data_task_in;
end else
begin
// MISS: cache entry not-available, find the next available location
// tag_miss_out = tag_entries[mru_entry];
// data_miss_out = cache_block[mru_entry];
$display("Cache Read MISS");
cache_search_task(data_task_out,hit_miss,hit_cache_entry,`TAG_ENTRY_INVALID);
if(hit_miss == `HIT)
begin
// HIT: cache has an availalbe entry, use that location for storing new data
$display("Cache Search HIT, hit_miss:%d, hit_cache_entry:%d, tag_check:%d, data_task_in:%d",hit_miss, hit_cache_entry, tag_check, data_task_in);
tag_valid_invalid_bit[hit_cache_entry] = `TAG_ENTRY_VALID;
tag_entries[hit_cache_entry] = tag_check;
cache_block[hit_cache_entry] = data_task_in;
end else
begin
// MISS: cache full, DO SOMETHING BETTER THAN THIS
// currently filling a single location of the cache
$display("Cache Full MISS, hit_miss:%d, hit_cache_entry:%d, tag_replacement_entry:%d, data_task_in:%d",hit_miss, hit_cache_entry, tag_replacement_entry, data_task_in);
tag_valid_invalid_bit[tag_replacement_entry] = `TAG_ENTRY_VALID;
tag_entries[tag_replacement_entry] = tag_check;
cache_block[tag_replacement_entry] = data_task_in;
end
end
tag_miss_out = tag_entries[mru_entry];
data_miss_out = cache_block[mru_entry];
data_task_out = {DATA_WIDTH-1{1'b0}};
$display("Cache out, tag_miss_out:%d, data_miss_out:%d", tag_miss_out, data_miss_out);
end
endtask
always @(posedge clk)
begin
if(enable == `CACHE_ENABLE)begin
control_in = vector_in[LINE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH];
tag_in = vector_in[LINE_WIDTH-OPCODE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH-TAG_WIDTH];
data_in = vector_in[LINE_WIDTH-OPCODE_WIDTH-TAG_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH-TAG_WIDTH-DATA_WIDTH];
$display("control: %d,tag_in: %d,data_in: %d",control_in, tag_in, data_in);
case(control_in)
`FLASH:
begin
$display("FLASH");
for(for_cnt_entries = {ENTRIES_WIDTH-1{1'b0}}; for_cnt_entries < ENTRIES_WIDTH; for_cnt_entries = for_cnt_entries + 1)
begin
tag_entries[for_cnt_entries]={TAG_WIDTH-1{1'b0}};
tag_valid_invalid_bit[for_cnt_entries]=`TAG_ENTRY_INVALID;
end
end
`READ:
begin
$display("CACHE READ");
cache_read_task(data_out,hit_miss_out,hit_entry,tag_in);
$display("READ DATA %d", data_out);
end
`WRITE:
begin
$display("WRITE DATA %d", data_in);
cache_write_task(data_out,data_out_miss,tag_out_miss,hit_miss_out,hit_entry,tag_in,mru_entry,data_in);
$display("CACHE WRITE");
end
`INVALID: $display("INVLAID");
default: $display("WRONG VALUE");
endcase
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_en,
src_dac_ddata,
src_dac_dunf,
src_dac_dvalid,
dst_dac_en,
dst_dac_ddata,
dst_dac_dunf,
dst_dac_dvalid
);
parameter CHANNEL_ID = 0;
parameter DATA_WIDTH = 32;
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_en;
input [(DATA_WIDTH-1):0] src_dac_ddata;
input src_dac_dunf;
input src_dac_dvalid;
input dst_dac_en;
output [(DATA_WIDTH-1):0] dst_dac_ddata;
output dst_dac_dunf;
output dst_dac_dvalid;
// output register to improve timing
reg dst_dac_dunf = 'h0;
reg [(DATA_WIDTH-1):0] dst_dac_ddata = 'h0;
reg dst_dac_dvalid = 'h0;
reg src_dac_en = 'h0;
// internal registers
reg [ 7:0] pn_data = 'hF2;
reg [31:0] status = 'h0;
reg [ 3:0] mode = 'h0;
// internal wires
wire [(SYMBOL_WIDTH-1):0] mod_data;
wire [15:0] dac_data_fltr_i;
wire [15:0] dac_data_fltr_q;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[7] ^ din[4];
dout[0] = din[6] ^ din[3];
pn = dout;
end
endfunction
// update control and status registers
always @(posedge clk) begin
status <= { 24'h0, RP_ID };
mode <= control[ 7:4];
end
// prbs generation
always @(posedge clk) begin
if(dst_dac_en == 1) begin
pn_data <= pn(pn_data);
end
end
// data for the modulator (prbs or dma)
assign mod_data = (mode == 1) ? pn_data[ 1:0] : src_dac_ddata[ 1:0];
// qpsk modulator
qpsk_mod i_qpsk_mod (
.clk(clk),
.data_input(mod_data),
.data_valid(dst_dac_en),
.data_qpsk_i(dac_data_fltr_i),
.data_qpsk_q(dac_data_fltr_q)
);
// output logic
always @(posedge clk) begin
src_dac_en <= dst_dac_en;
dst_dac_dvalid <= src_dac_dvalid;
case(mode)
4'h0 : begin
dst_dac_ddata <= src_dac_ddata;
dst_dac_dunf <= src_dac_dunf;
end
4'h1 : begin
dst_dac_ddata <= { dac_data_fltr_q, dac_data_fltr_i };
dst_dac_dunf <= 1'h0;
end
4'h2 : begin
dst_dac_ddata <= { dac_data_fltr_q, dac_data_fltr_i };
dst_dac_dunf <= src_dac_dunf;
end
default : begin
end
endcase
end
endmodule
|
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